MC33GD3000EPR2

MC33GD3000 Three phase field effect transistor predriver Rev. 10.0 — 16 March 2022 1 Product data sheet General description The 33GD3000 is a field effect transistor (FET) predriver designed for three phase motor control and similar applications. It meets the stringent requirements of automotive applications and is fully AEC-Q100 grade 1 qualified. The IC contains three high-side FET predrivers and three low-side FET predrivers. Three external bootstrap capacitors provide gate charge to the high-side FETs. The IC interfaces to a MCU via six direct input control signals, an SPI port for device setup and asynchronous reset, enable and interrupt signals. Both 5.0 and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are provided. The integrated circuit (IC) uses SMARTMOS technology. 2 Features and benefits • • • • • • • 3 Extended operating range from 6.0 V to 60 V covers 12 V and 48 V systems Gate drive capability of 1.0 A to 2.5 A Fully specified from 8.0 V to 40 V, covers 12 and 24 V automotive systems Device protection against reverse charge-injection from CGD and CGS of external FETs Dead time is programmable via the SPI port Simultaneous output capability enabled via safe SPI command AEC-Q100 grade 1 qualified Applications Automotive systems: • • • • • • • • • • Cooling fan Water pump Actuator controls Fuel pump Electro-hydraulic and electric power steering Engine and transmission control Motor control Braking pump Belt starter generator Turbo pump MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 4 Ordering information Table 1. Ordering information Type number Package Name MC33GD3000EP 5 Description Version HVQFN56 Plastic, thermal enhanced very thin quad flatpack; no leads; 56 terminals; 0.5 mm pitch; 8 mm x 8 mm x 0.9 mm body SOT684-17 Block diagram PUMP VPUMP VPWR VSUP MAIN CHARGE PUMP PGND TRICKLE CHARGE PUMP 5.0 V REG. VDD HOLD -OFF CIRCUIT VLS REG. VLS OSCILLATOR VDD UV DETECT 3x PX_BOOT RST T-LIM INT HIGHSIDE DRIVER VSUP EN1 EN2 PX_HS 3 PX_LS 3 CONTROL LOGIC DESAT. COMP. PX_HS_G 1.4 V PX_HS_S CS SI VSUP SCLK SO PHASEX PHASE COMP. 3 LOWSIDE DRIVER OC_OUT GND(2) PX_LS_G PX_LS_S OVERCUR. COMP. VSS I-SENSE AMP. OC_TH AMP_OUT AMP_N AMP_P VLS_CAP aaa-038791 Figure 1. Internal block diagram MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 2 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 6 Pinning information 6.1 Pinning Figure 2. Pinout diagram 6.2 Pin description Table 2. Pin definitions Symbol Pin Type Description Comments PA_BOOT 1 Analog input Phase A bootstrap Bootstrap capacitor for Phase A NC 2, 3, 5, 7, 13, 17, 41, 42 No connect VLS 4 Analog output VLS regulator VLS regulator output; power supply for the gate drives VPWR 6 Power input Voltage power Power supply input for gate drives PHASEA 8 Digital output Phase A Totem pole output of Phase A comparator; this output is low when the voltage on PA_HS_S (source of high-side FET) is less than 50 % of VSUP PGND 9 Ground Power ground Power ground for charge pump EN1 10 Digital input Enable 1 Logic signal input must be high (ANDed with EN2) to enable any gate drive output. EN2 11 Digital input Enable 2 Logic signal input must be high (ANDed with EN1) to enable any gate drive output MC33GD3000 Product data sheet No connection All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 3 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 2. Pin definitions...continued Symbol Pin Type Description Comments RST_B 12 Digital input Reset Reset input PUMP 14 Power drive out Pump Charge pump output VPUMP 15 Power input Voltage pump Charge pump supply VSUP 16 Analog input Supply voltage Supply voltage to the load. This pin is to be connected to the common drains of the external high-side FETs PHASEB 18 Digital output Phase B Totem pole output of Phase B comparator. This output is low when the voltage on PB_HS_S (source of high-side FET) is less than 50 % of VSUP PHASEC 19 Digital output Phase C Totem pole output of Phase C comparator. This output is low when the voltage on PC_HS_S (source of high-side FET) is less than 50 % of VSUP PA_HS_B 20 Digital input Phase A high-side Active low input logic signal enables the high-side driver for Phase A PA_LS 21 Digital input Phase A low-side Active high input logic signal enables the low-side driver for Phase A VDD 22 Analog output VDD regulator VDD regulator output capacitor connection PB_HS_B 23 Digital input Phase B high-side Active low input logic signal enables the high-side driver for Phase B PB_LS 24 Digital input Phase B low-side Active high input logic signal enables the low-side driver for Phase B INT 25 Digital output Interrupt Interrupt pin output CS_B 26 Digital input Chip select Chip select input. It frames SPI commands and enables SPI port. SI 27 Digital input Serial in Input data for SPI port. Clocked on the falling edge of SCLK, MSB first SCLK 28 Digital input Serial clock Clock for SPI port and typically is 3.0 MHz SO 29 Digital output Serial out Output data for SPI port. Tri-state until CS becomes low. PC_LS 30 Digital input Phase C low-side Active high input logic signal enables the low-side driver for Phase C PC_HS_B 31 Digital input Phase C high-side Active low input logic signal enables the high-side driver for Phase C AMP_OUT 32 Analog output Amplifier output Output of the current-sensing amplifier AMP_N 33 Analog input Amplifier invert Inverting input of the current-sensing amplifier AMP_P 34 Analog input Amplifier noninvert noninverting input of the current-sensing amplifier OC_OUT 35 Digital output Overcurrent out Totem pole digital output of the overcurrent comparator OC_TH 36 Analog input Overcurrent threshold Threshold of the overcurrent detector VSS 37 Ground Voltage source supply Ground reference for logic interface and power supplies GND 38, 39 Ground Ground Substrate and ESD reference, connect to VSS VLS_CAP 40 Analog output VLS regulator output capacitor VLS regulator connection for additional output capacitor, providing low impedance supply source for low-side gate drive PC_LS_S 43 Power input Phase C low-side source Source connection for Phase C low-side FET PC_LS_G 44 Power output Phase C low-side gate drive Gate drive output for Phase C low side PC_HS_S 45 Power input Source connection for Phase C high-side FET PC_HS_G 46 Power output Phase C high-side gate drive MC33GD3000 Product data sheet Phase C high-side source Gate drive for output Phase C high-side FET All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 4 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 2. Pin definitions...continued Symbol Pin Type Description Comments PC_BOOT 47 Analog input Phase C bootstrap Bootstrap capacitor for Phase C PB_LS_S 48 Power input Phase B low-side source Source connection for Phase B low-side FET PB_LS_G 49 Power output Phase B low-side gate drive Gate drive for output Phase B low side PB_HS_S 50 Power input Source connection for Phase B high-side FET PB_HS_G 51 Power output Phase B high-side gate drive Gate drive for output Phase B high side PB_BOOT 52 Analog input Phase B bootstrap Bootstrap capacitor for Phase B PA_LS_S 53 Power input Phase A low-side source Source connection for Phase A low-side FET PA_LS_G 54 Power output Phase A low-side gate drive Gate drive for output Phase A low side PA_HS_S 55 Power input Source connection for Phase A high-side FET PA_HS_G 56 Power output Phase A high-side gate drive Gate drive for output Phase A high side Ground Device performs as specified with the exposed pad unterminated (floating) however, it is recommended the exposed pad be terminated to pin 29 (VSS) and system ground EP 7 Phase B high-side source Phase A high-side source Exposed pad Functional descriptions 7.1 Introduction The 33GD3000 provides an interface between an MCU and the large FETs used to drive three phase loads. A typical load FET may have an on resistance of 4.0 mΩ or less and could require a gate charge of over 400 nC to fully turn on. The IC can operate in automotive 12 to 42 V environments. Because there are so many methods of controlling three phase systems, the IC enforces few constraints on driving the FETs. The IC does provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both FETs in a phase are not simultaneously enabled. A SPI port is used to configure the IC modes. 7.2 Functional pin description 7.2.1 Phase A (PHASEA) This pin is the totem pole output of the Phase A comparator. This output is low when the voltage on Phase A high-side source (source of the high-side load FET) is less than 50 % of VSUP. 7.2.2 Power ground (PGND) This pin is power ground for the charge pump. It should be connected to VSS, however routing to a single point ground on the PCB may help to isolate charge pump noise. 7.2.3 Enable 1 and enable 2 (EN1, EN2) Both of these logic signal inputs must be high to enable any gate drive output. When either or both are low, the internal logic (SPI port, etc.) still functions normally, but all gate drives are forced off (external power FET gates pulled low). The signal is asynchronous. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 5 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver When EN1 and EN2 return high to enable the outputs, each LS driver must be pulsed ON before the corresponding HS driver can be commanded ON. This ensures that the bootstrap capacitors are charged. See Section 11.3 "Initialization requirements". 7.2.4 Reset (RST) When the reset pin is low the integrated circuit (IC) is in a low power state. In this mode, all outputs are disabled, internal bias circuits are turned off, and a small pull-down current is applied to the output gate drives. The internal logic will be reset within 77 ns of RESET going low. When RST is low, the IC consumes minimal current. 7.2.5 Charge pump out (PUMP) This pin is the switching node of the charge pump circuit. The output of the internal charge pump support circuit. When the charge pump is used, it is connected to the external pumping capacitor. This pin may be left floating if the charge pump is not required. 7.2.6 Charge pump input (VPUMP) This pin is the input supply for the charge pump circuit. When the charge pump is required, this pin should be connected to a polarity protected supply. This input should never be connected to a supply greater than 40 V. If the charge pump is not required this pin may be left floating. 7.2.7 VSUP input (VSUP) The supply voltage pin should be connected to the common connection of the high-side FETs. It is the reference bias for the Phase Comparators and Desaturation Comparator. It is also used to provide power to the internal steady state trickle charge pump and to energize the hold off circuit. 7.2.8 Phase B (PHASEB) This pin is the totem pole output of the Phase B comparator. This output is low when the voltage on Phase B high-side source (source of the high-side load FET) is less than 50 % of VSUP. 7.2.9 Phase C (PHASEC) This pin is the totem pole output of the Phase C comparator. This output is low when the voltage on Phase C high-side source (source of the high-side load FET) is less than 50 % of VSUP. 7.2.10 Phase A high-side input (PA_HS) This input logic signal pin enables the high-side driver for Phase A. The signal is active low, and is pulled up by an internal current source. 7.2.11 Phase A low-side input (PA_LS) This input logic signal pin enables the low-side driver for Phase A. The signal is active high, and is pulled down by an internal current sink. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 6 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 7.2.12 VDD Voltage Regulator (VDD) VDD is an internally generated 5.0 V supply. The internal regulator provides continuous power to the IC and is a supply reference for the SPI port. A 0.47 µF (min) decoupling capacitor must be connected to this pin. This regulator is intended for internal IC use and can supply only a small (1.0 mA) external load current. A power-on-reset (POR) circuit monitors this pin and until the voltage rises above the threshold, the internal logic will be reset; driver outputs are tri-stated and SPI communication is disabled. The VDD regulator can be disabled by asserting the RST signal low. The VDD regulator is powered from the VPWR pin. 7.2.13 Phase B high-side control input (PB_HS) This pin is the input logic signal, enabling the high-side driver for Phase B. The signal is active low, and is pulled up by an internal current source. 7.2.14 Phase B low-side input (PB_LS) This pin is the input logic signal, enabling the low-side driver for Phase B. The signal is active high, and is pulled down by an internal current sink. 7.2.15 Interrupt (INT) The Interrupt pin is a totem pole logic output. When a fault is detected, this pin pulls high until it is cleared by executing the Clear Interrupt command via the SPI port. The faults capable of causing an interrupt can be masked via the MASK0 and MASK1 SPI registers to customize the response. 7.2.16 Chip select (CS) Chip select is a logic input that frames the SPI commands and enables the SPI port. This signal is active low, and is pulled up by an internal current source. 7.2.17 Serial in (SI) The Serial In pin is used to input data to the SPI port. Clocked on the falling edge of SCLK, it is the most significant bit (MSB) first. This pin is pulled down by an internal current sink. 7.2.18 Serial clock (SCLK) This logic input is the clock is used for the SPI port. The SCLK typically runs at 3.0 MHz (up to 5.0 MHz) and is pulled down by an internal current sink. 7.2.19 Serial out (SO) Output data for the SPI port streams from this pin. It is tri-stated until CS is low. New data appears on rising edges of SCLK in preparation for latching by the falling edge of SCLK on the master. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 7 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 7.2.20 Phase C low-side input (PC_LS) This input logic pin enables the low-side driver for Phase C. This pin is an active high, and is pulled down by an internal current sink. 7.2.21 Phase C high-side input (PC_HS) This input logic pin enables the high-side driver for Phase C. This signal is active low, and is pulled up by an internal current source. 7.2.22 Amplifier output (AMP_OUT) This pin is the output for the current sensing amplifier. It is also the sense input to the overcurrent comparator. 7.2.23 Amplifier inverting input (AMP_N) The inverting input to the current sensing amplifier. 7.2.24 Amplifier noninverting input (AMP_P) The noninverting input to the current sensing amplifier. 7.2.25 Overcurrent comparator output (OC_OUT) The overcurrent comparator output is a totem pole logic level output. A logic high indicates an overcurrent condition. 7.2.26 Overcurrent comparator threshold (OC_TH) This input sets the threshold level of the overcurrent comparator. 7.2.27 Voltage source supply (VSS) VSS is the ground reference for the logic interface and power supplies. 7.2.28 Ground (GND0, GND1) These two pins are connected internally to VSS by a 1.0 Ω resistor. They provide device substrate connections and also the primary return path for ESD protection. 7.2.29 VLS regulator capacitor (VLS_CAP) This connection is for a capacitor which provides a low-impedance for switching currents on the gate drive. A low ESR decoupling capacitor, capable of sourcing the pulsed drive currents must be connected between this pin and VSS. This is the same DC node as VLS, but it is physically placed on the opposite end of the IC to minimize the source impedance to the gate drive circuits. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 8 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 7.2.30 Phase C low-side source (PC_LS_S) The phase C low-side source is the pin used to return the gate currents from the low-side FET. Best performance is realized by connecting this node directly to the source of the low-side FET for phase C. 7.2.31 Phase C low-side gate (PC_LS_G) This is the gate drive for the Phase C low-side output FET. It provides high-current through a low-impedance to turn on and off the low-side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has also been designed to resist the influence of negative currents. 7.2.32 Phase C high-side source (PC_HS_S) The source connection for the Phase C high-side output FET is the reference voltage for the gate drive on the high-side FET and also the low-voltage end of the bootstrap capacitor. 7.2.33 Phase C high-side gate (PC_HS_G) This is the gate drive for the Phase C high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of negative currents. 7.2.34 Phase C bootstrap (PC_BOOT) This is the bootstrap capacitor connection for Phase C. A capacitor connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage across this capacitor is limited to about 15 V. 7.2.35 Phase B low-side source (PB_LS_S) The Phase B low-side source is the pin used to return the gate currents from the Lowside FET. Best performance is realized by connecting this node directly to the source of the low-side FET for Phase B. 7.2.36 Phase B low-side gate (PC_LS_G) This is the gate drive for the Phase B low-side output FET. It provides high-current through a low-impedance to turn on and off the low-side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has also been designed to resist the influence of negative currents. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 9 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 7.2.37 Phase B high-side source (PB_HS_S) The source connection for the Phase B high-side output FET is the reference voltage for the gate drive on the high-side FET and also the low-voltage end of the bootstrap capacitor. 7.2.38 Phase B high-side gate (PB_HS_G) This is the gate drive for the Phase B high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of negative currents. 7.2.39 Phase B bootstrap (PB_BOOT) This is the bootstrap capacitor connection for phase B. A capacitor connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage across this capacitor is limited to about 15 V. 7.2.40 PHASE A low-side source (PA_LS_S) The Phase A low-side source is the pin used to return the gate currents from the low-side FET. Best performance is realized by connecting this node directly to the source of the low-side FET for phase A. 7.2.41 Phase A low-side gate (PA_LS_G) This is the gate drive for the Phase A low-side output FET. It provides high-current through a low-impedance to turn on and off the low-side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has also been designed to resist the influence of negative currents. 7.2.42 Phase A high-side source (PA_HS_S) The source connection for the Phase A high-side output FET is the reference voltage for the gate drive on the high-side FET and also the low-voltage end of the bootstrap capacitor. 7.2.43 Phase A high-side gate (PA_HS_G) This is the gate drive for the Phase A high-side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of negative currents. 7.2.44 Phase A bootstrap (PA_BOOT) This is the bootstrap capacitor connection for phase A. A capacitor connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 10 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver gate. Typically, the bootstrap capacitor selection is 10 to 20 times the gate capacitance. The voltage across this capacitor is limited to about 15 V. 7.2.45 VLS regulator (VLS) VLS is the gate drive power supply regulated at approximately 15 V. This is an internally generated supply from VPWR. It is the source for the low-side gate drive voltage, and also the high-side bootstrap source. A low ESR decoupling capacitor, capable of sourcing the pulsed drive currents, must be connected between this pin and VSS. 7.2.46 VPWR input (VPWR) VPWR is the power supply input for VLS and VDD. Current flowing into this input recharges the bootstrap capacitors as well as supplying power to the low-side gate drivers and the VDD regulator. An internal regulator regulates the actual gate voltages. This pin can be connected to system battery voltage if power dissipation is not a concern. 7.2.47 Exposed pad (EP) The primary function of the exposed pad is to conduct heat out of the device. This pad may be connected electrically to the substrate of the device. The device performs as specified with the exposed pad unterminated (floating). However, it is recommended the exposed pad be terminated to pin 29 (VSS) and the system ground. 8 Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are with respect to VSS unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Parameter Conditions Min Max Unit Electrical ratings VSUP VSUP Supply Voltage • Normal Operation (Steady-state) • Transient Survival [1] — –1.5 58 80 V VPWR VPWR Supply Voltage • Normal Operation (Steady-state) • Transient Survival [1] — –1.5 58 80 V VPUMP Charge Pump PUMP, VPUMP –0.3 40 V –0.3 18 V –0.3 7.0 V –0.3 7.0 V [2] VLS VLS Regulator Outputs VDD Logic Supply Voltage VOUT Logic Output INT, SO, PHASEA, PHASEB, PHASEC, OC_OUT VIN Logic Input Pin Voltage EN1, EN2, Px_HS, Px_LS, SI, SCLK, CS, RST 10 mA –0.3 7.0 V VIN_A Amplifier Input Voltage • AMP_P - GND, 6.0 mA source or sink • AMP_N - GND, 6.0 mA source or sink –7.0 –7.0 V VOC Overcurrent comparator Threshold 10 mA –0.3 7.0 V VBOOT VHS_G VLS_G Driver Output Voltage • High-side bootstrap (PA_BOOT, PB_BOOT, PC_BOOT) • High-side (PA_HS_G, PB_HS_G, PC_HS_G) • Low-side (PA_LS_G, PB_LS_G, PC_LS_G) — — — 75 75 16 V MC33GD3000 Product data sheet VLS, VLS_CAP All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 [3] [4] © NXP B.V. 2022. All rights reserved. 11 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 3. Limiting values...continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are with respect to VSS unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Parameter VHS_G VHS_S VLS_G VLS_S Driver Voltage • High-side (PA_HS_G, PB_HS_G, PC_HS_G, PA_HS_S, PB_HS_ Transient Survival S, PC_HS_S) • Low-side (PA_LS_G, PB_LS_G, PC_LS_G, PA_LS_S, PB_LS_S, PC_LS_S) PX_BOOT to MAX difference HS_S PX_BOOT to PX_HS_G PX_HS_G to PX_HS_S PX_LS_G to PX_LS_S VESD Electrostatic discharge voltage Conditions Min Max Unit [5] –7.0 –7.0 –7.0 –7.0 75.0 75.0 18.0 7.0 V [6] 3.0 20.0 V • Static 3.0 16.5 • Static 3.0 16.5 • Static 3.0 16.5 Human Body Model (HBM) [7] PA_Boot, PA_HS_S, PA_HS_G, PB_Boot, PB_HS_S, PB_HS_G, PC_Boot, PC_HS_S, PC_HS_G, VPWR V –2000 +2000 –1000 +1000 Corner pins –750 +750 All other pins –300 +300 All other pins Charged Device Model (CDM) [7] Thermal ratings TSTG Storage Temperature –55 +150 °C TJ Operating Junction Temperature –40 +150 °C RθJC Thermal Resistance [8] — 3.0 °C/W TSOLDER Soldering Temperature [9] — — °C • Junction-to-Case [10] [1] [2] [3] [4] [5] The device will withstand load dump transient as defined by ISO7637 with peak voltage of 80 V. VLS can withstand overvoltage transient of 20 V on initial power-up prior to VLS constant regulation. Short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within this range. This voltage should not be applied without also taking voltage at HS_S and voltage at PX_LS_S into account. Actual operational limitations may differ from survivability limits. The VLS - VLS_S differential and the VBOOT - VHS_S differential must be greater than 3.0 V to insure the output gate drive will maintain a commanded OFF condition on the output. [6] For max ratings between any gate driver pin and VSUP when DCLINK = VSUP use VSUP max ratings. DCLINK is VSUP for this device. [7] ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). [8] Case is considered EP - pin 55 under the body of the device. The actual power dissipation of the device is dependent on the operating mode, the heat transfer characteristics of the board and layout and the operating voltage. See Figure 22 and Figure 23 for examples of power dissipation profiles of two common configurations. Operation above the maximum operating junction temperature will result in a reduction in reliability leading to malfunction or permanent damage to the device. [9] Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. [10] NXP's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes and enter the core ID) to view all orderable parts, and review parametrics. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 12 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 9 Electrical characteristics 9.1 Static electrical characteristics Table 4. Static electrical characteristics Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, – 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit — 6.0 8.0 V — — 1.0 — — 10 — 11 20 Power inputs VPWR_ST VPWR supply voltage startup threshold ISUP VSUP supply current IPWR_ON VPWR supply current ISUP IPWR Sleep state supply current VGATESS [1] VPWR = VSUP = 40 V, RST and ENABLE = 5.0 V • No output loads on gate drive pins, No PWM • No output loads on gate drive pins, 20 kHz, 50 % duty cycle VPWR = VSUP = 40 V, RST and ENABLE = 5.0 V • No output loads on gate drive pins, no PWM, outputs initialized • Output loads = 620 nC per FET, 20 kHz PWM mA [2] mA — — 95 RST = 0 V • VSUP = 40 V • VPWR = 40 V — — 14 56 30 100 Sleep state output gate voltage IG < 100 µA — — 1.3 V VBoot Trickle charge pump (bootstrap voltage) VSUP = 14 V 22 28 32 V VF Bootstrap diode forward Voltage at 10 mA — — 1.2 V 4.5 — 5.5 V — — 12 mA µA [3] VDD internal regulator VDD Output voltage • VPWR = 8 to 40 V, C = 0.47 µF • External load IDD_EXT = 0 to 1.0 mA IDD Internal VDD supply current VDD = 5.5 V, no external lLoad Peak output current VPWR = 16 V, VLS = 10 V [4] VLS regulator IPEAK VLS Linear regulator output voltage VTHVLS VLS disable threshold IVLS = 0 to 60 mA, VPWR > VLS + 2.0 V 350 600 800 mA [5] 13.5 15 17 V [6] 7.5 8.0 8.5 V Charge pump RDS(on)_HS RDS(on)_LS VTHREG Charge Pump • High-side switch-on resistance • Low-side switch-on resistance • Regulation threshold difference [7] [8] — — 250 6.0 5.0 500 10 9.4 900 Ω Ω mV VCP Charge pump output voltage • IOUT = 40 mA, 6.0 V < VSYS < 8.0 V • IOUT = 40 mA, VSYS > = 8.0 V [9] [8] 8.5 12 9.5 — — — V Gate drive RDS(on)_H_SRC High-side driver on resistance • VPWR = VSUP = 16 V, – 40 °C ≤ TA ≤ 25 °C (sourcing) • VPWR = VSUP = 16 V, 25 °C < TA ≤ 135 °C — — — — 6.0 8.5 Ω RDS(on)_H_SINK High-side driver on resistance VPWR = VSUP = 16 V (sinking) — — 3.0 Ω IHS_INJ High-side current injection allowed without malfunction — — 0.5 A RDS(on)_L_SRC Low-side driver on resistance (Sourcing) • VPWR = VSUP = 16 V, – 40 °C ≤ TA ≤ 25 °C • VPWR = VSUP = 16 V, 25 °C < TA ≤ 135 °C — — — — 6.0 8.5 Ω RDS(on)_L_SINK Low-side driver on resistance (Sinking) VPWR = VSUP = 16 V — — 3.0 Ω MC33GD3000 Product data sheet [8] [10] All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 13 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 4. Static electrical characteristics...continued Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, – 40 °C ≤ TA ≤ 135 °C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Parameter ILS_INJ Low-side current injection allowed without malfunction VGS_H VGS_L Gate source voltage VHS_G_HOLD Reverse high-side gate holding voltage Conditions [8] [10] Min Typ Max Unit — — 0.5 Α 13 13 14.8 15.4 16.5 17 VPWR = VSUP = 40 V • High-side, IGATE = 0 • Low-side, IGATE = 0 [11] • Gate output holding current = 2.0 µA • Gate output holding current = 5.0 µA, VSUP 1.0 µF. Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 18 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 9.3 Timing diagrams CS 0.2 VDD tLAG 0.7 VDD 0.2 VDD SCLK tLEAD tDI(SU) tDI(HOLD) 0.7 VDD SI MSB in tDO(EN) SO 0.2 VDD 0.7 VDD tVALID MSB out 0.2 VDD tDO(DIS) LSB out aaa-038725 Figure 3. SPI interface timing Px_HS Px_LS Desaturation fault From delay timer aaa-038792 Figure 4. Desaturation blanking and filtering detail Px_HS D Q CLK STATE MACHINE D Q CLK D MUX A OUT D Q CLK Px_HS_G Px_HS_S DEADTIME CONTROL Px_LS D Q CLK 1st PULSE D Q CLK D Q CLK Px_LS_G A OUT MUX B EN1 EN2 RST aaa-038793 Figure 5. Deadtime control delays MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 19 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Px_HS 50 % 10 V 1.0 V tD_ONH Px_HS_G tONH 50 % Px_LS 10 V 1.0 V tD_ONL Px_LS_G tONL aaa-038743 Figure 6. Driver turn-on time and turn-on delay Px_HS 50 % 10 V 1.0 V tD_OFFH Px_HS_G tOFFH 50 % Px_LS 10 V tD_OFFL Px_LS_G 1.0 V tOFFL aaa-038744 Figure 7. Driver turn-off time and turn-off delay RFBP AMP_P To Protection Circuits OC_TH + VID AMP_N Product data sheet RS + VIN - Rsense RS AMP_OUT RFBN MC33GD3000 REF All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 aaa-038745 © NXP B.V. 2022. All rights reserved. 20 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver -400 mV to +400 mV -400 mV to +400 mV 0V 0V 0 µS - 0.5 µS 0.5 µS - 50 µS 0.5 µS - 50 µS aaa-038746 Figure 8. Current amplifier and input waveform (VIN voltage across RSENSE) aaa-038747 200 gain (dB) 200 phase margin (degrees) Phase margin 100 100 Gain 0.00 0.00 A -100 102 103 104 105 106 -100 107 108 frequency (Hz) Figure 9. Typical amplifier open-loop gain and phase vs. frequency 16 14 aaa-038748 VSUP = 40 V VSUP = 24 V 12 10 VSUP = 14 V VSUP = 9 V 8 6 4 2 0 T50 T50 T30 T10 30 50 70 90 110 130 150 Figure 10. Typical high-side 100 % on gate voltage with 5.0 µA gate load MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 21 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 10 Functional internal block description MC33GD3000 Functional block diagram Integrated Supply Main Charge Pump Trickle Charge Pump 5.0 V Regulator VLS Regulator Sensing and Protection Hold-off Under-voltage Temperature De-sat Current Sense Phase Overcurrent High Side and Low Side Output Predrivers Logic and Control Fault Register Dead Time Phase Control Mode Control SPI Communication Integrated supply Sensing and protection Logic and control Drivers aaa-038801 Figure 11. Functional internal block description All functions of the IC can be described as the following five major functional blocks: • • • • • Logic inputs and interface Bootstrap supply Low-side drivers High-side drivers Charge pump 10.1 Logic inputs and interface This section contains the SPI port, control logic, and shoot-through timers. The IC logic inputs have Schmitt trigger inputs with hysteresis. Logic inputs are 3.0 compatible. The logic outputs are driven from the internal supply of approximately 5.0 V. The SPI registers and functionality is described completely in Section 11.2 "Logic commands and registers". SPI functionality includes the following: • Programming of deadtime delay—This delay is adjustable in approximately 50 ns steps from 0 ns to 12 µs. Calibration of the delay, because of internal IC variations, is performed via the SPI. • Enabling of simultaneous operation of high-side and low-side FETs—Normally, both FETs would not be enabled simultaneously. However, for certain applications where the load is connected between the high-side and low-side FETs, this could be advantageous. If this mode is enabled, the blanking time delay will be disabled. A sequence of commands may be required to enable this function to prevent inadvertent enabling. In addition, this command can only be executed once after reset to enable or disable simultaneous turn-on. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 22 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver • Setting of various operating modes of the IC and enabling of interrupt sources. The 33GD3000 allows different operating modes to be set and locked by an SPI command (FULLON, Desaturation Fault, Zero Deadtime). SPI commands can also determine how the various faults are (or are not) reported. • Read back of internal registers. The status of the 33GD3000 status registers can be read back by the Master (DSP or MCU). The Px_HS and Px_LS logic inputs are edge sensitive. This means the leading edge on an input causes the complementary output to immediately turn off and the selected one to turn on after the deadtime delay as illustrated in Figure 12. The deadtime delay timer always starts at the time a FET is commanded off and prevents the complementary FET from being commanded on until after the deadtime has elapsed. Commands to turn on the complementary FET after the deadtime has elapsed are executed immediately without any further delay. See Figure 5 and Figure 12. PA_HS PA_LS Deadtime delay PA_HS_G PA_LS_G aaa-038750 Figure 12. Edge sensitive logic inputs (phase A) 10.1.1 Low-side and bootstrap supply (VLS) This is the portion of the IC providing current to recharge the bootstrap capacitors. It also supplies the peak currents required for the low-side gate drivers. The power for the gate drive circuits is provided by VLS which is supplied from the VPWR pin. This pin can be connected to system battery voltage and is capable of withstanding up to the full load dump voltage of the system. However, the IC only requires a low-voltage supply on this pin, typically 13 V to 16 V. Higher voltages on this pin increases the IC power dissipation. In 12 V systems, the supply voltage can fall as low as 6.0 V. This limits the gate voltage capable of being applied to the FETs and reduces system performance due to the higher FET on-resistance. To allow a higher gate voltage to be supplied, the IC also incorporates a charge pump. The switches and control circuitry are internal; the capacitors and diodes are external. See Figure 21. 10.1.2 Low-side drivers These three drivers turn on and off the external Low-side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their drains. Additionally, these output drivers isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FET drains. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 23 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Low-side drivers switch power from VLS to the gates of the Low-side FETs. The Low-side drivers are capable of providing a typical peak current of 2.0 A. This gate drive current may be limited by external resistors in order to achieve a good trade-off between the efficiency and EMC (Electro-Magnetic Compatibility) compliance of the application. the low-side driver uses high-side PMOS for turn on and low-side isolated LDMOS for turn off. The circuit ensures the impedance of the driver remains low, even during periods of reduced current. Current limit is blanked immediately after subsequent input state change to ensure device stays off during dV/dt transients. 10.1.3 High-side drivers These three drivers switch the voltage across the bootstrap capacitor to the external high-side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their sources. Further, these output drivers isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FETs. The high-side drivers deliver power from their bootstrap capacitor to the gate of the external high-side FET, thus turning the high-side FET on. The high-side driver uses a level shifter, allowing the gate of the external high-side FET to be turned off by switching to the high-side FET source. The gate supply voltage for the high-side drivers is obtained from the bootstrap supply, so, a short time is required after the application of power to the IC to charge the bootstrap capacitors. To ensure this occurrence, the internal control logic does not allow a high-side switch to be turned on after entering the ENABLE state until the corresponding low-side switch is enabled at least once. Caution must be exercised after a long period of inactivity of the low-side switches to verify the bootstrap capacitor is not discharged. It is charged by activating the low-side switches for a brief period, or by attaching external bleed resistors from the HS_S pins to GND. See Section 11.3 "Initialization requirements". In order to achieve a 100 % duty cycle operation of the high-side external FETs, a fully integrated trickle charge pump provides the charge necessary to maintain the external FET gates at fully enhanced levels. The trickle charge pump has limited ability to supply external leakage paths while performing it's primary function. The graph in Figure 10 shows the typical margin for supplying external current loads. These limits are based on maintaining the voltage at CBOOT at least 3.0 V greater than the voltage on the HS_S for that phase. If this voltage differential becomes less than 3.0 V, the corresponding high-side FET most likely does not remain fully enhanced and the high-side driver may malfunction due to insufficient bias voltage between CBOOT and HS_S. The slew rate of the external output FET is limited by the driver output impedance, overall (external and internal) gate resistance and the load capacitance. To ensure the lowside FET is not turned on by a large positive dV/dt on the drain of the low-side FET, the turn-on slew rate of the high-side should be limited. If the slew rate of the high-side is limited by the gate-drain capacitance of the high-side FET, then the displacement current injected into the low-side gate drive output is approximately the same value. Therefore, to ensure the low-side drivers can be held off, the voltage drop across the low-side gate driver must be lower than the threshold voltage of the low-side FET. See Figure 13. Similarly, during large negative dV/dt, the high-side FET is able to remain off if its gate drive low-side switch, develops a voltage drop less than the threshold voltage of the highside FET. The gate drive low-side switch discharges the gate to the source. Additionally, during negative dV/dt the low-side gate drive could be forced below ground. The low-side FETs must not inject detrimental substrate currents in this condition. The occurrence of these cases depends on the polarity of the load current during switching. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 24 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Phase X output Px_HS_S VLS D LS control Lowside driver Discrete FET package CDC iCDG Px_LS_G G - + Rg CDS CGC S Px_LS_S Phase return Px_HS_G Deadtime Px_LS_G Phase x Output voltage VSUP dV/dt -VD aaa-038752 Figure 13. Positive DV/dt transient 10.1.4 Driver fault protection The 33GD3000 integrates several protection mechanisms against various faults. The first of them is the current sense amplifier with the overcurrent comparator. These two blocks are common for all three driver phases. 10.1.4.1 Current sense amplifier This amplifier is usually connected as a differential amplifier. See Figure 8. It senses a current flowing through the external FETs as a voltage across the current sense resistor RSENSE. because the amplifier common mode range does not extend below ground, it is necessary to use an external reference to permit measuring both positive and negative currents. The amplifier output can be monitored directly (e.g. by the microcontroller's ADC) at the AMP_OUT pin, providing the means for closed loop control with the 33GD3000 . The output voltage is internally compared with the overcurrent comparator threshold voltage. See Figure 21. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 25 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 10.1.4.2 Overcurrent comparator The amplified voltage across RSENSE is compared with the preset threshold value by the overcurrent comparator input. If the current sense amplifier output voltage exceeds the threshold of the overcurrent comparator, it would change the status of its output (OC_OUT pin) and the fault condition would be latched. See Figure 17. The occurrence of this fault would be signaled by the return value of the Status Register 0. If the proper interrupt mask has been set, this fault condition generates an interrupt - the INT pin asserts High. The INT is held in the High state until the fault is removed, and the appropriate bit in the Status Register 0 is cleared by the CLINT0 command. This fault reporting technique is described in detail in Section 11.2 "Logic commands and registers". 10.1.4.3 Desaturation detector The Desaturation Detector is a comparator integrated into the output driver of each phase channel. It provides an additional means to protect against "Short-to-Ground" fault condition. A short to ground is detected by an abnormally high-voltage drop in VDS of the high-side FET. Note that if the gate-source voltage of the high-side FET drops below saturation, the device goes into linear mode of conduction, which can also cause a desaturation error. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 26 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 3x VSUP VLS T-Lim Px_BOOT VSUP HS control Highside driver Px_HS_G 1.4 V Desat. Comp VSUP Phase Comp LS control R Phase X output Px_HS_S Lowside driver Phase x output shorted to ground (Low-side FET shorted) Px_LS_G Phase return R Px_LS_S To current sense amplifier VLS_CAP Px_HS_G tBLANK Deadtime RSense tFILT Px_LS_G Correct phase x Output voltage VSUP 0.5 VSUP Phase x Output voltage shorted to ground -VD Correct Fault PHASEx Phase error Desaturation error aaa-038753 Figure 14. Short to ground detection When switching from low-side to high-side, the high-side is commanded ON after the end of the deadtime. The deadtime period starts when the low-side is commanded OFF. If the voltage at Px_HS_S is less than 1.4 V below VSUP after the blanking time (tBLANK), a desaturation fault is initiated. An additional 1.0 μs digital filter is applied from the initiation of the desaturation fault before it is registered, and all phase drivers are turned OFF (Px_HS_G clamped to Px_HS_S and Px_LS_G clamped to Px_LS_S). If the desaturation fault condition clears before the filter time expires, the fault is ignored and the filter timer resets. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 27 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Valid faults are registered in the fault status register, which can be retrieved by way of the SPI. Additional SPI commands mask the INT flag and disable an output stage shutdown, due to desaturation and phase errors. See 7.2, Logic commands and registers on page 35 for details on masking INT behavior and disabling the protective function. 3x VSUP VLS T-Lim Px_BOOT VSUP HS control Highside driver Px_HS_G 1.4 V Desat. Comp VSUP Phase Comp LS control R Phase x output shorted to ground (High-side FET shorted) Lowside driver Px_HS_S Phase X output Px_LS_G Phase return R Px_LS_S To current sense amplifier VLS_CAP RSense Px_HS_G Deadtime tBLANK Px_LS_G Phase x Output voltage shorted to VSUP VSUP 0.5 VSUP Correct phase x Output voltage -VD Fault PHASEx Correct Phase error aaa-038772 Figure 15. Short to supply detection 10.1.4.4 Phase comparator Faults could also be detected as phase errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 28 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver A phase error is detected by a Phase comparator. The Phase comparator compares the voltage at the Px_HS_S node with a reference of one half the voltage at the VSUP pin. A high-side phase error (which also triggers the Desaturation Detector) occurs when the high-side FET is commanded on, and Px_HS_S is still low at the end of the deadtime and blanking time duration. Similarly, a LS phase error occurs when the low-side FET is commanded on, and the Px_HS_S is still high at the end of the deadtime and blanking time duration. The Phase Error flag is the triple OR of phase errors from each phase. Each phase error is the OR of the high-side and low-side phase errors. This flag can generate an interrupt if the appropriate mask bit is set. The INT is held in the high state until the fault is removed, and the appropriate bit in the Status Register 0 is cleared by the CLINT1 command. This fault reporting mechanism is described in detail in Section 11.2 "Logic commands and registers". 10.1.5 VLS undervoltage because VLS supplies both the gate driver circuits and the gate voltage, it is critical it maintains sufficient potential to place the power stage FETs in saturation. because proper operation cannot continue with insufficient levels, a low VLS condition shuts down driver operation. The VLS undervoltage threshold is between 7.5 V and 8.5 V. When a decreasing level reaches the threshold, both the HS and the LS output gate circuit drive the gates OFF for about 8.0 μs before reducing the drive to hold off levels. because low VLS is a condition for turning on the Hold Off circuit, Hold Off then provides a weak pulldown on all gates. A filter timeout of about 700 ns insures noise on VLS does not cause premature protective action. When VLS rises above this threshold again, the LS Gate immediately follows the level of the input. However, a short initialization sequence must be executed to restore operation of the HS Gate. See Section 11.3 "Initialization requirements". Because VLS is no longer undervoltage, the Hold Off circuit is turned off and the HS Gate is in a high-impedance state until the LS Gate responds to an input command to turn off. 10.1.6 Hold off circuit The IC guarantees the output FETs are turned off in the absence of VDD or VPWR by means of the Hold off circuit. A small current source, generated from VSUP, typically 100 µA, is mirrored and pulls all the output gate drive pins low when VDD is less than about 3.0 V, RST is active (low), or when VLS is lower than the VLS_Disable threshold. A minimum of 3.0 V is required on VSUP to energize the Hold off circuit. 10.1.7 Charge pump The charge pump circuit provides the basic switching elements required to implement a charge pump, when combined with external capacitors and diodes for enhanced low-voltage operation. When the 33GD3000 is connected per the typical application using the charge pump (see Figure 21), the regulation path for VLS includes the charge pump and a linear regulator. The regulation set point for the linear regulator is nominally at 15.34 V. As long as VLS output voltage (VLSOUT) is greater than the VLS analog regulator threshold (VLSATH) minus VTHREG, the charge pump is not active. If VLSOUT < VLSATH – VTHREG the charge pump turns ON until VLSOUT > VLSATH – VTHREG + VHYST MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 29 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver VHYST is approximately 200 mV. VLSATH does not interfere with this cycle even when there is overlap in the thresholds, due to the design of the regulator system. The maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the pump frequency (nominally 130 kHz), and the RDS(on) of the pump FETs. The effective charge voltage for the pump capacitor would be VSYS – 2 * VDIODE. The total charge transfer would then be CPUMP * (VSYS – 2*VDIODE). Multiplying by the switch frequency gives the theoretical current the pump can transfer: FPUMP * CPUMP * (VSYS – 2*VDIODE). Note: There is also another smaller, fully integrated charge pump (Trickle Charge Pump - see Figure 1) that is used to maintain the high-side drivers' gate VGS in 100 % duty cycle modes. 11 Functional device operation 11.1 Operational modes 11.1.1 Reset and enable The 33GD3000 has three power modes of operation described in Table 6. There are three global control inputs (RST, EN1, EN2) that together, with the status of VDD, VLS, and DESAT/PHASE faults control the behavior of the IC. The operating status of the IC can be described by the following five modes: • Sleep Mode - When RST is low, the IC is in Sleep mode. The current consumption of the IC is at minimum. • Standby Mode - The RST input is high while one of the Enable inputs is low. The IC is fully biased up and operating, all the external FETs are actively turned off by both highside and low-side gate drives. The IC is ready to enter the Enable mode. • Initialization Mode - When EN1, EN2, and RST all go high, the device enters the Initialization mode. Toggling the LS and then the HS initializes the driver and normal operation in the Enable mode begins. (See Section 11.3 "Initialization requirements") • Enable Mode - After initialization is complete, the device goes into the Enable mode and operates normally. Normal operation continues in this mode as long as both enable pins and RST are high. • Fault Protection Mode - If a protective fault occurs (either Desat/Phase or VLS UV) the device enters a Fault Protection mode. After a fault clears, the device requires initialization again before resuming normal Enable mode operation. Table 6. Functions of RST, EN1, and EN2 pins RST EN1, EN2 0 xx Sleep Mode - In this mode (low quiescent current) the driver output stage is switched off with a weak pulldown. All error and SPI registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except SO are clamped to VSS. 1 0x x0 Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external FETs (after initialization). The SPI port is functional. Logic level outputs are driven with low-impedance. SO is high-impedance unless CS is low. VDD, Charge Pump and VLS regulators are all operating. The IC is ready to move to Enable mode. Mode of operation (driver condition) MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 30 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 6. Functions of RST, EN1, and EN2 pins...continued RST 1 EN1, EN2 11 Mode of operation (driver condition) Initialization Mode - Low-side drivers are enabled, SPI is fully operational. Ready for initialization. See Section 11.3. Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs require a pulse on Px_LS before corresponding HS outputs are turn on to charge the bootstrap capacitor. All error pins and register bits are active if detected. Fault Protection Mode - Drivers are turned OFF or disabled per the fault and protection mode registers. Recovery requires initialization See Section 11.3. Table 7. Functional ratings (TJ = -40 °C to 150 °C and supply voltage range VSUP = VPWR = 5.0 V to 45 V, C = 0.47 µF) Characteristic Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open (Driver output is switched off, high-impedance mode) Value [1] [1] Default State of input pin Px_HS, CS if left open (Driver output is switched off, high-impedance mode) [1] Low (2.0 V) To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 31 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Sleep Mode Sleep Y N RST Standby Mode STBY Initialization N EN Y Enable (Normal) Mode ENABLE LS N LS Toggle Y HS Toggle Y ENABLE HS N DESAT/ Disabled Fault Protection N DESAT/ PHASE N Y Driver OFF VLS UV DESAT/ PHASE N Y N Y Disable Driver Holdoff Active Driver OFF Y VLS UV N Y N EN Y Y RST N aaa-038773 Figure 16. Device operational flow diagram 11.2 Logic commands and registers 11.2.1 Command descriptions The IC contains internal registers to control the various operating parameters, modes, and interrupt characteristics. These commands are sent and status is read via 8-bit SPI commands. The IC uses the last eight bits in a SPI transfer, so devices can be daisychained. The first three bits in an SPI word can be considered to be the Command with the trailing five bits being the data. The SPI logic generates a framing error and ignores the SPI message if the number of received bits is not eight or not a multiple of eight. After RST, the first SPI result returned is Status Register 0. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 32 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 8. Command list Command Name 000x xxxx NULL 0010 xxxx MASK0 Sets a portion of the interrupt mask using lower four bits of command. A "1" bit enables interrupt generation for this flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0. 0011 xxxx MASK1 Sets a portion of the interrupt mask using lower four bits of command. A "1" bit enables interrupt generation for this flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0. 010x xxxx Mode Enables Desat/Phase Error mode. Enables FULLON mode. Locks further mode changes. Returns Status Register 0. 0110 xxxx CLINT0 Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears the interrupt latch for this flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0. 0111 xxxx CLINT1 Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears the interrupt latch for this flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0. 100x xxxx Description These commands are used to read IC status. These commands do not change any internal IC status. Returns Status Register 0-3, depending on sub command. DEADTIME Set deadtime with calibration technique. Returns Status Register 0. 11.2.2 Fault reporting and interrupt generation Different fault conditions described in the previous chapters can generate an interrupt INT pin output signal asserted high. When an interrupt occurs, the source can be read from Status Register 0, which is also the return word of most SPI messages. Faults are latched on occurrence, and the interrupt and faults are only cleared by sending the corresponding CLINTx command. A fault still existing continue to assert an interrupt. Note: If there are multiple pending interrupts, the INT line does not toggle when one of the faults is cleared. Interrupt processing circuitry on the host must be level sensitive to correctly detect multiple simultaneous interrupt. Thus, when an interrupt occurs, the host can query the IC by sending a NULL command; the return word contains flags indicating any faults not cleared since the CLINTx command was last written (rising edge of CS) and the beginning of the current SPI command (falling edge of CS). The NULL command causes no changes to the state of any of the fault or mask bits. The logic clearing the fault latches occurs only when: • A valid command had been received, i.e., no framing error • A state change did not occur during the SPI message (if the bit is being returned as a 0 and a fault change occurs during the middle of the SPI message, the latch remains set). The latch is cleared on the trailing (rising) edge of the CS pulse. Note, to prevent missing any faults the CLINTx command should not generally clear any faults without being observed; i.e., it should only clear faults returned in the prior NULL response. 11.2.3 NULL commands This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message 000x xx00 reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 33 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 9. NULL commands SPI Data Bits 7 6 5 4 3 2 1 0 Write 0 0 0 x x x 0 0 Reset NULL Commands are described in detail in Section 11.2.4 of this document. 11.2.3.1 MASK command This is the mask for interrupts. A bit set to "1" enables the corresponding interrupt. Because of the number of MASK bits, this register is in two portions: 1. MASK0 a. MASK1 Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. Figure 17 illustrates how interrupts are enabled and faults cleared. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch and status register 0 bit corresponding to the lower nibble of the command. Table 10. MASK0 register SPI Data Bits 7 6 5 4 3 2 1 0 Write 0 0 1 0 x x x x 1 1 1 1 Reset 11.2.3.2 Interrupt handling To status register From MASKx:N register Mask bit INT source Various faults Latch INT clear From clint command net N Fault S INT R net 0 aaa-038774 Figure 17. Interrupt handling Table 11. MASK1 register SPI Data Bits 7 6 5 4 3 2 1 0 Write 0 0 1 1 x x x x 1 1 1 1 Reset Table 12. Setting interrupt masks Mask:bit Description MASK0:0 Overtemperature on any gate drive output generates an interrupt if this bit is set. MASK0:1 Desaturation event on any output generates an interrupt if this bit is set. MASK0:2 VLS Undervoltage generates an interrupt if this bit is set. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 34 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Table 12. Setting interrupt masks...continued Mask:bit Description MASK0:3 Overcurrent Error–if the overcurrent comparator threshold is exceeded, an interrupt is generated. MASK1:0 Phase Error–if any Phase comparator output is not at the expected value when an output is command on, an interrupt is generated. This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration of the desaturation blanking interval. In FULLON mode, this signal is blanked and cannot generate an error. MASK1:1 Framing Error–if a framing error occurs, an interrupt is generated. MASK1:2 Write Error after locking. MASK1:3 Reset Event–If the IC is reset or disabled, an interrupt occurs. because the IC always starts from a reset condition, this can be used to test the interrupt mechanism, because when the IC comes out of RESET, an interrupt immediately occurs. 11.2.3.3 MODE command This command is sent by sending binary 010x xxxx data. Table 13. Mode Command SPI Data Bits 7 6 5 4 3 2 1 0 Write 0 1 0 0 Desaturation Fault Mode 0 FULLON Mode Mode Lock 0 0 0 0 Reset • Bit 0–Mode Lock is used to enable or disable Mode Lock. This bit can only be cleared with a device reset. because the Mode Lock mode can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. If an attempt is made to write to a register when Mode Lock is enabled, a Write Error fault is generated. • Bit 1–FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high and low-side drivers in a phase on simultaneously. This could be useful in special applications such as alternator regulators, or switched-reluctance motor drive applications. There is no deadtime control in FULLON mode. Input signals directly control the output stages, synchronized with the internal clock. This bit is a "0", after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents both outputs from being turned on simultaneously. • Bit 3– Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to "0", any desaturation on any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the CLINT command. When 1, desaturation faults are completely ignored. Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities are: – 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates an Interrupt, if interrupts are enabled. – 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked. Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further changes. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 35 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 11.2.3.4 DEADTIME command Deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. The deadtime timer starts when a FET is commanded off. See Figure 5 and Figure 12. The deadtime control is disabled by enabling the FULLON mode. The deadtime is set by sending the DEADTIME command (100x xxx1), and then sending a calibration pulse of CS. This pulse must be 16 times longer than the required deadtime. See Figure 18. Deadtime is measured in cycle times of the internal time base, fTB. This measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low gate transactions in the same phase. For example: the internal time base is running at 20 MHz and a 1.5 µs deadtime is required. First a DEADTIME command is sent (using the SPI), then a CS is sent. The CS pulse is 16*1.5 = 24 µs wide. The IC measures this pulse as 24000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in the deadtime register. Until the next deadtime calibration is performed, 30 clock cycles separates the turn off and turn on gate signals in the same phase. The worst case error immediately after calibration is +0/-1 time base cycle, for this example +0 ns/-50 ns. Note that if the internal time base drifts, the effect on dead time scales directly. Sending a ZERO DEADTIME command (100x xxx0) sets the deadtime timer to 0. However, simultaneous turn-on of high-side and low-side FETs in the same phase is still prevented unless the FULLON command has been transmitted. There is no calibration pulse expected after receiving the ZERO DEADTIME command. After RESET, deadtime is set to the maximum value of 255 time base cycles (typically 15 µs). The IC ignores any SPI data sent during the calibration pulse. If there are any transitions on SI or SCLK while the Deadtime CS pulse is low, a Framing error is generated, however, the CS pulse is used to calibrate the deadtime Table 14. Deadtime command SPI Data Bits 7 6 5 4 3 2 1 0 Write 1 0 0 x x x x ZERO/CA LIBRATE x x x x Reset CS Deadtime calibration pulse SCLK Deadtime command SI SO aaa-038775 Figure 18. Deadtime calibration 11.2.4 Status registers After any SPI command, the status of the IC is reported in the return value from the SPI port. There are four variants of the NULL command used to read various status in the IC. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 36 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Other commands return a general status word in the Status Register 0. There are four Status Registers in the IC. Status Register 0 is most commonly used for general status. Registers one through three are used to read or confirm internal IC settings. 11.2.4.1 Status register 0 (status latch bits) This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command returns the following data: Table 15. Status register 0 SPI Data Bits Results Register 0 Read Reset 7 6 5 RESET Event Write Error Framing Error 1 0 0 4 3 2 Phase Error Overcurrent Low VLS 0 0 0 1 0 DESAT Detected on any channel TLIM Detected on any channel 0 0 All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits set. If the status is still present, this bit does not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively. • Bit 0–is a flag for Overtemperature on any channel. This bit is the OR of the latched three internal TLIM detectors. This flag can generate an interrupt if the appropriate mask bit is set. • Bit 1–is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal high-side desaturation detectors and phase error logic. Faults are also detected on the low-side as phase errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which also triggers the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still low in the deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the Px_HS_S is still high in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the appropriate mask bit is set. • Bit 2– is a flag for Low Supply Voltage. This flag can generate an interrupt if the appropriate mask bit is set. • Bit 3–is a flag for the output of the Overcurrent Comparator. This flag can generate an interrupt if the appropriate mask bit is set. • Bit 4–is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the individual high or Low-side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an interrupt if the appropriate mask bit is set. • Bit 5–is a flag for a Framing Error. A framing error is a SPI message not containing one or more multiples of eight bits. SCLK toggling while measuring the Deadtime calibration pulse is also a framing error. This would typically be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This flag can generate an interrupt if the appropriate mask bit is set. • Bit 6–indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one defined in the Table 8. This would typically be a software error. This flag can generate an interrupt if the appropriate mask bit is set. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 37 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver • Bit 7–is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set. 11.2.4.2 Status register 1 (mode bits) This register is read by sending the NULL1 command (000x xx01). This is guaranteed to not affect IC operation and returns the following data: Table 16. Status register 1 SPI Data Bits 7 Results Register 1 Read 0 Reset 0 6 5 Desaturation Zero Mode Deadtime Set 0 0 4 3 2 1 0 Calibration Overflow Deadtime Calibration 0 FULLON Mode Lock Bit 0 0 0 0 0 • Bit 0–Lock Bit indicates the IC registers (Deadtime, MASKn, CLINTn, and Mode) are locked. Any subsequent write to these registers is ignored and sets the Write Error flag. • Bit 1– is the present status of FULLON Mode. If this bit is set to "0", the FULLON mode is not allowed. A "1" indicates the IC can operate in FULLON Mode (both highside and low-side FETs of one phase can be simultaneously turned on). • Bit 3–indicates Deadtime Calibration occurred. It is "0" until a successful Deadtime command is executed. This includes the Zero Deadtime setting, as well as a Calibration Overflow. • Bit 4–is a flag for a Deadtime Calibration Overflow. • Bit 5–is set if Zero Deadtime is commanded. • Bit 6–reflects the current state of the Desaturation/Phase Error turn-off mode. 11.2.4.3 Status register 2 (mask bits) This register is read by sending the NULL2 command (000x xx10). This is guaranteed to not affect IC operation and returns the following data: Table 17. Status register 2 SPI Data Bits Results Register 2 Read 7 6 5 4 3 2 1 0 Mask1:3 Mask1:2 Mask1:1 Mask1:0 Mask0:3 Mask0:2 Mask0:1 Mask0:0 1 1 1 1 1 1 1 1 Reset 11.2.4.4 Status register 3 (deadtime) This register is read by sending the NULL3 command (000x xx11). This is guaranteed to not affect IC operation and returns the following data: Table 18. Status register 3 SPI Data Bits Results Register 3 Read Reset 7 6 5 4 3 2 1 0 Dead7 Dead6 Dead5 Dead4 Dead3 Dead2 Dead1 Dead0 0 0 0 0 0 0 0 0 These bits represent the calibration applied to the internal oscillator to generate the requested deadtime. If calibration is not yet performed, all these bits return 0 even though the actual dead time is the maximum. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 38 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 11.3 Initialization requirements The 33GD3000 provides safe, dependable gate control for three phase BLDC motor control units when it is properly configured. However, if improperly initialized, the highside gate drive can be left in a high-impedance mode which allows charge to accumulate from external sources, eventually turning on the high-side output transistor. It is prudent to follow a well defined initialization procedure which establishes known states on the gates of all the phase drivers before any current flows in the motor. 11.3.1 Recovery from sleep mode (RESET) The output gate drive is pulled low with the hold off circuit as long as VLS is low, there is a Power On Reset condition or +5.0 V is low. These conditions are present during a reset condition. When first coming out of a reset condition, the gate drive circuits are in a high-impedance state until the first command is given for operation. After the reset line goes high, the supplies begin to operate and the hold off circuit is deactivated. The phase input lines do not have any effect on the gate drive until both ENABLE1 and ENABLE2 go high, and even then the low-side gate must be commanded on before the high-side gate can be operated. This is to insure the bootstrap capacitor has been charged before commencing normal operation. The high-side gate must then be commanded on and then off to initialize the output latches. A proper initialization sequence places the output gate drives in a low-impedance known condition prior to releasing the device for normal operation. A valid initialization sequence would go something like this: 1. 2. 3. 4. 5. RESET goes high (ENABLE1 and ENABLE2 remain low) SPI commands to configure valid interrupts, DESAT mode and Dead Time are issued SPI command to clear all interrupt conditions ENABLE1 and ENABLE2 are set HIGH (LS outputs are now enabled) PA_LS, PB_LS, and PC_LS are toggled HIGH for about 1.0 μs (HS outputs are enabled, but not latched) 6. Toggle nPA_HS, nPB_HS, and nPC_HS LOW for DEAD TIME plus at least 0.1 μs (HS outputs are now latched and operational). End of initialization. Doing step 6 simultaneously on all HS inputs places the motor into High-side Recirculation mode and does not cause motion during the time they are ON. This action forces the high-side gate drive out of tri-state mode and leaves it with the HS_G shorted to HS_S on all phases. The HS output FETs is OFF and ready for normal motor control. Step 5 and step 6 can be done on all the stated inputs simultaneously. It may be desirable for the HS (step 6) to be toggled simultaneously to prevent current from flowing in the motor during initialization. Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS, nPB_HS, and nPC_HS are edge sensitive. Toggling the LS inputs enables the HS drivers, so for the HS drivers to be initialized correctly the edge of the input signal to the HS drivers must come after the LS input toggle. A failure to do this results in the HS gate output remaining in a highimpedance mode. This can result in an accumulation of charge, from internal and external leakage sources, on the gate of the HS output FET causing it to turn ON even though the input level to the 33GD3000 would appear to indicate it should be OFF. When this happens, the logic of the 33GD3000 allows the LS output FET to be turned ON MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 39 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver without taking any action on the HS gate because the logic is still indicating the HS gate is OFF. The initial LS input transition from low to high needs to be after both ENABLE inputs are high (the device in NORMAL mode) for the same reason. The delay between ENABLE and the LS input should be 280 ns minimum to insure the device is out of STBY mode. Once initialized the output gate drives continues to operate in a low-impedance mode as commanded by the inputs until the next reset event. INT SPI CS Px_HS Px_LS EN1-2 RST VDD VLS VPWR VSUP tPU_VDD tPU_VLS t1 t2 t3 t4 t5 t6 aaa-038776 Figure 19. Full initialization Table 19. Full initialization timing description Time tPU_VDD, tPU_VLS Description Min. Power up time from RESET 2.0 ms Comments RESET must remain high long enough for VDD and VLS to reach the full regulated voltage. The normal time for this to occur is specified as 2.0 ms maximum. If there is more capacitance on VLS or VDD than the normal values given in the specification, this time may need to be increased. In general, the time may be safely scaled linearly with the capacitance. If the charge pump is used, it may also increase this time. An estimate of increased time, due to the charge pump, would be to add 25 %. For example, the nominal VLS capacitance is 2.2 µF on each pin, the power up time should be increased to 4.0 ms, 5.0 ms if using the charge pump. t1 End of SPI communication 0 ns to EN1 and EN2 rising edge t2 EN1 and EN2 rising edge to 280 ns first LS output command Restricted by EN1 and EN2 propagation delay t3 Initial LS ON period 1.0 µs Nominally 1.0 µs is more that enough. The calculated value is 5*CBOOT(RSENSE + RDSON_LS). 100 ns for default recovery. t4 LS OF to HS ON 0 ns No defined maximum, but HS is undefined until beginning of toggle on the HS t5 Initial HS ON period 100 ns + dead time Minimum: Dead-time + 100 ns to guarantee the HS is switched. Maximum: Same limitations as Normal Operation. Unlimited time if leakage currents are less than trickle charge pump margin. t6 HS OFF to Normal Operation 0 ns Immediately begin Normal Operation MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 40 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 11.3.2 Recovery from standby mode or a fault When the 33GD3000 is placed in Standby mode or a fault condition causes a shutdown, the Gate outputs are all driven low. The high-side gate drive is then disabled and locked to prevent unauthorized transitions. This requires an initialization sequence to recover normal operation at the end of this mode of operation. The initialization sequence is nearly identical to recovery from Sleep mode, with the modification that the initial pulse to the low-side control inputs can be reduced to a 100 ns pulse (the low-side gates may not actually change state). The initialization is then completed by cycling the high-side gates to re-engage the gate drive and insure that it is in the proper state prior to resuming normal operation. A valid initialization sequence would go something like this: 1. SPI command to clear all interrupt conditions 2. ENABLE1 and ENABLE2 are set HIGH (LS outputs are now enabled) 3. PA_LS, PB_LS and PC_LS are toggled HIGH for at least 100 ns (HS gate drive outputs are enabled) longer if bootstrap capacitors need charged. 4. Toggle nPA_HS, nPB_HS and nPC_HS LOW for DEAD TIME plus at least 100 ns. End of initialization. Doing step 4 simultaneously on all HS inputs places the motor into High-side Recirculation mode and does not cause motion during the time they are ON. This action restores the high-side gate drive operation and leave it with the HS_G shorted to HS_S on all phases. The HS output FETs will be OFF and ready for normal motor control. Step 3 and step 4 can be done on all the stated inputs simultaneously. In fact it is desirable for the HS (step 4) to be toggled simultaneously to prevent current from flowing in the motor during initialization. Note the inputs PA_LS, PB_LS, PC_LS, nPA_HS, nPB_HS, and nPC_HS are edge sensitive. Toggling the LS inputs enables the HS drivers, so for the HS drivers to be initialized correctly, the edge of the input signal to the HS drivers must come after the LS input toggle. A failure to do this results in the HS gate output remaining locked out from input control. The initial LS input transition from low to high needs to be after both ENABLE inputs are high (the device in Normal mode) for the same reason. The delay between ENABLE and the LS input should be 280 ns minimum to insure the device is out of STBY mode. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 41 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver INT SPI nCS CLEAR Px_Combined nPx_HS 0.1 µS Px_LS EN2 EN1 0.1 µS aaa-038778 Figure 20. Recovery initialization The horizontal divisions are not to scale. They are a reference to show the sequence of operation. Either individual nPx_HS and Px_LS or nPx_Combined may be used. nPx_Combined is defined as both nPx_HS and Px_LS tied together or operated to the same logic level simultaneously. 11.3.3 IC initialization This process flow initializes the IC and its software environment. 1. Apply power (VSYS) to module 2. Remove RST (RST goes high, EN1 and EN2 are still low) a. When RST rises above the threshold, the device powers up. The charge pump (if configured) starts and allows VDD and VLS to stabilize. 3. Initialize registers a. Clear all interrupt status flags (send CINT0 and CINT1) b. Initialize MASK register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. c. Set desired dead time either by commanding zero dead time or calibrating the dead time. d. Send MODE command with desired bits, and also the Lock bit. e.g. 01000001. This prevents further mode changes. 4. Bring EN1 & EN2 high 5. Initialize the outputs a. Command all Px_HS to logic 1 (High-side OFF) b. Command all Px_LS to logic 1 (commanding low-side ON). The input must transition from low to high after EN1 and EN2 have gone high. c. Wait for the bootstrap capacitors to charge (about 1 us typically) d. Command all Px_LS to logic 0 (command low-side OFF) e. Command all Px_HS to logic 0 (command high-side ON) f. Command all Px_HS to logic 1 (command high-side OFF) The device is now ready for normal operation. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 42 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 11.3.4 Interrupt handler When an interrupt occurs, the general procedure is to send NULL0 and NULL1 commands to determine what happened, take corrective action (if needed), clear the fault, and return. Because the return value from an SPI command is actually returned in the subsequent message, main-loop software trying to read SR1, SR2, or SR3, may experience an interrupt between sending the SPI command and the subsequent read. Thus if these registers are to be read, special care must be taken in the software to ensure the correct results are being interpreted. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 43 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 12 Typical applications 12.1 Typical 12 V application VSYS to other two phases +12 V nom. D1 D2 C6 C1 C2 PUMP MAIN CHARGE PUMP VPUMP VPWR 5V reg. VDD VSUP TRICKLE CHARGE PUMP VLS reg. HOLD -OFF CIRCUIT PGND VLS VDD OSCILLATOR C3 C4 UV DETECT 3x Px_BOOT T-Lim VSUP RST INT EN1 EN2 Px_HS Px_LS 1.4 V desat. comp. CONTROL LOGIC 3 3 Cx_Boot Rg_HS Px_HS_G QHS (optional) DRIVER phase x output Px_HS_S CS SI SCLK SO PHASE_x HIGHSIDE VSUP LOWSIDE phase comp. QLS (optional) DRIVER 3 Rg_LS Px_LS_G to motor phase return Px_LS_S R1 OC_OUT GND over-cur. comp. OC_TH Rsense R3 R2 I-sense amp. AMP_OUT AMP_N AMP_P VLS_CAP C5 to ADC Rfb aaa-033850 Figure 21. Typical 12 V application diagram using charge pump (+12 V battery system) MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 44 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver aaa-038780 1.0 Power dissipated (Ω) 0.8 0.6 0.4 0.2 0 5 10 15 20 25 30 35 40 Supply voltage (V) Figure 22. Power dissipation profile of application using charge pump Reference application with: • • • • • • Pump capacitor: 1.0 μF MLC Pump filter capacitor: 47 μF low ESR aluminum electrolytic Pump diodes: MUR120 Output FET gate charge: 240 nC @ 10 V PWM Frequency: 20 kHz Switching Single Phase Power dissipation (Ω) Below approximately 17 V the charge pump is actively regulating VPWR. The increased power dissipation is due to the charge pump losses. Above this voltage the charge pump oscillator shuts down and VSYS is passed through the pump diodes directly to VPWR. aaa-038781 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10 20 30 40 50 60 Supply voltage (V) Figure 23. Power dissipation profile of application not using charge pump Reference application with: • Output FET gate charge: 240 nC @ 10 V • PWM Frequency: 20 kHz • Switching Single Phase MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 45 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver • No connections to PUMP or VPUMP • VPWR connected to VSYS If VPWR is supplied by a separate preregulator, the power dissipation profile is nearly flat at the value of the preregulator voltage for all VSYS voltages. 12.2 Recommended 48 V application to other two phases +48 V nom. VSYS IN LIN REG OUT C6 +16 V nom. C2 PUMP MAIN CHARGE PUMP VPUMP VPWR 5V reg. VDD VSUP TRICKLE CHARGE PUMP VLS reg. HOLD -OFF CIRCUIT PGND VLS VDD OSCILLATOR C3 C4 UV DETECT 3x Px_BOOT T-Lim VSUP RST INT EN1 EN2 Px_HS Px_LS 1.4 V CONTROL LOGIC 3 3 CS SI SCLK SO PHASE_x HIGHSIDE desat. comp. Cx_Boot Rg_HS Px_HS_G DRIVER phase x output Px_HS_S VSUP LOWSIDE phase comp. Rg_LS Px_LS_G to motor QLS (optional) DRIVER 3 QHS (optional) phase return Px_LS_S R1 OC_OUT GND over-cur. comp. OC_TH Rsense R3 R2 I-sense amp. AMP_OUT AMP_N AMP_P VLS_CAP C5 to ADC Rfb aaa-033848 Figure 24. Recommended 48 V application diagram MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 46 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 13 Packaging 13.1 Packaging dimension For the most current package revision, visit www.nxp.com and perform a keyword search using the "98ASA00654D" listed below. Dimensions shown are provided for reference only. MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 47 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 48 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 49 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Figure 25. Package dimensions MC33GD3000 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 50 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver 14 Revision history Revision Date 1.0 4/2015 • Initial Release 5/2015 • Updated Thermal resistance value and unit in Table 3 7/2015 • Changed part number from PC to MC in the Orderable parts on page 2 8/2015 • Corrected Operating Junction Temperature value in Table 3 3.0 10/2015 • Revised VESD values in Table 3 4.0 12/2015 • Corrected upper end operating range value on page 1 • Corrected VSUP value in Table 3 5.0 6/2018 • U pdated targeted application on page 1 6.0 8/2018 • Added AEC-Q100 grade 1 qualified to general description and features list on page 1 7.0 4/2019 • Moved content from Section 8 to Section 8.1 • Added Section 8.2 8.0 9/2020 • Changed format of document to latest NXP style • Table 3 – Added PX_BOOT to HS_S – Added footnote 5, "For max ratings between any gate driver pin and VSUP when DCLINK = VSUP use VSUP max ratings. DCLINK is VSUP for this device." 9.0 10/2020 • Table 3 – Added footnote to VLS: VLS can withstand overvoltage transient of 20 V on initial power-up prior to VLS constant regulation. 10.0 3/2022 • Changed document title to "Three phase field effect transistor predriver" from "Three phase field effect transistor" 2.0 MC33GD3000 Product data sheet Description of Changes All information provided in this document is subject to legal disclaimers. Rev. 10.0 — 16 March 2022 © NXP B.V. 2022. All rights reserved. 51 / 52 MC33GD3000 NXP Semiconductors Three phase field effect transistor predriver Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 7.2.30 7.2.31 7.2.32 7.2.33 7.2.34 7.2.35 7.2.36 7.2.37 7.2.38 7.2.39 7.2.40 7.2.41 7.2.42 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Ordering information .......................................... 2 Block diagram ..................................................... 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 3 Functional descriptions ......................................5 Introduction ........................................................ 5 Functional pin description ..................................5 Phase A (PHASEA) ...........................................5 Power ground (PGND) ...................................... 5 Enable 1 and enable 2 (EN1, EN2) ................... 5 Reset (RST) .......................................................6 Charge pump out (PUMP) .................................6 Charge pump input (VPUMP) ............................6 VSUP input (VSUP) ...........................................6 Phase B (PHASEB) ...........................................6 Phase C (PHASEC) .......................................... 6 Phase A high-side input (PA_HS) ......................6 Phase A low-side input (PA_LS) ........................6 VDD Voltage Regulator (VDD) .......................... 7 Phase B high-side control input (PB_HS) .......... 7 Phase B low-side input (PB_LS) ....................... 7 Interrupt (INT) .................................................... 7 Chip select (CS) ................................................ 7 Serial in (SI) ...................................................... 7 Serial clock (SCLK) ........................................... 7 Serial out (SO) .................................................. 7 Phase C low-side input (PC_LS) ....................... 8 Phase C high-side input (PC_HS) ..................... 8 Amplifier output (AMP_OUT) ............................. 8 Amplifier inverting input (AMP_N) ......................8 Amplifier noninverting input (AMP_P) ................ 8 Overcurrent comparator output (OC_OUT) ........8 Overcurrent comparator threshold (OC_TH) ......8 Voltage source supply (VSS) .............................8 Ground (GND0, GND1) ..................................... 8 VLS regulator capacitor (VLS_CAP) ..................8 Phase C low-side source (PC_LS_S) ................9 Phase C low-side gate (PC_LS_G) ................... 9 Phase C high-side source (PC_HS_S) .............. 9 Phase C high-side gate (PC_HS_G) ................. 9 Phase C bootstrap (PC_BOOT) ........................ 9 Phase B low-side source (PB_LS_S) ................ 9 Phase B low-side gate (PC_LS_G) ................... 9 Phase B high-side source (PB_HS_S) ............ 10 Phase B high-side gate (PB_HS_G) ................10 Phase B bootstrap (PB_BOOT) .......................10 PHASE A low-side source (PA_LS_S) .............10 Phase A low-side gate (PA_LS_G) ..................10 Phase A high-side source (PA_HS_S) .............10 7.2.43 Phase A high-side gate (PA_HS_G) ................ 10 7.2.44 Phase A bootstrap (PA_BOOT) ....................... 10 7.2.45 VLS regulator (VLS) ........................................ 11 7.2.46 VPWR input (VPWR) .......................................11 7.2.47 Exposed pad (EP) ........................................... 11 8 Limiting values .................................................. 11 9 Electrical characteristics .................................. 13 9.1 Static electrical characteristics .........................13 9.2 Dynamic electrical characteristics ....................16 9.3 Timing diagrams .............................................. 19 10 Functional internal block description ............. 22 10.1 Logic inputs and interface ............................... 22 10.1.1 Low-side and bootstrap supply (VLS) .............. 23 10.1.2 Low-side drivers .............................................. 23 10.1.3 High-side drivers ..............................................24 10.1.4 Driver fault protection ...................................... 25 10.1.4.1 Current sense amplifier ................................... 25 10.1.4.2 Overcurrent comparator ...................................26 10.1.4.3 Desaturation detector ...................................... 26 10.1.4.4 Phase comparator ........................................... 28 10.1.5 VLS undervoltage ............................................ 29 10.1.6 Hold off circuit ..................................................29 10.1.7 Charge pump ...................................................29 11 Functional device operation ............................ 30 11.1 Operational modes .......................................... 30 11.1.1 Reset and enable ............................................ 30 11.2 Logic commands and registers ........................32 11.2.1 Command descriptions .................................... 32 11.2.2 Fault reporting and interrupt generation ...........33 11.2.3 NULL commands ............................................. 33 11.2.3.1 MASK command ..............................................34 11.2.3.2 Interrupt handling .............................................34 11.2.3.3 MODE command ............................................. 35 11.2.3.4 DEADTIME command ..................................... 36 11.2.4 Status registers ................................................36 11.2.4.1 Status register 0 (status latch bits) .................. 37 11.2.4.2 Status register 1 (mode bits) ........................... 38 11.2.4.3 Status register 2 (mask bits) ............................38 11.2.4.4 Status register 3 (deadtime) ............................ 38 11.3 Initialization requirements ................................ 39 11.3.1 Recovery from sleep mode (RESET) .............. 39 11.3.2 Recovery from standby mode or a fault ........... 41 11.3.3 IC initialization ................................................. 42 11.3.4 Interrupt handler .............................................. 43 12 Typical applications .......................................... 44 12.1 Typical 12 V application ...................................44 12.2 Recommended 48 V application ......................46 13 Packaging .......................................................... 47 13.1 Packaging dimension .......................................47 14 Revision history ................................................ 51 © NXP B.V. 2022. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 March 2022 Document identifier: MC33GD3000