Freescale Semiconductor
Technical Data
Document Number: MC34703
Rev. 5.0, 8/2006
10A+ Switch-Mode Power
Supply with LDO Regulator
34703
The 34703 integrated power supply IC is designed to support the
PowerQUICC™ family of MCUs as well as other MCUs and DSPs
requiring a high current core supply. The 34703 incorporates a highperformance switching regulator for the microprocessor’s core
supply, and a low-dropout (LDO) linear regulator control circuit to
provide I/O and bus voltage.
The switching regulator is an efficient synchronous buck converter
with integrated low RDS(ON) high side and low side FETs.
Temperature and current sensing is built in and provides protection
for the IC as well as the external circuitry.
The 34703 incorporates specific advanced protection features for
use with high power processors and controllers, including power-up
and power-down sequencing of the I/O and core supply voltages in
relation to each other.
INTEGRATED POWER SUPPLY IC
Features
PNB SUFFIX
98ASA10705D
33-PIN PQFN
• Wide input Operating Voltage Range: 2.8 V to 13.5 V
• Adjustable Output Voltages
• Continuous Core Voltage Supply Currents up to 10 A (with
infrequent excursions to 12 A permitted)
• Undervoltage Lockout
• Selectable Power Sequencing
• Programmable Watchdog Timer
• Voltage Margining via I2C Bus
• Overcurrent Protection
• Reset with Programmable Power-ON Delay
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34703PNB/R2
-40 to 85°C
33 PQFN
2.8 to 13.5 V
34703
VIN1
VIN2
MCU
LDRV
ISNS
LDO
VBST
VBST (sense)
VBD
VDDH (I/O)
LCMP
FREQ
SR
CLKSYN
I2C
Bus
Optional
LFB
SDA
RESET
SCL
BOOT
EN1
SW_A
EN2
SW_B
POR
VBST
VOUT
CLKSEL
COMP
PGND
VDDI
GND
ADDR
INV
RT
Figure 1. MC34703 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
VDDL (Core)
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIN1
VIN1
VDDI
VDDI
Supply
Voltage
Regulator
Vref
VBST
VBST
VBD
2
Boost
Control
Vref
VDDI
VBST
Voltage
Margining
EN2
RT
Reset
Control
RESET
Reset Watchdog Timer
INV
SysCon
POR
Timer
SR
Slew
Rate
LFB
LDRV
VDDI
Power
Sequencing
EN1
Bandgap
reference
1
Vref 3
VDDI
VBST
Powerdown
VLDO
VOUT
Linear
Regulator
Control
with
ILim
ISNS
LDO
LFB
LCMP
UVLO
Pwr Seq.
Q4
VBST
Current Limit
SR
VDDI
Buck
Control
Logic
Q1
BOOT
VIN2
SW
Q2
PGND
7
VDDI
Buck
HS
and
LS
Driver
5
5
7
0.8 V
6
INV
6
ADDR
SDA
I2C
Oscillator
Ramp
Generator
Pwr Seq.
VOUT
Q3
SCL
CLKSEL CLKSYN
FREQ
GND
COMP
Figure 2. 34703 Simplified Internal Block Diagram
34703
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
SR
LCMP
ISNS
LDO
9
10
11
13
14
15
16
17
18
19
RT
12
20
21
VOUT
RESET
8
LFB
ADDR
7
LDRV
FREQ
6
GND
SCL
5
VDDI
VIN1
4
CLKSYN
CLKSEL
3
SDA
EN2
2
EN1
VBST
1
VBST SENSE
VBD
PIN CONNECTIONS
22
INV
33
23
26
NC
(Heatsink Only)
BOOT
32
COMP
24
28
SW
27
30
SW
VIN2
29
PGND
Figure 3. 34703 Pin Connections Bottom View
Table 1. 34703 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
VBST
Input
Boost Voltage
Input for internal boost regulator. The internal boost regulator provides
8 V (at up to 45 mA current) to supply the gate drive circuits for the
integrated power MOSFETs and the external N-channel power MOSFET
of the linear regulator.
2
EN2
Input
Enable Pin 2
Enable 2 Input. The combination of the logic state of the Enable 1 and
Enable 2 inputs determine operation mode and type of power sequencing
of the IC.
3
CLKSEL
Input/Output
Clock Selection
This pin sets the CLKSYN pin either as an oscillator output or
synchronization input pin. The CLKSEL pin is also used for the I2C
address selection.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34703 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
4
VIN1
Input
Input Voltage 1
The input supply pin for the integrated circuit. The internal circuits of the
IC are supplied through this pin.
5
SCL
Input
Serial Clock
6
FREQ
Input
Oscillator Frequency
The switcher oscillator frequency can be adjusted by connecting an
external resistor RF to the FREQ pin. The default switching frequency
(FREQ pin left open or tied to VDDI) is ~300 kHz.
7
ADDR
Input
Address
I2C address selection. This pin can be either left open, tied to VDDI, or
grounded through a 10 kΩ resistor.
8
RESET
Output
Reset
9
LCMP
Input
Linear Compensation
10
ISNS
Input
Current Sense
Current sense pin of the LDO to provide overcurrent protection of the
linear regulator’s external power MOSFET. The voltage drop over the
LDO current sense resistor RS is sensed between the ISNS and the LDO
pins. The LDO current limit can be adjusted by selecting the proper value
of the current sense resistor RS.
11
LDO
Input
Linear Regulator
Input pin of the linear regulator power sequence and current limit control
circuits.
12
VBD
Output
Boost Voltage Drain
Drain of the internal boost regulator's switching power MOSFET.
VBST
Input
Boost Voltage Sense
Note, this pin must be connected to VBST (pin 1) and is not intended to
provide power to external circuitry.
Enable 1 Input. The combination of the logic state of the Enable 1 and
Enable 2 inputs determine operation mode and type of power sequencing
of the IC.
13
SENSE
I2C bus pin. Serial clock.
The Reset pin indicates to the external circuitry when one of the
regulators protection features has been activated. Note, since it is an
open drain output it has to be pulled up to some supply voltage (e.g., the
output of the LDO) by an external resistor.
Linear regulator compensation pin.
14
EN1
Input
Enable Pin 1
15
SDA
Input/Output
Serial Data
16
CLKSYN
Input/Output
Clock Sync Input/
Oscillator Output
Oscillator synchronization input pin or oscillator output pin. The CLKSYN
pin can be configured either as an oscillator output when the CLKSEL pin
is left open or it can be used as a synchronization input when the CLKSEL
pin is grounded.
17
VDDI
Passive
Vdd Filter
Internal supply voltage capacitor pin. A ceramic low ESR 1.0 µF capacitor
in parallel with a ceramic 100nF capacitor should be connected from this
pin to ground. The VDDI power supply voltage is for internal use only; do
not use externally.
18
GND
Signal
Ground
19
RT
Passive
Reset Timer
20
LDRV
Output
LDO Gate Drive
LDO gate drive of the external pass N-channel MOSFET.
21
LFB
Input
LDO Feedback
Linear regulator feedback pin.
22
VOUT
Output
Output Voltage Power
Sequencing Control
23
INV
Input
Error Amp
24
COMP
Input
Switcher
Compensation
I2C bus pin. Serial data.
Analog ground of the IC.
This pin allows programming the Power-ON Reset delay by means of an
external RC network.
This pin must be directly connected to the output voltage of the buck
converter. This pin controls the buck regulators output voltage (Vout) in
accordance with the power sequencing control mode set by EN1 and
EN2.
Buck Controller Error Amplifier inverting input.
Buck converter compensation pin.
34703
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. 34703 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number
Pin Name
Pin Function
Formal Name
25, 31
Definition
These pins are not present in package.
26
NC
Heatsink
No electrical connection, thermal heatsinking only.
27, 28
SW
Output
Switch
29
PGND
Power
Power Ground
Buck regulator and Power Sequencing shunt FETs Power Ground.
30
VIN2
Input
Input Voltage 2
Buck regulator power input. Drain of the high-side power MOSFET.
32
BOOT
Input
Bootstrap
Bootstrap capacitor input.
33
SR
Passive
Slew Rate
Buck converter Slew Rate control pin.
Buck regulator switching node. This pin is connected to the high power
inductor.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Supply Voltage
VIN1, VIN2
-0.3 to 14
V
Switching Node
SW
-1.0 to 14
V
BOOT
-0.3 to 8.5
V
VSR
-0.3 to 8.5
V
VBST
-0.3 to 8.5
V
Boost Regulator Drain
VBD
-0.3 to 9.5
V
RESET Drain Voltage
RESET
-0.3 to 7.0
V
Enable Pins (EN1, EN2)
VENABLE
-0.3 to 14
V
VLOGIC
-0.3 to 7.0
V
Analog Pins (INV, VOUT)
VANALOG1
-0.3 to 7.0
V
Analog Pins (LDRV, LFB, LDO, LCMP, ISNS)
VANALOG2
-0.3 to 8.5
V
Analog Pins (CLKSEL, ADDR, RT, FREQ, VDDI)
VANALOG3
-0.3 to 3.6
V
Human Body Model (2)
VESD1
±2000
Machine Model (3)
VESD2
±200
TSTG
-65 to 150
°C
PD
2.0
W
TSOLDER
245
°C
TJMAX
125
°C
TA
-40 to 85
°C
RθJA
38
°C/W
RθJB
~1.0
°C/W
ELECTRICAL RATINGS
Buck Regulator Bootstrap Input (BOOT - SW)
Differential Voltage (SR - SW)
Boost Regulator Output
(1)
Logic Pins (SDA, SCL, CLKSYN)
ESD Voltage
V
THERMAL RATINGS
Storage Temperature
Power Dissipation (TA = 85°C) (4)
Lead Soldering Temperature (5)
Maximum Operating Junction Temperature
Package Operating Temperature Range (Ambient Temperature)
THERMAL RESISTANCE
Thermal Resistance, Junction to Ambient (6)
Thermal Resistance, Junction to Base
(7)
Notes
1. Maximum recommended filter capacitor: 10 µF. (Note, VBST pin is not short-circuit protected.)
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
3.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4.
Maximum still-air power dissipation at indicated ambient temperature; higher power dissipations may be possible with additional heatsinking and forced-air cooling.
Lead soldering temperature limit is for 10 seconds maximum duration. Contact Freescale Sales Office for immersion soldering time/
temperature limits.
Thermal resistance measured in accordance with EIA/JESD51-2.
Theoretical thermal resistance from the die junction to the exposed heat-sinking pins.
5.
6.
7.
34703
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions -40°C ≤ TJ ≤ 85°C unless otherwise noted. Input voltages 2.8 V ≤ VIN ≤ 13.5 V. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Operating Voltage Range (VIN1, VIN2)
VIN
2.8
–
13.5
V
Start-Up Voltage Threshold (Boost Switching)
VST
–
1.6
1.8
V
VBST Undervoltage Lockout (Internal use only)
VBSTUVLO
5.5
6.0
6.5
V
Input DC Supply Current (Normal Operation Mode, Enabled) (8)
IIN
–
60
–
mA
VIN1 Pin Input Supply Current (EN1 = EN2 = 0) (8)
IIN1
–
13
–
mA
VIN2 Pin Input Leakage Current (EN1 = EN2 = 0) (8)
IIN2
–
100
–
µA
Output Voltage (11)
VOUT
10% VIN
–
5.0
V
Output DC Current (10) (11)
IOUT
0.1
–
12
A
GENERAL (VIN1, VIN2, VBST, VDDI) (9)
BUCK CONVERTER (INV, VOUT)
Buck Converter Feedback Voltage
VINV
IVOUT = 100 mA to 10 A, VIN1 = VIN2 = 2.8 V to 13.5 V.
No RB Resistor. Includes Load Regulation Error
Buck Converter Voltage Margining Step
Buck Converter Line Regulation
(12)
VMVO
0.8
0.816
–
1.0
–
-1.0
–
1.0
-2.0
–
2.0
1.7
4.6
7.5
–
–
25
–
–
10
%
IVOUTLK
VOUT = 5.0 V
High-Side Power MOSFET Q1 RDS(ON) (10)
Low-Side Power MOSFET Q2 RDS(ON) (10)
mA
RDS(ON)
ID = 1.0 A, TA = 25°C, VBST = 8.0 V
mΩ
RDS(ON)
ID = 1.0 A, TA = 25°C, VBST = 8.0 V
%
%
REGLDVO
IVOUT = 100 mA to 10 A
VOUT Input Leakage Current
0.784
REGLNVO
VIN1 = VIN2 = 2.8 V to 13.5 V, IVOUT = 10 A
Buck Converter Load Regulation (12)
V
mΩ
Buck Converter Peak Current Limit (High Level)
IHLIM
12
15
19
A
Buck Converter Valley Current Limit (Low Level)
ILLIM
6.0
7.5
9.0
A
VOUT Internal Pull-Down MOSFET Current Limit
IQ3LIM
0.75
1.7
2.0
–
–
3.0
TSD
150
170
190
°C
TSDHys
–
15
–
°C
TA = 25°C, VBST = 8.0 V
VOUT Internal Pull-Down MOSFET RDS(ON)
Thermal Shutdown Hysteresis
(12)
Ω
Q3RDS(ON)
ID = 1.0 A, TA = 25°C, VBST = 8.0 V
Thermal Shutdown (12)
A
Notes
8. Not production tested; typical values for reference only.
9. VDDI is an internal supply voltage. It should not be used for any external purpose.
10.
11.
Design information only; not production tested.
Minimum output voltage can be adjusted to 0.8 V when VIN < 8 V. Maximum currents subject to sufficient heat-sinking.
12.
Guaranteed by design.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions -40°C ≤ TJ ≤ 85°C unless otherwise noted. Input voltages 2.8 V ≤ VIN ≤ 13.5 V. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
RIN
–
14
–
MΩ
ROUT
–
1.4
–
kΩ
AVOL
–
80
–
dB
GBW
–
4.0
–
MHz
SR
–
2.0
–
V/µs
–
2.0
–
–
0.4
–
VSCRAMP
–
0.6
–
V
Oscillator Low-Level Output Voltage (CLKSYN Pin),
CLKSEL Open
VOSCOL
–
0.1
0.4
V
Oscillator High-Level Output Voltage (CLKSYN Pin),
CLKSEL Open (14)
VOSCOH
2.7
–
3.3
V
Oscillator Input Voltage Threshold (CLKSYN Pin),
CLKSEL Grounded
VOSCIH
1.2
1.6
2.0
V
Oscillator Frequency Adjusting Reference Voltage (FREQ) (16)
VFREQ
1.15
1.27
1.35
V
RFREQ
5.0
–
20
kΩ
7.5
8.0
8.5
7.5
8.0
8.8
VINBSU
–
1.6
1.8
V
Boost Regulator Peak Current Limit (Power FET Peak Current)
IPBD
0.75
1.0
1.5
A
Boost Regulator Power FET Valley Current Limit (Low Level)
ILBD
550
600
900
mA
–
900
–
CBST
–
10
–
µF
ESRCBST
–
–
100
mΩ
BUCK ERROR AMPLIFIER (INV, COMP)
Input Impedance (13)
Output Impedance
(13)
DC Open Loop Gain
(13)
Gain Bandwidth Product
Slew Rate
(13)
(13)
Output Voltage Swing – High Level
VEAOH
VIN1 > 3.3 V, IOEA = -400 mA (13)
Output Voltage Swing – Low Level
V
VEAOL
IOEA = 400 mA (13)
Slope Compensation Ramp (13)
V
OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Resistor Range
(16)
BOOST REGULATOR (VBST, VIN)
Boost Regulator Output Voltage
VBST
IBST = 20mA, VIN1 = VIN2 = 2.8 V to 8.0 V
Boost Regulator Output Voltage(15)
VBST(VGREG)
IBST = 20mA, VIN1 = VIN2 > 8.0V
Boost Regulator Start-Up Voltage
Boost Power FET RDS(ON)
(16)
Boost Regulator Recommended Output Capacitor Maximum ESR
V
RDS(ON)
IBST = 500 mA, VIN1 = VIN2 = 13.5V
Boost Regulator Recommended Output Capacitor
V
mΩ
Notes
13. Design information only. It is not production tested.
14. All internal high level voltages are reference to the VDDI voltage.
15. When the input is above 8 V an integrated linear regulator will provide VBST; under this configuration the external inductor must be
removed and the VBD pin left open (floating).
16. Guaranteed by design.
34703
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions -40°C ≤ TJ ≤ 85°C unless otherwise noted. Input voltages 2.8 V ≤ VIN ≤ 13.5 V. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.8
–
4.5
Unit
LINEAR REGULATOR (LDO, ISNS, LDRV, LFB) (17)
LDO Output Voltage Range (17)
VLDO
VIN1 = VIN2 = 2.8 V to 13.5 V, ILDO = 100 mA to 2000 mA
LDO Feedback Voltage, LFB Pin Connected to LDO Pin
V
VLDO
VIN1 = VIN2 = 2.8 V to 13.5 V, ILDO = 100 mA to 2000 mA. Includes
Load Regulation Error
LDO Voltage Margining Step Size
VMLDO
LDO Line Regulation
V
0.784
0.8
0.816
–
1.0
–
-1.0
–
1.0
-1.0
–
1.0
REGLNVLDO
VIN1 = VIN2 = 2.8 V to 13.5 V, ILDO = 1000 mA
LDO Load Regulation
%
REGLDVLDO
ILDO = 100 mA to 2000 mA
LDO Ripple Rejection, Dropout Voltage VDO = 1.0 V,
VRIPPLE = +1.0 V p-p (18)
%
VLDORR
Sinusoidal, f = 300 kHz, ILDO = 500 mA
%
dB
–
26
–
–
50
–
VCSTH
35
45
65
mV
LDO Pin Input Current
ILDO
1.0
2.0
4.0
mA
LDO Feedback Input Current (LFB Pin)
ILFB
-1.0
0.04
1.0
µA
LDO Drive Output Current (LDRV Pin)
ILDRV
2.0
4.0
5.0
mA
IDRLIM
–
3.6
–
mA
50
125.0
200
RIN
–
10
–
ΜΩ
ROUT
–
60
–
Ω
0.75
1.7
2.0
–
–
3.2
CLDO
–
10
–
µF
ESRCLDO
–
100
–
mΩ
TSD
150
170
190
°C
TSDHYS
–
15
–
°C
tSS
–
800
–
µs
LDO Maximum Dropout Voltage (VIN - VLDO)
(18)
VDO
VLDO = 2.5 V, ILDO = 2000 mA
LDO Current Sense Comparator Threshold Voltage (VCS - VLDO)
LDO Drive Current Limit (LDRV Pin)
(18)
ISNS Pin Input Leakage Current
LDO Error Amplifier Input Impedance (LFB Pin) (18)
LDO Error Amplifier Output Impedance (LCMP Pin)
(18)
LDO Internal Pull-Down MOSFET Current Limit
IQ4LIM
TA = 25°C, VBST = 8.0 V (LDO Pin)
LDO Internal Pull-Down MOSFET RDS(ON)
A
Ω
Q4RDS(ON)
ID = 1.0 A, TA = 25°C, VBST = 8.0 V
LDO Recommended Output Capacitance
LDO Recommended Output Capacitor ESR
Thermal Shutdown Hysteresis
µA
ISNSLK
VISNS = 5.0 V
Thermal Shutdown (LDO Pull-Down FET Q4)
mV
(19)
(19)
Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1)
(18)
Notes
17. The LDO output range is given for the MOSFET as depicted on Figure 33. Should the customer select another MOSFET, It is the
customer’s responsibility to properly select the MOSFET given the expected power dissipation, voltage drop across it and any other
constraint that could impact the MOSFET reliability and range of work.
18. Not production tested for typical values specified.
19. Guaranteed by design.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions -40°C ≤ TJ ≤ 85°C unless otherwise noted. Input voltages 2.8 V ≤ VIN ≤ 13.5 V. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VTHEN
1.2
1.6
2.0
V
VIHYS
–
0.1
–
V
Enable (EN1, EN2) Pull-Down Resistance
RPU
30
60
90
kΩ
RESET Low-Level Output Voltage, IOL = 5.0 mA
VOL
–
0.1
0.4
V
ILKGRST
–
–
10
µA
VOUTI TH
-12
-7.5
-4.0
%
VOUTI TH
4.0
7.5
12
%
VLDOI TH
-12
-7.5
-4.0
%
VLDOI TH
4.0
7.5
12
%
VTHRT
0.8
1.2
1.5
V
ISRT
17
25
34
mA
VSATRT
–
45
100
mV
CT
–
–
33
µF
CLKSEL Threshold Voltage
VTHCLKS
1.2
1.6
2.0
V
CLKSEL Pull-Up Resistance
RPUCLKS
60
120
240
kΩ
ADDR Threshold Voltage
VTHADDR
1.2
1.6
2.0
V
ADDR Pull-Up Resistance
RPUADDR
60
120
240
kΩ
VITH
1.3
–
1.7
V
VIHYS
–
0.2
–
V
II
–
–
10
µA
VOL
–
–
0.4
V
CI
–
–
10
pF
CONTROL AND SUPERVISORY CIRCUITS (EN1, EN2, RESET, CLKSEL, ADDR, RT)
Enable (EN1, EN2) Input Voltage Threshold
(21)
Enable (EN1, EN2) Input Voltage Threshold Hysteresis
RESET Leakage Current, OFF State, Pulled Up to 5.0 V
RESET Undervoltage Threshold on VOUT (∆VOUT/VOUT)
RESET Overvoltage Threshold on VOUT (∆VOUT/VOUT)
(20)
RESET Undervoltage Threshold on VLDO (∆VLDO/VLDO)
RESET Overvoltage Threshold on VLDO (∆VLDO/VLDO)
RT Voltage Threshold
RT current source
RT Saturation Voltage, Reset Timer Current = 300 µA
Maximum Value of the RT Capacitor
I2 C
(20)
(20)
(20)
Bus (SDA, SCL)
Input Threshold Voltage
Input Voltage Threshold Hysteresis
(21)
SDA, SCL Input Current, Input Voltage = 0.4 V to 5.5 V
SDA Low-Level Output Voltage, 3.0 mA Sink Current
SDA, SCL Capacitance
Notes
20. This parameter does not include the tolerance of the external resistor divider.
21. Not production tested for typical values specified.
34703
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using
the typical application circuit (see Figure 27) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
D
10
–
90
%
–
10
–
–
10
–
–
14
–
–
14
–
–
6.0
–
–
6.0
–
–
150
–
BUCK CONVERTER (SW, SR)
Duty Cycle Range (Normal Operation) (22)
Switching Node SW Rise Time
(22)
tROPEN
ILOAD = 10 A, SR = OPEN, VIN1 = VIN2 = 3.3 V
Switching Node SW Fall Time (22)
tFOPEN
ILOAD = 10 A, SR = OPEN, VIN1 = VIN2 = 3.3 V
Switching Node SW Rise Time (22)
Switching Node SW Fall Time (22)
ns
tFSW
ILOAD = 10 A, SR = SW, VIN1 = VIN2 = 3.3 V
Switching Node SW Rise Time (22)
ns
tRBOOT
ILOAD = 10 A, SR = BOOT,VIN1 = VIN2 = 3.3 V
Switching Node SW Fall Time (22)
ns
tFBOOT
ILOAD = 10 A, SR = BOOT, VIN1 = VIN2 = 3.3 V
Maximum Deadtime (22)
tD
(22)
ns
tPD
VINV < 0.8 V to VSW > 90% of High Level or VINV > 0.8 V to VSW < 10%
of Low Level
Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1)
Fault Condition Timeout
ns
tRSW
ILOAD = 10 A, SR = SW, VIN1 = VIN2 = 3.3 V
Buck Control Loop Propagation Delay
ns
(22)
(22)
ns
ns
–
tSS
50
–
µs
800
tFAULT
–
10
–
ms
tRET
–
100
–
ms
Oscillator Default Frequency (Switching Frequency), FREQ Pin Open
fOSC
250
300
350
kHz
Oscillator Frequency Range
fOSC
200
400
kHz
Oscillator Output Signal Duty Cycle (Square Wave, 180° Out-of-Phase with
the Internal Suitable Oscillator) (23)
DOSC
Synchronization Pulse Minimum Duration (22)
Retry Timer Cycle
(22)
OSCILLATOR (FREQ)
%
–
50
–
tSYNC
300
–
–
ns
tON
–
24
–
µs
tBSTPD
–
50
–
ns
–
35
–
–
5.0
–
BOOST REGULATOR (VBST, VBST (sense), VBD)
Boost Regulator FET Maximum ON Time (23)
Boost Regulator Control Loop Propagation Delay
Boost Switching Node VBD Rise Time
(22)
(22)
tBR
IBST = 45 mA
Boost Switching Node VBD Fall Time (22)
IBST = 45 mA
ns
tBF
ns
Notes
22. Design Information only. Not production tested.
23. Not production tested for typical values specified.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using
the typical application circuit (see Figure 27) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ISR
–
2.5
–
A/µs
tFAULT
–
10
–
ms
tRET
–
100
–
ms
fSCL
–
–
100
kHz
tBUF
4.7
–
–
µs
4.0
–
–
LINEAR REGULATOR (LDO)
Output Current Slew Rate (24)
Fault Condition Timeout
Retry Timer Cycle
(24)
(24)
2
PIN, I C BUS (SDA, SCL)
SCL Clock Frequency (25)
Bus Free Time Between a STOP and a START Condition
(25)
Hold Time (Repeated) START Condition (After this period, the first clock
pulse is generated.) (25)
µs
tHDSTA
Low Period of the SCL Clock (25)
tLOW
4.7
–
–
µs
(25)
tHIGH
4.0
–
–
µs
–
–
250
tSUSTA
4.7
–
–
µs
tHDDAT
0.0
–
–
µs
tSUDAT
250
–
–
ns
tSUSTO
4.0
–
–
µs
CB
–
–
400
pF
High Period of the SCL Clock
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to
400 pF, 3.0 mA Sink Current (25)
Setup Time for a Repeated START Condition (25)
Data Hold Time for
Data Setup Time
I2 C
bus devices
(25), (26)
(25)
Setup Time for STOP Condition
(25)
Capacitive Load for Each Bus Line
(25)
tF
ns
Notes
24. Not production tested for typical values specified.
25. Design Information only. Not production tested.
26. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
34703
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
tHDSTA
tHDSTA
tSUSTA
tHDDAT
tSUDAT
tSUSTO
SR
Figure 4. Definition of Time on the I2C Bus
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
370
365
360
355
350
345
340
335
330
325
320
-50
1.00
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
-60
Output Voltage
Regulation (%)
FOSC
fOSC (KHz)
ELECTRICAL PERFORMANCE CURVES
0
50
100
-10
TA C° Degree
Quiescent Current (mA)
Efficiency (%)
Figure 8. Buck Converter Voltage Regulation vs
Ambient Temperature
Vin=7V,
Vo=5V
Vin=7.0V,
Vout
=5.0V
92
90
88
86
84
82
80
0
2
4
6
90
TA C° Degree
Figure 5. fOSC vs Ambient Temperature
94
40
8
10
100
Vo=3.3V
Vout
=3.3V
80
60
40
20
0
0
12
5
10
15
Input Voltage (V)
Load Current (A)
Figure 6. Efficiency vs Load Current
Figure 9. Quiescent Current vs Input Voltage
0.15
400
0.10
fosc (KHz)
Voltage Regulation (%)
0.20
0.05
0.00
-0.05
350
300
-0.10
-0.15
250
-0.20
8
0
2
4
6
8
10
12
9
10
11
12
13
R
RFF Value (kΩ
0 )
Load Current (A)
Figure 7. Buck Converter Voltage Regulation
vs Load Current
Figure 10. RF vs Frequency
(RF is R1 in the application schematic on page 34)
34703
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34703 power supply integrated circuit is an efficient
means to supply the PowerQUICC and other families of
Freescale microprocessors. It incorporates a highperformance synchronous buck regulator, supplying the
microprocessor’s core, and a low dropout (LDO) linear
regulator providing the microprocessor I/O and bus voltages.
This device incorporates many advanced features
including up/down power sequencing, undervoltage lock-out,
current shut-down limit, and temperature shut-down limit, to
ensure proper operation and protection of the CPU and
power system. The device can be configured to support
different voltages and modes of operation, permitting the
functions to be tailored to the specific application.
FUNCTIONAL PIN DESCRIPTION
BOOST VOLTAGE PIN (VBST)
OSCILLATOR FREQUENCY PIN (FREQ)
Internal boost regulator output voltage. The internal boost
regulator provides a 45 mA output current to supply the drive
circuits for the integrated power MOSFETs and the external
N-channel power MOSFET of the linear regulator. The
voltage at the VBST pin is 8.0 V nominal.
This switcher frequency selection pin can be adjusted by
connecting external resistor RF to the FREQ pin. The default
switching frequency (FREQ pin left open or tied to VDDI) is
~300 kHz.
ENABLE 1 AND 2 PINS (EN1 AND EN2)
The ADDR pin is used to set the address of the device
when used in an I2C communication. This pin can either be
tied to VDDI or grounded through a 10 kΩ resistor. Refer to
I2C Bus Operation on page 25 for more information on this
pin.
These two pins permit positive logic control of the Enable
function and selection of the Power Sequencing mode
concurrently. Table 5 depicts the EN1 and EN2 function and
Power Sequencing mode selection.
Both EN1 and EN2 pins have internal pulldown resistors
and both can withstand a short circuit to the supply voltage,
13.5 V.
Table 5. Operating Mode Selection
EN1
EN2
Operating Mode
0
0
Regulators Disabled
0
1
Standard Power Sequencing
1
0
Inverted Power Sequencing
1
1
No Power Sequencing,
Regulators Enabled
CLOCK SELECTION PIN (CLKSEL)
This pin sets the CLKSYN pin as either an oscillator output
or a synchronization input pin. The CLKSEL pin is also used
for the I2C address selection.
INPUT VOLTAGE 1 PIN (VIN1)
The input supply pin for the integrated circuit. The internal
circuits of the IC are supplied through this pin.
ADDRESS PIN (ADDR)
RESET OUTPUT PIN (RESET)
The Reset Control circuit monitors both the switching
regulator and the LDO feedback voltages. It is an open drain
output and has to be pulled up to the logic supply voltage
(e.g., the output of the LDO) by an external resistor.
The Reset Control circuit supervises both output
voltages—the linear regulator output VLDO and the switching
regulator output VOUT. When either of these two regulators
is out of regulation (high or low), the RST pin is pulled low.
There is a 20 µs internal delay filter preventing erroneous
resets. During power-up sequencing, RST is held low until the
Reset Timer times out.
LINEAR COMPENSATION PIN (LCMP)
Linear regulator compensation pin.
CURRENT SENSE PIN (ISNS)
Current sense pin of the LDO. Overcurrent protection of
the linear regulator external power MOSFET. The voltage
drop over the LDO current sense resistor RS is sensed
between the ISNS and LDO pins. The LDO current limit can
be adjusted by selecting the proper value of the current
sensing resistor RS.
SERIAL CLOCK PIN (SCL)
I2C bus pin. Serial clock.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
LINEAR REGULATOR PIN (LDO)
Input pin of the linear regulator power sequence control
circuit.
LINEAR FEEDBACK PIN (LFB)
Linear regulator feedback pin.
OUTPUT VOLTAGE PIN (VOUT)
BOOST DRAIN PIN (VBD)
Drain of the internal boost regulator power MOSFET.
VBST (SENSE)
Sense pin of the internal boost regulator output voltage.
SERIAL DATA PIN (SDA)
I2C bus pin. Serial data.
CLOCK SYNCHRONIZATION PIN (CLKSYN)
Oscillator output/synchronization input pin.
Output voltage of the buck converter. Input pin of the
switching regulator power sequence control circuit.
ERROR AMP INVERTING INPUT PIN (INV)
Buck Controller Error Amplifier inverting input.
BUCK SWITCHER COMPENSATION (COMP)
Output voltage of the buck converter error amplifier.
Compensation pin.
SWITCH PINS (SW)
Buck regulator switching node. This pin is connected to the
inductor.
VDD FILTER PIN (VDDI)
Internal Logic Supply Voltage Pin: a low-ESR 1.0 µF 6.0 V
capacitor must be connected between this pin and signal
ground.
POWER GROUND PINS (PGND)
Buck regulator power ground.
INPUT VOLTAGE 2 PINS (VIN2)
RESET TIMER PIN (RT)
The Reset Timer power-up delay (RT) pin is used to set
the delay between the time when the LDO and switcher
outputs are active and stable and the RST output is released.
An external resistor and capacitor are used to program the
timer. The power-up delay can be obtained by using the
following formula:
t D ~ 10 ms + R tC t
Where R t is the Reset Timer programming resistor and C t
is the Reset Timer programming capacitor, both connected in
parallel from RT to ground.
Buck regulator power input. Drain of the high-side power
MOSFET.
BOOTSTRAP PIN (BOOT)
Bootstrap capacitor input.
SWITCHER SLEW RATE CONTROL (SR)
Buck slew rate control pin. For faster Slew Rates, connect
the pin to the boot pin (Boot). For medium speeds, the pin
should be left open. For slowest options, connect the pin to
the Switch Pin (SW).
LINEAR DRIVE PIN (LDRV)
LDO gate drive of the external pass N-channel MOSFET.
34703
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INTRODUCTION
The paragraphs below describe the functional sub-circuits
of the 34703 integrated power supply IC.
Figure 11. 34703 Functional Internal Block Diagram
BOOST REGULATOR
A boost regulator provides a high voltage necessary to
properly drive the buck regulator power MOSFETs,
especially during the low input voltage condition. The LDO
regulator external N-channel MOSFET gate is also powered
from the boost regulator. In order to properly enhance the
high-side MOSFETs when only a +3.3 V supply rail powers
the integrated circuit, the boost regulator provides an output
voltage of 8.0 V nominal value.
The 34703 boost regulator uses a simple hysteretic
current control technique, which allows fast power-up and
does not require any compensation. When the boost
regulator main power switch (low side) is turned on, the
current in the inductor starts to ramp up. After the inductor
current reaches the upper current limit (nominally set at
1.0 A), the low-side switch is turned off and the current
charges the output capacitor through the internal rectifier.
When the inductor current falls below the valley current limit
value (nominally 600 mA), the low-side switch is turned on
again, starting the next switching cycle. After the boost
regulator output capacitor reaches its regulation limit, the lowside switch is turned off until the output voltage falls below the
regulation limit again.
NOTE: Should the input voltage be higher than 8.0 V,
an internal linear regulator provides the required boost
voltage. In this configuration the external boost inductor
must be removed and the VBD pin left floating!
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
7.75V
Booster Output Voltage
Fault Timer
t FAULT = 10 ms
t FAULT = 10 ms
I pk Cu rrent Limit
Ip k
6.0 V
0.5 I pk
0.5 Ipk
Retry Timer
t Ret = 10 0 ms
0A
Figure 13. Switching Regulator Current Limit
(Not To Scale)
0V
Ipk = 1 A typ.
Booster Inductor Current
0.6 A typ.
0.2 A typ.
0.1 A typ.
Figure 12. Boost Regulator Startup (Not To Scale)
BUCK REGULATOR
The buck regulator is a high-frequency (300 kHz default,
adjustable in the range from 200 kHz to 400 kHz),
synchronous buck converter driving integrated high-side and
low-side N-channel power MOSFETs. The buck regulator
output voltage is adjustable by means of an external resistor
divider to provide the required output voltage. Its high current
ouput is well suited for directly powering the core of the
microprocessor.
A typical bootstrap technique is used to provide the
voltage necessary to properly enhance the high-side
MOSFET gate. However, when the regulator is supplied from
a low-input voltage (e.g., a +3.3 V supply rail), the bootstrap
capacitor is charged from the internal boost regulator output
VBST through an external diode. This arrangement allows the
34703 to operate efficiently even from a very low input
voltage source.
In order to avoid destruction of the supplied circuits, a
current limit with retry capability was implemented in the buck
regulator. When an overcurrent condition occurs and the
switch current reaches the peak current limit value, the main
(high-side) switch is turned off until the inductor current
decays to the valley value, which is one-half of the peak
current limit. If an overcurrent condition exists for 10 ms, the
buck regulator control circuit shuts the switcher OFF and the
switcher retry timer starts to time out. When the timer expires
after 100 ms, the switcher engages the start-up sequence
and runs for 10 ms, repeatedly checking for the overcurrent
condition. During the current limited operation (e.g., in case
of short circuit on the buck regulator output), the buck
regulator operation is not synchronized to the oscillator
frequency.
The buck regulator output voltage can be adjusted from
0.8 V to 5.0 V. Power-up, power-down, and fault
management are coordinated with the linear regulator.
Figure 14. Buck Converter Overcurrent Protection
34703
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
timer expires after 100 ms, the LDO tries to power up again
for 10 ms, repeatedly checking for the overcurrent condition.
The current limit of the LDO is determined by the
following formula:
ILIM = 45 mV / RS
Where RS is the LDO current sense resistor, connected
between the ISNS pin and the LDO pin output (see
Figure 27).
The output voltage of the LDO can be adjusted by means
of an external resistor divider connected to the feedback
control pin LFB. The linear regulator output voltage can be
adjusted in the range of 0.8 V to 5.0 V, but the LDO output
voltage is always lower than the input voltage to the regulator.
Power-up, power-down, and fault management are
coordinated with the switching regulator.
THERMAL SHUTDOWN
Figure 15. LDO Converter Overcurrent Protection
SWITCHING OSCILLATOR
A 300 kHz (default) oscillator sets the switching frequency
of the buck regulator. The frequency of the oscillator can be
adjusted between 200 kHz and 400 kHz by an optional
external resistor RF connected from the FREQ pin of the
integrated circuit to ground. See Figure 10 for frequency
resistor selection.
The CLKSYN pin can be configured either as an oscillator
output when the CLKSEL pin is left open or it can be used as
a synchronization input when the CLKSEL pin is grounded.
The oscillator output signal is a square wave logic signal with
50 percent duty cycle, 180 degrees out-of-phase with the
internal clock signal. This allows opposite phase
synchronization of two 3370x devices.
When the CLKSYN pin is used as synchronization input
(CLKSEL pin grounded), the external resistor RF chosen from
the chart in Figure 10 should be used to synchronize the
internal ramp generator to the external clock. Operation is
only recommended between 200 kHz and 400 kHz. The
supplied synchronization signal does not need to be
50 percent duty cycle. Minimum pulse width is 300 ns.
LOW DROPOUT LINEAR REGULATOR (LDO)
The adjustable low dropout linear regulator (LDO) is
capable of supplying up to a 2.0 A output current. It has a
current limit feature with retry capability.
Current limiting is implemented via a sense resistor that
feeds back a small voltage to the ISNS pin. When the sense
resistor is used, the control circuit limits the current for 10 ms
when the voltage measured across the current sense resistor
reaches a 45 mV threshold. If the overcurrent condition still
exists after the 10ms time period, the linear regulator is
turned off. At the same time the overcurrent condition is
detected, the Retry Timer starts to count down. When the
In order to increase the overall safety of the system
designed with the 34703, an internal thermal shutdown
function has been incorporated into the switching regulator
circuit. The 34703 senses the temperature of the buck
regulator main switching FET (high-side FET Q1; see
Figure 2), the low-side (synchronous FET Q2), and control
circuit. If the temperature of any of the monitored components
exceeds the limit of safe operation (thermal shutdown), the
switching regulator will be shut down. After the temperature
falls below the value given by the thermal shutdown
hysteresis window, the switcher will retry to operate again.
The VOUT/LDO pull-down FETs Q3/Q4 have an
independent thermal shutdown control. When the Q3/Q4
temperature exceeds the thermal shutdown limit, Q3/Q4 will
be turned off without affecting the switcher operation.
The maximum junction temperature is 125°C and thermal
shutdown is 170°C. It is not recommended to operate this IC
beyond these thresholds.
WATCHDOG TIMER
A watchdog function is available via I2C bus
communication. It is possible to select either window
watchdog or time-out watchdog operation, as illustrated in
Figure 16.
Watchdog time-out starts when the watchdog function is
activated via I2C bus sending a Watchdog Programming
command byte, thus determining watchdog operation
(window or time-out) and period duration (refer to Table 6). If
the watchdog is cleared by receiving a new Watchdog
Programming command through the I2C bus, the watchdog
timer is reset and the new time-out period begins. If the
watchdog time expires, the RESET will become active (LOW)
for a time determined by the RC components of the RT timer
plus 10 ms. After a watchdog time-out, the function is no
longer active.
When the Window Watchdog function is selected, the
timer cannot be cleared during the Closed Window time,
which is 50% of the total watchdog period. When the
watchdog is cleared, the timer is reset and starts a new time-
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
out period. If the watchdog is not cleared during the Open
Window time, the RESET will become active (LOW) for a time
determined by the RC components of the RT timer plus
10 ms.
Watchdog Closed
No Watchdog Clear Allowed
Window Open
for Watchdog Clear
Table 6. Watchdog Programming Command Byte
(as a 2nd Command Byte)
Address
Value
Action
0
1
1
0
0
0
0
0
1st Command
0
1
1
0
0
0
0
0
WD OFF (27)
0
1
1
0
1
0
0
0
WD 1280 ms
WinOFF
50% of Watchdog Period
0
1
1
0
1
0
0
1
WD 320 ms WinOFF
Watchdog Period
Timing Selected via I2C Bus – See Table 1
0
1
1
0
1
0
1
0
WD 80 ms WinOFF
Window Watchdog
0
1
1
0
1
0
1
1
WD 20 ms WinOFF
0
1
1
0
1
1
0
0
WD 1280 ms WinON
0
1
1
0
1
1
0
1
WD 320 ms WinON
0
1
1
0
1
1
1
0
WD 80 ms
WinON
0
1
1
0
1
1
1
1
WD 20 ms
WinON
Window Open for Watchdog Clear
Watchdog Period
Timing Selected via I2C Bus – See Table 1
Time-Out Watchdog
Figure 16. Watchdog Operation
Notes
27. The Watchdog feature will be turned ON
automatically after receiving any other valid
command byte changing watchdog time.
34703
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SOFT START
INVERTED POWER SEQUENCING
A switching regulator and LDO soft start feature is
incorporated in the 34703. The soft start is active each time
the IC is enabled, VIN is reapplied, or after a fault retry. Other
transient events do not activate the soft start.
When the power supply IC is operating in the Inverted
Power Sequencing mode, the linear regulator (LDO) output
provides the core voltage for the microprocessor, as
illustrated in Figure 19. Table 5, page 15, shows the Power
Sequencing mode selection.
VOLTAGE MARGINING
3.3 Vinput
The 34703 includes a voltage margining feature accessed
through the I2C bus. Voltage margining allows for
independent adjustment of the Switcher VOUT voltage and the
linear output VLDO. Each can be adjusted up and down in 1%
steps to a range of ±7%. This feature allows for worst case
system validation; i.e., determining the design margin.
Margining details are described in the section entitled I2C Bus
Operation, beginning on page 25 of this datasheet.
34703
VIN1
VIN2
VBST (sense)
LCMP
SR
CLKSYN
POR
RESET
SCL
BOOT
The power sequencing of the two outputs of this power
supply IC is in compliance with the Freescale Power QUICC
and other 32-bit microprocessor requirements. When the
input voltage is applied, the switcher and linear regulator
outputs follow the supply rail voltage during powering up and
down in the limits given by the microcontroller power
sequencing specification, illustrated in Figures 17 through
19. There are two possible power sequencing modes,
Standard and Inverted, as explained below. The third mode
of operation is Power Sequencing Disabled.
EN1
SW_A
SW_B
EN2
Optional
MCU
LFB
SDA
VBST
1.5 V
VDDL (Core)
VOUT
CLKSEL
COMP
PGND
VDDI
GND
ADDR
INV
RT
3.3 V Input Supply (I/O Voltage)
V Start-Up
When the power supply IC operates in the Standard Power
Sequencing mode, the switcher output provides the core
voltage for the microprocessor. This situation and operating
conditions are illustrated in Figure 17 and Figure 18. Table 5,
page 15, shows the Power Sequencing mode selection.
VDDH (I/O)
LDO
VBD
FREQ
POWER SEQUENCING MODES
STANDARD POWER SEQUENCING
Other
Circuits
2.5 V
LDRV
ISNS
VBST
Slope
1.0 V/ms
(typ.)
∆V = 2.5 V
Max. Lead
1.8 V Core Voltage
∆V = 2.5 V
Max. Lead
∆V = 0.4 V
Max. Lag
Figure 17. Standard Power Up / Down Sequence
in +3.3 V Supply System
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER SEQUENCING
5.0 Vinput
Requirements
34703
VIN1
VIN2
LDRV
ISNS
LDO
VBST
VBST (sense)
VBD
3.3 V
VDDH (I/O)
LCMP
1. I/O supply voltage not to exceed core voltage by more
than 2.5 V.
2. Core supply voltage not to exceed I/O voltage by more
than 0.4 V.
FREQ
SR
CLKSYN
SDA
Optional
POR
RESET
SCL
BOOT
EN1
SW_A
SW_B
EN2
5.0 V
MCU
LFB
VBST
1.5 V
VDDL (Core)
VOUT
CLKSEL
COMP
VDDI
PGND
GND
ADDR
INV
RT
Methods of Control
The 34703 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also
achieved through the intrinsic operation of the regulators.
The EN1 and EN2 pins can be used to disable the power
sequencing (refer to Table 5, page 15).
Intrinsic Operation
∆V = 2.5 V
Max. Lead
5.0 V Input Supply
∆V = 2.5 V
Max. Lead
3.3 V I/O Voltage (VLDO)
V Start-Up
1.8 V Core Voltage
(VOUT)
∆V = 0.4 V
Max. Lag
∆V = 0.4 V
Max. Lag
Figure 18. Standard Power Up / Down Sequence
in +5.0 V Supply System
34703
VIN1
LDRV
ISNS
LDO
VBST
VBST (sense)
VBD
1.5 V
VDDL (Core)
LCMP
FREQ
SR
CLKSYN
5.0 V
Optional
MCU
LFB
SDA
POR
RESET
SCL
BOOT
EN1
SW_A
EN2
SW_B
VBST
3.3 V
VDDH (I/O)
VOUT
CLKSEL
COMP
∆V = 2.5 V
Max. Lead
PGND
GND
ADDR
VDDI
INV
RT
5.0 V Input Supply
∆V = 2.5 V
Max. Lead
1.8 V Core Voltage (VLDO)
∆V = 0.4 V
Max. Lag
1. LDO > VOUT + 2.3 V, turn off LDO. The LDO can be
forced off. This occurs whenever the LDO output
voltage exceeds the switcher output voltage by more
than 2.3 V.
2. LDO > VOUT + 2.4 V, shunt LDO to ground. If turning
off the LDO is insufficient and the LDO output voltage
exceeds the switcher output voltage by more than
2.4 V, a 1.0 Ω shunt FET is turned on that discharges
the LDO load capacitor to ground. The shunt FET is
used for switcher output shorts to ground and for power
down in case of VIN1 ≠ VIN2 with the switcher output
falling faster than the LDO.
3. LDO < VOUT + 2.2 V, cancel (1) and (2) above, reenable LDO. Normal operation resumes when the LDO
output voltage is less than 2.2 V above the switcher
output voltage.
3.3 V I/O Voltage (VOUT)
V Start-Up
Standard Power Sequencing Control
Comparators monitor voltage differences between the
LDO (LDO pin) and the switcher (VOUT pin) outputs as
follows:
5.0 Vinput
VIN2
For both the LDO and switcher, whenever the output
voltage is below the regulation point, the LDO external Pass
FET will be on or the Buck High-Side FET will be on at a duty
cycle controlled by the switcher. Because these devices are
FETs, current can flow in either direction, balancing the
voltages via the common supply pin. The ability to maintain
the FETs on will depend on the available gate voltage, and
thus the size of the boost regulator storage capacitor.
∆V = 0.4 V
Max. Lag
Figure 19. Inverted Power Up / Down Sequence
in +5.0 V Supply System
4. LDO < VOUT - 0.1 V, turn off switcher. The switcher can
be forced off. This occurs whenever the LDO is less
than VOUT - 0.1 V.
5. LDO < VOUT - 0.3 V, turn on Sync (LS) FET and 1.0 Ω
VOUT sink FET. The Buck High-Side FET is forced off
and the Sync FET is forced on. This occurs when the
switcher output voltage exceeds the LDO output by
more than 300 mV.
34703
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
6. LDO > VOUT, reset (4) and (5) above. Normal operation
resumes when LDO > VOUT.
Inverted Power Sequencing Control
Comparators monitor voltage differences between the
switcher (VOUT pin) and LDO (LDO pin) outputs as follows:
1. VOUT > LDO + 2.2 V, turn off VOUT . The switcher VOUT
can be forced off. This occurs whenever the VOUT
output voltage exceeds the LDO output voltage by
more than 2.3 V.
2. VOUT > LDO + 2.4 V, shunt VOUT to ground. If turning
off the switcher VOUT is insufficient and the VOUT
output voltage exceeds the LDO output voltage by
more than 2.4 V, a 1.0 Ω shunt FET is turned on that
discharges the VOUT load capacitor to ground. The
shunt FET is used for LDO output shorts to ground and
for power-down in case of VIN1 ≠ VIN2 with LDO output
falling faster than the VOUT.
3. VOUT < LDO + 2.2 V, cancel (1) and (2) above, reenable VOUT . Normal operation resumes when the
VOUT output voltage is less than 2.2 V above the LDO
output voltage.
where VOUT is falling faster than VIN, the Buck High-Side FET
will attempt to maintain VOUT. In the case where VIN is falling
faster than VOUT, the Buck High-Side FET is also on, and the
VOUT load capacitor will be discharged through the Buck
High-Side FET to VIN. Thus, provided VIN does not fall too
fast, the core voltage (VOUT) will not exceed the I/O voltage
(VIN) by more than a maximum of 0.4 V.
Shorted Load
1. VOUT shorted to ground. This will cause the I/O voltage
to exceed the core voltage by more than 2.5 V. The
load is protected by a current limit.
2. VIN shorted to ground. Until the switcher load
capacitance is discharged, the core voltage will exceed
the I/O voltage by more than 0.4 V. By the intrinsic
operation of the switcher, the load capacitor will be
discharged rapidly through the Buck High-Side FET to
VIN.
3. VOUT shorted to supply. No load protection. 34703
protected by a thermal limit.
Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply
VIN1 ≠ VIN2
4. VOUT < LDO - 0.2 V, turn off LDO. The LDO can be
forced off. This occurs whenever the VOUT is less than
VLDO - 0.2 V.
The LDO supplies the microprocessor I/O voltage. The
switcher supplies the core (e.g., 1.8 V nominal) (see
Figure 18, page 22).
5. VOUT < LDO - 0.3 V, turn on the 1.0 Ω LDO sink FET.
This occurs when the LDO output voltage exceeds the
VOUT output by more than 300 mV.
Power Up
6. VOUT > LDO, reset (4) and (5) above. Normal operation
resumes when VOUT > LDO.
STANDARD OPERATING MODE
Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V
The 3.3 V supplies the microprocessor I/O voltage, the
switcher supplies core voltage (e.g., 1.8 V nominal), and the
LDO operates independently (see Figure 17, page 21).
Power sequencing depends only on the normal switcher
intrinsic operation to control the Buck High-Side FET.
Power Up
When VIN is rising, initially VOUT will be below the
regulation point and the Buck High-Side FET will be on. In
order not to exceed the 2.5 V differential requirement
between the I/O (VIN) and the core (VOUT), the switcher must
start up at 2.5 V or less and be able to maintain the 2.5 V or
less differential. The maximum slew rate for VIN is 1.0 V/ms.
Power Down
When VIN is falling, VOUT will be below the regulation point;
therefore the Buck High-Side FET will be on. In the case
This condition depends upon the regulator current limit,
load current and capacitance, and the relative rise times of
the VIN1 and VIN2 supplies. There are 2 cases:
1. LDO rises faster than VOUT . The LDO uses control
methods (1) and (2) described in the Methods of
Control section, page 22.
2. VOUT rises faster than LDO. The switcher uses control
methods (4) and (5) described in the Methods of
Control section.
Power Down
This condition depends upon the regulator load current
and capacitance and the relative fall times of the VIN1 and
VIN2 supplies. There are 2 cases:
1. VOUT falls faster than LDO. The LDO uses control
methods (1) and (2) described in the Methods of
Control section, page 22.
In the case VIN1 = VIN2 the intrinsic operation will turn on
both the Buck High-Side FET and the LDO external Pass
FET, and will discharge the LDO load capacitor into the
VIN supply.
2. LDO falls faster than VOUT . The switcher uses control
methods (4) and (5) described in the Methods of
Control section.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Shorted Load
1. VOUT shorted to ground. The LDO uses method (1)
and (2) described in the Methods of Control section.
the LDO, the load capacitor will be discharged rapidly
through the Pass FET to VIN.
3. LDO shorted to supply. No load protection.
2. LDO shorted to ground. The switcher uses control
methods (4) and (5) described in the Methods of
Control section, page 22.
Single 5.0 V Supply, VIN1 = VIN2, or Dual Supply
VIN1 ≠ VIN2
3. VIN1 shorted to ground. This is equivalent to the LDO
output shorted to ground.
The switcher VOUT supplies the microprocessor I/O
voltage. The LDO supplies the core (e.g., 1.8 V nominal) (see
Figure 19, page 22).
4. VIN2 shorted to ground. This is equivalent to the
switcher output shorted to ground.
5. VOUT shorted to supply. No load protection. 34703
protected by current limit and thermal limit.
6. LDO shorted to supply. No load protection. 34703
protected by current limit and thermal limit.
INVERTED OPERATING MODE
Single 3.3 V Supply, VIN = VIN1 = VIN2 = 3.3 V
The 3.3 V supplies the microprocessor I/O voltage, the
LDO supplies core voltage (e.g., 1.8 V nominal), and the
switcher VOUT operates independently. Power sequencing
depends only on the normal LDO intrinsic operation to control
the Pass FET.
Power Up
When VIN is rising, initially LDO will be below the
regulation point and the Pass FET will be on. In order not to
exceed the 2.5 V differential requirement between the I/O
(VIN) and the core (LDO), the LDO must start up at 2.5 V or
less and be able to maintain the 2.5 V or less differential. The
maximum slew rate for VIN is 1.0 V/ms.
Power Down
When VIN is falling, LDO will be below the regulation point;
therefore the Pass FET will be on. In the case where LDO is
falling faster than VIN, the Pass FET will attempt to maintain
LDO. In the case where VIN is falling faster than LDO, the
Pass FET is also on, and the LDO load capacitor will be
discharged through the Pass FET to VIN. Thus, provided VIN
does not fall too fast, the core voltage (LDO) will not exceed
the I/O voltage (VIN) by more than maximum of 0.4 V.
Shorted Load
1. LDO shorted to ground. This will cause the I/O voltage
to exceed the core voltage by more than 2.5 V. The
load is protected by a current limit.
2. VIN shorted to ground. Until the LDO load capacitance
is discharged, the core voltage will exceed the I/O
voltage by more than 0.4 V. By the intrinsic operation of
Power Up
This condition depends upon the regulator current limit,
load current and capacitance, and the relative rise times of
the VIN1 and VIN2 supplies. There are 2 cases:
1. VOUT rises faster than LDO. The switcher VOUT uses
control methods (1) and (2) described in the Methods
of Control section, page 23.
2. LDO rises faster than VOUT . The LDO uses control
methods (4) and (5) described in the Methods of
Control section.
Power Down
This condition depends upon the regulator load current
and capacitance and the relative fall times of the VIN1 and
VIN2 supplies. There are 2 cases:
1. LDO falls faster than VOUT . The VOUT uses control
methods (1) and (2) described in the Methods of
Control section, page 23.
In the case VIN1 = VIN2 the intrinsic operation will turn both
the Buck High-Side FET and the LDO external Pass FET,
and will discharge the VOUT load capacitor into the VIN
supply.
2. VOUT falls faster than LDO. The LDO uses control
methods (4) and (5) described in the Methods of
Control section.
Shorted Load
1. LDO shorted to ground. The VOUT uses methods (1)
and (2) described in the Methods of Control section,
page 23.
2. VOUT shorted to ground. The LDO uses control
methods (4) and (5) described in the Methods of
Control section.
3. VIN1 shorted to ground. This is equivalent to the LDO
output shorted to ground.
4. VIN2 shorted to ground. This is equivalent to the
switcher VOUT output shorted to ground.
5. LDO shorted to supply. No load protection.
6. VOUT shorted to supply. No load protection. 34703
protected by a thermal limit.
34703
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
I2C BUS OPERATION
Writing Data Into the Slave Device
2
The 34703 device is compatible with the I C interface
standard. SDA and SCL pins are the Serial Data and Serial
Clock pins of the I2C bus.
I2C COMMAND AND DATA FORMATS
Communication Start
Communication starts with a START condition, followed by
the slave device unique address. Figure 20 illustrates the
data transfer beginning an I2C communication for a 7-bit
slave address.
S
7-Bit Address
R/W
Ack
Figure 20. Communication Using 7-Bit Address
After the address acknowledgment by the slave, DATA
can be written into the slave registers. The R/W bit must be
set to 0 so DATA will be written. Figure 22 shows the data
write sequence. Actions performed by the slave device are
grayed.
S
7-Bit Address
0
Ack
DATA
Ack
(W i )
Figure 22. Data Transfer for Write Operations
Data Definition
For the sake of the 34703 acting as a slave device, the
master writes a Command Byte and writes one Data Byte.
The Command Byte identifies the kind of operation required
by the master and has two fields, as illustrated in Figure 23:
1. Address field
Slave Address Definition
The 34703 has the two LSB’s address bits defined by the
state of the CLKSEL pin and the ADDR pin.
Note The state of the CLKSEL pin also defines the
configuration of the oscillator synchronization CLKSYN pin.
This feature allows up to four 34703 ICs to communicate
in the same I2C bus, all of them sharing the same high-order
address bits. A different combination of bits A1 and A0 is
assigned to each individual part to assure its unique address.
Figure 21 illustrates the flexible addressing feature for a 7-bit
address. Table 7 provides the definition of the selectable
portion of the device address.
Bits 6
5
4 3 2 1
1
1
1
0
Bits
7
6
5
4
3
2
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Address Field
Value Field
Figure 23. Command Byte
Table 8. Address Field Definitions
Code
Operation
Write
001
Voltage Margining
W
A1 A0
010
Not Used
–
Selectable
Address
011
Watchdog
W
1
Fixed Address
0
2. Value field
The address field is selected from the list in Table 8.
Figure 21. Address Bit Definition for 7-Bit Address
Refer to Table 10, page 26, which summarizes the value
field definitions for the entire set of operation options.
Table 7. Definition of Selectable Portion of Device
Address
CLKSEL Pin
ADDR Pin
A1
A0
Low
Low
0
0
Low
Open
0
1
Open
Low
1
0
Open
Open
1
1
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Security in Writing Commands
Table 10. Command Byte Definitions
All writing operations are critical and must not be
inadvertently latched after a false command. To improve the
security level, a so-called first command is defined to initiate
each write communications.
A first command has the Command Byte address field
equal to the related operation one, followed by a null value
field (all zeros). Table 9 summarizes first command
definitions. The master sends the first command before the
Command Byte for the intended operation.
Operation
Address
Voltage Margining 0
(As a 2nd
Command Byte)
Value
Action
0
1
0
0
0
0
0 1st Command
0
0
1
x
0
0
0
0 Output Normal
0
0
1
x
0
0
0
1
+ 1%
0
0
1
x
0
0
1
0
+ 2%
0
0
1
x
0
0
1
1
+ 3%
0
0
1
x
0
1
0
0
+ 4%
LDO Output: x = 0
0
0
1
x
0
1
0
1
+ 5%
Switcher Output
x=1
0
0
1
x
0
1
1
0
+ 6%
Operation
0
0
1
x
0
1
1
1
+ 7%
001 00000
Voltage Margining
0
0
1
x
1
0
0
1
- 1%
011 00000
Watchdog Programming
0
0
1
x
1
0
1
0
- 2%
0
0
1
x
1
0
1
1
- 3%
Voltage Margining Operation
0
0
1
x
1
1
0
0
- 4%
After starting the communication in Writing mode, the
master sends the first command followed by the specific
Command Byte to set the required voltage margining for
either the LDO or the switcher (see Figure 24). To achieve a
simultaneous set for both LDO and switcher, two specific
commands must be issued in sequence after the first
command, one for each supply.
0
0
1
x
1
1
0
1
- 5%
0
0
1
x
1
1
1
0
- 6%
0
0
1
x
1
1
1
1
- 7%
0
1
1
0
0
0
0
0 1st Command
0
1
1
0
0
0
0
0
Table 9. First Command Definitions
First Command
0 0 1 0 0 0 0 0 Ack 0 0 1 x x x x x
First Byte for Voltage Margining
Watchdog
Programming
(As a 2nd
Command Byte)
(28)
0
1
1
0
1
0
0
0
WD 1280 ms
WinOFF
0
1
1
0
1
0
0
1
WD 320 ms
WinOFF
0
1
1
0
1
0
1
0
WD 80 ms
WinOFF
0
1
1
0
1
0
1
1
WD 20 ms
WinOFF
0
1
1
0
1
1
0
0
WD 1280 ms
WinON
0
1
1
0
1
1
0
1
WD 320 ms
WinON
0
1
1
0
1
1
1
0
WD 80 ms
WinON
0
1
1
0
1
1
1
1
WD 20 ms
WinON
Command Byte
Figure 24. Voltage Margining Programming
(One Supply Only)
Note x bits are defined in Table 10, page 26.
Watchdog Programming Operation
For watchdog operation control, the master periodically
sends a watchdog first command followed by a command
byte selecting, or confirming, the watchdog period according
to the options listed in Table 10, page 26. Also see Figure 25.
The internal watchdog timer will be cleared each time a
watchdog command is written into the device, provided it
arrives during the window open time. The Command
01100000 sent twice will shut the time OFF, and the
watchdog function will be disabled. Any other valid watchdog
command turns on the timer again.
WD OFF
Notes
28. The Watchdog feature will be turned ON automatically after
receiving any other valid command byte changing watchdog
time.
0 1 1 0 0 0 0 0 Ack 0 1 1 x x x x x
First Byte for Watchdog Programming
Command Byte
Figure 25. Watchdog Timer Programming
Note x bits are defined in Table 10, page 26.
34703
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Communication Stop
Only the master can terminate the data transfer by issuing
a STOP condition. The slave waits for this condition to
resume its initial state waiting for the next START condition
(see Figure 26).
should be included before the STOP condition (P); for
instance, 001 10010 to set switcher in its second setting
(switcher output voltage = +2% above its nominal value).
Data Transfer Example
The master device controlling the I2C bus will always start
addressing a 34703 slave IC in writing mode (R/W = 0) in
order to be able to write a Command Byte just after the
address acknowledge. I2C bus protocol defines this
circumstance as a master-transmitter and slave-receiver
configuration.
Eventually this Command Byte can again define a Write
operation (e.g., Voltage Margining, see Figure 26), and the
master will keep the data transfer direction.
Figure 26 illustrates a communication beginning with the
slave address, the first command for voltage margining, and
a third byte containing the address field 001 and the value
field 00101 corresponding with the LDO fifth setting (LDO
output voltage = +5% above its nominal value). If a
simultaneous setting for switcher is needed, a fourth byte
S A6 A5 A4 A3 A2 A1 A0 0 Ack
START
Write
Slave Address
0
0
1
0
0
0
0
0 Ack
First Command for Voltage Margining
0
0
1
0
0
1
0
1 Ack P
STOP
Address Field Value Field = LDO
5th Setting
Figure 26. Complete Data Transfer Example
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
+3V3
+3V3
VIN1
VIN1
VDDI
VDDI
Supply
Voltage
Regulator
+3V3
VBST
Bandgap
reference
Vref
VBST
VDDI
VBST
LDRV
VDDI
VBD
2
Boost
Control
+3V3
Vref
1
Vref 3
VBST
VDDI
Power
Sequencing
Powerdown
Voltage
Margining
EN2
RT
RESET
Reset
Control
Reset Watchdog Timer
INV
SR
Slew
Rate
LFB
I2C
SR
VDDI
7
VDDI
VLDO = 2V5 @ 2 A
LCMP
Q4
BOOT
VIN2
Buck
HS
and
LS
Driver
5
Q1
VBD
+3V3
SW
Q2
PGND
7
5
0.8 V
6
VOUT = 1V2 @ 10 A
INV
6
Oscillator
SCL
CLKSEL CLKSYN
LDO
LFB
Current Limit
ADDR
SDA
ISNS
VBST
Buck
Control
Logic
SysCon
POR
Timer
UVLO
Pwr Seq.
VLDO
VOUT
EN1
Linear
Regulator
Control
with
ILim
VOUT
Ramp
Generator
FREQ
GND
Pwr Seq.
Q3
COMP
Figure 27. 34703 Typical Application
BOOST REGULATOR
When the input voltage to be used is less than 8.0 V, the
boost regulator should be used. The boost regulator is made
active by adding a small external inductor, and provides an
output voltage of 8.0 V nominal value for driving the gates of
the buck regulator power MOSFETs, the linear regulator
power MOSFET gate, and also for the internal Vddi supply.
The boost inductor value should be at least 10 uH for the
proper boost operation. NOTE: If the input voltage to be used
is greater than 8 V, the boost regulator must not be
implemented, and the boost inductor, if present, must be
removed from the circuit. A 0.1 µF capacitor is recommended
to be added at Pin VBST for filtering high frequency noise in
the system board.
BUCK REGULATOR
Output Voltage Setting
The buck output voltage is set by an external resistor
network (R9 and R14) and an internal reference voltage. The
external resistor network feeds back the dc output voltage,
and an error amplifier compares it with an internal reference
voltage Vref (See Figure 28). The buck output voltage can be
calculated from the following equation:
V output = V vef × ( 1 + R 9 ⁄ R 14 )
Where Vref designed in MC34703 is 0.8 V typ.
34703
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
high as possible unit gain crossover frequency with a gain
slope of -1, and enough phase margin ( at least 45°) for the
closed loop transfer function. The bandwidth should be
between 20 -30% of the switching frequency. In the power
system, there is a double pole created by the output LC filter,
and a zero generated by output capacitor ESR (equivalent
series resistance).
The poles are located:
If R9 is chosen as 5.1 kΩ (recommended), R14 will be
calculated as 4.08 kΩ for the output voltage of 1.8 V; in a
same manner, R14 is 1.63 kΩ for an output voltage of 3.3 V.
We recommend using 1% tolerance resistors (R9 and R14)
for the precise output voltage.
The following table shows the recommendation values of
R9 and R14 as referred to different buck output voltages:
1
F p1, p2 = -----------------------------2π L × C
O
O
Table 11. Recommendation of R9 and R14 Value for
Different Output Voltage
Vo
R9 (KΩ)
R14 (KΩ)
0.8
5.1
•
1.8
5.1
4.12
2.0
5.1
3.4
3.3
5.1
1.65
5.0
5.23
1.0
The zero is located:
1
F z1 = --------------------------------------2π × R ESR × C 0
Where CO is the capacitance of the output capacitor, Lo is
the inductance of the output filter inductor. RESR is the total
equivalent series resistance of output capacitors.
Based on the typical system conditions, the type 3
compensation scheme has been chosen to use as shown in
Figure 28.
Compensation Loop Determination
The MC34703 has a simple PWM voltage mode control
loop to achieve an excellent line and load regulation. The
goal for the compensation loop circuit design is to achieve as
Lo
SW
Vin
Gate
Drivers
Vout
High Side
Low Side
+ Co1
C26
R9
ERROR
PWM
COMPARATOR AMPLIFIER
R12
INV
Vref
C24
SAW
VOLTAGE
Vref
( 0.8 V)
C2
R5
R14
COMP
Figure 28. Buck Regulator Compensation Circuit
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
TYPICAL APPLICATIONS
The location of the three poles and two zeros from the
transfer function is shown by the following equations:
F s, p1 = 0
Figure 29 shows the asymptotic bode gain and phase plot
for the type 3 compensation scheme. The poles and /or
zeroes are adjusted in order to shape the gain profile and
make sure the phase has sufficient margin (to meet the
system stability criteria).
C 2 + C 24
F s, p2 = ----------------------------------------------2π × R 5 × C 2 × C 24
1
F s, p3 = ------------------------------------2π × R 12 × C 26
1
F s, z1 = ---------------------------------2π × R 5 × C 24
1
F s, z2 = -----------------------------------------------------2π × ( R 9 + R 12 ) × C 26
Gain (dB)
FFs,p1
s,p1
Fs,p2
Fs,p2
Fs,z1
Fs,z1
Fs,p3
F 3
s,p
Fs,z2
Fs,z2
Frequency (Hz)
Phase (o)
90
0
Frequency (Hz)
- 90
Figure 29. Bode and Phase plot for Type Compensation Scheme
Output Inductor Calculation
If the output inductor is designed to guarantee the buck
regulator will operate at critical mode or continuous mode
within all load conditions, the following equation will be used
to calculate the inductance of the output inductor:
V output × ( V in – V output )
L ≥ ---------------------------------------------------------------------2 × I output × V in × F s
Where L is the output inductor value in Henries, Vin is the
input voltage in Volts, Ioutput is the minimum output current in
Amps, and Fs is the switching frequency in Hertz. In this
equation, the magnitude of the ripple current is assumed as
2 times minimum load current.
For example: Input voltage is 5.5 V, minimum output
current is 0.2 A, output voltage is 1.8 V, the operating
frequency is 300 kHz, the inductance of output inductor is
calculated as 10 µH for an initial value.
Output Capacitor Calculating
The minimum capacitance of output capacitor could be
calculated from the following equation:
V output
C O min = ----------------------------------------------- × ( 1 – D )
8 × F s2 × L × ∆V pp
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
Where D is minimum switching duty cycle, Fs is the
operating frequency in Hertz, L is output inductance in
Henries, and ∆ Vpp is output ripple voltage in Volts.
For example, if the output voltage is 1.8V, the minimum
duty cycle is 33%, the operating frequency is 300 kHz, the
inductance is 10H and ∆ Vpp is 50 mV, the minimum
capacitance of output capacitor will be calculated as 3.3 µF,
as start value. However, this value is only concerned with the
ripple voltage. In the system, one needs to consider load
changes from overload to minimum load and keep the output
voltage within spec, so that the actual output capacitor value
varies with the system requirements.
The relationship between the ripple voltage and the ESR
of output capacitor is shown as follows:
∆V pp = ∆I ripple × R ESR
Output Current Limit Setting
The default setting of the limit is 11 A. When the output
current exceeds 11 A, the current limit timer starts to time out
while the control circuit limits the output current. If the over
current condition lasts for more than 10 ms, the buck
regulator is shut off and tuned on again after 100 ms. This
type of operation provides equivalent protection to the analog
“current fold-back” operation. See Figure 30.
VRESET
VOUT
VLDO
IOUT
Figure 30. Buck is in the Over Current Condition
When the buck output current (Channel 3) reaches and
exceeds limit, Reset Pin (Channel 1) is pulled down
immediately. Channel 4 is Buck output voltage (1.8V);
Channel 2 is LDO output voltage (3.3V).
LINEAR REGULATOR
Output Voltage Setting
The output voltage (VLDO) of the linear regulator (LDO)
can be set by the following equation:
R 11
V ldo = V ref × ⎛ 1 + --------⎞
⎝
R 10⎠
For example, if R10 is chosen as 15 kΩ (recommended),
R11 will be calculated as 18.75 kΩ for the output voltage of
1.8 V; in a same manner, R11 is 46.87 kΩ for the output
voltage of 3.3 V.
We recommend using 1% tolerance resistors (R10 and
R11) for the precise output voltage.
The following table shows the recommended values of
and referred to different buck output voltage:
Table 12. Recommendation of and Value for Different
Voltage
Vo
R10 (KΩ)
R11 (K)Ω
0.8
15
•
Where VREF is the linear regulator reference voltage,
typically is 0.8V at the LFB Pin.
1.8
15
18.7
2.0
15
22.6
Figure 31 shows the MC34703 linear regulator circuit with
its compensation circuit.
3.3
15
47
5.0
15
78.7
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Analog Integrated Circuit Device Data
Freescale Semiconductor
31
TYPICAL APPLICATIONS
C25
LCMP
R7
C23
MOSFET
Vin
Rs
Vout
Co2 +
LDRV
ISNS
LDO
R11
LFB
Vref
R10
Figure 31. Linear Regulator Circuit
Compensation Components Setting
The compensation component values have been
determined by the design. The recommended values are the
following:
C25 = 10nF, C23 =6.8nF, R7 = 1.5KΩ
Since the compensation component values designed are
dependent on the output capacitor value, the capacitance of
10 µF for the output capacitor Co is recommended.
Figure 31. The voltage drop caused by the regulator output
current flowing through the current sense resistor is sensed
between the LDO and the ISNS pins. When the sensed
voltage exceeds 45 mV (Design), the current limit timer starts
to time out while the control circuit limits the output current. If
the over current condition lasts for more than 10 ms, the
linear regulator is shut off and tuned on again after 100 ms.
This type of operation provides equivalent protection to the
analog “current fold-back” operation. Figure 32 shows a
sample of the LDO in the Over current protection.
Output Current Limit Setting
The current limit of the linear regulator can be adjusted by
means of an external current sense resistor Rs, see
VRESET
VOUT
VLDO
IOUT
Figure 32. LDO in the Over Current Condition
34703
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
When the LDO output current (Channel 3) reaches and
exceeds limit, Reset Pin (Channel 1) is pulled down
immediately. Channel 2 is LDO output voltage (3.3 V);
Channel 4 is Buck output voltage (1.8 V).
The current limit of the LDO can be set by using the
following formula:
45mV
R s = ---------------I LIMIT
Power MOSFET Selecting
To keep the LDO working under stable operation, low input
capacitance is recommended for the external power
MOSFET. However, if input capacitance is too small, it may
lead the feedback loop into an unstable region. In this case,
a suggested MOSFET for the LDO, is IRL2703S or
NTD60N02R from On Semiconductor.
Layout Guidelines
To achieve a working power supply (regulator) design,
care must be taken in the PCB layout, not just the electrical
design. The PCB layout plays a critical role in the power
supply performance. A good PCB layout design will improve
regulation parameters and electromagnetic compatibility
(EMC) performance of switching power supply. In order to
avoid any inductive or capacitive coupling of the switching
power supply noise into the sensitive analog control circuits,
the noisy power ground and clean quiet signal ground should
be well separated on the PCB board, and connected only at
one point. The power routing should be made by heavy
traces or area of copper. The power path and its return
should be placed, if possible, on top of each other on different
layers or opposite sides of the PCB board.
The switching power supply input and output capacitors
should be physically placed very close to the power pins
(Vin2, SW, and PGND) of the 34703. Their ground pins,
together with the 34703 power ground pins (PGND), should
be connected by a single island of the power ground copper
to create the “single island” grounding.
The bootstrap capacitor should be tightly connected to the
integrated circuit as well. The same guidelines as those for
the layout of the main switching buck regulator should be
applied to the layout of the low power auxiliary boost
regulator and to some extent, the power path of the linear
regulator.
A four layer PCB is recommended for this product. It is
imperative to provide a VOUT (-) pin at the ground side of the
output capacitors, in order to ensure adequate load
regulation. The same is also true for LDO.
It is also recommended that the vias on the PCB used to
connect the second row of contacts (pins 13 to 21) on the IC,
have a hole diameter no larger than 0.009".
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
TYPICAL APPLICATION CIRCUIT
PCB LAYOUTS AND BOM
TYPICAL APPLICATION CIRCUIT
PCB LAYOUTS AND BOM
Figure 33. A Typical Application Circuit Schematic
34703
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATION CIRCUIT
PCB LAYOUTS AND BOM
Table 13. Bill of Material of a Typical Application Circuit
Application Bill of Material
NOTE: ALL BOM COMPONENTS ARE RoHS COMPLIANT. 4-layer PCB TO BE SMONiG (soldermask over Nickel Gold Flash) with micro vias plated with
Cu until filled nearly solid (9mil thru-holes plated until diameter < 5mil).
Part-ID
Value
Device
Package & Description
U1
MC34703
MC34703
PQFN33 FREESCALE Power Management IC
Q1
NTLTD7900N
MOSFET
CHIPFET Protected Power MOSFET (ON Semi)
D1
MMSD4148T1G diode
SOD123 Switching DIODE (ON Semi)
VO, VL
RED or YEL
CHIPLED
0603
C9
330 µF
ALEL
UHN1C331MPD Nichicon Ultra Low Impedance
C7, C17
10 µF
ALEL
ECEA1EKS100 (Panasonic KS series)
C11, 12, 15
2.2 µF
CERAMIC
C1206 CAPACITOR
C1
100 nF
CERAMIC
C1206 CAPACITOR
C28
10 µF
CERAMIC
C1206 ECJ-3YB1E106M (Panasonic X5R series, digikey# PCC2326TR-ND
C14
1 µF
CERAMIC
C1206 CAPACITOR
C29
100 nF
CERAMIC
C1206 CAPACITOR
C21, C24
33 nF
CERAMIC
C1206 CAPACITOR
C25, C30
10 nF
CERAMIC
C0603 CAPACITOR
C23
6.8 nF
CERAMIC
C0603 CAPACITOR
C19
4.7 nF
CERAMIC
C0805 CAPACITOR
C26
4.7 nF
CERAMIC
C1206 CAPACITOR
C22
680 pF
CERAMIC
C0603 CAPACITOR
C20
100 pF
CERAMIC
C0603 CAPACITOR
L2
10 µH
INDUCTOR
16T#30AWG WOUND ON T26-18 Micrometals.com CORE
L2-alt.
10 µH
INDUCTOR
22T#30AWG WOUND ON T20=70 Micrometals.com CORE
L3
3.2 µH
INDUCTOR
6T#18AWG WOUND ON T50-70D Micrometals.com CORE
L3-alt.
2.2 µH
INDUCTOR
9T#18AWG WOUND ON T50-18B Micrometals.com CORE
RSENSE
.025
NONINDUCTIVE
WW RESISTOR WLAR025FE (Ohmite.com)
R1
10K
R-US_R0603
R0603 RESISTOR
R2
47K
R-US_R0603
R0603 RESISTOR
R3
33
R-US_R0603
R0603 RESISTOR
R4
33
R-US_M1206
M1206 RESISTOR
R5
4.7K
R-US_R0603
R0603 RESISTOR
R7
1.5K
R-US_R0603
R0603 RESISTOR
R8, R9
5.1K
R-US_R0603
R0603 RESISTOR
R10
22K
R-US_R0603
R0603 RESISTOR
R11
47K
R-US_R0603
R0603 RESISTOR
R12
75
R-US_R0603
R0603 RESISTOR
R13
50
R-US_R0603
R0603 RESISTOR
R14
10K
R-US_R0603
R0603 RESISTOR
R17, R18
470
R-US_R0603
R0603 RESISTOR
R15, R16
50K
10TURN TRIMPOT
3223-W-1-503-E BOURNS SMD Trimming Potentiometer
Notes
29.
Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their
application.
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
TYPICAL APPLICATION CIRCUIT
PCB LAYOUTS AND BOM
Figure 34. PCB Layer 1
Figure 36. PCB Layer 3
Figure 35. PCB Layer 2
Figure 37. PCB Layer 4
34703
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATION CIRCUIT
TYPICAL WAVEFORM CHARACTERISTICS OF THE EVB BOARD
TYPICAL WAVEFORM CHARACTERISTICS OF THE EVB BOARD
VOUT
VLDO
Figure 38. Power Up Sequences
(Standard Mode, Vin = 5 V, Voutput = 1.8 V, VLDO = 3.3 V)
VOUT
VLDO
Figure 41. Power Down Sequences
(Inverted Mode, Vin = 7 V, Voutpu t= 5 V, VLDO = 3.3 V)
VOUT
VLDO
Vripple
Figure 39. Power Down Sequences
(Standard Mode, Vin = 5 V, Voutput = 1.8 V, VLDO = 3.3 V)
Figure 42. Output Ripple Voltage (Vin = 5 V, Io = 10 A)
VOUT
Vripple
VLDO
Figure 40. Power Up Sequences
(Inverted Mode, Vin = 7 V, Voutput = 5 V, VLDO = 3.3 V)
Figure 43. The Same Output Waveform as Figure 42
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
TYPICAL APPLICATION CIRCUIT
TYPICAL WAVEFORM CHARACTERISTICS OF THE EVB BOARD
VOUT
Vripple
IO
Figure 44. Output Ripple Voltage (Vin= 10 V, Io = 10 A)
Figure 46. Load Transient Response
(Step-Up Io = 0.1 A - 5 A)
VOUT
Vripple
IO
Figure 45. The Same Output Waveform as Figure 44
Figure 47. Load Transient Response
(Step-Down Io = 5 A - 0.1 A)
34703
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
PNB SUFFIX
33-PIN PQFN
PLASTIC PACKAGE
98ASA10705D
ISSUE 0
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
PACKAGING
PACKAGE DIMENSIONS
PNB SUFFIX
33-PIN PQFN
PLASTIC PACKAGE
98ASA10705D
ISSUE 0
34703
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PNB SUFFIX
33-PIN PQFN
PLASTIC PACKAGE
98ASA10705D
ISSUE 0
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
PACKAGING
PACKAGE DIMENSIONS
PNB SUFFIX
33-PIN PQFN
PLASTIC PACKAGE
98ASA10705D
ISSUE 0
34703
42
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PNB SUFFIX
33-PIN PQFN
PLASTIC PACKAGE
98ASA10705D
ISSUE 0
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
PACKAGING
PNB SUFFIX
33-PIN PQFN
PLASTIC PACKAGE
98ASA10705D
ISSUE 0
34703
44
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
0.0
Initial Release
2.0
8/2005
•
•
•
3.0
11/2005
•
•
Added new 98ASA10705D Drawing
Updated ISO drawing
4.0
2/2006
•
•
•
•
•
•
•
Updated Introduction / Features
Revised Figure 1, Simplified Application Diagram
Revised Table 1, Pin Definitions
Revised Typical Application Section
Changed Table 3, Static Buck Converter Peak Current Limit (High Level) Max rating from 18 to 19
and LDO Internal Pull-Down MOSFET RDS(ON), ID = 1.0 A, TA = 25°C, VBST = 8.0 V Max rating from
3.0 to 3.2
Condensed Bill of Material.
Corrected pin definitions on VBST, RESET, CLKSYN, and GND (pin 26)
Corrected images for Internal Block Diagram, Pin Connections, and Typical Applications to reflect
changes made to RESET and GND pins.
Clarified description of the Buck Converter in the Functional Internal Block Description.
Changed Output Current Slew Rate from TBD to 2.5 A/µs.
•
•
Minor corrections to typical application graphics
Updated to the prevailing Freescale form and style
•
•
•
5.0
8/2006
Implemented Revision History page
Incorporated engineering comments
Converted to Freescale format
34703
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
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MC34703 Rev. 5.0
8/2006
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Freescale Semiconductor reserves the right to make changes without further notice to
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