MC34931SEK

NXP Semiconductors Technical Data Document Number: MC34931 Rev. 4.0, 8/2016 5.0 A H-Bridge 34931 Industrial The 34931 is a monolithic H-Bridge Power IC in a robust thermally enhanced package. It is designed for any low voltage DC servo motor control application within the current and voltage limits stated in this specification. This device is powered by SMARTMOS technology. The 34931 H-Bridge is able to control inductive loads with currents up to 5.0 A peak. RMS current capability is subject to the degree of heatsinking provided to the device package. Internal peak current limiting (regulation) is activated at load currents above 6.5 A ±1.5 A. Output loads can be pulse-width modulated (PWMed at frequencies up to 20 kHz. A load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller’s A/D input. A status flag output reports undervoltage, overcurrent, and overtemperature fault conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. The disable inputs are provided to force the H-Bridge outputs to tri-state (high-impedance off-state). Features • 5.0 V to 36 V continuous operation with 24 V nominal operating voltage (transient operation from 5.0 V to 40 V) • 235 mΩ maximum RDS(on) at TJ = 150 °C (each H-Bridge MOSFET) • 3.0 V and 5.0 V TTL/CMOS logic compatible inputs • Overcurrent limiting (regulation) via internal constant-off-time PWM • Output short-circuit protection (short to VPWR or GND) • Temperature-dependant current-limit threshold reduction • All inputs have an internal source/sink to define the default (floating input) states • Sleep mode with current draw < 20 µA H-BRIDGE EK SUFFIX (PB-FREE) 98ARL10543D 32-PIN SOICW-EP Applications • DC motor control • DC brushed and servo motor driver • Copiers, printers • Factory automation • POS, ATM, vending kiosks • Robotics • Security camera control • Ticketing, toll systems VPWR VDD 34931 SF VPWR FB CCP OUT1 MCU IN1 MOTOR IN2 OUT2 D1 EN/D2 PGND AGND Figure 1. MC34931 simplified application diagram © 2016 NXP B.V. 1 Orderable parts Table 1. Orderable part variations Part number PWM frequency MC34931EK 11 kHz MC34931SEK 20 kHz Temperature (TA) Package Notes - 40 °C to 85 °C 32 SOICW-EP (1) Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 34931 2 NXP Semiconductors 2 Internal block diagram VPWR LOGIC SUPPLY CCP VDD VCP CHARGE PUMP HS1 HS2 OUT1 TO GATES OUT2 HS1 IN1 LS1 IN2 HS2 EN/D2 D1 SF FB GATE DRIVE AND PROTECTION LOGIC LS1 LS2 PGND LS2 VSENSE ILIM PWM CURRENT MIRROR AND CONSTANT OFF-TIME PWM CURRENT REGULATOR AGND PGND Figure 2. 34931 Simplified internal block diagram 34931 NXP Semiconductors 3 3 Pin connections 3.1 Pinout diagram AGND 1 32 SF D1 2 31 IN1 FB 3 30 N/C N/C 4 29 IN2 EN/D2 5 28 CCP N/C 6 27 N/C VPWR 7 26 VPWR VPWR 8 25 VPWR N/C 9 24 N/C OUT1 10 23 OUT2 OUT1 11 22 OUT2 N/C 12 21 N/C N/C 13 20 N/C N/C 14 19 N/C PGND 15 18 PGND PGND 16 17 PGND EP 32 SOICW-EP Transparent Top View Figure 3. 34931 pin connections A functional description of each pin can be found in the Functional Description section beginning on page 12. Table 2. 34931 pin definitions Pin number Pin name Pin function Formal name Definition 2 D1 Logic Input Disable Input 1 (Active High) When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input with ~ 80 μA source so default condition = disabled. 3 FB Analog Output Feedback The load current feedback output provides ground referenced 0.24% of the high-side output current. (Tie to GND through a resistor if not used.) 5 EN/D2 Logic Input Enable Input When EN/D2 is logic HIGH the H-Bridge is operational. When EN/D2 is logic LOW, the H-Bridge outputs are tri-stated and placed in Sleep mode. (logic input with ~ 80 μA sink so default condition = Sleep mode.) 7, 8, 25, 26 VPWR Power Input Positive Power Supply These pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the PCB. 10, 11 OUT1 Power Output H-Bridge Output 1 15-18 PGND Power Ground Power Ground 22, 23 OUT2 Power Output H-Bridge Output 2 28 CCP Analog Output Charge Pump Capacitor External reservoir capacitor connection for the internal charge pump; connected to VPWR. Allowable values are 30 nF to 100 nF. Note: This capacitor is required for the proper performance of the device. 29 IN2 Logic Input Input 2 Logic input control of OUT2;e.g., when IN2 is logic HIGH, OUT2 is set to VPWR, and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger Input with ~ 80 μA source so default condition = OUT2 HIGH.) Source of HS1 and drain of LS1 High-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the PCB. Source of HS2 and drain of LS2 34931 4 NXP Semiconductors Table 2. 34931 pin definitions (continued) Pin number Pin name Pin function Formal name Definition 31 IN1 Logic Input Input 1 Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWR, and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with ~ 80 μA source so default condition = OUT1 HIGH.) 32 SF Logic Output Open Drain Status Flag (Active Low) Open drain active LOW Status Flag output (requires an external pull-up resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VSFLOW < 0.4 V at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.) 1 AGND Analog Ground Analog Signal Ground 4, 6, 9, 12-14, 19-21, 24, 27, 30 N/C None No Connect EP EP Thermal Pad Exposed Pad The low-current analog signal ground must be connected to PGND via lowimpedance path (