NXP Semiconductors
Data Sheet: Technical Data
Document Number: MC34932
Rev. 4.0, 8/2016
Dual 5.0 A H-Bridge
34932
Industrial
The 34932 is a monolithic H-Bridge Power IC in a robust thermally enhanced
package. The 34932 has two independent monolithic H-Bridge Power ICs in the
same package. They are designed for any low voltage DC servo motor control
application within the current and voltage limits stated in this specification. This
device is powered by SMARTMOS technology.
H-BRIDGE
Each H-Bridge in the 34932 is able to control inductive loads with currents up to
5.0 A peak. RMS current capability is subject to the degree of heatsinking
provided to the device package. Internal peak current limiting (regulation) is
activated at load currents above 6.5 A ±1.5 A. Output loads can be pulse-width
modulated (PWMed at frequencies up to 20 kHz. A load current feedback
feature provides a proportional (0.24% of the load current) current output
suitable for monitoring by a microcontroller’s A/D input. A status flag output
reports undervoltage, overcurrent, and overtemperature fault conditions.
Two independent inputs provide polarity control of two half-bridge totem pole
outputs. Two independent disable inputs are provided to force the H-Bridge
outputs to tri-state (high-impedance off state).
EK SUFFIX (PB-FREE)
98ASA99334D
54-PIN SOICW-EP
Features
• 5.0 V to 36 V continuous with 24 V nominal operating voltage (transient
operation from 5.0 V to 40 V)
• 235 mΩ maximum RDS(on) at TJ = 150 °C (each H-Bridge MOSFET)
• 3.0 V and 5.0 V TTL/CMOS logic compatible inputs
• Output short-circuit protection (short to VPWR or GND)
• Overcurrent limiting (regulation) via internal constant-off-time PWM
• Temperature dependant current limit threshold reduction to allow for
continuous operation without shutdown
• All inputs have an internal source/sink to define the default (floating input)
states
• Sleep mode with current draw < 20 µA (each half with inputs floating or set
to match default logic states)
Applications
• DC motor control
• DC brushed and servo motor driver
• Copiers, printers
• Factory automation
• POS, ATM, vending kiosks
• Robotics
• Security camera control
• Ticketing, toll systems
VPWR
VDD
34932
SFA
FBA
MCU
IN1
IN2
D1
EN/D2
IN3
IN4
D3
EN/D4
FBB
VPWRA
CCPA
OUT1
MOTOR
OUT2
PGNDA
AGNDA
VPWR
VPWRB
CCPB
OUT3
MOTOR
VDD
SFB
PGNDB
AGNDB
OUT4
Figure 1. MC34932 simplified application diagram
© 2016 NXP B.V.
1
Orderable parts
Table 1. Orderable part variations
Part number
PWM frequency
MC34932EK
11 kHz
MC34932SEK
20 kHz
Temperature (TA)
Package
Notes
-40 °C to 85 °C
54 SOICW-EP
(1)
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
34932
2
NXP Semiconductors
2
Internal block diagram
VPWRA
LOGIC SUPPLY
CCPA
VDD
VCP CHARGE
PUMP
HS1
HS2
OUT1
TO GATES
OUT2
HS1
IN1
LS1
IN2
HS2
EN/D2
D1
GATE DRIVE
AND
PROTECTION
LOGIC
LS1
PGND
LS2
VSENSE
SFA
LS2
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
ILIM PWM
FBA
H-Bridge A
AGNDA
PGNDA
H-Bridge B
LOGIC SUPPLY
CCPB
VDD
VPWRB
VCP CHARGE
PUMP
HS1
HS2
OUT3
TO GATES
OUT4
HS1
IN3
LS1
IN4
HS2
EN/D4
D3
GATE DRIVE
AND
PROTECTION
LOGIC
SFB
LS1
PGND
LS2
VSENSE
ILIM PWM
FBB
AGNDB
LS2
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
PGNDB
Figure 2. 34932 simplified internal block diagram
34932
NXP Semiconductors
3
3
Pin connections
3.1
Pinout diagram
VPWRA
NC
D1
FBA
EN/D2
NC
NC
NC
VPWRA
OUT1
OUT1
PGNDA
PGNDA
NC
PGNDB
PGNDB
OUT4
OUT4
VPWRB
CCPB
NC
NC
IN4
IN3
SFB
VPWRB
AGNDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EP
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
AGNDA
VPWRA
SFA
IN1
IN2
NC
NC
CCPA
VPWRA
OUT2
OUT2
PGNDA
PGNDA
NC
PGNDB
PGNDB
OUT3
OUT3
VPWRB
NC
NC
NC
EN/D4
FBB
D3
NC
VPWRB
54 SOICW-EP
Transparent Top View
Figure 3. 34932 pin connections
A functional description of each pin can be found in the Functional Description section beginning on page 12.
Table 2. 34932 pin definitions
Pin number
Pin name
Pin function
Formal name
Definition
3
D1
Logic Input
Disable Input 1
(Active High)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input with
~ 80 μA source so default condition = disabled.
4
FBA
Analog
Output
Feedback
H-Bridge A load current feedback output provides ground referenced 0.24% of the highside output current. (Tie to GND through a resistor if not used.)
5
EN/D2
Logic Input
Enable Input
When EN/D2 is logic HIGH, H-Bridge A is operational. When EN/D2 is logic LOW, the
H-Bridge A outputs are tri-stated and H-Bridge A is placed in Sleep Mode. (logic input
with ~ 80 μA sink so default condition = Sleep Mode.)
1, 9, 46, 53
VPWRA
Power Input
Positive Power
Supply
These pins must be connected together physically as close as possible and directly
soldered down to a wide, thick, low resistance supply plane on the PCB.
10, 11
OUT1
Power
Output
H-Bridge Output 1
H-Bridge A source of HS1 and drain LS1.
12, 13, 42,
43
PGNDA
Power
Ground
Power Ground
High-current power ground pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low resistance ground plane on the
PCB. PGNDA should be connected to PGNDB with a low-impedance path.
34932
4
NXP Semiconductors
Table 2. 34932 pin definitions (continued)
Pin number
Pin name
Pin function
Formal name
Definition
15, 16, 39,
40
PGNDB
Power
Ground
Power Ground
High-current power ground pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low resistance ground plane on the
PCB. PGNDB should be connected to PGNDA with a low-impedance path.
17, 18
OUT4
Power
Output
H-Bridge Output 4
H-Bridge B Source of HS2 and drain of LS2.
19, 26, 28,
36
VPWRB
Power Input
Positive Power
Supply
These pins must be connected together physically as close as possible and directly
soldered down to a wide, thick, low resistance supply plane on the PCB.
20
CCPB
Analog
Output
Charge Pump
Capacitor
External reservoir capacitor connection for H-Bridge B internal charge pump; connected
to VPWRB. Allowable values are 30 to 100 nF. Note: This capacitor is required for the
proper performance of the device.
23
IN4
Logic Input
Input 4
Logic input control of OUT4.
24
IN3
Logic Input
Input 3
Logic input control of OUT3.
25
SFB
Logic Output
- Open Drain
Status Flag B
(Active Low)
H-Bridge B open drain active LOW Status Flag output (requires an external pull-up
resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VSFLOW < 0.4 V
at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
30
D3
Logic Input
Disable Input 3
(Active High)
When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated. Schmitt trigger input with
~80 μA source so default condition = disabled.
31
FBB
Analog
Output
Feedback B
H-Bridge B load current feedback output provides ground referenced 0.24% of the highside output current. (Tie to GND through a resistor if not used.)
32
EN/D4
Logic Input
Enable Input
When EN/D4 is logic HIGH, H-Bridge B is operational. When EN/D4 is logic LOW, the HBridge B outputs are tri-stated and H-Bridge B is placed in Sleep Mode. (logic input with
~ 80μA sink so default condition = Sleep Mode.)
37, 38
OUT3
Power
Output
H-Bridge Output 3
H-Bridge B Source of HS1 and drain of LS1.
44, 45
OUT2
Power
Output
H-Bridge Output 2
H-Bridge A source of HS2 and drain of LS2.
47
CCPA
Analog
Output
Charge Pump
Capacitor
External reservoir capacitor connection for H-Bridge A internal charge pump; connected
to VPWRA. Allowable values are 30 to 100 nF. Note: This capacitor is required for the
proper performance of the device.
50
IN2
Logic Input
Input 2
Logic input control of OUT2.
51
IN1
Logic Input
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWRA, and
when IN1 is logic LOW, OUT1 is set to PGNDA. (Schmitt trigger Input with ~ 80 μA
source so default condition = OUT1 HIGH.)
52
SFA
Logic Output
- Open Drain
Status Flag
(Active Low)
H-Bridge A open drain active LOW Status Flag output (requires an external pull-up
resistor to VDD. Maximum permissible load current < 0.5 mA. Maximum VSFLOW < 0.4 V
at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
54
27
AGNDA
AGNDB
Analog
Ground
Analog Signal
Ground
The low-current analog signal ground must be connected to PGND via low-impedance
path (< 10 mΩ, 0 Hz to 20 kHz).
2, 6 - 8, 14,
21, 22, 29,
33 - 35, 41,
48, 49
NC
None
No Connect
These pins have no electrical connection or function.
EP
EP
Thermal Pad
Exposed Pad
Exposed TAB is also the main heatsinking path for the device and must be connected to
ground.
34932
NXP Semiconductors
5
4
Electrical characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device. These parameters are not production tested.
Ratings
Symbol
Value
Unit
VPWR(SS)
VPWR(T)
- 0.3 to 36
- 0.3 to 40
V
Logic Input Voltage(2)
VIN
- 0.3 to 7.0
V
SFA, SFB Output(3)
V SF
- 0.3 to 7.0
V
Continuous Output Current(4)
IOUT(CONT)
5.0
A
Electrical ratings
Power Supply Voltage
• Normal Operation (Steady-state)
• Transient Overvoltage(1)
ESD Voltage(5)
•
•
•
•
•
Human Body Model
Machine Model
Charge Device Model
Corner Pins
All Other Pins
VESD1
VESD2
± 2000
± 200
V
±750
±500
Thermal ratings
TSTG
- 65 to 150
°C
TA
TJ
- 40 to 85
- 40 to 150
°C
Peak Package Reflow Temperature During Reflow(7),(8)
TPPRT
Note 8
°C
Approximate Junction-to Case Thermal Resistance(9)
RTHJC
< 1.0
°C/W
Storage Temperature
Operating Temperature(6)
• Ambient
• Junction
Notes
1. Device survives repetitive transient overvoltage conditions for durations not to exceed 500 ms at duty cycle not to exceed 5.0%. External protection
is required to prevent device damage in case of a reverse power condition.
2. Exceeding the maximum input voltage on IN1, IN2, IN3, IN4, EN/D2, EN/D4, D1, or D3 may cause a malfunction or permanent damage to the
device.
3. Exceeding the pull-up resistor voltage on the open drain SFA or SFB pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature ≤ 150 °C.
5. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF, RZAP =
0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
6.
7.
8.
9.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief nonrepetitive excursions of junction temperature above 150 °C can be tolerated, provided the duration does not exceed 30 seconds maximum. (Nonrepetitive events are defined as not occurring more than once in 24 hours.)
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board) values
varies depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum die temperature
represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJA must be
< 5.0 °C/W for maximum current at 70 °C ambient. Module thermal design must be planned accordingly.
34932
6
NXP Semiconductors
4.2
Static electrical characteristics
Table 4. Static electrical characteristics
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 36 V, - 40 °C ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Specifications given for
H-Bridge A apply symmetrically to H-Bridge B.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
VPWR(SS)
VPWR(t)
5.0
–
–
–
36
40
V
IPWR(SLEEP)
–
15
20
μA
IPWR(STANDBY)
–
–
18
mA
VUVLO(ACTIVE)
VUVLO(INACTIVE)
VUVLO(HYS)
4.15
–
150
–
–
200
–
5.0
350
V
V
mV
Charge Pump Voltage (CP Capacitor = 33 nF), No PWM
• VPWR = 5.0 V
• VPWR = 36 V
VCP - VPWR
3.5
–
–
–
–
12
V
Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 11 kHz for
MC34932EK and 20 kHz for MC34932SEK
• VPWR = 5.0 V
• VPWR = 36 V
VCP - VPWR
–
–
–
12
V
Power inputs (VPWR)
Operating Voltage Range(10)
• Steady-state
• Transient (t < 500 ms)(11)
Sleep State Supply Current(12)
• EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and IOUT = 0 A
Standby Supply Current (Part Enabled)
• IOUT = 0 A, VEN = 5.0 V
Undervoltage Lockout Thresholds
• VPWR(FALLING)
• VPWR(RISING)
• Hysteresis
Charge pump
3.5
–
Control inputs
Operating Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
• Logic Threshold HIGH
• Logic Threshold LOW
• Hysteresis
Logic Input Currents, VPWR = 8.0 V
• Input EN/D2, EN/D4 (internal pull-downs), VIH = 5.0 V
• Inputs IN1, IN2, D1, IN3, IN4, D3 (internal pull-ups), VIL = 0 V
VI
–
–
5.5
V
VIH
VIL
VHYS
2.0
–
250
–
–
400
–
1.0
–
V
V
mV
IIN
20
-200
80
-80
200
-20
μA
Notes
10. Device specifications are characterized over the range of 8.0 V ≤ VPWR ≤ 36 V. Continuous operation above 36 V may degrade device reliability.
Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device survives the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once every 10
seconds.
12. IPWR(SLEEP) is with Sleep Mode activated and EN/D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating. Typical value
characterized under the following conditions: TA = 85 °C and VPWR = 36 V.
34932
NXP Semiconductors
7
Table 4. Static electrical characteristics (continued)
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 36 V, - 40 °C ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Specifications given for
H-Bridge A apply symmetrically to H-Bridge B.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
–
–
–
120
–
–
–
235
325
ILIM
5.2
–
6.5
4.2
8.0
–
A
High-side Short-circuit Detection Threshold (Short-circuit to Ground)(13)
ISCH
11
13
16
A
Low-side Short-circuit Detection Threshold (Short-circuit to VPWR)(13)
ISCL
9.0
11
14
A
IOUTLEAK
–
-140
–
–
100
–
μA
VF
–
–
2.0
V
TLIM
THYS
175
–
–
12
200
–
°C
Current Foldback at TJ(13)
TFB
165
–
185
°C
Current Foldback to Thermal Shutdown Separation(13)
TSEP
10
–
15
°C
0.0
0.0
0.35
2.86
5.71
11.43
–
270
0.775
3.57
7.14
14.29
50
750
1.56
4.28
8.57
17.15
μA
μA
mA
mA
mA
mA
ISFLEAK
–
–
5.0
μA
VSFLOW
–
–
0.4
V
Power outputs OUT1, OUT2
Output-ON Resistance(14), ILOAD = 3.0 A
• VPWR = 8.0 V, TJ = 25 °C
• VPWR = 8.0 V, TJ = 150 °C
• VPWR = 5.0 V, TJ = 150 °C
RDS(ON)
mΩ
Output Current Regulation Threshold
• TJ < TFB
(13)
• TJ ≥ TFB (Fold back Region - see Figure 9 and Figure 11)
Output Leakage Current(15), Outputs off, VPWR = 36 V
MC34932EK and MC34932SEK
• VOUT = VPWR
• VOUT = Ground
Output MOSFET Body Diode Forward Voltage Drop, IOUT = 3.0 A
Overtemperature Shutdown(13)
• Thermal Limit at TJ
• Hysteresis at TJ
High-side current sense feedback
•
•
•
•
•
•
Feedback Current (pin FB sourcing current)(16)
I OUT = 0.0 mA
I OUT = 300 mA
I OUT = 500 mA
I OUT = 1.5 A
I OUT = 3.0 A
I OUT = 6.0 A
I FB
Status flag(17)
Status Flag Leakage Current(18)
• V SF = 5.0 V
Status Flag SET Voltage(19)
• I SF = 300 µA
Notes
13.
14.
15.
16.
This parameter is Guaranteed By Design.
Output-ON resistance as measured from output to VPWR and from output to GND.
Outputs switched OFF via D1.
Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: RFB = 270 Ω.
17.
Status Flag output is an open drain output requiring a pull-up resistor to logic VDD.
18.
19.
Status Flag Leakage Current is measured with Status Flag HIGH and not SET.
Status Flag Set Voltage measured with Status Flag LOW and SET with I SF = 300 μA. Maximum allowable sink current from this pin is
< 500 μA . Maximum allowable pull-up voltage < 7.0 V.
34932
8
NXP Semiconductors
4.3
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 36 V, - 40 °C ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min.
Typ.
Max.
Unit
f PWM
–
–
–
–
11
20
kHz
f MAX
–
–
20
kHz
t DON
–
–
18
μs
t DOFF
–
–
12
μs
ILIM Output Constant-OFF Time(23),(25)
tA
15
20.5
32
μs
ILIM Blanking Time(24),(25)
tB
12
16.5
27
μs
Disable Delay Time(26)
t DDISABLE
–
–
8.0
μs
t F, t R
1.9
0.2
3.9
1.1
8.0
1.5
μs
Short-circuit /Overtemperature Turn-OFF (Latch-OFF) Time(28),(29)
t FAULT
–
–
8.0
μs
Power-ON Delay Time(29)
t POD
–
1.0
5.0
ms
Output MOSFET Body Diode Reverse Recovery Time(29)
tRR
75
100
150
Charge Pump Operating Frequency(29)
fCP
–
7.0
–
Timing characteristics
PWM Frequency(20)
• MC34932EK
• MC34932SEK
Maximum Switching Frequency During Current Limit Regulation(21)
Output ON Delay(22)
• VPWR = 24 V
Output OFF Delay(22)
• VPWR = 24 V
Output Rise and Fall Time(27)
• MC34932EK
• MC34932SEK
ns
MHz
Notes
20. The maximum PWM frequency should be limited to frequencies < 11 kHz for MC34932EK and < 20 kHz for MC34932SEK in order to allow the
internal high-side driver circuitry time to fully enhance the high-side MOSFETs at a duty cycle range of 15 to 85%.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s inductance,
capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM frequency during current
limit.
22. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction) of the
OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of the output response
signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the output response signal. See
Figure 4, page 10.
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so the short-circuit detection threshold comparators may have time to act.
25. Parameter guaranteed by characterization.
26. * Disable Delay Time measurement is defined in Figure 5, page 10.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 24 V,
RLOAD = 3.0 ohm. See Figure 6, page 10.
28.
29.
Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents possess a
di/dt which ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short-circuit event detection and causing the
shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode may cause junction
temperatures to rise. Junction temperatures above ~160 °C causes the output current limit threshold to “fold back”, or decrease, until ~175 °C is
reached, after which the tLIM thermal latch-OFF occurs. Permissible operation within this fold back region is limited to non-repetitive transient events
of duration not to exceed 30 seconds (see Figure 9).
Parameter is Guaranteed By Design.
34932
NXP Semiconductors
9
VIN1, IN2 (V)
Timing diagrams
5.0
VOUT1, 2 (V)
4.4
VPWR
1.5 V
1.5 V
0
t DON
t DOFF
80%
20%
0
TIME
5.0 V
1.5 V
0V
IO = 100 mA
VOUT1, 2
VD1, EN/D2 (V)
Figure 4. Output delay time
tDDISABLE
90%
0V
TIME
Figure 5. Disable delay time
VOUT1, 2 (V)
.
tF
VPWR
tR
90%
90%
10%
0
10%
TIME
Figure 6. Output switching time
Overload Condition
IOUT, CURRENT (A)
9.0
ISC Short-circuit Detection Threshold
tB
6.5
0.0
5.0
tB = ILIM Blanking Time
tA = Constant-OFF Time (OUT1 and OUT2 Tri-stated)
tA
ILIM
t ON
TIME
Figure 7. Current limit blanking time and constant-off time
34932
10
NXP Semiconductors
Short-circuit Condition
t FAULT
IOUT, CURRENT (A)
9.0
ISC Short-circuit Detection Threshold
Hard Short Occurs
tB
6.5
OUT1, OUT2 Tri-stated,
SF set Low
ILIM
0.0
5.0
t B (~16 μs)
TIME
Figure 8. Short-circuit detection turn-off time tFAULT
.
Current Limit Threshold Foldback.
Operation within this region must be
limited to non-repetitive events not to
exceed 30 s per 24 hr.
ILIM, CURRENT (A)
6.5
4.2
tSEP
tLIM
Thermal Shutdown
tHYS
tFB
tLIM
Figure 9. Output current limiting foldback region
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5
Functional description
5.1
Introduction
The 34932 has two identical H-Bridge drivers in the same package. The only connection shared internally is the Analog Ground (AGND).
This description is given for the H-Bridge A half of the total device. However, the H-Bridge B half exhibits identical behavior.
Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make
the 34932 a very attractive, cost-effective solution for controlling a broad range of small DC motors. The 34932 outputs are capable of
supporting peak DC load currents of up to 5.0 A from a 36 V VPWR source. An internal charge pump and gate drive circuitry which can
support external PWM frequencies up to 11 kHz in MC34932EK and 20 kHz in MC34932SEK.
The 34932 has an analog feedback (current mirror) output pin (the FB pin) which provides a constant-current source ratioed to the active
high-side MOSFETs’ current. This can be used to provide monitoring of output current to facilitate closed-loop operation for motor speed/
torque control, or for the detection of open load conditions.
Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. Two independent disable inputs, D1 and
EN/D2, provide the means to force the H-bridge outputs to a high-impedance state (all H-bridge switches OFF). The EN/D2 pin also
controls an enable function allowing the IC to be placed in a power-conserving Sleep mode.
The 34932 has output current limiting (via constant OFF-time PWM current regulation), output short-circuit detection with latch-OFF, and
overtemperature detection with latch-OFF. Once the device is latched-OFF due to a fault condition, either of the disable inputs (D1 or EN/
D2), or VPWR must be to clear the status flag.
Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering.
The current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold. This means the
current limit threshold is reduced to around 4.2 A as the junction temperature increases above 160 °C. When the temperature is above
175 °C, overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to continue operating for short
periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load.
5.2
Functional pin description
5.2.1
Power ground and analog ground (PGND and AGND)
The power and analog ground pins should be connected together with a very low-impedance connection.
5.2.2
Positive power supply (VPWR)
VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as
short as possible traces, offering as low an impedance as possible between pins.
5.2.3
Status flag (SF)
This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to VDD. The
maximum VDD is < 7.0 V. Refer to Table 6 for the SF Output status definition.
5.2.4
Input 1, 2 and disable input 1 (IN1, IN2, and D1)
These pins are input control pins used to control the outputs. These pins are 3.0 V/5.0 V CMOS-compatible inputs with hysteresis. IN1
and IN2 independently control OUT1 and OUT2, respectively. D1 input is used to tri-state disable the H-Bridge outputs.
When D1 is SET (D1 = logic HIGH) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device
circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 4.
5.2.5
H-Bridge output (OUT1, OUT2)
These pins are the outputs of the H-bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1,
and EN/D2 inputs. The outputs have PWM current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state
latch-OFF) with hysteresis as well as short circuit latch-OFF protection.
A disable timer (time t B) is incorporated to distinguish between load currents higher than the ILIM threshold and short circuit currents. This
timer is activated at each output transition.
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5.2.6
Charge pump capacitor (CCP)
This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is from 30
to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly without the external
reservoir capacitor.
5.2.7
Enable input/disable input 2 (EN/D2)
The EN/D2 pin performs the same function as D1 pin, when it goes to a logic LOW the outputs are immediately tri-stated. It is also used
to place the device in a Sleep mode so as to consume very low currents. When the EN/D2 pin voltage is a logic LOW state, the device is
in the Sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pull-down resistor
maintains the device in Sleep mode in the event EN is driven through a high-impedance I/O or an unpowered microcontroller, or the EN/
D2 input becomes disconnected.
5.2.8
Feedback (FB)
The 34932 has a feedback output (FB) for monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for motor
speed and torque control.
The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction, a
ground-referenced 0.24% of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback
current can be converted to a proportional voltage equivalent and the controlling microcontroller can measure the current proportional
voltage with its analog-to-digital converter (ADC). This is intended to provide the user with only first-order motor current feedback for motor
torque control. The resistance range for the linear operation of the FB pin is 100 Ω < RFB < 300 Ω.
If PWM-ing is implemented using the disable pin input (only D1), a small filter capacitor (~1.0 µF) may be required in parallel with the RFB
resistor to ground for spike suppression.
5.3
Functional internal block description
MC34932 - Functional Block Diagram
Analog Control & Protection
Voltage Regulation
Current Sense
Temperature Sense
H-Bridge
Output Drivers
Charge Pump
Gate Control Logic
Input Logic Control
Fault Logic
OUT1 - OUT2
Protection Logic Control
MCU Interface
Analog Control & Protection
Logic and Control
H-Bridge Output Drivers
Figure 10. Functional internal block diagram
5.3.1
Analog control and protection circuitry
An on-chip voltage regulator supplies the internal logic. The charge pump provides gate drive for the H-Bridge MOSFETs. The Current
and Temperature sense circuitry provides detection and protection for the output drivers. Output undervoltage protection shuts down the
MOSFETS.
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5.3.2
Gate control logic
The 34932 is a monolithic H-Bridge Power IC designed primarily for any low-voltage DC servo motor control application within the current
and voltage limits stated for the device. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two
independent disable inputs are provided to force the H-Bridge outputs to tri-state (high-impedance off-state).
5.3.3
H-Bridge output drivers: OUT1 and OUT2
The H-Bridge is the power output stage. The current flow from OUT1 to OUT2 is reversible and under full control of the user by way of the
Input Control Logic. The output stage is designed to produce full load control under all system conditions. All protective and control
features are integrated into the control and protection blocks. The sensors for current and temperature are integrated directly into the
output MOSFET for maximum accuracy and dependability.
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Functional device operation
6.1
Operational modes
SF LOGIC OUT
EN/D2 LOGIC IN
D1 LOGIC IN
INn LOGIC IN
ILOAD OUTPUT CURRENT (A)
6
9.0
Typical Short-circuit Detection Threshold
6.5
Typical Current Limit Threshold
High Current Load Being Regulated via Constant-OFF-Time PWM
PWM
Current
Limiting
Moderate Current Load
Hard Short Detection and Latch-OFF
0
[1]
[0]
IN1 IN2
IN1 or IN2
IN1 or IN2
IN2 or IN1
IN2 or IN1
[1]
[0]
[1]
[0]
[1]
Outputs
[0]
Tri-stated
Outputs
Tri-stated
Outputs Operation
(per Input Control Condition)
Time
Figure 11. Operating states
6.2
Logic commands
Table 6. Truth table
The tri-state conditions and the status flag are reset using D1 or D2. The truth table uses the following notations: L = LOW, H = HIGH, X
= HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.
Device state
Input conditions
Status
Outputs
EN/D2
D1
IN1
IN2
SF
OUT1
OUT2
Forward
H
L
H
L
H
H
L
Reverse
H
L
L
H
H
L
H
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Table 6. Truth table
The tri-state conditions and the status flag are reset using D1 or D2. The truth table uses the following notations: L = LOW, H = HIGH, X
= HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.
Input conditions
Device state
Status
Outputs
EN/D2
D1
IN1
IN2
SF
OUT1
OUT2
Freewheeling Low
H
L
L
L
H
L
L
Freewheeling High
H
L
H
H
H
H
H
Disable 1 (D1)
H
H
X
X
L
Z
Z
IN1 Disconnected
H
L
Z
X
H
H
X
IN2 Disconnected
H
L
X
Z
H
X
H
D1 Disconnected
H
Z
X
X
L
Z
Z
Undervoltage Lockout(30)
H
X
X
X
L
Z
Z
Overtemperature(31)
H
X
X
X
L
Z
Z
Short-circuit(31)
H
X
X
X
L
Z
Z
Sleep mode EN/D2
L
X
X
X
H
Z
Z
EN/D2 disconnected
Z
X
X
X
H
Z
Z
Notes
30. In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage recovery, status flag is reset
automatically or automatically cleared and the outputs are restored to their original operating condition.
31. When a short-circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals and the
status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1, EN/D2, or VPWR.
Forward
Load
Current
OFF
OUT2
ON
OFF
OFF
ON
ON
OUT1
OUT1
LOAD
OUT2
ON
LOAD
OUT2
ON
OFF
PGND
VPWR
VPWR
Load
Current
ON
LOAD
Low-Side Recirculation
(Forward)
VPW R
V PW R
VPWR
VPWR
Load
Current
OUT1
Reverse
High-Side Recirculation
(Forward)
V PW R
V PW R
OUT1
PGND
LOAD
OUT2
Load
Current
ON
ON
PGND
PGND
PGND
OFF
OFF
OFF
PGND
OFF
PGND
PGND
Figure 12. 34932 power stage operation
6.3
Protection and diagnostic features
6.3.1
Short-circuit protection
If an output short-circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and
the fault status output flag (SF) is SET to logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the EN/D2 input changes
from logic LOW to logic HIGH, the output bridge becomes operational again and the fault status flag resets (cleared) to a logic HIGH state.
The output stage always switches into the mode defined by the input pins (IN1, IN2, D1, and EN/D2), provided the device junction
temperature is within the specified operating temperature range.
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6.3.2
Internal PWM current limiting
The maximum current flow under normal operating conditions should be less than 5.0 A. The instantaneous load currents is limited to ILIM
via the internal PWM current limiting circuitry. When the ILIM threshold current value is reached, the output stages are tri-stated for a fixed
time (T A) of 20 µs typical. Depending on the time constant associated with the load characteristics, the output current decreases during
the tri-state duration until the next output ON cycle occurs.
The PWM current limit threshold value is dependent on the device junction temperature. When - 40 °C < TJ < 160 °C, ILIM is between the
specified minimum/maximum values. When TJ exceeds 160 °C, the ILIM threshold decreases to 4.2 A. Shortly above 175 °C the device
overtemperature circuit detects tLIM and an overtemperature shutdown occurs. This feature implements a graceful degradation of
operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the motor’s gear-reduction train
to be handled.
Important:
Die temperature excursions above 150 °C are permitted only for non-repetitive durations < 30 seconds. Provision must be made at the
system level to prevent prolonged operation in the current-foldback region.
6.3.3
Overtemperature shutdown and hysteresis
If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag (SF) is SET to logic LOW.
To reset from this condition, D1 must change from logic HIGH to logic LOW, or EN/D2 must change from logic LOW to logic HIGH. When
reset, the output stage switches ON again, provided the temperature is below the overtemperature threshold limit, EN/D2 clears the fault.
When the junction temperature is below the overtemperature threshold limit minus the hysteresis, D1 clears the fault.
Important:
Resetting from the fault condition clears the fault status flag. Powering down and powering up the device also resets the 34932 from the
fault condition.
6.3.4
Output avalanche protection
If VPWR were to become an open circuit, the outputs would likely tri-state simultaneously due to the disable logic. This could result in an
unclamped inductive discharge. The VPWR input to the 34932 should not exceed 40 V during this transient condition, to prevent electrical
overstress of the output drivers.This can be accomplished with a zener clamp or MOV, and/or an appropriately valued input capacitor with
sufficiently low ESR (see Figure 13).
VPW R
VPW R
Bulk
Low ESR
Cap.
100nF
OUT1
M
9
I/Os
OUT2
AGND
PGND
Figure 13. Avalanche protection
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7
Typical applications
7.1
Introduction
A typical application schematic is shown in Figure 14. For precision high-current applications in harsh, noisy environments, the VPWR bypass capacitor may need to be substantially larger.
VPWR
100 μF
100 nF
VPWRA
33 nF
LOGIC SUPPLY
CCPA
VDD
VCP CHARGE
PUMP
HS1
HS2
OUT1
M
TO GATES
OUT2
HS1
IN1
IN2
EN/D2
D1
+5.0 V
STATUS
FLAG
TO
ADC RFB
270 Ω
SFA
LS1
LS2
LS1
HS2
GATE DRIVE
AND
PROTECTION
LOGIC
PGND
LS2
VSENSE
ILIM PWM
FBA
CURRENT MIRRORS
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
1.0 μF
AGNDA
PGNDA
Figure 14. 34932 typical application schematic 1/2 device
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Packaging
8.1
Package dimensions
For the most current package revision, visit www.nxp.com and perform a keyword search using the 98Axxxxxxxxx listed below.
Dimensions shown are provided for reference ONLY.
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9
Thermal addendum
9.1
Introduction
This thermal addendum is provided as a supplement to the MC34932 technical datasheet. The addendum provides thermal performance
information critical in the design and development of system applications. All electrical, application, and packaging information is provided
in the datasheet.
9.2
Package and thermal considerations
The MC34932 is offered in a 54-pin SOICW-EP. There is a single heat source (P), a single junction temperature (TJ), and thermal
resistance (RθJA).
TJ
=
RθJA
.
P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This
methodology is not meant to, and does not predict the performance of a package in an application-specific environment. Stated values
were obtained by measurement and simulation according to the standards listed below.
Table 7. Table of thermal resistance data
Rating
Value
Unit
Notes
Junction to Ambient
Natural Convection
Single Layer board (1s)
RθJA
58.8
°C/W
(32),(33)
Junction to Ambient
Natural Convection
Four layer board (2s2p)
RθJA
24.4
°C/W
(32),(34)
Junction to Board
RθJB
7.0
°C/W
(35)
Junction to Case (bottom / flag)
RθJC (bottom)
0.36
°C/W
(38)
Junction to Case (top)
RθJC (top)
18.0
°C/W
(36)
ΨJT
2.0
°C/W
(37)
Junction to Package Top
Natural Convection
Notes
32. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
33. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
34. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
35. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
36. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
37. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
38. Thermal resistance between the die and the case bottom/flag surface (simulated) (flag bottom side fixed to ambient temperature).
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Figure 15. Transient thermal resistance RθJA MC34932EK on 2s2p test board
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Figure 16. Typical duty cycle linearity over frequency at 36 V for MC34932SEK
Operating the part continuously at more than 24 V and up to 36 V while switching the outputs at high frequencies causes additional power
dissipation on the die due to high switching losses. This could result in junction temperature (TJ) exceeding the thermal foldback
temperature (TFB) and even thermal shutdown (TLIM) threshold. Hence, while operating the part at such conditions, it is important to
consider methods to keep the junction temperature (TJ) below 165 °C to prevent the part exceeding the thermal foldback temperature
threshold (TFB) and limit the current internally.
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Reference section
Table 8. Thermal analysis reference documents
Reference
Description
AN4146
Thermal Modeling and Simulation of 12V Gen3 eXtreme Switch Devices with SPICE
BASICTHERMALWP
Basic Principles of Thermal Analysis for Semiconductor Systems
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11
Revision history
Revision
Date
1.0
7/2013
2.0
10/2013 •
3.0
4.0
Description
•
Reduced the sleep mode current specifications
•
Updated as per PCN # 16555
Added new part number MC34931SEK with higher slew rate to support PWM frequency up to 20 kHz
Updated the operating voltage up to 36 V (max.) after characterization and testing
Changed the rise/fall time, sleep current, output leakage current, sleep and stand-by current based on test and
characterization data
Added performance curves of key parameters to show operation up to 36 V
9/2015
•
•
Changed the document classification from Advance Information to Technical Data
Added a column for PWM frequency to Table 1
8/2016
•
Updated to NXP document form and style
2/2015
•
•
•
•
Initial Release based the 33932 Data sheet
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Document Number: MC34932
Rev. 4.0
8/2016
