Freescale Semiconductor
Advance Information
Document Number: MC34981
Rev. 2.0, 9/2013
Single High Side Switch
(4.0 mOhm), PWM clock up to
60 kHz
34981
Industrial
The 34981 is a high frequency, self-protected 4.0 m RDS(ON) high
side switch used to replace electromechanical relays, fuses, and
discrete devices in power management applications.
The 34981 can be controlled by pulse-width modulation (PWM) with
a frequency up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features. The 34981 is suitable for loads with high
inrush current, as well as motors and all types of resistive and inductive
loads.
The 34981 is packaged in a 12 x 12 mm non-leaded power-enhanced
PQFN package with exposed tabs.
This device is powered by SMARTMOS technology.
Features
•
•
•
•
•
•
•
•
•
Single 4.0 m RDS(ON) maximum high side switch
PWM capability up to 60 kHz with duty cycle from 5% to 100%
Very low standby current
Slew-rate control with external capacitor
Overcurrent and overtemperature protection, undervoltage
shutdown, and fault reporting
Reverse supply protection
Gate drive signal for external low side N-channel MOSFET with
protection features
Output current monitoring
Temperature feedback
VDD
HIGH SIDE SWITCH
Bottom View
FK (Pb-Free Suffix)
98ARL10521D
16-PIN PQFN (12 X 12)
Applications:
•
•
•
•
•
DC motors
Solenoids
Power distribution
Heating elements
Pumps
VPWR
VDD
34981
CONF
MCU
I/O
FS
I/O
INLS
I/O
EN
I/O
A/D
INHS
TEMP
A/D
CSNS
VPWR
CBOOT
OUT
DLS
GLS
OCLS SR GND
Figure 1. 34981 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
M
ORDERABLE PARTS
ORDERABLE PARTS
Table 1. Orderable Part Variations
Part Number (1)
Notes
MC34981ABHFK
Temperature (TA)
Package
-40 to 125 °C
16 PQFN
Notes
1. To Order parts in Tape & Reel, add the R2 suffix to the part number.
34981
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Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
Undervoltage
Detection
Temperature
Feedback
TEMP
CBOOT
Bootstrap Supply
SR
Gate Driver
Slew Rate Control
FS
EN
Logic
INHS
INLS
Current Protection
Overtemperature
Detection
OUT Current
Recopy
5.0V
RDWN
OUT
IDWN
5.0 V
Low Side
Gate Driver
and Protection
GLS
DLS
ICONF
CONF
IOCLS
CrossConduction
GND
CSNS
OCLS
Figure 2. 34981 Simplified Internal Block Diagram
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
Package Transparent Top View
CSNS
TEMP
EN
INHS
FS
INLS
CONF
OCLS
DLS
GLS
SR
CBOOT
4
5
6
7
8
9
1
2
3
10
11
12
GND
13
VPWR
14
15
16
OUT
OUT
Figure 3. Pin Connections
Descriptions of the pins listed in the table below can be found in the Functional Description section located on page 15.
Table 2. PIN DEFINITIONS
Pin
Number
Pin Name
Pin
Function
Formal Name
1
CSNS
Reports
Output Current Monitoring
2
TEMP
Reports
Temperature Feedback
3
EN
Input
Enable
(Active High)
4
INHS
Input
Serial Input High Side
5
FS
Reports
Fault Status
(Active Low)
6
INLS
Input
Serial Input Low Side
7
CONF
Input
Configuration Input
This input manages MOSFET N-channel cross-conduction.
8
OCLS
Input
Low Side Overload
This pin sets the VDS protection level of the external low side MOSFET.
9
DLS
Input
Drain Low Side
This pin is the drain of the external low side N-channel MOSFET.
10
GLS
Output
Low Side Gate
This output pin drives the gate of the external low side N-channel
MOSFET.
11
SR
Input
Slew Rate Control
12
CBOOT
Input
Bootstrap Capacitor
13
GND
Ground
Ground
14
VPWR
Input
Positive Power Supply
15, 16
OUT
Output
Output
Definition
This pin is used to generate a ground-referenced voltage for the
microcontroller (MCU) to monitor output current.
This pin is used by the MCU to monitor board temperature.
This pin is used to place the device in a low-current Sleep mode.
This input pin is used to control the output of the device.
This pin monitors fault conditions and is active LOW.
This pin is used to control an external low side N-channel MOSFET.
This pin controls the output slew rate.
This pin provides the high pulse current to drive the device.
This is the ground pin of the device.
This pin is the source input of operational power for the device.
These pins provide a protected high side power output to the load
connected to the device.
34981
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
VPWR
Steady-state
-16 to 41
Input/Output Pins Voltage(2)
Output Voltage
INHS, INLS,
CONF, CSNS, FS,
TEMP, EN
- 0.3 to 7.0
VOUT
Positive
V
V
41.0
Negative
Continuous Output Current
V
-5.0
(3)
IOUT
40.0
A
ICL(CSNS)
15.0
mA
ICL(EN)
2.5
mA
VSR
- 0.3 to 54.0
V
CBOOT Voltage
CBOOT
- 0.3 to 54.0
V
OCLS Voltage
VOCLS
- 5.0 to 7.0
V
Low Side Gate Voltage
VGLS
- 0.3 to 15.0
V
Low Side Drain Voltage
VDLS
- 5.0 to 41.0
V
CSNS Input Clamp Current
EN Input Clamp Current
SR Voltage
ESD
Voltage(4)
Human Body Model (HBM)
VESD
V
± 2000
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
± 750
All Other Pins (2-11, 13-14)
± 500
Notes
2. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN pins may cause a malfunction or permanent damage to the
device.
3. Continuous high side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
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Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
THERMAL RATINGS
Operating Temperature
°C
Ambient
TA
- 40 to 125
Junction (5)
TJ
- 40 to 150
TSTG
- 55 to 150
RJC
1.0
RJA
30.0
TPPRT
Note 8
Storage Temperature
(6)
Thermal Resistance
C/W
Junction to Power Die Case
Junction to Ambient
Peak Package Reflow Temperature During
C
Reflow(7), (8)
°C
Notes
5. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not
exceed 125C.
6. Device mounted on a 2s2p test board per JEDEC JESD51-2.
7. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Fully Operational
6.0
–
27.0
Extended(9)
4.5
–
27.0
–
10.0
12.0
–
10.0
12.0
Unit
POWER INPUT (VPWR)
Supply Voltage Range
VPWR
VPWR Supply Current
V
IPWR(ON)
INHS = 1 and OUT Open, INLS = 0
VPWR Supply Current
mA
IPWR(SBY)
INHS = INLS = 0, EN = 5.0 V, OUT Connected to GND
Sleep-state Supply Current
mA
A
IPWR(SLEEP)
(VPWR < 14 V, EN = 0 V, OUT Connected to GND)
TA = 25 C
–
–
5.0
TA = 125 C
–
–
50.0
Undervoltage Shutdown
VPWR(UV)
2.0
4.0
4.5
V
Undervoltage Hysteresis
VPWR(UVHYS)
0.05
0.15
0.3
V
VPWR = 6.0 V
–
–
6.0
VPWR = 9.0 V
–
–
5.0
VPWR = 13.0 V
–
–
4.0
VPWR = 6.0 V
–
–
10.2
VPWR = 9.0 V
–
–
8.5
VPWR = 13.0 V
–
–
6.8
–
–
8.0
75
100
125
–
1/20000
–
POWER OUTPUT (IOUT, VPWR)
Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 25 C)
Output Drain-to-Source ON Resistance (IOUT = 20 A, TA = 150 C)
Output Source-to-Drain ON Resistance (IOUT = -20 A, TA = 25
C)(10)
RDS(ON)25
RDS(ON)150
A
CSR
9.0 V < VPWR < 16 V, CSNS < 4.5 V
Current Sense Ratio (CSR) Accuracy
m
I OCH
9.0 V < VPWR < 16 V
Current Sense Ratio
m
RSD(ON)
VPWR = - 12 V
Output Overcurrent Detection Level
m
–
CSR_ACC
%
9.0 V < VPWR < 16 V, CSNS < 4.5 V
Output Current
5.0 A
-20
–
20
15 A, 20 A, and 30 A
-15
–
15
Notes
9. OUT can be commanded fully on, PWM is available at room. Low Side Gate driver is available. Protections and Diagnosis are not
available. Min/max parameters are not guaranteed.
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
4.5
6.0
7.0
0
13
17
TSD
160
175
190
°C
TSDHYS
5.0
–
20
C
5.0
5.4
6.0
POWER OUTPUT (VPWR) (continued)
Current Sense Voltage Clamp
VCL(CSNS)
I CSNS = 15 mA
Current Sense Leakage(11)
V
A
ILEAK(CSNS)
I NHS = 1 with OUT opened of load or INHS = 0
Overtemperature Shutdown
(12)
Overtemperature Shutdown Hysteresis
LOW SIDE GATE DRIVER (VPWR, VGLS, VOCLS)
Low Side Gate Voltage
VGLS
VPWR = 6.0 V
V
VPWR = 9.0 V
8.0
8.4
9.0
VPWR = 13 V
12.0
12.4
13.0
VPWR = 27 V
12.0
12.4
13.0
Low Side Gate Sinked Current
I GLSNEG
VGLS = 2.0 V, VPWR = 13 V
Low Side Gate Sourced Current
–
100
–
–
100
–
-50
–
+50
I GLSPOS
VGLS = 2.0 V, VPWR = 13 V
Low Side Overload Detection Level versus Low Side Drain Voltage
mA
mA
VDS_LS
VOCLS - VDLS, (VOCLS V
mV
CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS)
Input Logic High-voltage (CONF, INHS, INLS)
VIH
3.3
–
–
V
Input Logic Low-voltage (CONF, INHS, INLS)
VIL
–
–
1.0
V
VINHYS
100
600
1200
mV
Input Logic Active Pull-down Current (INHS, INLS)
IDWN
5.0
10
20
A
Enable Pull-down Resistor (EN)
RDWN
100
200
400
k
Enable Voltage Threshold (EN)
VEN
Input Logic Voltage Hysteresis (CONF, INHS, INLS)
Input Clamp Voltage (EN)
Input Active Pull-up Current (OCLS)
Input Active Pull-up Current (CONF)
V
VCLEN
IEN < 2.5 mA
Input Forward Voltage (EN)
2.5
V
7.0
–
14
VF(EN)
-2.0
–
-0.3
V
IOCLS p
50
100
200
A
I CONF
5.0
10
20
A
Notes
11. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations
but not tested in production.
12. Parameter is guaranteed by process monitoring but is not production tested.
34981
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
FS Tri-state Capacitance(13)
CFS
–
–
20
pF
FS Low-state Output Voltage
VFSL
–
0.2
0.4
CONTROL INTERFACE (CONF, INHS, INLS, EN, OCLS) (continued)
IFS = -1.6 mA
Temperature Feedback
V
VTFEED
TA = 25°C for VPWR = 14 V
Temperature Feedback
V
Derating(13)
DTFEED
3.35
3.45
3.55
-8.5
-8.9
-9.3
mV/°C
Notes
13. Parameter is guaranteed by process monitoring but is not production tested.
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Charge Blanking Time (CBOOT)(15)
t ON
10
25
50
s
Output Rising Slew Rate
SRR
CONTROL INTERFACE AND POWER OUTPUT TIMING (CBOOT, VPWR)
VPWR = 13 V, from 10% to 90% of VOUT, SR Capacitor = 4.7 nF,
RL= 5.0
Output Falling Slew Rate
8.0
Output Turn-ON Delay
Output PWM ratio at 60
kHz(18)
Time to Reset Fault Diagnosis
35
200
400
700
500
1000
1500
f PWM
–
20
60
kHz
R PWM
5.0
–
95
%
100
200
400
1.0
10
20
t DLYON
ns
t DLYOFF
ns
t RSTDIAG
(overload on high side or external low side)
Output Overcurrent Detection Time
V/s
16
VPWR = 13 V, SR Capacitor = 4.7 nF
Input Switching Frequency(14)
35
8.0
VPWR = 13 V, SR Capacitor = 4.7 nF
Output Turn-OFF Delay Time(17)
16
SRF
VPWR = 13 V, from 90% to 10% of VOUT, SR Capacitor = 4.7 nF,
RL= 5.0
Time(16)
V/s
t OCH
s
s
Notes
14. The 34981 fully operates down to DC. To reset a latched Fault the INHS pin must go low for the “Time to reset Fault Diagnosis” (tRSTDIAG).
15.
16.
Values for CBOOT=100 nF. Refer to Sleep Mode on page 16. Parameter is guaranteed by design and not production tested.
Turn-ON delay time measured from rising edge of INHS that turns the output ON to VOUT = 0.5 V with RL= 5.0 resistive load.
17.
Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to VOUT = VPWR -0.5 V with RL= 5.0 resistive load.
18.
The ratio is measured at VOUT = 50% VPWR without SR capacitor. The device is capable of 100% duty cycle.
34981
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
INHS
5.0 V
0.0 V
VOUT
RPWM
VPWR - 0.5 V
50%VPWR
0.5 V
t DLY(ON)
t DLY(OFF)
VOUT
90% Vout
10% Vout
SR R
SR F
Figure 4. Time Delays Functional Diagrams
EN
FS
t ON After
5.0 V
CONF
INHS
INLS
OUT
GLS
Figure 5. Normal Mode, Cross-Conduction Management
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
EN
FS
t ON After
CONF
INHS
0.0 V
High Side ON
High Side OFF
INLS
OUT
GLS
Figure 6. Normal Mode, Independent High Side and Low Side
34981
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
7.0
RDS(ON)
(m)
RdsON
(mOhm)
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-50
0
50
100
150
200
Temperature (°C)
Temperature
(°C)
IIpwr(sleep)(µA)
PWR(SLEEP) (A)
Figure 7. Typical RDS(ON) vs. Temperature at VPWR = 13 V
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
4.5
6.0
9.0
12.0
12.5
13.0
14.0
17.0
21.0
V
Vpwr(V)
PWR (V)
Figure 8. Typical Sleep-state Supply Current vs. VPWR at 150 °C
Vout Rise Time (ns)
1600
1400
1200
1000
800
600
400
200
0
0
2.0
4.0
6.0
8.0
10
SR Capacitor (nF)
Figure 9. VOUT Rise Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Vout Fall Time (ns)
1600
1400
1200
1000
800
600
400
200
0
0
2.0
4.0
6.0
8.0
10
SR Capacitor (nF)
Figure 10. VOUT Fall Time vs. SR Capacitor From 10% to 90% of VOUT at 25 °C and VPWR = 13 V
34981
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34981 is a high-frequency self-protected silicon
4.0 mRDS(ON) high side switch used to replace
electromechanical relays, fuses, and discrete devices in
power management applications. The 34981 can be
controlled by pulse-width modulation (PWM) with a frequency
up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features.
The 34981 is suitable for loads with high inrush current, as
well as motors and all types of resistive and inductive loads.
A dedicated parallel input is available for an external low side
control with protection features and cross-conduction
management.
FUNCTIONAL PIN DESCRIPTIONS
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the high
side OUT current and is used externally to generate a
ground-referenced voltage for the microcontroller (MCU) to
monitor OUT current.
TEMPERATURE FEEDBACK (TEMP)
This pin reports an analog value proportional to the
temperature of the GND flag (pin 13). It is used by the MCU
to monitor board temperature.
ENABLE [ACTIVE HIGH] (EN)
This is an input used to place the device in a low-current
Sleep Mode. This pin has an active passive internal pulldown.
INPUT HIGH SIDE (INHS)
The input pin is used to directly control the OUT. This input
has an active internal pull-down current source and requires
CMOS logic levels.
two MOSFETs are controlled independently. When CONF is
at VDD 5.0 V, the two MOSFETs cannot be on at the same
time.
LOW SIDE OVERLOAD (OCLS)
This pin sets the VDS protection level of the external low
side MOSFET. This pin has an active internal pull-up current
source. It must be connected to an external resistor.
DRAIN LOW SIDE (DLS)
This pin is the drain of the external low side N-channel
MOSFET. Its monitoring allows protection features: low side
short protection and VPWR short protection.
LOW SIDE GATE (GLS)
This pin is an output used to drive the gate of the external
low side N-channel MOSFET.
SLEW RATE CONTROL (SR)
A capacitor connected between this pin and ground is
used to control the output slew rate.
FAULT STATUS (FS)
This pin is an open drain-configured output requiring an
external pull-up resistor to VDD (5.0 V) for fault reporting.
When a device fault condition is detected, this pin is active
LOW.
INPUT LOW SIDE (INLS)
This input pin is used to directly control an external low
side N-channel MOSFET and has an active internal pulldown current source and requires CMOS logic levels. It can
be controlled independently of the INHS depending of CONF
pin.
CONFIGURATION INPUT (CONF)
This input pin is used to manage the cross-conduction
between the internal high side N-channel MOSFET and the
external low side N-channel MOSFET. The pin has an active
internal pull-up current source. When CONF is at 0 V, the
BOOTSTRAP CAPACITOR (CBOOT)
A capacitor connected between this pin and OUT is used
to switch the OUT in PWM mode.
GROUND (GND)
This pin is the ground for the logic and analog circuitry of
the device.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source input of operational power for the device. The VPWR
pin is a backside surface mount tab of the package.
OUTPUT (OUT)
Protected high side power output to the load. Output pins
must be connected in parallel for operation.
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
NORMAL MODE
The 34981 has 2 operating modes: Sleep and Normal
depending on EN input.
SLEEP MODE
Sleep Mode is the state of the 34981 when the EN is
logic [0]. In this mode, OUT, the gate driver for the external
MOSFET, and all unused internal circuitry are off to minimize
current draw.
The 34981 goes to the Normal operating mode when the
EN pin is logic [1]. The INHS and INLS commands are
disabled t ON after the EN transitions to logic [1] to enable the
charge of the bootstrap capacitor.
Table 6. Operating Modes
Condition
CONF INHS
INLS
OUT
GLS
FS
EN
Comments
Sleep
x
x
x
x
x
H
L
Device is in Sleep Mode. The OUT and low side gate are OFF.
Normal
L
H
H
H
H
H
H
Normal mode. High side and low side are controlled
independently. The high side and the low side are both on.
Normal
L
L
L
L
L
H
H
Normal mode. High side and low side are controlled
independently. The high side and the low side are both off.
Normal
L
L
H
L
H
H
H
Normal mode. Half-bridge configuration. The high side is off
and the low side is on.
Normal
L
H
L
H
L
H
H
Normal mode. Half-bridge configuration. The high side is on
and the low side is off.
Normal
H
PWM
H
PWM
PWM_bar
H
H
Normal mode. Cross-conduction management is activated.
Half-bridge configuration.
H = High level
L = Low level
x = Don’t care
PWM_bar = Opposite of pulse-width modulation signal.
PROTECTION AND DIAGNOSTIC FEATURES
UNDERVOLTAGE
The 34981 incorporates undervoltage protection. In case
of VPWR VOCLS, the GLS pin goes to 0 V and the OCLS
internal current source is disconnected and OCLS goes to
0 V. The GLS pin and the OCLS pin are reset (and the fault
is delatched) by a logic [0] at the INLS pin for at least
t RST(DIAG). Figure 13 and Figure 14 illustrate the behavior in
case of overload on the low side gate driver.
When connected to an external resistor, the OCLS pin with
its internal current source sets the VOCLS level. By changing
the external resistance, the protection level can be adjusted
depending on low side characteristics. A 33 k resistor gives
a VDS level of 3.3 V typical.
This protection circuitry measures the voltage between the
drain of the low side (DLS pin) and the 34981 ground (GND
pin). For this reason it is key the low side source, the 34981
ground and the external resistance ground connection, are
connected together in order to prevent false error detection
due to ground shifts.
The maximum OCLS voltage being 4.0 V, a resistor bridge
on DLS must be used to detect a higher voltage across the
low side.
CONFIGURATION
The CONF pin manages the cross-conduction between
the internal MOSFET and the external low side MOSFET.
With the CONF pin at 0 V, the two MOSFETs can be
independently controlled. A load can be placed between the
high side and the low side.
With the CONF pin at 5.0 V, the two MOSFETs cannot be
on at the same time. They are in half-bridge configuration as
shown in the 34981 Simplified Application Diagram. If INHS
and INLS are at 5.0 V at the same time, INHS has priority and
OUT is at VPWR. If INHS changes from 5.0 V to 0 V with INLS
at 5.0 V, GLS goes to high state as soon as the VGS of the
internal MOSFET is lower than 2.0 V typically. A half-bridge
application could consist in sending PWM signal to the INHS
pin and 5.0 V to the INLS pin with the CONF pin at 5.0 V.
Figure 20, illustrates the simplified application diagram in
the 34981 Simplified Application Diagram with a DC motor
and external low side. The CONF and INLS pins are at 5.0 V.
When INHS is at 5.0 V, current is flowing in the motor. When
INHS goes to 0 V, the load current recirculates in the external
low side.
BOOTSTRAP SUPPLY
Bootstrap supply provides current to charge the bootstrap
capacitor through the VPWR pin. A short time is required after
the application of power to the device to charge the bootstrap
capacitor. A typical value for this capacitor is 100 nF. An
internal charge pump allows continuous MOSFET drive.
When the device is in the sleep mode, this bootstrap supply
is off to minimize current consumption.
HIGH SIDE GATE DRIVER
The high side gate driver switches the bootstrap capacitor
voltage to the gate of the MOSFET. The driver circuit has a
low-impedance drive to ensure the MOSFET remains OFF in
the presence of fast falling dV/dt transients on the OUT pin.
This bootstrap capacitor connected between the power
supply and the CBOOT pin provides the high pulse current to
drive the device. The voltage across this capacitor is limited
to about 13 V typical.
An external capacitor connected between pins SR and
GND is used to control the slew rate at the OUT pin. Figure 9
and Figure 10 give VOUT rise and fall time versus different SR
capacitors.
LOW SIDE GATE DRIVER
The low side control circuitry is PWM capable. It can drive
a standard MOSFET with an RDS(ON) as low as 10.0 m at a
frequency up to 60 kHz. The VGS is internally clamped at
12 V typically to protect the gate of the MOSFET. The GLS
pin is protected against short by a local overtemperature
sensor.
THERMAL FEEDBACK
The 34981 has an analog feedback output (TEMP pin)
provides a value in inverse proportion to the temperature of
the GND flag (pin 13). The controlling microcontroller can
“read” the temperature proportional voltage with its analogto-digital converter (ADC). This can be used to provide realtime monitoring of the PC board temperature to optimize the
motor speed and to protect the whole electronic system.
TEMP pin value is VTFEED with a negative temperature
coefficient of DTFEED.
REVERSE SUPPLY
The 34981 survives the application of reverse supply
voltage as low as -16 V. Under these conditions, the output’s
gate is enhanced to decrease device power dissipation. No
additional passive components are required. The 34981
survives these conditions until the maximum junction rating is
reached.
In the case of reverse supply in a half-bridge application, a
direct current passes through the external freewheeling diode
and the internal high side.
As Figure 11 shows, it is essential to protect this power
line. The proposed solution is an external N-channel low side
with its gate tied to supply voltage through a resistor. A high
side in the VPWR line could be another solution.
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
GROUND (GND) DISCONNECT PROTECTION
VDD
MCU
VPWR
No current
If the DC motor module ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the output state at the time of
disconnection. A 10 k resistor needs to be added between
the EN pin and the rest of the circuitry in order to ensure the
device turns off in case of ground disconnect and to prevent
exceeding this pin’s maximum ratings.
34981
GND
OUT
FAULT REPORTING
VPWR
Diode
10.0 k
M
This 34981 indicates the faults below as they occur by
driving the FS pin to logic [0]:
• Overtemperature fault
• Overcurrent fault on OUT
• Overload fault on the external low side MOSFET
The FS pin returns to logic [1] when the over temperature
fault condition is removed. The two other faults are latched.
Figure 11. Reverse Supply Protection
34981
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Table 7. Functional Truth Table in Fault Mode
Conditions
CONF INHS
INLS
OUT
GLS
FS
EN
TEMP CSNS OCLS
Comments
Overtemperature
on OUT
x
x
x
L
H
L
H
L
x
x
The 34981 is currently in Fault mode.
The OUT is OFF. TEMP at 0V
indicates this fault. Once the fault is
removed 34981 recovers its normal
mode.
Overtemperature
on GLS
x
x
x
L
L
L
H
L
x
x
The 34981 is currently in Fault mode.
The OUT is OFF and GLS is at 0V.
TEMP at 0V indicates this fault. Once
the fault is removed 34981 recovers its
Normal Mode.
Overcurrent
on OUT
x
H
L
L
x
L
H
x
L
x
The 34981 is currently in Fault mode.
The OUT is OFF. It is reset by a
logic [0] at INHS for at least t RST(DIAG).
When INHS goes to 0 V, CSNS goes to
5.0 V.
Overload
on External Low
Side MOSFET
L
L
H
x
L
L
H
x
x
L
The 34981 is currently in Fault mode.
GLS is at 0 V and OCLS internal
current source is off. The external
resistance connected between OCLS
and GND pin pulls OCLS pin to 0 V.
The fault is reset by a logic [0] at INLS
for at least t RST(DIAG).
H = High level
L = Low level
x = Don’t care
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
EN
5.0 V
CONF
5.0 V
INHS
INLS
OUT
0.0 V
GLS
5.0 V
FS
5.0 V
0.0 V
TEMP
0.0 V
0.0 V
TSD
Temperature
Hysteresis
TSD
Hysteresis
OUT
Thermal Shutdown
on OUT
High Side ON
Thermal Shutdown
on OUT
High Side OFF
Figure 12. Overtemperature on Output
34981
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
5.0 V
EN
5.0 V
INLS
0.0 V
t RST(DIAG)
GLS
0.0 VLow Side OFF
5.0 V
FS
0.0 V
OCLS
0.0 V
VDS_LS = VOCLS
VDS_LS
Case 1: Overload Removed
Overload on Low Side
Figure 13. Overload on Low Side Gate Drive, Case 1
5.0 V
EN
INLS
0.0 V
t RST(DIAG)
GLS
0.0 V Low Side OFF
FS
0.0 V
OCLS
0.0 V
VDS_LS = VOCLS
VDS_LS
Case 2: Low Side Still Overloaded
Overload on Low Side
Figure 14. Overload on Low Side Gate Drive, Case 2
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
5.0 V
EN
INHS
0.0 V
t RST(DIAG)
OUT
0.0 V
5.0 V
FS
0.0 V
VCL (CSNS)
CSNS
0.0 V
IOCH
Fault Removed
IOUT
Overcurrent on High Side
Figure 15. Overcurrent on Output
Figure 16. High Side Overcurrent
34981
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Current in Motor
Recirculation in Low Side
Figure 17. Cross-Conduction with Low Side
Overtemperature
INHS
TEMP
OUT
IOUT
Figure 18. Overtemperature on OUT
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Figure 19. Maximum Operating Frequency for SR Capacitor of 4.7 nF
34981
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 20 shows a typical application for the 34981. A brush DC motor is connected to the output. A low side gate driver is
used for the freewheeling phase. Typical values for external capacitors and resistors are given.
.
VPWR
VPWR
VDD
VDD
34981
VPWR
SR
Voltage regulator
2.2 nF
1.0 k
10 k
I/O
10 k
I/O
10 k
I/O
MCU
10 k
I/O
100 nF
CBOOT
100 nF
CONF
FS
INLS
EN
OUT
DLS
INHS
A/D
TEMP
A/D
CSNS
GLS
OCLS
GND
1.0 k
330 F
M
33 k
Figure 20. 34981 Typical Application Diagram
EMC AND EMI RECOMMENDATIONS
INTRODUCTION
This section relates the EMC capability for 34981, high
frequency high-current high side switch. This device is a selfprotected silicon switch used to replace electromechanical
relays, fuses, and discrete circuits in power management
applications.
This section presents the key features of the device and its
targeted applications. The standard to measure conducted
and radiated emissions is provided. Concrete measurements
on the 34981 and improvements to reduce electromagnetic
emission are described.
DEVICE FEATURES
This 34981 is a 4.0 m self-protected, high side switch
digitally controlled from a microcontroller (MCU) with
extended diagnostics, able to drive DC motors up to 60 kHz.
A bootstrap architecture has been used to provide fast
transient gate voltage in order to reach 4.0 m RDS(ON)
maximum at room temperature. In parallel, a charge pump is
implemented to offer continuous on-state capability. This
dual current supply of the high side MOSFET allows a duty
cycle from 5% to 100%. An external capacitor connected
between pins SR and GND is used to control the slew rate at
the output and, therefore, reduce electromagnetic
perturbations.
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. To reduce global
power dissipation, the freewheeling diode can be replaced by
an external discrete MOSFET in low side configuration. The
IC integrates a gate driver, which controls and protects this
external MOSFET in the event of a short-circuit to supply.
The product manages the cross conduction between the
internal high side and the external low side when used in a
half-bridge configuration. The two MOSFETs can be
controlled independently when the CONF pin is at 0 V. To
eliminates fuses, the device is self-protected from severe
short-circuits (100 A typical) with an innovative overcurrent
strategy.
The 34981 has a current feedback for real-time monitoring
of the load current through an MCU analog/digital converter
to facilitate closed-loop operation for motor speed control.
The 34981 has an analog thermal feedback used by the
MCU to monitor PC board temperature to optimize the motor
control and to protect the entire electronic system. Therefore,
an overtemperature shutdown feature protects the IC against
high overload condition.
Figure 21 illustrates the typical application diagram.
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
HOW TO MEASURE ELECTROMAGNETIC
EMISSION ACCORDING TO THE CISPR25
34981
One EMC standard standard is the CISPR25, edited by
the International Electrotechnical Commission. This standard
describes the measurement method to measure both
conducted and radiated emission.
CONDUCTED EMISSION MEASUREMENT
Figure 21. Typical Application Diagram
APPLICATION
OUT
Imotor (10A/div)
34981 OFF
MC33981
OFF
MC33981
34981 ONON
200 0+ 200mm
Contact to
Ground Plane
Power Supply
BF Generator
+
-
Supply
Engine cooling, air conditioning, and fuel pump are the
targeted applications for the 34981. Conventional solutions
are designed with discrete components are not optimized in
terms of component board size, protection, and diagnostics.
The 34981 is the right candidate to develop lighter and more
compact units.
DC motor speed adjustment allows optimization of energy
consumption by reducing supply voltage, hence the mean
voltage applied to the motor. The commonly used control
technique is pulse wide modulation (PWM) where the
average voltage is proportional to the duty cycle. Most
applications require a PWM frequency of at least 20 kHz to
avoid audible noise. Figure 22 illustrates typical waveforms
when switching the 34981 at 20 kHz with a duty cycle of 80%.
The output voltage (OUT) and current in the motor (IMOTOR)
waveforms are represented.
Conducted emission is the emission produced by the
device on the power supply cable. The test bench is
described by CISPR25 (see Figure 23).
The Line Impedance Stabilization Network (LISN), also
called artificial network (AN), in a given frequency range
(150 kHz to 108 MHz), provides a specified load impedance
for the measurement of disturbance voltages and isolates the
equipment under test (EUT) from the supply in that frequency
range.
LISN
Ground
Out
EUT
Non-Conductive
Material
Load
High Side Driver Signal
Electrical to Optical
Converter
Coaxial Cable
Ground Plane in Copper
12V Power Supply
Spectrum Analyzer
Figure 23. Test Bench for Conducted Emission
The EUT must operate under typical loading and other
conditions just as it must in the vehicle so maximum emission
state occurs. These operating conditions must be clearly
defined in the test plan to ensure both supplier and customer
are performing identical tests.
For the testing described in this application note, the out
pin of the 34981 was connected to an inductive load (0.47
+ 1.0 H) switching at 20 kHz with a duty cycle of 80%. The
output current was 17 A continuous.
The ground return of the EUT to the chassis must be as
short as possible. The power supply is 13.5 V.
RADIATED EMISSION MEASUREMENT
The radiated emission measurement consists of
measuring the electromagnetic radiation produced by the
equipment under test. CISPR 25 gives the schematic test
bench described in Figure .
Figure 22. Current and Voltage waveforms
34981
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
To measure radiated emission over all frequency ranges,
several antenna types must be used:
• 0.15 MHz to 30 MHz: 1.0 m vertical monopole in
vertical polarization.
• 30 MHz to 200 MHz: a biconical antenna used in
vertical and horizontal polarization.
• 200 MHz to 1,000 MHz: a log-periodic antenna used in
vertical and horizontal polarization.
BOARD SETUP
The initial configuration of our 34981 board is represented
in Figure 25.
No SR capacitor is used. Therefore, the obtained
switching times are the maximum values. A capacitor of
1000 F is connected between VPWR and GND.
GND
Out
34981
33981
VPWR
Figure 25. 34981 Initial Configuration
CONDUCTED MEASUREMENTS
TEST SETUP
Key
1
EUT (grounded locally if
required in test plan)
8
Biconical antenna
2
Test harness
3
Load simulator (placement
and ground connection)
10 High quality doubleshielded coaxial cable
(50 )
–
–
4
Power supply (location
optional)
11 Bulkhead connector
5
Artificial Network (AN)
12 Measuring instrument
6
Ground plane (bonded to
shielded enclosure)
13 RF absorber material
7
Low relative permittivity
support ( 1.4)
14 Stimulation and monitoring
system
To perform a conducted emission measurement in
accordance with the CISPR 25 standard, the test bench in
Figure 26 was developed.
Power Supply
LISN
Measurement
Point for
Conducted
Emission
EUT
Figure 24. Test Bench for Radiated Emission
EMC RESULTS AND IMPROVEMENTS
The 34981 OUT is connected to an inductive load (0.47
+ 1.0mH) switching at 20 kHz with duty = 80%. The current in
the load was 17 A continuous.
Non-Conductive
Material
Load (1.0 mH + 0.47 Ω)
Optical PWM Signal
Figure 26. Conducted Emission Test Setup
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
TYPICAL APPLICATIONS
EMC AND EMI RECOMMENDATIONS
EFFECTS OF SOME PARAMETERS
RC Out
Filter C2
The conducted emissions level rise with the duty cycle.
When the duty increases the di/dt on the VPWR line is higher.
The device has to deliver more current and provide more
energy. Figure 27 describes the effect of duty cycle increase
on the VPWR current waveform. The conducted emission
level rises with the output frequency. This is due to the
increasing number of commutations.
di/dt
PI
Filter
C3
C1
di/dt
Duty Cycle
Increase
I(t) on V
PWR
I(t) on VBAT
RC In
Filter
t
SR
Figure 27. VPWR Current
HOW TO REDUCE ELECTROMAGNETIC EMISSION
By adjusting the slew rate of the device during turn ON and
turn OFF with SR capacitor, the electromagnetic emissions
can be reduced.
Conductive emission tests were performed (taking care of
the board filtering and routing that have a big impact on EMC
performances).
Figure 29. Enhanced Board
The chart in Figure 30 shows the spectrum of the
enhanced board and the initial board. The improvement is
appreciatively 15 dB to 20 dB in the all frequency range. The
enhanced board is now in accordance with the Class 3 limits
of the CISPR25 standard for conducted emission.
An optimized solution was found by adding the following
external components to the initial board:
• PI filter on the VPWR: 2 x 3 F and 3.5H
• RC IN filter between VPWR and GND: a 2.0 resistor in
series with a 100 nF capacitor
• RC Out filter between OUT and GND: a 4.7 resistor
in series with a 100 nF capacitor
• Capacitor C1 of 10 nF between VPWR and GND
• Capacitor C2 of 10 nF between OUT and GND
• Capacitor C3 of 10 nF between OUT and VPWR
• Capacitor SR of 3.3 nF
C3 = 10 nF
RC In Filter
RC Out Filter
Figure 30. Conducted Emission Spectrum for 34981
GND
100 nF
Figure 28. 34981 with Filter
The EMC enhanced board with adapted value filter is
represented in Figure 29.
Inductive Load
SR
3.3 nF
4.7 Ω
33891
34981
C2 = 10 nF
2Ω
3000 μF
Free Wheel Diode
OUT
C1 = 10 nF
PI filter
3.5 μH
100 nF
VPWR
BAT
V
RADIATED MEASUREMENTS
This test was performed in order to evaluate the
characteristic of the device relating to radiated emission.
Measurements have been done in accordance with the
CISPR 25 standard as shown in Figure 31. The tested board
was the EMC enhanced board.
34981
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
POWER DISSIPATION
1.5 m Length
of Cable
CISPR
Class 3
Limits
Anechoic
Chamber
34981
33981
Emission
LISN and
Inductive Load
EUT
Figure 32. Radiated Emission Spectrum for 34981
1 m Vertical
Monopole
Antenna
Figure 31. Radiated Emission Test Set-up
The results of these measurements are represented in
Figure 32. The enhanced board is in accordance with the
Class 3 limits of the CISPR25 standard for radiated emission.
CONCLUSION
This document explains how to measure conducted and
radiated emission in accordance with the CISPR25 standard.
Measurements were performed on the 34981 in real
application conditions, when driving an inductive load. An
optimized filtering solution was put in place to have the tested
system in accordance with the Class 3 limits. The same
method can be used with other PC boards.
POWER DISSIPATION
INTRODUCTION
This section relates to the power dissipation capability for
34981, high frequency high-current high side switch. This
device is a self-protected silicon switch used to replace
electromechanical relays, fuses, and discrete circuits in
power management applications.
This section presents the key features of the device and its
targeted applications. The theoretical calculations for power
dissipation and die junction temperatures are determined in
this document for inductive loads. A concrete example with
DC motor driven by the 34981 is analyzed in DC Motor 200W.
DEVICE FEATURES
This 34981 is a 4.0 m self-protected, high side switch
digitally controlled from a microcontroller (MCU) with
extended diagnostics, able to drive DC motors up to 60 kHz.
A bootstrap architecture has been used to provide fast
transient gate voltage in order to reach 4.0 m RDS(ON)
maximum at room temperature. In parallel, a charge pump is
implemented to offer continuous on-state capability. This
dual current supply of the high side MOSFET allows a duty
cycle from 5% to 100%. An external capacitor connected
between pins SR and GND is used to control the slew rate at
the output and, therefore, reduce electromagnetic
perturbations.
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. To reduce global
power dissipation, the freewheeling diode can be replaced by
an external discrete MOSFET in low side configuration. The
IC integrates a gate driver which controls and protects this
external MOSFET in the event of a short-circuit to supply.
The product manages the cross conduction between the
internal high side and the external low side when used in a
half-bridge configuration. The two MOSFETs can be
controlled independently when the CONF pin is at 0 V. To
eliminates fuses, the device is self-protected from severe
short-circuits (100 A typical) with an innovative overcurrent
strategy.
The 34981 has a current feedback for real-time monitoring
of the load current through an MCU analog/digital converter
to facilitate closed-loop operation for motor speed control.
The 34981 has an analog thermal feedback used by the
MCU to monitor PC board temperature to optimize the motor
control and to protect the entire electronic system. Therefore,
an overtemperature shutdown feature protects the IC against
high overload condition.
Figure 33 illustrates the typical application diagram.
34981
Figure 33. Typical Application Diagram
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
TYPICAL APPLICATIONS
POWER DISSIPATION
APPLICATION
Engine cooling, air conditioning, and fuel pump are the
targeted applications for the 34981. Conventional solutions
are designed with discrete components are not optimized in
terms of component board size, protection, and diagnostics.
The 34981 is the right candidate to develop lighter and more
compact units.
The adjustment of the DC motor speed allows optimizing
of energy consumption. It is realized by chopping the supply
voltage, hence the mean voltage, applied to the motor. The
commonly used control technique is pulse wide modulation
(PWM) where the average voltage is proportional to the duty
cycle. Most applications require a PWM frequency of at least
20 kHz to avoid audible noise. Figure 34 illustrates typical
waveforms when switching the 34981 at 20 kHz with a duty
cycle of 80%. The output voltage (OUT) and current in the
motor (IMOTOR) waveforms are represented.
The following analysis assumes an inductive load and
assumes the current is constant in the load.
The case being considered in this paper is inductive load
and the hypothesis is the current is constant in the load.
ON-STATE LOSSES
The mean on-state loss periods in the 34981 can be
calculated as follows:
Pon_state = a · RDS(ON) · IOUT2 where ‘a’ is the duty cycle.
The critical parameter is the on resistance (RDS(ON))
increases with temperature. The 34981 has a maximum
RDS(ON) at 25 ºC of 4.0 m and its deviation with
temperature is only 1.7 as shown in Figure 35.
7
OUT
RDSON (mOhm)
6
5
4
3
2
1
Imotor (10A/div)
0
-50
0
50
100
150
200
Temperature (°C)
MC34981 OFF
MC33981
OFF
MC34981 ON
MC33981
ON
Figure 34. Current and Voltage waveforms
POWER DISSIPATION
The 34981 power dissipation is the sum of two kinds of
losses:
• On-State losses when device is fully ON,
• Switching losses when the device switches ON and
OFF.
Figure 35. RDS(ON) vs. Temperature
SWITCHING LOSSES
The mean switching losses in the 34981 can be calculated
as follows:
Pswitching = (tON . FREQ . VPWR . IOUT) / 2 + (tOFF . FREQ .
VPWR . IOUT) / 2
where tON/tOFF is the turn on/off time.
The switching time is a critical parameter. The 34981
provides adjustable slew rates through an external capacitor
(SR), which slow down the rise and fall times to reduce the
electromagnetic emissions. However, this adjustment has an
impact on power dissipation. Figure 36 gives the positive
(SRR) and negative (SRF) slew rate versus different values of
SR. This is illustrated in Figure 37.
34981
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
POWER DISSIPATION
RECIRCULATION PHASE
100
0
80
)
60
s
µ
/
V
40
(f
R
20
S
1
0
SRf(V/µs)
4.5
6
9
Vpwr
14
27
90
80
70
60
50
40
30
20
10
0
0
1
2.2
3.3
4.7
6.8
4.5
6
9
14
27
Vbat
Figure 36. Positive and Negative Slew Rate
vs. SR Capacitor
In standard configuration, the motor current recirculation is
handled by an external freewheeling diode. With the 34981,
the freewheeling diode can be replaced by an external lowside discrete MOSFET.
The power dissipation during the recirculation phase is
calculated as follows for the diode and the low-side MOSFET
respectively:
Pdiode = (1-a) . VF . IOUT
where ‘a’ is the duty cycle
Pmosfet_ls = (1-a) . RDS(ON)_ls . IOUT2
where RDS(ON)_ls is the on resistance of the low side.
APPLICATIONS EXAMPLES
EXCEL TOOL
An excel tool has been created with all the above formulas
to calculate the dissipated power and the junction
temperature knowing the application conditions. An example
of the interface is given in Figure 38. The parameters to enter
concern the load, the high side device, the recirculation, and
the board. They are VPWR, DC current in the load (Imax for
100% of duty cycle), PWM frequency, 34981 RDS(ON) at
150 ºC, SR capacitor, low side RDS(ON) at 150 ºC, ambient
temperature, and thermal impedance.
INPUTS
Load
Vpwr
12 V
Imax
20 A
Frequency
High Side
Device (HS)
20 KHz
RDSON
@150°C
6.8 mOhm
SR
Capacitor
0 nF
Low Side Characteristics
Recirculation
Figure 37. OUT switching vs. SR Capacitor
JUNCTION TEMPERATURE
The junction temperature of the 34981 can be calculated
knowing the power dissipation and the thermal
characteristics of the PC board with this formula:
TJ = TA + (Pon_state + Pswitching). RTHJA
where TJ is the junction temperature, TA the ambient
temperature, and RTHJA the thermal impedance junction to
ambient.
Board
RDSON
@150°C
Rthja
T ambiant
20 mOhm
15°C/W
85°C
Figure 38. Excel Tool
The calculations are done with the maximum RDS(ON) for
the 34981 and the low side. The current is also considered
constant in the load. The model taken for the VF of the diode
is (0.4 + 0.01 . IOUT) Volts.
The listed conditions in Figure 38 are the ones chosen for
the entire document.
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
TYPICAL APPLICATIONS
POWER DISSIPATION
DC MOTOR 200W
INFLUENCE OF SR CAPACITOR
A concrete example is the 34981. A 200 W DC motor, a
frequency of 20 kHz, and an ambient temperature of 85 ºC
are chosen. The 34981 is evaluated using the following
board. The thermal impedance of the board is in the range of
15 ºC/W.
The SR capacitor value has an impact on these switching
losses. Figure 41 illustrates the percentage of the switching
losses versus the total power dissipation for the same load
conditions as Figure 38. The higher the SR capacitor value,
the higher the switching losses. They can be more than 50%
of the total power dissipation in the 34981 with a 4.7 nF
capacitor and is a basic applications trade-off. A compromise
should be found between the power dissipation and the
electromagnetic capability (EMC) performance.
6
P switch in g
Pon
Power Dissipation (W)
5
4
3
2
1
0
Figure 39. 34981 Evaluation Board
0
2 .2
3 .3
4 .7
C s r (n F )
POWER DISSIPATION
Figure 41. Power Switching vs. SR Capacitor
Figure 40 illustrates the power dissipation in the 34981.
The conditions are listed in Figure 38. Maximum power
dissipation of 3.1 W is obtained with a duty of 95%.
MC33981 Power Dissipation
MC34981
3.5
RECIRCULATION PHASE
Figure 42 illustrates the power dissipation for the two
recirculation approaches, diode or low side MOSFET. The
power dissipation gain for the entire system when using the
low side instead of the diode can reach up to 1.5 W with a
duty cycle of 50%.
Pon_state
P switching
Ptotal
Total Board Power Dissipation
2.5
4.5
4.0
2.0
Power Dissipation (W)
MC33981 Power Dissipation (W)
MC34981
3.0
1.5
1.0
0.5
3.5
3.0
Power HS
Power Diode
2.5
Power Total Board with Diode
2.0
Power LS
Power Total Board with LS
1.5
1.0
0.5
0.0
0
0
0
10
20
30
40
50
60
70
80
90
100
Duty Cycle (%)
Figure 40. Power Dissipation (Pon and Pswitching) vs.
Duty Cycle
10
20
30
40
50
60
70
80
90
100
Ratio PWM %
Figure 42. Total Board Power Dissipation
34981
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
POWER DISSIPATION
JUNCTION TEMPERATURE
CONCLUSION
The junction temperature of the 34981 versus duty cycle
for the condition listed in Figure 38, is given in Figure 43. The
maximum obtained junction temperature is 132 ºC with a duty
cycle of 95%. This value is far from the 150ºC maximum
guaranteed junction.
Knowing the application conditions, this document
explained how to calculate power dissipation during on-state
and switching phases and the junction temperature for the
34981 when controlling a DC motor. A concrete example with
a 200 W DC motor was given in DC Motor 200W. The same
principle can be used for other DC motors and other
environmental conditions.
140.00
Junction Temperature (°C)
120.00
100.00
80.00
60.00
40.00
20.00
0.00
0
10
20
30
40
50
60
70
80
90
100
Duty cycle (%)
Figure 43. Junction Temperature vs. Duty Cycle
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 34981 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit
board. The AN2467 provides guidelines for Printed Circuit Board design and assembly.
PACKAGING DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using “98ARL10521D”.
Dimensions shown are provided for reference ONLY.
FK SUFFIX
16-PIN PQFN
98ARL10521D
ISSUE C
34981
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
16-PIN PQFN
98ARL10521D
ISSUE C
34981
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
34981
THERMAL ADDENDUM (REV 3.0)
INTRODUCTION
This thermal addendum is provided as a supplement to the 34981 technical
datasheet. The addendum provides thermal performance information critical in
the design and development of system applications. All electrical, application,
and packaging information is provided in the datasheet.
16-PIN
PQFN
PACKAGING AND THERMAL CONSIDERATIONS
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RJAmn.
For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RJ21 and RJ22, respectively.
TJ1
TJ2
=
RJA11 RJA12
RJA21 RJA22
.
98ARL10521D
16-PIN PQFN
12 MM X 12 MM
Note For package dimensions, refer to
98ARL10521D.
P1
P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and does not predict the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation according to the standards listed below.
STANDARDS
Table 8. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W]
Thermal
Resistance
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
JAmn(1), (2)
22
18
41
(2), (3)
7.0
4.0
27
JAmn(1), (4)
62
48
81
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