NXP Semiconductors
Advance Information
Document Number: MC34FS6407-08
Rev. 3.0, 7/2016
Power system basis chip with high
speed can transceiver
FS6407
FS6408
The FS6407/FS6408 SMARTMOS devices area multi-output, power supply,
integrated circuit, including HSCAN transceiver, dedicated to the industrial
market.
Multiple switching and linear voltage regulators, including low-power mode
(32 μA) are available with various wake-up capabilities. An advanced power
management scheme is implemented to maintain high efficiency over wide input
voltages (down to 2.7 V) and wide output current ranges (up to 1.5 A).
The FS6407/FS6408 include enhanced safety features, with multiple fail-safe
outputs, becoming a full part of a safety oriented system partitioning, to reach a
high integrity safety level.
The built-in enhanced high-speed CAN interface fulfills the ISO11898-2 and -5
standards.
Features
• Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting
buck-boost and standard buck
• Switching mode power supply (SMPS) dedicated to MCU core supply, from
1.2 V to 3.3 V delivering up to 1.5 A
• Multiple wake-up sources in low-power mode: CAN and/or IOs
• Six configurable I/Os
• Linear voltage regulator dedicated to auxiliary functions, or to a sensor supply
(VCCA tracker or independent), 5.0 V or 3.3 V
• Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os
supply (VCCA), 5.0 V or 3.3 V
POWER SYSTEM BASIS CHIP
AE SUFFIX (PB-FREE)
98ASA00173D
48-PIN LQFP-EP
Applications
• Automation (PLC, robotics)
• Building control (lift)
• Transportation (mobile machine, military)
• Medical (Infusion pump, stairs)
Input
supply
VDD
BOOTS_CORE
SW_CORE
VPRE
GATE_LS
BOOTS_PRE
SW_PRE2
SW_PRE1
VSUP2
VSUP1
VSUP3
VSENSE
COMP_CORE
VCCA_E
VCCA_B
VCCA
VAUX_E
VDDIO
VAUX_B
Vaux
34FS6407
34FS6408
CAN-5V
Ignition
Vcca
AD ref.
voltage
Vcore or
Vcca
MOSI
MISO
SCLK
NCS
MUX_OUT
VAUX
SELECT
MCU
VCORE_SNS
FB_CORE
INTB
IO_0
SPI
ADC Input
NMI
VDDIO
IO_1
RSTB
IO_2
Reset
VDDIO
IO_3
IO_4
FS0B
Vpre
IO_5
CANH
CAN BUS
DEBUG
CANL
GNDA
GND_COM
DGND
VDD
TXD
DEBUG
mode
RXD
CAN
Figure 1. FS6407/FS6408 simplified application diagram - buck boost configuration
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
FCCU
Input
supply
VDD
BOOTS_CORE
SW_CORE
VPRE
GATE_LS
BOOTS_PRE
SW_PRE2
SW_PRE1
VSUP2
VSUP1
VSUP3
MCU
VCORE_SNS
FB_CORE
Vpre
COMP_CORE
VCCA_E
VSENSE
VCCA_B
Vpre
VCCA
VAUX_E
VDDIO
Vcca
AD ref.
voltage
Vcore or
Vcca
VAUX_B
SELECT
CAN-5V
Ignition
MOSI
MISO
SCLK
NCS
MUX_OUT
34FS6407
34FS6408
VAUX
INTB
IO_0
IO_1
SPI
ADC Input
NMI
VDDIO
Reset
RSTB
IO_2
VDDIO
IO_3
FS0B
IO_4
Vpre
IO_5
CANH
DEBUG
CAN BUS
CANL
VDD
GNDA
GND_COM
DGND
TXD
DEBUG
mode
RXD
CAN
FCCU
Figure 2. Simplified application diagram - buck configuration, VAUX not used, VCCA = 100 mA
FS6407/FS6408
2
NXP Semiconductors
1
Orderable parts
Table 1. Orderable part variations
Part number
MC34FS6407NAE
MC34FS6408NAE
Temperature (TA)
Package
CAN
-40 °C to 125 °C
48-pin LQFP exposed pad
1
Vcore
0.8 A
Notes
(1)
1.5 A
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
FS6407/FS6408
NXP Semiconductors
3
2
Internal block diagram
COMP_CORE
BOOTS_CORE
VCORE_SNS
FB_CORE
SW_CORE
DGND
VPRE
GATE_LS
BOOTS_PRE
SW_PRE2
SW_PRE1
VSUP2
VSUP1
VPRE
VSUP3
TSD
TSD
VPRE SMPS
VCORE SMPS
TSD
VAUX_E
VAUX_B
VAUX
VPRE
VPRE
TSD
VAUX Linear Regulator
VPRE
VCAN
TSD
Internal Linear
Regulator
CAN-5V
VCCA_E
VCCA_B
VCCA
VCCA Linear Regulator
VPRE3
Analog
Reference #1
SELECT
VREF
(2.5V)
VPRE
VPRE
Charge Pump
Die
Temp
GNDA
MUX
Interface
MUX_OUT
Select
IO_0
IO_1
IO_2
I/Os
Interface
IO_3
6
V2p5
Logic
Main
OSC
Main
Power Management
State Machine
IO_4
IO_5
CAN-5V
VPRE
VAUX
Voltage Regulator
SUPERVISOR
(Over & undervoltage)
VSUP1&2
CAN diag
Vsense
Debug
INTB
MOSI
MISO
SCLK
NCS
SPI
Main
VDDIO
VCCA FB_core
DEBUG
MISO FS
V2p5Logic
FS
5
Analog Reference #2
FS
VPRE
SPI
FS
Fail-safe Machine
VDDIO
RSTB
FS0B
OSC
FS
VSUP3
VSENSE
CAN-5V
CANH
VDDIO
Debug
Select
HSCAN Interface
CANL
VSENSE
RXD
TXD
GND_COM
Fail-safe Logic & supply
Figure 3. FS6407/FS6408 simplified internal block diagram
FS6407/FS6408
NXP Semiconductors
4
3
Pin connections
VPRE
VAUX
VAUX_B
VAUX_E
VCCA_E
VCCA_B
VCCA
GATE_LS
DGND
BOOT_PRE
SW_PRE2
Pinout diagram for FS6407/FS6408
SW_PRE1
3.1
Transparent top view
VSUP1
BOOT_CORE
VSUP2
SW_CORE
VSENSE
VCORE_SNS
VSUP3
COMP_CORE
NC
FB_CORE
GND_COM
SELECT
CAN_5V
VDDIO
RSTB
NC
NC
RXD
TXD
IO_3
IO_2
MISO
MUX_OUT
MOSI
IO_0
AGND
SCLK
IO_5
DEBUG
NCS
IO_4
IO_1
INTB
CANL
FS0B
CANH
Figure 4. FS6407/FS6408 pinout
3.2
Pin definitions
A functional description of each pin can be found in the functional pin description section beginning on page 22.
Table 2. FS6407/FS6408 pin definition
Pin Number
Pin Name
Type
Definition
1
VSUP1
A_IN
Power supply of the device. An external reverse battery protection diode in series is mandatory
2
VSUP2
A_IN
Second power supply. Protected by the external reverse battery protection diode used for VSUP1. VSUP1
and VSUP2 must be connected together externally.
3
VSENSE
A_IN
Sensing of the battery voltage. Must be connected prior to the reverse battery protection diode.
4
VSUP3
A_IN
Third power supply dedicated to the device supply. Protected by the external reverse battery protection
diode used for VSUP1. Must be connected between the reverse protection diode and the input PI filter.
5, 22, 23
NC
N/A
Not connected. Pins must be left open.
6
GND_COM
GND
Dedicated ground for CAN
7
CAN_5V
A_OUT
8
CANH
A_IN/OUT HSCAN output High
9
CANL
A_IN/OUT HSCAN output Low
Output voltage for the embedded CAN interface
FS6407/FS6408
NXP Semiconductors
5
Table 2. FS6407/FS6408 pin definition (continued)
Pin Number
10
11
Pin Name
IO_4:5
Type
Definition
D_IN
A_OUT
Can be used as digital input (load dump proof) with wake-up capability or as an output gate driver
Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another
IC for safety purposes.
Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition
Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI.
Can be used as analog or digital input (load dump proof) with wake-up capability (selectable)
Analog input: Pin status can be read through the MUX output pin
Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another
IC for safety purposes
Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition
Rk: For safety purposes, IO_1 can also be used to monitor the middle point of a redundant resistor bridge
connected on VCORE (in parallel to the one used to set the Vcore voltage).
12
13
IO_0:1
A_IN
D_IN
14
FS0B
D_OUT
15
DEBUG
D_IN
16
AGND
17
MUX_OUT
A_OUT
Multiplexed output to be connected to an MCU ADC input. Selection of the analog parameter is available
at MUX-OUT through the SPI.
18
19
IO_2:3
D_IN
Digital input pin with wake-up capability (logic level compatible)
Digital INPUT: Pin status can be read through the SPI. Can be used to monitor error signals from MCU for
safety purposes.
Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition.
20
TXD
D_IN
Transceiver input from the MCU which controls the state of the HSCAN bus. Internal pull-up to VDDIO.
Internal pull-up to VDDIO.
21
RXD
D_OUT
Receiver output which reports the state of the HSCAN bus to the MCU
24
RSTB
D_OUT
This output is asserted low when the safety block reports a failure. The main function is to reset the MCU.
Reset input voltage is also monitored in order to detect external reset and fault condition. Open drain
structure.
25
MISO
D_OUT
SPI bus. Master Input Slave Output
26
MOSI
D_IN
SPI bus. Master Output Slave Input
27
SCLK
D_IN
SPI Bus. Serial clock
28
NCS
D_IN
No Chip Select (Active low)
29
INTB
D_OUT
30
VDDIO
A_IN
Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.
31
SELECT
D_IN
Hardware selection pin for VAUX and VCCA output voltages
32
FB_CORE
A_IN
VCORE voltage feedback. Input of the error amplifier.
33
COMP_CORE
A_IN
Compensation network. Output of the error amplifier.
34
VCORE_SNS
A_IN
VCORE output voltage sense
35
SW_CORE
A_IN
VCORE switching point
36
Output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is
detected. Open drain structure.
Debug mode entry input
GROUND Analog ground connection
This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable.
Internal pull-up to VDDIO.
BOOT_CORE A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive
37
VPRE
A_OUT
VPRE output voltage
38
VAUX
A_OUT
VAUX output voltage. External PNP ballast transistor. Collector connection
39
VAUX_B
A_OUT
VAUX voltage regulator. External PNP ballast transistor. Base connection
40
VAUX_E
A_OUT
VAUX voltage regulator. External PNP ballast transistor. Emitter connection
41
VCCA_E
A_OUT
VCCA voltage regulator. External PNP ballast transistor. Emitter connection
42
VCCA_B
A_OUT
VCCA voltage regulator. External PNP ballast transistor. Base connection
FS6407/FS6408
6
NXP Semiconductors
Table 2. FS6407/FS6408 pin definition (continued)
Pin Number
Pin Name
Type
Definition
43
VCCA
A_OUT
VCCA output voltage. External PNP ballast transistor. Collector connection
44
GATE_LS
A_OUT
Low-side MOSFET gate drive for “Non-inverting Buck-boost” configuration
45
DGND
46
BOOT_PRE
47
SW_PRE2
A_IN
Second pre-regulator switching point
48
SW_PRE1
A_IN
First pre-regulator switching point
GROUND Digital ground connection
A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive
FS6407/FS6408
NXP Semiconductors
7
4
General product characteristics
4.1
Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
Ratings
Value
Unit
Notes
(2)
Electrical ratings
VSUP1/2/3
DC Voltage at Power Supply Pins
-1.0 to 40
V
VSENSE
DC Voltage at Battery Sense Pin
-14 to 40
V
VSW1,2
DC Voltage at SW_PRE1 and SW_PRE2 Pins
-1.0 to 40
V
DC Voltage at VPRE Pin
-0.3 to 8
V
DC Voltage at Gate_LS pin
-0.3 to 8
V
VBOOT_PRE
DC Voltage at BOOT_PRE pin
-1.0 to 50
V
VSW_CORE
DC Voltage at SW_CORE pin
-1.0 to 8.0
V
VCORE_SNS
DC Voltage at VCORE_SNS pin
0.0 to 8.0
V
VBOOT_CORE
DC Voltage at BOOT_CORE pin
0.0 to 15
V
DC Voltage at FB_CORE pin
-0.3 to 2.5
V
DC Voltage at COMP_CORE pin
-0.3 to 2.5
V
DC Voltage at VAUX_E, VAUX_B pin
-0.3 to 40
V
DC Voltage at VAUX pin
-2.0 to 40
V
DC Voltage at VCCA_B, VCCA_E pin
-0.3 to 8.0
V
VCCA
DC Voltage at VCCA pin
-0.3 to 8.0
V
VDDIO
DC Voltage at VDDIO
-0.3 to 8.0
V
VFS0
DC Voltage at FS0B (with ext R mandatory)
-0.3 to 40
V
DC Voltage at DEBUG
-0.3 to 40
V
DC Voltage at IO_0:1; 4:5 (with ext R = 5.1 kΩ in series mandatory)
-0.3 to 40
V
-0.3 to VDDIO+0.3
V
DC Voltage at SELECT
-0.3 to 8.0
V
DC Voltage on CANL, CANH
-27 to 40
V
DC Voltage on CAN_5 V
-0.3 to 8.0
V
IOs Maximum Current Capability(IO_0, IO_1, IO_4, IO_5)
-5.0 to 5.0
mA
VPRE
VGATE_LS
VFB_CORE
VCOMP_CORE
VAUX_E,B
VAUX
VCCA_B,E
VDEBUG
VIO_0,1,4,5
VDIG
VSELECT
VBUS_CAN
VCAN_5V
I_IO0, 1, 4, 5
DC Voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD,
IO_2, IO_3
Notes
2. All VSUPS (VSUP1/2/3) must be connected to the same supply (Figure 49)
FS6407/FS6408
8
NXP Semiconductors
Table 3. Maximum ratings (continued)
All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Symbol
VESD-HBM1
VESD-HBM2
VESD-HBM3
VESD-CDM1
VESD-CDM2
VESD-GUN1
VESD-GUN2
VESD-GUN3
VESD-GUN4
VESD-GUN5
VESD-GUN6
VESD-GUN7
VESD-GUN8
Ratings
ESD Voltage
Human Body Model (JESD22/A114) - 100 pF, 1.5 kΩ
• All pins (ESD Class 2)
• VSUP1,VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5,FS0B, DEBUG
(ESD Class 3A)
• CANH, CANL (ESD Class 3A)
Charge Device Model (JESD22/C101):
• All Pins (ESD Class 2)
• Corner Pins (ESD Class 2)
System level ESD (Gun Test)
• VSUP1, VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5, FS0B
330 Ω / 150 pF Unpowered According to IEC61000-4-2:
330 Ω / 150 pF Unpowered According to OEM CAN, FLexray Conformance
2.0 kΩ / 150 pF Unpowered According to ISO10605.2008
2.0 kΩ / 330 pF Powered According to ISO10605.2008
• CANH, CANL
330 Ω / 150 pF Unpowered According to IEC61000-4-2:
330 Ω / 150 pF Unpowered According to OEM CAN, FLexray Conformance
2.0 kΩ / 150 pF Unpowered According to ISO10605.2008
2.0 kΩ / 330 pF Powered According to ISO10605.2008
Value
Unit
±2.0
±4.0
±6.0
kV
kV
kV
±500
±750
V
V
Notes
(3)
±8.0
±8.0
±8.0
±8.0
kV
kV
kV
kV
±15.0
±12.0
±15.0
±15.0
kV
kV
kV
kV
Thermal ratings
TA
Ambient Temperature
-40 to 125
°C
TJ
Junction Temperature
-40 to 150
°C
TSTG
Storage Temperature
-55 to 150
°C
30
°C/W
(4)
Thermal Resistance Junction to Case Top
24.2
°C/W
(5)
Thermal Resistance Junction to Case Bottom
0.9
°C/W
(6)
Thermal resistance
RθJA
RθJCTOP
RθJCBOTTOM
Notes
3.
4.
5.
6.
Thermal Resistance Junction to Ambient
Compared to AGND.
Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1).
Thermal resistance between the die and the solder par on the bottom of the packaged based on simulation without any interface resistance.
FS6407/FS6408
NXP Semiconductors
9
4.2
Static electrical characteristics
Table 4. Operating range
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.0
–
13.0
mA
Power Supply Current for VSUP3 in Normal Mode (VSUP > VSUP_UV_7)
–
3.5
5.0
mA
ISUP_LPOFF1
Power Supply Current in LPOFF (VSUP = 14 V at TA = 25 °C)
–
32
–
µA
ISUP_LPOFF2
Power Supply Current in LPOFF (VSUP = 18 V at TA = 80 °C)
–
42
60
µA
Power Supply Undervoltage Warning
–
8.5
–
V
Notes
Power supply
ISUP123
ISUP3
VSNS_UV
Power Supply Current in Normal Mode (VSUP > VSUP_UV_7)
VSNS_UV_HYST
Power Supply Undervoltage Warning Hysteresis
0.1
–
–
V
VSUP_UV_7
Power Supply Undervoltage Lockout (power-up)
7.0
–
8.0
V
VSUP_UV_5
Power Supply Undervoltage Lockout (power-up)
–
–
5.6
V
VSUP_UV_L
Power Supply Undervoltage Lockout (falling - Boost config.)
–
–
2.7
V
VSUP_UV_L_B
Power Supply Undervoltage Lockout (falling - Buck config.)
–
–
4.6
V
(7)
Power Supply Undervoltage Lockout Hysteresis
–
0.1
–
V
(8)
6.25
VPRE_UV_4
–
VSUP -
6.75
–
VSUP_UV_HYST
VPRE voltage pre-regulator
VPRE Output Voltage
• Buck mode (VSUP > VSUP_UV_7)
VPRE
• Buck mode (VSUP_UV_7 ≥ VSUP ≥ 4.6 V)
• Boost mode (VSUP ≥ 2.7 V)
VPRE Maximum Output Current Capability
• Buck or Boost with VSUP > VSUP_UV_7
IPRE
• Buck with VSUP_UV_7 ≥ VSUP ≥ 4.6 V
• Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V
• Boost with 6.0 V ≥ VSUP ≥ 4.0 V
• Boost with 4.0 V ≥ VSUP ≥ 2.7 V
IPRE_LPOFF
VPRE Maximum Output Current Capability in LPOFF at low VSUP
voltage
• Buck with VSUP_UV_7 ≥ VSUP ≥ 4.6 V
• Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V
• Boost with 6.0 V ≥ VSUP ≥ 4.0 V
• Boost with 4.0 V ≥ VSUP ≥ 2.7 V
6.0
RDSON_PR
E * IPRE
–
7.0
–
0.5
–
1.0
0.3
–
–
–
–
–
1.7
1.7
1.7
–
–
0.05
1.7
1.0
0.3
–
–
–
–
–
–
–
–
P3
V
A
(8)
A
(8)
IPRE_LIM
VPRE Output Current Limitation
3.5
–
–
A
IPRE_OC
VPRE Overcurrent Detection Threshold (in buck mode only)
5.0
–
–
A
VPRE_UV
VPRE Undervoltage Detection Threshold (Falling)
5.5
–
6.0
V
Notes
7. VSUP_UV_L_B = VPRE_UV_4P3 + RDSON_PRE * IPRE
8.
Guaranteed by design
FS6407/FS6408
10
NXP Semiconductors
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VPRE Undervoltage Hysteresis
0.05
–
0.15
V
(9)
VPRE Shut-off Threshold (Falling - buck and buck/boost)
4.2
–
4.5
V
VPRE Shut-off Hysteresis
0.05
–
0.15
V
VPRE Pass Transistor On Resistance
–
–
200
mΩ
VPRE Line Regulation
–
20
–
mV
(9)
LORVPRE_BUCK
VPRE Load Regulation for COUT = 57 µF
• IPRE from 50 mA to 2.0 A - Buck mode
–
100
–
mV
(9)
LORVPRE_BOOST
VPRE Load Regulation for COUT = 57 µF
• IPRE from 50 mA to 2.0 A - Boost mode
–
500
–
mV
(9)
VPRE_LL_H
VPRE_LL_L
VPRE Pulse Skipping Thresholds
–
–
200
180
–
–
mV
TWARN_PRE
VPRE Thermal Warning Threshold
–
105
–
°C
VPRE voltage pre-regulator (continued)
VPRE_UV_HYST
VPRE_UV_4P3
VPRE_UV_4P3_
HYST
RDSON_PRE
LIR_VPRE
TSD_PRE
VPRE Thermal Shutdown Threshold
160
–
–
°C
TSD_PRE_HYST
VPRE Thermal Shutdown Hysteresis
–
10
–
°C
VPRE-1
–
VPRE
V
–
–
0.5
V
0.784
0.8
0.816
V
–
–
–
–
0.8
1.5
A
1
1.8
–
–
2
3.5
A
–
–
200
mΩ
VG_LS_OH
LS Gate Driver High Output Voltage (IOUT = 50 mA)
VG_LS_OL
LS Gate driver Low Level (IOUT = 50 mA)
(9)
(9)
Vcore voltage regulator
VCORE_FB
ICORE
ICORE_LIM
RDSON_CORE
VCORE Feedback Input Voltage
VCORE Output Current Capability in Normal Mode
• FS6407N
• FS6408N
VCORE Output Current Limitation
• FS6407N
• FS6408N
VCORE Pass Transistor On Resistance
LORVCORE_1.2
VCORE Transient Load regulation - 1.2 V range
-60
–
60
mV
(9), (10)
LORVCORE_3.3
VCORE Transient Load regulation - 3.3 V range
-100
–
100
mV
(9) (10)
VCORE_LL_H
VCORE_LL_L
VCORE Pulse Skipping Thresholds
–
–
180
160
–
–
mV
TWARN_CORE
VCORE Thermal Warning Threshold
–
105
–
°C
TSD_CORE
VCORE Thermal Shutdown Threshold
160
–
–
°C
TSD_CORE_HYST
VCORE Thermal Shutdown Hysteresis
–
10
–
°C
,
(9)
Notes
9.
10.
Guaranteed by design
COUT = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs
FS6407/FS6408
NXP Semiconductors
11
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
4.95
4.9
4.85
3.2505
3.234
3.201
5.0
5.0
5.0
3.3
3.3
3.3
5.05
5.1
5.15
3.3495
3.366
3.399
Unit
Notes
V
(11)
VCCA voltage regulator
VCCA
VCCA Output Voltage
• 5.0 V config. with Internal ballast at 100 mA
• 5.0 V config with external ballast at 200 mA
• 5.0 V config with external ballast at 300 mA
• 3.3 V config with Internal ballast at 100 mA
• 3.3 V config with external ballast at 200 mA
• 3.3 V config with external ballast at 300 mA
ICCA_IN
VCCA Output Current (int. MOSFET)
–
–
100
mA
ICCA_OUT
VCCA Output Current (external PNP)
–
–
300
mA
ICCA_LIM_INT
VCCA Output Current Limitation (int. MOSFET)
100
–
675
mA
ICCA_LIM_OUT
VCCA Output Current Limitation (external PNP)
300
–
675
mA
ICCA_LIM_FB
VCCA Output Current Limitation Foldback
80
–
200
mA
VCCA_LIM_FB
VCCA Output Voltage Foldback Threshold
0.5
–
1.1
V
VCCA_LIM_HYST
VCCA Output Voltage Foldback Hysteresis
0.03
–
0.3
V
VCCA Base Current Capability
–
20
–
–
30
–
mA
VCCA Thermal Warning Threshold (int. MOSFET only)
–
105
–
°C
160
–
–
°C
VCCA Thermal Shutdown Hysteresis
–
10
–
°C
(12)
VCCA Transient Load Regulation
• ICCA = 10 mA to 100 mA (internal MOSFET)
• ICCA = 10 mA to 300 mA (external ballast)
–
–
1.0
%
(12)
ICCA_BASE_SC
ICCA_BASE_SK
TWARN_CCA
TSDCCA
TSDCCA_HYST
LORTVCCA
VCCA Thermal Shutdown Threshold (int. MOSFET only)
Notes
11. External PNP gain within 150 to 450
12. Guaranteed by design.
FS6407/FS6408
12
NXP Semiconductors
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Vaux voltage regulator
VAUX_5
VAUX Output Voltage (5.0 V configuration)
4.85
5.0
5.15
V
VAUX_33
VAUX Output Voltage (3.3 V configuration)
3.2
3.3
3.4
V
VAUX_TRK
VAUX Tracking Error (VAUX_5 and VAUX_33)
-15
–
+15
mV
IAUX_OUT
VAUX Output Current
–
–
300
mA
IAUX_LIM
VAUX Output Current Limitation
300
–
700
mA
IAUX_LIM_FB
VAUX Output Current Limitation Foldback
100
–
530
mA
VAUX_LIM_FB
VAUX Output Voltage Foldback Threshold
0.5
–
1.1
V
VAUX_LIM_HYST
VAUX Output Voltage Foldback Hysteresis
0.03
–
0.3
V
VAUX Base Current Capability
–
7.0
–
–
-7.0
–
mA
TSDAUX
VAUX Thermal Shutdown Threshold
160
–
–
°C
TSDAUX_HYST
VAUX Thermal Shutdown Hysteresis
–
10
–
°C
(13)
VAUX Static Load Regulation (IAUX_OUT = 10 mA to 300 mA)
–
15
–
mV
(13)
VAUX Transient Load Regulation
• IAUX_OUT = 10 mA to 300 mA
–
–
1.0
%
(13)
4.8
5.0
5.2
V
–
–
100
mA
IAUX_BASE_SC
IAUX_BASE_SK
LORVAUX
LORTVAUX
CAN_5V voltage regulator
VCAN
VCAN Output Voltage
VSUP > 6.0 V in Buck mode
VSUP > VSUP_UV_L in Boost mode
ICAN_OUT
VCAN Output Current
ICAN_LIM
VCAN Output Current Limitation
100
–
250
mA
TSDCAN
VCAN Thermal Shutdown Threshold
160
–
–
°C
TSDCAN_HYST
VCAN Thermal Shutdown Hysteresis
–
10
–
°C
VCAN Undervoltage Detection Threshold
4.25
–
4.8
V
VCAN Undervoltage Hysteresis
0.07
–
0.22
V
VCAN Overvoltage Detection Threshold
5.2
–
5.55
V
VCAN Overvoltage Hysteresis
0.07
–
0.22
V
–
100
–
mV
VCAN_UV
VCAN_UV_HYST
VCAN_OV
VCAN_OV_HYST
LORVCAN
VCAN Load Regulation (from 0 to 50 mA)
(13)
(13)
Notes
13.
Guaranteed by design.
FS6407/FS6408
NXP Semiconductors
13
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
7.2
–
8.0
V
–
0.1
–
V
Notes
Fail-safe machine voltage supervisor
VPRE_OV
VPRE Overvoltage Detection Threshold
VPRE_OV_HYST
VPRE Overvoltage Hysteresis
VCORE_FB_UV
VCORE FB Undervoltage Detection Threshold
0.67
–
0.773
V
VCORE FB Undervoltage Detection Threshold - Degraded mode
0.45
–
0.58
V
10
–
27
mV
0.84
–
0.905
V
VCORE FB Overvoltage Hysteresis
10
–
30
mV
VCORE_FB Drift versus IO_1
50
100
150
mV
VCORE Internal Pull-down Current (active when VCOR E is enabled)
5.0
12
25
mA
VCCA_UV_5
VCCA Undervoltage Detection Threshold (5.0 V config)
4.5
–
4.75
V
VCCA_UV_5D
VCCA Undervoltage Detection Threshold (Degraded 5.0 V)
3.0
–
3.2
V
VCCA_UV_33
VCCA Undervoltage Detection Threshold (3.3 V config)
3.0
–
3.2
V
–
0.07
–
V
VCORE_FB_UV_D
VCORE_FB_UV_
HYST
VCORE_FB_OV
VCORE_FB_OV_HYS
T
VCORE_FB_DRIFT
IPD_CORE
VCCA_UV_HYST
VCORE FB Undervoltage Hysteresis
VCORE FB Overvoltage Detection Threshold
VCCA Undervoltage Hysteresis
VCCA_OV_5
VCCA Overvoltage Detection Threshold (5.0 V config)
5.25
–
5.5
V
VCCA_OV_33
VCCA Overvoltage Detection Threshold (3.3 V config)
3.4
–
3.6
V
VCCA Overvoltage Hysteresis
–
0.15
–
V
VCCA Internal Pull-down Resistor (active when VCCA is disabled)
50
–
160
Ω
VAUX_UV_5
VAUX Undervoltage Detection Threshold (5.0 V config)
4.5
–
4.75
V
VAUX_UV_5D
VAUX Undervoltage Detection Threshold (Degraded 5.0 V)
3.0
–
3.2
V
VAUX_UV_33
VAUX Undervoltage Detection Threshold (3.3 V config)
3.0
–
3.2
V
–
0.07
–
V
VCCA_OV_HYST
RPD_CCA
VAUX_UV_HYST
VAUX Undervoltage Hysteresis
VAUX_OV_5
VAUX Overvoltage Detection Threshold (5.0 V config)
5.25
–
5.5
V
VAUX_OV_33
VAUX Overvoltage Detection Threshold (3.3 V config)
3.4
–
3.6
V
VAUX Overvoltage Hysteresis
–
0.07
–
V
VAUX Internal Pull-down Resistor (active when VAUX is disabled)
50
–
170
Ω
VAUX_OV_HYST
RPD_AUX
(14)
(14)
(14)
(14)
(14)
(14)
(14)
Notes
14.
Guaranteed by design.
FS6407/FS6408
14
NXP Semiconductors
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VRSTB_OL
Reset Low Output Level (I_RSTB = 2.0 mA and 2.0 V < VSUP < 40 V)
–
–
0.5
V
(15)
IRSTB_LIM
Reset Output Current Limitation
12
–
25
mA
VRSTB_IL
External Reset Detection Threshold (falling)
1.0
–
–
V
VRSTB_IH
External Reset Detection Threshold (rising)
–
–
2.0
V
0.2
–
–
V
Fail-safe outputs
VRSTB_IN_HYST
External Reset Input Hysteresis
VFS0B_OL
FS0B Low Output Level (I_FS0b = 2.0 mA)
–
–
0.5
V
IFS0B_LK
FS0B Input Current Leakage (VFS0B = 28 V)
–
–
1.0
µA
IFS0B_LIM
FS0B Output Current Limitation
6.0
–
12
mA
Digital High Input voltage level (IO_0:1, IO_4:5)
• Min Limit = 2.7 V at VSUP = 40 V
2.6
–
–
V
Digital High Input voltage level (IO_2, IO_3)
2.0
–
–
V
Digital Low Input voltage Level (IO_0:1; IO_4:5)
–
–
2.1
V
VIO_HYST
Input Voltage Hysteresis (IO_0:1, IO_4:5)
50
120
500
mV
VIO23_IL
Digital Low Input voltage Level (IO_2, IO_3)
–
–
0.9
V
Input Voltage Hysteresis (IO_2, IO_3)
200
450
700
mV
Input Current for IO_0:1
-5.0
–
100
µA
Input Current for IO_1 when used for FB_Core monitoring
-1.0
–
1.0
µA
Input Current for IO_2:5
-5.0
–
5.0
µA
Input Current for IO_0:5 in LPOFF
-1.0
–
1.0
µA
Digital input
VIO_IH
VIO23_IH
VIO_IL
VIO23_HYST
IIO_IN_0:1
IIO_IN_1
IIO_IN_2:5
IIO_IN_LPOFF
(16)
(16)
Output gate driver
VIO_OH
High Output Level at IIO_OUT = -2.5 mA
VPRE - 1.5
–
VPRE
V
VIO_OL
Low Output Level at IIO_OUT = +2.5 mA
0.0
–
1.0
V
Output Current Capability
2.5
–
–
–
–
-2.5
mA
VIO_OUT_SK
VIO_OUT_SC
Analog multiplexer
VAMUX_REF1
Internal Voltage Reference with 6.0 V < VSUP < 19 V
2.475
2.5
2.525
V
VAMUX_REF2
Internal Voltage Reference with VSUP ≤ 6.0 V or VSUP ≥ 19 V
2.468
2.5
2.532
V
–
9.9
–
mV/°C
2.08
2.15
2.22
V
VAMUX_TP_CO
VAMUX_TP
Internal Temperature sensor coefficient
Temperature Sensor MUX_OUT output voltage (at TJ=165°C)
(16)
Notes
15. For VSUP < 2.0 V, all supplies are already off and external pull-up on RSTB (e.g VCORE or VCCA) pulls the line down.
16.
Guaranteed by design.
FS6407/FS6408
NXP Semiconductors
15
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Interrupt
VINTB_OL
Low Output Level (IINT = 2.5 mA)
–
–
0.5
V
RPU_INT
Internal Pull-up Resistor (connected to VDDIO)
–
10
–
KΩ
IINT_LK
Input Leakage Current
–
–
1
µA
CAN transceiver
CAN logic input pin (TXD)
VTXD_IH
TXD High Input Threshold
0.7 x VDDIO
–
–
V
VTXD_IL
TXD Low Input Threshold
–
–
0.3 x VDDIO
V
TXDPULL-UP
TXD Main Device Pull-up
20
33
50
KΩ
-1.0
–
1.0
µA
TXDLK
TXD Input Leakage Current, VTXD = VDDIO
CAN logic output pin (RXD)
VRXD_OL1
Low Level Output Voltage (IRXD = 250 µA)
–
–
0.4
V
VRXD_OL2
Low Level Output Voltage (IRXD = 1.5 mA)
–
–
0.9
V
VOUTHIGH
High Level Output Voltage (IRXD = -250 µA, VDDIO = 3.0 V to 5.5 V)
VDDIO 0.4V
–
–
V
Differential Input Comparator Common Mode Range
-12
–
12
V
Differential Input Voltage Threshold in Sleep Mode
0.5
–
0.9
V
VIN_HYST
Differential Input Hysteresis (in TX, RX mode)
50
–
–
mV
RIN_CHCL
CANH, CANL Input Resistance
5.0
–
50
kΩ
RIN_DIFF
CAN Differential Input Resistance
10
–
100
kΩ
Input Resistance Matching
-3.0
–
3.0
%
VCANH
CANH Output Voltage (45 Ω < RBUS < 65 Ω)
• TX dominant state
• TX recessive state
2.75
2.0
–
2.5
4.5
3.0
V
VCANL
CANL Output Voltage (45 Ω < RBUS < 65 Ω)
• TX dominant state
• TX recessive state
0.5
2.0
–
2.5
2.25
3.0
V
CAN dominant voltage symmetry (VCANL + VCANH)
4.5
5
5.5
V
VOH-VOL
Differential Output Voltage
• TX dominant state (45 Ω < RBUS < 65 Ω)
• TX recessive state
1.5
-50
2.0
0.0
3.0
50
V
mV
ICANL-SK
CANL Sink Current Under Short-circuit Condition (VCANL ≤ 12 V, CANL
driver ON, TXD low)
40
–
100
mA
ICANH-SC
CANH Source Current Under Short-circuit Condition (VCANH = -2.0 V,
CANH driver ON, TXD low)
-100
–
-40
mA
RINSLEEP
CANH, CANL Input Resistance Device Supplied and in CAN Sleep
Mode
5.0
–
50
kΩ
CAN Output pins (CANH, CANL)
VDIFF_COM_MODE
VIN_DIFF_SLEEP
RIN_MATCH
VCAN_SYM
FS6407/FS6408
16
NXP Semiconductors
Table 4. Operating range (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
-0.1
0.0
0.1
V
-10
-10
–
–
10
10
µA
µA
Notes
CAN output pins (CANH, CANL) (continued)
VCANLP
CANL, CANH Output Voltage in Sleep Modes. No termination load.
ICAN
CANH, CANL Input Current, Device Unsupplied, (VCANH, VCANL =5.0V)
• VSUP and VCAN connected to GND
TOT
Overtemperature Detection
160
–
–
°C
THYST
Overtemperature Hysteresis
–
–
20
°C
• VSUP and VCAN connected to GND via 47k resistor
(17)
Digital interface
MISOH
High Output Level on MISO (IMISO = 1.5 mA)
VDDIO - 0.4
–
–
V
MISOL
Low Output Level on MISO (IMISO = 2.0 mA)
–
–
0.4
V
IMISO
Tri-state Leakage Current (VDDIO = 5.0 V)
-5.0
–
5.0
µA
VDDIO
Supply Voltage for MISO Output Buffer
3.0
–
5.5
V
IVDDIO
Current consumption on VDDIO
–
1.0
3.0
mA
SPILK
SCLK, NCS, MOSI Input Current
-1.0
–
1.0
µA
SCLK, NCS, MOSI High Input Threshold
2.0
–
–
V
NCS, MOSI Internal Pull-up (pull-up to VDDIO)
200
400
800
KΩ
–
–
0.8
V
VSPI_IH
RSPI
VSPI_IL
SCLK, NCS, MOSI Low Input Threshold
Debug
VDEBUG_IL
Low Input Voltage Threshold
2.1
2.35
2.6
V
VDEBUG_IH
High Input Voltage Threshold
4.35
4.6
4.97
V
IDEBUG_LK
Input Leakage Current
-10
–
10
µA
Notes
17. Guaranteed by design and characterization.
FS6407/FS6408
NXP Semiconductors
17
4.3
Dynamic electrical characteristics
Table 5. Dynamic electrical characteristics
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Digital interface timing
fSPI
SPI Operation Frequency (50% DC)
0.5
–
8.0
MHz
tMISO_TRANS
MISO Transition Speed, 20 - 80%
• VDDIO = 5.0 V, CLOAD = 50 pF
• VDDIO = 5.0 V, CLOAD = 150 pF
5.0
5.0
–
–
30
50
ns
tCLH
Minimum Time SCLK = HIGH
62
–
–
ns
tCLL
Minimum Time SCLK = LOW
62
–
–
ns
tPCLD
Propagation Delay (SCLK to data at 10% of MISO rising edge)
–
–
30
ns
tCSDV
NCS = LOW to Data at MISO Active
–
–
75
ns
tSCLCH
SCLK Low Before NCS Low (setup time SCLK to NCS change H/L)
75
–
–
ns
tHCLCL
SCLK Change L/H after NCS = low
75
–
–
ns
tSCLD
SDI Input Setup Time (SCLK change H/L after MOSI data valid)
40
–
–
ns
tHCLD
SDI Input Hold Time (MOSI data hold after SCLK change H/L)
40
–
–
ns
tSCLCL
SCLK Low Before NCS High
100
–
–
ns
tHCLCH
SCLK High After NCS High
100
–
–
ns
tPCHD
NCS L/H to MISO at High-impedance
–
–
75
ns
NCS Min. High Time
500
–
–
ns
NCS Filter Time
10
–
40
ns
tSCLCL
tHCLCH
tONNCS
tNCS_MIN
NCS
tONNCS
tSCLCH
tHCLCL
tCLH
tCLL
SCLK
MISO
tPCHD
z
tPCLD
tCSDV
Tri-state
Not used
LSB
MSB
tHCLD
tSCLD
MOSI
LSB
MSB
Figure 5. SPI timing diagram
500 ns min
NCS
3.5 µs min
AnyFail
Fail-safe
Any
Safe
registeracces
access
register
Any main
Any Main
register
register
access
acces
AnyFail
Fail-safe
Any
Safe
register acces
access
register
Figure 6. Register access restriction
FS6407/FS6408
18
NXP Semiconductors
Table 5. Dynamic electrical characteristics (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
CAN dynamic characteristics
tDOUT
TXD Dominant State Timeout
0.8
–
5.0
ms
tDOM
Bus Dominant Clamping Detection
0.8
–
5.0
ms
tLOOP
Propagation Loop Delay TXD to RXD
• RLOAD = 120 Ω, C between CANH and CANL = 100 pF,
C at RxD < 15 pF
–
–
255
ns
t1PWU
Single Pulse Wake-up Time
0.5
–
5.0
µs
t3PWU
Multiple Pulse Wake-up Time
0.5
–
1.0
µs
t3PTO1
Multiple Pulse Wake-up Timeout (120 µs bit selection)
100
120
–
µs
t3PTO2
Multiple Pulse Wake-up Timeout (360 µs bit selection)
330
360
–
µs
–
–
100
µs
tCAN_READY
Delay to Enable CAN by SPI Command (NCS rising edge) to CAN to
Transmit (device in normal mode and CAN interface in TX/RX mode)
(18)
Fail-safe state machine
OSCFSSM
Oscillator
405
–
495
kHz
CLKFS_MIN
Fail-safe Oscillator Monitoring
150
–
–
kHz
tIC_ERR
IO_0:5 Filter Time
4.0
–
20
µs
tACK_FS
Acknowledgement Counter (used for IC error handling IO_1 and IO_5)
7.0
–
9.7
ms
t_DFS_RECOVERY
IO_0 Filter Time to Recover from Deep Reset and Fail State
0.8
–
1.3
ms
tIO1_DRIFT_MON
IO_1 filter time
1.0
–
2.0
ms
tRSTB_FB
RSTB Feedback Filter Time
8.0
–
15
µs
tFSOB_FB
FS0B Feedback Filter Time
8.0
–
15
µs
tRSTB_BLK
RSTB Feedback Blanking Time
180
–
320
µs
tFSOB_BLK
FS0B Feedback Blanking Time
180
–
320
µs
tRSTB_POR
Reset Delay Time (after a Power On Reset or from LPOFF)
12
15.9
23.6
ms
tRSTB_LG
Reset Duration (long pulse)
8.0
–
10
ms
tRSTB_ST
Reset duration (short pulse)
1.0
–
1.3
ms
tRSTB_IN
External Reset Delay time
8.0
–
15
µs
tDIAG_SC
Fail-safe Output Diagnostic Counter (FS0B)
550
–
800
µs
44
–
–
µF
Fail-safe output
(19)
VSUP voltage supply
CSUP
Minimum capacitor on Vsup
Notes
18. For proper CAN operation, TXD must be set to high level before CAN enable by SPI, and must remain high for at least TCAN_READY.
19.
This timing is not guaranteed in case of fault during startup phase (after Power On Reset of from LPOFF)
FS6407/FS6408
NXP Semiconductors
19
Table 5. Dynamic electrical characteristics (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
412
437.5
465
kHz
–
–
30
ns
VPRE Soft Start Duration (COUT ≤ 100 µF)
500
–
700
µs
VPRE Current Limitation Blanking Time
200
–
600
ns
tIPRE_OC
VPRE Overcurrent Filtering Time
30
–
120
ns
tPRE_UV
VPRE Undervoltage Filtering Time
20
–
40
µs
Vpre Shut-off Filtering Time
3.0
–
7.0
µs
VPRE Load Regulation Variation
–
–
25
A/ms
tPRE_WARN
VPRE Thermal Warning Filtering Time
30
–
40
µs
tPRE_TSD
VPRE Thermal Detection Filtering Time
1.0
–
3.0
µs
–
–
50
ns
1.0
–
3.0
µs
20
–
40
ns
Notes
VPRE voltage pre-regulator
fSW_PRE
VPRE Switching Frequency
tSW_PRE
VSW_PRE On and Off Switching Time
tPRE_SOFT
tPRE_BLK_LIM
tPRE_UV_4p3
dIPRE/DT
tLS_RISE/FALL
LS Gate Voltage Switching Time (IOUT = 300 mA)
(20)
(20)
(20)
Vsense voltage regulator
tVSNS_UV
VSNS Undervoltage Filtering Time
Vcore voltage regulator
tCORE_BLK_LIM
VCORE Current Limitation Blanking Time
fSW_CORE
VCORE Switching Frequency
2.20
2.34
2.49
MHz
tSW_CORE
VSW_CORE On and Off Switching Time
6.0
–
12
ns
VCORE_SOFT
VCORE Soft Start (COUT = 100 µF max)
–
–
10
V/ms
tCORE_WARN
VCORE Thermal Warning Filtering Time
30
–
40
µs
tCORE_TSD
VCORE Thermal Detection Filtering Time
1.0
–
3.0
µs
VCCA Output Current Limitation Filter Time
1.0
–
3.0
µs
VCCA Output Current Limitation Duration
10
50
–
–
–
–
ms
VCCA Thermal Warning Filtering Time
30
–
40
µs
tCCA_TSD
VCCA Thermal Detection Filter Time (int. MOSFET)
1.0
–
3.0
µs
dILOAD/dt
VCCA Load Transient
–
2.0
–
A/ms
VCCA Soft Start (5.0 V and 3.3 V)
–
–
50
V/ms
Vcca voltage regulator
tCCA_LIM
tCCA_LIM_OFF1
tCCA_LIM_OFF2
tCCA_WARN
VCCA_SOFT
(20)
Notes
20. Guaranteed by characterization.
FS6407/FS6408
20
NXP Semiconductors
Table 5. Dynamic electrical characteristics (continued)
TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to
ground.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VAUX Output Current Limitation Filter Time
1.0
–
3.0
µs
VAUX Output Current Limitation Duration
10
50
–
–
–
–
ms
tAUX_TSD
VAUX Thermal Detection Filter Time
1.0
–
3.0
µs
dIAUX/dt
VAUX Load Transient
–
2.0
–
A/ms
VAUX Soft Start (5.0 V and 3.3 V)
–
–
50
V/ms
Notes
Vaux voltage regulator
tAUX_LIM
tAUX_LIM_OFF1
tAUX_LIM_OFF2
VAUX_SOFT
(21)
CAN_5V voltage regulator
tCAN_LIM
Output Current Limitation Filter Time
2.0
–
4.0
µs
tCAN_TSD
VCAN Thermal Detection Filter Time
1.0
–
3.0
µs
tCAN_UV
VCAN Undervoltage Filtering Time
4.0
–
7.0
µs
tCAN_OV
VCAN Overvoltage Filtering Time
100
–
200
µs
dICAN/dt
VCAN Load Transient
–
100
–
A/ms
VPRE Overvoltage Filtering Time
128
–
234
µs
tCORE_UV
VCORE FB Undervoltage Filtering Time
4.0
–
10
µs
tCORE_OV
VCORE FB Overvoltage Filtering Time
128
–
234
µs
tCCA_UV
VCCA Undervoltage Filtering Time
4.0
–
10
µs
tCCA_OV
VCCA Overvoltage Filtering Time
128
–
234
µs
tAUX_UV
VAUX Undervoltage Filtering Time
4.0
–
10
µs
tAUX_OV
VAUX Overvoltage Filtering Time
128
–
234
µs
0.0
–
100
kHz
SPI Selection to Data Ready to be Sampled on Mux_out
• VDDIO = 5.0 V, CMUX_OUT = 1.0 nF
–
–
10
tINTB_LG
INTB Pulse Duration (long)
90
100
–
µs
tINTB_ST
INTB Pulse Duration (short)
20
25
–
µs
60
70
80
µs
(21)
Fail-safe machine voltage supervisor
tPRE_OV
Digital input - multi-purpose IOS
FIO_IN
Digital Input Frequency Range
Analog multiplexer
tMUX_READY
µs
Interrupt
Functional sate machine
tWU_GEN
General Wake-up Signal Deglitch Time (for any wu signal on IOs)
Notes
21. Guaranteed by characterization.
FS6407/FS6408
NXP Semiconductors
21
5
5.1
Functional pin description
Introduction
The FS6407/FS6408 is the third generation of the System Basis Chip, combining:
• High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as
sensors, and accurate reference voltage for A to D converters.
• Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, protection, and Fail-safe
operation mode.
• Low-power mode, with ultra low-current consumption.
• Various wake-up capabilities.
• Enhanced safety features with multiple fail-safe outputs and scheme to support SIL applications.
5.2
Power supplies (VSUP1, VSUP2, VSUP3)
VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage
reference. VSUP1, 2, and 3 are robust against ISO7637 pulses. VSUP1,2, and 3 must be connected to the same supply (Figure 49).
5.3
VSENSE input (VSENSE)
This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold
detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE
voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulses.
5.4
Pre-regulator (VPRE)
A highly flexible SMPS pre-regulator is implemented in the FS6407/FS6408. It can be configured as a “non-inverting buck-boost converter”
(Figure 24) or “standard buck converter” (Figure 23), depending on the external configuration (connection of pin GATE_LS). The
configuration is detected automatically during start-up sequence.
The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side
switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a typical output voltage of 6.5 V, which
is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default.
5.5
VCORE output (from 1.2 V to 3.3 V range)
The VCORE block is an SMPS regulator. The voltage regulator is a step down DC-DC converter operating in voltage control mode. The
output voltage is configurable from 1.2 V to 3.3 V range thanks to an external resistor divider connected between VCORE and the
feedback pin (FB_CORE) (as example in Figure 1, Figure 2, and Figure 49).
The stability of the converter is done externally, by using the COMP_CORE pin. Current limitation, overvoltage, and undervoltage
detectors are provided. VCORE can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCORE by
SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCORE
overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled
by default.
FS6407/FS6408
22
NXP Semiconductors
5.6
VCCA output, 5.0 V or 3.3 V selectable
The VCCA voltage regulator is used to provide an accurate voltage output (5.0 V, 3.3 V) selectable through an external resistor connected
to the SELECT pin.
The VCCA output voltage regulator can be configured using an internal transistor delivering very good accuracy (±1.0% for 5.0 V
configuration and ±1.5% for 3.3 V configuration), with a limited current capability (100 mA) for an analog to digital converter, or with an
external PNP transistor, giving higher current capability (up to 300 mA) with lower output voltage accuracy (±3.0% for 300 mA) when using
a local supply.
Current limitation, overvoltage, and undervoltage detectors are provided. VCCA can be turned ON or OFF via a SPI command, however
it is not recommended to turn OFF VCCA by SPI when VCCA is configured safety critical (both overvoltage and undervoltage have an
impact on RSTB and FS0B). VCCA overcurrent (with the use of external PNP only) and overvoltage information disables VCCA.
Diagnostics are reported in the dedicated register and generate an Interrupt. VCCA is enabled by default.
5.7
VAUX output, 5.0 V or 3.3 V selectable
The VAUX pin provides an auxiliary output voltage (5.0 V, 3.3 V) selectable through an external resistor connected to SELECT pin. It uses
an external PNP ballast transistor for flexibility and power dissipation constraints. The VAUX output voltage regulator can be used as
“auxiliary supply” (local supply) or “sensor supply” (external supply) with the possibility to be configured as a tracking regulator following
VCCA.
Current limitation, overvoltage, and undervoltage detectors are provided. VAUX can be turned ON or OFF via a SPI command, however
it is not recommended to turn OFF VAUX by the SPI when VAUX is configured safety critical (both overvoltage and undervoltage have an
impact on RSTB and FS0B). VAUX overcurrent and overvoltage information disables VAUX, reported in the dedicated register, and
generates an Interrupt. VAUX is enabled by default.
5.8
SELECT input (VCCA, VAUX voltage configuration)
VCCA and VAUX output voltage configurations are set by connecting an external resistor between the SELECT pin and Ground.
According to the value of this resistor, the voltage of VCCA and VAUX are configured after each Power On Reset, and after a wake-up
event when device is in LPOFF. Information latches until the next hardware configuration read. Regulator voltage values can be read on
the dedicated register via the SPI.
Table 6. VCCA/VAUX voltage selection (Figure 50)
VCCA(V)
VAUX(V)
R Select
Recommended value
3.3
3.3
VAUX_UV
VPREVPRE_UV
SELECT pin
config.
detection
VPRE VCORE_UV &
VCCA > VCCA_UV &
VAUX > VAUX_UV
ABIST
RSTb delay = 8s
IO_0
- RSTb is asserted low
ABIST Pass
- RSTb delay running
- RSTb is asserted low
RST delay=8s OR
Rst_error_count=6
- VCAN/VCORE OFF
- VAUX/VCCA OFF
- Fail Safe OFF Deep Fail
Safe
- FS0b = Low
- RSTb = Low
Assert RSTb
No activate RST &
RST delay expired
Activate RST
FS0b low & No
activate RST &
RST delay expired
External
RST
- RSTb is released
No external RST &
No activate RST
External RSTb =
8s
External
RST
Activate
RST
2 > RST_error_count < 6
Release
RSTb
Activate RST or
WD Not OK
INIT FS
- Unlock SPI init registers
- Start 256ms open window
- RSTb is released
WD OK
RST delay=8s
- FS0b is asserted low
FS0B Low
Ext. IC error (IO0:1
and/or IO4:5)
Ext. IC error (IO0:1
and/or IO4:5)
External
RST
RST_err_count = 0
& FS_OUT ok
NORMAL
WD is
RUNNING
- Start WD close/open window
Release
FSOb
-FS0b is
released
No FS0b
Figure 11. Detailed fail-safe state diagram
FS6407/FS6408
NXP Semiconductors
33
6.5.2
Watchdog operation
A windowed watchdog is implemented in the FS6407/FS6408 and is based on “question/answer” principle (Challenger). The watchdog
must be continuously triggered by the MCU in the open watchdog window, otherwise an error is generated. The error handling and
watchdog operations are managed by the Fail-safe state machine. For debugging purpose, this functionality can be inhibited by setting
the right voltage on the DEBUG pin at start-up.
The watchdog window duration is selectable through the SPI during the INIT FS phase or in Normal mode. The following values are
available: 1.0 ms, 2.0 ms, 3.0 ms, 4.0 ms, 6.0 ms, 8.0 ms, 12 ms, 16.0 ms, 24 ms, 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, and 1024 ms.
The watchdog can also be inhibited through the SPI register to allow “reprogramming” (ie.at vehicle level through CAN).
An 8-bit pseudo-random word is generated, due to a linear feedback shift register implemented in the FS6407/FS6408. The MCU can
send the seed of the LFSR or use the LFSR generated by the FS6407/FS6408 during the INIT phase and performs a pre-defined
calculation. The result is sent through the SPI during the “open” watchdog window and verified by the FS6407/FS6408. When the result
is right, a new LFSR is generated and the watchdog window is restarted. When the result is wrong, the WD error counter is incremented,
the watchdog window is restarted, and the LFSR value is not changed. Any access to the WD register during the “closed” watchdog
window is considered a wrong WD refresh.
6.5.2.1
Normal operation (first watchdog refresh)
At power up, when the RSTB is released as high (after around 16 ms), the INIT phase starts for a maximum duration of 256 ms and this
is considered as a fully open watchdog window. During this initialization phase the MCU sends the seed for the LFSR, or uses the default
LFSR value generated by the FS6407/FS6408 (0xB2), available in the WD_LFSR register (Table 74). Using this LFSR, the MCU performs
a simple calculation based on this formula. As an example, the result of this calculation based on LFSR default value (0xB2) is 0x4D.
LFSR_OUT[7:0]
x
+
-
4
6
4
NOT
/
WD_answer[7:0]
4
Figure 12. Watchdog answer calculation
The MCU sends the results in the WD answer register (Table 76). When the watchdog is properly refreshed during the open window, the
256 ms open window is stopped and the initialization phase is finished. A new LFSR is generated and available in the WD LFSR register,
Table 73. If the watchdog refresh is wrong or if the watchdog is not refreshed during this 256 ms open window (INIT FS phase), the device
asserts the reset low and the RSTB error counter is incremented by “1”.
After a good watchdog refresh, the device enters the Normal WD refresh mode, where open and closed windows are defined either by
the configuration made during initialization phase in the watchdog window register (Table 72), or by the default value already present in
this register (3.0 ms).
6.5.2.2
Normal watchdog refresh
The watchdog must be refreshed during every open window of the window period configured in the register Table 72. Any WD refresh
restarts the window. This ensures the synchronization between MCU and FS6407/FS6408.
The duration of the “window” is selectable through the SPI with no access restriction, means the window duration can be changed in the
INIT phase or Normal mode. Doing the change in normal operation allow the system integrator to configure the watchdog window duration
on the fly:
• The new WD window duration (except after disable) is taken into account when a write in the WD_answer register occurs (good or bad
WD answer) or when the previous WD window is finished without any writing (WD timeout)
• The new WD window duration after disable is taken into account when SPI command is validated
The duty cycle of the window is set to 50% and is not modifiable.
Window Period
CLOSED
OPEN
Refresh
Slot
CLOSED
OPEN
Refresh
Slot
Figure 13. Windowed watchdog
FS6407/FS6408
34
NXP Semiconductors
6.5.2.3
Watchdog in debug mode
When the device is in debug mode (entered via the DEBUG pin), the watchdog continues to operate, but does not affect the device
operation by asserting a reset or fail-safe pins. For the user, operation appears without the watchdog. If needed and to debug the
watchdog itself, the user can operate as in Normal mode and check LFSR values, the watchdog refresh counter, the watchdog error
counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application.
6.5.2.4
Wrong watchdog refresh handling
Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU. According to consecutive
numbers of wrong watchdog refreshes, the device can decide to assert the RSTB only, or to go in deep Fail-safe mode where only a Power
On Reset or a transition on IO_O helps the system to recover.
6.5.2.5
Watchdog error counter
The watchdog error counter is implemented in the device to filter the incorrect watchdog refresh. Each time a watchdog failure occurs, the
device increments this counter by 2. The WD error counter is decremented by 1 each time the watchdog is properly refreshed. This
principle ensures that a cyclic “OK/NOK” behavior converges to a failure detection. To allow flexibility in the application, the maximum
value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode.
Watchdog Error Counter
WD_CNT_error = 6
WD refresh NOK
0
WD refresh NOK
1
WD refresh NOK
2
Watchdog Error Counter
WD_CNT_error = 4
WD refresh NOK
0
WD refresh NOK
1
WD refresh NOK
2
WD refresh OK
WD refresh NOK
0
WD refresh OK
WD refresh OK
1
WD refresh OK
WD refresh OK
WD refresh NOK
Watchdog Error Counter
WD_CNT_error = 2
2
WD refresh OK
3
3
WD refresh NOK
WD refresh OK
WD refresh NOK
4
4
WD refresh OK
5
WD refresh NOK
6
Figure 14. Watchdog error counter configuration (INIT_WD register, bits WD_CNT_error_1:0)
FS6407/FS6408
NXP Semiconductors
35
6.5.2.6
Watchdog refresh counter
The watchdog refresh counter is used to decrement the RST error counter. Each time the watchdog is properly refreshed, the watchdog
refresh counter is incremented by “1”. Each time the watchdog refresh counter reaches “6” and if next WD refresh is also good, the RST
error counter is decremented by “1” (case with WD_CNT_refresh_1:0 configured at 6).
Whatever the position is in the watchdog refresh counter, each time there is a wrong refresh watchdog, the watchdog refresh counter is
reset to “0”. To allow flexibility in the application, the maximum value of this watchdog refresh counter is configurable in the INIT_WD
register, but only when device is in INIT FS mode.
Watchdog Refresh Counter
WD_CNT_refresh = 6
Watchdog Refresh Counter
WD_CNT_refresh = 4
WD Refresh NOK
2
WD Refresh OK
3
WD Refresh OK
4
WD Refresh OK
5
WD Refresh OK
6
WD Refresh OK
WD Refresh NOK /
WD_OFF
WD Refresh OK
WD Refresh NOK /
WD_OFF
WD Refresh OK
WD Refresh NOK /
WD_OFF
0
WD Refresh OK
1
WD Refresh NOK /
WD_OFF
2
3
4
WD Refresh NOK
0
0
WD Refresh OK
1
Watchdog Refresh Counter
WD_CNT_refresh = 1
WD Refresh NOK
WD Refresh NOK
0
WD Refresh OK
WD Refresh OK
Watchdog Refresh Counter
WD_CNT_refresh = 2
WD Refresh NOK /
WD_OFF
WD Refresh OK
1
WD Refresh OK
2
WD Refresh NOK /
WD_OFF
WD Refresh NOK /
WD_OFF
1
WD Refresh OK /
WD Refresh NOK /
WD_OFF
WD Refresh OK /
WD Refresh NOK /
WD_OFF
WD Refresh NOK /
WD_OFF
WD Refresh OK /
WD Refresh NOK /
WD_OFF
WD Refresh NOK /
WD_OFF
WD Refresh OK /
WD Refresh NOK /
WD_OFF
Figure 15. Watchdog refresh counter configuration (INIT_WD register, WD_CNT_refresh_1:0)
Table 10. Watchdog error table
WINDOW
SPI
CLOSED
OPEN
BAD Key
WD_NOK
WD_NOK
GOOD Key
WD_NOK
WD_OK
None (time out)
No_issue
WD_NOK
Any access to the watchdog register during the “closed” watchdog window is considered as a wrong watchdog refresh. Watchdog timeout,
meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh.
FS6407/FS6408
36
NXP Semiconductors
6.5.3
Reset error counter
The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is
incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage,
overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated.
The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from
reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from
reset and fail to deep reset and fail (Deep Fail-safe mode), where regulators are off, RSTB and FS0B are activated, and a power on reset
or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the
RSTB_err_FS bit in the INIT FSSM2 register (Table 70).
If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”.
If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”.
This configuration must be done during INIT FS phase.
The final value of the reset error counter is based on the intermediate configuration.
• RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 16). When reset error counter reaches 6, the device goes into deep reset and
fails.
• RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 17). When reset error counter reaches 2, the device goes into deep reset and
fails.
In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails.
Conditions leading to an increment of the RSTB error counter, and according to the product configuration are:
• Watchdog error counter = 6
• Watchdog refresh NOK during INIT phase or Watchdog timeout
• IO_23 error detection (FCCU)
• Undervoltage
• Overvoltage
• IO_1 FB_Core Delta
• FS0B shorted to VDD
• SPI DED
• Reset request by the SPI
• External reset
Conditions leading to a transition go to FS, according to the product configuration are:
• IO_01/IO_23/IO_45 error detection
• Undervoltage
• Overvoltage
• IO_1 FB_Core Delta
• Analog BIST fail
• SPI DED
• RSTB shorted to high
FS6407/FS6408
NXP Semiconductors
37
Reset Error Counter
(Cfg SPI RSTb_err_FS=0; WD_CNT_refresh=6)
7 consecutive WD Refresh OK
POR or from
LPOFF mode
gotoFS
INCR
7 consecutive WD Refresh OK
INCR
7 consecutive WD Refresh OK
INCR
7 consecutive WD Refresh OK
1
INCR = WD error counter = WD_CNT_error[1:0] |
WD refresh NOK during INIT |
IO23_ERR |UV/OV |
IO_1 FB_Core delta |
FS0b_shorttovdd |
SPI DED |
Reset by SPI |
External reset
gotoFS = IO01/23/45_ERR |
UV/OV|
IO_1 FB_Core delta |
ABIST_fail |
SPI DED |
RSTb_short2hi
(7 = WD_CNT_refresh + 1)
0
gotoFS
2
3
Active FS0
INCR
7 consecutive WD Refresh OK
4
Active FS0
INCR
7 consecutive WD Refresh OK
5
Active FS0
INCR
Active FS0
Turn OFF regulators
6
RSTb asserted for 8
seconds
Figure 16. RSTB error counter (RSTB_err_FS = 0)
Reset Error Counter
(Cfg SPI RSTb_err_FS=1; WD_CNT_refresh=6)
INCR = WD error counter = WD_CNT_error[1:0] |
WD refresh NOK during INIT |
IO23_ERR |UV/OV |
IO_1 FB_Core delta |
FS0b_shorttovdd |
SPI DED |
Reset by SPI |
External reset
7 consecutive WD Refresh OK
POR or from
LPOFF mode
INCR/gotoFS
Active FS0
gotoFS = IO01/23/45_ERR |
UV/OV |
IO_1 FB_Core delta |
ABIST_fail |
SPI DED |
RSTb_short2hi
(7 = WD_CNT_refresh + 1)
0
7 consecutive WD Refresh OK
1
INCR
Active FS0
Turn OFF regulators
2
RSTb asserted for 8
seconds
Figure 17. RSTB error counter(RSTB_err_FS = 1)
FS6407/FS6408
38
NXP Semiconductors
6.5.3.1
RST error counter at start-up or resuming from LPOFF mode
At start-up or when resuming from LPOFF mode the reset error counter starts at level 1 and FS0B is asserted low. To remove the
activation of FS0B, the RST error counter must go back to value “0” (seven consecutive good watchdog refresh decreases the reset error
counter down to 0) and a right command is sent to FS_OUT register (Figure 20).
1st WD refresh OK after
INIT phase. Start of the
WD window
New fully OPEN window of
256 ms
WD window
OK
WD error
counter
NOK
0
NOK
3
4
2
NOK
OK
Reset error
counter
OK
NOK
6
4
5
1
RSTb
delay time
RSTB
WD Refresh
counter
0
1
0
0
0
1
1
0
Figure 18. Example of WD operation generating a reset (WD_error_cnt = 6)
New fully OPEN window of
256 ms
WD window
OK
NOK
WD error
counter
4
Reset error
counter
1
RSTb
WD Refresh
counter
OK
OK
OK
OK
OK
OK
OK
0
6
2
1
RSTb
delay time
0
1
2
3
4
5
6
0
1
Figure 19. Example of WD operation leading a decrement of the reset error counter (WD_resfresh_cnt = 6)
FS6407/FS6408
NXP Semiconductors
39
# WD refresh counter max value +1
consecutive WD answers OK
FS_OUT
write OK
Reset error counter
RST_ERR_CNT
1
# WD refresh counter max value +1
consecutive WD answers OK
0
1
RSTb
FS0b
WD error counter
=6
WD error counter
=6
WD error counter
=6
2
FS_OUT
write OK
3
2
1
0
Reset delay
Output stage ON
OFF
ON
OFF
Figure 20. Reset error counter and FS0B deactivation sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6)
6.5.4
Fail-safe output (FS0B) deactivation
When the fail-safe output FS0B is asserted low by the device due to a fault, some conditions must be validated before allowing the FS0B
pin to be deactivated by the device. These conditions are:
• Fault is removed
• Reset error counter must be at “0”
• FS_OUT register must be filled with the right value.
6.5.4.1
Faults triggering FS0B activation
The activation of the FS0B is clearly dependent on the product configuration, but the following items can be settled:
• IO_01/IO_23/IO_45 error detection
• Undervoltage
• Overvoltage
• IO_1 FB_Core Delta
• Analog BIST fail (not configurable)
• SPI DED (not configurable)
• RSTB shorted to high (not configurable)
• RSTB error counter level
6.5.5
SPI DED
Some SPI registers affect some safety critical aspects of the fail-safe functions, and thus are required to be protected against SEU (Single
Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open.
Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content.
At this stage, if there is 1 single bit flip, the detection is made due to hamming code, and the error is corrected automatically (fully
transparent for the user), and a flag is sent. If there are two errors (DED - Dual Error Detection), the detection is made due to hamming
code but detected errors cannot be corrected. The flag is sent, RSTB and FS0B are activated.
6.5.6
FS_OUT register
When the fault is removed and the reset error counter changes back to level “0”, a right word must be filled in the FS_OUT register. The
value is dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied.
WD_LFSR_7:0=
b7
b6
b5
b4
b3
b2
b1
b0
FS_OUT_7:0 =
b0
b1
b2
b3
b4
b5
b6
b7
Figure 21. FS_OUT register based on LFSR value
FS6407/FS6408
40
NXP Semiconductors
6.6
Input voltage range
Due to the flexibility of the pre-regulator, the device can cover a wide battery input voltage range. However, a more standard voltage range
can still be covered using only the Buck configuration.
VSUP
Buck-Boost
Buck only
No operation
Risk of damage
No operation
Risk of damage
40 V
Extended voltage range
Extended voltage range
Potential VPRE thermal limitation
Potential VPRE thermal limitation
Normal voltage range
Normal voltage range
36 V
VSUP_UV_7
Extended voltage range
6.0 V
Extended voltage range
VPRE output current limitation
4.6 V
VPRE output current limitation
2.7 V
No operation
No operation
Figure 22. Input voltage range
• Thermal dissipation must be checked based on application use case to maintain junction temperature (TJ) 6.0 V.
For VCCA and VAUX 5.0 V configuration, undervoltage triggers at low VSUP (refer to VCCA_UV_5 and VAUX_UV_5).
6.7
Power management operation
A thermal sensor is implemented as close as possible to the pass transistor of each regulator (VPRE, VCORE, VCCA, VCAN) and an
associated individual thermal shutdown (TSD) protect these regulators independently. When the TSD threshold of a specific regulator is
reached, this regulator only is switched OFF and the information is reported in the main state machine. The regulator restarts automatically
when the junction temperature of the pass transistor decrease below the TSD threshold.
FS6407/FS6408
NXP Semiconductors
41
6.7.1
VPRE voltage pre-regulator
A highly flexible SMPS pre-regulator is implemented in the FS6407/FS6408. Depending on the input voltage requirement, the device can
be configured as “non-inverting buck-boost converter” (Figure 24) or “standard buck converter” (Figure 23). An external logic level
MOSFET (N-type) is required to operate in “non-inverting buck-boost converter”. The connection of the external MOSFET is detected
automatically during the start-up phase.
The converter operates in Current Control mode in any configuration. The high-side switching MOSFET is integrated to make the current
control easier. The PWM frequency is fixed at 440 kHz typical. The compensation network is fully integrated. VPRE output voltage is
regulated between 6.0 V and 7.0 V.
If the full current capability is not used for VCORE, VCCA, VAUX and CAN_5V, additional external LDO can be connected to VPRE to
fulfill application needs while the current load remains below the maximum current capability in all conditions.
PGND
PGND
PGND
Cout_Vpre4
ESR cap.
IPRE_LIM)
Reset condition
Description
TWARN_PRE
Report a thermal warning from VPRE
0
No thermal warning (TJ < TWARN_PRE)
1
Thermal warning (TJ > TWARN_PRE)
Reset condition
Description
BoB
Power On Reset / Read
Report a running mode of VPRE
0
Buck
1
Boost
Reset condition
Description
VPRE_STATE
Power On Reset / Read
Power On Reset
Report the activation state of VPRE SMPS
0
SMPS OFF
1
SMPS ON
Reset condition
Power On Reset
7.3.11 Status VREG2
Table 37. STATUS VREG2 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
Vpre_ Vcore_ Vother Ilim_co Twarn_ Vcore_ Twarn_ Ilim_cc Ilim_au Ilim_ca
G
G
s_G
re
core
state
cca
a
x
n
0
Table 38. Status VREG2. Description and configuration of the bits (default value in bold)
ILIM_CORE
Description
Report a current limitation condition on VCORE
0
No current limitation (ICORE_PK < ICORE_LIM)
1
Current limitation (ICORE_PK > ICORE_LIM)
Reset condition
Description
TWARN_CORE
Report a thermal warning from VCORE
0
No thermal warning (TJ < TWARN_CORE)
1
Thermal warning (TJ > TWARN_CORE)
Reset condition
Description
VCORE_STATE
Power On Reset / Read
Power On Reset / Read
Report the activation state of VCORE SMPS
0
SMPS OFF
1
SMPS ON
Reset condition
Power On Reset
FS6407/FS6408
NXP Semiconductors
75
Table 38. Status VREG2. Description and configuration of the bits (default value in bold)(continued)
Description
TWARN_CCA
Report a thermal warning from VCCA. Available only for internal pass MOSFET
0
No thermal warning (TJ < TWARN_CCA)
1
Thermal warning (TJ > TWARN_CCA)
Reset condition
Description
ILIM_CCA
Report a current limitation condition on VCCA
0
No current limitation (ICCA < ICCA_LIM)
1
Current limitation (ICCA > ICCA_LIM)
Reset condition
Description
ILIM_AUX
Power On Reset / Read
Report a current limitation condition on VAUX
0
No current limitation (IAUX < IAUX_LIM)
1
Current limitation (IAUX > IAUX_LIM)
Reset condition
Description
ILIM_CAN
Power On Reset
Power On Reset / Read
Report a current limitation condition on VCAN
0
No current limitation (ICAN < ICAN_LIM)
1
Current limitation (ICAN > ICAN _LIM)
Reset condition
Power On Reset / Read
7.3.12 Diag VREG1
Table 39. DIAG VREG1 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
Vpre_ Vcore_ Vother Vsns_u Vsup_u Tsd_pr
G
G
s_G
v
v_7
e
Vpre_ Vpre_u Tsd_co Vcore_ Vcore_
OV
v
re
FB_OV FB_uv
Table 40. Diag VREG1. Description and configuration of the bits (default value in bold)
Description
VSNS_UV
0
VBAT > VSNS_UV
1
VBAT < VSNS_UV
Reset condition
Description
VSUP_UV_7
Power On Reset / Read
Detection of VSUP below VSUP_UV_7
0
VSUP > VSUP_UV_7
1
VSUP < VSUP_UV_7
Reset condition
Description
TSD_PRE
Detection of VBATTERY below VSNS_UV
Power On Reset / Read
Thermal shutdown of VPRE
0
No TSD (TJ < TSD_PRE)
1
TSD occurred (TJ > TSD_PRE)
Reset condition
Power On Reset / Read
FS6407/FS6408
76
NXP Semiconductors
Table 40. Diag VREG1. Description and configuration of the bits (default value in bold) (continued)
Description
VPRE_OV
VPRE overvoltage detection
0
No overvoltage (VPRE < VPRE_OV)
1
Overvoltage detected (VPRE > VPRE_OV)
Reset condition
Description
VPRE_UV
VPRE undervoltage detection
0
No undervoltage (VPRE > VPRE_UV)
1
Undervoltage detected (VPRE < VPRE_UV)
Reset condition
Description
TSD_CORE
0
No TSD (TJ< TSD_CORE)
1
TSD occurred (TJ > TSD_CORE)
Description
Power On Reset / Read
VCORE overvoltage detection
0
No overvoltage (VCORE_FB < VCORE_FB_OV)
1
Overvoltage detected (VCORE_FB > VCORE_FB_OV)
Reset condition
Description
VCORE_FB_UV
Power On Reset / Read
Thermal shutdown of VCORE
Reset condition
VCORE_FB_OV
Power On Reset
Power On Reset / Read
VCORE undervoltage detection
0
No undervoltage (VCORE_FB > VCORE_FB_UV)
1
Undervoltage (VCORE_FB < VCORE_FB_UV)
Reset condition
Power On Reset / Read
7.3.13 Diag VREG2
Table 41. DIAG VREG2 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_
Reserved
G
IO_G
Vpre_ Vcore_ Vother Tsd_C
G
G
s_G
an
Vcan_ Vcan_u
OV
v
0
Tsd_au Ilim_au Vaux_ Vaux_u
x
x_off
OV
v
Table 42. Diag VREG2. Description and configuration of the bits (default value in bold)
Description
TSD_CAN
0
NO TSD (TJ < TSD_CAN)
1
TSD occurred (TJ > TSD_CAN)
Reset condition
Description
VCAN_OV
Thermal shutdown of VCAN
Power On Reset / Read
VCAN Overvoltage detection
0
No Overvoltage (VCAN < VCAN_OV)
1
Overvoltage detected (VCAN > VCAN_OV)
Reset condition
Power On Reset / Read
FS6407/FS6408
NXP Semiconductors
77
Table 42. Diag VREG2. Description and configuration of the bits (default value in bold) (continued)
Description
VCAN_UV
VCAN undervoltage detection
0
No undervoltage (VCAN > VCAN_UV)
1
Undervoltage detected (VCAN < VCAN_UV)
Reset condition
Description
TSD_AUX
Thermal shutdown of VAUX
0
No TSD (TJ < TSD_AUX)
1
TSD occurred (TJ > TSD_AUX)
Reset condition
Description
ILIM_AUX_OFF
0
T_LIMITATION < TAUX_LIM_OFF
1
T_LIMITATION >TAUX_LIM_OFF
Description
Power On Reset / Read
VAUX overvoltage detection
0
No overvoltage (VAUX < VAUX_OV)
1
Overvoltage detected (VAUX > VAUX_OV)
Reset condition
Description
VAUX_UV
Power On Reset
Maximum current limitation duration
Reset condition
VAUX_OV
Power On Reset / Read
Power On Reset / Read
VAUX undervoltage detection
0
No undervoltage (VAUX > VAUX_UV)
1
Undervoltage detected (VAUX < VAUX_UV)
Reset condition
Power On Reset / Read
7.3.14 Diag VREG3
Table 43. DIAG VREG3 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
0
Ilimcca_off
0
Vcca_
OV
0
Vcca_
UV
0
CAN_
Reserved
G
IO_G
Vpre_ Vcore_ Vother Tsd_cc
G
G
s_G
a
Table 44. Diag VREG3. Description and configuration of the bits (default value in bold)
Description
TSD_CCA
0
NO TSD (TJ < TSD_CCA)
1
TSD occurred (TJ > TSD_CCA)
Reset condition
Description
ILIM_CCA_OFF
Thermal shutdown of VCCA
Power On Reset / Read
Maximum current limitation duration. Available only when an external PNP is connected
0
T_LIMITATION < TCCA_LIM_OFF
1
T_LIMITATION >TCCA_LIM_OFF
Reset condition
Power On Reset / Read
FS6407/FS6408
78
NXP Semiconductors
Table 44. Diag VREG3. Description and configuration of the bits (default value in bold) (continued)
Description
VCCA_OV
VCCA overvoltage detection
0
No overvoltage (VCCA < VCCA_OV)
1
Overvoltage detected (VCCA > VCCA_OV)
Reset condition
Description
VCCA_UV
Power On Reset / Read
VCCA undervoltage detection
0
No undervoltage (VCCA > VCCA_UV)
1
Undervoltage detected (VCCA < VCCA_UV)
Reset condition
Power On Reset
7.3.15 Diag CAN1
Table 45. DIAG CAN1 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
CAN_d
Vpre_ Vcore_ Vother CANH_ CANH_ CANL_ CANL_
ominan
G
G
s_G
batt
gnd
batt
gnd
t
0
RXD_r TXD_d
ecessiv ominan
e
t
Table 46. Diag CAN1. Description and configuration of the bits (default value in bold)
Description
CANH_batt
0
No failure
1
Failure detected
Reset condition
Description
CANH_gnd
1
Failure detected
Power On Reset / Read
CANL short-circuit to battery detection
0
No failure
1
Failure detected
Reset condition
Description
Power On Reset / Read
CANL short-circuit to GND detection
0
No failure
1
Failure detected
Reset condition
Description
CAN_dominant
CANH short-circuit to GND detection
No failure
Description
CANL_gnd
Power On Reset / Read
0
Reset condition
CANL_batt
CANH short-circuit to battery detection
Power On Reset / Read
CAN Bus dominant clamping detection
0
No failure
1
Failure detected
Reset condition
Power On Reset / Read
FS6407/FS6408
NXP Semiconductors
79
Table 46. Diag CAN1. Description and configuration of the bits (default value in bold) (continued)
Description
RXD_recessive
RXD recessive clamping detection (short-circuit to 5.0 V)
0
No failure
1
Failure detected
Reset condition
Description
TXD_dominant
Power On Reset / Read
TXD dominant clamping detection (short-circuit to GND)
0
No failure
1
Failure detected
Reset condition
Power On Reset / Read
7.3.16 Diag CAN
Table 47. DIAG CAN register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
Vcore_ Vothers Reserv Reserv
G
_G
ed
ed
0
Reserv Reserv
ed
ed
0
CAN_O CAN_O
T
C
Table 48. Diag CAN. Description and configuration of the bits (default value in bold)
Description
CAN_OT
CAN overtemperature detection
0
No failure
1
Failure detected
Reset condition
Description
CAN_OC
Power On Reset / Read
CAN overcurrent detection
0
No failure
1
Failure detected
Reset condition
Power On Reset / Read
7.3.17 Diag SPI
Table 49. DIAG SPI register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
0
SPI_clk
0
SPI_re
q
0
SPI_pa
rity
0
Vcore_ Vothers
SPI_err
G
_G
FS6407/FS6408
80
NXP Semiconductors
Table 50. Diag SPI. Description and configuration of the bits (default value in blue)
Description
SPI_err
Secured SPI communication check
0
No error
1
Error detected in the secured bits
Reset condition
Description
SPI_CLK
SCLK error detection
0
16 clock cycles during NCS low
1
Wrong number of clock cycles ( 16)
Reset condition
Description
SPI_req
Power On Reset / Read
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address)
0
No error
1
SPI violation
Reset condition
Description
SPI_parity
Power On Reset / Read
Power On Reset / Read
SPI parity bit error detection
0
Parity bit OK
1
Parity bit error
Reset condition
Power On Reset / Read
7.3.18 Mode
Table 51. MODE register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
MOSI
1
0
1
0
1
0
1
P
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
MOSI
0
0
1
0
1
0
1
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit4
bit3
bit2
bit1
bit0
Goto_L INT_re Secure Secure Secure Secure
POFF quest
_3
_2
_1
_0
Vcore_ Vothers Reserv Reserv Reserv Reserv
G
_G
ed
ed
ed
ed
Reserv Reserv
ed
ed
INIT
Normal
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
Read
Vcore_ Vothers Reserv Reserv Reserv Reserv
G
_G
ed
ed
ed
ed
INIT
Normal
Reserv Reserv
ed
ed
FS6407/FS6408
NXP Semiconductors
81
Table 52. MODE. Description and configuration of the bits (default value in bold)
Configure the device in Low Power mode VREG OFF (LPOFF)
Description
Goto_LPOFF
0
No action
1
LPOFF mode
Reset condition
Description
INIT
Report if INIT mode of the main logic state machine is entered
0
Not in INIT mode
1
INIT MODE
Reset condition
Description
Normal
Power On Reset
Report if Normal mode of the main logic state machine is entered
0
Not in Normal mode
1
Normal mode
Reset condition
Description
INT_request
Power On Reset
Power On Reset
Request for an INT pulse
0
No Request
1
Request for an INT pulse
Reset condition
Description
Power On Reset
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure 3:0
7.3.19 Vreg mode
Table 53. VREG MODE register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
MOSI
1
0
1
0
1
1
0
P
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
Vpre_ Vcore_ Vother Reserv Reserv Reserv Reserv Vcore_ Vcca_
G
G
s_G
ed
ed
ed
ed
EN
EN
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
MOSI
0
0
1
0
1
1
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
Vcore_ Vcca_
EN
EN
bit5
Vaux_
EN
bit4
bit3
bit2
bit1
bit0
Vcan_ Secure Secure Secure Secure
EN
_3
_2
_1
_0
Vaux_
EN
Vcan_
EN
bit2
bit1
bit0
0
0
0
Vaux_
EN
Vcan_
EN
Read
Vpre_ Vcore_ Vother Reserv Reserv Reserv Reserv Vcore_ Vcca_
G
G
s_G
ed
ed
ed
ed
EN
EN
FS6407/FS6408
82
NXP Semiconductors
Table 54. VREG MODE. Description and configuration of the bits (default value in bold)
Description
VCORE_EN
VCORE control (Switch OFF NOT recommended if VCORE is SAFETY critical)
0
DISABLED
1
ENABLED
Reset condition
Description
VCCA_EN
VCCA control (Switch OFF NOT recommended if VCCA is SAFETY critical)
0
DISABLED
1
ENABLED
Reset condition
Description
VAUX_EN
Power On Reset
VAUX control (Switch OFF NOT recommended if VAUX is SAFETY critical)
0
DISABLED
1
ENABLED
Reset condition
Description
VCAN_EN
Power On Reset
Power On Reset
VCAN control
0
DISABLED
1
ENABLED
Reset condition
Description
Power On Reset
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure 3:0
7.3.20 IO_OUT-AMUX
Table 55. IO_OUT-AMUX register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
MOSI
1
0
1
0
1
1
1
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
IO_out IO_out IO_out IO_out
_4_EN
_4
_5_EN
_5
bit3
0
bit2
bit1
bit0
Amux_ Amux_ Amux_
2
1
0
Vcore_ Vothers IO_out IO_oou IO_out IO_out Reserv Amux_ Amux_ Amux_
G
_G
_4_EN
t_4
_5_EN
_5
ed
2
1
0
Read
Vcore_ Vothers IO_out IO_out IO_out IO_out Reserv Amux_ Amux_ Amux_
G
_G
_4_EN
_4
_5_EN
_5
ed
2
1
0
FS6407/FS6408
NXP Semiconductors
83
Table 56. IO_OUT-AMUX. Description and configuration of the bits (default value in bold)
Description
IO_out_4_EN
Enable the output gate driver capability for IO_4
0
High-impedance (IO_4 configured as input)
1
ENABLED (IO_4 configured as output gate driver)
Reset condition
Description
IO_out_4
Configure IO_4 output gate driver state
0
LOW
1
HIGH
Reset condition
Description
IO_out_5_EN
0
High-impedance (IO_5 configured as input)
1
ENABLED (IO_5 configured as output gate driver)
Description
Power On Reset
Configure IO_5 output gate driver state
0
LOW
1
HIGH
Reset condition
Description
AMUX_2:0
Power On Reset
Enable the output gate driver capability for IO_5
Reset condition
IO_out_5
Power On Reset
Power On Reset
Select AMUX output
000
Vref
111
Die Temperature Sensor
Reset condition
Power On Reset
7.3.21 CAN mode
Table 57. CAN MODE register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
MOSI
1
0
1
1
0
0
0
P
MISO
SPI_G
WU
CAN_
Reserved
G
IO_G
CAN_ CAN_
Vpre_ Vcore_ Vother
CAN_a Reserv Reserv Reserv CAN_w Reserv
mode_ mode_
G
G
s_G
uto_dis
ed
ed
ed
u
ed
1
0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_ CAN_
CAN_a
mode_ mode_
uto_dis
1
0
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
Read
CAN_
Reserved
G
IO_G
CAN_ CAN_
Vpre_ Vcore_ Vother
CAN_a Reserv Reserv Reserv CAN_w Reserv
mode_ mode_
G
G
s_G
uto_dis
ed
ed
ed
u
ed
1
0
FS6407/FS6408
84
NXP Semiconductors
Table 58. CAN MODE. Description and configuration of the bits (default value in bold)
Description
CAN_mode_1:0
Configure the CAN mode
00
Sleep / NO wake-up capability
01
LISTEN ONLY
10
Sleep / Wake-up capability
11
Normal operation mode
Reset condition
Description
CAN_auto_dis
Automatic CAN Tx disable
0
NO auto disable
1
Reset CAN_mode from “11” to “01” on CAN over temp or TXD dominant or RXD recessive event
Reset condition
Description
CAN_wu
Power On Reset
Power On Reset
Report a wake-up event from the CAN
0
No wake-up
1
Wake-up detected
Reset condition
Power On Reset / Read
Notes
22. CAN mode is automatically configured to “sleep + wake-up capability[10]” if CAN mode was different than “sleep + no wake-up capability [00]”
before the device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored.
7.3.22 Can_Mode_2
Table 59. CAN_MODE_2 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
MOSI
1
0
1
1
0
0
1
P
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
0
0
0
0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
0
0
0
0
Vcore_ Vothers
G
_G
bit4
bit3
bit2
bit1
bit0
Vcan_
secure secure secure secure
OV_Mo
_3
_2
_1
_0
n
Vcan_
Reserv Reserv Reserv
OV_Mo
ed
ed
ed
n
Read
Vcore_ Vothers
G
_G
Vcan_
Reserv Reserv Reserv
OV_Mo
ed
ed
ed
n
FS6407/FS6408
NXP Semiconductors
85
Table 60. CAN_MODE_2. Description and configuration of the bits (default value in bold)
Description
Vcan_OV_Mon
VCAN OV Monitoring
0
OFF. VCAN OV is not monitored. Flag is ignored
1
ON. VCAN OV flag is under monitoring. In case of OV the VCAN regulator is switched OFF.
Reset condition
Description
Power On Reset
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure 3:0
7.3.23 INIT SUPERVISOR1
Table 61. INIT SUPERVISOR1 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
1
1
0
0
0
0
1
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
Vcore_ Vcore_ Vcca_F Vcca_F secure Secure Secure Secure
FS1
FS_0
S_1
S_0
_3
_2
_1
_0
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F
G
_G
_err
_CLK
_Req _Parity FS1
FS_0
S_1
S_0
Read
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F
G
_G
_err
_CLK
_Req _Parity FS1
FS_0
S_1
S_0
Table 62. INIT SUPERVISOR1. Description and configuration of the bits (default value in bold)
Description
Vcore_FS1:0
00
No effect of VCORE_FB_OV and VCORE_FB_UV on RSTb and FSxx
01
VCORE_FB_OV DOES HAVE an impact on RSTb and FSxx. VCORE_FB_UV DOES HAVE an impact on RSTb
only
10
VCORE_FB_OV DOES HAVE an impact on RSTb and FSxx. No effect of VCORE_FB_UV on RSTb and FSxx
11
Both VCORE_FB_OV and VCORE_FB_UV DO HAVE an impact on RSTb and FSxx
Reset condition
Description
Vcca_FS1:0
VCORE safety input.
Power On Reset
VCCA safety input.
00
No effect of VCCA_OV and VCCA_UV on RSTb and FSxx
01
VCCA_OV DOES HAVE an impact on RSTb and FSxx. VCCA_UV DOES HAVE an impact on RSTb only
10
VCCA_OV DOES HAVE an impact on RSTb and FSxx. No effect of VCCA_UV on RSTb and FSxx
11
Both VCCA_OV and VCCA_UV DO HAVE an impact on RSTb and FSxx
Reset condition
Power On Reset
FS6407/FS6408
86
NXP Semiconductors
Table 62. INIT SUPERVISOR1. Description and configuration of the bits (default value in bold) (continued)
Description
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure3:0
Description
SPI_FS_err
Secured SPI communication check, concerns Fail-safe logic only
0
No error
1
Error detected in the secured bits
Reset condition
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit
Description
SPI_FS_CLK
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Power On Reset
Invalid SPI access (Wrong Write or Read, Write to INIT registers in Normal mode, wrong address), concerns
fail-safe logic only.
Description
SPI_FS_Req
Power On Reset
0
No error
1
SPI violation
Reset condition
Description
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
SPI_FS_Parity
7.3.24 INIT SUPERVISOR2
Table 63. INIT SUPERVISOR2 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
MOSI
1
1
0
0
0
1
0
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
MOSI
0
1
0
0
0
1
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
Vaux_F Vaux_F
S1
S_0
bit5
bit4
0
DIS_8s
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS
G
_G
_err
_CLK
_req _Parity
bit3
bit2
bit1
bit0
Secure Secure Secure Secure
_3
_2
_1
_0
Vaux_F Vaux_F
S1
S_0
0
DIS_8s
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
0
DIS_8s
Read
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS
G
_G
_err
_CLK
_req _Parity
Vaux_F Vaux_F
S1
S_0
FS6407/FS6408
NXP Semiconductors
87
Table 64. INIT SUPERVISOR2. Description and configuration of the bits (default value in bold)
Description
Vaux_FS1:0
00
No effect of VAUX_OV and VAUX_UV on RSTb and FSxx
01
VAUX_OV DOES HAVE an impact on RSTb and FSxx. VAUX_UV DOES HAVE an impact on RSTb only
10
VAUX_OV DOES HAVE an impact on RSTb and FSxx. No effect of VAUX_UV on RSTb and FSxx
11
Both VAUX_OV and VAUX_UV DO HAVE an impact on RSTb and FSxx
Reset condition
Description
DIS_8s
1
DISABLED
Description
Secured bits based on write bits
Secured SPI communication check, concerns fail-safe logic only.
0
No error
1
Error detected in the secured bits
Reset condition
Description
Power On Reset
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by SPI_CLK_ bit
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Description
Power On Reset
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns
fail-safe Logic only
0
No error
1
SPI violation
Reset condition
Description
SPI_FS_Parity
Power On Reset
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure3:0
SPI_FS_Req
Disable the 8.0 s timer used to enter Deep Fail-safe mode
ENABLED
Description
SPI_FS_CLK
Power On Reset
0
Reset condition
SPI_FS_err
VAUX safety input.
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
FS6407/FS6408
88
NXP Semiconductors
7.3.25 INIT SUPERVISOR3
Table 65. INIT SUPERVISOR3 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
MOSI
1
1
0
0
0
1
1
P
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
Vcca_5 Vaux_5
D
D
bit4
0
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS
G
_G
_err
_CLK
_req _Parity
bit3
bit2
bit1
bit0
Secure Secure Secure Secure
_3
_2
_1
_0
0
Reserv Vcca_5 Vaux_5
ed
D
D
Read
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS
G
_G
_err
_CLK
_req _Parity
0
Reserv Vcca_5 Vaux_5
ed
D
D
Table 66. INIT SUPERVISOR3. Description and configuration of the bits (default value in bold)
Description
VCCA_5D
0
Normal 5.0 V undervoltage detection threshold (VCCA_UV_5)
1
Degraded mode, i.e lower undervoltage detection threshold applied (VCCA_UV_D)
Reset condition
Description
VAUX_5D
Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V
Normal 5.0 V undervoltage detection threshold (VAUX_UV_5)
1
Degraded mode, i.e lower undervoltage detection threshold applied (VAUX_UV_5D)
Description
Power On Reset
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2= NOT(bit4)
Secured_1=bit7
Secured_0=bit6
Secure3:0
Description
Secured SPI communication check, concerns fail-safe logic only
0
No error
1
Error detected in the secured bits
Reset condition
Description
SPI_FS_CLK
Power On Reset
0
Reset condition
SPI_FS_err
Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V
Power On Reset
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Power On Reset
FS6407/FS6408
NXP Semiconductors
89
Table 66. INIT SUPERVISOR3. Description and configuration of the bits (default value in bold) (continued)
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns
fail-safe logic only
Description
SPI_FS_Req
0
No error
1
SPI violation
Reset condition
Description
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
SPI_FS_Parity
7.3.26 Init FSSM1
Table 67. INIT FSSM1 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
1
1
0
0
1
0
0
P
MISO
SPI_G
WU
CAN_
Reserved
G
IO_G
Vpre_ Vcore_ Vother
G
G
s_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
IO_01_ IO_1_F IO_45_ RSTb_l Secure Secure Secure Secure
FS
S
FS
ow
_3
_2
_1
_0
SPI_F
SPI_F SPI_F SPI_F
IO_01_ IO_1_F IO_45_ RSTb_l
S_Parit
S_err S_CLK S_req
FS
S
FS
ow
y
Read
CAN_
Reserved
G
IO_G
Vpre_ Vcore_ Vother
G
G
s_G
SPI_F
SPI_F SPI_F SPI_F
IO_01_ IO_1_F IO_45_ RSTb_l
S_Parit
S_err S_CLK S_req
FS
S
FS
ow
y
Table 68. INIT FSSM1. Description and configuration of the bits (default value in bold)
Description
IO_01_FS
0
NOT SAFETY
1
SAFETY CRITICAL
Reset condition
Description
IO_1_FS
Power On Reset
Configure IO_1 as safety inputs
0
NOT SAFETY
1
SAFETY CRITICAL (External resistor bridge monitoring active)
Reset condition
Description
IO_45_FS
Configure the couple of IO_1:0 as safety inputs
Power On Reset
Configure the couple of IO_5:4 as safety inputs
0
NOT SAFETY
1
SAFETY CRITICAL
Reset condition
Power On Reset
FS6407/FS6408
90
NXP Semiconductors
Table 68. INIT FSSM1. Description and configuration of the bits (default value in bold) (continued)
Description
RSTb_low
0
10 ms
1
1.0 ms
Reset condition
Description
Description
1
Error detected in the secured bits
Power On Reset
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Description
Power On Reset
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns
fail-safe logic only
0
No error
1
SPI violation
Reset condition
Description
SPI_FS_Parity
Secured SPI communication check, concerns fail-safe logic only
No error
Description
SPI_FS_Req
Secured bits based on write bits
0
Reset condition
SPI_FS_CLK
Power On Reset
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure3:0
SPI_FS_err
Configure the Rstb LOW duration time
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
FS6407/FS6408
NXP Semiconductors
91
7.3.27 Init FSSM2
Table 69. INIT FSSM2 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
MOSI
1
1
0
0
1
0
1
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
MOSI
0
1
0
0
1
0
1
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
RSTb_ IO_23_
err_FS
FS
bit5
bit4
PS
0
bit3
bit2
bit1
bit0
Secure Secure Secure Secure
_3
_2
_1
_0
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_
G
_G
_err
_CLK
_req _Parity err_FS
FS
PS
0
bit2
bit1
bit0
0
0
0
PS
0
Read
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_
G
_G
_err
_CLK
_req _Parity err_FS
FS
Table 70. INIT FSSM2. Description and configuration of the bits (default value in bold)
Description
IO_23_FS
0
NOT SAFETY
1
SAFETY CRITICAL
Reset condition
Description
RSTb_err_FS
Configure the values of the RSTb error counter
intermediate = 3; final = 6
1
intermediate = 1; final = 2
Description
Power On Reset
Configure the FCCU polarity
0
Fccu_eaout_1:0 active HIGH
1
Fccu_eaout_1:0 active LOW
Reset condition
Description
Power On Reset
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure3:0
Description
SPI_FS_err
Power On Reset
0
Reset condition
PS
Configure the couple of IO_3:2 as safety inputs for FCCU monitoring
Secured SPI communication check, concerns fail-safe logic only
0
No error
1
Error detected in the secured bits
Reset condition
Power On Reset
FS6407/FS6408
92
NXP Semiconductors
Table 70. INIT FSSM2. Description and configuration of the bits (default value in bold) (continued)
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by SPI_CLK_ bit
Description
SPI_FS_CLK
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns
fail-safe Logic only
Description
SPI_FS_Req
Power On Reset
0
No error
1
SPI violation
Reset condition
Description
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
SPI_FS_Parity
7.3.28 WD window
Table 71. WD WINDOW register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
1
1
0
0
1
1
0
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
WD_wi WD_wi WD_wi WD_wi Secure Secure Secure Secure
ndow3 ndow2 ndow1 ndow0
_3
_2
_1
_0
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi
G
_G
_err
_CLK
_req _Parity ndow3 ndow2 ndow1 ndow0
Read
Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi
G
_G
_err
_CLK
_req _Parity ndow3 ndow2 ndow1 ndow0
Any WRITE command to the WD_window in the Normal mode must be followed by a READ command to verify the correct change of the WD window
duration
FS6407/FS6408
NXP Semiconductors
93
Table 72. WD Window. Description and configuration of the bits (default value in bold)
Description
WD_Window_3:0
0000
DISABLE
0001
1.0 ms
0010
2.0 ms
0011
3.0 ms
0100
4.0 ms
0101
6.0 ms
0110
8.0 ms
0111
12 ms
1000
16 ms
1001
24 ms
1010
32 ms
1011
64 ms
1100
128 ms
1101
256 ms
1110
512 ms
1111
1024 ms
Reset condition
Description
Description
1
Error detected in the secured bits
Power On Reset
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by the SPI_CLK bit.
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Description
Power On Reset
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns
fail-safe logic only
0
No error
1
SPI violation
Reset condition
Description
SPI_FS_Parity
Secured SPI communication check, concerns fail-safe logic only
No error
Description
SPI_FS_Req
Secured bits based on write bits
0
Reset condition
SPI_FS_CLK
Power On Reset
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure3:0
SPI_FS_err
Configure the watchdog window duration. Duty cycle if set to 50%
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
FS6407/FS6408
94
NXP Semiconductors
7.3.29 WD_LFSR
Table 73. WD LFSR register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
1
1
0
0
1
1
1
P
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
Vpre_
G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_
G
Reserve
d
IO_G
Vpre_
G
WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF
SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Vcore_ Vother WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF
G
s_G
SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Read
Vcore_ Vother WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF
G
s_G
SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Table 74. WD LFSR. Description and configuration of the bits (default value in bold)
Description
WD 8 bits LFSR value. Used to write the seed at any time
0...
WD_LFSR_7:0
bit7:bit0: 10110010 default value at start-up or after a Power on reset: 0xB2 (23), (24)
1...
Reset condition
Power On Reset
Notes
23. Value Bit7:Bit0: 1111 1111 is prohibited.
24. During a write command, MISO reports the previous register content.
7.3.30 WD answer
Table 75. WD answer register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MOSI
1
1
0
1
0
0
0
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MOSI
0
1
0
1
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WD_an WD_an WD_an WD_an WD_an WD_an WD_an WD_an
swer_7 swer_6 swer_5 swer_4 swer_3 swer_2 swer_1 swer_0
Vcore_ Vothers
RSTb
G
_G
FS0
WD
FS0_G
IO_FS_
G
0
FS_EC FS_reg
C
_Ecc
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
0
0
0
FS0
WD
FS0_G
IO_FS_
G
0
Read
Vcore_ Vothers
RSTb
G
_G
FS_EC FS_reg
C
_Ecc
FS6407/FS6408
NXP Semiconductors
95
Table 76. WD answer. Description and configuration of the bits (default value in bold)
Description
WD_answer_7:0
0...
1...
Reset condition
Description
RSTb
FS0b
Reset occurred
Reset condition
Power On Reset / Read
Description
Report a fail-safe event
0
No fail-safe
1
Fail safe event occurred / Also default state at power-up after LPOFF as FS0b is asserted low
Report a watchdog refresh ERROR
WD refresh OK
1
WRONG WD refresh
Power On Reset / Read
Report a fail-safe output failure
0
No failure
1
Failure
Reset condition
Description
Power On Reset / Read
Report an IO monitoring error
0
No error
1
Error detected
Reset condition
Description
Power On Reset
Report an error code correction on fail-safe state machine
0
No ECC
1
ECC done
Reset condition
Description
FS_req_ECC
Power On Reset / Read
0
Description
FS_ECC
Report a reset event
1
Reset condition
IO_FS_G
Power On Reset / RSTb LOW
No Reset
Description
FS0_G
Answer = (NOT(((LFSR x 4)+6)-4))/4
0
Reset condition
WD
WD answer from the MCU
Power On Reset / Read
Report an error code correction on fail-safe registers
0
No ECC
1
ECC done
Reset condition
Power On Reset / Read
FS0_G = RSTB_short_high or FS0B_short_high or FS0B_short_low
IO_FS_G = IO_01_fail or IO_1_fail or IO_23_fail or IO_45_fail
Values of the three registers WD_answer, WD_counter, and DIAG_FS2 are updated at the end of any SPI access to one of these
registers. To always get up to date values, it is recommended to make two consecutive SPI accesses to these registers. Example: read
WD_answer, read again WD_answer, read WD_counter, read DIAG_FS2. The first read updates the three registers and the second read
report the latest information.
FS6407/FS6408
96
NXP Semiconductors
7.3.31 Fail-safe out (FS_out)
Table 77. Fail-safe out register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MOSI
1
1
0
1
0
0
1
P
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FS_out FS_out FS_out FS_out FS_out FS_out FS_out FS_out
_7
_6
_5
_4
_3
_2
_1
_0
Vcore_ Vothers
G
_G
0
0
0
0
0
0
0
0
bit3
bit2
bit1
bit0
Table 78. Fail-safe out. Description and configuration of the bits (default value in bold)
Description
Secured 8 bits word to release the FS0b
0...
FS_out_7:0
Depend on LFSR_out value and calculation
1...
Reset condition
Power On Reset -> Default = 00h
7.3.32 RSTB request
Table 79. RSTB request register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
MOSI
1
1
0
1
0
1
0
P
0
0
RSTb_r
equest
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
0
0
0
0
Vcore_ Vothers
G
_G
Secure Secure Secure Secure
_3
_2
_1
_0
0
0
0
0
Table 80. RSTB request. Description and configuration of the bits (Default value in bold)
Description
RSTb_request
0
No request
1
Request a RSTb low pulse
Reset condition
Description
Secure3:0
Request a RSTb low pulse
Power On Reset / When RSTb done
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
FS6407/FS6408
NXP Semiconductors
97
7.3.33 INIT_WD
Table 81. INIT WD register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MOSI
1
1
0
1
0
1
1
P
MISO
SPI_G
WU
CAN_ Reserve
G
d
IO_G
Vpre_
G
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
IO_G
Vpre_
G
Vcore_ Vother
G
s_G
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WD_C WD_C WD_C WD_C
secure secure secure secure
NT_err NT_err NT_refr NT_refr
3
2
1
0
or_1
or_0
esh_1 esh_0
SPI_F WD_C WD_C WD_C WD_C
SPI_F SPI_F SPI_F
S_Parit NT_err NT_err NT_refr NT_refr
S_err S_CLK S_Req
y
or_1
or_0
esh_1 esh_0
Read
CAN_ Reserve
G
d
Vcore_ Vother
G
s_G
SPI_F WD_C WD_C WD_C WD_C
SPI_F SPI_F SPI_F
S_Parit NT_err NT_err NT_refr NT_refr
S_err S_CLK S_Req
y
or_1
or_0
esh_1 esh_0
Table 82. INIT WD. Description and configuration of the bits (default value in bold)
Description
WD_CNT_error_1:0
00
6
01
6
10
4
11
2
Reset Condition
Description
WD_CNT_refresh_
1:0
Power On Reset
Configure the maximum value of the WD refresh counter
00
6
01
4
10
2
11
1
Reset Condition
Description
Power On Reset
Secured bits based on write bits
Secured_3 = NOT(bit5)
Secured_2 = NOT(bit4)
Secured_1 = bit7
Secured_0 = bit6
Secure3:0
Description
SPI_FS_err
Configure the maximum value of the WD error counter
Secured SPI communication check, concerns fail-safe logic only
0
No error
1
Error detected in the secured bits
Reset condition
Power On Reset
FS6407/FS6408
98
NXP Semiconductors
Table 82. INIT WD. Description and configuration of the bits (default value in bold) (continued)
SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both
main and fail-safe logics. Other errors flagged by the SPI_CLK bit.
Description
SPI_FS_CLK
0
16 clock cycles during NCS low
1
Wrong number of clock cycles (16)
Reset condition
Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns
fail-safe logic only
Description
SPI_FS_Req
Power On Reset
0
No error
1
SPI violation
Reset condition
Description
Power On Reset
SPI parity bit error detection, concerns fail-safe logic only
0
Parity bit OK
1
Parity bit ERROR
Reset condition
Power On Reset
SPI_FS_Parity
7.3.34 Diag FS1
Table 83. DIAG FS1 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
0
0
0
Vcore_ Vothers RSTb_ RSTb_
G
_G
ext
diag
0
FS0b_ FS0b_
diag_1 diag_0
Table 84. Diag FS1. Description and configuration of the bits (default value in bold)
Description
RSTb_diag
RSTb_ext
FS0b_diag_1:0
Report a RSTb short-circuit to HIGH
0
No Failure
1
Short-circuit HIGH
Reset condition
Power On Reset / Read
Description
Report an external RSTb
0
No external RSTb
1
External RSTb
Reset condition
Power On Reset / Read
Description
Report a failure on FS0b
00
No Failure
01
Short-circuit LOW / open load
1X
Short-circuit HIGH
Reset condition
Power On Reset / Read
FS6407/FS6408
NXP Semiconductors
99
7.3.35 WD counter
Table 85. WD counter register description
Read
bit15 bit14 bit13 bit12 bit11
MOSI
0
1
MISO
SPI_
G
WU
0
1
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
1
0
0
0
0
0
0
0
0
0
1
CAN_ Rese
Vpre_ Vcore_ Vothers_ WD_err WD_err WD_err
IO_G
G
rved
G
G
G
_2
_1
_0
WD_ref WD_refr WD_refr
resh_2 esh_1
esh_0
0
0
Table 86. WD counter. Description and configuration of the bits (default value in bold)
Description
Report the value of the watchdog error counter
000
WD_err_2:0
From 0 to 5 (6 generates a Reset and this counter is reset to 0)
to 110
Reset condition
Power On Reset
Description
Report the value of the watchdog refresh counter
000
WD_refresh_2:0
From 0 to 6 (7 generate a decrease of the RST_err_cnt and this counter is reset to 0)
to 111
Reset condition
Power On Reset
7.3.36 Diag FS2
Table 87. DIAG FS2 register description
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G
Reserv
ed
IO_G
Vpre_G
Vcore_ Vothers RSTb_ RSTb_ RSTb_
G
_G
err_2
err_1
err_0
0
IO_45_ IO_23_ IO_1_F IO_01_
fail
fail
ail
fail
Table 88. Diag FS2. Description and configuration of the bits (default value in bold)
Description
RSTb_err_2:0
000
001
…
110
Reset condition
Description
IO_45_fail
Report the value of the RSTb error counter
Error counter is set to 1 by default
Power On Reset
Report an error in the IO_45 protocol
0
No error
1
Error detected
Reset condition
Power On Reset / Read
FS6407/FS6408
100
NXP Semiconductors
Table 88. Diag FS2. Description and configuration of the bits (default value in bold) (continued)
Description
IO_23_fail
0
No error
1
Error detected
Reset condition
Description
IO_1_fail
Power On Reset / Read
Report an error in the IO_1 monitoring (external resistor string monitoring)
0
No error
1
Error detected
Reset condition
Description
IO_01_fail
Report an error in the FCCU protocol
Power On Reset
Report an error in the IO_01 protocol
0
No error
1
Error detected
Reset condition
Power On Reset / Read
FS6407/FS6408
NXP Semiconductors
101
8
List of interruptions and description
The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set
through the SPI during INIT phase. It is possible to mask some Interruption source (see Detail of register mapping).
Table 89. Interruptions list
Event
Description
VSNS_UV
Detection of VBATTERY below 8.5 V
VSUP_UV_7
Detection of VSUP below 7.0 V (after reverse current protection diode)
ILIM_PRE
Pre-regulator Current Limitation
TWARN_PRE
Temperature warning on the pass transistor
BoB
Return the running state of VPRE converter (Buck or Boost mode)
VPRE_STATE (VPRE_SMPS_EN)
Return the activation state of VPRE DC/DC converter
VPRE OV
Report a VPRE overvoltage detection
VPRE UV
Report a VPRE undervoltage detection
ILIM_CORE
VCORE Current limitation
TWARN_CORE
Temperature warning on the pass transistor
VCORE_STATE (VCORE_SMPS_EN)
Return the activation state of VCORE DC/DC converter
VCORE OV
Report a VCORE overvoltage detection
VCORE UV
Report a VCORE undervoltage detection
ILIM_CCA
VCCA Current limitation
TWARN_CCA
Temperature warning on the pass transistor (Internal Pass transistor only)
TSDVCCA
Temperature shutdown of the VCCA
ILIM_CCA_OFF
Current limitation maximum duration expiration. Only used when external PNP connected.
VCCA OV
Report a VCCA overvoltage detection
VCCA UV
Report a VCCA undervoltage detection
ILIM_AUX
VAUX Current limitation
ILIM_AUX_OFF
Current limitation maximum duration expiration. Only used when external PNP connected.
VAUX OV
Report a VAUX overvoltage detection
VAUX UV
Report a VAUX undervoltage detection
TSDVAUX
Temperature shutdown of the VAUX
ILIM_CAN
VCAN Current limitation
VCAN OV
Report a VCAN overvoltage detection
VCAN UV
Report a VCAN undervoltage detection
TSDCAN
Temperature shutdown on the pass transistor. Auto restart when TJ < (TSDCAN - TSDCAN_HYST).
IO_0
Report IO_0 digital state change
IO_1
Report IO_1 digital state change
IO_2
Report IO_2 digital state change
IO_3
Report IO_3 digital state change
IO_4
Report IO_4 digital state change
IO_5
Report IO_5 digital state change
IO_0_WU
Report IO_0 WU event
FS6407/FS6408
102
NXP Semiconductors
Table 89. Interruptions list (continued)
IO_1_WU
Report IO_1 WU event
IO_2_WU
Report IO_2 WU event
IO_3_WU
Report IO_3 WU event
IO_4_WU
Report IO_4 WU event
IO_5_WU
Report IO_5 WU event
CAN_WU
Report a CAN wake-up event
CAN_OT
CAN overtemperature detection
RXD_recessive
CAN RXD recessive clamping detection (short-circuit to 5.0 V)
TXD_dominant
CAN TXD dominant clamping detection (short circuit to GND)
CAN_dominant
CAN bus dominant clamping detection
INT_Request
MCU request for an Interrupt pulse
SPI_err
Secured SPI communication check
SPI_CLK
Report a wrong number of CLK pulse different than 16 during the NCS low pulse in Main state machine
SPI_Req
Invalid SPI access (Wrong write or read, write to INIT registers in normal mode, wrong address)
SPI_Parity
Report a Parity error in Main state machine
FS6407/FS6408
NXP Semiconductors
103
Typical applications
PGND
VAUX
5.1KΩ +/-5%
12KΩ +/-5%
24KΩ +/-5%
51KΩ +/-5%
GND
RSelect
Key on
Resistor must be
close to Select pin
GND
5.1 kΩ
R2(+/-5%)
39KΩ
18KΩ
C2
1nF
150pF
Cout
2*10µF
2*10µF
IO_2
FCCU monitoring
from Freescale
MCU
MOSI
MISO
SCLK
NCS
GND
0R
MUX_OUT
MCU inputs
GND
INTB
MCU Int.
VDDIO
5.1KΩ
GND
RSTB
Vaux (5V or 3.3V)
300mA capability +/-3% accuracy
IO_3
MCU RESET
VDDIO
or VSUP3
GND
FS0B
IO_5
MUX_OUT (output selected by SPI)
Vsense or
VIO_0 or
VIO_1 or
Internal 2.5V reference voltage (2.5V +/-1%)
5.1 kΩ
GND
CANH
CAN BUS
100nF
MCU SPI
IO_4
5.1 kΩ
4
GND
10 nF
Recommended
connection for IOs not
used in the application
C1
220pF
680pF
Vcca (5V or 3.3V), available configurations
Whithout Ext. PNP : 100mA capability +/-1% accuracy for 5V
configuration, +/-1.5% accuracy for 3.3V configuration,
With Ext. PNP : < 200mA +/-2% accuracy
With Ext. PNP : 300mA capability +/-3% accuracy
IO_1
Optional
R1(+/-5%)
200Ω
510Ω
(If connected to Vcore, must be
connected closed to coutx 10µF x 2)
SELECT
IO_0
From 2nd Vcore
resistor bridge
R4(+/-1%)
8.06KΩ
8.06KΩ
10 µF
GND
Connected to Vcca or Vcore
VDDIO
1 nF
Vbat
R3(+/-1%)
4.32KΩ
24.9KΩ
EMI sup. Capacitor must be connected
closed to load (220nF) and connected to
GND
4.7 µF
Capacitor closed to
Vcca pin
10 nF
CAN-5V
Optional
Vcore voltage
1.23V
3.3V
ESR cap.
800mA, DI/DT = 2A/µs)
1µF
Example of IO
connection and usage
