NXP Semiconductors
Data sheet: Advance Information
Document Number: PF3000
Rev. 9.0, 8/2017
Power management integrated
circuit (PMIC) for i.MX 7 & i.MX 6SL/
SX/UL
PF3000
The PF3000 is a power management integrated circuit (PMIC) designed
specifically for use with the NXP i.MX 7 and i.MX 6SL/SX/UL application
processors. With up to four buck converters, six linear regulators, RTC supply,
and coin-cell charger, the PF3000 can provide power for a complete system,
including applications processors, memory, and system peripherals. This device
is powered by SMARTMOS technology.
Features:
• Four adjustable high efficiency buck regulators: 1.75 A, 1.5 A, 1.25 A, 1.0 A
• Selectable modes: PWM, PFM, APS
• 5.0 V, 600 mA boost regulator with PFM or auto mode
• Six adjustable general purpose linear regulators
• Input voltage range: 2.8 V to 4.5 V or 3.7 V to 5.5 V
• OTP (One Time Programmable) memory for device configuration
• Programmable start-up sequence and timing
• Selectable output voltage, frequency, soft start
• I2C control
• Coin cell charger and always ON RTC supply
• DDR reference voltage
• -40 °C to +125 °C operating junction temperature
PF3000
POWER MANAGEMENT
EP SUFFIX
98ASA00719D
48 QFN 7.0 X 7.0
ES SUFFIX
98ASA00933D
48 QFN 7.0 X 7.0
Applications:
• Tablets
• eReaders
• Wearables
• POS terminals
• Industrial control
• Medical monitoring
• Home automation
• Home security/energy management
i.MX
VREFDDR
Switching regulators
DDR MEMORY
INTERFACE
DDR Memory
SW3
0.90 to 1.65 V @ 1.5 A
SW1A
0.7 to 1.425 V, 1.8V, 3.3V @ 1.0 A
Processor
ARM Core
SW1B
0.70 to 1.475 V @ 1.75 A
Processor SOC
SW2
1.50 to 1.85 V @ 1.25 A
or 2.5 to 3.3 V @ 1.25 A
SWBST
5.00 to 5.15 V @ 0.6 A
SD-MMC/
NAND Mem.
SATA
HDD
RESETBMCU
PWRON
STANDBY
SD_VSEL
INTB
Linear
regulators
VCC_SD
1.80 to 1.85 V @ 100 mA
or 2.85 to 3.3 V @ 100 mA
V33
Li CELL
Charger
2.85 - 3.3 V @ 350 mA
Sensors
Camera
WAM
GPS/MIPI
GPS
MIPI
uPCIe
VLDO3
Camera
HDMI
LDVS Display
USB
Ethernet
CAN
1.8 - 3.3 V @ 100 mA
VLDO4
1.8 - 3.3 V @ 350 mA
Main Supply
2.8 – 5.5 V
Cluster/HUD
Front USB
POD
Rear Seat
Infotaiment
Figure 1. PF3000 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2017.
Audio
Codec
I2C
I2C
VLDO2
0.80 to 1.55 V @ 250 mA
External AMP
Microphones
Speakers
Parallel control/GPIOS
VLDO1
1.8 to 3.3 V @ 100 mA
COINCELL
SATA - FLASH
NAND - NOR
Interfaces
Rear USB
POD
Table of Contents
1
2
3
4
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1 Control logic and interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.2 One-time-programmable memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.4 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.5 Optional front-end input LDO regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.6 Internal core voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.7 VREFDDR voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.8 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.9 Boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.10 LDO Regulators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.11 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.5.1 State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.5.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.5.3 Performance characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.6 Control Interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.6.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.6.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.6.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.6.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.6.5 Specific registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.6.6 Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
10.1Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PF3000
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
The PF3000 is available with pre-programmed OTP memory configurations. The devices are identified using the program codes from
Table 1. Details of the OTP programming for each device can be found in Table 42.
Table 1. Orderable part variations
Part number
Temperature (TA)
Package
Programming options
MC32PF3000A0EP
0 - Not programmed
MC32PF3000A1EP
1 (i.MX 7 with DDR3L)
MC32PF3000A2EP
2 (i.MX 7 with LPDDR3)
MC32PF3000A3EP
MC32PF3000A4EP
MC32PF3000A5EP
-40 °C to 85 °C
(For use in Consumer
applications)
3 (i.MX 6SX with DDR3L)
98ASA00719D, 48 QFN 7.0 mm x
7.0 mm with exposed pad
4 (i.MX 6SX with DDR3)
6 (i.MX 6UL with LPDDR2)
MC32PF3000A7EP
7 (i.MX 6UL with DDR3L)
MC32PF3000A8EP
8 (i.MX 6UL with DDR3)
MC33PF3000A0ES
0 - Not programmed
MC33PF3000A3ES
MC33PF3000A5ES
98ASA00933D, 48 QFN 7.0 mm x
7.0 mm WF-type (wettable flank)
4 (i.MX 6SX with DDR3)
5 (i.MX 6SL with LPDDR2)
6 (i.MX 6UL with LPDDR2)
MC33PF3000A7ES
7 (i.MX 6UL with DDR3L)
MC34PF3000A0EP
0 - Not programmed
MC34PF3000A1EP
1 (i.MX 7 with DDR3L)
MC34PF3000A2EP
2 (i.MX 7 with LPDDR3)
MC34PF3000A4EP
MC34PF3000A5EP
,
3 (i.MX 6SX with DDR3L)
-40 °C to 105 °C
(For use in Automotive
applications)
MC33PF3000A6ES
MC34PF3000A3EP
(1) (2)
5 (i.MX 6SL with LPDDR2)
MC32PF3000A6EP
MC33PF3000A4ES
Notes
-40 °C to 105 °C
(For use in Industrial
applications)
(1) (2)
,
3 (i.MX 6SX with DDR3L)
98ASA00719D, 48 QFN 7.0 mm x
7.0 mm with exposed pad
4 (i.MX 6SX with DDR3)
(1) (2)
,
5 (i.MX 6SL with LPDDR2)
MC34PF3000A6EP
6 (i.MX 6UL with LPDDR2)
MC34PF3000A7EP
7 (i.MX 6UL with DDR3L)
MC34PF3000A8EP
8 (i.MX 6UL with DDR3)
Notes
1. For tape and reel, add an R2 suffix to the part number.
2. The programming options specified in this table are reference for customer application. The part number selection should match the board power
tree design. Table 42 provides details of the OTP programming for each device.
PF3000
NXP Semiconductors
3
GENERAL DESCRIPTION
2
General description
The PF3000 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 7 series of multi-media
application processors. It is also capable of providing full power solution to i.MX 6SL/SX/UL processors.
2.1
Features
This section summarizes the PF3000 features.
• Input voltage range to PMIC: 2.8 V to 4.5 V, or 3.7 V to 5.5 V (3)
• Buck regulators
• Configurable three to four channels
• SW1A/B, 2.75 A (single); 0.7 V to 1.425 V, 1.8 V, 3.3 V
• SW1A, 1.0 A (independent); 0.7 V to 1.425 V, 1.8 V, 3.3 V
• SW1B 1.75 A (independent); 0.7 V to 1.475 V
• SW2, 1.25 A; 1.50 V to 1.85 V or 2.50 V to 3.30 V
• SW3, 1.5 A; 0.90 V to 1.65 V
•
•
•
•
•
•
•
•
•
•
•
•
Dynamic voltage scaling
Modes: PWM, PFM, APS
Programmable output voltage
Programmable current limit
Programmable soft start sequence
Programmable PWM switching frequency
• Boost regulator
• SWBST, 5.0 to 5.15 V, 0.6 A, OTG support
• Modes: PFM and Auto
• OCP fault interrupt
• LDOs
• VCC_SD, 1.8 V to 1.85 V or 2.85 V to 3.30 V, 100 mA based on SD_VSEL
• V33, 2.85 V to 3.30 V, 350 mA
• VLDO1, 1.8 V to 3.3 V, 100 mA
• VLDO2, 0.80 V to 1.55 V, 250 mA
• VLDO3, 1.8 V to 3.3 V, 100 mA
• VLDO4, 1.8 V to 3.3 V, 350 mA
Always ON RTC Regulator/Switch VSNVS 3.0 V, 1.0 mA
DDR memory reference voltage, VREFDDR, 0.5 V to 0.9 V, 10 mA
OTP (One time programmable) memory for device configuration, user-programmable start-up sequence and timing
Battery backed memory including coin cell charger
I2C interface
User programmable standby, sleep/LPSR, and Off modes
Notes
3. 2.8 V to 4.5 V when VIN is used at input. 3.7 V to 5.5 V when VPWR is used as input.
PF3000
4
NXP Semiconductors
GENERAL DESCRIPTION
2.2
Functional block diagram
PF3000 functional internal block diagram
Power generation
OTP startup configuration
OTP prototyping
(Try before burn)
Voltage
Sequence and
timing
Phasing and
frequency selection
Switching regulators
SW1A
(0.7 V to 1.425 V,
1.8 V, 3.3 V, 1.0 A)
Linear regulators
VCC_SD
(1.80 V or 1.85 V, 100 mA)
or (2.85 V or 3.3 V, 100 mA)
V33
( 2.85 V to 3.30 V, 350 mA)
Bias & references
Internal core voltage reference
SW1B
(0.70 V to 1.475 V , 1.75 A)
DDR voltage reference
Logic and control
Parallel MCU interface
VLDO1
(1.8 V to 3.3 V, 100 mA)
SW2
VLDO2
(1.50 V to 1.85 V, 1.25 A)
or (2.50 V to 3.30 V, 1.25 A)
(0.80 V to 1.55 V, 250 mA)
VLDO3
Regulator control
I2C communication & registers
SW3
(0.90 V to 1.65 V, 1.5 A)
(1.8 V to 3.3 V, 100 mA)
VLDO4
(1.8 V to 3.3 V, 350 mA)
Fault detection and protection
Thermal
Current limit
Boost regulator
(5.0 V to 5.15 V, 600 mA)
USB OTG Supply
VPWR front end LDO overvoltage indicator
VSNVS
(1.0 V to 3.0 V, 1.0 mA)
RTC supply with coin cell
charger
Figure 2. Functional block diagram
PF3000
NXP Semiconductors
5
INTERNAL BLOCK DIAGRAM
3
Internal block diagram
PF3000
VLDO1
VLDO1IN
100 mA
VLDO1
SW1A
1.0 A
Buck
VLDO2
VLDO2IN
SW1AFB
O/P
Drive
SW1AIN
SW1ALX
250 mA
VLDO2
VLDO3
VLDO34IN
SW1B
100 mA
VLDO3
1.75 A
Buck
VLDO4
VLDO4
O/P
Drive
SW1BFB
SW1BLX
SW1BIN
GNDREF1
350 mA
Core Control logic
VCC_SD
1.8 V/3.15V
100 mA
VCC_SD
Initialization State Machine
SW2
V33
2.85 V3.30 V
350 mA
V33
VIN2
O/P
Drive
SW2LX
SW2IN
SW2FB
1.25 A
Buck
GNDREF2
Supplies
Control
OTP
SW3FB
VDDOTP
CONTROL
I2C
Interface
VDDIO
SCL
SW3
1.5 A
Buck
SDA
O/P
Drive
SW3IN
SW3LX
GNDREF2
DVS CONTROL
DVS Control
VIN2
SWBST
I2C Register
map
VCOREDIG
VCOREREF
Trim-In-Package
O/P
Drive
SWBSTLX
SWBSTFB
Reference
Generation
VCORE
600 mA
Boost
Clocks and
resets
GNDREF
VPWR
LDOG
VREF
LDO
VIN
Li Cell
Charger
LICELL
Clocks
32 kHz and
16 MHz
Best
of
Supply
VSNVS
VREFDDR
VINREFDDR
INTB
RESETBMCU
SD_VSEL
STANDBY
ICTEST
PWRON
VSNVS
VHALF
Figure 3. PF3000 simplified internal block diagram
PF3000
6
NXP Semiconductors
37 SWBSTFB
38 VIN2
39 VDDOTP
40 GNDREF
41 VCORE
42 VIN
48 PWRON
Transparent Top View
43 VCOREDIG
Pinout diagram
44 VCOREREF
4.1
45 SDA
Pin connections
47 VDDIO
4
46 SCL
PIN CONNECTIONS
INTB
1
36 LICELL
SD_VSEL
2
35 SWBSTLX
RESETBMCU
3
34 VSNVS
STANDBY
4
33 VCC_SD
ICTEST
5
32 V33
SW1AFB
6
31 VPWR
EP
SW1BFB
11
26 GNDREF2
GNDREF1
12
25 VREFDDR
VINREFDDR 24
27 SW3FB
VHALF 23
10
VLDO4 22
SW1BIN
VLDO34IN 21
28 SW3IN
VLDO3 20
9
SW2FB 19
SW1BLX
SW2IN 18
29 SW3LX
SW2LX 17
8
VLDO2IN 16
SW1ALX
VLDO2 15
30 LDOG
VLDO1 14
7
VLDO1IN 13
SW1AIN
Figure 4. Pinout diagram
PF3000
NXP Semiconductors
7
PIN CONNECTIONS
4.2
Pin definitions
Table 2. Pin definitions
Pin number
Pin name
Pin
function
Type
1
INTB
O
Digital
Open drain interrupt signal to processor
2
SD_VSEL
I/O
Digital
Input from i.MX processor to select VCC_SD regulator voltage
• SD_VSEL=0, VCC_SD = 2.85 V to 3.3 V
• SD_VSEL= 1, VCC_SD = 1.8 V to 1.85 V
3
RESETBMCU
O
Digital
Open drain reset output to processor
4
STANDBY
I
Digital
Standby input signal from processor
5
ICTEST
I
Digital and
Analog
6
SW1AFB (4)
I
Analog
SW1A output voltage feedback pin. Route this trace separately from the high current
path and terminate at the output capacitance or near the load, if possible for best
regulation
7
SW1AIN (4)
I
Analog
Input to SW1A regulator. Bypass with at least a 4.7 µF ceramic capacitor and a 0.1 µF
decoupling capacitor as close to the pin as possible
8
SW1ALX (4)
O
Analog
Switcher 1A switch node connection. Connect to SW1A inductor when used in SW1A
independent mode. Connect to SW1BLX and connect to SW1AB inductor when using
SW1A/B as a single regulator
9
SW1BLX (4)
O
Analog
Switcher 1B switch node connection. Connect to SW1B inductor when used in SW1B
independent mode. Connect to SW1ALX and connect to SW1AB inductor when using
SW1A/B as a single regulator
10
SW1BIN (4)
I
Analog
Input to SW1B regulator. Bypass with at least a 4.7 µF ceramic capacitor and a 0.1 µF
decoupling capacitor as close to the pin as possible
11
SW1BFB (4)
I
Analog
SW1B output voltage feedback pin. Route this trace separately from the high current
path and terminate at the output capacitor or near the load, if possible for best regulation
12
GNDREF1
GND
GND
Ground reference for SW1A/B. Connect to GND. Keep away from high current ground
return paths
13
VLDO1IN
I
Analog
VLDO1 input supply. Bypass with a 1.0 µF decoupling capacitor as close to the pin as
possible
14
VLDO1
O
Analog
VLDO1 regulator output. Bypass with a 2.2 µF ceramic output capacitor
15
VLDO2
O
Analog
VLDO2 regulator output. Bypass with a 4.7 µF ceramic output capacitor
16
VLDO2IN
I
Analog
VLDO2 input supply. Bypass with a 1.0 µF decoupling capacitor as close to the pin as
possible
17
SW2LX (4)
O
Analog
Switcher 2 switch node connection.Connect to SW2 inductor
18
SW2IN (4)
I
Analog
Input to SW2 regulator. Bypass with at least a 4.7 µF ceramic capacitor and a 0.1 µF
decoupling capacitor as close to the pin as possible
19
SW2FB (4)
I
Analog
SW2 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
20
VLDO3
O
Analog
VLDO3 regulator output. Bypass with a 2.2 µF ceramic output capacitor
21
VLDO34IN
I
Analog
VLDO3 and VLDO4 input supply. Bypass with a 1.0 µF decoupling capacitor as close to
the pin as possible
22
VLDO4
O
Analog
VLDO4 regulator output. Bypass with a 2.2 µF ceramic output capacitor
23
VHALF
I
Analog
Half supply reference for VREFDDR. Bypass with 0.1 µF to ground.
24
VINREFDDR
I
Analog
VREFDDR regulator input. Connect a 0.1 µF capacitor between VINREFDDR and
VHALF pin. Ensure there is at least 1.0 µF net capacitance from VINREFDDR to ground
25
VREFDDR
O
Analog
VREFDDR regulator output.Bypass with 1.0 µF to ground
Definition
Reserved pin. Connect to GND in application
PF3000
8
NXP Semiconductors
PIN CONNECTIONS
Table 2. Pin definitions (continued)
26
GNDREF2
GND
GND
Reference ground for SW2 and SW3 regulators. Connect to GND. Keep away from high
current ground return paths
27
SW3FB (4)
I
Analog
SW3 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
28
SW3IN (4)
I
Analog
Input to SW3 regulator. Bypass with at least a 4.7 µF ceramic capacitor and a 0.1 µF
decoupling capacitor as close to the pin as possible
29
SW3LX (4)
O
Analog
Switcher 3 switch node connection. Connect the SW3 inductor
30
LDOG
O
Analog
Connect to gate of front-end LDO external pass P-MOSFET. Leave floating if VPWR
LDO is not used
31
VPWR
I
Analog
Input to optional front-end VPWR LDO for systems with input voltage > 4.5 V
32
V33
O
Analog
V33 regulator output. Bypass with a 4.7 µF ceramic output capacitor
33
VCC_SD
O
Analog
Output of VCC_SD regulator. Bypass with a 2.2 µF ceramic output capacitor.
34
VSNVS
O
Analog
VSNVS regulator/switch output. Bypass with 0.47 µF capacitor to ground.
35
SWBSTLX (4)
I/O
Analog
SWBST switch node connection. Connect to SWBST inductor and anode of Schottky
diode
36
LICELL
I/O
Analog
Coin cell supply input/output. Bypass with 0.1 µF capacitor. Connect to optional coin cell.
37
SWBSTFB (4)
I
Analog
SWBST output voltage feedback pin. Route this trace separately from the high current
path and terminate at the output capacitor
38
VIN2
I
Analog
Input to VCC_SD, V33 regulators and SWBST control circuitry. Connect to VIN rail and
bypass with 10 µF capacitor
39
VDDOTP
I
Digital &
Analog
40
GNDREF
GND
GND
41
VCORE
O
Analog
Internal analog core supply. Bypass with 1 µF capacitor to ground
42
VIN
I
Analog
Main IC supply. Bypass with 1.0 µF capacitor to ground. Connect to system input supply
if voltage ≤ 4.5 V. Connect to drain of external PFET when VPWR LDO is used for
systems with input voltage > 4.5 V
Supply to program OTP fuses. Connect VDDOTP to GND during normal application
Ground reference for IC core circuitry. Connect to ground. Keep away from high current
ground return paths
43
VCOREDIG
O
Analog
Internal digital core supply. Bypass with 1.0 µF capacitor to ground
44
VCOREREF
O
Analog
Main band gap reference. Bypass with 220 nF capacitor to ground
45
SDA
I/O
Digital
I2C data line (open drain). Pull up to VDDIO with a 4.7 kΩ resistor
46
SCL
I
Digital
I2C clock. Pull up to VDDIO with a 4.7 kΩ resistor
47
VDDIO
I
Analog
Supply for I2C bus. Bypass with 0.1 µF ceramic capacitor. Connect to 1.7 to 3.6 V
supply. Ensure that VDDIO is always lesser than or equal to VIN
48
PWRON
I
Digital
Power ON/OFF input from processor
-
EP
GND
GND
Expose pad. Functions as ground return for buck and boost regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal dissipation
Notes
4. Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to VIN with a 0.1 μF bypass capacitor.
PF3000
NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
5
General product characteristics
5.1
Absolute maximum ratings
Table 3. Absolute maximum voltage ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Description
Value
Unit
Notes
Electrical ratings
VPWR, ICTEST, LDOG, SWBSTLX
–
-0.3 to 7.5
V
VIN, VIN2, VLDO1IN, SW1AIN, SW1BIN,
SW2IN, SW3IN, SW1ALX, SW1BLX, SW2LX,
SW3LX
–
-0.3 to 4.8
V
OTP programming input supply voltage
-0.3 to 10.0
V
Boost switcher feedback
-0.3 to 5.5
V
–
-0.3 to 3.6
V
VLDO2 linear regulator output
-0.3 to 2.5
V
VCOREDIG
Digital core supply voltage output
-0.3 to 1.65
V
VCOREREF
Bandgap reference voltage output
-0.3 to 1.5
V
±2000
±500
V
VDDOTP
SWBSTFB
INTB, SD_VSEL, RESETBMCU, STANDBY,
SW1AFB, SW1BFB, SW2FB, SW3FB, VLDO1,
VLDO2IN, VLDO3, VLDO34IN, VLDO4, VHALF,
VINREFDDR, VREFDDR, V33, VCC_SD,
VSNVS, LICELL, VCORE, SDA, SCL, VDDIO,
PWRON
VLDO2
VESD
ESD ratings
• Human body model
• Charge device model
(5)
(6)
Notes
5. 10 V maximum voltage rating during OTP fuse programming. 7.5 V maximum DC voltage rated otherwise.
6. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),
robotic (CZAP = 4.0 pF).
PF3000
10
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
5.2
Thermal Characteristics
Table 4. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Thermal Ratings
TA
Ambient operating temperature range
• Industrial version
• Consumer version
-40
-40
105
85
°C
TJ
Operating junction temperature range
-40
125
°C
Storage temperature range
-65
150
°C
–
(9)
°C
(8) (9)
TST
TPPRT
Peak package reflow temperature
(7)
QFN48 thermal resistance and package dissipation ratings
RθJA
Junction to ambient, natural convection
• Four layer board (2s2p)
• Eight layer board (2s6p)
–
–
24
15
°C/W
(10) (11)
(12)
RθJB
Junction to board
–
11
°C/W
(13)
RΘJCBOTTOM
Junction to case bottom
–
1.4
°C/W
(14)
ΨJT
Junction to package top
• Natural convection
–
1.3
°C/W
(15)
Notes
7. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Thermal
Protection Thresholds for thermal protection features.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
9. NXP's package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
10. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
11. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
12. Per JEDEC JESD51-6 with the board horizontal.
13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
15. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC
JESD51-2. When Greek letters (Ψ) are not available, the thermal characterization parameter is written as Psi-JT.
PF3000
NXP Semiconductors
11
GENERAL PRODUCT CHARACTERISTICS
5.3
Current consumption
The current consumption of the individual blocks is described in detail in the following table.
Table 5. Current consumption summary
TA= -40 °C to 105 °C, VPWR= 0 V (External pass FET is not populated), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VPWR = 0 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode
PF3000 conditions
Coin cell
VSNVS from LICELL, All other blocks
off, VIN = 0.0 V
Off
Sleep LPSR
Standby
ON
System conditions
Typ.
Max.
Unit
Notes
No load on VSNVS
4.0
7.0
μA
(16) (17)
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 kHz RC on
All other blocks off
VIN ≥ UVDET
No load on VSNVS, PMIC able to
wake-up
16
25
μA
(16) (17)
VSNVS from VIN
Wake-up from PWRON active
Trimmed reference active
SW3 PFM. All other regulators off.
Trimmed 16 MHz RC off
32 kHz RC on
VREFDDR disabled
No load on any of the regulators.
130 (16)
200 (19)
220 (16)
μA
(18)
LDO1 & LDO3 activated in addition to
SW3
No load on any of the regulators.
170 (16)
260 (19)
248 (16)
μA
(18)
VSNVS from either VIN or LICELL
SW1A in PFM
SW1B in PFM
SW2 in PFM
SW3 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VLDO1-4 enabled
V33 enabled
VCC_SD enabled
VREFDDR enabled
No load on any of the regulators.
297
450
μA
(18)
VSNVS from VIN
SW1A in APS
SW1B in APS
SW2 in APS
SW3 in APS
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VLDO1-4 enabled
V33 enabled
VCC_SD enabled
VREFDDR enabled
No load on any of the regulators.
1.2
mA
Notes
16. At 25 °C only.
17. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
18.
19.
For PFM operation, headroom should be 300 mV or greater.
At 105 °C only.
PF3000
12
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
5.4
Electrical characteristics
Table 6. Electrical characteristics – front-end input LDO
All parameters are specified at TA = -40 °C to 105 °C, VPWR = 5.0 V, VIN = 4.4 V, IVIN = 300 mA, typical external component values, unless
otherwise noted. Typical values are characterized at VPWR = 5.0 V, VIN = 4.4 V, IVIN = 300 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
4.6
3.7
–
–
5.5
4.6
V
(20)
Front end input LDO (VPWR LDO)
VPWR
Operating input voltage
• In regulation
• In dropout operation
VIN
On mode output voltage, 4.6 V < VPWR < 5.5 V,
0.0 mA < IVIN < 3000 mA
4.3
4.4
4.55
V
IVIN
Operating load current at VIN, 3.7 V < VPWR < 5.5 V
0.0
–
3.0
A
–
5.0
10
mA
ILDOGQ
ON mode quiescent current, no load,
Low-power mode output voltage, 4.6 V < VPWR < 5.5 V
0.0 mA < IVIN < 1.0 mA
3.7
4.5
V
VIN_OFF
Off mode output voltage, (CL = 100 μF) 4.6 V < VPWR < 5.5 V,
0.0 mA < IVIN < 35 μA
3.2
4.8
V
ILDOQLP
Low-power mode quiescent current, no load (Standby/Sleep/LPSR
states)
VPWRUV
VPWROV
VIN
–
150
300
μA
VPWR undervoltage threshold (upon undervoltage condition the
external pass FET is turned off)
3.1
–
3.7
V
VPWR overvoltage threshold (upon overvoltage condition interrupt is
asserted at INTB)
5.5
–
6.5
V
IVINUVILIMIT
VPWR LDO current limit under VIN short-circuit (VIN < UVDET)
–
–
300
mA
IVINLEAKAGE
Reverse leakage current from VIN to VPWR, No external pass FET,
VPWR is grounded, device is in OFF state
–
–
1.0
µA
VPWR LDO Off mode quiescent current
–
–
75
μA
IVPWROFF
(21)
Notes
20. While the front end LDO can handle spikes up to 7.5 V at VPWR for as long as 200 µs, the circuit is not expected to be continuously operated
when VPWR is above 5.5 V.
21. This specification gives the leakage current in the VPWR LDO block. Total OFF mode current includes the quiescent current from the other blocks
as specified in Table 5.
PF3000
NXP Semiconductors
13
GENERAL PRODUCT CHARACTERISTICS
Table 7. Static electrical characteristics – SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1xIN = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, typical external component
values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1xIN = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(22), (23)
Switch mode supply SW1A/B (single phase)
VSW1AIN
VSW1BIN
Operating input voltage
2.8
–
4.5
V
VSW1AB
Nominal output voltage
–
Table 53
–
V
-25
25
mV
-25
35
mV
45
mV
-6.0
6.0
%
-6.0
6.0
%
Output voltage accuracy
PWM, APS, 2.8 V < VSW1xIN < 4.5 V, 0 < ISW1AB < 2.75 A
0.7 V ≤ VSW1AB ≤ 1.2 V
• PFM, APS, 2.8 V < VSW1xIN < 4.5 V, 0 < ISW1AB < 2.75A
1.225 V < VSW1AB < 1.425 V
• PFM, steady state, 2.8 V < VSW1xIN < 4.5 V, 0 < ISW1AB < 150 mA
1.8 V ≤ VSW1AB ≤ 1.425 V
• PWM, APS, 2.8 V < VSW1xIN < 4.5 V, 0 < ISW1AB < 2.75A
1.8 V < VSW1AB < 3.3 V
• PFM, steady state, 2.8 V < VSW1xIN < 4.5 V, 0 < ISW1AB < 150 mA
1.8 V ≤ VSW1AB ≤ 3.3 V
•
VSW1ABACC
Rated output load current,
• 2.8 V ≤ VSW1xIN ≤ 4.5 V, 0.7 V < VSW1AB < 1.425 V, 1.8V, 3.3V
ISW1AB
Quiescent current
• PFM mode
• APS mode
ISW1ABQ
-45
–
2750
–
–
mA
–
–
22
300
–
–
µA
3.5
2.6
5.5
4.0
7.5
5.4
A
ISW1ABLIM
Current limiter peak current detection , current through inductor
• SW1xILIM = 0
• SW1xILIM = 1
ΔVSW1AB
Output ripple
–
5.0
–
mV
Discharge resistance
–
600
–
Ω
RSW1ABDIS
Switch mode supply SW1A (independent)
VSW1AIN
Operating input voltage
2.8
–
4.5
V
VSW1A
Nominal output voltage
–
Table 53
–
V
-25
25
mV
-25
25
mV
35
mV
-45
45
mV
-6.0
6.0
%
-6.0
6.0
%
Output voltage accuracy
PWM, APS, 2.8 V < VSW1AIN < 4.5 V, 0 < ISW1A < 1.0 A
0.7 V ≤ VSW1A ≤ 1.2 V
• APS, 3.0 V ≤ VSW1AIN ≤ 3.6 V, 0.01 A < ISW1A < 0.75 A
VSW1A = 1.225 V, TA = 0 °C to 85 °C
•
•
VSW1AACC
•
•
•
ISW1A
PWM, APS, 2.8 V < VSW1AIN < 4.5 V, 0 < ISW1A < 1.0 A
1.225 V < VSW1A ≤ 1.425 V
PFM, steady state, 2.8 V < VSW1AIN < 4.5 V, 0 < ISW1A < 50 mA
0.7 V ≤ VSW1A ≤ 1.425V
PWM, APS, 2.8 V < VSW1AIN < 4.5 V, 0 < ISW1A < 1.0 A
1.8 V ≤ VSW1A ≤ 3.3 V
PFM, steady state, 2.8 V < VSW1AIN < 4.5 V, 0 < ISW1A < 50 mA
1.8 V ≤ VSW1A ≤ 3.3 V
Rated output load current
2.8 V < VSW1AIN < 4.5 V, 0.7 V < VSW1A < 1.425 V, 1.8V, 3.3V
-25
(22), (23)
–
1000
–
–
mA
–
–
50
250
–
–
µA
Switch mode supply SW1a (independent) (Continued)
ISW1AQ
Quiescent current
• PFM mode
• APS mode
PF3000
14
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 7. Static electrical characteristics – SW1 (continued)
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1xIN = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, typical external component
values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1xIN = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
1.78
1.3
2.75
2.0
3.7
2.7
A
ISW1ALIM
Current limiter peak current detection, current through inductor
• SW1AILIM = 0
• SW1AILIM = 1
ΔVSW1A
Output Ripple
–
5.0
–
mV
RONSW1AP
SW1A P-MOSFET RDSON, at VSW1AIN = 3.3 V
–
265
295
mΩ
RONSW1AN
SW1A N-MOSFET RDSON, at VSW1AIN = 3.3 V
–
300
370
mΩ
ISW1APQ
SW1A P-MOSFET leakage current, VSW1AIN = 4.5 V
–
–
10.5
µA
ISW1ANQ
SW1A N-MOSFET leakage current, VSW1AIN = 4.5 V
–
–
3.5
µA
RSW1ADIS
Discharge resistance
–
600
–
Ω
Notes
Switch mode supply SW1B (independent)
VSW1BIN
Operating input voltage
2.8
–
4.5
V
VSW1B
Nominal output voltage
–
Table 53
–
V
VSW1BACC
ISW1B
ISW1BQ
Output voltage accuracy
• PWM, APS, 2.8 V < VSW1BIN < 4.5 V, 0 < ISW1B < 1.75 A
0.7 V < VSW1B < 1.2 V
• PWM, APS, 2.8 V < VSW1BIN < 4.5 V, 0 < ISW1B < 1.75 A
1.225 V < VSW1B < 1.475 V
• PFM, steady state 2.8 V < VSW1BIN < 4.5 V, 0 < ISW1B < 50 mA
0.7 V < VSW1B < 1.475 V
Rated output load current
2.8 V < VSW1BIN < 4.5 V, 0.7 V < VSW1B < 1.475 V
Quiescent current
• PFM mode
• APS mode
-25
-25
(24), (25)
25
–
-45
35
mV
45
1750
–
–
mA
–
–
50
150
–
–
µA
2.4
1.725
3.50
2.65
4.725
3.575
A
ISW1BLIM
Current limiter peak current detection, current through inductor
• SW1BILIM = 0
• SW1BILIM = 1
ΔVSW1B
Output ripple
–
5.0
–
mV
RONSW1BP
SW1B P-MOSFET RDSON, at VSW1BIN = 3.3 V
–
195
225
mΩ
RONSW1BN
SW1B N-MOSFET RDSON, at VSW1BIN = 3.3 V
–
228
295
mΩ
ISW1BPQ
SW1B P-MOSFET leakage current, VSW1BIN = 4.5 V
–
–
12
µA
ISW1BNQ
SW1B N-MOSFET leakage current, VSW1BIN = 4.5 V
–
–
4.0
µA
RSW1BDIS
Discharge resistance during OFF mode
–
600
–
Ω
Notes
22. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
23. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any PF3000 regulator, or external system supply.
24. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
25. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any PF3000 regulator, or external system supply.
PF3000
NXP Semiconductors
15
GENERAL PRODUCT CHARACTERISTICS
Table 8. Dynamic electrical characteristics - SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1xIN = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, typical external component
values, fSW1x = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1xIN = 3.6 V, VSW1x = 1.2 V, ISW1x =
100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW1AB = 0 mA, DVS clk = 25 mV/4 μs, VIN =
VSW1xIN = 4.5 V, VSW1AB = 1.425 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW1AB = 0 mA, DVS clk =
25 mV/4 μs, VIN = VSW1xIN = 4.5 V, VSW1AB = 1.425 V
–
–
500
µs
Start-up overshoot, ISW1A = 0 mA, DVS clk = 25 mV/4.0 μs, VIN =
VSW1AIN = 4.5 V, VSW1A = 1.425 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW1A = 0 mA, DVS clk =
25 mV/4.0 μs, VIN = VSW1AIN = 4.5 V, VSW1A = 1.425 V
–
–
500
µs
Start-up overshoot, ISW1B = 0 mA, DVS clk = 25 mV/4.0 μs, VIN =
VSW1BIN = 4.5 V, VSW1B = 1.475 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW1B = 0 mA, DVS clk =
25 mV/4 μs, VIN = VSW1BIN = 4.5 V, VSW1B = 1.475 V
–
–
500
µs
Notes
Switch mode supply SW1A/B (single phase)
VSW1ABOSH
tONSW1AB
Switch mode supply SW1A (independent)
VSW1AOSH
tONSW1A
Switch mode supply SW1B (independent)
VSW1BOSH
tONSW1B
Table 9. Static electrical characteristics – SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(26), (27)
Switch mode supply SW2
VSW2IN
Operating input voltage
2.8
–
4.5
V
VSW2
Nominal output voltage
–
Table 55
–
V
-3.0%
-6.0%
–
–
3.0%
6.0%
-6.0%
-6.0%
–
–
6.0%
6.0%
1250
–
–
–
–
–
23
145
305
–
–
–
VSW2ACC
ISW2
ISW2Q
Output voltage accuracy
• PWM, APS, 2.8 V ≤ VSW2IN ≤ 4.5 V, 0 ≤ ISW2 ≤ 1.25 A
• 1.50 V ≤ VSW2 ≤ 1.85 V
• 2.5 V ≤ VSW2 ≤ 3.3 V
• PFM, 2.8 V ≤ VSW2IN ≤ 4.5 V, 0 ≤ ISW2 ≤ 50 mA
• 1.50 V ≤ VSW2 ≤ 1.85 V
• 2.5 V ≤ VSW2 ≤ 3.3 V
Rated output load current, 2.8 V < VSW2IN < 4.5 V,
1.50 V < VSW2 < 1.85 V, 2.5 V < VSW2 < 3.3 V
Quiescent current
• PFM mode
• APS mode (low output voltage settings)
• APS mode (high output voltage settings, SW2_HI=1)
%
mA
(28)
µA
Notes
26. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
27. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any PF3000 regulator, or external system supply.
28. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW2IN - VSW2) = ISW2*
(DCR of Inductor +RONSW2P + PCB trace resistance).
PF3000
16
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 9. Static electrical characteristics – SW2 (continued)
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
1.625
1.235
2.5
1.9
3.375
2.565
A
Notes
Switch mode supply SW2 (continued)
ISW2LIM
Current limiter peak current detection, current through inductor
• SW2ILIM = 0
• SW2ILIM = 1
ΔVSW2
Output ripple
–
5.0
–
mV
RONSW2P
SW2 P-MOSFET RDSON at VIN = VSW2IN = 3.3 V
–
215
245
mΩ
RONSW2N
SW2 N-MOSFET RDSON at VSW2IN = VSW2IN = 3.3 V
–
258
326
mΩ
ISW2PQ
SW2 P-MOSFET leakage current, VIN = VSW2IN = 4.5 V
–
–
10.5
µA
ISW2NQ
SW2 N-MOSFET leakage current, VIN = VSW2IN = 4.5 V
–
–
3.0
µA
RSW2DIS
Discharge resistance during OFF mode
–
600
–
Ω
Table 10. Dynamic electrical characteristics - SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW2 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN =
VSW2IN = 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW2 = 0.0 mA, DVS clk =
25 mV/4 μs, VIN = VSW2IN = 4.5 V
–
–
500
µs
Notes
Switch mode supply SW2
VSW2OSH
tONSW2
Table 11. Static electrical characteristics – SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
(29), (30)
Switch mode supply SW3
VSW3IN
Operating input voltage
2.8
–
4.5
V
VSW3
Nominal output voltage
–
Table 57
–
V
-3.0%
–
3.0%
-6.0%
–
6.0%
1500
–
–
VSW3ACC
ISW3
Output voltage accuracy
• PWM, APS, 2.8 V < VSW3IN < 4.5 V, 0 < ISW3 < 1.5 A, 0.9 V < VSW3
< 1.65 V
• PFM, steady state (2.8 V < VSW3IN < 4.5 V, 0 < ISW3 < 50 mA), 0.9 V
< VSW3 < 1.65 V
Rated output load current, 2.8 V < VSW3IN < 4.5 V, 0.9 V < VSW3 <
1.65 V, PWM, APS mode
%
mA
(31)
Notes
29. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
30. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any PF3000 regulator, or external system supply.
31. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW3IN - VSW3) =
ISW3* (DCR of Inductor +RONSW3P + PCB trace resistance).
PF3000
NXP Semiconductors
17
GENERAL PRODUCT CHARACTERISTICS
Table 11. Static electrical characteristics – SW3 (continued)
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Unit
–
–
50
150
–
–
µA
1.95
1.45
3.0
2.25
4.05
3.05
A
Notes
Switch mode supply SW3 (continued)
ISW3Q
Quiescent current
• PFM mode
• APS mode
ISW3LIM
Current limiter peak current detection, current through inductor
• SW3ILIM = 0
• SW3ILIM = 1
ΔVSW3
Output ripple
–
5.0
–
mV
RONSW3P
SW3 P-MOSFET RDSON at VIN = VSW3IN = 3.3 V
–
205
235
mΩ
RONSW3N
SW3 N-MOSFET RDSON at VIN = VSW3IN = 3.3 V
–
250
315
mΩ
ISW3PQ
SW3 P-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
12
µA
ISW3NQ
SW3 N-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
4.0
µA
RSW3DIS
Discharge resistance during Off mode
–
600
–
Ω
Table 12. Dynamic electrical characteristics - SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Symbol
VSW3OSH
tONSW3
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW3 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN =
VSW3IN = 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW3 = 0 mA, DVS clk =
25 mV/4 μs, VIN = VSW3IN = 4.5 V
–
–
500
µs
Notes
Table 13. Static electrical characteristics - SWBST
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external
component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Unit
Notes
2.8
–
4.5
V
(32), (33)
Switch mode supply SWBST
VSWBSTIN
Input voltage range
VSWBST
Nominal output voltage
–
Table 59
–
V
ISWBST
Continuous load current
• 2.8 V ≤ VIN ≤ 3.0 V
• 3.0 V ≤ VIN ≤ 4.5 V
500
600
–
–
–
–
mA
-4.0
–
3.0
%
–
222
289
μA
VSWBSTACC
ISWBSTQ
Output voltage accuracy, 2.8 V ≤ VIN ≤ 4.5 V, 0 < ISWBST
< ISWBSTMAX
Quiescent current (auto mode)
Notes
32. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
33. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any PF3000 regulator, or external system supply.
PF3000
18
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 13. Static electrical characteristics - SWBST (continued)
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external
component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Unit
ΔVSWBST
Output ripple, 2.8 V ≤ VIN ≤ 4.5 V, 0 < ISWBST < ISWBSTMAX, excluding
reverse recovery of Schottky diode
–
–
120
mVp-p
ISWBSTLIM
Peak Current Limit
1400
2200
3200
mA
RDS(on)BST
MOSFET on resistance
–
206
306
mΩ
ISWBSTHSQ
NMOS Off leakage, VSWBST = 4.5 V, SWBSTMODE [1:0] = 00
–
1.0
5.0
µA
Notes
Switch mode supply SWBST (continued)
(34)
Notes
34. Only in Auto and APS modes.
Table 14. Dynamic electrical characteristics - SWBST
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external
component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISWBST = 0.0 mA
–
–
500
mV
Turn-on time, enable to 90% of VSWBST, ISWBST = 0.0 mA
–
–
2.0
ms
Notes
Switch mode supply SWBST
VSWBSTOSH
tONSWBST
Table 15. Static electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating input voltage
• Valid coin cell range
• Valid VIN
1.8
2.25
–
–
3.3
4.5
V
(35)
ISNVS
Operating load current, VINMIN < VIN < VINMAX
1.0
–
1000
μA
VSNVS
Output voltage
-5.0%
• 5.0 μA < ISNVS < 1000 μA (OFF), 3.20 V < VIN < 4.5 V
-5.0%
• 5.0 μA < ISNVS < 1000 μA (ON), 3.20 V < VIN < 4.5 V
• 5.0 μA < ISNVS < 1000μA (Coin cell mode), 2.84 V < VCOIN < 3.3 V VCOIN-0.10
3.0
3.0
–
7.0%
5.0%
VCOIN
–
–
110
mV
1100
–
6750
μA
VSNVS
VIN
VSNVSDROP
ISNVSLIM
Dropout voltage, 2.85 V < VIN < 2.9 V, 1.0 μA < ISNVS < 1000 μA
Current limit, VIN > VTH1
V
VSNVS DC, SWITCH
VLiCell
Operating input voltage, valid coin cell range
1.8
–
3.3
V
ISNVS
Operating load current
1.0
–
1000
μA
–
–
100
Ω
RDS(on)SNVS
Internal switch RDS(on), VCOIN = 2.6 V
Notes
35. The maximum operating input voltage is 4.55 V when VPWR LDO is used
PF3000
NXP Semiconductors
19
GENERAL PRODUCT CHARACTERISTICS
Table 16. Dynamic electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values, unless
otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(36),(37)
VSNVS
VSNVSTON
Turn-on time (load capacitor, 0.47 μF), from VIN = VTH1 to 90% of
VSNVS, VCOIN = 0.0 V, ISNVS = 5.0 μA
–
–
24
ms
VSNVSOSH
Start-up overshoot, ISNVS = 5.0 μA
–
40
70
mV
VSNVSLOTR
Transient load response, 3.2 < VIN ≤ 4.5 V, ISNVS = 100 to 1000 μA
2.8
–
–
V
VTL1
VIN falling threshold (VIN powered to coin cell powered)
2.45
2.70
3.05
V
VTH1
VIN rising threshold (coin cell powered to VIN powered)
2.50
2.75
3.10
V
VIN threshold hysteresis for VTH1-VTL1
5.0
–
–
mV
Output voltage during crossover, VCOIN > 2.9 V, Switch to LDO: VIN >
VTH1, ISNVS = 100 μA, LDO to Switch: VIN < VTL1, ISNVS = 100 μA
2.45
–
–
V
VHYST1
VSNVSCROSS
Notes
36. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to 3.0 V.
37.
From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.
Table 17. Static electrical characteristics - VLDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
VLDO1NOM
+0.250
–
–
4.5
4.5
V
(38), (39)
–
Table 62
–
V
Rated output load current
100
–
–
mA
VLDO1TOL
Output voltage tolerance, VLDO1INMIN < VLDO1IN < 4.5 V, 0.0 mA <
ILDO1 < 100 mA, VLDO1 = 1.8 V to 3.3 V
-3.0
–
3.0
%
ILDO1Q
Quiescent current, no load, change in IVIN, when VLDO1 enabled
–
13
–
μA
122
167
280
mA
VLDO1 linear regulator
VLDO1IN
VLDO1NOM
ILDO1
ILDO1LIM
Operating input voltage
• 1.8 V ≤ VLDO1NOM ≤ 2.5 V
• 2.6 V ≤ VLDO1NOM ≤ 3.3 V
Nominal output voltage
Current limit, ILDO1 when VLDO1 is forced to VLDO1NOM/2
Notes
38. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
39. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any PF3000 regulator, or external system supply.
PF3000
20
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 18. Dynamic electrical characteristics - VLDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
35
52
40
60
–
–
dB
–
–
–
-114
-129
-135
-102
-123
-130
Notes
VLDO1 linear regulator
PSRRVLDO1
PSRR, ILDO1 = 75 mA, 20 Hz to 20 kHz
• VLDO1 = 1.8 V to 3.3 V, VLDO1IN = VLDO1INMIN + 100 mV
• VLDO1 = 1.8 V to 3.3 V, VLDO1IN = VLDO1NOM + 1.0 V
Output noise density, VLDO1IN = VLDO1INMIN, ILDO1 = 75 mA
NOISEVLDO1
• 100 Hz to UVDET
(PWRON_CFG=1)
OFF
PWRON=1
& VIN > UVDET
(PWRON_CFG =0)
Or
PWRON= 0 < 4sec
& VIN > UVDET
(PWRON_CFG=1)
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
PWRON = 0 held >=4 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
ON
Thermal shudown
STANDBY asserted
STANDBY de-asserted
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
PWRON = 0 held >=4 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
Standby
(Suspend)
Thermal shudown
* VIN should be above UVDET to allow a power up and VIN must have crossed above the UVDET rising threshold without decaying below the
UVDET falling threshold.
Figure 15. State diagram
To complement the state diagram in Figure 15, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 32 for the UVDET thresholds. Additionally, I2C control is not possible in the
coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and ON states.
6.5.1.1
ON mode
The PF3000 enters the On mode after a turn-on event. RESETBMCU is de-asserted, and pulled high via an external pull-up resistor, in
this mode of operation. To enter the On mode, VIN voltage must surpass the rising UVDET threshold and PWRON must be asserted. From
the On mode, when the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin
cell mode.
PF3000
54
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.5.1.2
OFF mode
The PF3000 enters the Off mode after a turn-off event. Only VCOREDIG and VSNVS are powered in the mode of operation. To exit the
Off mode, a valid turn-on event is required. RESETBMCU is asserted, LOW, in this mode. Turn off events can be achieved using the
PWRON pin, thermal protection, as described below.
6.5.1.3
PWRON pin
The PWRON pin is used to power off the PF3000. The PWRON pin can be configured with OTP to power off the PMIC under the following
two conditions:
1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
6.5.1.4
Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event
does not power on the PMIC while it is in thermal protection. The part remains in Off mode until the die temperature decreases below a
given threshold. See Power dissipation section for more detailed information.
6.5.1.5
Standby mode
• Depending on STANDBY pin configuration, Standby is entered when the STANDBY pin is asserted. This is typically used for low-power
mode of operation.
• When STANDBY is de-asserted, standby mode is exited.
A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control
of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by
lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of
the regulators in standby is pre-programmed through the I2C interface. Note that the STANDBY pin is programmable for Active High or
Active Low polarity, and that decoding of a standby event takes into account the programmed input polarity as shown in Table 74. When
the PF3000 is powered up first, regulator settings for the standby mode are mirrored from the regulator settings for the ON mode. To
change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for
standby mode as required. For simplicity, STANDBY is generally be referred to as active high throughout this document.
Table 74. Standby pin and polarity control
STANDBY (Pin) (66)
STANDBYINV (I2C bit) (67)
STANDBY Control (65)
0
0
0
0
1
1
1
0
1
1
1
0
Notes
65. STANDBY = 0: System is not in standby, STANDBY = 1: system is in standby
66. The state of the STANDBY pin only has influence in On mode.
67. Bit 6 in Power Control register (ADDR - 0x1B)
Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond
to the pin level changes. A programmable delay is provided to hold off the system response to a standby event. This allows the processor
and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into
standby mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 75, STBYDLY delays the standby initiated response for the entire IC, until the
STBYDLY counter expires. An allowance should be made for three additional 32 kHz cycles required to synchronize the standby event.
PF3000
NXP Semiconductors
55
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 75. STANDBY delay - initiated response
STBYDLY[1:0] (68)
Function
00
No delay
01
One 32 kHz period (default)
10
Two 32 kHz periods
11
Three 32 kHz periods
Notes
68. Bits [5:4] in Power Control register (ADDR - 0x1B)
6.5.1.6
Sleep/LPSR mode
• Depending on PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
• To exit sleep mode, assert the PWRON pin.
In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[3:0] for SW1A/B and by SWxOFF[2:0] for SW2 and SW3.
The activated regulators maintains settings for this mode and voltage until the next turn-on event. Table 76 shows the control bits in sleep
mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event. If LPSR is activated by requesting
VDD_LPSR and VCC_GPIO to stay ON, LDO1 and LDO3 enables in low-power mode.
Table 76. Regulator mode control
SWxOMODE
Off operational mode (sleep) (69)
0
Off
1
PFM
Notes
69. For sleep mode, activated switching regulators, should use the Off mode
set point as programmed by SW1xOFF[4:0] for SW1A/B and
SW2OFF[2:0] for SW2, and SW3OFF[3:0] for SW3.
6.5.1.7
Coin cell mode
In the Coin Cell state, the coin cell is the only valid power source to the PMIC. No turn-on event is accepted in the Coin Cell state. Transition
to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. If the coin cell is depleted, a
complete system reset occurs. At the next application of power and the detection of a turn-on event, the system re-initializes with all I2C
bits including, those that reset on COINPORB are restored to their default states.
PF3000
56
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.5.2
State machine flow summary
Table 77 provides a summary matrix of the PF3000 flow diagram to show the conditions needed to transition from one state to another.
Table 77. State machine flow summary
Next state
STATE
OFF
Coin cell
Sleep
Standby
ON
OFF
X
VIN < UVDET
X
X
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
PWRON_CFG = 1
PWRON = 0 < 4.0 s
& VIN > UNDET
Coin cell
VIN > UVDET
X
X
X
X
X
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
PWRON_CFG = 1
PWRON = 0 < 4.0 s &
VIN > UNDET
VIN < UVDET
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
X
Standby de-asserted
VIN < UVDET
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
Standby asserted
X
Initial state
Sleep/
LPSR
Thermal shutdown
X
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
LPSR (LDO1 & LDO3 or
V33 Enabled) if
VLDO1OMODE =1
& VLDO3OMODE=1 or
V33OMODE=1
VIN < UVDET
Thermal shutdown
Standby
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
Thermal shutdown
ON
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
PF3000
NXP Semiconductors
57
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.5.3
Performance characteristics curves
(VIN = 3.6 V, SW1AOUT = 1.0 V; SW1BOUT = 1.0 V, SW2OUT = 1.8 V, SW3OUT = 1 V, SWBSTOUT = 5.0 V Switching frequency = 2.0 MHz,
Mode = APS; LDO1OUT = 1.8 V, LDO2OUT = 1.0 V, LDO3OUT = 1.8 V, LDO4OUT = 1.8 V, V33OUT = 3.3 V, VCC_SDOUT = 3.3 V, unless
otherwise noted)
Figure 18. Load transient response - LDO2
Figure 16. Typical startup waveforms
Figure 19. Load transient response - LDO4 and V33
Figure 17. Load transient response - LDO1, LDO3 and
VCC_SD
PF3000
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Figure 21. Load transient response - SWBST
Figure 22. Switching frequency vs. temperature
Figure 20. Load transient response - buck regulators
Figure 23. Quiescent current - buck regulators in APS mode
PF3000
NXP Semiconductors
59
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
31
29
SW1A, SW1B
Quiescent current (uA)
27
25
23
SW2, Vout = 3.3 V
21
SW3
19
SW2, Vout = 1.5 V
17
15
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (Ԩ)
Figure 24. Quiescent current - buck regulators in PFM mode
Figure 27. Load regulation - LDOs
Figure 25. Quiescent current - LDOs
Figure 28. SW1A efficiency - APS and PWM modes
Figure 26. Load regulation - buck regulators
Figure 29. SW1A efficiency - PFM mode
PF3000
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Figure 30. Dropout voltage - VLDO1, VLDO3, VCC_SD VOUT = 3.3 V
Figure 32. Dropout voltage - VLDO4, V33 - VOUT = 3.3 V
Figure 31. Dropout voltage - VLDO1, VLDO3,
VCC_SD - VOUT = 1.8 V
Figure 33. Dropout voltage - VLDO4 - VOUT = 1.8 V
6.6
Control Interface I2C block description
The PF3000 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.
The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL
and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be
accomplished by reducing the drive strength of the I2C master via software. It is recommended to use a drive strength of 80 Ω or higher
to increase the edge times. Alternatively, this can be accomplished by using small capacitors from SCL and SDA to ground. For example,
use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 kΩ.
6.6.1
I2C device ID
I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. The I2C address is set to 0x08.
PF3000
NXP Semiconductors
61
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.2
I2C operation
The I2C mode of the interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for general call addressing.)
The I²C interface is configured as “Slave”.
Timing diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at:
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte
is sent out unless a STOP command or NACK is received prior to completion.
PF3000 only supports single-byte I2C transactions for read and write. The host initiates and terminates all communication. The host sends
a master command packet after driving the start condition. The device responds to the host if the master command packet contains the
corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the
host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.
PF3000 uses the “repeated start” operation for reads as shown in Figure 35
.
Figure 34. Data transfer on the I2C bus
Figure 35. Read operation
PF3000
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.3
Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt remains set until cleared.
Each interrupt can be cleared by writing a “1” to the appropriate bit in the Interrupt Status register; this causes the INTB pin to go high. If
there are multiple interrupt bits set the INTB pin remains low until all are either masked or cleared. If a new interrupt occurs while the
processor clears an existing interrupt bit, the INTB pin remains low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin does not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling
for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any
interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the
INTB pin goes low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable. Interrupts generated by external events are debounced; therefore, the event needs to be stable
throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT
summary Table 78. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.6.4
Interrupt bit summary
Table 78 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer to
the related chapters.
Table 78. Interrupt, mask, and sense bits
Interrupt
Mask
Sense
LOWVINI
LOWVINM
LOWVINS
PWRONI
PWRONM
PWRONS
Purpose
Trigger
Debounce time (ms)
Low input voltage detect
Sense is 1 if below 2.70 V threshold
H to L
3.9 (70)
Power on button event
H to L
31.25 (70)
Sense is 1 if PWRON is high.
L to H
31.25
Dual
3.9
THERM110
THERM110M
THERM110S
Thermal 110 °C threshold
Sense is 1 if above threshold
THERM120
THERM120M
THERM120S
Thermal 120 °C threshold
Sense is 1 if above threshold
Dual
3.9
THERM125
THERM125M
THERM125S
Thermal 125 °C threshold
Sense is 1 if above threshold
Dual
3.9
THERM130
THERM130M
THERM130S
Thermal 130 °C threshold
Sense is 1 if above threshold
Dual
3.9
SW1AFAULTI
SW1AFAULTM
SW1AFAULTS
Regulator 1A overcurrent limit
Sense is 1 if above current limit
L to H
8.0
SW1BFAULTI
SW1BFAULTM
SW1BFAULTS
Regulator 1C overcurrent limit
Sense is 1 if above current limit
L to H
8.0
SW2FAULTI
SW2FAULTM
SW2FAULTS
Regulator 2 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
SW3FAULTI
SW3FAULTM
SW3FAULTS
Regulator 3 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
SWBSTFAULTI
SWBSTFAULTM
SWBSTFAULTS
SWBST overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO1FAULTI
VLDO1FAULTM
VLDO1FAULTS
VLDO1 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO2FAULTI
VLDO2FAULTM
VLDO2FAULTS
VLDO2 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VCC_SDFAULTI
VCC_SDFAULTM
VCC_SDFAULTS
VCC_SD overcurrent limit
Sense is 1 if above current limit
L to H
8.0
PF3000
NXP Semiconductors
63
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 78. Interrupt, mask, and sense bits (continued)
Interrupt
Mask
Sense
Purpose
Trigger
Debounce time (ms)
V33FAULTI
V33FAULTM
V33FAULTS
V33 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO3FAULTI
VLDO3FAULTM
VLDO1FAULTS
VLDO3 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO4FAULTI
VLDO4FAULTM
VLDO4FAULTS
VLDO4 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
OTP_ECCI
OTP_ECCM
OTP_ECCS
1 or 2 bit error detected in OTP registers
Sense is 1 if error detected
L to H
-
OTP_AUTO_BLOW OTP_AUTO_BLOWM
OTP_AUTO_BLOWS
Interrupt to indicate completion of fuse
auto blow
L to H
-
VPWROVI
VPWROVS
VPWR pin overvoltage interrupt
L to H
0.122
VPWROVM
Notes
70. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
A full description of all interrupt, mask, and sense registers is provided in Table 79 to Table 90.
Table 79. Register INTSTAT0 - ADDR 0x05
Bit #
R/W
Default
PWRONI
Name
0
R/W1C
0
Power on interrupt bit
LOWVINI
1
R/W1C
0
Low-voltage interrupt bit
THERM110I
2
R/W1C
0
110 °C Thermal interrupt bit
THERM120I
3
R/W1C
0
120 °C Thermal interrupt bit
THERM125I
4
R/W1C
0
125 °C Thermal interrupt bit
THERM130I
5
R/W1C
0
130 °C Thermal interrupt bit
7:6
–
0b00
Unused
Description
Unused
Table 80. Register INTMASK0 - ADDR 0x06
Name
Bit #
R/W
Default
PWRONM
0
R/W1C
1
Power on interrupt mask bit
LOWVINM
1
R/W1C
1
Low-voltage interrupt mask bit
THERM110M
2
R/W1C
1
110 °C thermal interrupt mask bit
THERM120M
3
R/W1C
1
120 °C thermal interrupt mask bit
THERM125M
4
R/W1C
1
125 °C thermal interrupt mask bit
THERM130M
5
R/W1C
1
130 °C thermal interrupt mask bit
7:6
–
0b00
Unused
Description
Unused
PF3000
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 81. Register INTSENSE0 - ADDR 0x07
Name
Bit #
R/W
Default
Description
PWRONS
0
R
0
Power on sense bit
0 = PWRON low
1 = PWRON high
LOWVINS
1
R
0
Low-voltage sense bit
0 = VIN > 2.7 V
1 = VIN ≤ 2.7 V
THERM110S
2
R
0
110 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM120S
3
R
0
120 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM125S
4
R
0
125 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM130S
5
R
0
130 °C thermal sense bit
0 = Below threshold
1 = Above threshold
ICTESTS
6
R
0
0 = ICTEST pin is grounded
1 = ICTEST to VCOREDIG or greater
VDDOTPS
7
R
0
Additional VDDOTP voltage sense pin
0 = VDDOTP grounded
1 = VDDOTP to VCOREDIG or greater
Table 82. Register INTSTAT1 - ADDR 0x08
Name
Bit #
R/W
Default
Description
SW1AFAULTI
0
R/W1C
0
SW1A overcurrent interrupt bit
SW1BFAULTI
1
R/W1C
0
SW1B overcurrent interrupt bit
Unused
2
R/W1C
0
Unused
SW2FAULTI
3
R/W1C
0
SW2 Overcurrent interrupt bit
SW3FAULTI
4
R/W1C
0
SW3 Overcurrent interrupt bit
Unused
5
R/W1C
0
Unused
Unused
6
R/W1C
0
Unused
Unused
7
–
0
Unused
Table 83. Register INTMASK1 - ADDR 0x09
Bit #
R/W
Default
SW1AFAULTM
Name
0
R/W
1
SW1A overcurrent interrupt mask bit
Description
SW1BFAULTM
1
R/W
1
SW1B overcurrent interrupt mask bit
Unused
2
R/W
1
Unused
SW2FAULTM
3
R/W
1
SW2 overcurrent interrupt mask bit
SW3FAULTM
4
R/W
1
SW3 overcurrent interrupt mask bit
Unused
5
R/W
1
Unused
Unused
6
R/W
1
Unused
Unused
7
–
0
Unused
PF3000
NXP Semiconductors
65
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 84. Register INTSENSE1 - ADDR 0x0A
Name
Bit #
R/W
Default
Description
SW1AFAULTS
0
R
0
SW1A overcurrent sense bit
0 = Normal operation
1 = Above current limit
Unused
1
R
0
Unused
SW1BFAULTS
2
R
0
SW1B overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW2FAULTS
3
R
0
SW2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW3FAULTS
4
R
0
SW3 overcurrent sense bit
0 = Normal operation
1 = Above current limit
Unused
5
R
0
Unused
Unused
6
R
0
Unused
Unused
7
–
0
Unused
Table 85. Register INTSTAT3 - ADDR 0x0E
Name
Bit #
R/W
SWBSTFAULTI
0
R/W1C
0
Unused
1
–
0b0
Unused
0b0
High when overvoltage event is detected in the
front-end LDO circuit. This bit defaults to 0b1
when VPWR is grounded and the VIN path is
used to power the PF3000.
VPWROVI
Unused
2
R/W1C
Default
Description
SWBST overcurrent limit interrupt bit
5:3
–
0b0
Unused
OTP AUTO BLOW
6
R/W1C
0b0
High after auto fuse blow sequence is completed
OTP_ECCI
7
R/W1C
0
OTP error interrupt bit
Table 86. Register INTMASK3 - ADDR 0x0F
Name
Bit #
R/W
Default
SWBSTFAULTM
0
R/W
1
SWBST overcurrent limit interrupt mask bit
Unused
1
–
0
Unused
VPWROVM
2
R/W
1
VPWR overvoltage interrupt mask bit
Unused
Description
5:3
–
0b000
OTP_AUTO_BLOW_
DONE_M
Unused
6
R/W
1
OTP auto blow mask bit
OTP_ECCM
7
R/W
1
OTP error interrupt mask bit
PF3000
66
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 87. Register INTSENSE3 - ADDR 0x10
Name
Bit #
R/W
Default
SWBSTFAULTS
0
R
0
Unused
1
–
0b0
VPWROVS
2
R
0
5:3
–
0b000
OTP_AUTO_BLOW_
DONE_S
6
R
0
OTP auto blow sense bit. This bit is high while
the auto blow sequence is running. Do not read/
write the OTP TBB registers while this bit is 1.
OTP_ECCS
7
R
0
OTP error sense bit
0 = No error detected
1 = OTP error detected
Unused
Description
SWBST overcurrent limit sense bit
0 = Normal operation
1 = Above current limit
Unused
VPWR overvoltage interrupt sense bit
Unused
Table 88. Register INTSTAT4 - ADDR 0x11
Name
Bit #
R/W
Default
VLDO1FAULTI
0
R/W1C
0
VLDO1 overcurrent interrupt bit
VLDO2FAULTI
1
R/W1C
0
VLDO2 overcurrent interrupt bit
VCC_SDFAULTI
2
R/W1C
0
VCC_SD overcurrent interrupt bit
V33FAULTI
3
R/W1C
0
V33 overcurrent interrupt bit
VLDO3FAULTI
4
R/W1C
0
VLDO3 overcurrent interrupt bit
5
R/W1C
0
VLDO4 overcurrent interrupt bit
7:6
–
0b00
VLDO4FAULTI
Unused
Description
Unused
Table 89. Register INTMASK4 - ADDR 0x12
Name
Bit #
R/W
Default
VLDO1FAULTM
0
R/W
1
VLDO1 overcurrent interrupt mask bit
VLDO2FAULTM
1
R/W
1
VLDO2 overcurrent interrupt mask bit
VCC_SDFAULTM
2
R/W
1
VCC_SD overcurrent interrupt mask bit
V33FAULTM
3
R/W
1
V33 overcurrent interrupt mask bit
VLDO3FAULTM
4
R/W
1
VLDO3 overcurrent interrupt mask bit
5
R/W
1
VLDO4 overcurrent interrupt mask bit
7:6
–
0b00
VLDO4FAULTM
Unused
Description
Unused
Table 90. Register INTSENSE4 - ADDR 0x13
Name
Bit #
R/W
Default
Description
VLDO1FAULTS
0
R
0
VLDO1 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VLDO2FAULTS
1
R
0
VLDO2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VCC_SDFAULTS
2
R
0
VCC_SD overcurrent sense bit
0 = Normal operation
1 = Above current limit
PF3000
NXP Semiconductors
67
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 90. Register INTSENSE4 - ADDR 0x13 (continued)
Name
Bit #
R/W
Default
V33FAULTS
3
R
0
V33 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VLDO3FAULTS
4
R
0
VLDO3 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VLDO4FAULTS
5
R
0
VLDO4 overcurrent sense bit
0 = Normal operation
1 = Above current limit
7:6
–
0b00
Unused
6.6.5
Description
Unused
Specific registers
6.6.5.1
IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on the chip and described in Table 91 to Table 93.
Table 91. Register DEVICEID - ADDR 0x00
Name
Bit #
R/W
Default
Description
DEVICEID
3:0
R
0x0
0000 = PF3000
FAMILY
7:4
R
0x3
0011 = PF3000
Table 92. Register SILICON REV- ADDR 0x03
Name
METAL_LAYER_REV
FULL_LAYER_REV
Bit #
3:0
7:4
R/W
R
R
Default
Description
0x0
Represents the metal mask revision
Pass 0.0 = 0000
…
Pass 0.15 = 1111
0x1
Represents the full mask revision
Pass 1.0 = 0001
…
Pass 15.0 = 1111
Table 93. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
FIN
1:0
R
0b00
Allows for characterizing different options within
the same reticule
FAB
3:2
R
0b00
Represents the wafer manufacturing facility
Unused
7:4
R
0b0000
Unused
PF3000
68
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.2
Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
Table 94. Register MEMA ADDR 0x1C
Name
MEMA
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank A
Table 95. Register MEMB ADDR 0x1D
Name
MEMB
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank B
Table 96. Register MEMC ADDR 0x1E
Name
MEMC
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank C
Table 97. Register MEMD ADDR 0x1F
Name
MEMD
6.6.5.3
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank D
Register descriptions
This section describes all the PF3000 registers and their individual bits. Address order is as listed in Register map.
6.6.5.3.1
Interrupt status register 0 (INTSTAT0)
INSTAT0 is one of the four status interrupt registers. This register contains six status flags. Write a logic 1 to clear a flag.
Table 98. Status interrupt register 0 (INTSTAT0)
Access: User read/write (71)
Address: 0x05 functional page
7
6
R
W
Default
0
0
5
4
3
2
1
0
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
71. Read: Anytime
Write: Anytime
PF3000
NXP Semiconductors
69
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 99. INTSTAT0 field descriptions
Field
Description
5
THERM130I
130 °C Thermal interrupt bit — THERM130I is set to 1 when the THERM130 threshold specified in is crossed in either direction (bidirectional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM130 threshold.
1 Die temperature has crossed THERM130 threshold.
4
THERM125I
125 °C Thermal interrupt bit — THERM125I is set to 1 when the THERM125 threshold specified in is crossed in either direction (bidirectional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM125 threshold.
1 Die temperature has crossed THERM125 threshold.
3
THERM120I
120 °C Thermal interrupt bit — THERM120I is set to 1 when the THERM120 threshold specified in is crossed in either direction (bidirectional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM120 threshold.
1 Die temperature has crossed THERM120 threshold.
110 °C Thermal interrupt bit — THERM110I is set to 1 when the THERM110 threshold specified in
2
THERM110I
is crossed in either direction (bi-directional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM110 threshold.
1 Die temperature has crossed THERM110 threshold.
1
LOWVINI
Low-voltage interrupt bit — LOWVINI is set to 1 when a low-voltage event occurs on VIN. This flag can only be cleared by writing a
1. Writing a 0 has no effect.
0 VIN > 2.7 V (typical)
1 VIN < 2.7 V (typical)
0
PWRONI
Power on interrupt bit —PWRONI is set to 1 when the turn on event occurs. This flag can only be cleared by writing a 1. Writing a 0
has no effect.
0 Power on has not occurred.
1 Power on has occurred.
6.6.5.3.2
Interrupt status mask register 0 (INTMASK0)
INTMASK0 is the mask register for the status interrupt register INTSTAT0. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 100. Interrupt status mask register 0 (INTMASK0)
Access: User read/write (72)
Address: 0x06 functional page
7
6
R
W
Default
0
0
5
4
3
2
1
0
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
1
1
1
1
1
1
= Unimplemented or Reserved
Notes
72. Read: Anytime
Write: Anytime
PF3000
70
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 101. INTMASK0 field descriptions
Field
Description
5
THERM130M
130 °C Thermal interrupt mask bit
0 THERM130I Unmasked
1 THERM130I Masked
4
THERM125M
125 °C Thermal interrupt mask bit
0 THERM125I Unmasked
1 THERM125I Masked
3
THERM120M
120 °C Thermal interrupt mask bit
0 THERM120I Unmasked
1 THERM120I Masked
2
THERM110M
110 °C Thermal interrupt mask bit
0 THERM110I Unmasked
1 THERM110I Masked
1
LOWVINM
Low-voltage interrupt mask bit
0 LOWVINI Unmasked
1 LOWVINI Masked
0
PWRONM
Power on interrupt mask bit
0 PWRONI Unmasked
1 PWRONI Masked
6.6.5.3.3
Interrupt sense register 0 (INTSENSE0)
This register has seven read-only sense bits. These sense bits reflects the actual state of the corresponding function.
Table 102. Interrupt sense register 0 (INTSENSE0)
Access: User read-only (73)
Address: 0x07 functional page
7
R
6
VDDOTPS
5
4
3
2
1
0
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
X (76)
X (76)
X (76)
X (76)
X (75)
X (74)
W
Default
X (77)
0
= Unimplemented or Reserved
Notes
73.
74.
75.
76.
77.
Read: Anytime
Default value depends on the initial PWRON pin state.
Default value depends on the initial VIN voltage.
Default value depends on the initial temperature of the die.
Default value depends on the initial VDDOTP pin state.
Table 103. INTSENSE0 field descriptions
Field
7
VDDOTPS
Description
VDDOTP voltage sense bit
0 VDDOTP grounded.
1 VDDOTP to VCOREDIG or greater.
5
THERM130S
130 °C thermal interrupt sense bit
0 Die temperature below THERM130 threshold.
1 Die temperature above THERM130 threshold.
4
THERM125S
125 °C thermal interrupt sense bit
0 Die temperature below THERM125 threshold.
1 Die temperature has crossed THERM125 threshold.
PF3000
NXP Semiconductors
71
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 103. INTSENSE0 field descriptions (continued)
Field
Description
3
THERM120S
120 °C thermal interrupt sense bit
0 Die temperature below THERM120 threshold.
1 Die temperature has crossed THERM120 threshold.
2
THERM110S
110 °C thermal interrupt sense bit
0 Die temperature below THERM110 threshold.
1 Die temperature has crossed THERM110 threshold.
1
LOWVINS
Low-voltage interrupt sense bit
0 VIN > 2.7 V (typical)
1 VIN < 2.7 V (typical)
0
PWRONS
Power on interrupt sense bit
0 PWRON low.
1 PWRON high.
6.6.5.3.4
Interrupt status register 1 (INTSTAT1)
INSTAT1 is one of the four status interrupt registers. This register contains four status flags. Write a logic 1 to clear a flag.
Table 104. Status interrupt register 1 (INTSTAT1)
Access: User read/write (78)
Address: 0x08 functional page
7
6
5
R
W
Default
0
0
0
4
3
SW3FAULTI
SW2FAULTI
0
0
2
0
1
0
SW1BFAULTI
SW1AFAULTI
0
0
= Unimplemented or Reserved
Notes
78. Read: Anytime
Write: Anytime
Table 105. INTSTAT1 field descriptions
Field
Description
4
SW3FAULTI
SW3 overcurrent interrupt bit — SW3FAULTI is set to 1 when the SW3 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW3 in normal operation
1 SW3 above current limit
3
SW2FAULTI
SW2 overcurrent interrupt bit — SW2FAULTI is set to 1 when the SW2 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW2 in normal operation
1 SW2 above current limit
1
SW1BFAULTI
SW1B overcurrent interrupt bit — SW1BFAULTI is set to 1 when the SW1B regulator is in current limit protection. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
0 SW1B in normal operation
1 SW1B above current limit
0
SW1AFAULTI
SW1A overcurrent interrupt bit — SW1AFAULTI is set to 1 when the SW1A regulator is in current limit protection. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
0 SW1A in normal operation
1 SW1A above current limit
PF3000
72
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.5
Interrupt status mask register 1 (INTMASK1)
INTMASK1 is the mask register for the status interrupt register INTSTAT1. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 106. Interrupt status mask register 1 (INTMASK1)
Access: User read/write (79)
Address: 0x09 functional page
7
6
5
R
W
Default
0
0
0
4
3
SW3FAULTM
SW2FAULTM
1
1
2
1
0
SW1BFAULTM SW1AFAULTM
0
1
1
= Unimplemented or Reserved
Notes
79. Read: Anytime
Write: Anytime
Table 107. INTMASK1 field descriptions
Field
Description
4
SW3FAULTM
SW3 overcurrent interrupt mask bit
0 SW3FAULTI Unmasked
1 SW3FAULTI Masked
3
SW2FAULTM
SW2 overcurrent interrupt mask bit
0 SW2FAULTI Unmasked
1 SW2FAULTI Masked
1
SW1BFAULTM
SW1B overcurrent interrupt mask bit
0 SW1BFAULTI Unmasked
1 SW1BFAULTI Masked
0
SW1AFAULTM
SW1A overcurrent interrupt mask bit
0 SW1AFAULTI Unmasked
1 SW1AFAULTI Masked
6.6.5.3.6
Interrupt sense register 1 (INTSENSE1)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 108. Interrupt sense register 1 (INTSENSE1)
Access: User read-only (80)
Address: 0x0A functional page
7
6
5
R
4
3
SW3FAULTS
SW2FAULTS
X (81)
X (81)
2
1
0
SW1BFAULTS
SW1AFAULTS
X (81)
X (81)
W
Default
0
0
0
0
= Unimplemented or Reserved
Notes
80. Read: Anytime
81. Default value depends on the regulator initial state
PF3000
NXP Semiconductors
73
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 109. INTSENSE1 field descriptions
Field
Description
4
SW3FAULTS
SW3 overcurrent sense bit
0 SW3 in normal operation
1 SW3 above current limit
3
SW2FAULTS
SW2 overcurrent sense bit
0 SW2 in normal operation
1 SW2 above current limit
1
SW1BFAULTS
SW1B overcurrent sense bit
0 SW1B in normal operation
1 SW1B above current limit
0
SW1AFAULTS
SW1A overcurrent sense bit
0 SW1A in normal operation
1 SW1A above current limit
6.6.5.3.7
Interrupt status register 3 (INTSTAT3)
INSTAT3 is one of the four status interrupt registers. This register contains four status flags. Write a logic 1 to clear a flag.
Table 110. Status Interrupt Register 3 (INTSTAT3)
Access: User read/write (82)
Address: 0x0E functional page
R
W
7
6
OTP_ECCI
OTP_AUTO_BL
OW_DONEI
0
0
Default
5
4
3
2
1
VPWROVI
0
0
0
0
0
SWBSTFAULTI
0
0
= Unimplemented or Reserved
Notes
82. Read: Anytime
Write: Anytime
Table 111. INTSTAT3 field descriptions
Field
Description
7
OTP_ECCI
OTP error interrupt bit — OTP_ECCI is set to 1 when an error is detected in OTP registers. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 No error detected
1 OTP error detected
6
OTP_AUTO_BL
OW_DONEI
OTP auto fuse blow interrupt bit — OTP_AUTO_BLOW_DONEI is set to 1 after the auto fuse blow sequence is completed. This
flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 OTP auto fuse blow sequence not completed
1 OTP auto fuse blow sequence completed
2
VPWROVI
VPWR overvoltage interrupt bit — High when an overvoltage event is detected in the front-end LDO circuit. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 VPWR in normal operation range.
1 VPWR in overvoltage range.
0
SWBSTFAULTI
SWBST overcurrent limit interrupt bit — SWBSTFAULTI is set to 1 when the SWBST regulator is in current limit protection. This
flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 SWBST in normal operation
1 SWBST above current limit
PF3000
74
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.8
Interrupt status mask register 3 (INTMASK3)
INTMASK3 is the mask register for the status interrupt register INTSTAT3. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 112. Interrupt status mask register 3 (INTMASK3)
Access: User read/write (83)
Address: 0x0F functional page
R
W
7
6
OTP_ECCM
OTP_AUTO_BL
OW_DONEM
1
1
Default
5
4
3
2
1
VPWROVM
0
0
0
1
0
SWBSTFAULTM
0
1
= Unimplemented or Reserved
Notes
83. Read: Anytime
Write: Anytime
Table 113. INTMASK3 field descriptions
Field
Description
OTP error interrupt mask bit
0 OTP_ECCI Unmasked
1 OTP_ECCI Masked
7
OTP_ECCM
OTP auto blow mask bit
0 OTP_AUTO_BLOW_DONEI Unmasked
1 OTP_AUTO_BLOW_DONEI Masked
6
OTP_AUTO_BLO
W_DONEM
VPWR overvoltage interrupt mask bit
0 VPWROVI Unmasked
1 VPWROVI Masked
2
VPWROVM
SWBST overcurrent limit interrupt mask bit
0 SWBSTFAULTI Unmasked
1 SWBSTFAULTI Masked
0
SWBSTFAULTM
6.6.5.3.9
Interrupt sense register 3 (INTSENSE3)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 114. Interrupt sense register 3 (INTSENSE3)
Access: User read-only (84)
Address: 0x10 functional page
R
7
6
OTP_ECCS
OTP_AUTO_B
LOW_DONES
0
0
5
4
3
2
1
VPWROVS
0
SWBSTFAULTS
W
Default
0
0
0
0
0
X (85)
= Unimplemented or Reserved
Notes
84. Read: Anytime
85. Default value depends on the regulator initial state
PF3000
NXP Semiconductors
75
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 115. INTSENSE3 field descriptions
Field
Description
OTP error sense bit
0 No error detected
1 OTP error detected
7
OTP_ECCS
OTP auto blow sense bit — This bit is high while the auto blow sequence is running. Do not read/write the OTP TBB registers
while this bit is 1.
0 SW2 in normal operation
1 SW2 at current limit
6
OTP_AUTO_BLO
W_DONES
VPWR overvoltage interrupt sense bit
0 VPWR in normal operation range.
1 VPWR in overvoltage range.
2
VPWROVS
SWBST overcurrent limit sense bit
0 SWBST in normal operation
1 SWBST above current limit
0
SWBSTFAULTS
6.6.5.3.10
Interrupt status register 4 (INTSTAT4)
INSTAT4 is one of the four status interrupt registers. This register contains six status flags. Write a logic 1 to clear a flag.
Table 116. Status interrupt register 4 (INTSTAT4)
Access: User read/write (86)
Address: 0x11 functional page
7
6
R
W
Default
0
0
5
4
3
VLDO4FAULTI
VLDO3FAULTI
V33FAULTI
0
0
0
2
1
0
VCC_SDFAULT
VLDO2FAULTI
I
0
0
VLDO1FAULTI
0
= Unimplemented or Reserved
Notes
86. Read: Anytime
Write: Anytime
Table 117. INTSTAT4 field descriptions
Field
Description
5
VLDO4FAULTI
VLDO4 overcurrent interrupt bit — VLDO4FAULTI is set to 1 when the VLDO4 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO4 in normal operation
1 VLDO4 above current limit
4
VLDO3FAULTI
VLDO3 overcurrent interrupt bit — VLDO3FAULTI is set to 1 when the VLDO3 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO3 in normal operation
1 VLDO3 above current limit
3
V33FAULTI
V33 overcurrent interrupt bit — V33FAULTI is set to 1 when the V33 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 V33 in normal operation
1 V33 above current limit
PF3000
76
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 117. INTSTAT4 field descriptions (continued)
Field
Description
2
VCC_SDFAULTI
VCC_SD overcurrent interrupt bit — VCC_SDFAULTI is set to 1 when the VCC_SD regulator is in current limit protection. This
flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 VCC_SD in normal operation
1 VCC_SD above current limit
1
VLDO2FAULTI
VLDO2 overcurrent interrupt bit — VLDO2FAULTI is set to 1 when the VLDO2 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO2 in normal operation range.
1 VLDO2 above current limit
0
VLDO1FAULTI
VLDO1 overcurrent interrupt bit — SWBSTFAULTI is set to 1 when the SWBST regulator is in current limit protection. This flag
can only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO1 in normal operation range.
1 VLDO1 above current limit
6.6.5.3.11
Interrupt status mask register 4 (INTMASK4)
INTMASK4 is the mask register for the status interrupt register INTSTAT4. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 118. Interrupt status mask register 4 (INTMASK4)
Access: User read/write (87)
Address: 0x12 functional page
7
6
R
W
Default
0
5
4
3
2
1
0
VLDO4FAULT
M
VLDO3FAULT
M
V33FAULTM
VCC_SDFAUL
TM
VLDO2FAULT
M
VLDO1FAULTM
1
1
1
1
1
1
0
= Unimplemented or Reserved
Notes
87. Read: Anytime
Write: Anytime
Table 119. INTMASK4 field descriptions
Field
Description
5
VLDO4FAULTM
VLDO4 overcurrent interrupt mask bit
0 VLDO4FAULTI Unmasked
1 VLDO4FAULTI Masked
4
VLDO3FAULTM
VLDO3 overcurrent interrupt mask bit
0 VLDO3FAULTI Unmasked
1 VLDO3FAULTI Masked
3
V33FAULTM
V33 overcurrent interrupt mask bit
0 V33FAULTI Unmasked
1 V33FAULTI Masked
2
VCC_SDFAULTM
VCC_SD overcurrent interrupt mask bit
0 VCC_SDFAULTI Unmasked
1 VCC_SDFAULTI Masked
1
VLDO2FAULTM
VLDO2 Overcurrent interrupt mask bit
0 VLDO2FAULTI Unmasked
1 VLDO2FAULTI Masked
0
VLDO1FAULTM
VLDO1 overcurrent interrupt mask bit
0 VLDO1FAULTI Unmasked
1 VLDO1FAULTI Masked
PF3000
NXP Semiconductors
77
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.12
Interrupt sense register 4 (INTSENSE4)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Access: User read-only (88)
Address: 0x13 functional page
7
6
R
5
4
3
VLDO4FAULTS VLDO3FAULTS
V33FAULTS
2
1
0
VCC_SDFAULT
VLDO2FAULTS VLDO1FAULTS
S
W
Default
0
0
X (89)
X (89)
X (89)
X (89)
X (89)
X (89)
= Unimplemented or Reserved
Notes
88. Read: Anytime
89. Default value depends on the regulator initial state
Table 120. INTSENSE4 Field Descriptions
Field
Description
5
VLDO4FAULTS
VLDO4 overcurrent sense bit
0 VLDO4 in normal operation
1 VLDO4 above current limit
4
VLDO3FAULTS
VLDO3 overcurrent sense bit
0 VLDO3 in normal operation
1 VLDO3 above current limit
3
V33FAULTS
V33 overcurrent sense bit
0 V33 in normal operation
1 V33 above current limit
2
VCC_SDFAULT
S
VCC_SD overcurrent sense bit
0 VCC_SD in normal operation
1 VCC_SD above current limit
1
VLDO2FAULTS
VLDO2 overcurrent sense bit
0 VLDO2 in normal operation
1 VLDO2 above current limit
0
VLDO1FAULTS
VLDO1 overcurrent sense bit
0 VLDO1 in normal operation
1 VLDO1 above current limit
PF3000
78
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.13
Coin cell control register (COINCTL)
This register is used to control the coin cell charger.
Table 121. Coin cell control register (COINCTL)
Access: User read/write (90)
Address: 0x1A functional page
7
6
5
4
3
R
2
1
COINCHEN
W
Default
0
0
0
0
0
0
VCOIN
0
0
0
= Unimplemented or Reserved
Notes
90. Read: Anytime
Write: Anytime
Table 122. COINCTL field descriptions
Field
3
COINCHEN
2:0
VCOIN
6.6.5.3.14
Description
Coin cell charger enable bit
0 Coin cell charger disabled.
1 Coin cell charger enabled.
Coin cell charger output voltage selection — This field is used to set the coin cell charging voltage from 2.50 V to 3.30 V. See
Table 70 for all options selectable through these bits.
Power control register (PWRCTL)
Table 123. Power control register (PWRCTL)
Access: User read/write (91)
Address: 0x1B functional page
R
W
7
6
REGSCPEN
STANDBYINV
0
0
Default
5
4
STBYDLY
0
3
2
PWRONBDBNC
1
0
0
1
0
PWRONRSTE
N
RESTARTEN
0
0
= Unimplemented or Reserved
Notes
91. Read: Anytime
Write: Anytime
PF3000
NXP Semiconductors
79
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 124. PWRCTL field descriptions
Field
Description
7
REGSCPEN
Short-circuit protection enable bit — When REGSCPEN is set to 1, whenever a current limit event occurs on a LDO regulator, this
regulator is shutdown.
0 Short-circuit protection disabled
1 Short-circuit protection enabled
6
STANDBYINV
4:3
STBYDLY
STANDBY inversion bit —STANDBYINV is used to control the polarity of the STANDBY pin.
0 STANDBY pin is active high
1 STANDBY pin is active low
STANDBY delay bits — STBYDLY is used to set the delay between a standby request from the STANDBY pin and the entering in
standby mode.
00 No delay
01 One 32 kHz period (default)
10 Two 32 kHz periods
11 Three 32 kHz periods
3:2
PWRONDBNC
PWRON programmable debouncer bits — PWRONDBNC is used to set the debounce time for the PWRON input pin. For
configuration, see Table 36.
1
PWRONRSTEN
PWRON reset enable bit — When set to 1, the PF3000 can enter OFF mode when the PWRON pin is held low for 4 seconds or
longer. See PWRON Pin section for details.
0 Disallow OFF mode after PWRON held low
1 Allow OFF mode after PWRON held low
0
RESTARTEN
6.6.5.3.15
Restart enable bit — When set to 1, the PF3000 restarts automatically after a power off event generated by the PWRON (held low
for 4 seconds or longer) when PWR_CFG bit = 1.
0 Automatic restart disabled.
1 Automatic restart enabled.
Embedded memory register A (MEMA)
Table 125. Embedded memory register A (MEMA)
Access: User read/write (92)
Address: 0x1C functional page
7
6
5
4
R
2
1
0
0
0
0
0
MEMA
W
Default
3
0
0
0
0
= Unimplemented or Reserved
Notes
92. Read: Anytime
Write: Anytime
Table 126. MEMA field descriptions
Field
Description
7:0
MEMA
Memory bank A — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
PF3000
80
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.16
Embedded memory register B (MEMB)
Table 127. Embedded memory register B (MEMB)
Address: 0x1D functional page
7
6
5
Access: User read/write
4
R
2
1
0
0
0
0
0
MEMB
W
Default
3
0
0
0
0
= Unimplemented or Reserved
Notes
93. Read: Anytime
Write: Anytime
Table 128. MEMB field descriptions
Field
Description
7:0
MEMB
Memory bank B — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
6.6.5.3.17
Embedded memory register C (MEMC)
Table 129. Embedded Memory Register C (MEMC)
Access: User read/write (94)
Address: 0x1E functional page
7
6
5
4
R
2
1
0
0
0
0
0
MEMC
W
Default
3
0
0
0
0
= Unimplemented or Reserved
Notes
94. Read: Anytime
Write: Anytime
Table 130. MEMC field descriptions
Field
Description
7:0
MEMC
Memory bank C — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
PF3000
NXP Semiconductors
81
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.18
Embedded memory register D (MEMD)
Table 131. Embedded memory register D (MEMD)
Access: User read/write (95)
Address: 0x1F functional page
7
6
5
4
R
3
2
1
0
0
0
0
0
MEMD
W
Default
0
0
0
0
= Unimplemented or Reserved
Notes
95. Read: Anytime
Write: Anytime
Table 132. MEMD field descriptions
Field
Description
7:0
MEMD
Memory bank D — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
6.6.5.3.19
SW1A voltage control register (SW1AVOLT)
This register is used to set the output voltage of the SW1A regulator in normal operation.
Table 133. SW1A voltage control register (SW1AVOLT)
Access: User read/write (96)
Address: 0x20 functional page
7
6
5
4
3
R
1
0
X (97)
X (97)
SW1A
W
Default
2
0
0
0
X (97)
X (97)
X (97)
= Unimplemented or Reserved
Notes
96. Read: Anytime
Write: Anytime
97. Default value depends on OTP content.
Table 134. SW1AVOLT field descriptions
Field
4:0
SW1A
Description
SW1A output voltage — Refer to Table 53
PF3000
82
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.20
SW1A standby voltage control register (SW1ASTBY)
This register is used to set the output voltage of the SW1A regulator in standby operation.
Table 135. SW1A standby voltage control register (SW1ASTBY)
Access: User read/write (98)
Address: 0x21 functional page
7
6
5
4
3
R
1
0
X (99)
X (99)
SW1ASTBY
W
Default
2
0
0
0
X (99)
X (99)
X (99)
= Unimplemented or Reserved
Notes
98. Read: Anytime
Write: Anytime
99. Default value depends on OTP content.
Table 136. SW1ASTBY field descriptions
Field
4:0
SW1ASTBY
6.6.5.3.21
Description
SW1A standby output voltage — Refer to Table 53
SW1A sleep mode voltage control register (SW1AOFF)
This register is used to set the output voltage of the SW1A regulator in sleep mode operation.
Table 137. SW1A sleep mode voltage control register (SW1AOFF)
Access: User read/write (100)
Address: 0x22 functional page
7
6
5
4
3
R
1
0
X (101)
X (101)
SW1AOFF
W
Default
2
0
0
0
X (101)
X (101)
X (101)
= Unimplemented or Reserved
Notes
100. Read: Anytime
Write: Anytime
101. Default value depends on OTP content.
Table 138. SW1AOFF field descriptions
Field
4:0
SW1ASTBY
Description
SW1A sleep mode output voltage — Refer to Table 53
PF3000
NXP Semiconductors
83
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.22
SW1A switching mode selector register (SW1AMODE)
This register is used to set the switching mode of the SW1A regulator.
Table 139. SW1A switching mode selector register (SW1AMODE)
Access: User read/write (102)
Address: 0x23 functional page
7
6
R
5
4
3
2
SW1AOMODE
W
Default
0
0
0
1
0
X (103)
X (103)
SW1AMODE
X (103)
0
X (103)
= Unimplemented or Reserved
Notes
102. Read: Anytime
Write: Anytime
103. Default value depends on OTP content.
Table 140. SW1AMODE field descriptions
Field
5
SW1AOMODE
3:0
SW1AMODE
6.6.5.3.23
Description
SW1A Off mode bit— This bit configures the mode entered by SW1A after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW1A switching mode selector — Refer to Table 47
SW1A configuration register (SW1ACONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW1A regulator.
Table 141. SW1A configuration register (SW1ACONF)
Access: User read/write (104)
Address: 0x24 functional page
7
R
5
SW1ADVSSPE
ED
W
Default
6
0
X (105)
4
SW1APHASE
0
3
2
1
SW1AILIM
SW1AFREQ
0
X (105)
X (105)
0
0
X (105)
= Unimplemented or Reserved
Notes
104. Read: Anytime
Write: Anytime
105. Default value depends on OTP content.
PF3000
84
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 142. SW1ACONF field descriptions
Field
Description
SW1A DVS speed bit— This bit configures the DVS stepping rates speed for SW1A. Refer to the Table 48.
0 25 mV step each 2.0 μs.
1 25 mV step each 4.0 μs.
6
SW1ADVSSPEED
5:4
SW1APHASE
SW1A phase clock bit— SW1APHASE is used to set the phase clock for SW1A. Refer to Table 49.
3:2
SW1AFREQ
SW1A switching frequency— SW1APHASE is used to set the desired switching frequency for SW1A. Refer to Table 51.
SW1A current limiter bit— This bit configures the current limit for SW1A.
0 2.75 A (typ).
1 2.0 A (typ).
0
SW1AILIM
6.6.5.3.24
SW1B voltage control register (SW1BVOLT)
This register is used to set the output voltage of the SW1B regulator in normal operation.
Table 143. SW1B voltage control register (SW1BVOLT)
Access: User read/write (106)
Address: 0x2E functional page
7
6
5
4
3
R
1
0
X (107)
X (107)
SW1B
W
Default
2
0
0
0
X (107)
X (107)
X (107)
= Unimplemented or Reserved
Notes
106. Read: Anytime
Write: Anytime
107. Default value depends on OTP content.
Table 144. SW1BVOLT field descriptions
Field
4:0
SW1B
Description
SW1B output voltage — Refer to Table 53.
PF3000
NXP Semiconductors
85
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.25
SW1B standby voltage control register (SW1BSTBY)
This register is used to set the output voltage of the SW1B regulator in standby operation.
Table 145. SW1B standby voltage control register (SW1BSTBY)
Access: User read/write (108)
Address: 0x2F functional page
7
6
5
4
3
R
1
0
X (109)
X (109)
SW1BSTBY
W
Default
2
0
0
0
X (109)
X (109)
X (109)
= Unimplemented or Reserved
Notes
108. Read: Anytime
Write: Anytime
109. Default value depends on OTP content.
Table 146. SW1BSTBY field descriptions
Field
4:0
SW1BSTBY
6.6.5.3.26
Description
SW1B standby output voltage — Refer to Table 53.
SW1B sleep mode voltage control register (SW1BOFF)
This register is used to set the output voltage of the SW1B regulator in sleep mode operation.
Table 147. SW1B sleep mode voltage control register (SW1BOFF)
Access: User read/write (110)
Address: 0x30 functional page
7
6
5
4
3
R
1
0
X (111)
X (111)
SW1BOFF
W
Default
2
0
0
0
X (111)
X (111)
X (111)
= Unimplemented or Reserved
Notes
110. Read: Anytime
Write: Anytime
111. Default value depends on OTP content.
Table 148. SW1BOFF field descriptions
Field
4:0
SW1BSTBY
Description
SW1B sleep mode output voltage — Refer to Table 53.
PF3000
86
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.27
SW1B switching mode selector register (SW1BMODE)
This register is used to set the switching mode of the SW1B regulator.
Table 149. SW1B switching mode selector register (SW1BMODE)
Access: User read/write (112)
Address: 0x31 functional page
7
6
5
R
3
2
SW1BOMOD
E
W
Default
4
0
0
1
0
X (113)
X (113)
SW1BMODE
0
X (113)
0
X (113)
= Unimplemented or Reserved
Notes
112. Read: Anytime
Write: Anytime
113. Default value depends on OTP content.
Table 150. SW1BMODE field descriptions
Field
5
SW1BOMODE
3:0
SW1BMODE
6.6.5.3.28
Description
SW1B Off mode bit— This bit configures the mode entered by SW1B after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW1B switching mode selector — Refer to Table 47.
SW1B configuration register (SW1BCONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW1B regulator.
Table 151. SW1B configuration register (SW1BCONF)
Access: User read/write X (114)
Address: 0x32 functional page
7
R
W
Default
6
5
SW1BDVSSPEED
0
X (115)
4
SW1BPHASE
0
3
2
1
SW1BFREQ
0
X (115)
X (115)
0
SW1BILIM
0
X (115)
= Unimplemented or Reserved
Notes
114. Read: Anytime
Write: Anytime
115. Default value depends on OTP content.
PF3000
NXP Semiconductors
87
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 152. SW1BCONF field descriptions
Field
Description
SW1B DVS speed bit— This bit configures the DVS stepping rates speed for SW1B. Refer to the Table 48.
0 25 mV step each 2.0 μs.
1 25 mV step each 4.0 μs.
6
SW1BDVSSPEED
5:4
SW1BPHASE
SW1B phase clock bit— SW1BPHASE is used to set the phase clock for SW1B. Refer to Table 49.
3:2
SW1BFREQ
SW1B switching frequency— SW1BPHASE is used to set the desired switching frequency for SW1B. Refer to Table 51.
SW1B current limiter bit— This bit configures the current limit for SW1B.
0 2.75 A (typ).
1 2.0 A (typ).
0
SW1BILIM
6.6.5.3.29
SW2 voltage control register (SW2VOLT)
This register is used to set the output voltage of the SW2 regulator in normal operation.
Table 153. SW2 voltage control register (SW2VOLT)
Access: User read/write (116)
Address: 0x35 functional page
7
6
R
4
3
SW2_HI
W
Default
5
0
0
X (117)
2
1
0
X (117)
X (117)
SW2
X (117)
X (117)
X (117)
= Unimplemented or Reserved
Notes
116. Read: Anytime
Write: Anytime
117. Default value depends on OTP content.
Table 154. SW2VOLT field descriptions
Field
4:0
SW2
5
SW2_HI
Description
SW2 output voltage — Refer to Table 55.
SW2 Output voltage range —This bit configures the range of SW2 Output voltage. Refer to Table 55.
0 Low output voltage settings
1 High output voltage settings
PF3000
88
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.30
SW2 standby voltage control register (SW2STBY)
This register is used to set the output voltage of the SW2 regulator in standby operation.
Table 155. SW2 standby voltage control register (SW2STBY)
Access: User read/write (118)
Address: 0x36 functional page
7
6
R
4
3
SW2_HI
W
Default
5
0
0
X (119)
2
1
0
X (119)
X (119)
SW2STBY
X (119)
X (119)
X (119)
= Unimplemented or Reserved
Notes
118. Read: Anytime
Write: Anytime
119. Default value depends on OTP content.
Table 156. SW2STBY field descriptions
Field
4:0
SW2STBY
5
SW2_HI
6.6.5.3.31
Description
SW2 standby output voltage — Refer to Table 55.
SW2 output voltage range —This bit configures the range of SW2 Output voltage. Refer to Table 55.
0 Low output voltage settings
1 High output voltage settings
SW2 sleep mode voltage control register (SW2OFF)
This register is used to set the output voltage of the SW2 regulator in sleep mode operation.
Table 157. SW2 sleep mode voltage control register (SW2OFF)
Access: User read/write (120)
Address: 0x37 functional page
7
6
R
4
3
SW2_HI
W
Default
5
0
0
X (121)
2
1
0
X (121)
X (121)
SW2OFF
X (121)
X (121)
X (121)
= Unimplemented or Reserved
Notes
120. Read: Anytime
Write: Anytime
121. Default value depends on OTP content.
PF3000
NXP Semiconductors
89
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 158. SW2OFF field descriptions
Field
4:0
SW2STBY
5
SW2_HI
6.6.5.3.32
Description
SW2 sleep mode output voltage — Refer to Table 55.
SW2 output voltage range —This bit configures the range of SW2 Output voltage. Refer to Table 55.
0 Low output voltage settings
1 High output voltage settings
SW2 switching mode selector register (SW2MODE)
This register is used to set the switching mode of the SW2 regulator.
Table 159. SW2 switching mode selector register (SW2MODE)
Access: User read/write (122)
Address: 0x38 functional page
7
6
R
4
3
2
SW2OMODE
W
Default
5
0
0
0
1
0
X (123)
X (123)
SW2MODE
0
X (123)
X (123)
= Unimplemented or Reserved
Notes
122. Read: Anytime
Write: Anytime
123. Default value depends on OTP content.
Table 160. SW2MODE field descriptions
Field
5
SW2OMODE
3:0
SW2MODE
Description
SW2 Off mode bit— This bit configures the mode entered by SW2 after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW2 switching mode selector — Refer to Table 47.
PF3000
90
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.33
SW2 configuration register (SW2CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW2 regulator.
Table 161. SW2 configuration register (SW2CONF)
Access: User read/write (124)
Address: 0x39 functional page
7
6
R
5
SW2DVSSPEE
D
W
Default
X (125)
0
4
3
SW2PHASE
0
2
1
SW2FREQ
X (125)
0
0
SW2ILIM
X (125)
0
X (125)
= Unimplemented or Reserved
Notes
124. Read: Anytime
Write: Anytime
125. Default value depends on OTP content.
Table 162. SW2CONF field descriptions
Field
Description
SW2 DVS speed bit- This bit configures the DVS stepping rates speed for SW2. Refer to the Table 48.
0 25 mV step each 2.0 μs.
1 25 mV step each 4.0 μs.
6
SW2DVSSPEED
5:4
SW2PHASE
SW2 phase clock bit— SW2PHASE is used to set the phase clock for SW2. Refer to Table 49.
3:2
SW2FREQ
SW2 switching frequency— SW2PHASE is used to set the desired switching frequency for SW2. Refer to Table 51.
SW2 current limiter bit— This bit configures the current limit for SW2.
0 2.75 A (typ).
1 2.0 A (typ).
0
SW2ILIM
6.6.5.3.34
SW3 voltage control register (SW3VOLT)
This register is used to set the output voltage of the SW3 regulator in normal operation.
Table 163. SW3 voltage control register (SW3VOLT)
Access: User read/write (126)
Address: 0x3C functional page
7
6
5
4
3
R
1
0
X (127)
X (127)
SW3
W
Default
2
0
0
0
X (127)
X (127)
X (127)
= Unimplemented or Reserved
Notes
126. Read: Anytime
Write: Anytime
127. Default value depends on OTP content.
PF3000
NXP Semiconductors
91
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 164. SW3VOLT field descriptions
Field
4:0
SW3
6.6.5.3.35
Description
SW3 output voltage — Refer to Table 57.
SW3 standby voltage control register (SW3STBY)
This register is used to set the output voltage of the SW3 regulator in standby operation.
Table 165. SW3 standby voltage control register (SW3STBY)
Access: User read/write (128)
Address: 0x3D functional page
7
6
5
4
3
R
1
0
X (129)
X (129)
SW3STBY
W
Default
2
0
0
0
X (129)
X (129)
X (129)
= Unimplemented or Reserved
Notes
128. Read: Anytime
Write: Anytime
129. Default value depends on OTP content.
Table 166. SW3STBY field descriptions
Field
4:0
SW3STBY
6.6.5.3.36
Description
SW3 standby output voltage — Refer to Table 57.
SW3 sleep mode voltage control register (SW3OFF)
This register is used to set the output voltage of the SW3 regulator in sleep mode operation.
Table 167. SW3 sleep mode voltage control register (SW3OFF)
Access: User read/write (130)
Address: 0x3E functional page
7
6
5
4
3
R
1
0
X (131)
X (131)
SW3OFF
W
Default
2
0
0
0
X (131)
X (131)
X (131)
= Unimplemented or Reserved
Notes
130. Read: Anytime
Write: Anytime
131. Default value depends on OTP content.
PF3000
92
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 168. SW3OFF field descriptions
Field
4:0
SW3STBY
6.6.5.3.37
Description
SW3 sleep mode output voltage — Refer to Refer to Table 57.
SW3 switching mode selector register (SW3MODE)
This register is used to set the switching mode of the SW3 regulator.
Table 169. SW3 switching mode selector register (SW3MODE)
Access: User read/write (132)
Address: 0x3F functional page
7
6
R
4
3
2
SW3OMODE
W
Default
5
0
0
0
1
0
X (133)
X (133)
SW3MODE
X (133)
0
X (133)
= Unimplemented or Reserved
Notes
132. Read: Anytime
Write: Anytime
133. Default value depends on OTP content.
Table 170. SW3MODE field descriptions
Field
5
SW3OMODE
3:0
SW3MODE
6.6.5.3.38
Description
SW3 Off mode bit— This bit configures the mode entered by SW3 after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW3 switching mode selector — Refer to Table 47.
SW3 configuration register (SW3CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW3 regulator.
Table 171. SW3 configuration register (SW3CONF)
Access: User read/write (134)
Address: 0x40 functional page
7
R
5
SW3DVSSPEE
D
W
Default
6
0
X (135)
4
SW3PHASE
0
3
2
1
SW3FREQ
0
X (135)
X (135)
0
SW3ILIM
0
X (135)
= Unimplemented or Reserved
Notes
134. Read: Anytime
Write: Anytime
135. Default value depends on OTP content.
PF3000
NXP Semiconductors
93
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 172. SW3CONF field descriptions
Field
Description
SW3 DVS speed bit— This bit configures the DVS stepping rates speed for SW3. Refer to the Table 48.
0 25 mV step each 2.0 μs.
1 25 mV step each 4.0 μs.
6
SW3DVSSPEED
5:4
SW3PHASE
SW3 phase clock bit— SW3PHASE is used to set the phase clock for SW3. Refer to Table 49.
3:2
SW3FREQ
SW3 switching frequency— SW3PHASE is used to set the desired switching frequency for SW3. Refer to Table 51.
SW3 current limiter bit— This bit configures the current limit for SW3.
0 2.75 A (typ).
1 2.0 A (typ).
0
SW3ILIM
6.6.5.3.39
SWBST setup and control register (SWBSTCTL)
This register is used to configure both the output voltage and switching modes of the SWBST regulator.
Table 173. SWBST configuration register (SWBSTCTL)
Access: User read/write (136)
Address: 0x66 functional page
7
R
6
5
4
SWBST1STBYMODE
W
Default
0
X (137)
X (137)
3
2
SWBST1MODE
0
X (137)
X (137)
1
0
SWBST1VOLT
X (137)
X (137)
= Unimplemented or Reserved
Notes
136. Read: Anytime
Write: Anytime
137. Default value depends on OTP content.
Table 174. SWBSTCTL field descriptions
Field
6:5
SWBST1STBYMODE
Description
SWBST switching mode in standby— SWBST1MODE is used to set the switching mode in standby mode.
00 OFF
01 PFM
10 Auto (138)
11 APS
3:2
SWBST1MODE
SWBST switching mode in normal operation— SWBST1MODE is used to set the switching mode on normal operation.
00 OFF
01 PFM
10 Auto (138)
11 APS
1:0
SWBST1VOLT
SWBST output voltage— SWBST1VOLT is used to set the output voltage for SWBST.
00 5.000 V (typ.)
01 5.050 V (typ.)
10 5.100 V (typ.)
11 5.150 V (typ.)
Notes
138. In auto mode, the controller automatically switches between PFM and APS modes depending on the load current. Regulator switches in auto mode
if enabled in the startup sequence.
PF3000
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.40
Front-end LDO control register (LDOGCTL)
This register is used to configure the front-end LDO standby mode operation.
Table 175. Front-end LDO control register (LDOGCTL)
Access: User read/write (139)
Address: 0x69 functional page
7
6
5
4
3
2
1
R
0
STBY_LOWPO
WER_B
W
Default
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
139. Read: Anytime
Write: Anytime
Table 176. LDOGCTL field descriptions
Field
Description
0
STBY_LOWPOWER_B
Front-end LDO standby mode operation bit— When STBY_LOWPOWER_B bit is set to 1, the front-end LDO does not enter
in low-power mode during IC standby mode.
0 Low-power mode enabled during IC standby mode.
1 Low-power mode disabled during IC standby mode.
6.6.5.3.41
VREFDDR control register (VREFDDRCTL)
This register is used to control the VREFDDR supply operation.
Table 177. VREFDDR control register (VREFDDRCTL)
Access: User read/write (140)
Address: 0x6A functional page
7
6
5
4
3
2
1
0
R
VREFDDREN
W
Default
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
140. Read: Anytime
Write: Anytime
Table 178. VREFDDR field descriptions
Field
0
VREFDDREN
Description
VREFDDR supply enable bit— VREFDDREN is used to enable or disable the VREFDDR supply.
0 VREFDDR supply disabled
1 VREFDDR supply enabled
PF3000
NXP Semiconductors
95
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.42
VSNVS control register (VSNVSCTL)
This register is used to control the VSNVS supply operation.
Table 179. VSNVS control register (VSNVSCTL)
Access: User read/write (141)
Address: 0x6B functional page
7
6
5
4
3
2
1
0
R
VSNVSVOLT
W
Default
0
0
0
0
X (142)
0
X (142)
X (142)
= Unimplemented or Reserved
Notes
141. Read: Anytime
Write: Anytime
142. Default value depends on OTP content.
Table 180. VSNVSCTL field descriptions
Field
Description
VSNVS output voltage configuration— VSNVSVOLT is used to configure the VSNVS output voltage. Values below are
typical voltages.
000 = RSVD
001 = RSVD
010 = RSVD
011 = RSVD
100 = RSVD
101 = RSVD
110 = 3.0 V (default)
111 = RSVD
2:0
VSNVSVOLT
6.6.5.3.43
VLDO1 control register (VLDO1CTL)
This register is used to configure output voltage, normal and standby mode operation of the VLDO1 regulator.
Table 181. VLDO1 control register (VLDO1CTL)
Access: User read/write (143)
Address: 0x6C functional page
R
W
Default
7
6
5
4
LDO1OMODE
VLDO1LPWR
VLDO1STBY
VLDO1EN
0
0
0
X (144)
3
2
1
0
X (144)
X (144)
VLDO1
X (144)
X (144)
= Unimplemented or Reserved
Notes
143. Read: Anytime
Write: Anytime
144. Default value depends on OTP content.
PF3000
96
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 182. VLDO1CTL field descriptions
Field
Description
7
LDO1OMODE
VLDO1 OFF mode bit—LDO1OMODE is used to configure VLDO1 operating mode when a PWRON turn-off event occurs.
0 VLDO1 in OFF mode if a PWRON turn off event occurs
1 VLDO1 in sleep mode if a PWRON turn off event occurs
6
VLDO1LPWR
VLDO1 Low-power mode enable bit— When VLDO1LPWR is set to 1, VLDO1 can enter Low-power mode per the conditions in
the Table 66.
0 Low-power mode disabled
1 Low-power mode enabled
5
VLDO1STBY
VLDO1 standby enable bit— When VLDO1STBY is set to 1, VLDO1 is turned off during standby mode. Refer to Table 66.
0 VLDO1 is ON during standby mode.
1 VLDO1 is OFF during standby mode.
VLDO1 enable bit — VLDO1EN is used to enable or disable the VLDO1 regulator.
0 VLDO1 disabled
1 VLDO1 enabled
4
VLDO1EN
3:0
VLDO1
6.6.5.3.44
VLDO1 output voltage configuration— Refer to Table 62.
VLDO2 control register (VLDO2CTL)
This register is used to configure output voltage, normal, and standby mode operation of the VLDO2 regulator.
Table 183. VLDO2 control register (VLDO2CTL)
Access: User read/write (145)
Address: 0x6D functional page
R
W
Default
7
6
5
4
LDO2OMODE
VLDO2LPWR
VLDO2STBY
VLDO2EN
0
0
0
X (146)
3
2
1
0
X (146)
X (146)
VLDO2
X (146)
X (146)
= Unimplemented or Reserved
Notes
145. Read: Anytime
Write: Anytime
146. Default value depends on OTP content.
PF3000
NXP Semiconductors
97
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 184. VLDO2CTL field descriptions
Field
Description
7
LDO2OMODE
VLDO2 OFF mode bit—LDO2OMODE is used to configure VLDO2 operating mode when a PWRON turn-off event occurs.
0 VLDO2 in OFF mode if a PWRON turn off event occurs
1 VLDO2 in Sleep mode if a PWRON turn off event occurs
6
VLDO2LPWR
VLDO2 low-power mode enable bit— When VLDO2LPWR is set to 1, VLDO2 can enter low-power mode per the conditions in
the LDO control table.
0 Low-power mode disabled
1 Low-power mode enabled
5
VLDO2STBY
VLDO2 standby enable bit— When VLDO2STBY is set to 1, VLDO2 is turned off during standby mode. Refer to Table 66.
0 VLDO2 is ON during standby mode.
1 VLDO2 is OFF during standby mode.
VLDO2 enable bit — VLDO2EN is used to enable or disable the VLDO2 regulator.
0 VLDO2 disabled
1 VLDO2 enabled
4
VLDO2EN
3:0
VLDO2
6.6.5.3.45
VLDO2 output voltage configuration— Refer to Table 62.
VCC_SD control register (VCC_SDCTL)
This register is used to configure output voltage, normal and standby mode operation of the VCC_SD regulator.
Table 185. CC_SD control register (VCC_SDCTL)
Access: User read/write (147)
Address: 0x6E functional page
7
R
W
Default
6
5
VCC_SDOMOD
VCC_SDLPWR VCC_SDSTBY
E
0
0
0
4
3
2
1
0
VCC_SDEN
X (148)
VCC_SD
0
0
X (148)
X (148)
= Unimplemented or Reserved
Notes
147. Read: Anytime
Write: Anytime
148. Default value depends on OTP content.
PF3000
98
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 186. VCC_SDCTL field descriptions
Field
Description
7
VCC_SDOMODE
VCC_SD OFF mode bit— VCC_SDOMODE is used to configure VCC_SD operating mode when a PWRON turn-off event occurs.
0 VCC_SD in OFF mode if a PWRON turn off event occurs
1 VCC_SD in Sleep mode if a PWRON turn off event occurs
6
VCC_SDLPWR
VCC_SD low-power mode enable bit— When VCC_SDLPWR is set to 1, VCC_SD can enter low-power mode per the conditions
in the Table 66.
0 Low-power mode disabled
1 Low-power mode enabled
5
VCC_SDSTBY
VCC_SD standby enable bit— When VCC_SDSTBY is set to 1, VCC_SD is turned off during standby mode. Refer to Table 66.
0 VCC_SD is ON during standby mode.
1 VCC_SD is OFF during standby mode.
VCC_SD enable bit — VCC_SDEN is used to enable or disable the VCC_SD regulator.
0 VCC_SD disabled
1 VCC_SD enabled
4
VCC_SDEN
1:0
VCC_SD
6.6.5.3.46
VCC_SD output voltage configuration— Refer to Table 65.
V33 control register (V33CTL)
This register is used to configure output voltage, normal, and standby mode operation of the V33 regulator.
Table 187. V33 control register (V33CTL)
Access: User read/write (149)
Address: 0x6F functional page
R
W
7
6
5
4
V33OMODE
V33LPWR
V33STBY
V33EN
0
0
0
X (150)
Default
3
2
1
0
V33
0
0
X (150)
X (150)
= Unimplemented or Reserved
Notes
149. Read: Anytime
Write: Anytime
150. Default value depends on OTP content.
Table 188. V33CTL field descriptions
Field
7
V33OMODE
Description
V33 OFF mode bit— V33OMODE is used to configure V33 operating mode when a PWRON turn-off event occurs.
0 V33 in OFF mode if a PWRON turn off event occurs
1 V33 in sleep mode if a PWRON turn off event occurs
6
V33LPWR
V33 low-power mode enable bit— When V33LPWR is set to 1, V33 can enter low-power mode per the conditions in the Table 66.
0 Low-power mode disabled
1 Low-power mode enabled
5
V33STBY
V33 standby enable bit— When V33STBY is set to 1, V33 is turned off during standby mode. Refer to Table 66.
0 V33 is ON during standby mode.
1 V33 is OFF during standby mode.
4
V33EN
1:0
V33
V33 Enable bit — V33EN is used to enable or disable the VLDO2 regulator.
0 V33 disabled
1 V33 enabled
V33 output voltage configuration— Refer to Table 64.
PF3000
NXP Semiconductors
99
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.47
VLDO3 control register (VLDO3CTL)
This register is used to configure output voltage, normal, and standby mode operation of the VLDO3 regulator.
Table 189. VLDO3 control register (VLDO3CTL)
Access: User read/write (151)
Address: 0x70 functional page
R
W
7
6
5
4
LDO3OMODE
VLDO3LPWR
VLDO3STBY
VLDO3EN
0
0
0
X (152)
Default
3
2
1
0
X (152)
X (152)
VLDO3
X (152)
X (152)
= Unimplemented or Reserved
Notes
151. Read: Anytime
Write: Anytime
152. Default value depends on OTP content.
Table 190. VLDO3CTL field descriptions
Field
Description
7
LDO3OMODE
VLDO3 OFF mode bit—LDO3OMODE is used to configure VLDO3 operating mode when a PWRON turn-off event occurs.
0 VLDO3 in OFF mode if a PWRON turn off event occurs
1 VLDO3 in sleep mode if a PWRON turn off event occurs
6
VLDO3LPWR
VLDO3 low-power mode enable bit— When VLDO3LPWR is set to 1, VLDO3 can enter low-power mode per the conditions in
the Table 66.
0 Low-power mode disabled
1 Low-power mode enabled
5
VLDO3STBY
VLDO3 standby enable bit— When VLDO3STBY is set to 1, VLDO3 is turned off during standby mode. Refer to Table 66.
0 VLDO3 is ON during standby mode.
1 VLDO3 is OFF during standby mode.
4
VLDO3EN
3:0
VLDO3
VLDO3 enable bit — VLDO3EN is used to enable or disable the VLDO3 regulator.
0 VLDO3 disabled
1 VLDO3 enabled
VLDO3 output voltage configuration— Refer to Table 63.
PF3000
100
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.48
VLDO4 control register (VLDO4CTL)
This register is used to configure output voltage, normal, and standby mode operation of the VLDO4 regulator.
Table 191. VLDO4 control register (VLDO4CTL)
Access: User read/write (153)
Address: 0x71 functional page
R
W
7
6
5
4
LDO4OMODE
VLDO4LPWR
VLDO4STBY
VLDO4EN
0
0
0
X (154)
Default
3
2
1
0
X (154)
X (154)
VLDO4
X (154)
X (154)
= Unimplemented or Reserved
Notes
153. Read: Anytime
Write: Anytime
154. Default value depends on OTP content.
Table 192. VLDO4CTL field descriptions
Field
Description
7
LDO4OMODE
VLDO4 OFF mode bit—LDO4OMODE is used to configure VLDO4 operating mode when a PWRON turn-off event occurs.
0 VLDO4 in OFF mode if a PWRON turn off event occurs
1 VLDO4 in sleep mode if a PWRON turn off event occurs
6
VLDO4LPWR
VLDO4 low-power mode enable bit— When VLDO4LPWR is set to 1, VLDO4 can enter low-power mode per the conditions in
the Table 66.
0 Low-power mode disabled
1 Low-power mode enabled
5
VLDO4STBY
VLDO4 standby enable bit— When VLDO4STBY is set to 1, VLDO4 is turned off during standby mode. Refer to Table 66.
0 VLDO4 is ON during standby mode.
1 VLDO4 is OFF during standby mode.
VLDO4 enable bit — VLDO4EN is used to enable or disable the VLDO4 regulator.
0 VLDO4 disabled
1 VLDO4 enabled
4
VLDO4EN
3:0
VLDO4
6.6.5.3.49
VLDO4 output voltage configuration— Refer to Table 63.
Page selection register
This register is used to access the extended register pages.
Table 193. Page selection register
Access: User read/write (155)
Address: 0x7F functional page
7
6
5
4
3
2
R
0
0
0
PAGE
W
Default
1
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
155. Read: Anytime
Write: Anytime
PF3000
NXP Semiconductors
101
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 194. Page register field descriptions
Field
Description
3:0
PAGE
6.6.6
Register page selection — The PAGE field is used to select one of the three available register pages.
0000 Functional page selected
0001 Extended page 1 selected
0010 Extended page 2 selected
Register map
The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access registers in Extended page 1, one must first write
0x01 to the page register at address 0x7F, and to access registers Extended page 2, one must first write 0x02 to the page register at
address 0x7F. To access the Functional page from one of the extended pages, no write to the page register is necessary.
Registers that are missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect. The
contents of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read/Write bits that are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are
subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that may have other dependencies. For
example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.
PF3000
102
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.6.1
Register map
Table 195. Functional page
BITS[7:0]
Add
Register
name
R/W
Default
00
DeviceID
R
8'b0011_0000
03
04
05
06
07
08
09
0A
0E
0F
10
11
12
13
1A
R
FABID
R
INTMASK0
INTSENSE0
INTSTAT1
INTMASK1
INTSENSE1
INTSTAT3
INTMASK3
INTSENSE3
INTSTAT4
INTMASK4
INTSENSE4
COINCTL
6
5
4
–
–
–
–
0
0
1
1
3
2
RW1C
R/W
R
RW1C
R/W
R
RW1C
R/W
R
RW1C
R/W
R
R/W
1
0
DEVICE ID [3:0]
0
0
FULL_LAYER_REV[3:0]
SILICONREVI
D
INTSTAT0
7
0
0
METAL_LAYER_REV[3:0]
8'b0001_0000
0
0
0
1
0
0
0
–
–
–
–
0
0
0
0
0
0
0
0
–
–
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
0
0
0
0
0
0
0
0
–
–
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
0
0
1
1
1
1
1
1
VDDOTPS
ICTESTS
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
0
0
x
x
x
x
x
x
–
–
–
SW3FAULTI
SW2FAULTI
–
SW1BFAULTI
SW1AFAULTI
0
0
0
0
0
x
0
0
–
–
–
SW3FAULTM
SW2FAULTM
–
0
1
1
1
1
1
–
–
–
SW3FAULTS
SW2FAULTS
–
0
x
x
x
x
x
FAB[1:0]
0
FIN[1:0]
8'b0000_0000
8'b0000_0000
8'b0011_1111
8'b00xx_xxxx
8'b0000_0000
SW1BFAULTM SW1AFAULTM
8'b0111_1111
1
1
SW1BFAULTS SW1AFAULTS
8'b0xxx_xxxx
x
x
OTP_ECCI
OTP AUTO
BLOW DONE
–
–
–
VPWROVI
–
SWBSTFAULT
I
0
0
0
0
0
0
0
0
OTP_ECCM
OTP_AUTO_B
LOW_DONEM
–
–
–
VPWROVI
–
SWBSTFAULT
M
1
1
0
0
0
1
0
1
OTP_ECCS
OTP_AUTO_B
LOW_DONES
–
–
–
VPWROVS
–
SWBSTFAULT
S
0
0
0
0
0
0
0
0
–
–
0
0
0
0
0
–
–
VLDO4
FAULTM
VLDO3
FAULTM
V33
FAULTM
0
0
1
1
1
1
1
1
–
–
VLDO4
FAULTS
VLDO3
FAULTS
V33
FAULTS
VCC_SD
FAULTS
VLDO2
FAULTS
VLDO1
FAULTS
0
0
x
x
x
x
x
x
–
–
–
–
COINCHEN
0
0
0
0
0
8'b0000_0000
8'b1100_0101
8'b0000_000x
VLDO4FAULTI VLDO3FAULTI
V33FAULTI
8'b0000_0000
8'b0011_1111
8'b00xx_xxxx
VCC_SDFAUL
VLDO2FAULTI VLDO1FAULTI
TI
0
0
VCC_SDFAUL VLDO2FAULT
TM
M
0
VLDO1FAULT
M
VCOIN[2:0]
8'b0000_0000
0
0
0
PF3000
NXP Semiconductors
103
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 195. Functional page (continued)
BITS[7:0]
Add
Register
name
R/W
Default
1B
PWRCTL
R/W
8'b0001_0000
7
6
REGSCPEN
STANDBYINV
0
0
5
4
3
STBYDLY[1:0]
0
2
PWRONBDBNC[1:0]
1
1
0
PWRONRSTE
N
RESTARTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
–
MEMA[7:0]
1C
MEMA
R/W
8'b0000_0000
0
0
0
0
MEMB[7:0]
1D
MEMB
R/W
8'b0000_0000
0
0
0
0
0
0
0
0
MEMC[7:0]
1E
MEMC
R/W
8'b0000_0000
MEMD[7:0]
1F
20
21
22
23
24
2E
2F
30
31
32
35
36
37
MEMD
SW1AVOLT
SW1ASTBY
SW1AOFF
SW1AMODE
SW1ACONF
SW1BVOLT
SW1BSTBY
SW1BOFF
SW1BMODE
SW1BCONF
SW2VOLT
SW2STBY
SW2OFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b0000_0000
0
0
0
0
–
–
–
0
0
0
–
–
–
0
0
0
–
–
–
0
0
0
–
SW1A[4:0]
8'b000x_xxxx
–
–
–
SW1ASTBY[4:0]
8'b000x_xxxx
–
–
–
SW1AOFF[4:0]
8'b000x_xxxx
–
–
–
–
–
–
SW1APHASE[1:0]
SW1AFREQ[1:0]
–
SW1AILIM
–
0
0
0
0
1
0
1
0
–
–
SW1AOMODE
–
0
0
0
x
–
SW1ADVSSP
EED
x
-1
0
–
–
–
0
x
x
–
–
–
SW1AMODE[3:0]
8'b0000_xxxx
8'bxx00_0100
0
–
SW1B[4:0]
8'b0xx1_0010
1
0
0
SW1BSTBY[4:0]
8'b0xx1_0010
0
x
x
–
–
–
1
0
x
x
1
–
–
SW1BOMODE
–
0
0
0
–
–
SW1BDVS
SPEED
x
0
0
SW1BOFF[4:0]
8'b0xx1_0010
0
0
SW1BMODE[3:0]
8'b0001_1000
–
–
–
SW1BPHASE[1:0]
SW1BFREQ[1:0]
–
SW1BILIM
–
0
0
–
0
0
–
–
–
–
SW2_HI
0
x
x
x
–
–
–
–
–
SW2_HI
0
x
x
x
–
–
–
–
–
SW2_HI
0
x
x
x
–
8'bx100_0100
–
–
SW2[2:0]
8'b0xxx_0110
–
–
–-
SW2STBY[2:0]
8'b0xxx_xxxx
–
–
–-
SW2STBY[2:0]
8'b0xxx_xxxx
–
–
–-
PF3000
104
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 195. Functional page (continued)
BITS[7:0]
Add
Register
name
R/W
Default
38
SW2MODE
R/W
8'b0010_1000
39
3C
3D
3E
3F
40
SW2CONF
SW3VOLT
SW3STBY
SW3OFF
SW3MODE
SW3CONF
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
–
–
SW2OMODE
–
0
0
1
0
–
SW2DVS
SPEED
x
–
0
1
–
–
–
–
0
x
x
x
–
–
–
–
0
x
x
x
–
–
–
–
8'bxx01_0100
69
6A
6B
6C
6D
6E
6F
70
71
7F
SWBSTCTL
LDOGCTL
VREFDDRCTL
VSNVSCTL
VLDO1CTL
VLDO2CTL
VCC_SDCTL
V33CTL
VLDO3CTL
VLDO4CTL
Page Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
SW2MODE[3:0]
1
SW2PHASE[1:0]
0
SW2FREQ[1:0]
–
–
0
0
–
SW2ILIM
0
0
–
–
–
–
–
–
SW3[3:0]
8'b0xxx_1100
–
–
SW3STBY[3:0]
8'b0xxx_1100
–
–
SW3OFF[3:0]
8'b0xxx_1100
0
x
x
x
–
–
SW3OMODE
–
0
0
1
1
–
SW3DVS
SPEED
x
–
–
–
SW3MODE[3:0]
8'b0011_1000
8'bxx10_0100
–
66
3
1
SW3PHASE[1:0]
1
SWBST1STBYMODE[1:0]
0
–
8'b0xx0_10xx
0
SW3FREQ[1:0]
–
–
SWBST1MODE[1:0]
–
0
0
–
SW3ILIM
0
0
SWBST1VOLT[1:0]
0
–
–
0
–
–
–
–
–
–
–
–
–
–
–
STBY_LP_B
0
x
x
x
x
x
x
x
–
–
–
VREFDDREN
–
–
–
–
0
0
0
–
0
0
0
0
–
–
–
–
–
0
0
0
0
0
LDO1OMODE
VLDO1LPWR
VLDO1STBY
VLDO1EN
0
0
0
–
LDO2OMODE
VLDO2LPWR
VLDO2STBY
VLDO2EN
0
0
0
VCC_SDOMO
DE
VCC_SDLPW
R
0
8'b0xxx_xxx0
8'b000x_0000
VSNVSVOLT[2:0]
8'b0000_0110
1
1
0
–
–-
–
–-
VLDO1[3:0]
8'b010x_1110
–
–
–
–
–
VCC_SDSTBY
VCC_SDEN
–
–
0
0
–
x
x
V33OMODE
V33LPWR
V33STBY
V33EN
–
–
0
0
0
–
x
x
VLDO3OMOD
E
VLDO3LPWR
VLDO3STBY
VLDO3EN
0
0
0
–
VLDO4OMOD
E
VLDO4LPWR
VLDO4STBY
VLDO4EN
0
0
0
–
–
–
–
0
0
0
VLDO2[3:0]
8'b000x_1000
8'b000x_xx10
VCC_SD[1:0]
–
–
V33[1:0]
8'b000x_xx10
8'b010x_0000
8'b000x_xxxx
–
–
–
–
–
–
0
0
VLDO3[3:0]
–
–
VLDO4[3:0]
–
–
PAGE[4:0]
8'b0000_0000
0
0
0
PF3000
NXP Semiconductors
105
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 196. Extended page 1
Address
80
84
8A
BITS[7:0]
Register
Name
TYPE
OTP FUSE
READ EN
R/W
OTP LOAD
MASK
OTP ECC SE1
R/W
R
Default
8'bxxx0_0000
8C
OTP ECC DE1
R
8'bxxx0_0000
8D
RSVD
R
8'bxxx0_0000
A0
OTP SW1A
VOLT
R/W
8'b00xx_xxxx
3
2
1
0
–
–
–
–
–
–
–
OTP FUSE
READ EN
0
0
0
x
x
x
x
x
START
RL PWBRTN
FORCE
PWRCTL
RL PWRCTL
RL OTP
RL OTP ECC
RL OTP
FUSE
RL TRIM FUSE
0
0
0
0
0
0
0
0
–
–
–
ECC5_SE
ECC4_SE
ECC3_SE
ECC2_SE
ECC1_SE
x
x
x
0
0
0
0
0
–
–
–
ECC5_DE
ECC4_DE
ECC3_DE
ECC2_DE
ECC1_DE
x
x
x
0
0
0
0
0
x
x
OTP_SW1A_VOLT[4:0]
x
x
x
x
x
x
OTP_SW1A_SEQ[2:0]
A1
OTP SW1A
SEQ
A2
OTP SW1x
CONFIG
R/W
OTP SW1B
VOLT
R/W
OTP SW1B
SEQ
R/W
RSVD
R/W
AC
4
8'bxxx0_0000
R
AA
5
8'b0000_0000
RSVD
A9
6
8'b000x_xxx0
8B
A8
7
–
–
–
–
OTP_SW1_CONFIG[1:0]
x
x
x
x
x
x
x
x
x
x
x
AE
B0
x
BC
x
x
OTP_SW1B_SEQ[2:0]
8'b00xx_xxxx
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8'b00xx_xxxx
OTP_SW2_HI
OTP SW2
VOLT
R/W
OTP SW2 SEQ
R/W
OTP_SW2_VOLT[2:0]
8'b0xxx_xxxx
x
x
x
x
x
x
OTP SW2
CONFIG
R/W
OTP SW3
VOLT
R/W
OTP SW3 SEQ
R/W
x
x
x
x
x
–
–
–
–
–
–
0
0
0
x
x
0
R/W
x
OTP_SW2_FREQ[1:0]
x
x
OTP_SW3_VOLT[3:0]
8'b0xxx_xxxx
x
x
x
x
x
x
x
OTP_SW3_SEQ[2:0]
8'b0xxx_xxxx
x
x
x
x
x
–
OTP SWBST
VOLT
x
8'b0000_00xx
x
R/W
x
OTP_SW2_SEQ[2:0]
x
–
OTP SW3
CONFIG
x
8'b0xxx_xxxx
x
B2
x
OTP_SW1B_VOLT[4:0]
–
B1
x
8'b00xx_xxxx
–
AD
OTP_SW1x_FREQ[1:0]
8'b000x_xxXx
x
x
OTP_SW3_FREQ[1:0]
8'b0xxx_xxxx
x
x
x
x
x
x
–
–
–
–
–
–
0
0
0
0
0
0
x
x
OTP_SWBST_VOLT[1:0]
8'b0000_00xx
0
0
PF3000
106
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 196. Extended page 1 (continued)
Address
BD
C0
C4
C8
C9
CC
CD
D0
D1
D4
BITS[7:0]
Register
Name
TYPE
OTP SWBST
SEQ
R/W
OTP VSNVS
VOLT
R/W
RSVD
R/W
OTP VLDO1
VOLT
Default
7
6
5
4
3
2
1
0
–
–
–
–
–
0
0
0
0
0
–
–
–
–
–
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
–
0
0
0
x
x
x
x
x
OTP_SWBST_SEQ[2:0]
8'b0000_xxxx
0
0
0
OTP_VSNVS_VOLT[2:0]
8'b0000_0xxx
8'b000x_x0xx
OTP_VLDO1_VOLT[3:0]
R/W
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VLDO1_SEQ[3:0]
OTP VLDO1
SEQ
R/W
OTP VLDO2
VOLT
R/W
OTP VLDO2
SEQ
R/W
OTP VCC_SD
VOLT
R/W
OTP VCC_SD
SEQ
R/W
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VLDO2_VOLT[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VLDO2_SEQ[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
–
x
OTP_VCC_SD_VOLT[2:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VCC_SD_SEQ[2:0]
8'b0000_xxxx
0
0
0
0
0
x
x
x
OTP_V33_VOLT[2:0]
OTP V33
VOLT
R/W
OTP V33 SEQ
R/W
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_V33_SEQ[3:0]
D5
8'b0000_xxxx
0
D8
D9
DC
DD
E0
E4
E5
E6
0
0
x
x
x
x
OTP_VLDO3_VOLT[3:0]
OTP VLDO3
VOLT
R/W
OTP VLDO3
SEQ
R/W
OTP VLDO4
VOLT
R/W
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VLDO3_SEQ[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VLDO4_VOLT[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VLDO4_SEQ[3:0]
OTP VLDO4
SEQ
R/W
OTP PU
CONFIG1
R/W
8'b0000_xxxx
0
OTP FUSE
POR1
R/W
RSVD
R/W
RSVD
0
R/W
0
0
0
x
OTP_PWRON
_CFG
8'b000x_xxxx
x
x
OTP_SWDVS
_CLK
x
OTP_SEQ_CL
K_SPEED
x
x
x
x
x
x
x
x
TBB_POR
–
–
–
–
–
–
–
0
0
0
0
0
0
x
0
–
–
–
–
–
–
–
0
0
0
0
0
0
0
–
–
–
–
–
–
–
0
0
0
0
0
0
0
8'b0000_00x0
8'b0000_00x0
8'b0000_00x0
PF3000
NXP Semiconductors
107
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 196. Extended page 1 (continued)
Address
E7
E8
F0
F1
F7
FF
BITS[7:0]
Register
Name
TYPE
RSVD
R
OTP PWRGD
EN
R/W/M
RSVD
R/W
RSVD
OTP BLOWN
OTP I2C
ADDR
R/W
R/W
R/W
Default
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
0
0
0
0
0
0
0
–
–
–
–
–
–
–
OTP_PG_EN
0
0
0
0
0
0
x
0
–
–
–
0
0
0
x
x
x
x
x
–
–
–
0
0
0
x
x
x
x
x
8'b0000_00x0
8'b0000_000x
8'b000x_xxxx
8'b000x_xxxx
–
–
–
–
–
–
–
OTP_BLOWN
0
0
0
0
0
0
0
x
8'b0000_000x
8'b0000_1xxx
USE_DEFAUL
T_ADD
I2C_SLV
ADDR[3]
–
0
0
0
0
OTP_I2C_SLV ADDR[2:0]
1
x
x
x
2
1
0
Table 197. Extended page 2
Address
81
83
84
85
BITS[7:0]
Register
Name
TYPE
SW1A
PWRSTG
R/W
SW1B
PWRSTG
SW2 PWRSTG
SW3 PWRSTG
R
R
R
Default
8'b1111_1111
8'b1111_1111
8'b1111_1111
8'b1111_1111
88
PWRCTRL
OTP CTRL
8D
I2C WRITE
ADDRESS
TRAP
R/W
8'b0000_0000
8E
I2C TRAP
PAGE
R/W
8'b0000_0000
R
8'b0000_0001
8F
I2C TRAP
CNTR
R/W
8'b0000_0000
90
IO DRV
R/W
8'b00xx_xxxx
D0
OTP AUTO
ECC0
R/W
8'b0000_0000
D8
Reserved
–
8'b0000_0000
D9
Reserved
–
8'b0000_0000
7
6
5
4
3
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
RSVD
RSVD
RSVD
1
1
1
1
1
–
0
0
0
1
1
1
SW2_PWRSTG[2:0]
RSVD
1
RSVD
–
1
SW1B_PWRSTG[2:0]
RSVD
1
RSVD
–
SW1A_PWRSTG[2:0]
1
1
1
SW3_PWRSTG[2:0]
RSVD
1
1
1
PG_SHDWN_
EN
–
–
–
OTP_PWRGD
_EN
0
0
0
0
1
0
0
0
0
0
0
0
0
0
I2C_WRITE_ADDRESS_TRAP[7:0]
0
0
0
LET_IT_ ROLL
RSVD
RSVD
0
0
0
0
0
0
0
I2C_TRAP_PAGE[4:0]
I2C_WRITE_ADDRESS_COUNTER[7:0]
0
0
0
0
0
0
x
x
x
x
x
x
AUTO_ECC
_BANK5
AUTO_ECC
_BANK4
AUTO_ECC_B
ANK3
AUTO_ECC
_BANK2
AUTO_ECC_B
ANK1
0
0
0
0
0
0
0
0
SDA_DRV[1:0]
0
RSVD
–
–
–
0
0
0
INTB_DRV[1:0]
RESETBMCU_DRV[1:0]
AUTO_BLOW_TIME[7:0]
0
0
0
START
RELOAD
EN_RW
0
0
0
0
0
AUTO_FUSE_ AUTO_FUSE_ AUTO_FUSE_ AUTO_FUSE_ AUTO_FUSE_
BLOW5
BLOW4
BLOW3
BLOW2
BLOW1
0
0
0
0
0
PF3000
108
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 197. Extended page 2 (continued)
Address
E1
E2
E3
E4
E5
F1
F2
F3
F4
F5
BITS[7:0]
Register
Name
TYPE
OTP ECC
CTRL1
R/W
OTP ECC
CTRL2
OTP ECC
CTRL3
OTP ECC
CTRL4
OTP ECC
CTRL5
OTP FUSE
CTRL1
OTP FUSE
CTRL2
OTP FUSE
CTRL3
OTP FUSE
CTRL4
OTP FUSE
CTRL5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
7
6
RSVD
ECC1_CALC_
CIN
0
0
RSVD
ECC2_CALC_
CIN
0
0
RSVD
ECC3_CALC_
CIN
0
0
RSVD
ECC4_CALC_
CIN
0
0
RSVD
ECC5_CALC_
CIN
0
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
ECC1_CIN_TBB[5:0]
0
0
0
0
ECC2_CIN_TBB[5:0]
0
0
0
0
ECC3_CIN_TBB[5:0]
0
0
0
0
ECC4_CIN_TBB[5:0]
0
0
0
0
ECC5_CIN_TBB[5:0]
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
0
0
ANTIFUSE1_E ANTIFUSE1_L ANTIFUSE1_R
N
OAD
W
0
0
0
ANTIFUSE2_E ANTIFUSE2_L ANTIFUSE2_R
N
OAD
W
0
0
0
ANTIFUSE3_E ANTIFUSE3_L ANTIFUSE3_R
N
OAD
W
0
0
0
ANTIFUSE4_E ANTIFUSE4_L ANTIFUSE4_R
N
OAD
W
0
0
0
ANTIFUSE5_E ANTIFUSE5_L ANTIFUSE5_R
N
OAD
W
0
0
0
BYPASS1
0
BYPASS2
0
BYPASS3
0
BYPASS4
0
BYPASS5
0
PF3000
NXP Semiconductors
109
TYPICAL APPLICATIONS
7
Typical applications
7.1
Application diagram
SW1AOUT
1.0uF
VIN
VLDO1IN
2.2uF
1.0uF
SW1A
1.0 A
Buck
VLDO2IN
4.7uF
1.0uF
PF3000
VLDO1
100 mA
VLDO1
V33
VLDO2
250 mA
VLDO2
O/P
Drive
1.5uH
SW1ALX
SW1AIN
VIN
100nF
4.7uF
2 x 22uF
SW1AFB
VIN
VLDO34IN
SW1BOUT
VLDO3
100 mA
VLDO3
2.2uF
4.7uF
SW1B
1.75 A
Buck
VLDO4
350 mA
VLDO4
Core Control logic
4.7uF
100nF
2 x 22uF
GNDREF1
SW2OUT
V33
350 mA
V33
VIN
10uF
VIN
SW1BFB
Initialization State Machine
4.7uF
1.5uH
SW1BLX
SW1BIN
VCC_SD
100 mA
VCC_SD
2.2uF
O/P
Drive
SW2
1.25 A
Buck
Supplies
Control
OTP
VIN2
O/P
Drive
1.5uH
SW2LX
SW2IN
VIN
4.7uF
100nF
2 x 22uF
SW2FB
VDDOTP
VDDIO
VDDIO
CONTROL
I2C
Interface
4.7k
4.7k
100nF
SCL
To
MCU
SDA
DVS CONTROL
DVS Control
SW3OUT
O/P
Drive
SW3
1.5 A
Buck
1.5uH
SW3LX
SW3IN
VIN
4.7uF
100nF
2 x 22uF
SW3FB
GNDREF2
1.0uF
I2C
Register
map
VCOREDIG
220nF
VCOREREF
1.0uF
Reference
Generation
VCORE
VIN
VIN2
Trim-In-Package
SWBST
600 mA
Boost
Clocks and
resets
O/P
Drive
2.2uH
SWBSTLX
10uF
SWBSTOUT
2 x 22uF
SWBSTFB
GNDREF
1.0uF
VREFDDR
SW3OUT
VINREFDDR
Clocks
100nF
32kHz and 16MHz
VHALF
1.0uF
100nF
+5V
VPWR
VREF
2 x 47uF
4.7uF
100nF
LDOG
Package Pin Legend
Output Pin
LDO
Input Pin
Bi-directional Pin
VIN*
VDDIO
100k
VDDIO
100k
0.47uF
To/From Processor
SD_VSEL
VSNVS
INTB
220nF
Best
of
Supply
VSNVS
Coin Cell
Battery
Li Cell
Charger
STANDBY
LICELL
RESETBMCU
1.0uF
ICTEST
100nF
PWRON
2 x 47uF
VIN
Notes:
*: The PF3000 can also be powered through VIN directly (ie. 3.7V Li-ion Battery
application). In this case, the Front-End LDO regulator is not used : the external
MOSFET has to be unpopulated and VPWR pin must be connected to GND .
The capacitors on VPWR can be removed and only a 2.2uF capacitor on VIN to
ground is necessary in this case.
- Unused BUCK and BOOST: Connect input pin SWxIN to VIN with a 0.1 uF
bypass capacitor to ground. Leave LX and FB pins floating.
- Unused LDO: output can be left floating . Connect input pin to GND if not shared
with other LDOs.
Figure 36. Typical application schematic
PF3000
110
NXP Semiconductors
BILL OF MATERIALS
8
Bill of materials
The following table provides a complete list of the recommended components on a full featured system using the PF3000 Device for
-40 °C to 85 °C applications. Components are provided with an example part number; equivalent components may be used.
Table 198. Bill of materials for -40 °C to 85 °C applications
Value
Qty
Description
Part#
Manufacturer
Component/Pin
PMIC
N/A
1
Power management IC
PF3000
NXP
IC
IND PWR 1.5 μH at 1.0 MHz 2.9 A
20% 2016
DFE201610E-1R5M
TOKO INC.
SW1A, SW1B, SW2, SW3
inductors
IND PWR 1.5 μH at 1.0 MHz 2.2 A
20% 1210
BRL3225T1R5M
Taiyo Yuden
Alternate for low-power
applications
Buck regulators
1.5 µH
4
4.7 µF
4
CAP CER 4.7 µF 10 V 20% X5R
0402
GRM155R61A475MEAA
Murata
SW1A, SW1B, SW2, SW3 input
capacitors
0.1 µF
4
CAP CER 0.1 µF 10 V 20% X5R
0201
GRM033R61A104ME84
Murata
SW1A, SW1B, SW2, SW3 input
capacitors (optional)
22 µF
8
CAP CER 22 µF 10 V 20% X5R
0603
GRM188R61A226ME15
Murata
SW1A, SW1B, SW2, SW3 output
capacitors
IND PWR 2.2 µH at 1.0 MHz 2.4 A
20% 2016
DFE201610E-2R2M
TOKO INC.
SWBST inductor
IND PWR 2.2 µH at 1.0 MHz
1.85 A 20% 1210
BRL3225T2R2M
Taiyo Yuden
Alternate for low-power
applications
Boost regulator
2.2 µH
1
10 µF
1
CAP CER 10 µF 10 V 20% X5R
0402
GRM155R61A106ME11
Murata
SWBST input capacitor
N/A
1
DIODE SCH PWR RECT 1.0 A
20 V SMT
MBR120LSFT3G
ON Semi
SWBST diode
22 µF
2
CAP CER 22 µF 10 V 20% X5R
0603
GRM188R61A226ME15D
Murata
SWBST output capacitors
Linear regulators
1.0 µF
3
CAP CER 1.0 µF 10 V 20% X5R
0201
GRM033R61A105ME44
Murata
VLDO1, VLDO2, VLDO3 and
VLDO4 input capacitors
2.2 µF
3
CAP CER 2.2 µF 10 V 20% X5R
0201
GRM033R61A225ME47
Murata
VLDO1, VLDO3, VCC_SD
output capacitors
10 µF
1
CAP CER 10 µF 10 V 20% X5R
0402
GRM155R61A106ME11
Murata
V33 and VCC_SD input
capacitor
4.7 µF
3
CAP CER 4.7 µF 10 V 20% X5R
0402
GRM155R61A475MEAA
Murata
VLDO2, VLDO4, V33 output
capacitors
1.0 µF
4
CAP CER 1.0 µF 10 V 20% X5R
0201
GRM033R61A105ME44
Murata
VCORE, VCOREDIG,
VREFDDR, VINREFDDR
capacitors
0.22 µF
2
CAP CER 0.22 µF 10 V 20% X5R
0201
GRM033R61A224ME90
Murata
VCOREREF and Coin Cell
output capacitors
0.47 µF
1
CAP CER 0.47 µF 10 V 20% X5R
0201
GRM033R61A474ME90
Murata
VSNVS output capacitor
47 µF
4
CAP CER 47 µF 10 V 20% X5R
0805
GRM21BR61A476ME15
Murata
Front-end LDO capacitors for
VIN and VPWR.
Miscellaneous
PF3000
NXP Semiconductors
111
BILL OF MATERIALS
Table 198. Bill of materials for -40 °C to 85 °C applications (continued)
Value
Qty
Description
Part#
Manufacturer
Component/Pin
2.2 µF
1
CAP CER 2.2 µF 10 V 20% X5R
0201
GRM033R61A225ME47
Murata
VIN input capacitor when not
using Front-end LDO
0.1 µF
5
CAP CER 0.1 µF 10 V 10% X5R
0201
GRM033R61A104KE84
Murata
VDDIO, VHALF, VPWR, VIN
input capacitors (optional)
N/A
1
TRAN PMOS 11. A 12 V 12 SOT1220
PMPB15XP
NXP
External MOSFET
100 k
2
RES MF 100 k 1/16 W 1% 0402
RC0402FR-07100KL
Yageo America
Pull-up resistors
4.7 k
2
RES MF 4.70 k 1/20 W 1% 0201
RC0201FR-074K7L
Yageo America
I²C pull-up resistors
The following table provides a complete list of the recommended components on a full featured system using the PF3000 Device for
-40 °C to 105 °C applications. Components are provided with an example part number, equivalent components may be used.
Table 199. Bill of materials for -40 °C to 105 °C applications
Value
Qty
Description
Part#
Manufacturer
Component/Pin
PMIC
N/A
1
Power management IC
PF3000
NXP
IC
IND PWR 1.5 µH at 1.0 MHz 2.9 A
20% 2016
DFE201610E-1R5M
Toko Inc.
SW1A, SW1B, SW2, SW3
inductors
IND PWR 1.5 µH at 1.0 MHz 2.2 A
20% 1210
BRL3225T1R5M
Taiyo Yuden
Alternate for low-power
applications
Buck regulators
1.5 µH
4
4.7 µF
4
CAP CER 4.7 µF 10 V 10% X7S
0603
GRM188C71A475KE11
Murata
SW1A, SW1B, SW2, SW3 input
capacitors
0.1 µF
4
CAP CER 0.1 µF 10 V 10% X7S
0201
GRM033C71A104KE14
Murata
SW1A, SW1B, SW2, SW3 input
capacitors (optional)
22 µF
8
CAP CER 22 µF 10 V 20% X7T
0805
GRM21BD71A226ME44
Murata
SW1A, SW1B, SW2, SW3 output
capacitors
IND PWR 2.2 µH at 1.0 MHz 2.4 A
20% 2016
DFE201610E-2R2M
Toko Inc.
SWBST Inductor
IND PWR 2.2 µH at 1.0 MHz
1.85 A 20% 1210
BRL3225T2R2M
Taiyo Yuden
Alternate for low-power
applications
Boost regulator
2.2 µH
1
10 µF
1
CAP CER 10 µF 10 V 20% X7T
0603
GRM188D71A106MA73
Murata
SWBST input capacitor
N/A
1
DIODE SCH PWR RECT 1.0 A
20 V SMT
MBR120LSFT3G
ON Semi
SWBST diode
22 µF
2
CAP CER 22 µF 10 V 20% X5R
0603
GRM188R61A226ME15D
Murata
SWBST output capacitors
Linear regulators
1.0 µF
3
CAP CER 1.0 µF 10 V 10% X7S
0402
GRM155C71A105KE11
Murata
VLDO1, VLDO2, VLDO3 and
VLDO4 input capacitors
2.2 µF
3
CAP CER 2.2 µF 10 V 10% X7S
0402
GRM155C71A225KE11
Murata
VLDO1, VLDO3, VCC_SD
output capacitors
10 µF
1
CAP CER 10 µF 10 V 20% X7T
0603
GRM188D71A106MA73
Murata
V33 and VCC_SD input capacitor
PF3000
112
NXP Semiconductors
BILL OF MATERIALS
Table 199. Bill of materials for -40 °C to 105 °C applications (continued)
Value
Qty
Description
Part#
Manufacturer
Component/Pin
4.7 µF
3
CAP CER 4.7 µF 10 V 10% X7S
0603
GRM188C71A475KE11
Murata
VLDO2, VLDO4, V33 output
capacitors
1.0 µF
4
CAP CER 1.0 µF 10 V 10% X7R
0402
GRM155C71A105KE11
Murata
VCORE, VCOREDIG,
VREFDDR, VINREFDDR
capacitors
0.22 µF
2
CAP CER 0.22 µF 10 V 10% X7R
0402
GRM155R71A224KE01
Murata
VCOREREF and coin cell output
capacitors
0.47 µF
1
CAP CER 0.47 µF 10 V 20% X5R
0201
GRM155R71A474KE01
Murata
VSNVS output capacitor
47 µF
4
CAP CER 47 µF 10 V 20% X7R
1210
GRM32ER71A476ME15
Murata
Front-end LDO capacitors for
VIN and VPWR.
2.2 µF
1
CAP CER 2.2 µF 10 V 10% X7S
0402
GRM155C71A225KE11
Murata
VIN input capacitor when not
using front-end LDO
0.1 µF
5
CAP CER 0.1 µF 10 V 10% X7S
0201
GRM033C71A104KE14
Murata
VDDIO, VHALF, VPWR, VIN
input capacitors (optional)
N/A
1
TRAN PMOS 11. A 12 V 12 SOT1220
PMPB15XP
NXP
External MOSFET
100 k
2
RES MF 100k 1/16 W 1% 0402
RC0402FR-07100KL
Yageo America
Pull-up resistors
4.7 k
2
RES MF 4.70k 1/20 W 1% 0201
RC0201FR-074K7L
Yageo America
I²C pull-up resistors
Miscellaneous
PF3000
NXP Semiconductors
113
THERMAL INFORMATION
9
Thermal information
9.1
Rating data
The thermal rating data of the packages has been simulated with the results listed in Thermal ratings. Junction to ambient thermal
resistance nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal
resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-JMA) is used for both junction-to-ambient on a
2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated
that the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.
9.2
Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RθJA x PD)
with:
TA = Ambient temperature for the package in °C
RθJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four
layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RθJB x PD) with
TB = Board temperature at the package perimeter in °C
RθJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
PF3000
114
NXP Semiconductors
PACKAGING
10
Packaging
10.1
Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing's document number. See the Thermal Characteristics section for specific thermal characteristics
for each package.
Table 200. Package drawing information
Package
Suffix
Package outline drawing number
48-pin QFN 7X7 mm - 0.5mm pitch
EP
98ASA00719D
48 QFN 7.0 mm x 7.0 mm WF-type (wettable flank)
ES
98ASA00933D
PF3000
NXP Semiconductors
115
PACKAGING
PF3000
116
NXP Semiconductors
PACKAGING
PF3000
NXP Semiconductors
117
PACKAGING
PF3000
118
NXP Semiconductors
PACKAGING
PF3000
NXP Semiconductors
119
PACKAGING
PF3000
120
NXP Semiconductors
REVISION HISTORY
11
Revision history
Revision
Date
1.0
11/2014
•
Initial release
2.0
2/2015
•
•
•
•
•
•
•
VREFDDR output accuracy spec re-formatted
Added typical performance waveforms
Corrected OTP option 1 set points
LDO current limit specifications updated
VPWR LDO output voltage accuracy specification updated
Updated register names of Extended Page 1 registers to maintain consistency throughout document
Added typical bill of materials
3.0
2/2015
•
•
Corrected Register INTSENSE0 - ADDR 0x07
Added orderable part numbers PC32PF3000A5EP and PC34PF3000A5EP
4.0
6/2015
•
•
•
•
•
•
•
•
•
•
Included i.MX Series processor
Redefined voltages for SW1A and SW1A/B
Corrected typographic errors
Improved bill of materials capacitors
Updated SW1A/B, SW1A, and SW1B Output Voltage Accuracy
Added note on LICELL for Operating Input Voltage
Improved temperature range to 105 °C
Updated ILIM max values for Linear regulators
VCOREDIG/VCOREREF tables updated
Updated LSL of ISW1BLIM to 2.4 A
5.0
6/2015
•
•
•
Replaced i.MX Series by i.MX 7
Added i.MX 6UL processor
Updated Bill of Materials Table 199
•
Added MC32PF3000A6EP, MC34PF3000A6EP, MC32PF3000A7EP, and MC34PF3000A7EP parts
to the Orderable Part Variations Table
Updated Table 42
Removed i.MX 6 DL note on Power Virus
Updated the definition of rated current for switchers and linear regulators
6.0
8/2015
Description of changes
•
•
•
•
•
3/2016
•
7.0
8/2016
9/2016
8.0
9.0
3/2017
8/2017
Added 98ASA00933D and the page 1 package image for wettable flank
Changed Table 2, pins 7, 10, 18, and 28, from Bypass with at least a 10 μF to Bypass with at least a
4.7 μF
Added PC33PF3000A0ES, PC33PF3000A3ES, PC33PF3000A4ES, PC33PF3000A5ES,
PC33PF3000A6ES, and PC33PF3000A7ES to Table 1
•
Changed PC33PF3000A0ES, PC33PF3000A3ES, PC33PF3000A4ES, PC33PF3000A5ES,
PC33PF3000A6ES, and PC33PF3000A7ES to MC parts in Table 1
•
Updated Table 66 LDO Control to accurately describe all modes
•
Added MC32PF3000A8EP and MC34PF3000A8EP parts to Table 1
•
•
Added new note (2) to Table 1
Updated VSW1AACC parameter in Table 7
•
•
Added OTP configuration for A8 to Table 42
Updated Table 80 (changed default value to 1)
•
Updated notes (47) and (49) as per 201707041I
PF3000
NXP Semiconductors
121
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products herein.
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specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
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© NXP B.V. 2017.
Document Number: PF3000
Rev. 9.0
8/2017