NXP Semiconductors
Data sheet: Advance Information
Document Number: PF3001
Rev. 4.0, 8/2017
Power management integrated
circuit (PMIC) for i.MX 7 and i.MX 6
SoloLite/SoloX/UltraLite processors
PF3001
The PF3001 is a SMARTMOS power management integrated circuit (PMIC)
designed specifically for always ON applications with the NXP i.MX 7 and i.MX
6 SoloLite/SoloX/UltraLite application processors. With up to three buck
converters, six linear regulators, RTC supply, and coin-cell charger, the PF3001
can provide power for a complete system, including applications processors,
memory, and system peripherals.
POWER MANAGEMENT
Features:
• Three adjustable high efficiency buck regulators: 2.75 A, 1.5 A, 1.25 A
• Selectable modes: PWM, PFM, APS
• Programmable output voltage, PWM switching frequency, current limit
• Six adjustable general purpose linear regulators
•
•
•
•
EP SUFFIX
98ASA00719D
48 QFN 7.0 X 7.0
Applications:
• IPTV
• Set top boxes
• POS terminals
• Industrial control
• Medical monitoring
• Home automation/security/energy management
Input voltage range: 2.8 V to 4.5 V or 3.7 V to 5.5 V
I2C control
Coin cell charger and always ON RTC supply
-40 °C to +125 °C Operating Junction Temperature
i.MX
PF3001
Switching regulators
SW3
ES SUFFIX
98ASA00933D
48 QFN 7.0 X 7.0
DDR MEMORY
DDR MEMORY
INTERFACE
0.90 – 1.65 V, 1.5A
Processor
ARM Core
SW1
0.70 – 3.30 V, 2.75A
SW2
1.50 – 1.85 V
or 2.5 -3.3 V, 1.25A
Processor SOC
SD-MMC/
NAND Mem.
SATA
HDD
RESETBMCU
PWRON
Li CELL
Charger
SATA - FLASH
NAND - NOR
Interfaces
Parallel control /
GPIOs
SD_VSEL
INTB
2
External AMP
Microphones
Speakers
Audio
Codec
I2C
IC
Sensors
Linear regulators
VLDO1 1.8 – 3.3 V,
VLDO2 0.8 – 1.55 V, 250mA
VCC_SD 1.8 – 1.85 V
or 2.85 – 3.3 V, 100mA
V33
2.85 -3.3 V,
350mA
VLDO3 1.8 – 3.3 V,
100mA
VLDO4 1.8 -3.3 V,
350mA
COINCELL
Camera
100mA
Main Supply
2.8 - 5.5 V
WAM
GPS/MIPI
LVDS
Display
Cluster/
HUD
GPS
MIPI
Micro PCIe
HDMI
USB
Ethernet
CAN
Front USB
POD
Rear Seat
Infotainment
Figure 1. PF3001 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2017.
Camera
Rear USB
POD
Table of Contents
1
2
3
4
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1 Control logic and interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.2 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3.4 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.5 Optional front-end input LDO regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.6 Internal core voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.7 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.8 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.9 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5.1 State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.5.3 Performance characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.6 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.6.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.6.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.6.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.6.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.6.5 Specific registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.6.6 Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.1Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PF3001
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
The PF3001 is available with pre-programmed OTP memory configurations. The devices are identified using the program codes from
Table 1. Details of the start-up programming for each device can be found in Table 32.
Table 1. Orderable part variations
Part number
Temperature (TA)
Package
Programming options
MC32PF3001A1EP
1 (i.MX 7 with DDR3L)
MC32PF3001A2EP
2 (i.MX 7 with LPDDR3)
MC32PF3001A3EP
MC32PF3001A4EP
MC32PF3001A5EP
-40 °C to 85 °C
(For use in consumer
applications)
3 (i.MX 6SX with DDR3L)
98ASA00719D, 48 QFN 7.0 mm x
7.0 mm with exposed pad
4 (i.MX 6SX with DDR3)
6 (i.MX 6UL with LPDDR2)
MC32PF3001A7EP
7 (i.MX 6UL with DDR3L)
MC33PF3001A7ES
-40 °C to 105 °C
(For use in automotive
applications)
98ASA00933D, 48 QFN 7.0 mm x
7.0 mm WF-type (wettable flank)
6 (i.MX 6UL with LPDDR2)
7 (i.MX 6UL with DDR3L)
MC34PF3001A1EP
1 (i.MX 7 with DDR3L)
MC34PF3001A2EP
2 (i.MX 7 with LPDDR3)
MC34PF3001A3EP
MC34PF3001A4EP
MC34PF3001A5EP
-40 °C to 105 °C
(For use in industrial
applications)
(1)
5 (i.MX 6SL with LPDDR2)
MC32PF3001A6EP
MC33PF3001A6ES
Notes
(1)
3 (i.MX 6SX with DDR3L)
98ASA00719D, 48 QFN 7.0 mm x
7.0 mm with exposed pad
4 (i.MX 6SX with DDR3)
(1)
5 (i.MX 6SL with LPDDR2)
MC34PF3001A6EP
6 (i.MX 6UL with LPDDR2)
MC34PF3001A7EP
7 (i.MX 6UL with DDR3L)
Notes
1. For Tape and Reel add an R2 suffix to the part number.
PF3001
NXP Semiconductors
3
GENERAL DESCRIPTION
2
General description
The PF3001 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX series of multi-media
application processors. It is also capable of providing full power solutions to i.MX 6SL, 6SX, 6UL, and i.MX7processors.
2.1
Features
This section summarizes the PF3001 features.
• Input voltage range to PMIC: 2.8 V to 4.5 V, or 3.7 V to 5.5 V (2)
• Buck regulators
• SW1, 2.75 A; 0.7 V to 1.425 V, 1.8 V, 3.3 V
• SW2, 1.25 A; 1.50 V to 1.85 V, or 2.50 V to 3.30 V
• SW3, 1.5 A; 0.90 V to 1.65 V
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable PWM switching frequency
• LDOs
• VCC_SD, 1.8 V to 1.85 V, or 2.85 V to 3.30 V, 100 mA based on SD_VSEL
• V33, 2.85 V to 3.30 V, 350 mA
• VLDO1, 1.8 V to 3.3 V, 100 mA
• VLDO2, 0.80 V to 1.55 V, 250 mA
• VLDO3, 1.8 V to 3.3 V, 100 mA
• VLDO4, 1.8 V to 3.3 V, 350 mA
• Always ON RTC regulator/switch VSNVS 3.0 V, 1.0 mA
• Battery backed memory including coin cell charger
• I2C interface
Notes
2. 2.8 V to 4.5 V when VIN is used at input. 3.7 V to 5.5 V when VPWR is used as input.
PF3001
4
NXP Semiconductors
GENERAL DESCRIPTION
2.2
Functional block diagram
PF3001 functional internal block diagram
Power generation
Fixed OTP configuration
Voltage and PWRON
configuration fixed
DVS speed fixed
Sequence and
timing fixed
Phasing and
frequency fixed
Switching regulators
SW1
(0.7 V to 1.425 V,1.8 V,
3.3 V, 2.75 A)
Linear regulators
VCC_SD
(1.80 V to 1.85 V, 100 mA)
or (2.85 V to 3.3 V, 100 mA)
V33
Bias & references
Internal core voltage reference
SW2
(1.50 V to 1.85 V, 1.25 A)
or (2.50 V to 3.30 V, 1.25 A)
( 2.85 V to 3.30 V, 350 mA)
VLDO1
(1.8 V to 3.3 V, 100 mA)
SW3
Logic and control
Parallel MCU interface
(0.90 V to 1.65 V, 1.5 A)
Regulator control
I2C communication & registers
VLDO2
(0.80 V to 1.55 V, 250 mA)
VLDO3
(1.8 V to 3.3 V, 100 mA)
VLDO4
(1.8 V to 3.3 V, 350 mA)
Fault detection and protection
Thermal
Current limit
VPWR front end LDO overvoltage indicator
VSNVS
(1.0 V to 3.0 V, 1.0 mA)
RTC supply with coin cell
charger
Figure 2. PF3001 functional block diagram
PF3001
NXP Semiconductors
5
INTERNAL BLOCK DIAGRAM
3
Internal Block Diagram
PF3001
VLDO1
VLDO1IN
100 mA
VLDO1
VLDO2
VLDO2IN
250 mA
VLDO2
VLDO3
VLDO34IN
100 mA
VLDO3
SW1
VLDO4
VLDO4
2.75 A
Buck
350 mA
O/P
Drive
Core Control logic
1.8 V/3.15 V
100 mA
Initialization State Machine
SW2
V33
2.85 V - 3.30 V
350 mA
V33
SW1IN
GNDREF1
VCC_SD
VCC_SD
SW1FB
SW1LX
O/P
Drive
SW2LX
SW2IN
SW2FB
1.25 A
Buck
GNDREF2
Supplies
Control
OTP
VIN2
SW3FB
ICTEST2
CONTROL
I2C
Interface
VDDIO
SCL
SW3
1.5 A
Buck
SDA
O/P
Drive
SW3IN
SW3LX
GNDREF2
DVS
I2C Register
map
VCOREDIG
VCOREREF
Trim-In-Package
Reference
Generation
VCORE
Clocks and
resets
GNDREF
VPWR
LDOG
VREF
LDO
Clocks
32 kHz and 16 MHz
VIN
Li Cell
Charger
LICELL
Best
of
Supply
INTB
RESETBMCU
SD_VSEL
GND
PWRON
ICTEST1
VSNVS
VSNVS
Figure 3. PF3001 simplified internal block diagram
PF3001
6
NXP Semiconductors
37 NC
38 VIN2
39 ICTEST2
40 GNDREF
41 VCORE
42 VIN
48 PWRON
Transparent top view
43 VCOREDIG
Pinout diagram
44 VCOREREF
4.1
45 SDA
Pin connections
47 VDDIO
4
46 SCL
PIN CONNECTIONS
INTB
1
36 LICELL
SD_VSEL
2
35 NC
RESETBMCU
3
34 VSNVS
GND
4
33 VCC_SD
ICTEST1
5
32 V33
SW1FB
6
31 VPWR
EP
NC
11
26 GNDREF2
GNDREF1
12
25 NC
GND 24
27 SW3FB
NC 23
10
VLDO4 22
SW1IN
VLDO34IN 21
28 SW3IN
VLDO3 20
9
SW2FB 19
SW1LX
SW2IN 18
29 SW3LX
SW2LX 17
8
VLDO2IN 16
SW1LX
VLDO2 15
30 LDOG
VLDO1 14
7
VLDO1IN 13
SW1IN
Figure 4. PF3001 pinout diagram
PF3001
NXP Semiconductors
7
PIN CONNECTIONS
4.2
Pin definitions
Table 2. Pin definitions
Pin number
Pin name
Pin
function
Type
1
INTB
O
Digital
Open drain interrupt signal to processor
2
SD_VSEL
I/O
Digital
Input from i.MX processor to select VCC_SD regulator voltage
• SD_VSEL=0, VCC_SD = 2.85 V to 3.3 V
• SD_VSEL= 1, VCC_SD = 1.8 V to 1.85 V
3
RESETBMCU
O
Digital
Open drain reset output to processor
4
GND
I
GND
Ground reference. Connect to ground.
5
ICTEST1
I
Digital and
Analog
6
SW1FB (3)
I
Analog
SW1 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitance or near the load, if possible for best regulation
7
SW1IN (3)
I
Analog
Input to SW1 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
8
SW1LX (3)
O
Analog
Switcher 1 switch node connection. Connect to SW1LX and connect to SW1 inductor
9
SW1LX
(3)
O
Analog
Switcher 1 switch node connection. Connect to SW1LX and connect to SW1 inductor
10
SW1IN (3)
I
Analog
Input to SW1 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
11
NC
–
Reserved
Definition
Reserved pin. Connect to GND in application
Leave floating
Ground reference for SW1. Connect to GND. Keep away from high current ground
return paths
12
GNDREF1
GND
GND
13
VLDO1IN
I
Analog
VLDO1 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible
14
VLDO1
O
Analog
VLDO1 regulator output. Bypass with a 2.2 μF ceramic output capacitor
15
VLDO2
O
Analog
VLDO2 regulator output. Bypass with a 4.7 μF ceramic output capacitor
16
VLDO2IN
I
Analog
VLDO2 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible
17
SW2LX (3)
O
Analog
Switcher 2 switch node connection. Connect to SW2 inductor
18
SW2IN (3)
I
Analog
Input to SW2 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
19
SW2FB (3)
I
Analog
SW2 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
20
VLDO3
O
Analog
VLDO3 regulator output. Bypass with a 2.2 μF ceramic output capacitor
21
VLDO34IN
I
Analog
VLDO3 and VLDO4 input supply. Bypass with a 1.0 μF decoupling capacitor as close to
the pin as possible
22
VLDO4
O
Analog
VLDO4 regulator output. Bypass with a 2.2 μF ceramic output capacitor
23
NC
–
Reserved
24
GND
GND
GND
25
NC
–
Reserved
26
GNDREF2
GND
GND
Reference ground for SW2 and SW3 regulators. Connect to GND. Keep away from high
current ground return paths
27
SW3FB (3)
I
Analog
SW3 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
28
SW3IN (3)
I
Analog
Input to SW3 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
Leave floating
Ground reference. Connect to ground. Keep away from high current ground return paths
Leave floating
PF3001
8
NXP Semiconductors
PIN CONNECTIONS
Table 2. Pin definitions (continued)
Pin number
Pin name
Pin
function
Type
29
SW3LX (3)
O
Analog
Switcher 3 switch node connection. Connect the SW3 inductor
30
LDOG
O
Analog
Connect to gate of front-end LDO external pass P-MOSFET. Leave floating if VPWR
LDO is not used
31
VPWR
I
Analog
Input to optional front-end VPWR LDO for systems with input voltage > 4.5 V
32
V33
O
Analog
V33 regulator output. Bypass with a 4.7 μF ceramic output capacitor
33
VCC_SD
O
Analog
Output of VCC_SD regulator. Bypass with a 2.2 μF ceramic output capacitor.
34
VSNVS
O
Analog
VSNVS regulator/switch output. Bypass with 0.47 μF capacitor to ground.
35
NC
–
Reserved
36
LICELL
I/O
Analog
37
NC
–
Reserved
38
VIN2
I
Analog
39
ICTEST2
I
Digital &
Analog
40
GNDREF
GND
GND
41
VCORE
O
Analog
Internal analog core supply. Bypass with 1.0 μF capacitor to ground
42
VIN
I
Analog
Main IC supply. Bypass with 1.0 μF capacitor to ground. Connect to system input supply
if voltage ≤ 4.5 V. Connect to drain of external PFET when VPWR LDO is used for
systems with input voltage > 4.5 V
43
VCOREDIG
O
Analog
Internal digital core supply. Bypass with 1.0 μF capacitor to ground
44
VCOREREF
O
Analog
Main band gap reference. Bypass with 220 nF capacitor to ground
45
SDA
I/O
Digital
I2C data line (open drain). Pull up to VDDIO with a 4.7 kΩ resistor
46
SCL
I
Digital
I2C clock. Pull up to VDDIO with a 4.7 kΩ resistor
47
VDDIO
I
Analog
Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor. Connect to 1.7 V to 3.6 V
supply. Ensure VDDIO is always lesser than or equal to VIN
48
PWRON
I
Digital
Power ON/OFF input from processor
-
EP
GND
GND
Expose pad. Functions as ground return for buck and boost regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal dissipation
Definition
Leave floating
Coin cell supply input/output. Bypass with 0.1 μF capacitor. Connect to optional coin
cell.
Leave floating
Input to VCC_SD, V33 regulators. Connect to VIN rail and bypass with 10 μF capacitor
Reserved pin. Connect to GND in application
Ground reference for IC core circuitry. Connect to ground. Keep away from high current
ground return paths
Notes
3. Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to VIN with a 0.1 μF bypass capacitor.
PF3001
NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
5
General product characteristics
5.1
Maximum ratings
Table 3. Maximum voltage ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Description
Value
Unit
Notes
(4)
Electrical ratings
VPWR, ICTEST1, ICTEST2, LDOG
–
-0.3 to 7.5
V
VIN, VIN2, VLDO1IN, SW1IN, SW2IN, SW3IN,
SW1LX, SW2LX, SW3LX
–
-0.3 to 4.8
V
INTB, SD_VSEL, RESETBMCU, SW1FB,
SW2FB, SW3FB, VLDO1, VLDO2IN, VLDO3,
VLDO34IN, VLDO4, V33, VCC_SD, VSNVS,
LICELL, VCORE, SDA, SCL, VDDIO, PWRON
–
-0.3 to 3.6
V
VLDO2 linear regulator output
-0.3 to 2.5
V
VCOREDIG
Digital core supply voltage output
-0.3 to 1.65
V
VCOREREF
Bandgap reference voltage output
-0.3 to 1.5
V
±2000
±500
V
VLDO2
VESD
ESD ratings
• Human body model
• Charge device model
(5)
Notes
4. 7.5 V Maximum DC voltage rated.
5. ESD testing is performed in accordance with the Human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge device model
(CDM), Robotic (CZAP = 4.0 pF).
PF3001
10
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
5.2
Thermal characteristics
Table 4. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Thermal ratings
TA
Ambient operating temperature range
• Industrial version
• Consumer version
-40
-40
105
85
°C
TJ
Operating junction temperature range
-40
125
°C
Storage temperature range
-65
150
°C
–
(8)
°C
(7) (8)
TST
TPPRT
Peak package reflow temperature
(6)
QFN48 thermal resistance and package dissipation ratingS
RθJA
Junction to ambient, natural convection
• Four layer board (2s2p)
• Eight layer board (2s6p)
–
–
24
15
°C/W
(9) (10)
(11)
RθJB
Junction to Board
–
11
°C/W
(12)
RΘJCBOTTOM
Junction to case bottom
–
1.4
°C/W
(13)
ΨJT
Junction to package top
• Natural convection
–
1.3
°C/W
(14)
Notes
6. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See thermal
protection thresholds for thermal protection features.
7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
8. NXP's package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
9. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
10. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
11. Per JEDEC JESD51-6 with the board horizontal.
12. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
14. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC
JESD51-2. When Greek letters (Ψ) are not available, the thermal characterization parameter is written as Psi-JT.
PF3001
NXP Semiconductors
11
GENERAL PRODUCT CHARACTERISTICS
5.3
Current consumption
The current consumption of the individual blocks is described in detail in the following table.
Table 5. Current consumption summary
TA= -40 °C to 105 °C, VPWR= 0 V (External pass FET is not populated), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VPWR = 0 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode
PF3001 conditions
Coin Cell
VSNVS from LICELL, All other blocks
off, VIN = 0.0 V
System conditions
Typ.
Max.
Unit
Notes
No load on VSNVS
4.0
7.0
μA
(15) (16)
Off
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 kHz RC on
All other blocks off
VIN ≥ UVDET
No load on VSNVS, PMIC able to
wake-up
16
25
μA
(15) (16)
ON
VSNVS from VIN
SW1 in APS
SW2 in APS
SW3 in APS
Trimmed 16 MHz RC enabled
Trimmed reference active, VLDO1-4
enabled
V33 enabled
VCC_SD enabled
No load on any of the regulators.
1.2
mA
Notes
15. At 25 °C only.
16. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
PF3001
12
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
5.4
Electrical characteristics
Table 6. Electrical characteristics – front-end input LDO
All parameters are specified at TA = -40 °C to 105 °C, VPWR = 5.0 V, VIN = 4.4 V, IVIN = 300 mA, typical external component values, unless
otherwise noted. Typical values are characterized at VPWR = 5.0 V, VIN = 4.4 V, IVIN = 300 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
4.6
3.7
–
–
5.5
4.6
V
(17)
Front end input LDO (VPWR LDO)
VPWR
Operating input voltage
• In regulation
• In dropout operation
VIN
On mode output voltage, 4.6 V < VPWR < 5.5 V,
0.0 mA < IVIN < 3000 mA
4.3
4.4
4.55
V
IVIN
Operating load current at VIN, 3.7 V < VPWR < 5.5 V
0.0
–
3.0
A
–
5.0
10
mA
ILDOGQ
ON mode quiescent current, No load,
Low power mode output voltage, 4.6 V < VPWR < 5.5 V
0.0 mA < IVIN < 1.0 mA
3.7
4.5
V
Off mode output voltage, (CL = 100 μF) 4.6 V < VPWR < 5.5 V,
0.0 mA < IVIN < 35 μA
3.2
4.8
V
VPWRUV
VPWR undervoltage threshold (upon undervoltage condition the
external pass FET is turned off)
3.1
–
3.7
V
VPWROV
VPWR overvoltage threshold (upon overvoltage condition interrupt is
asserted at INTB)
5.5
–
6.5
V
VIN
VPWROFFMODE
IVINUVILIMIT
VPWR LDO current limit under VIN short-circuit (VIN < UVDET)
–
–
300
mA
IVINLEAKAGE
Reverse leakage current from VIN to VPWR, No external pass FET,
VPWR is grounded, device is in OFF state
–
–
1.0
µA
VPWR LDO Off mode quiescent current
–
–
75
μA
IVPWROFF
(18)
Notes
17. While the front end LDO can handle spikes up to 7.5 V at VPWR for as long as 200 µs, the circuit is not expected to be continuously operated
when VPWR is above 5.5 V.
18. This specification gives the leakage current in the VPWR LDO block. Total OFF mode current includes the quiescent current from the other blocks
as specified in Table 5.
PF3001
NXP Semiconductors
13
GENERAL PRODUCT CHARACTERISTICS
Table 7. Static electrical characteristics – SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, typical external component
values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
(19)
Switch mode supply SW1
VSW1IN
Operating input voltage
2.8
–
4.5
V
VSW1
Nominal output voltage
–
Table 40
–
V
-25
25
mV
-25
25
mV
45
mV
-6.0
6.0
%
-6.0
6.0
%
Output voltage accuracy
• PWM, APS, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 2.75 A
0.7 V ≤ VSW1 ≤ 1.2 V
• PFM, APS, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 2.75A
1.225 V < VSW1 < 1.425 V
• PFM, steady state, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 150 mA
1.8 V ≤ VSW1 ≤ 1.425 V
• PWM, APS, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 2.75A
1.8 V < VSW1 < 3.3 V
• PFM, steady state, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 150 mA
1.8 V ≤ VSW1 ≤ 3.3 V
VSW1ACC
ISW1
ISW1Q
•
Rated output load current,
2.8 V ≤ VSW1IN ≤ 4.5 V, 0.7 V < VSW1 < 1.425 V, 1.8 V, 3.3 V
Quiescent current
• PFM mode
• APS mode
-45
–
–
–
2750
mA
–
–
22
300
–
–
µA
3.5
2.6
5.5
4.0
7.5
5.4
A
ISW1LIM
Current limiter peak current detection , current through inductor
• SW1ILM = 0 (default)
• SW1ILM = 1
ΔVSW1
Output ripple
–
5.0
–
mV
Discharge resistance
–
600
–
Ω
RSW1DIS
Notes
19. The maximum operating input voltage is 4.55 V when VPWR LDO is used
Table 8. Dynamic electrical characteristics - SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, typical external component
values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up Overshoot, ISW1 = 0 mA, slew rate = 25 mV/4 μs,
VIN = VSW1IN = 4.5 V, VSW1 = 1.425 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW1 = 0 mA,
slew rate = 25 mV/4 μs, VIN = VSW1IN = 4.5 V, VSW1 = 1.425 V
–
–
500
µs
Notes
Switch mode supply SW1 (single phase)
VSW1OSH
tONSW1
PF3001
14
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 9. Static electrical characteristics – SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(20), (21)
Switch mode supply SW2
VSW2IN
Operating Input Voltage
2.8
–
4.5
V
VSW2
Nominal output voltage
–
Table 42
–
V
-3.0
-6.0
–
–
3.0
6.0
%
-6.0
-6.0
–
–
6.0
6.0
–
–
1250
ISW2Q
Quiescent current
• PFM mode
• APS mode (low output voltage settings, CTL_SW2_HL = 0)
• APS mode (high output voltage settings, CTL_SW2_HL = 1)
–
–
–
23
145
305
–
–
–
ISW2LIM
Current limiter peak current detection, current through inductor
• SW2ILM = 0 (default)
• SW2ILM = 1
1.625
1.235
2.5
1.9
3.375
2.565
A
ΔVSW2
Output ripple
–
5.0
–
mV
RONSW2P
SW2 P-MOSFET RDS(on) at VIN = VSW2IN = 3.3 V
–
215
245
mΩ
RONSW2N
SW2 N-MOSFET RDS(on) at VSW2IN = VSW2IN = 3.3 V
–
258
326
mΩ
ISW2PQ
SW2 P-MOSFET leakage current, VIN = VSW2IN = 4.5 V
–
–
10.5
µA
ISW2NQ
SW2 N-MOSFET leakage current, VIN = VSW2IN = 4.5 V
–
–
3.0
µA
RSW2DIS
Discharge resistance during OFF mode
–
600
–
Ω
VSW2ACC
ISW2
Output voltage accuracy
• PWM, APS, 2.8 V ≤ VSW2IN ≤ 4.5 V, 0 ≤ ISW2 ≤ 1.25 A
• 1.50 V ≤ VSW2 ≤ 1.85 V
• 2.5 V ≤ VSW2 ≤ 3.3 V
• PFM, 2.8 V ≤ VSW2IN ≤ 4.5 V, 0 ≤ ISW2 ≤ 50 mA
• 1.50 V ≤ VSW2 ≤ 1.85 V
• 2.5 V ≤ VSW2 ≤ 3.3 V
Rated output load current,
2.8 V < VSW2IN < 4.5 V, 1.50 V < VSW2 < 1.85 V, 2.5 V < VSW2 < 3.3 V
mA
(22)
µA
Notes
20. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
21. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any PF3001 regulator, or external system supply.
22. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW2IN - VSW2) = ISW2*
(DCR of Inductor +RONSW2P + PCB trace resistance).
Table 10. Dynamic electrical characteristics - SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW2 = 0.0 mA, slew rate = 25 mV/4 μs,
VIN = VSW2IN = 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW2 = 0.0 mA,
slew rate = 25 mV/4 μs, VIN = VSW2IN = 4.5 V
–
–
500
µs
Notes
Switch Mode Supply SW2
VSW2OSH
tONSW2
PF3001
NXP Semiconductors
15
GENERAL PRODUCT CHARACTERISTICS
Table 11. Static electrical characteristics – SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
(23)
Switch mode supply SW3
VSW3IN
Operating input voltage
2.8
–
4.5
V
VSW3
Nominal output voltage
–
Table 44
–
V
-3.0
–
3.0
-6.0
–
6.0
–
–
1500
mA
–
–
50
150
–
–
µA
1.95
1.45
3.0
2.25
4.05
3.05
A
VSW3ACC
ISW3
ISW3Q
Output voltage accuracy
• PWM, APS, 2.8 V < VSW3IN < 4.5 V, 0 < ISW3 < 1.5 A,
0.9 V < VSW3 < 1.65 V
• PFM, steady state (2.8 V < VSW3IN < 4.5 V, 0 < ISW3 < 50 mA),
0.9 V < VSW3 < 1.65 V
Rated output load current, 2.8 V < VSW3IN < 4.5 V,
0.9 V < VSW3 < 1.65 V, PWM, APS mode
Quiescent current
• PFM mode
• APS mode
%
ISW3LIM
Current limiter peak current detection, current through inductor
• SW3ILIM = 0 (default)
• SW3ILIM = 1
ΔVSW3
Output ripple
–
5.0
–
mV
RONSW3P
SW3 P-MOSFET RDS(on) at VIN = VSW3IN = 3.3 V
–
205
235
mΩ
RONSW3N
SW3 N-MOSFET RDS(on) at VIN = VSW3IN = 3.3 V
–
250
315
mΩ
ISW3PQ
SW3 P-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
12
µA
ISW3NQ
SW3 N-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
4.0
µA
RSW3DIS
Discharge resistance during off mode
–
600
–
Ω
(24)
Notes
23. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
24. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW3IN - VSW3) =
ISW3* (DCR of Inductor +RONSW3P + PCB trace resistance).
Table 12. Dynamic Electrical Characteristics - SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW 3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Symbol
VSW3OSH
tONSW3
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW3 = 0.0 mA, slew rate = 25 mV/4 μs, VIN =
VSW3IN = 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW3 = 0 mA,
slew rate = 25 mV/4 μs, VIN = VSW3IN = 4.5 V
–
–
500
µs
Notes
PF3001
16
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 13. Static electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating input voltage
• Valid coin cell range
• Valid VIN
1.8
2.25
–
–
3.3
4.5
V
(25)
ISNVS
Operating load current, VINMIN < VIN < VINMAX
1.0
–
1000
μA
VSNVS
Output voltage
-5.0
• 5.0 μA < ISNVS < 1000 μA (OFF), 3.20 V < VIN < 4.5 V
-5.0
• 5.0 μA < ISNVS < 1000 μA (ON), 3.20 V < VIN < 4.5 V
• 5.0 μA < ISNVS < 1000 μA (coin cell mode), 2.84 V < VCOIN < 3.3 V VCOIN-0.10
3.0
3.0
–
7.0
5.0
VCOIN
%
%
V
–
–
110
mV
1100
–
6750
μA
Operating input voltage, valid coin cell range
1.8
–
3.3
V
Operating load current
1.0
–
1000
μA
–
–
100
Ω
VSNVS
VIN
VSNVSDROP
ISNVSLIM
Dropout voltage, 2.85 V < VIN < 2.9 V, 1.0 μA < ISNVS < 1000 μA
Current limit, VIN > VTH1
VSNVS DC, switch
VLICELL
ISNVS
RDSONSNVS
Internal switch RDS(on), VCOIN = 2.6 V
Notes
25. The maximum operating input voltage is 4.55 V when VPWR LDO is used
Table 14. Dynamic electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, typical external component values, unless
otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(26),(27)
VSNVS
VSNVSTON
Turn-on time (load capacitor, 0.47 μF), from VIN = VTH1 to 90% of
VSNVS, VCOIN = 0.0 V, ISNVS = 5.0 μA
–
–
24
ms
VSNVSOSH
Start-up overshoot, ISNVS = 5.0 μA
–
40
70
mV
VSNVSLOTR
Transient load response, 3.2 < VIN ≤ 4.5 V, ISNVS = 100 to 1000 μA
2.8
–
–
V
VTL1
VIN falling threshold (VIN powered to coin cell powered)
2.45
2.70
3.05
V
VTH1
VIN rising threshold (coin cell powered to VIN powered)
2.50
2.75
3.10
V
VIN threshold hysteresis for VTH1-VTL1
5.0
–
–
mV
Output voltage during crossover, VCOIN > 2.9 V, switch to LDO:
VIN > VTH1, ISNVS = 100 μA, LDO to switch: VIN < VTL1,
ISNVS = 100 μA
2.45
–
–
V
VHYST1
VSNVSCROSS
Notes
26. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to 3.0 V.
27.
From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.
PF3001
NXP Semiconductors
17
GENERAL PRODUCT CHARACTERISTICS
Table 15. Static electrical characteristics - VLDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
VLDO1NOM
+0.250
–
–
4.5
4.5
V
(28), (29)
VLDO1 linear regulator
VLDO1IN
Operating input voltage
• 1.8 V ≤ VLDO1NOM ≤ 2.5 V
• 2.6 V ≤ VLDO1NOM ≤ 3.3 V
VLDO1NOM
Nominal output voltage
–
Table 47
–
V
ILDO1
Operating load current
0.0
–
100
mA
VLDO1TOL
Output voltage tolerance, VLDO1INMIN < VLDO1IN < 4.5 V, 0.0 mA <
ILDO1 < 100 mA, VLDO1 = 1.8 V to 3.3 V
-3.0
–
3.0
%
ILDO1Q
Quiescent current, no load, change in IVIN, when VLDO1 enabled
–
13
–
μA
122
167
280
mA
ILDO1LIM
Current limit, ILDO1 when VLDO1 is forced to VLDO1NOM/2
Notes
28. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
29. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any PF3001 regulator, or external system supply.
Table 16. Dynamic electrical characteristics - VLDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
35
52
40
60
–
–
dB
–
–
–
-114
-129
-135
-102
-123
-130
Notes
VLDO1 linear regulator
PSRRVLDO1
PSRR, ILDO1 = 75 mA, 20 Hz to 20 kHz
• VLDO1 = 1.8 V to 3.3 V, VLDO1IN = VLDO1INMIN + 100 mV
• VLDO1 = 1.8 V to 3.3 V, VLDO1IN = VLDO1NOM + 1.0 V
Output noise density, VLDO1IN = VLDO1INMIN, ILDO1 = 75 mA
NOISEVLDO1
• 100 Hz to
