MC34SB0800AE

NXP Semiconductors Daya Sheet:Advance Information Document Number: MC34SB0800 Rev. 3.0, 8/2016 Fully integrated octal valve controller system on chip SB0800 The SB0800 device is a valves and pump controller system designed for use in harsh industrial environments. INDUSTRIAL CONTROLLER CHIP It has eight high-current low-side drivers for use with solenoid valves, and highside gate drivers for use with controlling two external N-channel MOSFETs, for DC motor and a master relay for solenoid coils. Alongside this, the SB0800 has three analog to digital converters, plus a low-side driver allowing drive resistive charges. The SB0800 boosts an internal charge pump, permitting the high-side drivers to use inexpensive N-channel MOSFETs. The digital I/O pins can be configured for both 5.0 V and 3.3 V levels for easy connection to any microprocessor. The SB0800 uses standard SPI protocol communication. The SB0800 is a perfect solution for hydraulic and pneumatic applications. This device is powered by SMARTMOS technology. Features • Operating voltage 6.0 V to 36 V • Eight valves control • Four current regulated valves up to 2.25 A (5.0 kHz) • Four PWMed valves up to 5.0 A (5.0 kHz) • High-side predriver for valves protection • Pump motor predriver up to 500 Hz PWM • 16-bit SPI interface with watchdog • Three 10-bit ADC channels • High-side driver for general purpose (RDS(on) 1.0 Ω) • Low-side driver for resistive charge (RDS(on) 14.0 Ω) • Die temperature warning • Supervision AE SUFFIX (PB-FREE) 98ASA10763D 64-PIN LQFP-EP Applications Industrial Controller • Spot Welding • Dialysis machines • Fluid Coating • Blood pressure • Temperature Control • Soda dispensers • Brake Pressure • Laser Cutting • Heavy equipment and construction machinery • Bottle Moulding • Fork lifts • Filling Pressure • 3D Printer • Oxygen Concentrator • Water control system for irrigation (connected to farm tractor) • Medical test equipment • Food control in animal farm MC34SB0800 VPWR External 5.0V Regulator DOSV VINT_A VCC5 VINT_D P53_CFG VPWR VPWR RSTB VPWR SO SI CSB SCLK CP HD_D HD_G HD_S LD NC M Figure 1. SB0800 simplified 5.0 V application diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © 2016 NXP B.V. VPWR PD_D PD_G PD_S GND_D Solenoid coil LSD5 LSD6 LSD7 LSD8 HS VPWR ADINx GND_A 4 3 LSD1 LSD2 LSD3 LSD4 GND_P0,1...5 Solenoid coil MCU 1 Orderable parts This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.nxp.com and perform a part number search for the following device numbers. Table 1. Orderable part variations Part number Temperature (TA) Package Description Notes 34SB0800 octal valves and pump controller system on chip for industrial MC34SB0800AE -40 °C to 125 °C 10 x 10, 64 LQFP-EP • Four PWMed valve controls and four current regulated valve controls • Safe switch control • Pump motor control up to 500 Hz • High-side driver for general purpose • Low-side FET for resistive loads (1) Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. SB0800 2 NXP Semiconductors Table of Contents 1 2 3 4 5 6 7 8 9 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 Thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 Logical inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 High-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 Pump motor pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 Low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 Low-side driver for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6 Analog to digital converter (x3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 High-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.8 Monitoring module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.9 Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.10 SPI and data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SB0800 NXP Semiconductors 3 2 Internal block diagram VCC5 VPWR P53_CFG Internal Power Supply Charge Pump CP PD_D DOSV VINT_A VINT_D RSTB Supervision HD_S LSD1 LSD2 LSD3 LSD4 LSD5 LSD6 LSD7 LSD8 PD_G PD_S Safe MOSFET Predriver 16 Bit SPI Decoding / Encoding Registers CSB SCLK SO SI Current Regulation Or PWM LSDx (x4 ch) ADC (x3 ch) ADINx HD_D HD_G Pump Motor Predriver PWM LSDx (x4 ch) GND_A GND_D High-side Driver HS Low-side Driver LD GND_Px EP Figure 2. SB0800 simplified internal block diagram SB0800 4 NXP Semiconductors Pin connections 3.1 Pinout diagram P53_CGF 3 Figure 3. SB0800 64-pin LQFP-EP pinout diagram SB0800 NXP Semiconductors 5 3.2 Pin definitions Table 2. SB0800 pin definitions Pin number Pin name 1 RSTB Reset Reset PIN external pull-up 2 GND_P0 Supply Power Ground 0 (4) no no 4 GND_P1 Supply Power Ground 1 no no (4) 5, 6 LSD1 Low-side Driver for Current Regulated & Open Drain Output for Low-side Driver 1 PWMed Valves no no (2) 7, 8 LSD2 Low-side Driver for Current Regulated & Open Drain Output for Low-side Driver 2 PWMed Valves no no (2) 9, 10 LSD3 Low-side Driver for Current Regulated & Open Drain Output for Low-side Driver 3 PWMed Valves no no (2) 11, 12 LSD4 Low-side Driver for Current Regulated & Open Drain Output for Low-side Driver 4 PWMed Valves no no (2) 13 GND_P2 Supply Power Ground 2 no no (4) 14 SCLK SPI SPI Interface Clock Input no no SI SPI SPI Interface Digital Input no no CSB SPI SPI Interface Chip Interface no no Low-side Driver Open Drain Output for Low-side no no Charge Pump Charge Pump Output. For internal use, connect a storage capacitor of > 68 nF to VPWR. no no Supply Supply PIN connect to battery through reverse diode no no High-side Driver for General Purpose (optional) High-side driver for general purpose no no 15 16 18 LD Pin function Definition DOSV = 5.0 V DOSV = 3.3 V 24 CP 25 VPWR 26 HS 28 PD_G Motor Pump Driver Gate Output to Control Pump Motor FET Connect to gate of external pump motor FET no no 29 PD_S Motor Pump Driver Source Feedback Pump Motor FET Connect to source of external pump motor FET no no 30 PD_D Motor Pump Driver Drain Feedback Pump Motor FET Connect to drain of external pump motor FET no no 31 HD_G High-side Driver for Valve’s Fail-safe FET Gate Output to Control High-side FET Connect to gate of external pump motor FET no no 32 HD_S High-side Driver for Valve’s Fail-safe FET Source Feedback High-side FET Connect to source of external High-side FET no no 33 HD_D High-side Driver for Valve’s Fail-safe FET Drain Feedback High-side FET Connect to drain of external High-side FET no no 37 GND_P3 Supply Power Ground 3 no no 38, 39 (2) LSD8 Low-side Driver for PWMed Valves Open Drain Output for Low-side Driver 8 no no 40, 41 (2) LSD7 Low-side Driver for PWMed Valves Open Drain Output for Low-side Driver 7 no no 42, 43 (2) LSD6 Low-side Driver for PWMed Valves Open Drain Output for Low-side Driver 6 no no 44, 45 (2) LSD5 Low-side Driver for PWMed Valves Open Drain Output for Low-side Driver 5 no no 46 GND_P4 Supply Power Ground 4 no no 48 ADIN3 ADC Analog to Digital Input 3 no no Notes (4) (4) SB0800 6 NXP Semiconductors Table 2. SB0800 pin definitions (continued) Pin number Pin name DOSV = 5.0 V DOSV = 3.3 V 49 ADIN2 ADC Analog to Digital Input 2 no no 50 ADIN1 ADC Analog to Digital Input 1 no no 51 GND_A Supply Analog Ground no no 52 VINT_A Internal Function 2.5 V internal supply for analog no no (2) 53 VINT_D Internal Function 2.5 V internal supply for digital no no (2) 54 GND_D Supply Digital Ground no no 55 VCC5 Supply 5.0 V Supply PIN 5V 5V 56 DOSV Supply Digital Output Voltage Supply, DOSV under voltage reset 5V 3.3V 57 SO SPI SPI Interface Digital Output 64 P53_CFG Supply Input to select output voltage at DOSV (5.0 V/ 3.3 V) no no 20, 21, 22, 23, 58, 59, 60, 61, 62 NC Not connected Pin used for production tests and must not be grounded no no 3, 17, 19, 27, 34, 35, 36, 47, 63 NC Not connected Pin used for production tests and must be grounded no no Exposed pad GND_P5 Supply Power Ground 5 no no Pin function Definition Notes DOSV bias (4) Notes 2. Pins must be shorted together 3. 220 nF/10 V capacitor needed 4. All GND_Px pins must be shorted together at the PCB level. SB0800 NXP Semiconductors 7 4 General product characteristics 4.1 Maximum ratings Table 3. Maximum ratings Voltage parameters are absolute voltages referenced to GND_A, GND_D and flag (tied together internally). Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (rating) Min. Max. Unit Notes Supply VVPWR Analog Power supply voltage -0.3 40 V VDOSV Digital Output Supply Voltage -0.3 7.0 V Selection of 5.0 V or 3.3 V for the digital -0.3 7.0 V Digital power supply voltage -0.3 7.0 V VGND_A Ground analog -0.3 0.3 V VGND_D Ground digital -0.3 0.3 V VGND_P Ground exposed pad -0.3 0.3 V VVINT_A Internal regulator analog power supply -0.3 3.0 V VVINT_D Internal regulator digital power supply -0.3 3.0 V -0.3 or VPWR -0.3 VPWR +15 -0.3 40 or VPWR +0.3 V VP53_CFG VVCC5 Internal function Charge pump VCP Internal charge pump V High-side driver for general purpose VHS High-side driver High-side driver for valve’s fail-safe FET VHD_G Gate of the high-side predriver -20 55 V VHD_S Source of the high-side predriver -0.3 40 V VHD_D Drain of the high-side predriver -0.3 40 V VPD_G Gate of the Motor Pump predriver -0.3 55 V VPD_S Source of the Motor Pump predriver -0.3 40 V VPD_D Drain of the Motor Pump predriver -0.3 40 V VRSTB Reset pin -0.3 7.0 V Input analog to digital -0.3 7.0 V Motor pump driver Reset A to D converter VADINx SB0800 8 NXP Semiconductors Table 3. Maximum ratings (continued) Voltage parameters are absolute voltages referenced to GND_A, GND_D and flag (tied together internally). Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (rating) Min. Max. Unit Notes SPI VSO Serial peripheral interface slave output -0.3 DOSV +0.3 V VSI Serial peripheral interface slave input -0.3 7.0 V VCSB Serial peripheral interface chip select -0.3 7.0 V VSCLK Serial peripheral interface clock -0.3 7.0 V Table active clamp -100 mA 40 Energy capability (EAR) at 125 °C • LSD1—4, with 20 mH load — 30 Energy capability (EAR) at 125 °C • LSD5—8, with 20 mH load — 40 Energy capability (EAR) at 125 °C • HS, with 20 mH load — 13 Drain continuous current; during on state • LSDx — 5.0 Maximum negative current for 5.0 ms without being destroyed • LSDx -6.0 — Input current • P53_CFG, SI, CSB, SCLK, RSTB -20 20 Low-side driver for valves (LSD1-8) Low-side driver for valves VLSDx Low-side driver Low-side driver VLD V Energy capability ELSD1—4 ELSD5—8 EHS mJ mJ mJ Currents ILSDX(POS) ILSDX(NEG) IDIG 4.2 A A mA Operating conditions This section describes the operating conditions and the current consumptions. Conditions apply to all the following data, unless otherwise noted. Table 4. Operating conditions Voltage parameters are absolute voltages referenced to GND. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (rating) Min. Typ. Max. VPWR Functional operating supply voltage. Device is fully functional. • All features are operating 6.0 — 36 VCC5 Functional operating supply voltage. Device is fully functional. • All features are operating. 4.75 — 5.25 VDOSV Functional operating supply voltage. Device is fully functional. • All features are operating. 3.13 — 5.25 Unit Notes V V V SB0800 NXP Semiconductors 9 4.3 Supply currents This section describes the operating conditions and the current consumptions. Conditions apply to all the following data, unless otherwise noted. Table 5. Supply currents Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 36 V, 4.75 V ≤ VCC5 ≤ 5.25 V, 3.13 V ≤ VDOSV ≤ 5.25 V, - 40 °C ≤ TJ ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Description (rating) Min. Typ. Max. Unit Quiescent current of VPWR measured at 36 V, VCC5 = 0 V — — 30 μA Current of VPWR in operating mode, VCC5 = 5.0 V — 20 — mA — 10 — mA — — 10 mA Min. Typ. Max. Unit Operational junction Temperature -40 — 150 °C TSTG Storage Temperature -65 — 150 °C RθJC RθJC, Thermal Resistance, Junction to Case (Package exposed pad) Steady state — — 2.0 °C/W Peak Package Reflow Temperature During Reflow — — Note 7 °C Notes VPWR current consumptions IQVPWR IVPWR VCC5 current consumptions IVCC5 Current of VCC5 pin in operating mode (SPI frequency at 10 MHz) DOSV current consumptions IDOSV 4.4 Current of DOSV pin in operating mode (SPI frequency at 10 MHz) Thermal ratings Table 6. Thermal data Symbol TJ TPPRT Description (rating) Notes (5)(6) Notes 5. Lead soldering temperature limit is for 10 seconds maximum duration. Lead soldering can be done twice. Device must be delivered in dry pack. 6. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. SB0800 10 NXP Semiconductors 4.5 Logical inputs and outputs Table 7. Logical inputs/outputs VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified. Symbol Description (rating) Min. Max. Unit Notes Logical inputs VIH_X Input High-voltage • P53_CFG, RSTB, SI, CSB, SCLK, ADIN1, ADIN2, ADIN3 — 2.0 V VIL_X Input Low-voltage • P53_CFG, RSTB, SI, CSB, SCLK, ADIN1, ADIN2, ADIN3 0.8 — V Logical outputs VOH_X Input High-voltage, with 1.0 mA • SO 0.8 x DOSV — V VOL_X Input Low-voltage, with 1.0 mA • SO — 0.4 V VOL_RSTB RSTB Low-voltage, with 1.0 mA • RSTB — 0.4 V SB0800 NXP Semiconductors 11 5 General description 5.1 Block diagram Four Valves Low-side (PWM) Four Valves Low-side (regulated) Three Analog to Digital Converter Motor Pump Predriver (500 Hz) One High-side Driver SPI Registers (16 Bits) Supervision Figure 4. SB0800 functional block diagram 5.2 Functional description The SB0800 device is a valves and pump controller, designed for use in harsh industrial environments, requiring few external components. The SB0800 eight high-current low-side drivers for use with solenoid valves, and high-side gate drivers for controlling two external Nchannel MOSFETs for use with a pump motor and master relay for a solenoid coil. In conjunction with this primary functionality, the SB0800 has one low-side driver to control a resistive load. The SB0800 boosts an internal charge-pump, allowing the high-side drivers to use inexpensive N-channel MOSFETs. The digital I/O pins can be configured for both 5.0 V and 3.3 V levels for easy connection to any microprocessor. Also, the device integrated three Analog to Digital converters. The SB0800 uses standard SPI protocol for communication. 5.3 Features This section presents the detailed features of SB0800. Table 8. Device features set Function Description High-side Driver for Fail-safe FET • • • High-side Fail-safe FET driver Overcurrent shutdown Load leakage detection High-side Driver for general purpose • • • • • High-side switch connected to VPWR (1.0 Ω max Rds(on) at 125 °C) Open load detection VDS state monitoring Overcurrent shutdown Overtemperature shutdown Pump Driver • • Pump motor driver up to 500 Hz PWM frequency controllable through SPI command or a digital signal Overcurrent shutdown between external FET drain and source SB0800 12 NXP Semiconductors Table 8. Device features set (continued) Function Description • • • • • • Solenoid driver (300 mΩ max. RDS(on) at 125 °C) works either as current regulator or as PWM Current regulation deviation: ±2.0% Configurable PWM frequency from 3.0 kHz to 5.0 kHz PWM duty cycle 10-bit resolution Open load detection VDS state monitoring • • • Overcurrent shutdown Overtemperature shutdown Send current regulation error flag (only for current regulation modules) • Solenoid driver (225 mΩ max RDS(ON) at 125 °C) are PWM low-side driver • • • • • • • Configurable PWM frequency from 3.0 kHz to 5.0 kHz PWM duty cycle resolution 0.39% Open load detection VDS state monitoring Overcurrent shutdown Overtemperature shutdown Max switch-off energy 40 mJ • • • Low-side driver (20 mA max, RDS(on) 8.0 Ω) Open load detection VDS state monitoring • • Overcurrent shutdown Overtemperature shutdown • Low-side driver (350 mA max, RDS(on) 1.0 Ω) • • • • Open load detection VDS state monitoring Overcurrent shutdown Overtemperature shutdown Analog to Digital Converter (x3) • • • • • 10-bit ADC External ADINx pins Internal voltages and temperature information Allow to control the pump by a MCU Allow to control the low-side resistive driver by a MCU Supervision • • • • • • • • • • • VINT_x undervoltage (internal regulator) VCC5 & DOSV undervoltage (supply voltage from external) Watchdog fault ALU check counter overflow External reset fault VPWR undervoltage and overvoltage detections Mismatch MAIN-AUX OSC CLK Temperature warning SPI failure Charge pump issue GND supervision Low-side solenoid driver (x4) Low-side solenoid driver (x4) Low-side resistive Driver Low-side Driver SB0800 NXP Semiconductors 13 6 Functional block description 6.1 Error handling Table 9. Error handling Type of error Detection condition Action Clear SPI flag Restart condition Notes High-side driver Overcurrent between external FET Drain and Source Load leakage ON HD_G Off + SPI fault flag (HD_oc) Write 1 to HD_clr_flt 1 hd_on rise- Ignore hd_on rise-edge command Write 1 to HD_clr_flt edge (SPI + SPI fault flag (HD lkg) bit) Write 1 to HD_clr_ fit and then turn on by SPI command (hd_ on) Write 1 to HD_clr_flt and then turn on by SPI command (hd_ on) Pump motor PWM driver Overcurrent between external FET Drain and Source ON PD_G Off + SPI fault flag (PD_oc) Write 1 to PD_clr_flt Write 1 to PD_clr_flt and then turn-on by SPI command (pd on) SPI flag only (LSDx_op) Read diagnosis No Read VDS state by SPI (vds_LSDx) update with min filter time (T1) rise and fall edge No LSDx Open Load VDS state monitoring OFF ON/OFF Overcurrent ON OFF fault FET only + SPI fault flag Write 1 to LSD_clr_flt (LSDx_oc) Write 1 to LSD_clr_flt and turn on by SPI command (LSDx duty cycle or current set point) Overtemperature ON OFF fault FET only + SPI fault flag Write 1 to LSD_clr_flt (LSDx_ot) Write 1 to LSD_clr_flt and turn on by SPI command (LSDx duty cycle or current set point) Current regulation error (only for LSD1-4) ON Read SPI flag only (LSDx_crer) Read diagnosis No OFF SPI flag only (LDx_op) Read diagnosis No Send VDS state by SPI (VDS_LD) update with min filter time (T1) rise and fall edge No LDx Open Load VDS state monitoring ON/OFF Overcurrent ON OFF fault FET only + SPI fault flag Write 1 to LD_clr_flt (LD_oc) Write 1 to LD_clr_flt and turn on by SPI command (LD_on) Overtemperature ON OFF fault FET only + SPI fault flag Write 1 to LD_clr_flt (LD_ot) Write 1 to LD_clr_flt and turn on by SPI command (LD_on) OFF SPI flag only (HS_ op) Read diagnosis No Send VDS state by SPI (VDS_ HS) update with min filter time No HS Open Load VDS state monitoring Overcurrent ON/OFF ON OFF fault FET only + SPI fault flag Write 1 to HS_clr_flt (HS_oc) Write 1 to HS_clr_flt and then turn on by SPI command (HS_ on) SB0800 14 NXP Semiconductors Table 9. Error handling (continued) Type of error Overtemperature Detection condition ON Action Clear SPI flag OFF fault FET only + SPI fault flag Write 1 to HS_clr_flt (HS_ot) Restart condition Notes Write 1 to HS_clr_flt and then turn on by SPI command (HS_on) Supervision VINT_x Undervoltage All except SPI register reset & Vint_uv go to Sleep mode High VCC5 & DOSV Undervoltage Wait undervoltage reset filter All except SPI register reset except VCC5_uv time T1 See Table 19, go to High Sleep mode (see Table 19) External reset fault No internal RSTB pulldown VPWR Undervoltage SPI registers go to initial state Read Vint_uv bit Read the Message 0 of SPI register (see Table 19) No See Table 19, 1. Normal condition All LSDx Off (Clear all LSDx duty 2. Turn on by SPI command RSTB is high cycle registers or current set point) 1. Normal condition 2. Read diagnosis (VPWR_UV) (LSDx duty cycle or current set state + SPI fault flag (VPWR_UV) point) VPWR Overvoltage RSTB is in high state All LSDx Off (Clear all LSDx duty 1. Normal condition cycle registers or current set point) 2. Read diagnosis + SPI fault flag (VPWR_OV) (VPWR_OV) 1. Normal condition 2. Turn on by SPI command (LSDx duty cycle or current set point) Mismatch SB0800 MAIN-AUX OSC CLK RSTB is in high state SPI registers goes to initial state low except, see Table 27 Read RST_clk bit No Temperature Warning RSTB is in high state SPI flag 1. Normal condition 2. Read diagnosis No SPI Failure RSTB is in high state SPI flag (Fmsg) Read diagnosis No VPRE 10 Monitoring RSTB is in high state Send by SPI (ADC) No No (9) VPRE 12 Monitoring RSTB is in high state Send by SPI (ADC) No No (9) VINT_x Monitoring RSTB is in high state Send by SPI (ADC) No No (9) Vcp_vpwr Monitoring RSTB is in high state Send by SPI (ADC) No No Temperature Monitoring RSTB is in high state Send by SPI (ADC) No No GND_D Supervision RSTB is in high state SPI flag only (FGND) No No GND_A Supervision; indirect detection by VCC5 or DOSV RSTB is in high state SPI flag only (VCC5_UV or DOSV_UV) No No (9) Notes 7. If xxx_clr_flt is written “1” by SPI, all SPI flags are set “0”, so SW engineer has to read the SPI flag first and then write xxx_clr_flt to default value “0”. 8. SW engineering can monitor internal supply voltage in real time with ADC reading, and can use fail-safe function. If these ADC results are not in a certain range, uC can reset the SB0800 (see ADC section). 9. Fail-safe switch off until power is off SB0800 NXP Semiconductors 15 6.2 High-side driver 6.2.1 Function description The high-side driver is intended to control the fail-safe switch for the overall solenoid path, and HD_G is controlled by the SPI command. Figure 5. High-side driver 6.2.2 High-side driver and fault protection 6.2.2.1 Overcurrent High-side driver protects the external n-channel power FET on HD_G in overcurrent conditions. The drain-source voltage of the FET on HD_G is checked if the high-side driver is switched on. If the measured drain-source voltage exceeds the overcurrent voltage threshold, the output of the overcurrent comparator is enabled. If the output of the comparator is active longer than the defined filter time, the output HD_G is switched off. Overcurrent detection logic has a masking time from hd_on turn-on against malfunctions on transient time. After switching off the power FET on HD_G by an overcurrent condition, the power FET can be turned back to a “normal state” by a SPI write 1 to the “HD_clr_flt” register, and then turned on by a SPI command. 6.2.2.2 Load leakage detection Each time HD_G is turned on, the ILCdet current is sourced out of the HD_S pin for the time tHD_LC, to check the external leakage current on the node in the application. The high-side switch on HD_G is turned on if the measured voltage is over the detection threshold. If this test fails, HD_G does not turn-on and the fault flag is set to high. The power FET can be turned back to a “normal state” only by a SPI write 1 to the “HD_clr_flt” register, and then turned on by a SPI command. When the power FET is switched off, the gate capacitance of the FET is discharged by a constant current, which is controlled fast and slow by a SPI command (HPD_sr). 6.2.2.3 External components of high-side driver For protection, external resistors RHD_D, RHD_G, and RHD_S are required (for example: RHD_D = 100 Ω, RHD_G = 100 Ω, RHD_S = 100 Ω). The zener clamping is necessary to protect the gate and source. The zener chains are used for avalanche clamping and protection against transients. SB0800 16 NXP Semiconductors Table 10. High-side driver electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit VHD_ON HD_G switch-on voltage - with pd_on: PWMat 500 Hz, 50% duty cycle through the SPI • 5.5 V ≤ VPWR < 6.0 V • 6.0 V ≤ VPWR < 7.0V • 7.0 V ≤ VPWR < 10 V • 10 V ≤ VPWR < 36 V VPWR+ 4 VPWR+5 VPWR+7 VPWR+10 — — — — VPWR+ 15 VPWR+15 VPWR+15 VPWR+15 VHD_OFF HD_G switch-off voltage — — 1 V Turn-on time - After tHD_LC — — 1.4 ms IHD_OFF_SLOW Turn-off current slow - VHD_G > 2.0 V. HPD_sr = 0 70 100 200 μA IHD_OFF_FAST Turn-off current fast - VHD_G > 2.0 V, HPD_sr = 1 1.0 2.0 4.5 mA Leakage current - 0 ≤ VHD_S ≤ 36 V, 6.0 ≤ VPWR ≤ 36 V — — 50 μA Leakage current - VCC5 = DOSV = 0 V, HD_D = PD_D = VPWR = 36 V — — 10 μA -15% 1.0 +15% V — 1.5 — mA Notes HD_G tHD_ON V HD_S lLEAK_HD_SRC HD_D LLEAK_HD_DRN Overcurrent detection VHD_OC Overcurrent detection threshold - VHD_D-VHD_S, RDRN, RSRC = 100 Ω Load leakage current detection IHD LC HD_S source current 6.3 Pump motor pre-driver 6.3.1 Function description This module is designed for pump motor predrivers, a maximum of 500 Hz PWM is possible. The pump motor pre-driver can be driven by a SPI command (pd_on) or through the ADIN1 pin by selecting Adin1_dis bit at “1”. Adin1_dis (SPI) Vbat ADIN1 Gate Driver PD_G Logic pd_on (SPI) Status / Fault (Trough SPI) PD_D Overcurrent PD_S R1 R2 R3 M PD_mt_cfg OCF_pd PGND Figure 6. Pump motor predriver SB0800 NXP Semiconductors 17 6.3.2 Fault Detection 6.3.2.1 Overcurrent The pump pre-driver protects the external n-channel power FET on PD_G in overcurrent conditions. The drain-source voltage of the FET on PD_G is checked if the high-side predriver is switched on. If the measured drain-source voltage exceeds the overcurrent voltage threshold, the output of the overcurrent comparator is enabled. If the output of the comparator is active longer than the defined filter time, the output PD_G is switched off. Overcurrent detection logic has a masking time from pd_on turn-on against malfunctions in transient time. The masking time and filter time of the pump predriver is controllable by the SPI bit (See SPI and data register). After switching off the power FET on PD_G by an overcurrent condition, the power FET can be turned back to a “normal state” by a SPI write 1 to the “PD_clr_flt” register, and then turned on by a SPI command. When the power FET is switched off, the gate capacitance of the FET is discharged by a constant current, which is controlled fast and slow by a SPI command (HPD_sr). 6.3.2.2 External components of pump predriver Protection of the resistors RPD_D, RPD_G, and RPD_S is required (for example: RPD_D = 2.0 kΩ, RPD_G = 100 Ω, RPD_S = 2.0 kΩ). Zener clamping is necessary to protect the gate and source. The zener chains are used for avalanche clamping and protection against transients. Table 11. Pump motor predriver electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit VPD_ON PD_G switch-on voltage - with pd_on: PWM at 500 Hz, 50% duty cycle through the SPI, 16 nF between PD_G & GND. pd_on = 1 without PWM • 5.5 V ≤ VPWR < 6.0 V • 6.0 V ≤ VPWR < 7.0V • 7.0 V ≤ VPWR < 10 V • 10 V ≤ VPWR < 36 V VPWR+ 4 VPWR+5 VPWR+7 VPWR+10 — — — — VPWR+ 15 VPWR+15 VPWR+15 VPWR+15 V VPD_OFF PD_G switch-off voltage - pull-up current < 20 μA — — 1 V Turn-on time — 0.5 — ms IPD_OFF_SLOW Turn-off current slow - PD_G > 2.0 V. HPD_sr = 0 70 100 200 μA IPD_OFF_FAST Turn-off current fast - PD_G >2.0 V, HPD_sr = 1 1.0 2.0 4.5 nA Leakage current - 0 ≤ VPD_src ≤ 36 V, 6.0 ≤ VPWR ≤ 36 V — — 10 μA Leakage current - VCC5 = DOSV = 0 V, HD_D = PD_D = VPWR = 36 V — — 10 μA -15% 1.0 +15% V Notes PD_G tPD_ON PD_S lLEAK_PD_SRC PD_D ILEAK_PD_DRN Overcurrent detection VPD_OC Overcurrent detection threshold - VPD_D - VPD_SRC, RDRN, RSRC = 2.0 kΩ tPD_OC1 Overcurrent detection filter time - OCF_pd = 0 — T2 — μs tPD_OC2 Overcurrent detection filter time - OCF_pd = 1 — 4*T1 — μs SB0800 18 NXP Semiconductors 6.4 Low-side driver 6.4.1 Functional description The SB0800 is designed to drive inductive loads in low-side configuration. All four channels are monitored by logic and faults are individually reported by the SPI. All external wiring to the loads and supply pins of the device are controlled. The device is self-protected against short-circuit and overtemperature at the outputs. Open Duty cycle (SPI) HSD VDS Monitoring Overcurrent Logic COIL Overtemperature Status / Fault (Trough SPI) LSDx Gate Driver PGND Figure 7. PWM low-side driver Channel 1 to 4 can work either as current regulator or as PWM. When Channels 1 to 4 work as a current regulator, freewheeling diodes must be connected. Each channel comprises an output transistor, a predriver circuit, a diagnostic circuitry, and a current regulator. The SPI register defines the target output current. The output current is controlled through the output PWM of the power stage. The LSD1-4 current slopes are controlled by a SPI command to reduce switching loss. The four power outputs consist of DMOS-power transistors with open drain outputs. The output transistor is equipped with an active clamp to limit the voltage at its output during turn-off with inductive loads. When the external fly-back diode is connected, the current re-circulation executes via the diode to the battery. When the diode is not connected, the PWM driver is equivalent to a digital driver. In those conditions, the inductive load forces the output voltage to increase until the voltage at the output is such that the output transistor turns on again. This lasts until the inductor current becomes zero. At that moment, the output transistor turns off. The predriver is in charge of applying the necessary voltage on the output transistor gate to minimize the On-resistance of the output switch. The duty cycle of PWM low-side drivers is programmed via an 8-bit SPI message. The duty cycle between 0% and 100% can be selected and the LSB of the 8 bits is weighted with an 0.39% duty. Each channel has an 8-bit SPI register of PWM duty cycle. The PWM low-side driver uses each channel as a digital low-side switch. PWMx duty cycle = 1111 1111 - Digital low-side switch ON (conducting) PWMx duty cycle = 0000 0000 - Digital low-side switch OFF The SB0800 provides interleaved phase shift switching to minimize switching noise of the solenoid coil. Each LSD1 to 4 have this cycle. SB0800 NXP Semiconductors 19 250 Ms (4.0 kHz PWM Frequency) Ch 1 Ch 2 Ch 3 Ch 4 SPI 4 SPI Access Figure 8. PWM valve control interleave Table 12. Low-side driver electrical characteristics VPWR = 6.0 to 36 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit Notes Power output RON_LSD14 On Resistance Channel 1 to 4: CR • TJ = 125 °C; 9.0 V ≤ VPWR ≤ 36 V; ILOAD = 2.0 A — — 0.255 Ω RON_LSD14_E On Resistance Channel 1 to 4: CR (extended mode) • TJ = 125 °C; 5.5 V ≤ VPWR ≤ 9.0 V; ILOAD = 2.0 A — — 0.33 Ω I LEAK_LSD Drain Leakage Current • LSD = 36 V — — 10 μA VCL_LSD Active Clamp Voltage — 38 45 V Rise Time/Fall Time • 10% to 90%, ILOAD = 1.0 A, VPWR =24 V; no capacitor didt = 0 (SPI bit) 1.0 0.1 1.7 1.35 3.0 3.0 μs Rise Time/Fall Time • 10% to 90%, ILOAD = 1.0 A, VPWR = 24 V; no capacitor didt = 1 (SPI bit) 0.05 0.1 0.5 1.0 1.0 3.0 μs 0.0 — 3.0 µs Timings tR_CR1 tF_CR1 tR_CR2 tF_CR2 tD on CR tD off CR Turn on/off Delay Time • Digital 1 to 10% or 90%, ILOAD = 1.0 A, VPWR = 24 V, no capacitor (10) SB0800 20 NXP Semiconductors Table 12. Low-side driver electrical characteristics (continued) VPWR = 6.0 to 36 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit 20% kHz Notes Timings LF_PWM 0000 0000 0000 0001 … 1111 1110 1111 1111 Output PWM frequency for LSD1-4 • LF_PWM xx = 111 • LF_PWM xx = 110 • LF_PWM xx = 101 • LF_PWM xx = 100 • LF_PWM xx = 000 (default) • LF_PWM xx = 011 • LF_PWM xx = 001 • LF_PWM xx = 010 -20% PWM Duty Cycle Programming (8-bits) • Can be used for digital low-side driver — — — — — 3.0 3.2 3.4 3.6 3.9 4.2 4.5 5.0 OFF 0.39 — 99.61 ON — — — — — % Notes 10. Digital: internal digital signal delivered by interleave synchronization block. See Figure 8. 6.4.2 LSD1 to LSD4 current regulation driver Figure 9. PWM low-side driver (current regulated) The load current is sensed by an internal low-side sense FET and digitized by an internal A/D converter. The target value of the current is given SPI messages. A digital current regulation circuitry compares the actual load current with the target current value and steers the duty cycle of the low-side power switch. The PI regulator characteristic can be adjusted via the SPI. SB0800 NXP Semiconductors 21 6.4.2.1 Target current Each current regulator channel has its own 10-bit target current register. The LSB of the 10 bits is weighted with 2.2 mA. A zero value disables the power stage of the respective channel. A new target current is instantaneously passed to the settling time, which is the settling of the new current value. PWMx target current value = 00 0000 0000 → 0 mA PWMx target current value = 00 0000 0001 → 2.2 mA … PWMx target current value = 11 1111 1110 → 2.248 A PWMx target current value = 11 1111 1111 → 2.250 A CR_DIS12/34 CR_fb Mode 0 0 current regulation Read current target (to check SPI write) 0 1 current regulation Read output duty cycle value for gate driver. 1 0 PWM Read programmed PWM duty cycle (to check SPI write) 1 1 PWM Read hardware ADC current value 6.4.2.2 LSD1-4 duty cycle (8-bit) or current read (10-bit) Current measurement The output current is measured during the “ON’ phase of the low-side driver. A fraction of the output current is diverted and (using a “current mirror” circuit) generates across an internal resistance a voltage relative to ground, this being proportional to the output current. 6.4.3 PI characteristics Digital PI-regulator with the Transfer function is programmed via the SPI register. KI ------------ + KP z–1 Transfer function: The integrator feedback register I charac bits define the regulation behavior of all channels. The default value is 1/8. Both current regulators remain idle until a non-zero value in I charac was programmed. A high proportional feedback value accelerates the regulator feedback and provides a faster settling of the regulated current after disturbances like battery voltage surge. Table 13. Duty cycle descriptions The duty cycle of PWM output is clamped minimum by options and maximum 100% (see 6.10, “SPI and data register"). Option 0 1 LLC 0 0 LLC Minimum duty cycle 0 10% • the measurement is done at tON/2 by consequence • the regulation current will be set at tON/2 1 3.12% • for a duty cycle > 10%, the measurement is done at tON/2 • for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at tON for 3.2% of duty cycle SB0800 22 NXP Semiconductors Table 13. Duty cycle descriptions The duty cycle of PWM output is clamped minimum by options and maximum 100% (see 6.10, “SPI and data register"). Option LLC 2 1 3 1 LLC Minimum duty cycle 0 3.12% + forced min duty cycle to 1.56% every two cycles • for a duty cycle > 10%, the measurement is done at tON/2 • for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at tON for 3.2% of duty cycle • for a duty cycle set at 1.56%, no measurement is done 1 3.12% + skip min duty cycle every two cycles • for a duty cycle > 10%, the measurement is done at tON/2 by consequence the regulation current will be set at tON/2 • for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at tON for 3.2% of duty cycle • no measurement is done during the skipping mode If the target current value is not reached within the regulation error delay time of tCR_ERR, the flag of the SPI register “LSDx_crer” is set to high. The current regulation loop is still running and tries to regulate at the target. Because it is not at the target, the duty cycle is either 100%, or minimum duty cycle by option. LSDx_crer error detection has no effect on the driver, only SPI fault reporting. The microcontroller can detect the fault through the SPI (LSDx_crer bit + ADC current reading), and shutdown the driver by sending 0 target current. Set Current – ADC result > “error threshold” during tCR_ERR then LSDx_crer is set to 1. This flag is latched & can be reset by the SPI read (LSDx_crer). Each of the four current regulation low-side drivers can be used as a PWM low-side switch. CR_disxx flag is enabled HIGH. The 8 MSB bits of the target current message are the PWM duty cycle. The first duty is controlled by the SPI bit FDCL (See SPI and data register). Table 14. LSD1 to LSD4 current regulation driver electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit — — — — OFF 2.2 ... 2.25 — — — — mA — — — — — — — — — — 65 50 25 ±10 ±2.0 Notes Current regulation 0000 0000 0000 0001 ... 1111 1111 ICR_DEV Target current programming (10-bits) Maximum regulation deviation • 0 mA ≤ ITARGET < 50 mA, includes ADC error • 50 mA ≤ ITARGET < 100 mA, includes ADC error • 100 mA ≤ ITARGET < 250 mA, includes ADC error • 250 mA ≤ ITARGET < 400 mA, includes ADC error • 400 mA ≤ ITARGET < 2.25 A, includes ADC error A mA (11) % Notes 11. Maximum regulation deviation performances noted in the table depend on external conditions (VPWR, load (R,L)). SB0800 NXP Semiconductors 23 6.5 Low-side driver for resistive load 6.5.1 Power output stages Open Controlled by SPI Vbat VDS Monitoring Logic Overcurrent Overtemperature Status / Fault (Through SPI) LD No Sink Current Gate Driver GND Figure 10. Low-side driver for resistive load diagram block The low-side driver consists of DMOS-power transistors with open drain output. The low-side driver can be driven by SPI commands or by a MCU through the ADIN2. The low-side driver is composed of an output transistor, a predriver circuit, and diagnostic circuitry. The predriver applies the necessary voltage on the output transistor gate to minimize the On resistance of the output switch. To avoid leakage current path, LD has no sink current. Table 15. Low-side driver electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit Notes On Resistance for LD • TJ = 125 °C, 6.0 V ≤ VPWR ≤ 36 V — — 14 Ω DC Current Capability — — 20 mA Drain Leakage Current • VPWR = 0, VCC5 = 0, LD = 30 V, no sink current — — 5.0 μA tD_ON_LD Turn On Delay Time for LD — — 1.0 μs (12) tD_OFF_LD Turn Off Delay Time for LD — — 1.0 μs (12) Power output LD RON_LD ILEAK_LD Timings Notes 12. From Digital Signal to 50% (turn ON) or 50% (turn OFF). RL = 1.0 kΩ, VPWR = 30V, no capacitor SB0800 24 NXP Semiconductors 6.5.2 Fault detection Open load An open condition is detected when the LD output is below the threshold OPLD for the defined filter time tOP_LD, the fault bit is set ld_OP (SPI error flag only). This function only operates during the off state. VDS state monitoring The VDS state monitoring gives real time state of LD drain voltage vs OPLD voltage. This signal is filtered and sent through the SPI vds_ld bit. If the VDS voltage is higher than OPLD with a filter time (T1), vds_ld is set to “1”. Overcurrent When the current is above the overcurrent threshold OCLD for the defined filter time tOC_LD, the driver is switched off, a SPI fault bit ld_OC is set, and the turn-on SPI command is cleared. The driver can be returned to the “normal state” by a SPI write “1” to “LD_clr_flt”, then turned on by a SPI command (LD_on). Overtemperature When the temperature is above the overtemperature threshold OTLD for the defined filter time tOT_LD, the driver is switched off, a SPI fault bit ld_OT is set, and the turn-on SPI command is cleared. The driver can be returned to the “normal state” when the temperature returns to the normal state, a SPI write “1” to “LD_clr_flt”, then turning on a SPI command (LD_on). Table 16. Low-side driver electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit Notes Overcurrent shutdown OCLD Overcurrent Shutdown Threshold Current for LD — 100 — mA tOC_LD Overcurrent Shutdown Filter Time — T1 — μs Open load detection OPLD Open Load Detection Threshold (also used for VDS monitoring) — 2.0 — V tOP_LD Open Load Detection Filter Time — T2 — μs VDS State Filter Time (rise & fall edge filter time) — T1 — μs VDS monitoring tVDS_LD Overtemperature shutdown OTLD Overtemperature Detection Threshold 180 195 210 °C tOT_LD Overtemperature Detection Filter Time — T1 — μs SB0800 NXP Semiconductors 25 6.6 Analog to digital converter (x3ch) ADC is referenced to VCC5 voltage and converts the voltage on 10 bits. It is used to read the following voltages: • Three analog input pins: ADINx • Internal voltage supplies (VINT_A, VINT_D, VPRE10, VPRE12, VCP_VPWR) • Average temperature of die, which is used by the temperature warning detection circuit (TEMP). Refer to the SPI Message Structure, Message #9. • Allows to read the current drain by the LSD1-4 in PWM mode. Also, it is possible to use ADIN1 and / or ADIN2 to control respectively the motor pump and / or the low-side driver for resistive load directly by the MCU. Table 17. Direct control of pump and low-side Adin1_dis Pump control 0 Pd_on bit (SPI command) 1 By MCU Adin2_en Low-side for resistive load control 0 By MCU 1 Ld_on (SPI command) Table 18. ADC electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to 125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit Notes Total Error - 0 < ADINx < VCC5 — 3 — LSB (13) Conversion Time — 6.6 — μs Refresh Time - min ADC update time; shorter than 1.0 ms — 100 — μs -10.0 — 10.0 μA – — 30 pF ADC ADC_ERR tCONV tRFT ADINx IADI_LK CADI_CAP Input Leakage Current - 0 < ADINx < VCC5 Input Capacitance Internal voltage AD_VINT_A Voltage of internal analog regulator 440 512 590 LSB AD_VINT_D Voltage of internal digital regulator 440 512 590 LSB AD_VPRE10 VPRE10 - ADC ratio =VPRE10/3.3, 9.0 < VPWR < 36 V 400 600 800 LSB AD_VPRE12 VPRE12 - ADC ratio = VPRE12/3.0, 9.0 < VPWR < 36 V 590 790 980 LSB VCP-VPRWR - ADC ratio = VCP - VPWR/4.0, 9.0 < VPWR < 36 V 330 — 810 LSB Voltage at 25 °C — 717 — LSB deviation with 1.0 °C increments — -2.0 — LSB/°C AD_VCP Temperature reading AD_TEMP25 AD_DEV_TEMP Notes 13. If ADINx voltage is between VCC5 to max_rating, the ADC value does not change. Also between VCC5 min and GND, the ADC value does not change. 14. SW engineer can monitor internal supply voltage in real time with ADC, SPI reading, and can use fail-safe function. SB0800 26 NXP Semiconductors 6.7 High-side 6.7.1 Function description The device has one high-side, having an integrated high-side switch, controlled by the SPI command HS_on. It allows connecting and disconnecting loads like voltage dividers from the supply line, to reach low quiescent current of the total ECU or to driver small size relay driver. High Side Figure 11. High-side driver 6.7.2 Fault detection 6.7.2.1 Ground shift With a 2.0 V GND shift on the external relay coil (50 Ω), 30 mA could flow through the high-side output (diode between the SB0800_gnd & the high-side output) without damage to the SB0800 (see Figure 11). 6.7.2.2 Open load An open condition is detected when the high-side output is higher than the threshold OP_HS for the defined filter time tOP_HS. The fault bit is set HS_op (SPI error flag only). The function only operates during the off state. 6.7.2.3 VDS state monitoring The VDS state monitoring gives the real time state of HS drain voltage vs. OP_HS voltage. This signal is filtered and sent through the SPI vds_HS bit. If the HS output is lower than OP_hs with a filter time (T1), vds_HS is set to “1”. 6.7.2.4 Overcurrent When the current is above the overcurrent threshold OC_hs for the defined filter time tOC_HS, the driver is switched off, a SPI fault bit HS_oc is set, and the turn-on SPI command is cleared. The driver can be turned back to a “normal state” by a SPI write “1” to “HS_clr_flt”, then a turn on by the SPI command (HS_on). 6.7.2.5 Overtemperature When the temperature is above the overtemperature threshold OT_hs for the defined filter time tOT_HS, the driver is switched off, a SPI fault bit HS_ot is set, and the turn-on SPI command is cleared. The driver can be turned back to a “normal state” when the temperature returns to a normal state, a SPI write “1” to “HS_clr_flt”, and then a turn on by the SPI command (HS_on). SB0800 NXP Semiconductors 27 Table 19. High-side electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit On resistance • TJ = 125 °C, 9.0 V ≤ VPWR ≤ 36 V • TJ = 125 °C, 6.0 V ≤ VPWR ≤ 9.0 V — — — — 1.0 1.5 Ω DC current capability — 270 — mA Drain leakage current - VPWR = 14 V, VCC5 = 0 — — 2.0 μA Breakdown Voltage 40 — — V Turn on/off delay time — — 20 μs Notes Power output HS RON_HS ILEAK_HS V_BVDSS _HS Timing tD_ON_HS/ tD_OFF_HS (15) Overcurrent shutdown OC_HS Overcurrent shutdown threshold current — 650 — mA tOC_HS Overcurrent shutdown filter time - measured by sense FET — T1 — μs Open load detection threshold - include GND shift = 2.0 V, also used for VDS monitoring — 4.0 — V VDS state filter time — T1 — μs Open load detection OP_HS VDS monitoring tVDS_HS (16) Overtemperature shutdown OT_HS Overtemperature detection threshold 180 195 210 °C tOT_HS Overtemperature detection filter time — T1 — μs Notes 15. From digital signal to 50% (turn ON) or 50% (turn OFF). RL=1.0 KΩ, VPWR = 30 V, no capacitor 16. Used open load detection comparator rise & fall edge filter time SB0800 28 NXP Semiconductors 6.8 Monitoring module 34SB0800 MCU SEED Register SEED Generator Linear Feedback Shift Register (AR7:0) Linear Feedback Shift Register ALU Checker ALU Checker 34SB0800 ALU Result MCU ALU Result (MR7:0) Compare Result (34SB0800 & MCU) LOGIC ERROR Counter Figure 12. Block diagram of SB0800 monitoring module and MCU The monitoring module in SB0800 works independently from the MCU functionality. The SEED is an 8-bit word, initializing the monitoring module and transferred by the SPI. The MCU generates the SEED, and must fetch and send correct calculation results (MR7:0) to the SB0800 monitoring module within a defined time window. The SB0800 monitoring module confirms the result is sent and correct in the time window. ALU checker results of SB0800 monitoring module are transferred to the MCU by the SPI. The monitoring module also calculates the expected correct result, which is compared to the actual result from MCU. The result from MCU is an 8-bit MR. The 8 bits are sent to the monitoring module via the SPI interface. The monitoring cycle time starts by a write of MR, with the next MR written within in a fixed time window. A new cycle time is started automatically by a write of MR. MCU MOSI Calculation Calculation SEED MISO Calculation IF (MR2 = incorrect) THEN (ERR_CNT = 001) MR1 MR2 AR1 AR2 Compare Calculation Compare Time Window Figure 13. Timing diagram of SB0800 monitoring module and MCU ERR_CNT is a 3-bit counter. An incorrect result leads to incrementing the ERR_CNT by one, and a correct result leads to decrementing by one. The ERR_CNT 3-bit can be read by the SPI interface. SB0800 NXP Semiconductors 29 6.8.1 ERR_CNT behavior Reset with (RSTB pin = “Low”) IF (ERR_CNT ≥ 101) THEN (RSTB pin = “Low”) AND (MON_CNT reset) IF (ERR_CNT ≤ 100) AND (MR = incorrect) THEN (ERR_CNT = ERR_CNT+1) IF (ERR_CNT = 000) AND (MR = correct) THEN (ERR_CNT = ERR_CNT) IF (001 ≤ MON_CNT ≤ 100) AND (MR = correct) THEN (ERR_CNT = ERR_CNT - 1) The SB0800 monitors the time window of the SPI message #18 without writing to the SEED. The time window (tWD) counter starts with the RSTB pin rising edge. The time window (tWD) counter is reset with the SPI message #18 (with valid parity bit) and restart. If the SPI message #18 (with valid parity bit) is not transferred from the MCU before the time window (tWD) end period, the RSTB pin goes to a LOW state for the duration time of tRSTB_REC and the RST_wd flag is set “High”. When RSTB is at a low state (internal, external), the time window (tWD) counter is reset to zero. 6.8.2 Linear feedback shift register (LFSR) Both the SB0800 monitoring module and the MCU have LFSR for a pseudo-random number generator of ALU checker inputs. LFSR works in parallel with the SB0800 and MCU. LFSR is initialized by the SPI with a SEED 8-bit, then each MR write command generates a new pseudo-random number. The FF hex-value cannot be used for the SEED. D Q D FF1 Q FF2 kk cck kk cck D Q FF3 kk cck D Q D Q D FF5 FF4 kk cck Q FF6 kk cck kk cck D Q D Q FF7 FF8 kk cck kk cck kk cck Figure 14. Diagram of linear feedback shift register (LFSR) 6.8.3 ALU checker Both the SB0800 monitoring module and the MCU have an ALU checker. The ALU checker work in parallel with the SB0800 and MCU. The 8-bit input of the ALU checker is the 8-bit output of LFSR. The ALU checker proceeds on five sequential calculations. Multiplier pseudo-random value by fix value 4 Adder output multiplier by fix value 6 Subtract previous value with fix value 4 Inverting previous value: bitwise complement Divider previous value by fix value 4 LSFR_out [7:0] X + 4 6 NOT 4 ÷ MR [7:0] 4 Figure 15. Diagram of ALU checker SB0800 30 NXP Semiconductors Table 20. Monitoring module electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Notes MCU monitoring module tWD Timing window for Watchdog 10 — 60 ms tVAM Variation of the Watchdog Window Timing 60 75 90 ms Notes 17. The maximum setting window for the watchdog can be decreased to a SPI timing access. The range given in Table 33 shows the typical use case. Sequence examples to run the watchdog: Check when the pin reset goes high. 1st command: send the message 0: 0x00 to clear flags 2nd command: send the message 0: 0x00 to reinitialize the seed value. Then, no need to send the seed value again 3rd command: message 18: send the corresponding MR value calculated due the the seed value 4th: send the message desired Note: The message 18 (MR value) should be sent according the the tWD timing RESET RSTB Pin t_WD t_WD t_WD >= (tRSTB_EXT) SI State SEED SEED MR1 Message #n MR2 Message #n MRn Clear Flags of Message 0 Initialize SEED Value Send First MR Value Calculated Other SPI CMD Send Second MR Value Calculated Other SPI CMD Send n MR Value Calculated Start sequence recommanded by Freescale Figure 16. Watchdog sequence example 6.9 Supervision Table 21. Reaction to supply fault and reset condition Event RSTB LSDx HD PD LD Normal mode: After RSTB rising edge, No fault High Normal Normal VINT_x undervoltage Low (output) OFF OFF OFF OFF SPI register go to initial state Low except for Vint_uv which is reset to 1. After first read of Vint_uv, it is set back to 0. (18) Clock fail reset Low (output) OFF OFF OFF OFF SPI registers go to initial state Low except for Vint_uv unchanged & RST_clk which is set to 1. After first read of RST_clk, it is set back to 0. (18) Normal Normal SPI Notes Normal SB0800 NXP Semiconductors 31 Table 21. Reaction to supply fault and reset condition (continued) Event RSTB LSDx HD PD LD DOSV undervoltage Low (output) OFF OFF after tLSDx_HD_G OFF OFF SPI register go to initial state except reset flag (Vint_uv, VCC5_uv, DOSV_uv, RST_wd, RST_alu, RST_ext, RST_CLK) and hd_on (tLSDx_HD_G timing). (18) VCC5 undervoltage Low (output) OFF OFF OFF SPI register go to initial state except reset flag (Vint_uv, VCC5_uv, DOSV_uv, RST_wd, RST_alu, RST_ext, RST_CLK) and hd_on (tLSDx_HD_G timing). (18) Watchdog fault or ALU fault Low during tRSTB_REC (output) OFF OFF after tLSDx_HD_G OFF after tLSDx_HD_G OFF SPI Notes SPI register go to initial state except: - reset flag (Vint_uv, VCC5_uv, DOSV_uv, RST_wd, RST_alu, RST_ext, RST_CLK) - clear flag bits - hd_on (tLSDx_HD_G timing). - MR - Seed OFF (18) Note: P_charac and I_charac bits are reset in case of Watchdog fault or ALU fault, but SPI read returns the direct SPI write content. Same SPI behavior as Watchdog fault or ALU fault except seed. SPI register go to initial state except: - reset flag (Vint_uv, VCC5_uv, DOSV_uv, RST_wd, RST_alu, RST_ext, RST_CLK) - clear flag bits - hd_on (tLSDx_HD_G timing). - MR External Reset Low (input) OFF OFF after tLSDx_HD_G OFF Notes: P_charac and I_charac bits are reset in case of external reset, but SPI read returns the direct SPI write content. OFF Watchdog circuit Seed register (written by SPI write Message #0) is reset by External reset event and impossible to write to unless External reset flag is cleared. In the case of External reset, two identical SPI write Message #0 should be executed to reinitialize Seed register. First SPI Message #0 will clear External reset flag and second SPI Message #0 will finally reinitialize Seed register. In application, writing seed is preferred after checking if RST_ext is 1. (Only External Reset flag is to block writing Seed.) VPWR overvoltage No effect OFF VPWR undervoltage No effect OFF OFF after tLSDx_HD_G OFF after tLSDx_HD_G On No effect Following SPI registers go to initial state Low: A. LSDx Duty cycle or current set point. B. hd_on OFF No effect Following SPI registers go to initial state Low: A. LSDx Duty cycle or current set point. B. hd_on Notes 18. State defines for the duration of the fault and the following reset recovery time period. Restart conditions: SPI write message #0 has first to be executed to clear any reset or fault flags. Then new SPI command can be sent. Table 22. Start point of reset recovery time Fault mode Start point of tRST_REC VINT_A or VINT_D_uv or VCC_uv or DOSV_uv Come back normal voltage of all voltages Watchdog or ALU fault Fall edge of RSTB pin SB0800 32 NXP Semiconductors 6.9.1 Additional safety functions 6.9.1.1 VINT_A or VINT_D undervoltage supervision The SB0800 uses an internal supply for analog functions (VINT_A) and digital functions (VINT_D). The supply voltage VINT_A and VINT_D are supervised for undervoltage. When the voltage becomes lower than each threshold VINT_A_uv and VINT_D_uv, the RSTB pin is asserted low after detection filter time (tVINT). This reset state will continue until the voltage at pin VINT raises again. And if VINT becomes higher than each threshold VINT_A_uv and VINT_D_uv for same filter time (tVINT), the RSTB Pin goes high after reset recovery time (tRST_REC) and the related flag of the SPI register is set to high. For stabilization the internal supply VINT_A & VINT_D requires external capacitors. Two band-gaps are included in the SB0800, one is for the voltage reference and the other is for the diagnostic. The VINT_A and VINT_D voltages are sending through the SPI. SB0800 NXP Semiconductors 33 6.9.1.2 VCC5 supervision See Table 21 Reset condition and reaction. 6.9.1.3 DOSV supervision The supply voltage DOSV is supervised for undervoltage. When the voltage at pin DOSV becomes lower than DOSV_uv, the RST pin is asserted low after detection filter time (tVDUV). This reset state will continue until the voltage at pin DOSV raises again. And if DOSV becomes higher than (DOSV_uv) for same filter time (tVDUV), the RSTB Pin goes high after reset recovery time (tRST_REC) and the related flag of the SPI register is set to high. The P53_CFG pin decides the DOSV pin undervoltage threshold. Pin P53_CFG Condition Description Short to GND 5.0 V DOSV undervoltage threshold Short to VCC5 3.3V DOSV undervoltage threshold Figure 17. Configuration of VCC5 and DOSV for 5.0 V or 3.3 V application 6.9.1.4 Charge pump The charge pump generates a voltage of typically 12 V above the supply VPWR. The charge pump voltage is intended for internal use only. No additional load shall be connected to the CP pin. The charge pump requires a capacitor for energy storage and to cover transients. The voltage difference between CP and VPWR can be read by the SPI. 6.9.1.5 Internal clock supervision (mismatch MAIN-AUX CLK) The SB0800 has two independent clock modules, one is the main supply clock to all SB0800 systems. The other monitors the main clock fault and if a fault is detected, the SB0800 resets with the RST_CLK function (Table 21). This function starts when RSTB is in a high state. Mutual Supervision of Both Main and Auxiliary Clock: Clock monitoring continues to perform comparisons between the two clocks sources, CLK1 and CLK2. When everything is working correctly, both clocks are present and both have the same frequency of 14 MHz. If one of the clocks stops or if clocks are misaligned in frequency more than ±25% of 14 MHz (Table 23), an RSTB reset is generated (Table 21) and a SPI flag is reported (RST_CLK). The reset flag RST_CLK (same as other reset flags) is cleared in “clear on read” fashion, or in other words, the flag is cleared by a SPI Read command that reads the flag. In the case of a clock monitoring fault, the clock monitoring process will restart only after the clock monitoring flag (RST_CLK) is cleared on the first SPI message. If either CLK1or CLK2 disappears indefinitely, the clock monitoring fault will show anywhere from T1 to 2*T2. If clock frequencies are misaligned in more than ±25% of 14 MHz, the clock monitoring fault will show after a time delay of T2, as measured by the reference clock CLK1. The misaligned frequency detection error is measured in time window of T2 and the measurement is based on CLK1 clock as reference, therefore if the CLK1 frequency changes, the time window T2 cannot be guaranteed. SB0800 34 NXP Semiconductors The SB0800 internal clock monitoring function can be disabled by the SPI command (StopCLK2), with no effect of functionality except the clock monitoring function, because CLK1 is activated, but CLK2 is deactivated. Frequency modulation can be controlled by the FM_amp and FM_EM bits (See SPI and data register). The SPI command (FM_EN) enables the frequency modulated oscillator by two deviation frequency to spread the oscillator’s energy over a wide frequency band. There are two kinds of deviation frequencies (350 kHz and 700 kHz), which are decided by the SPI command (FM_amp). This spreading decreases the peak electromagnetic radiation level and improves electromagnetic compatibility (EMC) performance. If preferred, the sequence following by SPI command (StopCLK2), and later on if decided to reactivate the CLK2 (clock monitoring reactivated), a reset clk can be generated due to the fact the clk2 re-start, and can have a settling time > 2*T2, 1.0 ms max. In this case, reset is detected during reset recovery time and the CLK_RST (reading message #0) flag should read in a normal condition. 6.9.1.6 Die temperature warning The SB0800 has 1 temperature warning sensor in the cool place of the die. The threshold of temperature warning is 20 °C below overtemperature. In case of a temperature warning, outputs are not shutdown and the SPI-Bit shows the actual status at accessing time. 6.9.1.7 Ground supervision GND-loss monitors the voltage between PGND (global reference GND) and GND_D. In case of a disconnection of GND_D vs. all other grounds (pin 2, 4, 13, 37, 46, 51, and back side ground are soldered to ground), a detection GND_D disconnect as soon as the GND_D is higher than the threshold (V_GL) vs. others grounds, is reported through the flag FGND via the SPI register and set high after a filter time (tGL). 1. Connection degraded (resistive path) A. GND_D vs other grounds > V_GL but by having Vint_D –GND_D > min voltage required B. SPI communication still possible, and the flag FGND will be at 1 2. Disconnection (open physically) during a sequence (in Normal mode), the logic embedded will be frozen, because the voltage Vint_D –GND_D < min voltage required A. No SPI communication is possible B. If GND_D is reconnected normally, SPI communication recovers and the flag FGND will be at 1 Table 23. Electrical characteristics VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit -20% 45 20% ms — 10 — μs Undervoltage Reset Threshold at Shutdown (falling edge of DOSV) • P53_CFG = Low (< 0.8 V) • P53_CFG = High (> 2.0 V) — — 4.5 2.9 — — V Undervoltage Reset Filter Time — T1 — μs Notes Reset output SB0800 to MCU tRSTB_REC Reset Recovery Time Reset input MCU to SB0800 tRST_MIN Minimum External Reset Time (only for application) DOSV undervoltage DOSVUV_ 5V DOSVUV_ 3P3 tDVUV VCC5 undervoltage VCC5_UV Undervoltage Threshold — 4.5 — V tVCUV Undervoltage Filter Time — T1 — μs Consumption Current • VCC5 = 5.0 V; HD,PD = on; RSTB = high • During SPI communication — — — — 20 10 mA VCC5 supply I_VCC5 I_DOSV SB0800 NXP Semiconductors 35 Table 23. Electrical characteristics (continued) VPWR = 6.0 to 36 V, VCC5 = 4.75 to 5.25 V, DOSV = 3.13 to 5.25 V, TJ = -40 to +125 °C, unless otherwise specified. Symbol Characteristic Min. Typ. Max. Unit Notes Internal logic supply Vint_A Internal Analog Voltage - ILOAD = -10 mA 2.30 2.5 2.8 V Vint_D Internal Digital Voltage - ILOAD = -10 mA 2.30 2.5 2.8 V C_Vint Stabilization Capacitor at V_INT - Low-voltage capacitor ( 10%, the measurement is done at Ton/2. For 3.12% < DC < 10%, the measurement is done at the maximum value between Ton/2 and 3.12% Bit = 10 Bit = 10 Minimum duty cycle (DC) is: 3.12% + 1.56% every two cycles For DC > 10%, the measurement is done at Ton/2. For 3.12% < DC < 10% the regulation current approach up to 3.12% of DC and the measurement is done at the maximum value between Ton/2 and 3.12% For 1.56% < DC < 3.12%, 3.12% of DC and 1.56%. DC are forced every two cycles and no measurement is done during 1.56% of DC. Bit = 11 Minimum duty cycle (DC) is: 3.12% + skipping DC every two cycles For DC > 10%, the measurement is done at Ton/2. For 3.12% < DC < 10% the regulation current approach up to 3.12% of DC and the measurement is done at the maximum value between Ton/2 of DC and 3.12% For DC < 3.12%, the regulation current forces 3.12% and skipping every two cycles and no measurement is done during the skipping mode. Bit = 0 LSDx Feedback = SPI written value Bit = 1 LSDx Feedback = output CR_fb = 0 CR_dis12 01 CR_dis34 00 CR_fb = 1 CR_dis12 = 0 LSD1,2 Current regulation LSD1,2 Current regulation CR_dis12 = 1 LSD1,2 PWM LSD1,2 PWM CR_dis34 = 0 LSD3,4 Current regulation LSD3,4 Current regulation CR_dis34 = 1 LSD3,4 PWM LSD3,4 PWM SB0800 NXP Semiconductors 47 Table 38. Read message B15 B14 B13 B12 B11 P Fmsg X CR_fb B10 B09 Bits P 15 Fmsg 14 CR_fb 12 B06 B05 B04 B03 B02 B01 B00 vpre12 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Feedback of CR_fb CR_dis12 Feedback of CR_dis12 CR_dis34 Feedback of CR_dis34 6.10.3.9 B07 CR_dis CR_dis 12 34 Field vpre12 B08 10-bit ADC of vpre12 09:00 Message #8 Table 39. Write message B15 B14 B13 P B12 B11 B10 MSG_ID Field Bits P 15 MSG_ID 14: 10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0 0 0 0 0 0 0 0 0 B03 B02 B01 B00 Description Parity bit Message Identifier: 01000 Table 40. Read message B15 B14 P Fmsg B13 B12 B11 B10 lsd1_cr lsd2_cr lsd3_cr lsd4_cr er er er er B09 B08 B07 B06 B05 B04 vcp_vpwr SB0800 48 NXP Semiconductors Field Bits P 15 Fmsg 14 lsd1_crer 13 lsd2_crer 12 lsd3_crer 11 lsd4_crer 10 vcp_vpwr 09:00 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Current regulation error detection of LSD1 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD2 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD3 Bit = 0 Normal Bit = 1 Current regulation error detection of LSD4 10-bit ADC of vcp_vpwr SB0800 NXP Semiconductors 49 6.10.3.10 Message #9 Table 41. Write message B15 B14 B13 P B12 B11 B10 MSG_ID Field Bits P 15 MSG_ID 14: 10 LF_PWM_14 B08 B07 B06 X X X X B05 B04 B03 B02 LF_PWM_14 B01 B00 LF_PWM_58 Description Parity bit Message Identifier: 01001 05:03 LF_PWM_58 B09 02:00 Bit = 000 Output PWM frequency of LSD(1~4)= 3.9 kHz Bit = 001 Output PWM frequency of LSD(1~4)= 4.5 kHz Bit = 010 Output PWM frequency of LSD(1~4)= 5.0 kHz Bit = 011 Output PWM frequency of LSD(1~4)= 4.2 kHz Bit = 100 Output PWM frequency of LSD(1~4)= 3.6 kHz Bit = 101 Output PWM frequency of LSD(1~4)= 3.4 kHz Bit = 110 Output PWM frequency of LSD(1~4)= 3.2 kHz Bit = 111 Output PWM frequency of LSD(1~4)= 3.0 kHz Bit = 000 Output PWM frequency of LSD(5~8)= 3.9 kHz Bit = 001 Output PWM frequency of LSD(5~8)= 4.5 kHz Bit = 010 Output PWM frequency of LSD(5~8)= 5.0 kHz Bit = 011 Output PWM frequency of LSD(5~8)= 4.2 kHz Bit = 100 Output PWM frequency of LSD(5~8)= 3.6 kHz Bit = 101 Output PWM frequency of LSD(5~8)= 3.4 kHz Bit = 110 Output PWM frequency of LSD(5~8)= 3.2 kHz Bit = 111 Output PWM frequency of LSD(5~8)= 3.0 kHz Table 42. Read message B15 B14 P Fmsg B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 VINT_A Field Bits P 15 Fmsg 14 VINT_A 09:00 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. 10-bit ADC of internal supply SB0800 50 NXP Semiconductors 6.10.3.11 Message #10 Table 43. Write message B15 B14 B13 P B12 B11 B10 B09 B08 MSG_ID B06 B05 B04 B03 B02 B01 B00 LSD1 duty cycle (8-bit) or current set point (10-bit) Field Bits P 15 MSG_ID 14: 10 LSD1 duty cycle (8-bit) or current set point(10-bit) B07 Description Parity bit Message Identifier: 01010 CR_fb=0 CR_fb=1 CR_dis12= 0 LSD1, 2 current regulation Write current target (10 bits, 0 to 2.25 A) LSD1,2 current regulation Write current target (10 bits, 0 to 2.25 A) CR_dis12= 1 LSD1, 2 PWM Write programmed duty cycle (8 bits at 0%, 100% and 10% to 90%) LSD1[1:0]=XX LSD1,2 PWM Write programmed duty cycle (8 bits at 0%, 100% and 10% to 90%) LSD1[1:0]=XX 09:00 Table 44. Read message B15 B14 P Fmsg B13 B12 B11 B10 lsd1_ oc lsd1_op lsd1_ot Field Bits P 15 Fmsg 14 lsd1_ oc 13 lsd1_op 12 lsd1_ot 11 vds_LSD1 10 LSD1 duty cycle (8-bit) or current read (10-bit) B09 B08 vds_ LSD1 B07 B06 B05 B04 B03 B02 B01 B00 LSD1 duty cycle (8-bit) or current read (10-bit) Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD1 Bit = 0 Normal Bit = 1 Open Load detection of LSD1 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD1 Bit = 0 Normal Bit = 1 VDS detection of LSD1 (information only) CR_fb=0 CR_fb=1 CR_dis12= 0 LSD1,2 current regulation Read current target (to check SPI write) (10 bits, 0 to 2.25 A) LSD1,2 current regulation Output duty cycle value for gate driver (8 bits, for the range to 100%) CR_dis12= 1 LSD1,2 PWM Read programmed PWM duty cycle (to check SPI write) (8 bits at 0%, 100% and 10% to 90%) LSD(1~2)[1:0]=00 LSD1,2 PWM Read hardware ADC current value (10 bits for the range to 4.5A) 09:00 SB0800 NXP Semiconductors 51 6.10.3.12 Message #11 Table 45. Write message B15 B14 B13 P B12 B11 B10 B09 B08 MSG_ID Field Bits P 15 MSG_ID 14: 10 LSD2 duty cycle (8-bit) or current set point(10-bit) B07 B06 B05 B04 B03 B02 B01 B00 LSD2 duty cycle (8bit) or current set point (10-bit) Description Parity bit Message Identifier: 01011 CR_fb=0 CR_fb=1 CR_dis12= 0 LSD1,2 current regulation Write current target (10 bits, 0 to 2.25 A) LSD1,2 current regulation Write current target (10 bits, 0 to 2.25 A) CR_dis12= 1 LSD1,2 PWM Write programmed duty cycle (8 bits at 0%, 100% and 10% to 90%) LSD2[1:0]=XX LSD1,2 PWM Write programmed duty cycle (8 bits at 0%, 100% and 10% to 90%) LSD2[1:0]=XX 09:00 Table 46. Read message B15 B14 P Fmsg B13 B12 B11 B10 lsd2_ oc lsd2_op lsd2_ot Field Bits P 15 Fmsg 14 lsd2_ oc 13 lsd2_op 12 lsd2_ot 11 vds_LSD2 10 LSD2 duty cycle (8-bit) or current read (10-bit) B09 B08 vds_LS D2 B07 B06 B05 B04 B03 B02 B01 B00 LSD2 duty cycle (8-bit) or current read (10-bit) Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD2 Bit = 0 Normal Bit = 1 Open load detection of LSD2 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD2 Bit = 0 Normal Bit = 1 VDS detection of LSD2 (information only) CR_fb = 0 CR_fb=1 CR_dis12= 0 LSD1,2 current regulation Read current target (to check SPI write) (10 bits, 0 to 2.25 A) LSD1,2 current regulation Output duty cycle value for gate driver (8 bits, for the range to 100%) CR_dis12= 1 LSD1,2 PWM Read programmed PWM duty cycle (to check SPI write) (8 bits at 0%, 100% and 10% to 90%) LSD(1~2)[1:0]=00 LSD1,2 PWM Read hardware ADC current value (10 bits for the range to 4.5 A) 09:00 SB0800 52 NXP Semiconductors 6.10.3.13 Message #12 Table 47. Write message B15 B14 B13 P B12 B11 B10 B09 B08 MSG_ID Field B07 B05 B04 B03 B02 B01 B00 LSD3 duty cycle (8-bit) or current set point (10-bit) Bits Description P 15 Parity bit MSG_ID 14: 10 Message Identifier: 01100 LSD3 duty cycle (8-bit) or current set point(10-bit) B06 CR_fb=0 CR_fb=1 CR_dis34= 0 LSD3,4 current regulation Write current target (10 bits, 0 to 2.25 A) LSD3,4 current regulation Write current target (10 bits, 0 to 2.25 A) CR_dis34= 1 LSD3,4 PWM Write programmed duty cycle (8 bits at 0%, 100% and 10% to 90%) LSD3[1:0]=XX LSD3,4 PWM Write programmed duty cycle (8 bits at 0%, 100% and 10% to 90%) LSD3[1:0]=XX 09:00 Table 48. Read message B15 B14 P Fmsg B13 B12 B11 lsd3_ oc lsd3_op lsd3_ot B10 vds_LS D3 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 LSD3 duty cycle (8-bit) or current read (10-bit) SB0800 NXP Semiconductors 53 Field Bits P 15 Fmsg 14 lsd3_ oc 13 lsd3_op 12 lsd3_ot 11 vds_LSD3 10 LSD3 duty cycle (8-bit) or current read (10-bit) 6.10.3.14 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD3 Bit = 0 Normal Bit = 1 Open load detection of LSD3 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD3 Bit = 0 Normal Bit = 1 VDS detection of LSD3 (information only) CR_fb=0 CR_fb=1 CR_dis34= 0 LSD3,4 current regulation Read current target (to check SPI write) (10 bits, 0 to 2.25 A) LSD3,4 current regulation Output duty cycle value for gate driver (8 bits, for the range to 100%) CR_dis34= 1 LSD3,4 PWM LSD3,4 PWM Read programmed PWM duty cycle (to check SPI write) Read hardware ADC current value (8 bits at 0%, 100% and 10% to 90%) (10 bits for the range to 4.5 A) LSD(3~4)[1:0]=00 09:00 Message #13 Table 49. Write message B15 B14 B13 P B12 B11 B10 B09 B08 MSG_ID Field Bits P 15 MSG_ID 14: 10 LSD4 duty cycle (8-bit) or current set point (10-bit) B07 B06 B05 B04 B03 B02 B01 B00 LSD4 duty cycle (8-bit) or current set point (10-bit) Description Parity bit Message Identifier: 01101 CR_fb=0 CR_fb=1 CR_dis34= 0 LSD3, 4 current regulation Write current target (10 bits for the range to 2.25 A) LSD3, 4 current regulation Write current target (10 bits for the range to 2.25 A) CR_dis34= 1 LSD3,4 PWM Write programmed duty cycle (8 bits for the range to 100%) LSD4[1:0]=XX LSD3, 4 PWM Write programmed duty cycle (8 bits for the range to 100%) LSD4[1:0]=XX 09:00 SB0800 54 NXP Semiconductors Read message B15 B14 P Fmsg B13 B12 B11 lsd4_ oc lsd4_op lsd4_ot Field Bits P 15 Fmsg 14 lsd4_ oc 13 lsd4_op 12 lsd4_ot 11 vds_LSD4 10 LSD4 duty cycle (8-bit) or current read (10-bit) 6.10.3.15 B10 B09 B08 vds_LS D4 B07 B06 B05 B04 B03 B02 B01 B00 LSD4 duty cycle (8-bit) or current read (10-bit) Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD4 Bit = 0 Normal Bit = 1 Open load detection of LSD4 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD4 Bit = 0 Normal Bit = 1 VDS detection of LSD4 (information only) CR_fb=0 CR_fb=1 CR_dis34= 0 LSD3,4 current regulation Read current target (to check SPI write) (10 bits, 0 to 2.25 A) LSD3,4 current regulation Output duty cycle value for gate driver (8 bits, for the range to 100%) CR_dis34= 1 LSD3,4 PWM Read programmed PWM duty cycle (to check SPI write) (8 bits at 0%, 100% and 10% to 90%) LSD(3~4)[1:0]=00 LSD3,4 PWM Read hardware ADC current value (10 bits for the range to 4.5 A) 09:00 Message #14 Table 50. Write message B15 B14 B13 P B12 B11 B10 B09 B08 B07 MSG_ID B06 B05 B04 B03 B02 LSD5 duty cycle (8bit) Field Bits P 15 MSG_ID 14: 10 Message Identifier: 01110 LSD5 duty cycle 09:02 LSD5 PWM duty cycle B01 B00 X X B01 B00 X X Description Parity bit Read message B15 B14 P Fmsg B13 B12 B11 lsd5_ oc lsd5_op lsd5_ot B10 vds_ LSD5 B09 B08 B07 B06 B05 LSD5 duty cycle (8bit) B04 B03 B02 SB0800 NXP Semiconductors 55 Field Bits P 15 Fmsg 14 lsd5_ oc 13 lsd5_op 12 lsd5_ot 11 vds_LSD5 10 LSD5 duty cycle (8-bit) 09:02 6.10.3.16 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD5 Bit = 0 Normal Bit = 1 Open load detection of LSD5 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD5 Bit = 0 Normal Bit = 1 VDS detection of LSD5 (information only) Read Programmed PWM duty cycle (to check SPI write) (8 bits for the range to 100%) Message #15 Table 51. Write message B15 B14 B13 P B12 B11 B10 B09 B08 B07 MSG_ID B06 B05 B04 B03 B02 LSD6 duty cycle (8bit) Field Bits P 15 MSG_ID 14: 10 Message Identifier: 01111 LSD6 duty cycle 09:02 LSD6 PWM duty cycle B01 B00 X X B01 B00 X X Description Parity bit Read message B15 B14 P Fmsg B13 B12 B11 lsd6_ oc lsd6_op lsd6_ot B10 vds_ LSD6 B09 B08 B07 B06 B05 LSD6 duty cycle (8bit) B04 B03 B02 SB0800 56 NXP Semiconductors Field Bits P 15 Fmsg 14 lsd6_ oc 13 lsd6_op 12 lsd6_ot 11 vds_LSD6 10 LSD6 duty cycle (8-bit) 09:02 6.10.3.17 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD6 Bit = 0 Normal Bit = 1 Open load detection of LSD6 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD6 Bit = 0 Normal Bit = 1 VDS detection of LSD6 (information only) Read Programmed PWM duty cycle (to check SPI write) (8 bits for the range to 100%) Message #16 Table 52. Write message B15 B14 B13 P B12 B11 B10 B09 B08 B07 MSG_ID B06 B05 B04 B03 B02 LSD7 duty cycle (8bit) Field Bits P 15 MSG_ID 14: 10 Message Identifier: 10000 LSD7 duty cycle 09:02 LSD7 PWM duty cycle B01 B00 X X B01 B00 X X Description Parity bit Read message B15 B14 P Fmsg B13 B12 B11 lsd7_ oc lsd7_op lsd7_ot B10 vds_ LSD7 B09 B08 B07 B06 B05 LSD7 duty cycle (8bit) B04 B03 B02 SB0800 NXP Semiconductors 57 Field Bits P 15 Fmsg 14 lsd7_ oc 13 lsd7_op 12 lsd7_ot 11 vds_LSD7 10 LSD7 duty cycle (8-bit) 09:02 6.10.3.18 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD7 Bit = 0 Normal Bit = 1 Open load detection of LSD7 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD7 Bit = 0 Normal Bit = 1 VDS detection of LSD7 (information only) Read Programmed PWM duty cycle (to check SPI write) (8 bits for the range to 100%) Message #17 Table 53. Write message B15 B14 B13 P B12 B11 B10 B09 B08 B07 MSG_ID B06 B05 B04 B03 B02 LSD8 duty cycle (8bit) Field Bits P 15 MSG_ID 14: 10 Message Identifier: 10001 LSD8 duty cycle 09:02 LSD8 PWM duty cycle B01 B00 X X B01 B00 X X Description Parity bit Read message B15 B14 P Fmsg B13 B12 B11 lsd8_ oc lsd8_op lsd8_ot B10 vds_ LSD8 B09 B08 B07 B06 B05 LSD7 duty cycle (8bit) B04 B03 B02 SB0800 58 NXP Semiconductors Field Bits P 15 Fmsg 14 lsd8_ oc 13 lsd8_op 12 lsd8_ot 11 vds_LSD8 10 LSD8 duty cycle (8-bit) 09:02 6.10.3.19 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shutdown of LSD8 Bit = 0 Normal Bit = 1 Open load detection of LSD8 Bit = 0 Normal Bit = 1 Overtemperature shutdown of LSD7 Bit = 0 Normal Bit = 1 VDS detection of LSD8 (information only) Read Programmed PWM duty cycle (to check SPI write) (8 bits for the range to 100%) Message #18 Table 54. Write message B15 B14 B13 P B12 B11 B10 MSG_ID B09 B08 X X B07 B06 B05 B04 B03 B02 B01 B00 B02 B01 B00 MR Field Bits Description P 15 MSG_ID 14: 10 Message Identifier: 10010 MR 07:00 Monitoring result of MCU Parity bit Table 55. Read message B15 B14 B13 B12 B11 B10 P Fmsg X X X HD_lkg B09 B08 B07 B06 B05 B04 ERR_CNT B03 AR Field Bits Description P 15 Parity bit Fmsg 14 Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 0 Normal HD_lkg 11 Bit = 1 High-side driver leakage detected ERR_CNT 10:08 3 bit error counter value of monitoring logic AR 07:00 Monitoring result of SB0800 SB0800 NXP Semiconductors 59 6.10.3.20 Message #19 to 23 Reserved 6.10.3.21 Message #24 Table 56. Write message B15 B14 B13 P B12 B11 B10 MSG_ID Field Bits P 15 MSG_ID 14: 10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0 0 0 0 0 0 0 0 0 B03 B02 B01 B00 Description Parity bit Message Identifier: 11000 Table 57. Read message B15 B14 B13 B12 B11 B10 P Fmsg HS_oc HS_op HS_ot vds_HS Field Bits P 15 Fmsg 14 HS_oc 13 HS_op 12 HS_ot 11 vds_HS 10 AD_RST1 09:00 6.10.3.22 B09 B08 B07 B06 B05 B04 AD_RST1 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. Bit = 0 Normal Bit = 1 Overcurrent shut down of high-side Bit = 0 Normal Bit = 1 Open load detection of high-side Bit = 0 Normal Bit = 1 Overtemperature shut down of high-side Bit = 0 Normal Bit = 1 Vds detection of high-side (information only) 10-bit ADC of ADIN1 Message #25 Table 58. Write message B15 B14 P B13 B12 B11 MSG_ID Field Bits B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0 0 0 0 0 0 0 0 0 Description SB0800 60 NXP Semiconductors Parity bit P 15 MSG_ID 14: 10 Message Identifier: 11001 Table 59. Read message B15 B14 P Fmsg B13 B12 B11 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 AD_RST2 Field Bits P 15 Fmsg 14 AD_RST2 09:00 6.10.3.23 B10 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. 10-bit ADC of ADIN2 Message #26 Table 60. Write message B15 B14 B13 P B12 B11 B10 MSG_ID Field Bits P 15 MSG_ID 14: 10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 X X X X X X X X X X B03 B02 B01 Description Parity bit Message Identifier: 11010 Table 61. Read message B15 B14 P Fmsg B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B00 AD_RST3 Field Bits P 15 Fmsg 14 AD_RST3 09:00 Description Parity bit Bit = 0 Parity bit is correct. Previous transfer was valid. Bit = 1 Parity bit is not correct. Error detected during previous transfer. 10-bit ADC of ADIN3 SB0800 NXP Semiconductors 61 7 Typical applications 7.1 Application diagrams This section presents a typical Industrial applications schematic using SB0800, as shown in Figure 20. Figure 20. Industrial valves and pump control unit simplified diagram SB0800 62 NXP Semiconductors 8 Packaging 8.1 Package mechanical dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Package 10 x 10, 64-Pin LQFP Exposed Pad, with 0.5 mm pitch, and a 6.1 x 6.1 exposed pad Suffix AE Package outline drawing number 98ASA10763D SB0800 NXP Semiconductors 63 SB0800 64 NXP Semiconductors SB0800 NXP Semiconductors 65 SB0800 66 NXP Semiconductors 9 Revision history Revision Date 1.0 5/2014 • Initial release 11/2014 • Increased the operating voltage of the device to 36 V • Updated the parameters with new operating value 4/2015 • Changed doc classification from Product Preview to Advance Information • Corrected form and style 5/2015 • Updated document title 5/2015 • Added tVAM to Table 20 • Added Figure 16 8/2016 • Updated document to NXP form and style 2.0 3.0 Description of changes SB0800 NXP Semiconductors 67 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. Home Page: NXP.com There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits Web Support: http://www.nxp.com/support products herein. based on the information in this document. NXP reserves the right to make changes without further notice to any NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. NXP, the NXP logo, Freescale, the Freescale logo, SafeAssure, the SafeAssure logo, and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: MC34SB0800 Rev. 3.0 8/2016