MC34VR500V4ES

NXP Semiconductors Technical Data Document Number: MC34VR500 Rev. 10, 3/2020 Multi-output DC/DC regulator for QorIQ LS1/T1 family of communications processors 34VR500 Power Management The 34VR500 is a high performance, highly integrated, multi-output, SMARTMOS, DC/DC regulator solution, with integrated power MOSFETs ideally suited for the LS1/T1 family of communication processors. Integrating four switching and five linear regulators, the 34VR500 provides power to the complete system, including the processor, DDR memory, and system peripherals. Features: • Four buck converters: • SW1: 4.5 A • SW2: 2.0 A • SW3: 2.5 A • SW4: 1.0 A, (VTT tracking regulator) • Five general purpose linear regulators • DDR termination reference voltage (DDR3L and DDR4) • Programmable low-power modes • I2C control of all the regulators • Power Control Logic with processor interface and event detection Applications: • Internet of things (IoT) gateway • Mobile wireless router • MFP printer • Network attached storage • Automatic teller machine LS102X VR500 SW1 POWER CONTROL LOGIC 3.3 VIN BUS ES SUFFIX (WF-TYPE) 98ASA00589D 56 QFN-EP WF8X8 SW2 LDO2 LDO4 LDO5 SW3 SW4 REFOUT VDD TA_BB_VDD VDDC OVDD1/2 L1VDD OVDD GVDD DDR3 VTT LDO1 HDMI LDO3 Ethernet Figure 1. 34VR500 simplified application diagram © NXP B.V. 2020. Table of Contents 1 2 3 4 5 6 7 8 9 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3 34VR500 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.4 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 34VR500 2 NXP Semiconductors ORDERABLE PARTS 1 Orderable parts This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.nxp.com and perform a part number search for the following device numbers. Table 1. Orderable part variations Temperature (TA) Part number Package SW4 VTT mode MC34VR500V1ES Enabled MC34VR500V2ES Disabled MC34VR500V3ES Enabled MC34VR500V4ES Enabled Processor LS1020/21/22A MC34VR500V5ES -40 °C to +105 °C 56 QFN 8x8 mm Enabled Reference design DDR memory LS1021A IOT Gateway TWR-LS1021A DDR3L (VTT = 0.675 V) Notes N/A LS1043/23A T1023/13 LS1043ARDB T1023RDB DDR4 (VTT = 0.6 V) DDR3L (VTT = 0.675 V) MC34VR500V6ES Enabled LS1024A MC34VR500V7ES Enabled LS1020/21/22A MC34VR500V8ES Disabled LS1046A LS1046ARDB-PA MC34VR500V9ES Disabled LS1028 LS1028A-RDB MC34VR500VAES Enabled LS1043/23A T1023/13 LS1043ARDB T1023RDB MC34VR500VBES Disabled LX2160 (1)(2) DDR4 (VTT = 0.6 V) DDR4 (VTT = 0.6 V) N/A Notes 1. For tape and reel, add an R2 suffix to the part number. 2. See Table 8 for the start-up configuration. 34VR500 NXP Semiconductors 3 INTERNAL BLOCK DIAGRAM 2 Internal block diagram VR500 VLDOIN1 LDO1 LDO1 250 mA LDO2 LDO2 100 mA VLDOIN23 LDO3 LDO3 350 mA LDO4 LDO4 100 mA VLDOIN45 LDO5 LDO5 200 mA Buck Regulator Reference Generation LDO Reference Generation SW1 Buck Regulator 4500 mA FB1 SW2 Buck Regulator 2000 mA FB2 SW3 Buck Regulator 2500 mA FB3 SW4 Buck Regulator 1000 mA FB4 PVIN1 LX1 PVIN2 LX2 PVIN3 LX3 PVIN4 LX4 EPAD VDIG I C Interface REFOUT Main State Machine Clocks and Resets REFIN VHALF VDIG Regulator (Internal Use Only) VCC Regulator (Internal Use Only) VIN ICTEST1 EN VCC SGND4 2 ICTEST2 INTB VCCI2C SCL SDA Main and Standby Bandgap STBY PORB VBG VBIAS Figure 2. 34VR500 simplified internal block diagram 34VR500 4 NXP Semiconductors PIN CONNECTIONS SDA VBG VDIG VIN VCC SGND4 ICTEST2 DNC DNC DNC VBIAS Pinout diagram SCL 3.1 VCCI2C Pin connections EN 3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 INTB 1 42 DNC DNC 2 41 LDO5 PORB 3 40 VLDOIN45 STBY 4 39 LDO4 ICTEST1 5 38 FB3 DNC 6 37 PVIN3 PVIN1 7 LX1 8 LX1 9 36 LX3 EP 35 LX3 34 PVIN3 33 DNC PVIN1 10 LX1 32 SGND3 11 31 REFOUT PVIN1 12 30 REFIN FB1 13 29 VHALF 21 22 23 24 25 26 27 28 PVIN2 FB2 LDO2 VLDOIN23 LDO3 LDO1 20 PVIN2 VLDOIN1 19 LX2 18 LX4 17 PVIN4 16 FB4 15 DNC 14 SGND2 SGND1 Figure 3. 34VR500 pinout diagram 3.2 Pin definitions Table 2. 34VR500 Pin Definitions Pin number Pin name Pin function Max. rating Type 1 INTB O 3.6 V Digital 2, 6, 16, 33, 42, 44, 45, 46 DNC — — Reserved 3 PORB O 3.6 V Digital Open drain reset output to processor. 4 STBY I 3.6 V Digital Standby input signal from processor 5 ICTEST1 I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. Definition Open drain interrupt signal to processor Leave floating 34VR500 NXP Semiconductors 5 PIN CONNECTIONS Table 2. 34VR500 Pin Definitions (continued) Pin number Pin name Pin function Max. rating Type Definition 7, 10, 12 PVIN1 (3) I 4.8 V Analog Input to SW1 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 8, 9, 11 LX1 (3) O 4.8 V Analog SW1 switching node connection 13 FB1 (3) I 3.6 V Analog Output voltage feedback for SW1. Route this trace separately from the high current path and terminate at the output capacitance. 14 SGND1 GND - GND Signal ground for SW1 regulator. Connect to ground plane directly. 15 SGND2 GND - GND Signal ground for SW2 and SW4 regulators. Connect to ground plane directly. 17 VLDOIN1 I 3.6 V Analog Input supply for LDO1. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 18 LDO1 O 2.5 V Analog LDO1 regulator output, Bypass with a 4.7 μF ceramic output capacitor. 19 FB4 (3) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high current path and terminate at the output capacitance. 20 PVIN4 (3) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 21 LX4 (3) O 4.8 V Analog Regulator 4 switching node connection 22 (3) O 4.8 V Analog Regulator 2 switching node connection LX2 23, 24 PVIN2 (3) I 4.8 V Analog Input to SW2 regulator. Connect pins 23 and 24 together and bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to these pins as possible. 25 FB2 (3) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high current path and terminate at the output capacitance. 26 LDO2 O 3.6 V Analog LDO2 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 27 VLDOIN23 I 3.6 V Analog Input supply for LDO2 and LDO3. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 28 LDO3 O 3.6 V Analog LDO3 regulator output, Bypass with a 4.7 μF ceramic output capacitor. 29 VHALF I 3.6 V Analog Half supply reference for DDR reference. 30 REFIN I 3.6 V Analog REFOUT regulator input. Bypass with at least 1.0 μF decoupling capacitor as close to the pin as possible. 31 REFOUT O 3.6 V Analog REFOUT regulator output 32 SGND3 GND - GND Ground reference for the SW3 regulator. Connect directly to ground plane. 34, 37 PVIN3 (3) I 4.8 V Analog Input to SW3 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as close to the pin as possible. 35, 36 LX3 (3) O 4.8 V Analog Regulator SW3 switching node connection 38 FB3 (3) I 3.6 V Analog Output voltage feedback for SW3. Route this trace separately from the high current path and terminate at the output capacitance. 39 LDO4 O 3.6 V Analog LDO4 regulator output. Bypass with a 2.2 μF ceramic output capacitor. 40 VLDOIN45 I 4.8 V Analog Input supply for LDO4 and LDO5. Bypass with a 1.0 μF decoupling capacitor as close to the pin as possible. 43 VBIAS I 1.8 V Analog Bypass the pin with a 0.47 μF capacitor. 41 LDO5 O 3.6 V Analog LDO5 regulator output. By pass with a 2.2 μF ceramic output capacitor. 47 ICTEST2 I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. 48 SGND4 GND - GND 49 VCC O 3.6 V Analog Ground for the main band gap regulator. Connect directly to ground plane. Analog Core supply 34VR500 6 NXP Semiconductors PIN CONNECTIONS Table 2. 34VR500 Pin Definitions (continued) Pin number Pin name Pin function Max. rating Type 50 VIN I 4.8 V Analog Main chip supply 51 VDIG O 1.5 V Analog Digital Core supply 52 VBG O 1.5 V Analog Main band gap reference. Bypass with 0.22uF capacitor. 53 SDA I/O 3.6 V Digital I2C data line (Open drain) 54 SCL I 3.6 V Digital I2C clock 55 VCCI2C I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor 56 EN I 3.6 V Digital Enable input. Connect to the processor. Pull-up via an 8.0 kΩ to 100 kΩ to VBIAS if required - EP GND - GND Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. Definition Notes 3. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected to the VIN pin with a 0.1 μF bypass capacitor. 34VR500 NXP Semiconductors 7 GENERAL PRODUCT CHARACTERISTICS 4 General product characteristics 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. Symbol Description Value Unit -0.3 to 4.8 V ±2000 ±500 V Notes Electrical ratings VIN Main input supply voltage ESD Ratings Human Body Model Charge Device Model VESD (4) Notes 4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 4.2 Thermal characteristics Table 4. Thermal ratings Symbol Description (rating) Min. Max. Unit Notes Thermal ratings TA Ambient Operating Temperature Range -40 105 °C TJ Operating Junction Temperature Range -40 125 °C Storage Temperature Range -65 150 °C – Note 7 °C (6) (7) Junction to Ambient Natural Convection Four layer board (2s2p) Eight layer board (2s6p) – – 28 15 °C/W (8) (9) (10) Junction to Ambient (at 200 ft/min) Four layer board (2s2p) – 22 °C/W (8) (10) Junction to Board – 10 °C/W (11) Junction to Case Bottom – 1.2 °C/W (12) TST TPPRT Peak Package Reflow Temperature (5) QFN56 Thermal resistance and package dissipation ratings RθJA RθJMA RθJB RΘJCBOTTOM 34VR500 8 NXP Semiconductors GENERAL PRODUCT CHARACTERISTICS Table 4. Thermal ratings (continued) Symbol ΨJT Description (rating) Junction to Package Top Natural Convection Min. Max. Unit Notes – 2.0 °C/W (12) Notes 5. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 5 for thermal protection features. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 7. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable parts, and review parametrics. 8. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 9. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. 10. Per JEDEC JESD51-6 with the board horizontal. 11. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 13. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD512. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 4.2.1 Power dissipation During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the thermal management and to avoid overheating, the 34VR500 provides thermal protection. An internal comparator monitors the die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register INTSENSE0. In the event of excessive power dissipation, thermal protection circuitry will shut down the 34VR500. This thermal protection will act above the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protection is not tripped under normal conditions. Table 5. Thermal protection thresholds Parameter Min. Typ. Max. Units Thermal 110 °C Threshold (THERM110) 100 110 120 °C Thermal 120 °C Threshold (THERM120) 110 120 130 °C Thermal 125 °C Threshold (THERM125) 115 125 135 °C Thermal 130 °C Threshold (THERM130) 120 130 140 °C Thermal Warning Hysteresis 2.0 – 4.0 °C Thermal Protection Threshold 130 140 150 °C Notes 34VR500 NXP Semiconductors 9 GENERAL PRODUCT CHARACTERISTICS 4.3 Electrical characteristics 4.3.1 I/O specifications Table 6. General PMIC static characteristics. TA = -40 to 105 °C, VVIN = 2.8 to 4.5 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V ±4.0%, typical external component values and full load current range, unless otherwise noted. Pin Name EN PORB SCL SDA INTB STBY 4.3.2 Parameter Load Condition Min. Max. Unit VIL – 0.0 0.2 *VVBIAS V VIH – 0.8 *VVBIAS 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VVIN VVIN V VIL – 0.0 0.2 * VVCCI2C V VIH – 0.8 * VVCCI2C 3.6 V VIL – 0.0 0.2 * VVCCI2C V VIH – 0.8 * VVCCI2C 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7 * VVCCI2C VVCCI2C V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VVIN VVIN V VIL – 0.0 0.2 *VVBIAS V VIH – 0.8 *VVBIAS 3.6 V Notes Current consumption Table 7. Current consumption summary TA = -40 to 105 °C, (See Table 3), VVIN = 3.6 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V ±4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VVIN = 3.6 V, VVCCI2C = 3.3 V, and 25 °C, unless otherwise noted. Mode 34VR500 conditions System conditions Typ. Max. Unit Notes Off Wake-up from EN active 32 k RC on All other blocks off VIN ≥ UVDET PMIC able to wake-up 17 25 μA (14) (15) Sleep Wake-up from EN active Trimmed reference active SW3 PFM Trimmed 16 MHz RC off 32 k RC on REFOUT disabled DDR memories in self refresh 122 250 μA (15) 34VR500 10 NXP Semiconductors GENERAL PRODUCT CHARACTERISTICS Table 7. Current consumption summary (continued) TA = -40 to 105 °C, (See Table 3), VVIN = 3.6 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V ±4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VVIN = 3.6 V, VVCCI2C = 3.3 V, and 25 °C, unless otherwise noted. Mode Standby 34VR500 conditions SW1 in PFM SW2 in PFM SW3 in PFM SW4 in PFM Trimmed 16 MHz RC enabled Trimmed reference active LDO1 - 5 enabled REFOUT enabled System conditions Typ. Max. Unit Notes Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 297 550 μA (15) Notes 14. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically. 15. For PFM operation (as defined in Table 23). 34VR500 NXP Semiconductors 11 GENERAL DESCRIPTION 5 General description The 34VR500 is a high performance, highly integrated, multi-output, DC/DC regulator solution, with integrated power MOSFETs ideally suited for the LS1/T1 family of communication processors. 5.1 Features This section summarizes the 34VR500 features. • Input voltage range: 2.8 V to 4.5 V • Buck regulators • Four independent outputs • SW1, 4.5 A; 0.625 V to 1.875 V • SW2, 2.0 A; 0.625 V to 3.3 V • SW3, 2.5 A; 0.625 V to 3.3 V • SW4, 1.0 A; operates in VTT mode for DDR termination at 50 % of SW3 for 34VR500V1, 34VR500V3, 34VR500V4, 34VR500V5, 34VR500V6, 34VR500V7, 34VR500VA and 0.625 V to 1.975 V for 34VR500V2, 34VR500V8, 34VR500V9 • Dynamic voltage scaling • Modes: PWM, PFM, APS • Programmable output voltage • Programmable current limit • Programmable soft start • Programmable PWM switching frequency • Programmable OCP with fault interrupt • LDOs • Five general purpose LDOs • LDO1, 0.80 V to 1.55 V, 250 mA • LDO2, 1.8 V to 3.3 V, 100 mA • LDO3, 1.8 V to 3.3 V, 350 mA • LDO4, 1.8 V to 3.3 V, 100 mA • LDO5, 1.8 V to 3.3 V, 200 mA • Soft start • DDR memory reference voltage • REFOUT, 10 mA • 16 MHz internal master clock • I2C interface • User programmable Standby, Sleep, and OFF modes 34VR500 12 NXP Semiconductors GENERAL DESCRIPTION 5.2 Functional block diagram MC34VR500 Functional Block Diagram Start-up Configuration (Factory programmable) Power Generation Vo1 Vo4 SW1 (0.625 - 1.875 V) 4.5 A SW2 (0.625 – 3.3 V) 2.0 A SW4 (0.625 - 1.975 V) 1.0 A VT T o ption SW3 (0.625 – 3.3 V) 2.5 A LDO1 (0.8 - 1.55 V) 250 mA LDO2 (1.8 - 3.3 V) 100 mA Vo2 Voltage Phasing and Frequency Selection Sequence and Timing Vo3 Logic and Control LDO3 (1.8 – 3.3 V) 350 mA LDO4 (1.8 - 3.3 V) 100 mA Parallel MCU I nterf ace Regulat or Control 2 I C Communication & Registers Fault Detection & Protection LDO5 (1.8 - 3.3 V) 200 mA Thermal Current Limit Short-circuit Figure 4. 34VR500 functional block diagram 5.3 Functional description 5.3.1 Power generation The 34VR500 PMIC features four buck regulators, five general purpose LDOs, and a DDR voltage reference to supply voltages for the processor, memory, and peripheral devices. Depending on the system power path configuration, the five general purpose LDO regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific REFOUT voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination 5.3.2 Control logic The 34VR500 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including interrupt and reset. Startup voltage and sequence are internally programed. After power up, the regulator voltages can be changed via I2C. The 34VR500 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. 34VR500 NXP Semiconductors 13 GENERAL DESCRIPTION 5.3.2.1 Interface signals EN EN is an input signal to the IC that generates a turn-on event. Refer to section Turn on events for more details. STBY STBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STBY can be configured as active high or active low using the STBYINV bit. Refer to the section Standby mode for more details. PORB PORB is an open-drain, active low output. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 8 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. INTB INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is deasserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit. 34VR500 14 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6 Functional block requirements and behaviors 6.1 Start-up The 34VR500 starts up from the internal configuration, which is hard-coded into the device. However, the 34VR500 can be controlled through the I2C port after the Start-up sequence. It is also possible to modify the contents of the Internal Registers via the bus I2C to modify the start up parameters (see section Start sequence creation). 6.1.1 Device start-up configuration Table 8 shows the internal configuration for the 34VR500V1, 34VR500V2, 34VR500V3, 34VR500V4, 34VR500V5, 34VR500V6, 34VR500V7, 34VR500V8, 34VR500V9, 34VR500VA, 34VR500VB. Table 8. Start-up configuration Registers 34VR500V1 34VR500V2 34VR500V3 34VR500V4 34VR500V5 34VR500V6 34VR500V7 34VR500V8 34VR500V9 34VR500VA 34VR500VB Default I2C Address 0x08 LDO2_VOLT 1.8 V 1.8 V 1.8 V 2.5 V 2.5 V 1.8 V 1.8 V 2.5 V 2.5 V 2.5 V 3.3 V LDO2_SEQ 1 1 1 2 2 2 1 4 5 2 2 — 2.5 V 2.5 V 2.5 V LDO3_VOLT LDO3_SEQ 1 1 3 2 2 4 3 4 — 2 3 LDO4_VOLT 2.5 V 2.5 V 2.5 V 1.8 V 1.8 V 3.0 V 2.5 V 1.8 V 2.5 V 1.8 V 1.8 V LDO4_SEQ 1 1 1 3 3 5 1 5 8 3 — LDO5_VOLT 1.8 V 1.8 V 1.8 V 3.3 V 3.3 V 3.3 V 1.8 V 3.3 V — 3.3 V 3.3 V LDO5_SEQ 1 1 1 3 3 5 1 7 — 3 — SW1_VOLT 1.0 V 1.0 V 1.0 V 1.5 V 1.5 V 1.2 V 1.0 V 0.85 V 1.0 V 1.8 V 1.2 V 1 5 1 3 2 SW1_SEQ SW2_VOLT 1.0 V 1.0 V 1.0 V 1.8 V 1.8 V 1.1 V 1.0 V 1.35 V 2.5 V 1.35 V 1.8 V SW2_SEQ 2 2 2 1 1 1 2 1 2 1 1 SW3_VOLT 1.35 V 1.35 V 1.2 V 1.2 V 1.35 V 1.5 V 1.2 V 1.8 V 1.8 V 1.2 V 0.9 V SW3_SEQ 3 3 3 12 12 3 3 1 3 12 1 SW4_VOLT VTT 1.8 V VTT VTT VTT VTT VTT 1.0 V 1.35 V VTT VTT SW4_SEQ 3 3 3 12 12 3 3 5 4 12 — REFOUT_SEQ 3 3 3 12 12 3 3 — 4 12 3 LDO1_VOLT 1.2 V 1.2 V 1.2 V 1.35 V 1.35 V 1.1 V 1.35 V — — 1.35 V 1.35 V LDO1_SEQ 4 4 4 1 12 1 4 — — 1 — PU CONFIG, SEQ_CLK_SPEED 1.0 ms PU CONFIG, SWDVS_CLK 6.25 mV/μs SW1 CONFIG 2.0 MHz SW2 CONFIG 2.0 MHz SW3 CONFIG 2.0 MHz SW4 CONFIG 2.0 MHz 34VR500 NXP Semiconductors 15 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS UVDET VIN tD1 tR1 EN tD2 tR2 LDO2,3,4,5 tD3 tR2 SW1,2 tD3 tR2 SW3,4 REFOUT TD3 LDO1 tR2 tD4 tR3 PORB Figure 5. Starting sequence: example for V1 and V2 Table 9. 34VR500V1 and V2 start-up sequence timing Parameter Typ. Unit Turn-on delay 6.0 ms tR1 Rise time of EN (16) ms tD2 Turn-on delay of first regulator 2.5 ms 0.2 ms tD1 Description (17) tR2 Rise time of regulators tD3 Delay between regulators 1.0 ms tD4 Turn-on delay of PORB 2.0 ms tR3 Rise time of PORB 0.2 ms Notes 16. Depends on the external signal driving EN. 17. Rise time is a function of slew rate of regulators and nominal voltage selected. 34VR500 16 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.1.2 Start sequence creation The 34VR500 powers up based on the contents of the internal registers. Depending on certain bit settings, the internal registers are loaded from different sources, as shown in Figure 6. Figure 6. Starting sequence The contents of the internal registers are initialized to zero when a valid VIN is first applied. The values that are then loaded into the internal registers depend on the value of the TBB_POR (the initial value of TBB_POR is always “0”): • If TBB_POR = 0 the values are loaded from the Default Sequence (this is the case always for first starting) • If TBB_POR = 1 the values are loaded from the internal RAM. VIN must be valid to maintain the contents of the internal RAM. To power on with the contents of the internal RAM, the following conditions must exist: • VIN is valid • TBB_POR = 1 and there is a valid turn-on event via the EN pin To keep a regulator off during a start-up sequence is to set its sequence to 0. This corresponds to the XX_SEQ setting of 0x00. For example, 0x01 corresponds to a sequence of 1, and so on. 34VR500 NXP Semiconductors 17 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Figure 7 explains how to start from a new configuration. First VIN Applied 34VR500 regulators will not turn on Keep EN pin in low state Program the new start sequence and set TBB_POR to 1 I2C programming + TBB_POR = 1 Create a Turn On event via the EN pin Turn On event EN pin to high state TBB_POR TBB_POR = 1 Start from the Internal RAM TBB_POR = 0 Start from the Default Sequence Figure 7. Modifying a starting sequence Table 95 shows the portion of the register map concerning the programming of a new starting sequence. 6.2 16 MHz and 32 kHz clocks There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within -8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions: • VIN < UVDET • All regulators are in SLEEP mode • All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions: • During start-up, VIN > UVDET In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 20 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and ENI interrupts, which are referenced to the 32 kHz untrimmed clock. Table 10. 16 MHz clock specifications TA = -40 to 105 °C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V ±4.0%, and typical external component values. Typical values are characterized at VVIN = 3.6 V, and 25 °C, unless otherwise noted. Symbol VIN Parameters Operating Voltage from the VIN pin Min. Typ. Max. Units 2.8 – 4.5 V Notes 34VR500 18 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 10. 16 MHz clock specifications TA = -40 to 105 °C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V ±4.0%, and typical external component values. Typical values are characterized at VVIN = 3.6 V, and 25 °C, unless otherwise noted. f16MHZ 16 MHz Clock Frequency 14.7 16 17.3 MHz f2MHZ 2.0 MHz Clock Frequency 1.84 – 2.16 MHz (18) Notes 18. 2.0 MHz clock is derived from the 16 MHz clock. 6.2.1 Clock adjustment The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By changing the factory trim values of the 16 MHz clock, the user may add an offset as small as ±3.0% of the nominal frequency. Contact a NXP representative for detailed information on this feature. 6.3 Bias and references block description 6.3.1 Internal core voltage references All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VBG. The bandgap and the rest of the core circuitry are supplied from VCC. Table 11 shows the main characteristics of the core circuitry. Table 11. Core voltages electrical specifications(20) TA = -40 to 105 °C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V ±4.0%, and typical external component values. Typical values are characterized at VVIN = 3.6 V, and 25 °C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units Notes – – 1.5 1.3 – – V (19) – – 2.775 0.0 – – V (19) Output Voltage – 1.2 – V (19) VBGACC Absolute Accuracy – 0.5 – % VBGTACC Temperature Drift – 0.25 – % VDIG (digital core supply) VDIG Output Voltage ON mode OFF mode VCC (Analog core supply) VCC Output Voltage ON mode OFF mode VBG (bandgap / regulator reference) VBG Notes 19. 3.0 V < VIN < 4.5 V, no external loading on VDIG, VCC, or VBG. Extended operation down to UVDET, but no system malfunction. 20. For information only. 6.3.1.1 External components Table 12. External components for core voltages Regulator Capacitor value (μF) VDIG 1.0 VCC 1.0 VBG 0.22 34VR500 NXP Semiconductors 19 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.3.2 REFOUT voltage reference REFOUT is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then utilizes a voltage follower to drive the load. REFIN REFIN CHALF1 100 nF VHALF _ CHALF2 100 nF + Discharge REFOUT REFOUT CREFDDR 1.0 uf Figure 8. REFOUT block diagram 6.3.2.1 REFOUT control register The REFOUT voltage reference is controlled by a single bit in REFOUTCTRL register in Table 13. Table 13. Register REFOUTCTRL - ADDR 0x6A Name UNUSED REFOUTEN UNUSED Bit # R/W Default Description 3:0 – 0x00 UNUSED 4 R/W 0x00 Enable or disables REFOUT output voltage 0 = REFOUT Disabled 1 = REFOUT Enabled 7:5 – 0x00 UNUSED External components Table 14. REFOUT external components(21) Capacitor Capacitance (μF) REFIN(22) to VHALF 0.1 VHALF to GND 0.1 REFOUT 1.0 Notes 21. Use X5R or X7R capacitors. 22. REFIN to GND, 1.0 μF minimum capacitance is provided by buck regulator output. 34VR500 20 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS REFOUT specifications Table 15. REFOUT electrical characteristics TA = -40 to 105 °C (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VREFIN = 1.5 V, VVBIAS = 1.0 V ±4.0%, and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VREFIN = 1.5 V, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes REFOUT VREFIN Operating Input Voltage Range 1.2 – 1.8 V IREFDDR Operating Load Current Range 0.0 – 10 mA Current Limit, IREFDDR when VREFOUT is forced to VREFIN/4 10.5 15 25 mA Quiescent Current – 8.0 – μA VREFOUT Output Voltage 1.2 V < VREFIN < 1.8 V, 0.0 mA < IREFDDR < 10 mA – VREFIN/2 – V VREFOUTTOL Output Voltage Tolerance 1.2 V < VREFIN < 1.8 V, 0.6 mA ≤ IREFDDR ≤ 10 mA –1.0 – 1.0 % VREFOUTLOR Load Regulation 1.0 mA < IREFDDR < 10 mA, 1.2 V < VREFIN < 1.8 V – 0.40 – mV/mA tONREFDDR Turn-on Time, Enable to 90% of end value VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA – – 100 μs tOFFREFDDR Turn-Off Time, Disable to 10% of initial value VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA – – 10 ms VREFOUTOSH Start-up Overshoot VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA – 1.0 6.0 % VREFOUTTLR Transient Load Response VREFIN = 1.2 V, 1.8 V – 5.0 – mV IREFDDRLIM IREFDDRQ (23) Active mode – DC Active mode – AC Notes 23. When REFOUT is off there is a quiescent current of 1.5 μA typical. 34VR500 NXP Semiconductors 21 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4 Power generation 6.4.1 Modes of operation The operation of the 34VR500 can be reduced to four states, or modes: ON, OFF, Sleep, and Standby. Figure 9 shows the state diagram of the 34VR500, along with the conditions to enter and exit from each state. Thermal shutdown OFF Sleep EN = 1 & VIN > UVDET EN = 0 Any SWxOMODE bits=1 EN = 0 All SWxOMODE bits= 0 EN = 0 Any SWxOMODE bits=1 EN = 1 & VIN > UVDET ON Thermal shudown STANDBY asserted STANDBY de-asserted EN = 0 All SWxOMODE bits= 0 Standby Thermal shutdown Figure 9. State diagram To complement the state diagram in Figure 9, a description of the states is provided in following sections. Note that VIN must exceed the rising UVDET threshold to allow a power up. Refer to Table 22 for the UVDET thresholds. Additionally, the interrupt signal and INTB are only active in Sleep, Standby, and ON states. 6.4.1.1 On mode The 34VR500 enters the ON mode after a turn-on event. PORB is de-asserted, high, in this mode of operation. 6.4.1.2 Off mode The 34VR500 enters the OFF mode after a turn-off event. A thermal shutdown event also forces the 34VR500 into the OFF mode. Only VDIG is powered in this mode of operation. To exit the OFF mode, a valid turn-on event is required. PORB is asserted, LOW, in this mode. 34VR500 22 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.1.3 Standby mode • Depending on STBY pin configuration, Standby is entered when the STBY pin is asserted. This is typically used for low-power mode of operation. • When STBY is de-asserted, Standby mode is exited. A product may be designed to go into a Low-power mode after periods of inactivity. The STBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby are pre-programmed through the I2C interface. Note that the STBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarity as shown in Table 16. When the 34VR500 is powered up first, regulator settings for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STBY pin polarity to Active Low, set the STBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STBY will generally be referred to as active high throughout this document. Table 16. STBY pin and polarity control STBY (Pin)(25) STBYINV (I2C bit)(26) STBY Control (24) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 24. STBY = 0: System is not in Standby, STBY = 1: System is in Standby 25. The state of the STBY pin only has influence in On mode. 26. Bit 6 in Power Control Register (ADDR - 0x1B) Since STBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 17, STBYDLY will delay the Standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event. Table 17. STBY delay - initiated response STBYDLY[1:0](27) Function 00 No Delay 01 One 32 k period (default) 10 Two 32 k periods 11 Three 32 k periods Notes 27. Bits [5:4] in Power Control Register (ADDR - 0x1B) 34VR500 NXP Semiconductors 23 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.1.4 Sleep mode • Depending on EN pin configuration, Sleep mode is entered when EN is de-asserted and SWxOMODE bit is set. • To exit Sleep mode, assert the EN pin. In the Sleep mode, the regulator will use the set point as programmed by SW1OFF[5:0] for SW1, SW2, SW3, and SW4. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 18 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event. Table 18. Regulator mode control SWxOMODE Off operational mode (sleep) (28) 0 Off 1 PFM Notes 28. For sleep mode, an activated switching regulator, should use the off mode set point as programmed by SW1OFF[5:0] for SW1, SW2, SW3, and SW4. 6.4.2 State machine flow summary Table 19 provides a summary matrix of the 34VR500 flow diagram to show the conditions needed to transition from one state to another. Table 19. State machine flow summary Next state Initial state STATE OFF Sleep Standby ON OFF X X X EN = 1 & VIN > UVDET Sleep Thermal Shutdown X X EN = 1 & VIN > UVDET EN = 0, Any SWxOMODE = 1 X Standby de-asserted EN = 0, Any SWxOMODE = 1 Standby asserted X Standby Thermal Shutdown EN = 0, All SWxOMODE = 0 ON Thermal Shutdown EN = 0, All SWxOMODE = 0 6.4.2.1 Turn on events From OFF and Sleep modes, the PMIC is powered on by a turn ON event. VIN must be greater than UVDET for the PMIC to turn-on. When VIN is greater than UVDET, a logic high on the EN pin is a turn ON event, when EN is high before VIN is valid, a VIN transition, from 0.0 V to a voltage greater than UVDET, also a Turn ON event. See the State diagram, Figure 9, and the Table 19 for more details. Any regulator enabled in the Sleep mode will remain enabled when transitioning from Sleep to ON, i.e., the regulator will not be turned OFF and then ON again to match the start-up sequence. The following is a more detailed description of the EN configuration: • The EN signal is high and VIN > UVDET, the PMIC will turn ON; the interrupt and sense bits, ENI and ENS respectively, will be set. The sense bit will show the real time status of the EN pin. In this configuration, the EN input can be a mechanical switch debounced through a programmable debouncer, ENDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is generated for both the falling and the rising edge of the EN pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with ENDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode. 34VR500 24 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 20. EN hardware debounce bit settings Bits ENDBNC[1:0] State Turn on debounce (ms) Falling edge INT debounce (ms) Rising edge INT debounce (ms) 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 29. The sense bit, ENS, is not debounced and follows the state of the EN pin. 6.4.2.2 Turn off events EN pin The EN pin is used to power off the 34VR500. The Off mode is entered when the EN pin is low and SWxOMODE = 0. Thermal protection If the die temperature surpasses a given threshold, the thermal protection circuit will power off the 34VR500 to avoid damage. A turn-on event will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power dissipation section for more detailed information. Undervoltage detection The state machine will transition to the OFF mode when the voltage at the VIN pin drops below the UVDET undervoltage falling threshold. 6.4.3 Power tree The 34VR500 features four buck regulators, five general purpose LDOs, and a DDR voltage reference, to supply voltages for the application and peripheral devices. The buck regulators are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they are powered ON or OFF. The five general use LDO regulators are directly supplied from the main input supply or from the switching regulators depending on the application requirements. Since REFOUT is intended to provide DDR memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for REFOUT. Refer to Table 21 for a summary of all power supplies provided by the 34VR500. Table 21. Power tree summary Supply Output voltage (V) Step size (mV) Maximum load current (mA) SW1 0.625 - 1.875 25 4500 SW2 0.625 - 1.975 / 0.8 - 3.3 25 / 50 2000 SW3 0.625 - 1.975 / 0.8 - 3.3 25 / 50 2500 SW4 0.5*SW3_OUT (VTT for V1, V3, V4, V5), 0.625 - 1.975 (for V2) LDO1 0.80 – 1.55 50 250 LDO2 1.8 – 3.3 100 100 LDO3 1.8 – 3.3 100 350 LDO4 1.8 – 3.3 100 100 LDO5 1.8 – 3.3 100 200 REFOUT 0.5*SW3_OUT NA 10 1000 34VR500 NXP Semiconductors 25 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 22 summarizes the UVDET thresholds. Table 22. UVDET threshold UVDET threshold VIN Rising 3.1 V Falling 2.65 V VR500 LS102x SW1 VDDCORE (0.625 to 1.875 V), 4.5 A SW2 VDDC (0.625 to 3.3 V), 2.0 A VIN 3.3 V VDDCORE VDDC LDO2 (1.8 to 3.3 V), 100 mA OVDD1/2 LDO4 (1.8 to 3.3 V), 100 mA L1VDD LDO5 (1.8 to 3.3 V), 200 mA OVDD SW3 DDR CORE (0.625 to 3.3 V), 2.5 A SW4 System/VTT (0.625 to 1.975 V) (0.5*VDDR) 1.0 A SW3 VIN 3.3 V REFOUT 0.5*VDDR, 10 mA LDO1 (0.80 to 1.55 V), 250 mA DDR3 VTT Peripherals LDO3 (1.8 to 3.3 V), 350 mA Figure 10. 34VR500 typical power map 34VR500 26 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4 Buck regulators Each buck regulator is capable of operating in PFM, APS, and PWM switching modes. 6.4.4.1 Current limit Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 6.4.4.2 General control To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current variation. Available switching modes for buck regulators are presented in Table 23. Table 23. Switching mode description Mode Description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 24 summarizes the Buck regulator programmability for Normal and Standby modes. Table 24. Regulator mode control SWxMODE[3:0] Normal Mode Standby Mode SWxMODE[3:0] Normal Mode Standby Mode 0000 Off Off 1000 APS APS 0001 PWM Off 1001 Reserved Reserved 0010 Reserved Reserved 1010 Reserved Reserved 0011 PFM Off 1011 Reserved Reserved 0100 APS Off 1100 APS PFM 0101 PWM PWM 1101 PWM PFM 0110 PWM APS 1110 Reserved Reserved 0111 Reserved Reserved 1111 Reserved Reserved Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic voltage scaling. For each regulator, the output voltage options are the same for Normal and Standby modes. When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage programmed in its voltage register. 34VR500 NXP Semiconductors 27 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a EN turn-off event occurs, and any regulator whose SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state. Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up sequence as when powering On from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings. Table 18 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point as programmed by SWxOFF[5:0] for SW1, SW2, SW3, and SW4. 6.4.4.3 Dynamic voltage scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. 1. Normal operation: The output voltage is selected by I2C bits SWx[5:0] for SW1, SW2, SW3, and SW4. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 26. 2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SWxSTBY[5:0] for SW1, SW2, SW3, and SW4. Voltage transitions initiated by a Standby event are governed by the SWxDVSSPEED[1:0] and I2C bits shown in Table 26. 3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SWxOFF[5:0] for SW1, SW2, SW3, and SW4. Voltage transitions initiated by a turn-off event are governed by the SWxDVSSPEED[1:0] I2C bits shown in Table 26. Table 25, Table 26, summarize the set point control and DVS time stepping applied to all regulators. Table 25. DVS control logic for SW1, SW2, SW3, and SW4 STBY Set Point Selected by 0 SWx[5:0] 1 SWxSTBY[5:0] Table 26. DVS speed selection for SW1, SW2, SW3, and SW4 SWxDVSSPEED[1:0] Function 00 25 mV step each 2.0 μs 01 (default) 25 mV step each 4.0 μs 10 25 mV step each 8.0 μs 11 25 mV step each 16 μs The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. 34VR500 28 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Requested Set Point Internally Controlled Steps Example Actual Output Voltage Output Voltage Initial Set Point Actual Output Voltage Internally Controlled Steps Voltage Change Request Output Voltage with light Load Request for Higher Voltage Possible Output Voltage Window Request for Lower Voltage Initiated by I2C Programming, Standby Control Figure 11. Voltage stepping with DVS 6.4.4.4 Regulator phase clock The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 27. By default, each regulator is initialized at 90 ° out of phase with respect to each other. For example, SW1 is set to 0 °, SW2 is set to 90 °, SW3 is set to 180 °, and SW4 is set to 270 ° by default at power up. Table 27. Regulator phase clock selection SWxPHASE[1:0] Phase of Clock Sent to Regulator (degrees) 00 0 01 90 10 180 11 270 The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 29 shows the selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and 4.0 MHz, 180 ° are the same in terms of phasing. Table 28 shows the optimum phasing when using more than one switching frequency. Table 28. Optimum phasing Frequencies Optimum phasing 1.0 MHz 2.0 MHz 0° 180 ° 1.0 MHz 4.0 MHz 0° 180 ° 2.0 MHz 4.0 MHz 0° 180 ° 1.0 MHz 2.0 MHz 4.0 MHz 0° 90 ° 90 ° 34VR500 NXP Semiconductors 29 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 29. Regulator frequency configuration 6.4.4.5 SWxFREQ[1:0] Frequency 00 1.0 MHz 01 2.0 MHz 10 4.0 MHz 11 Reserved SW1 regulator The SW1 is a 4.5 A regulator capable of providing an output from 0.625 to 1.875 V. Figure 12 shows a high level block diagram of the SW1 regulator. PVIN1 PVIN1 SW1 LX1 LSW1 COSW1 SW1MODE ISENSE CINSW1 Controller Driver SW1FAULT EP Internal Compensation FB1 I2C Interface I2C Z2 Z1 VREF EA DAC Figure 12. SW1 regulator block diagram 6.4.4.6 SW1 setup and control registers SW1 output voltage is programmable from 0.625 to 1.875 V in steps of 25 mV. After power up in the default voltage, the output voltage can be changed in the Normal, Standby and Sleep mode by writing to the SW1[5:0], SW1STBY[5:0], and SW1OFF[5:0] respectively. Figure 30 shows the output voltage coding for these registers. Table 30. SW1 output voltage configuration Set point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 output (V) Set point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 output (V) 13 001101 0.6250 39 100111 1.2750 14 001110 0.6500 40 101000 1.3000 15 001111 0.6750 41 101001 1.3250 16 010000 0.7000 42 101010 1.3500 17 010001 0.7250 43 101011 1.3750 18 010010 0.7500 44 101100 1.4000 19 010011 0.7750 45 101101 1.4250 20 010100 0.8000 46 101110 1.4500 21 010101 0.8250 47 101111 1.4750 34VR500 30 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 30. SW1 output voltage configuration (continued) Set point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 output (V) Set point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 output (V) 22 010110 0.8500 48 110000 1.5000 23 010111 0.8750 49 110001 1.5250 24 011000 0.9000 50 110010 1.5500 25 011001 0.9250 51 110011 1.5750 26 011010 0.9500 52 110100 1.6000 27 011011 0.9750 53 110101 1.6250 28 011100 1.0000 54 110110 1.6500 29 011101 1.0250 55 110111 1.6750 30 011110 1.0500 56 111000 1.7000 31 011111 1.0750 57 111001 1.7250 32 100000 1.1000 58 111010 1.7500 33 100001 1.1250 59 111011 1.7750 34 100010 1.1500 60 111100 1.8000 35 100011 1.1750 61 111101 1.8250 36 100100 1.2000 62 111110 1.8500 37 100101 1.2250 63 111111 1.8750 38 100110 1.2500 Table 31 provides a list of registers used to configure and operate SW1 and a detailed description on each one of these register is provided in Table 31 through Table 36. Table 31. SW1 register summary Register Address Output SW1VOLT 0x2E SW1 Output voltage set point in normal operation SW1STBY 0x2F SW1 Output voltage set point in Standby SW1OFF 0x30 SW1 Output voltage set point in Sleep SW1MODE 0x31 SW1 Switching Mode selector register SW1CONF 0x32 SW1 DVS, Phase, Frequency and ILIM configuration Table 32. Register SW1VOLT - ADDR 0x2E Name Bit # R/W Default Description SW1 5:0 R/W 0x00 Sets the SW1 output voltage during normal operation mode. See Table 30 for all possible configurations. UNUSED 7:6 – 0x00 UNUSED Table 33. Register SW1STBY - ADDR 0x2F Name Bit # R/W Default Description SW1STBY 5:0 R/W 0x00 Sets the SW1 output voltage during Standby mode. See Table 30 for all possible configurations. UNUSED 7:6 – 0x00 UNUSED 34VR500 NXP Semiconductors 31 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 34. Register SW1OFF - ADDR 0x30 Name Bit # R/W Default Description SW1OFF 5:0 R/W 0x00 Sets the SW1 output voltage during Sleep mode. See Table 30 for all possible configurations. UNUSED 7:6 – 0x00 UNUSED Table 35. Register SW1MODE - ADDR 0x31 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW1 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 – 0x00 UNUSED SW1OMODE 5 R/W 0x00 Set status of SW1 when in Sleep mode 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED SW1MODE UNUSED Description Table 36. Register SW1CONF - ADDR 0x32 Name 6.4.4.7 Bit # R/W Default Description SW1ILIM 0 R/W 0x00 SW1 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW1FREQ 3:2 R/W 0x00 SW1 switching frequency selector. See Table 29. SW1PHASE 5:4 R/W 0x00 SW1 Phase clock selection. See Table 27. SW1DVSSPEED 7:6 R/W 0x00 SW1 DVS speed selection. See Table 26. SW1 external components Table 37. SW1 external component recommendations Components Description Component CINSW1 (30) SW1input capacitor 3 x 4.7 μF CIN1HF (30) SW1decoupling input capacitor 3 x 0.1 μF COSW1(30) SW1 output capacitor 7 x 22 μF LSW1 SW1 inductor 0.68 μH, DCR = 10 mΩ, ISAT = 9.0 A Notes 30. Use X5R or X7R capacitors. 34VR500 32 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.8 SW1 specifications Table 38. SW1 electrical characteristics All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch mode supply SW1 VPVIN1 Operating Input Voltage 2.8 – 4.5 V VSW1 Nominal Output Voltage – Table 30 – V -25 -3.0 – – 25 3.0 mV % -65 -45 -3.0 – – – 65 45 3.0 mV mV % – – 4500 mA 7.1 5.3 10.5 7.9 13.7 10.3 A VSW1ACC Output Voltage Accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1 < 4.5 A 0.625 V ≤ VSW1 ≤ 1.450 V 1.475 V ≤ VSW1 ≤ 1.875 V • PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1 < 150 mA 0.625 V < VSW1 < 0.675 V 0.7 V < VSW1 < 0.85 V 0.875 V < VSW1 < 1.875 V ISW1 ISW1LIM Rated Output Load Current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1 < 1.875 V Current Limiter Peak Current Detection • Current through Inductor SW1ILIM = 0 SW1ILIM = 1 VSW1 Start-up Overshoot ISW1 = 0 mA DVS clk = 25 mV/4 μs, VIN = VPVIN1 = 4.5 V, VSW1 = 1.875 V – – 66 mV tONSW1 Turn-on Time, Enable to 90% of end value ISW1 = 0 mA, DVS clk = 25 mV/4.0 μs, VIN = VPVIN1 = 4.5 V, VSW1 = 1.875 V – – 500 µs – – – 1.0 2.0 4.0 – – – – – – – – – 77 82 86 84 80 68 – – – – – – Output Ripple – 5.0 – mV VSW1LIR Line Regulation (APS, PWM) – – 20 mV VSW1LOR DC Load Regulation (APS, PWM) – – 20 mV VSW1LOTR Transient Load Regulation • Transient load = 0 to 2.25 A, di/dt = 100 mA/μs Overshoot Undershoot – – – – 50 50 fSW1 Switching Frequency SW1FREQ[1:0] = 00 SW1FREQ[1:0] = 01 SW1FREQ[1:0] = 10 MHz Efficiency • VIN = 3.6 V, fSW1 = 2.0 MHz, LSW1 = 1.0 μH PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 850 mA APS, PWM, 1.2 V, 1275 mA APS, PWM, 1.2 V, 2125 mA APS, PWM, 1.2 V, 4500 mA ηSW1 ΔVSW1 % mV 34VR500 NXP Semiconductors 33 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 38. SW1 electrical characteristics (continued) All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Quiescent Current PFM Mode APS Mode – – 18 145 – – µA RSW1DIS Discharge Resistance – 600 – Ω RONSW1P SW1 P-MOSFET RDS(on) VPVIN1 = 3.3 V – 60 77 mΩ RONSW1N SW1 N-MOSFET RDS(on) VPVIN1 = 3.3 V – 80 101 mΩ Notes Switch mode supply SW1 (continued) Efficiency (%) ISW1Q 100 90 80 70 60 50 40 30 20 10 0 2MHz, 1.8V, PWM 1MHz, 1.8V, PWM 100 1000 Load Current (mA) 10000 SW1 Efficiency Waveform: VIN = 3.3 V; VOUT = 1.8 V SW1 Efficiency Waveform: VIN = 3.6 V; VOUT = 1.2 V SW1 Efficiency Waveform: VIN = 3.6 V; VOUT = 1.2 V Figure 13. SW1 efficiency waveforms 34VR500 34 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Figure 14. Load transient response – SW1 (APS) 6.4.4.9 SW2 SW2 is a 2.0 A rated buck regulator. Table 23 describes the modes, and Table 24 show the options for the SWxMODE[3:0] bits. Figure 15 shows the block diagram and the external component connections for SW2 regulator. PVIN2 PVIN2 SW2 LX2 LSW2 COSW2 SW2MODE ISENSE CINSW2 Controller Driver SW2FAULT EP Internal Compensation FB2 I2C Interface I2C Z2 Z1 EA VREF DAC Figure 15. SW2 block diagram 34VR500 NXP Semiconductors 35 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.10 SW2 setup and control registers SW2 output voltage is programmable from 0.625 V to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal operation. Its value is determined by the default configuration. Therefore, once SW2[6] is set to "0", the output is limited to the lower output voltages from 0.625 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. Likewise, once bit SW2[6] is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by bits SW2[5:0]. In order to optimize the performance of the regulator, it is recommended only voltages from 2.000 V to 3.300 V be used in the high range, and the lower range be used for voltages from 0.625 V to 1.975 V. The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW2[5:0], SW2STBY[5:0] and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] are copied into bits SW2STBY[6], and SW2OFF[6] bits. Therefore, the output voltage range remains the same in all three operating modes. Table 39 shows the output voltage coding valid for SW2. Table 39. SW2 output voltage configuration Low output voltage range(31) High output voltage range Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output 0 0000000 Reserved 64 1000000 0.8000 1 0000001 Reserved 65 1000001 0.8500 2 0000010 Reserved 66 1000010 0.9000 3 0000011 Reserved 67 1000011 0.9500 4 0000100 Reserved 68 1000100 1.0000 5 0000101 Reserved 69 1000101 1.0500 6 0000110 Reserved 70 1000110 1.1000 7 0000111 Reserved 71 1000111 1.1500 8 0001000 Reserved 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 34VR500 36 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 39. SW2 output voltage configuration(continued) 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 31. For voltages less than 2.0 V, only use set points 9 to 63. Setup and control of SW2 is done through I2C registers listed i n Table 40, and a detailed description of each one of the registers is provided in Tables 41 to Table 45. 34VR500 NXP Semiconductors 37 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 40. SW2 register summary Register Address Description SW2VOLT 0x35 Output voltage set point on normal operation SW2STBY 0x36 Output voltage set point on Standby SW2OFF 0x37 Output voltage set point on Sleep SW2MODE 0x38 Switching Mode selector register SW2CONF 0x39 DVS, Phase, Frequency, and ILIM configuration Table 41. Register SW2VOLT - ADDR 0x35 Name Bit # R/W Default Description SW2 5:0 R/W 0x00 Sets the SW2 output voltage during normal operation mode. See Table 39 for all possible configurations. SW2 6 R 0x00 Sets the operating output voltage range for SW2. Set by OTP. See Table 39 for all possible configurations. UNUSED 7 – 0X00 UNUSED Table 42. Register SW2STBY - ADDR 0x36 Name Bit # R/W Default Description SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 39 for all possible configurations. SW2STBY 6 R 0x00 Sets the operating output voltage range for SW2 on Standby mode. This bit inherits the value configured on bit SW2[6] by OTP. See Table 39 for all possible configurations. UNUSED 7 – 0X00 UNUSED Table 43. Register SW2OFF - ADDR 0x37 Name Bit # R/W Default Description SW2OFF 5:0 R/W 0x00 Sets the SW2 output voltage during Sleep mode. See Table 39 for all possible configurations. SW2OFF 6 R 0x00 Sets the operating output voltage range for SW2 on Sleep mode. This bit inherits the value configured on bit SW2[6] by OTP. See Table 39 for all possible configurations. UNUSED 7 – 0X00 UNUSED Table 44. Register SW2MODE - ADDR 0x38 Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW2 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 – 0x00 UNUSED SW2OMODE 5 R/W 0x00 Set status of SW2 when in Sleep mode 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED SW2MODE UNUSED Description 34VR500 38 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 45. Register SW2CONF - ADDR 0x39 Name 6.4.4.11 Bit # R/W Default Description SW2ILIM 0 R/W 0x00 SW2 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 29. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. See Table 27. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 28. SW2 external components Table 46. SW2 external component recommendations Components SW2 Input capacitor (32) SW2 Decoupling input capacitor CINSW2 CIN2HF Description (32) COSW2(32) SW2 Output capacitor LSW2 SW2 Inductor Values 4.7 μF 0.1 μF 3 x 22 μF 1.5 μH DCR = 50 mΩ ISAT = 2.6 A Notes 32. Use X5R or X7R capacitors. 6.4.4.12 SW2 specifications Table 47. SW2 electrical characteristics All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch mode supply SW2 VPVIN2 Operating Input Voltage 2.8 – 4.5 V VSW2 Nominal Output Voltage – Table 39 – V -25 -3.0 -6.0 – – – 25 3.0 6.0 mV % % -65 -45 -3.0 -3.0 – – – – 65 45 3.0 3.0 mV mV % % Output Voltage Accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A VSW2ACC 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V • PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V 34VR500 NXP Semiconductors 39 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 47. SW2 electrical characteristics (continued) All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, and 25 °C, unless otherwise noted. Symbol ISW2 ISW2LIM Parameter Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V Current Limiter Peak Current Detection • Current through Inductor SW2ILIM = 0 SW2ILIM = 1 Min. Typ. Max. – – 2000 2.8 2.1 4.0 3.0 5.2 3.9 Unit Notes mA (33) A VSW2OSH Start-up Overshoot ISW2 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN2 = 4.5 V – – 66 mV tONSW2 Turn-ON Time, Enable to 90% of end value ISW2 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN2 = 4.5 V – – 500 µs – – – 1.0 2.0 4.0 – – – fSW2 Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 MHz Notes 33. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance). 34VR500 40 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 47. SW2 electrical characteristics (continued) All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit – 77 – – – – 68 68 76 – – – – – – – – – 94 95 96 94 92 86 – – – – – – Output Ripple – 5.0 – mV VSW2LIR Line Regulation (APS, PWM) – – 20 mV VSW2LOR DC Load Regulation (APS, PWM) – – 20 mV VSW2LOTR Transient Load Regulation • Transient load = 0.0 mA to 0.5 A, di/dt = 100 mA/μs Overshoot Undershoot – – – – 50 50 Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) – – – 23 145 305 – – – Notes Switch mode supply SW2 (continued) Efficiency • VIN = 2.8 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH APS, PWM, 1.0 V, 1000 mA • VIN = 4.5V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH ηSW2 ΔVSW2 ISW2Q • PFM, 1.0 V, 50 mA APS, 1.0 V, 1.0 mA APS, 1.0 V, 1000 mA VIN = 3.6V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 2000 mA % mV µA RONSW2P SW2 P-MOSFET RDS(on) at VIN = VPVIN2 = 3.3 V – 190 209 mΩ RONSW2N SW2 N-MOSFET RDS(on) at VIN = VPVIN2 = 3.3 V – 212 255 mΩ RSW2DIS Discharge Resistance – 600 – Ω 34VR500 NXP Semiconductors 41 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS SW2 Efficiency Waveform: VIN = 3.6V; VOUT = 1.8V Figure 16. SW2 efficiency waveforms Figure 17. Load transient response – SW2 (PWM) 6.4.4.13 SW3 SW3 is a 2.5 A regulator capable of providing an output from 0.625 V to 3.3 V. Figure 18 shows a high level block diagram of the SW3 regulator. 34VR500 42 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS PVIN3 PVIN3 SW3MODE ISENSE CINSW3 SW3 Controller LX3 Driver LSW3 COSW3 SW3FAULT EP Internal Compensation FB3 I2C Interface I2C Z2 Z1 VREF EA DAC Figure 18. SW3 regulator block diagram 6.4.4.14 SW3 setup and control registers SW3 output voltage is programmable from 0.625 V to 3.300 V; however, bit SW3 [6] in register SW3VOLT is read-only during normal operation. Its value is determined by the default configuration. Therefore, once SW3 [6] is set to “0”, the output is limited to the lower output voltages from 0.625 V to 1.975 V with 25 mV increments, as determined by bits SW3[5:0]. Likewise, once bit SW3[6] is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV increments, as determined by bits SW3[5:0]. In order to optimize the performance of the regulator, it is recommended only voltages from 2.00 V to 3.300 V be used in the high range and the lower range be used for voltages from 0.625 V to 1.975 V. The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW3[5:0], SW3STBY[5:0], and SW3OFF[5:0] bits respectively; however, the initial state of the SW3[6] bit is copied into the SW3STBY[6] and SW3OFF[6] bits. Therefore, the output voltage range remains the same on all three operating modes. Table 48 shows the output voltage coding valid for SW3. Table 48 shows the output voltage coding valid for SW3. Table 48. SW3 output voltage configuration Low output voltage range(34) High output voltage range Set point SW3[6:0] SW3 output Set point SW3[6:0] SW3 output 0 0000000 Reserved 64 1000000 0.8000 1 0000001 Reserved 65 1000001 0.8500 2 0000010 Reserved 66 1000010 0.9000 3 0000011 Reserved 67 1000011 0.9500 4 0000100 Reserved 68 1000100 1.0000 5 0000101 Reserved 69 1000101 1.0500 6 0000110 Reserved 70 1000110 1.1000 7 0000111 Reserved 71 1000111 1.1500 8 0001000 Reserved 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 34VR500 NXP Semiconductors 43 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 48. SW3 output voltage configuration (continued) Low output voltage range(34) High output voltage range Set point SW3[6:0] SW3 output Set point SW3[6:0] SW3 output 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 Reserved 34VR500 44 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 48. SW3 output voltage configuration (continued) Low output voltage range(34) High output voltage range Set point SW3[6:0] SW3 output Set point SW3[6:0] SW3 output 52 0110100 1.7000 116 1110100 Reserved 53 0110101 1.7250 117 1110101 Reserved 54 0110110 1.7500 118 1110110 Reserved 55 0110111 1.7750 119 1110111 Reserved 56 0111000 1.8000 120 1111000 Reserved 57 0111001 1.8250 121 1111001 Reserved 58 0111010 1.8500 122 1111010 Reserved 59 0111011 1.8750 123 1111011 Reserved 60 0111100 1.9000 124 1111100 Reserved 61 0111101 1.9250 125 1111101 Reserved 62 0111110 1.9500 126 1111110 Reserved 63 0111111 1.9750 127 1111111 Reserved Notes 34. For voltages less than 2.0 V, only use set points 9 to 63. Table 49 provides a list of registers used to configure and operate SW3. A detailed description on each of these register is provided on Tables 49 through Table 54. Table 49. SW3 register summary Register Address Output SW3VOLT 0x3C SW3 Output voltage set point on normal operation SW3STBY 0x3D SW3 Output voltage set point on Standby SW3OFF 0x3E SW3 Output voltage set point on Sleep SW3MODE 0x3F SW3 Switching mode selector register SW3CONF 0x40 SW3 DVS, phase, frequency and ILIM configuration Table 50. Register SW3VOLT - ADDR 0x3C Name Bit # R/W Default Description SW3 5:0 R/W 0x00 Sets the SW3 output voltage, during normal operation mode. See Table 48 for all possible configurations. SW3 6 R 0x00 Sets the operating output voltage range for SW3. Set by OTP. See Table 48 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 51. Register SW3STBY - ADDR 0x3D Name Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3 output voltage, during Standby mode. See Table 48 for all possible configurations. SW3 6 R 0x00 Sets the operating output voltage range for SW3 on Standby mode. This bit inherits the value configured on bit SW3[6] by OTP. See Table 48 for all possible configurations. UNUSED 7 – 0x00 UNUSED SW3STBY 34VR500 NXP Semiconductors 45 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 52. Register SW3OFF - ADDR 0x3E Name Bit # R/W Default 5:0 R/W 0x00 Sets the SW3 output voltage during Sleep mode. See Table 48 for all possible configurations. SW3 6 R 0x00 Sets the operating output voltage range for SW3 on Sleep mode. This bit inherits the value configured on bit SW3[6] by OTP. See Table 48 for all possible configurations. UNUSED 7 – 0x00 UNUSED SW3OFF Description Table 53. Register SW3MODE - ADDR 0x3F Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW3 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 – 0x00 UNUSED SW3OMODE 5 R/W 0x00 Set status of SW3 when in Sleep mode. 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED SW3MODE UNUSED Description Table 54. Register SW3CONF - ADDR 0x40 Name Bit # R/W Default SW3ILIM 0 R/W 0x00 SW3 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW3FREQ 3:2 R/W 0x00 SW3 switching frequency selector. See Table 29. SW3PHASE 5:4 R/W 0x00 SW3 Phase clock selection. See Table 27. SW3DVSSPEED 7:6 R/W 0x00 SW3 DVS speed selection. See Table 28. 6.4.4.15 Description SW3 external components Table 55. SW3 external component requirements Components Description SW3 CINSW3 (35) SW3 input capacitor 2 x 4.7 μF COSW3 (35) SW3 output capacitor 3 x 22 μF CIN3HF (35) SW3 decoupling input capacitor 2 x 0.1 μF LSW3 SW3 inductor 1.5 μH DCR = 25 mΩ ISAT = 5.0 A Notes 35. Use X5R or X7R capacitors. 34VR500 46 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.16 SW3 specifications Table 56. SW3 electrical characteristics All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Notes Switch mode supply SW3 VPVIN3 Operating Input Voltage 2.8 – 4.5 V VSW3 Nominal Output Voltage - Table 48 - V -25 -3.0 -6.0 – – – 25 3.0 6.0 mV % % -65 -45 -45 -3.0 – – – – 65 45 45 3.0 mV mV mV % – – 2500 3.5 2.7 5.0 3.8 6.5 4.9 Start-up Overshoot ISW3 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN3 = 4.5 V – – 66 mV Turn-on Time Enable to 90% of end value ISW3 = 0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN3 = 4.5 V – – 500 µs – – – 1.0 2.0 4.0 – – – VSW3ACC Output Voltage Accuracy • PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3 < 2.5 A 0.625 V < VSW3 < 0.85 V 0.875 V < VSW3 < 1.975 V 2.0 V < VSW3 < 3.3 V • PFM, steady state (2.8 V < VIN < 4.5 V, 0 < ISW3 < 50 mA) 0.625 V < VSW3 < 0.675 V 0.7 V < VSW3 < 0.85 V 0.875 V < VSW3 < 1.975 V 2.0 V < VSW3 < 3.3 V ISW3 ISW3LIM VSW3OSH tONSW3 fSW3 Rated Output Load Current • 2.8 V < VIN < 4.5 V, 0.625 V < VSW3 < 3.3 V PWM, APS mode Current Limiter Peak Current Detection • Current through inductor SW3ILIM = 0 SW3ILIM = 1 Switching Frequency SW3FREQ[1:0] = 00 SW3FREQ[1:0] = 01 SW3FREQ[1:0] = 10 mA (36) A MHz Notes 36. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VINSW3 - VSW3) = ISW3* (DCR of inductor +RONSW3xP + PCB trace resistance). 34VR500 NXP Semiconductors 47 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 56. SW3 electrical characteristics (continued) All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Efficiency • fSW3 = 2.0 MHz, LSW3 1.0 μH PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA – – – – – – 84 85 85 84 80 74 – – – – – – Output Ripple – 5.0 – mV VSW3LIR Line Regulation (APS, PWM) – – 20 mV VSW3LOR DC Load Regulation (APS, PWM) – – 20 mV VSW3LOTR Transient Load Regulation • Transient Load = 0.0 mA to 1.25 A, di/dt = 100 mA/μs Overshoot Undershoot – – – – 50 50 Quiescent Current PFM Mode APS Mode – – 22 300 – – 108 123 129 163 600 – Notes Switch mode supply SW3 (continued) ηSW3 ΔVSW3 ISW3Q RONSW3P SW3 P-MOSFET RDSON at VIN = VPVIN3 = 3.3 V – RONSW3N SW3 N-MOSFET RDSON at VIN = VPVIN3 = 3.3 V – RSW3DIS Discharge Resistance – % mV µA mΩ mΩ Ω 100 90 80 PFM - Vout = 1.5V 20 APS - Vout = 1.5V Efficiency (%) 70 ) % ( 60 yc n 50 e ic if 40 fE 30 10 PWM - Vout = 1.5V 0 0.1 1 10 100 1000 Load Current (mA) Figure 19. SW3 efficiency waveforms 34VR500 48 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Figure 20. Load transient response – SW3 (PWM) 6.4.4.17 SW4 SW4 operates by default in VTT mode (for the 34VR500V1, V3, V4, V5, V6, V7) and it's not possible to change this configuration and modify the output voltage after the Start-up sequence. SW4 operates in non VTT mode for the 34VR500V2 and it is possible to change the output voltage by the I2C bus. SW4 is a 1.0 A rated buck regulator capable of operating in two modes. In Regulator mode, it operates as a normal buck regulator with a programmable output between 0.625 and 1.975 V. It is capable of operating in the three available switching modes: PFM, APS, and PWM, described on Table 23 and configured by the SW4MODE[3:0] bits, as shown in Table 24. If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage will track the output voltage of SW3, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The minimum output voltage for SW4 in VTT mode is 0.6 V Figure 21 shows the block diagram and the external component connections for the SW4 regulator. PVIN4 PVIN4 CINSW4 SW4 LX4 LSW4 COSW4 SW4MODE ISENSE Controller Driver SW4FAULT EP Internal Compensation FB4 I2C Interface I2C Z2 Z1 EA VREF DAC Figure 21. SW4 block diagram 34VR500 NXP Semiconductors 49 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.4.18 SW4 setup and control registers In Regulator mode, the SW4 output voltage is programmable from 0.625 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW4[5:0], SW4STBY[5:0], and SW4OFF[5:0] bits, respectively. Table 57 shows the output voltage coding valid for SW4. Table 57. SW4 output voltage configuration Set Point SW4[5:0] SW4 Output Set Point SW4[5:0] SW4 Output 9 001001 0.6250 37 100101 1.3250 10 001010 0.6500 38 100110 1.3500 11 001011 0.6750 39 100111 1.3750 12 001100 0.7000 40 101000 1.4000 13 001101 0.7250 41 101001 1.4250 14 001110 0.7500 42 101010 1.4500 15 001111 0.7750 43 101011 1.4750 16 010000 0.8000 44 101100 1.5000 17 010001 0.8250 45 101101 1.5250 18 010010 0.8500 46 101110 1.5500 19 010011 0.8750 47 101111 1.5750 20 010100 0.9000 48 110000 1.6000 21 010101 0.9250 49 110001 1.6250 22 010110 0.9500 50 110010 1.6500 23 010111 0.9750 51 110011 1.6750 24 011000 1.0000 52 110100 1.7000 25 011001 1.0250 53 110101 1.7250 26 011010 1.0500 54 110110 1.7500 27 011011 1.0750 55 110111 1.7750 28 011100 1.1000 56 111000 1.8000 29 011101 1.1250 57 111001 1.8250 30 011110 1.1500 58 111010 1.8500 31 011111 1.1750 59 111011 1.8750 32 100000 1.2000 60 111100 1.9000 33 100001 1.2250 61 111101 1.9250 34 100010 1.2500 62 111110 1.9500 35 100011 1.2750 63 111111 1.9750 36 100100 1.3000 Full setup and control of SW4 is done through the I2C registers listed on Table 58, and a detailed description of each one of the registers is provided in Tables 59 to Table 63. 34VR500 50 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 58. SW4 register summary Register Address Description SW4VOLT 0x4A Output voltage set point on normal operation SW4STBY 0x4B Output voltage set point on Standby SW4OFF 0x4C Output voltage set point on Sleep SW4MODE 0x4D Switching mode selector register SW4CONF 0x4E DVS, phase, frequency and ILIM configuration Table 59. Register SW4VOLT - ADDR 0x4A Name SW4 UNUSED Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW4 output voltage during normal operation mode. See Table 57 for all possible configurations. 7 – 0x00 UNUSED Table 60. Register SW4STBY - ADDR 0x4B Name Bit # R/W Default Description SW4STBY 5:0 R/W 0x00 Sets the SW4 output voltage during Standby mode. See Table 57 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 61. Register SW4OFF - ADDR 0x4C Name Bit # R/W Default Description SW4OFF 5:0 R/W 0x00 Sets the SW4 output voltage during Sleep mode. See Table 57 for all possible configurations. UNUSED 7 – 0x00 UNUSED Table 62. Register SW4MODE - ADDR 0x4D Name Bit # R/W Default 3:0 R/W 0x08 Sets the SW4 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 – 0x00 UNUSED SW4OMODE 5 R/W 0x00 Set status of SW4 when in Sleep mode 0 = OFF 1 = PFM 7:6 – 0x00 UNUSED SW4MODE UNUSED Description 34VR500 NXP Semiconductors 51 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 63. Register SW4CONF - ADDR 0x4E Name Bit # R/W Default SW4ILIM 0 R/W 0x00 SW4 current limit level selection 0 = High level Current limit 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 29. SW4PHASE 5:4 R/W 0x00 SW4 Phase clock selection. See Table 27. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 28. 6.4.4.19 Description SW4 external components Table 64. SW4 external component recommendations Components CINSW4(37) CIN4HF (37) Description Values SW4 Input capacitor 4.7 μF SW4 Decoupling input capacitor 0.1 μF COSW4(37) SW4 Output capacitor LSW4 SW4 Inductor 3 x 22 μF 1.5 μH DCR = 50 mΩ ISAT = 2.6 A Notes 37. Use X5R or X7R capacitors. 6.4.4.20 SW4 specifications Table 65. SW4 electrical characteristics All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW4 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch mode supply SW4 VPVIN4 Operating Input Voltage 2.8 – 4.5 V VSW4 Nominal Output Voltage Normal operation VTT Mode – – Table 57 VSW3/2 – – V -25 -3.0 – – 25 3.0 mV % PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA 0.625 V < VSW4 < 0.675 V 0.7 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V -65 -45 -45 – – – 65 45 45 mV mV mV VTT Mode, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A -40 – 40 mV – – 1000 mA Output Voltage Accuracy • PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A 0.625 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V VSW4ACC • • ISW4 Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 1.975 V 34VR500 52 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 65. SW4 electrical characteristics (continued) All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, fSW4 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. 1.4 1.0 2.0 1.5 3.0 2.4 Unit Notes Switch mode supply SW4 (continued) ISW4LIM Current Limiter Peak Current Detection Current through inductor SW4ILIM = 0 SW4ILIM = 1 A VSW4OSH Start-up Overshoot ISW4 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN4 = 4.5 V – – 66 mV tONSW4 Turn-on Time Enable to 90% of end value ISW4 = 0.0 mA, DVS clk = 25 mV/4 μs, VIN = VPVIN4 = 4.5 V – – 500 µs Switching Frequency SW4FREQ[1:0] = 00 SW4FREQ[1:0] = 01 SW4FREQ[1:0] = 10 – – – 1.0 2.0 4.0 – – – Efficiency • fSW4 = 2.0 MHz, LSW4 = 1.0 μH PFM, 1.8 V, 1.0 mA PFM, 1.8 V, 50 mA APS, PWM 1.8 V, 200 mA APS, PWM 1.8 V, 500 mA APS, PWM 1.8 V, 1000 mA – – – – – 81 78 87 88 83 – – – – – – – – 78 76 66 – – – Output Ripple – 5.0 – mV VSW4LIR Line Regulation (APS, PWM) – – 20 mV VSW4LOR DC Load Regulation (APS, PWM) – – 20 mV VSW4LOTR Transient Load Regulation • Transient Load = 0.0 mA to 500 mA, di/dt = 100 mA/μs Overshoot Undershoot – – – – – – 22 145 – – µA fSW4 ηSW4 PWM 0.75 V, 200 mA PWM 0.75 V, 500 mA PWM 0.75 V, 1000 mA ΔVSW4 ISW4Q Quiescent Current PFM Mode APS Mode 50 50 MHz % mV RONSW4P SW4 P-MOSFET RDSON at VIN = VPVIN4 = 3.3 V – 236 274 mΩ RONSW4N SW4 N-MOSFET RDSON at VIN = VPVIN4 = 3.3 V – 293 378 mΩ RSW4DIS Discharge Resistance – 600 – Ω 34VR500 NXP Semiconductors 53 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 100 90 Efficiency (%) 80 70 ) % ( 60 yc n 50 ie ci ff 40 E 30 PFM - Vout = 1.8V APS - Vout = 1.8V 20 PWM - Vout = 1.8 V 10 PWM - Vout = 0.7 5V 0 0.1 1 10 100 1000 Load Current (mA) Figure 22. SW4 efficiency waveforms Figure 23. Load transient response – SW4 (PWM) 6.4.5 LDO regulators description This section describes the LDO regulators provided by the 34VR500. All regulators use the main bandgap as reference. Refer to Bias and references block description section for further information on the internal reference voltages. A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest bias currents may be attained by forcing the part into its Low Power mode by setting the LDOxLPWR bit. The use of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when PORB is low. 34VR500 54 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS VLDOINx VLDOINx VREF _ + LDOx LDOxLPWR LDOx LDOx I2C Interface CLDOx LDOx Discharge Figure 24. General LDO block diagram 6.4.5.1 Transient response waveforms Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 25. Note that the transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. 34VR500 NXP Semiconductors 55 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS IMAX ILOAD IMAX/10 1.0 us 1.0 us Transient Load Stimulus IL = IMAX/10 IL = IMAX Overshoot VOUT Undershoot VOUT Transient Load Response VINx_INITIAL VINx VINx_FINAL 10 us 10 us Transient Line Stimulus VINx_INITIAL VINx_FINAL Overshoot VOUT Undershoot VOUT Transient Line Response Figure 25. Transient waveforms 34VR500 56 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.4.5.2 Short-circuit protection All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its LDOxEN bit, while at the same time, an interrupt LDOxFAULTI will be generated to flag the fault to the system processor. The LDOxFAULTI interrupt is maskable through the LDOxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators will not automatically be disabled upon a short-circuit detection. However, the current limiter will continue to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, LDOxFAULTI, will be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 66 for SCP behavior configuration. Table 66. Short-circuit behavior 6.4.5.3 REGSCPEN[0] Short-circuit Behavior 0 Current limit 1 Shutdown LDO regulator control Each LDO is fully controlled through its respective LDOxCTL register. This register enables the user to set the LDO output voltage according to Table 67 for LDO1 and uses the voltage set point on Table 68 for LDO2 through LDO5. Table 67. LDO1 output voltage configuration Set point LDO1[3:0] LDO1 output (V) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550 34VR500 NXP Semiconductors 57 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 68. LDO2/3/4/5 output voltage configuration Set point LDOx[3:0] LDOx output (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 69 presents a summary of all valid combinations of the control bits on LDOxCTL register and the expected behavior of the LDO output. Table 69. LDO control LDOxEN LDOxLPWR LDOxSTBY STANDBY(38) LDOxOUT 0 X X X Off 1 0 0 X On 1 1 0 X Low Power 1 X 1 0 On 1 0 1 1 Off 1 1 1 1 Low Power Notes 38. STANDBY refers to a Standby event as described earlier. For more detail information, Table 70 through Table 74 provide a description of all registers necessary to operate all five general purpose LDO regulators. 34VR500 58 NXP Semiconductors FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 70. Register LDO1CTL - ADDR 0x6D Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO1 output voltage. See Table 67 for all possible configurations. LDO1EN 4 – 0x00 Enables or Disables LDO1 output 0 = OFF 1 = ON LDO1STBY 5 R/W 0x00 Set LDO1 output state when in Standby. Refer to Table 69. LDO1LPWR 6 R/W 0x00 Enable Low Power Mode for LDO1. Refer to Table 69. UNUSED 7 – 0x00 UNUSED LDO1 Description Table 71. Register LDO2CTL - ADDR 0x6E Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO2 output voltage. See Table 68 for all possible configurations. LDO2EN 4 – 0x00 Enables or Disables LDO2 output 0 = OFF 1 = ON LDO2STBY 5 R/W 0x00 Set LDO2 output state when in Standby. Refer to Table 69. LDO2LPWR 6 R/W 0x00 Enable Low Power Mode for LDO2. Refer to Table 69. UNUSED 7 – 0x00 UNUSED LDO2 Description Table 72. Register LDO3CTL - ADDR 0x6F Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO3 output voltage. See Table 68 for all possible configurations. LDO3EN 4 – 0x00 Enables or Disables LDO3 output 0 = OFF 1 = ON LDO3STBY 5 R/W 0x00 Set LDO3 output state when in Standby. Refer to Table 69. LDO3LPWR 6 R/W 0x00 Enable Low Power Mode for LDO3. Refer to Table 69. UNUSED 7 – 0x00 UNUSED LDO3 Description Table 73. Register LDO4CTL - ADDR 0x70 Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO4 output voltage. See Table 68 for all possible configurations. LDO4EN 4 – 0x00 Enables or Disables LDO4 output 0 = OFF 1 = ON LDO4STBY 5 R/W 0x00 Set LDO4 output state when in Standby. Refer to Table 69. LDO4LPWR 6 R/W 0x00 Enable Low Power Mode for LDO4. Refer to Table 69. UNUSED 7 – 0x00 UNUSED LDO4 Description 34VR500 NXP Semiconductors 59 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 74. Register LDO5CTL - ADDR 0x71 Name Bit # R/W Default Description 3:0 R/W 0x80 Sets LDO5 output voltage. See Table 68 for all possible configurations. LDO5EN 4 – 0x00 Enables or Disables LDO5 output 0 = OFF 1 = ON LDO5STBY 5 R/W 0x00 Set LDO5 output state when in Standby. Refer to Table 69. LDO5LPWR 6 R/W 0x00 Enable Low Power Mode for LDO5. Refer to Table 69. UNUSED 7 – 0x00 UNUSED LDO5 6.4.5.4 External components Table 75 lists the typical component values for the general purpose LDO regulators. Table 75. LDO external components Regulator Output capacitor (μF)(39) LDO1 4.7 LDO2 2.2 LDO3 4.7 LDO4 2.2 LDO5 2.2 Notes 39. Use X5R/X7R ceramic capacitors. 6.4.5.5 6.4.5.5.1 LDO specifications LDO1 Table 76. LDO1 electrical characteristics All parameters are specified at TA = -40 to 105 °C (See Table 3), VIN = 3.6 V, VLDOIN1 = 3.0 V, VLDO1[3:0] = 1111, ILDO1 = 10 mA, VVBIAS = 1.0 V ±4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN1 = 3.0 V, LDO1[3:0] = 1111, ILDO1 = 10 mA and 25 °C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes LDO1 VLDOIN1 Operating Input Voltage 1.75 – 3.40 V LDO1NOM Nominal Output Voltage – Table 67 – V ILDO1 Operating Load Current 0.0 – 250 mA -3.0 – 3.0 % LDO1 active mode - DC VLDO1TOL Output Voltage Tolerance 1.75 V