MC56F8037VLH

56F8037/56F8027 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8037 Rev. 8 04/2012 freescale.com Document Revision History Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. • Changed input propagation delay values in Table 10-21 as follows: Old values: 1 s typical, 2 s maximum New values: 35 ns typical, 45 ns maximum Rev. 2 In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. Rev. 3 • Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Changed the description of the GPIOC4 signal in Table 2-3 (was “...the signal goes to both the ANA0 and CMPAI3”, is “...the signal goes to both ANB0 and CMPB13”). Rev. 4 • Changed the ITCN_BASE address In Table 5-3 (was $00 F060, is $00 F0E0). • In Figure 5-10, moved the footnote marker (superscript 1) from bit 4 to “RESET”. • Changed the STANDBY > STOP IDD values in Table 10-6 as follows: Typical: was 290A, is 540A Maximum: was 390A, is 650A • Changed the POWERDOWN IDD values in Table 10-6 as follows: Typical: was 190A, is 440A Maximum: was 250A, is 550A • Changed footnote 1 in Table 10-12 (was “Output frequency after application of 8MHz trim value, at 125°C.”, is “Output frequency after application of factory trim”). • Deleted the text “at 125°C” from Figure 10-5. • Changed the maximum input offset voltage in Table 10-21 (was +/- 20 mV, is ±35 mV). Rev. 5 • In Table 2-3, changed VCAP value from 4.7F to 2.2F. • Revised Section 7, Security Features. • Added information for 56F8027 device throughout document. • Fixed miscellaneous typos. 56F8037/56F8027 Data Sheet, Rev. 8 2 Freescale Semiconductor Document Revision History Version History Description of Change Rev. 6 In the table Recommended Operating Conditions, removed the line “XTAL not driven by an external clock“ from the characteristic: “Oscillator Input Voltage High XTAL not driven by an external clock XTAL driven by an external clock source” In the table 56F8037/56F8027 Ordering Information, changed “MC56F8027VLD“ to “MC56F8027VLH“ Removed “Preliminary” from data sheet In the Select Peripheral Input Source for PWM2/PWM3 Pair Source Bits, fixed typos Added new part number to ordering information: MC56F8027MLH Rev. 7 Added MC56F8037MLH to the part ordering table. Rev. 8 • In section Section 5.6.18, changed bit15 from “PENDING” to reserved. • Added section Section 5.6.18.2 to describe the reserved bit. Please see http://www.freescale.com for the most current data sheet revision. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 3 56F8037/56F8027 General Description • Up to 32 MIPS at 32MHz core frequency • Three Programmable Interval Timers (PITs) • DSP and MCU functionality in a unified, C-efficient architecture • Two Queued Serial Communication Interfaces (QSCIs) with LIN slave functionality • 56F8037 offers 64KB (32K x 16) Program Flash • Two Queued Serial Peripheral Interfaces (QSPIs) • 56F8027 offers 32KB (16K x 16) Program Flash • Freescale’s scalable controller area network (MSCAN) 2.0 A/B Module • 56F8037 offers 8KB (4K x 16) Unified Data/Program RAM • Two 16-bit Quad Timers • 56F8027 offers 4KB (2K x 16) Unified Data/Program RAM • One Inter-Integrated Circuit (I2C) port • Computer Operating Properly (COP)/Watchdog • One 6-channel PWM module • On-Chip Relaxation Oscillator • Two 8-channel 12-bit Analog-to-Digital Converters (ADCs) • Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module • Two 12-bit Digital-to-Analog Converters (DACs) • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Two Analog Comparators RESET or GPIOA 4 JTAG/EOnCE Port or GPIOD PWM or TMRA or TMRB or CMP or QSPI1 or GPIOA 14 2 8 8 DAC or GPIOD VDD VSS 2 3 4 Digital Reg VDDA VSSA Analog Reg Low-Voltage Supervisor 16-Bit 56800E Core Address Generation Unit Program Controller and Hardware Looping Unit VCAP Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit PAB PDB CDBR CDBW AD0 Memory ADC or CMP or QSCI1 or GPIOC AD1 Program Memory 32K x 16 Flash 16K x 16 Flash Unified Data / Program RAM 4K x 16 2K x 16 Programmable Interval Timer I2C or CAN or TMRB or CMP or GPIOB 6 R/W Control XDB2 XAB1 XAB2 System Bus Control PAB PDB CDBR CDBW IPBus Bridge (IPBB) QSPI0 or PWM or I2C or TMRA or GPIOB 4 QSCI0 or PWM or I2C or QSPI1 or TMRA or TMRB or GPIOB COP/ Watchdog Interrupt Controller System Integration Module P O R 4 XTAL, CLKIN, or GPIOD O Clock S Generator* C EXTAL or GPIOD *Includes On-Chip Relaxation Oscillator 56F8037/56F8027 Block Diagram 56F8037/56F8027 Data Sheet, Rev. 8 4 Freescale Semiconductor 56F8037/56F8027 Data Sheet Table of Contents Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 1.3 1.4 1.5 1.6 56F8037/56F8027 Features . . . . . . . . . . . 6 56F8037/56F8027 Description . . . . . . . . . 8 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 9 Architecture Block Diagram . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . 18 Data Sheet Conventions . . . . . . . . . . . . . 18 Part 2 Signal/Connection Descriptions . . . 19 2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . 19 56F8037/56F8027 Signal Pins . . . . . . . . 24 Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 40 Features . . . . . . . . . . . . . . . . . . . . . . . . . 41 Operating Modes . . . . . . . . . . . . . . . . . . 41 Internal Clock Source . . . . . . . . . . . . . . . 42 Crystal Oscillator. . . . . . . . . . . . . . . . . . . 42 Ceramic Resonator . . . . . . . . . . . . . . . . . 43 External Clock Input - Crystal Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . 43 Alternate External Clock Input . . . . . . . . 44 Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 44 4.1 4.2 4.3 4.4 4.5 4.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . 44 Interrupt Vector Table . . . . . . . . . . . . . . . 45 Program Map . . . . . . . . . . . . . . . . . . . . . 47 Data Map . . . . . . . . . . . . . . . . . . . . . . . . 48 EOnCE Memory Map . . . . . . . . . . . . . . . 50 Peripheral Memory-Mapped Registers . . 51 Part 5 Interrupt Controller (ITCN) . . . . . . . . 68 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . 68 Features . . . . . . . . . . . . . . . . . . . . . . . . . 68 Functional Description . . . . . . . . . . . . . . 68 Block Diagram. . . . . . . . . . . . . . . . . . . . . 70 Operating Modes . . . . . . . . . . . . . . . . . . 71 Register Descriptions . . . . . . . . . . . . . . . 71 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Part 6 System Integration Module (SIM) . . . 93 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . 93 Features . . . . . . . . . . . . . . . . . . . . . . . . . 94 Register Descriptions . . . . . . . . . . . . . . . 95 Clock Generation Overview . . . . . . . . . 124 Power-Saving Modes . . . . . . . . . . . . . . 124 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 126 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 129 7.3 Product Analysis. . . . . . . . . . . . . . . . . . 131 Part 8 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . .131 8.1 8.2 8.3 Introduction. . . . . . . . . . . . . . . . . . . . . . 131 Configuration . . . . . . . . . . . . . . . . . . . . 131 Reset Values . . . . . . . . . . . . . . . . . . . . 135 Part 9 Joint Test Action Group (JTAG) . . .140 9.1 56F8037/56F8027 Information . . . . . . . 140 Part 10Specifications. . . . . . . . . . . . . . . . . .140 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 General Characteristics . . . . . . . . . . . . 140 DC Electrical Characteristics . . . . . . . . 144 AC Electrical Characteristics . . . . . . . . 147 Flash Memory Characteristics . . . . . . . 148 External Clock Operation Timing . . . . . 148 Phase Locked Loop Timing . . . . . . . . . 149 Relaxation Oscillator Timing. . . . . . . . . 149 Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 151 Serial Peripheral Interface (SPI) Timing 152 Quad Timer Timing. . . . . . . . . . . . . . . . 156 Queued Serial Communication Interface (QSCI) Timing . . . . . . . . . . . . . . . 158 Freescale’s Scalable Controller Area Network (MSCAN) Timing . . . . . . 159 Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . . . . . . . . . . . . . . . 159 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 161 Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . . . . 162 Equivalent Circuit for ADC Inputs . . . . . 163 Comparator (CMP) Parameters . . . . . . 164 Digital-to-Analog Converter (DAC) Parameters . . . . . . . . . . . . . . . . . 164 Power Consumption . . . . . . . . . . . . . . . 166 Part 11Packaging . . . . . . . . . . . . . . . . . . . . .168 11.1 56F8037/56F8027 Package and Pin-Out Information . . . . . . . . . . . 168 Part 12Design Considerations . . . . . . . . . .171 12.1 12.2 Thermal Design Considerations . . . . . . 171 Electrical Design Considerations . . . . . 172 Part 13Ordering Information . . . . . . . . . . . .173 Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .174 Part 7 Security Features. . . . . . . . . . . . . . . 129 7.1 7.2 Operation with Security Enabled. . . . . . 129 Flash Access Lock and Unlock Mechanisms130 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 5 Part 1 Overview 1.1 56F8037/56F8027 Features 1.1.1 • • • • • • • • • • • • • • 1.1.2 Digital Signal Controller Core Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency Single-cycle 16  16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits 32-bit arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller-style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging Difference Between Devices Table 1-1 outlines the key differences between the 56F8037 and 56F8027 devices. Table 1-1 Device Differences Feature 1.1.3 • • • 56F8037 56F8027 Program Flash 64KB 32KB Unified Data/Program RAM 8KB 4KB Memory Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security and protection that prevent unauthorized users from gaining access to the internal Flash On-chip memory — 64KB of Program Flash (56F8037 device) 32KB of Program Flash (56F8027 device) — 8KB of Unified Data/Program RAM (56F8037 device) 4KB of Unified Data/Program RAM (56F8027 device) • EEPROM emulation capability using Flash 56F8037/56F8027 Data Sheet, Rev. 8 6 Freescale Semiconductor 56F8037/56F8027 Features 1.1.4 • Peripheral Circuits for 56F8037/56F8027 One multi-function six-output Pulse Width Modulator (PWM) module — Up to 96MHz PWM operating clock — 15 bits of resolution — Center-aligned and Edge-aligned PWM signal mode — Four programmable fault inputs with programmable digital filter — Double-buffered PWM registers — Each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – External GPIO – Internal timers – Analog comparator outputs – ADC conversion result which compares with values of ADC high- and low-limit registers to set PWM output • Two independent 12-bit Analog-to-Digital Converters (ADCs) — 2 x 8 channel inputs — Supports both simultaneous and sequential conversions — ADC conversions can be synchronized by both PWM and timer modules — Sampling rate up to 2.67MSPS — 16-word result buffer registers • Two 12-bit Digital-to-Analog Converters (DACs) — 2 microsecond settling time when output swing from rail to rail — Automatic waveform generation generates square, triangle and sawtooth waveforms with programmable period, update rate, and range • Two 16-bit multi-purpose Quad Timer modules (TMRs) — Up to 96MHz operating clock — Eight independent 16-bit counter/timers with cascading capability — Each timer has capture and compare capability — Up to 12 operating modes • Two Queued Serial Communication Interfaces (QSCIs) with LIN Slave functionality — Full-duplex or single-wire operation — Two receiver wake-up methods: – Idle line – Address mark — Four-bytes-deep FIFOs are available on both transmitter and receiver • Two Queued Serial Peripheral Interfaces (QSPIs) 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 7 — Full-duplex operation — Master and slave modes — Four-words-deep FIFOs available on both transmitter and receiver — Programmable Length Transactions (2 to 16 bits) • One Inter-Integrated Circuit (I2C) port — Operates up to 400kbps — Supports both master and slave operation — Supports both 10-bit address mode and broadcasting mode • One Freescale scalable controller area network (MSCAN) module — Fully compliant with CAN protocol - Version 2.0 A/B — Supports standard and extended data frames — Supports data rate up to 1Mbps — Five receive buffers and three transmit buffers • • Three 16-bit Programmable Interval Timers (PITs) Two analog Comparators (CMPs) — Selectable input source includes external pins, DACs — Programmable output polarity — Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs — Output falling and rising edge detection able to generate interrupts • • • • • Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources Up to 53 General-Purpose I/O (GPIO) pins with 5V tolerance Integrated Power-On Reset and Low-Voltage Interrupt Module Phase Lock Loop (PLL) to provide high-speed clock to the core and peripherals Clock sources: — On-chip relaxation oscillator — External clock: crystal oscillator, ceramic resonator and external clock source • 1.1.5 • • • • • JTAG/EOnCE debug programming interface for real-time debugging Energy Information Fabricated in high-density CMOS with 5V tolerance On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power 1.2 56F8037/56F8027 Description The 56F8037/56F8027 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, 56F8037/56F8027 Data Sheet, Rev. 8 8 Freescale Semiconductor Award-Winning Development Environment configuration flexibility, and compact program code, the 56F8037/56F8027 is well-suited for many applications. The 56F8037/56F8027 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inverters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F8037/56F8027 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8037/56F8027 also offers up to 53 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8037 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified Data/Program RAM. The 56F8027 Digital Signal Controller includes 32KB of Program Flash and 4KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages. Program Flash page erase size is 512 Bytes (256 Words). A full set of programmable peripherals—PWM, ADCs, QSCIs, QSPIs, I2C, PITs, Quad Timers, DACs and analog comparators—supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs). 1.3 Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 Architecture Block Diagram The 56F8037/56F8027’s architecture is shown in Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. Figures 1-3, 1-4, 1-5, 1-6 and 1-7 detail how the device’s I/O pins are muxed. The figures do not show the on-board regulator and power and ground signals. Please see Part 2, Signal/Connection Descriptions, for information about which signals are multiplexed with those of other peripherals. 1.4.1 PWM, TMR and ADC Connections Figure 1-6 shows the over-limit and under-limit connections from the ADC to the PWM and the 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 9 connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for additional information. The PWM_reload_sync output can be connected to Timer A’s (TMRA) Channel 3 input; TMRA’s Channels 2 and 3 outputs are connected to the ADC sync inputs. TMRA Channel 3 output is connected to SYNC0 and TMRA Channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ADCB in parallel independent mode. These are controlled by bits in the SIM Control Register; see Section 6.3.1. 56F8037/56F8027 Data Sheet, Rev. 8 10 Freescale Semiconductor Architecture Block Diagram DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) Instruction Decoder Interrupt Unit ALU1 ALU2 R0 R1 R2 R3 R4 R5 N M01 N3 Looping Unit Program Memory SP XAB1 XAB2 PAB PDB Data / Program RAM CDBW CDBR XDB2 A2 B2 C2 D2 BitManipulation Unit Enhanced OnCE™ JTAG TAP Y A1 B1 C1 D1 Y1 Y0 X0 MAC and ALU A0 B0 C0 D0 IPBUS Interface Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter Figure 1-1 56800E Core Block Diagram 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 11 To/From IPBus Bridge OCCS (ROSC / PLL / OSC) Interrupt Controller Low-Voltage Interrupt GPIO A POR & LVI GPIO B System POR GPIO C SIM GPIO D RESET (Muxed with GPIOA7) COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8037/56F8027 Data Sheet, Rev. 8 12 Freescale Semiconductor Architecture Block Diagram To/From IPBus Bridge IPBus INTC SYNC PIT0 MSTR_CNT_EN 3 MSTR_CNT_EN DAC SYNC on Figure 1-5 SYNC PIT1 MSTR_CNT_EN SYNC PIT2 2 3 Sync0, Sync1 Over/Under Limits SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on Figure 1-5 GPIOC2 ANA2 (VREFHA) GPIOC3 ANA3 (VREFLA) ANA4 ANA1, 5-7 ADC ANB0 ANA4 on Figure 1-4 ANA1, 5-7 4 GPIOC1, 9-11 ANB0 on Figure 1-5 GPIOC6 ANB2 (VREFHA) GPIOC7 ANB3 (VREFLB) ANB4 ANB1, 5-7 ANB4 on Figure 1-4 ANB1, 5-7 4 GPIOC5, 13-15 Figure 1-3 56F8037/56F8027 I/O Pin-Out Muxing (Part 1/5) 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 13 To/From IPBus Bridge CLKO TA0 on Figure 1-7 GPIOB4 SS1 QSPI1 3 TA1-3 on Figure 1-7 SCLK1, MISO1, MOSI1 3 GPIOA12 - 14 3 TB0 on Figure 1-5 T0 TMRB TB1 on Figure 1-5 T1 T2, T3 1 2 QSCI0 2 TB2, TB3 on Figure 1-5 2 GPIOB6 - 7 RXD0, TXD0 2 TA2, TA3 on Figure 1-7 MISO0, MOSI0 QSPI0 GPIOB2 - 3 2 SCLK0, SS0 2 2 I2C SCL, SDA GPIOB0 - 1 2 2 2 GPIOB8 - 9 2 MSCAN CANTX, CANRX 2 2 ANA4, ANB4 on Figure 1-3 QSCI1 TXD1, RXD1 GPIOB12 - 13 2 GPIOC8 - 12 2 IPBus Figure 1-4 56F8037/56F8027 I/O Pin-Out Muxing (Part 2/5) 56F8037/56F8027 Data Sheet, Rev. 8 14 Freescale Semiconductor Architecture Block Diagram To/From IPBus Bridge FAULT1 on Figure 1-6 TA2 on Figure 1-7 CMP_IN1 CMP_IN3 CMPAI1 CMPAI3 GPIOC0 CMPA CMP_OUT CMP_IN2 Export Import GPIOA8 CMPAO on Figure 1-6, Figure 1-7 CMPAI2 GPIOA10 ANA0 on Figure 1-3 TB2 on Figure 1-4 GPIOB10 DAC0 TB0 on Figure 1-4 2 3 DAC0 GPIOD6 DAC1 GPIOD7 TA0o, TA1o on Figure 1-7 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 TB1 on Figure 1-4 DAC1 TB3 on Figure 1-4 Import Export CMP_IN2 CMP_OUT ANB0 on Figure 1-3 GPIOB11 GPIOA11 CMPBI2 CMPBO on Figure 1-6, Figure 1-7 CMPB GPIOC4 CMP_IN3 CMP_IN1 CMPBI3 CMPBI1 TA3 on Figure 1-7 GPIOA9 FAULT2 on Figure 1-6 IPBus Figure 1-5 56F8037/56F8027 I/O Pin-Out Muxing (Part 3/5) 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 15 To/From IPBus Bridge TA0 on Figure 1-7 GPIOA6 2 TA2 - 3 on Figure 1-7 GPIOA0 - 3 4 PWM0 - 3 FAULT0 2 PWMA4 - 5 1 GPIOA4 - 5 2 PWM FAULT1 FAULT1 on Figure 1-5 CMPAO on Figure 1-5 FAULT2 RELOAD PSRC0 - 2 1 FAULT3 FAULT2 on Figure 1-5 CMPBO on Figure 1-5 TA1 on Figure 1-7 RELOAD on Figure 1-7, Figure 1-5 IPBus GPIOB5 CMPBO on Figure 1-5 CMPAO on Figure 1-5 3 3 3 3 GPIOB2 - 4 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3o on Figure 1-3 Figure 1-6 56F8037/56F8027 I/O Pin-Out Muxing (Part 4/5) 56F8037/56F8027 Data Sheet, Rev. 8 16 Freescale Semiconductor Architecture Block Diagram To/From IPBus Bridge TA0o on Figure 1-6 (PWM) T0o T0i TA0 on Figure 1-6 (GPIOA6) TA0 on Figure 1-4 (GPIOB4) T1o T1i TA1 on Figure 1-4(GPIOA12) TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA) SYNC1 on Figure 1-3 (ADC) TMRA TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) T2o T2i TA2 on Figure 1-5 (GPIOA8) TA2 on Figure 1-4 (GPIOA13) TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5) T3o T3i TA3 on Figure 1-5 (GPIOA9) TA3 on Figure 1-4 (GPIOA14) TA 3 on Figure 1-4 (GPIOB3) RELOAD on Figure 1-6 (PWM) IPBus Figure 1-7 56F8037/56F8027 I/O Pin-Out Muxing (Part 5/5) 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 17 1.5 Product Documentation The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8037/56F8027. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.com Table 1-2 56F8037/56F8027 Chip Documentation Topic Description Order Number DSP56800E Reference Manual Detailed description of the 56800E family architecture, 16-bit Digital Signal Controller core processor, and the instruction set DSP56800ERM 56F802x and 56F803x Peripheral Reference Manual Detailed description of peripherals of the 56F802x and 56F803x family of devices MC56F80xxRM 56F802x and 56F803x Serial Bootloader User Guide Detailed description of the Serial Bootloader in the 56F802x and 56F803x family of devices 56F80xxBLUG 56F8037/56F8027 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) MC56F8037/56F8027 56F8037/56F8027 Errata Details any chip issues that might be present MC56F8037/56F8027E 1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F8037/56F8027 Data Sheet, Rev. 8 18 Freescale Semiconductor Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8037/56F8027 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Power Inputs (VDD, VDDA) 4 Ground (VSS, VSSA) 5 Supply Capacitors 2 Reset1 1 Pulse Width Modulator (PWM) Ports1 13 Queued Serial Peripheral Interface 0 (QSPI0) Ports1 4 Queued Serial Peripheral Interface 1 (QSPI1) Ports1 4 Timer Module A (TMRA) Ports1 4 Timer Module B (TMRB) Ports1 4 Analog-to-Digital Converter (ADC) Ports1 16 Digital-to-Analog Converter (DAC) Ports1 2 Queued Serial Communications Interface 0 (QSCI0) Ports1 2 Queued Serial Communications Interface 1 (QSCI1) Ports1 2 Inter-Integrated Circuit Interface (I2C) Ports1 2 MSCAN Ports1 2 Oscillator Signals1 2 JTAG/Enhanced On-Chip Emulation (EOnCE)1 4 1. Pins may be shared with other peripherals. See Table 2-2. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 19 In Table 2-2, peripheral pins in bold identify reset state. Table 2-2 56F8037/56F8027 Pins Peripherals: Pin # Pin Name Signal Name GPIO I2C QSCI RXD0 QSPI ADC PWM Quad Timer DAC Comp MSCAN Power & Ground 1 GPIOB6 GPIOB6, RXD0, SDA, CLKIN B6 SDA 2 GPIOB1 GPIOB1, SS0, SDA B1 SDA 3 GPIOB7 GPIOB7, TXD0, SCL B7 SCL 4 GPIOB5 GPIOB5, TA1, FAULT3, CLKIN B5 FAULT3 TA1 5 GPIOA9 GPIOA9, FAULT2, TA3, CMPBI1 A9 FAULT2 TA3 CMPBI1 6 GPIOA11 GPIOA11, TB3, CMPBI2 A11 TB3 CMPBI2 7 VDD VDD VDD 8 VSS VSS VSS 9 GPIOC12 GPIOC12, ANB4, RXD1 C12 10 GPIOC4 GPIOC4, ANB0, CMPBI3 C4 ANB0 11 GPIOC5 GPIOC5, ANB1 C5 ANB1 12 GPIOC13 GPIOC13, ANB5 C13 ANB5 13 GPIOC6 ANB2, VREFHB C6 ANB2 VREFHB 14 GPIOC7 GPIOC7, ANB3, VREFLB C7 ANB3 VREFLB 15 GPIOD7 GPIOD7, DAC1 D7 16 VDDA VDDA VDDA 17 VSSA VSSA VSSA 18 GPIOD6 GPIOD6, DAC0 D6 19 GPIOC3 GPIOC3, ANA3, VREFLA C3 ANA3 VREFLA 20 GPIOC2 GPIOC2, ANA2, VREFHA C2 ANA2 VREFHA JTAG Misc. CLKIN SS0 TXD0 RXD1 CLKIN ANB4 CMPBI3 DAC1 DAC0 21 GPIOC9 GPIOC9, ANA5 C9 ANA5 22 GPIOC1 GPIOC1, ANA1 C1 ANA1 23 GPIOC10 GPIOC10, ANA6 C10 ANA6 24 GPIOC0 GPIOC0, ANA0, CMPAI3 C0 ANA0 25 GPIOC11 GPIOC11, ANA7 C11 26 GPIOC8 GPIOC8, ANA4, TXD1 C8 27 VSS VSS CMPAI3 ANA7 TXD1 ANA4 VSS 56F8037/56F8027 Data Sheet, Rev. 8 20 Freescale Semiconductor Introduction Table 2-2 56F8037/56F8027 Pins (Continued) Peripherals: Pin # Pin Name 28 VCAP Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN VCAP Power & Ground JTAG Misc. VCAP 29 TCK TCK, GPIOD2 D2 30 GPIOB10 GPIOB10, CMPAO, TB0 B10 TCK 31 RESET RESET, GPIOA7 A7 32 GPIOB3 GPIOB3, MOSI0, TA3, PSRC1 B3 MOSI0 PSRC1 TA3 33 GPIOB2 GPIOB2, MISO0, TA2, PSRC0 B2 MISO0 PSRC0 TA2 34 GPIOA6 GPIOA6, FAULT0, TA0 A6 FAULT0 TA0 35 GPIOA10 GPIOA10, TB2, CMPAI2 A10 36 GPIOA8 GPIOA8, FAULT1, TA2, CMPAI1 A8 37 GPIOA12 GPIOA12, TB1, SCLK1, TA1 A12 SCLK1 38 GPIOB4 GPIOB4, SS1, TB0, TA0, PSRC2, CLKO B4 SS1 39 GPIOA5 GPIOA5, PWM5, TA3, FAULT2 A5 40 VSS VSS VSS 41 VDD VDD VDD 42 GPIOB0 GPIOB0, SCLK0, SCL B0 43 GPIOA4 GPIOA4, PWM4, TA2, FAULT1 A4 44 GPIOA13 GPIOA13, TB2, MISO1, TA2 A13 MISO1 TB2 TA2 45 GPIOA14 GPIOA14, TB3, MOSI1, TA3 A14 MOSI1 TB3 TA3 46 GPIOB9 GPIOB9, SDA, CANRX B9 47 GPIOA2 GPIOA2, PWM2 A2 PWM2 48 GPIOA3 GPIOA3, PWM3 A3 PWM3 49 VCAP VCAP VCAP 50 VDD VDD VDD 51 VSS VSS VSS 52 GPIOD5 GPIOD5, XTAL, CLKIN D5 XTAL CLKIN 53 GPIOD4 GPIOD4, EXTAL D4 EXTAL 54 GPIOB8 GPIOB8, SCL, CANTX B8 55 GPIOA1 GPIOA1, PWM1 A1 TB0 CMPAO RESET FAULT1 SCL TB2 CMPAI2 TA2 CMPAI1 TB1 TA1 PSRC2 TA0 TB0 PWM5 FAULT2 TA3 CLKO SCLK0 PWM4 FAULT1 TA2 SDA CANRX SCL CANTX PWM1 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 21 Table 2-2 56F8037/56F8027 Pins (Continued) Peripherals: Pin # Pin Name Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN Power & Ground JTAG 56 GPIOA0 GPIOA0, PWM0 A0 57 GPIOB12 GPIOB12, CANTX B12 CANTX 58 GPIOB13 GPIOB13, CANRX B13 CANRX 59 TDI TDI, GPIOD0 D0 60 GPIOB11 GPIOB11, CMPBO, TB1 B11 61 GPIOC15 GPIOC15, ANB7 C15 ANB7 62 GPIOC14 GPIOC14, ANB6 C14 ANB6 63 TMS TMS, GPIOD3 D3 TMS 64 TDO TDO, GPIOD1 D1 TDO Misc. PWM0 TD1 TB1 CMPBO 56F8037/56F8027 Data Sheet, Rev. 8 22 Freescale Semiconductor Introduction VDD Power VSS Ground VDDA Power VSSA Ground Other Supply Ports VCAP GPIOD4 (EXTAL) OSC Port or GPIO GPIOD5 (XTAL, CLKIN) 3 4 1 1 4 1 1 1 56F8037/56F8027 2 1 1 1 1 1 1 1 RESET or GPIOA RESET (GPIOA7) 1 1 1 GPIOB0 (SCLK0, SCL) QSPI0 or I2C or PWM or TMRA or GPIOB GPIOB1 (SS0, SDA) GPIOB2 (MISO0, TA2, PSRC0) GPIOB3 (MOSI0, TA3, PSRC1) 1 1 1 1 1 1 1 1 1 QSCI0 or PWM or I2C or TMRA or TMRB or QSPI1 or GPIOB GPIOB4 (SS1, TB0, TA0, PSRC2, CLKO) GPIOB5 (TA1, FAULT3, CLKIN) 1 1 1 GPIOB7 (TXD0, SCL) 1 1 1 1 GPIOD6-7 (DAC0-1) 1 2 1 3 TDI (GPIOD0) TDO (GPIOD1) JTAG/ EOnCE or GPIOD TCK (GPIOD2) TMS (GPIOD3) GPIOA4 (PWM4, TA2, FAULT1) GPIOA5 (PWM5, TA3, FAULT2) GPIOA6 (FAULT0, TA0) GPIOA8 (FAULT1, TA2, CMPAI1) GPIOA9 (FAULT2, TA3, CMPBI1) GPIOA10 (TB2, CMPAI2) GPIOA11 (TB3, CMPBI2) PWM or TMRA or TMRB or CMP or QSPI1 or GPIOA GPIOA12 (SCLK1, TB1, TA1) GPIOA13 (MISO1, TB2, TA2) GPIOA14 (MOSI1, TB3, TA3) GPIOB8 (SCL, CANTX) GPIOB9 (SDA, CANRX) GPIOB10 (TB0, CMPAO) GPIOB11 (TB1, CMPBO) GPIOB12 (CANTX) I2 C or CAN or TMRB or CMP or GPIOB GPIOB13 (CANRX) 1 GPIOB6 (RXD0, SDA, CLKIN) DAC or GPIOD GPIOA0-3 (PWM0-3) 1 1 1 1 1 1 1 1 1 3 GPIOC0 (ANA0 & CMPAI3) GPIOC1 (ANA1) GPIOC2 (ANA2, VREFHA) GPIOC3 (ANA3, VREFLA) GPIOC8 (ANA4, TXD1) GPIOC9-11 (ANA5-7) GPIOC4 (ANB0 & CMPBI3) ADC or CMP or QSCI1 or GPIOC GPIOC5 (ANB1) GPIOC6 (ANB2, VREFHB) GPIOC7 (ANB3, VREFLB) GPIOC12 (ANB4, RXD1) GPIOC13-15 (ANA5-7) Figure 2-1 56F8037/56F8027 Signals Identified by Functional Group 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 23 2.2 56F8037/56F8027 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 7 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VDD 41 VDD 50 VSS 8 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers. VSS 27 VSS 40 VSS 51 VDDA 16 Supply Supply ADC Power — This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. VSSA 17 Supply Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules. VCAP 28 Supply Supply VCAP 49 VCAP — Connect this pin to a 2.2F or greater bypass capacitor in order to bypass the core voltage regulator, required for proper chip operation. See Section 10.2.1. RESET 31 Input Input, internal pull-up enabled Reset — This input is a direct hardware reset on the processor. When RESET is asserted low, the chip is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. (GPIOA7) Input/Open Drain Output Port A GPIO — This GPIO pin can be individually programmed as an input or open drain output pin. Note that RESET functionality is disabled in this mode and the chip can only be reset via POR, COP reset, or software reset. After reset, the default state is RESET. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 24 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA0 56 (PWM0) Type Input/ Output State During Reset Input, internal pull-up enabled Output Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0. GPIOA1 55 (PWM1) Input/ Output Input, internal pull-up enabled Output Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM1 — This is one of the six PWM output pins. After reset, the default state is GPIOA1. GPIOA2 47 (PWM2) Input/ Output Input, internal pull-up enabled Output Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM2 — This is one of the six PWM output pins. After reset, the default state is GPIOA2. GPIOA3 48 (PWM3) Input/ Output Output Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM3 — This is one of the six PWM output pins. After reset, the default state is GPIOA3. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 25 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA4 43 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM4) Output PWM4 — This is one of the six PWM output pins. (TA21) Input/ Output TA2 — Timer A, Channel 2 (FAULT12) Input Fault1 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA4. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 1 The TA2 signal is also brought out on the GPIOA8-9, GPIOA13-14 and GPIOB2-3 pins. 2 The Fault1 signal is also brought out on the GPIOA8-9, GPIOB4 and GPIOB10 pins. GPIOA5 39 Input/ Output Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM5) Output PWM5 — This is one of the six PWM output pins. (TA33) Input/ Output TA3 — Timer A, Channel 3 (FAULT24) Input Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA5. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 3 The TA3 signal is also brought out on the GPIOA8-9, GPIOA13-14 and GPIOB2-3 pins. 4The Fault2 signal is also brought out on the GPIOA8-9, GPIOB4 and GPIOB10 pins. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 26 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA6 34 Type Input/ Output State During Reset Input, internal pull-up enabled Input (FAULT0) Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA0 — Timer A, Channel 0. (TA05) After reset, the default state is GPIOA6. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 5 The TA0 signal is also brought out on the GPIOB4 pin. GPIOA8 36 Input/ Output (FAULT1) Input (TA2) Input/ Output (CMPAI1) Input Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault1 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA2 — Timer A, Channel 2. Comparator A, Input 1 — This is an analog input to Comparator A. After reset, the default state is GPIOA8. The peripheral functionality is controlled via the SIM. See Section 6.3.16. GPIOA9 5 Input/ Output (FAULT2) Input (TA3) Input/ Output (CMPBI1) Input Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault2 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA2 — Timer A, Channel 3. Comparator B, Input 1 — This is an analog input to Comparator B. After reset, the default state is GPIOA9. The peripheral functionality is controlled via the SIM. See Section 6.3.16. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 27 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA10 35 Type Input/ Output (TB26) Input/ Output (CMPAI2) Input State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. TB2 — Timer B, Channel 2. Comparator A, Input 2 — This is an analog input to Comparator A. After reset, the default state is GPIOA10. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 6 The TB2 signal is also brought out on the GPIOA13 pin. GPIOA11 6 Input/ Output (TB37) Input/ Output (CMPBI2) Input Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. TB3 — Timer B, Channel 3. Comparator B, Input 2 — This is an analog input to Comparator B. After reset, the default state is GPIOA11. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 7 The TB3 signal is also brought out on the GPIOA14 pin. GPIOA12 37 Input/ Output Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (SCLK1) Input/ Output QSPI1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. (TB18) Input/ Output TB1 — Timer B, Channel 1. (TA19) Input/ Output TA1 — Timer A, Channel 1. After reset, the default state is GPIOA12. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 8The 9 TB1 signal is also brought out on the GPIOB11 pin. The TA1 signal is also brought out on the GPIOB5 pin. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 28 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA13 44 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO1) Input/ Output QSPI1 Master In/Slave Out— This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master devices uses to latch the data. (TB210) Input/ Output TB2 — Timer B, Channel 2. (TA211) Input/ Output TA2 — Timer A, Channel 2. After reset, the default state is GPIOA13. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 10 The TB2 signal is also brought out on the GPIOA10 pin. 11The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOB2 pins. GPIOA14 45 (MOSI1) Input/ Output Input/ Output Input, internal pull-up enabled Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI1 MasterOut/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave devices uses to latch the data. TB3 — Timer B, Channel 3. 12 (TB312) Input/ Output TA3 — Timer A, Channel 3. (TA313) Input/ Output After reset, the default state is GPIOA14. The peripheral functionality is controlled via the SIM. See Section 6.3.16. The TB3 signal is also brought out on the GPIOA11 pin. 13The TA3 signal is also brought out on the GPIOA5, GPIOA9, and GPIOB3 pins. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 29 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB0 42 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SCLK0) Input/ Output QSPI0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. A Schmitt trigger input is used for noise immunity. (SCL14) Input/ Output Serial Clock — This pin serves as the I2C serial clock. After reset, the default state is GPIOB0. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 14The SCL signal is also brought out on the GPIOB7 and GPIOB8 pins. GPIOB1 2 Input/ Output (SS0) Input/ Output (SDA15) Input Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. QSPI0 Slave Select — SS is used in slave mode to indicate to the QSPI0 module that the current transfer is to be received. Serial Data — This pin serves as the I2C serial data line. After reset, the default state is GPIOB1. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 15The SDA signal is also brought out on the GPIOB6 and GPIOB9 pins. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 30 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB2 33 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO0) Input/ Output QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. (TA216) Input/ Output TA2 — Timer A, Channel 2 (PSRC0) Input PSRC0 — External PWM signal source input for the complementary PWM4/PWM5 pair. After reset, the default state is GPIOB2. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 16The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOA13 pins. GPIOB3 32 Input/ Output Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MOSI0) Input/ Output QSPI0 Master Out/Slave In— This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. (TA317) Input/ Output TA3 — Timer A, Channel 3 (PSRC1) Input PSRC1 — External PWM signal source input for the complementary PWM2/PWM3 pair. After reset, the default state is GPIOB3. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 17The TA3 signal is also brought out on the GPIOA5, GPIOA9 and GPIOA14 pins. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 31 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB4 38 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SS1) Input/ Output QSPI1 Slave Select — This is used in slave mode to indicate to the QSPI1 module that the current transfer is to be received. (TB018) Input/ Output TB0 — Timer B, Channel 0 (TA019) Input/ Output TA0 — Timer A, Channel 0 Input (PSRC2) PSRC2 — External PWM signal source input for the complementary PWM0/PWM1 pair. Output (CLKO) Clock Output — This is a buffered clock output; the clock source is selected by Clockout Select (CLKOSEL) bits in the Clock Output Select Register (CLKOUT). See Section 6.3.7. After reset, the default state is GPIOB4. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 18The 19 TB0 signal is also brought out on the GPIOB4 and GPIOB10 pins. The TA0 signal is also brought out on the GPIOB4 and GPIOA6 pins. GPIOB5 4 Input/ Output Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (TA120) Input/ Output (FAULT3) Input FAULT3 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. (CLKIN) Input External Clock Input— This pin serves as an external clock input. TA1 — Timer A, Channel 1 After reset, the default state is GPIOB5. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 20 The TA1 signal is also brought out on the GPIOA12 pin. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 32 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB6 1 Type Input/ Output (RXD0) Input (SDA21) Input/ Output (CLKIN) Input State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Receive Data 0 — QSCI0 receive data input. Serial Data — This pin serves as the I2C serial data line. External Clock Input — This pin serves as an optional external clock input. After reset, the default state is GPIOB6. The peripheral functionality is controlled via the SIM (See Section 6.3.16) and the CLKMODE bit of the OCCS Oscillator Control Register. 21 The SDA signal is also brought out on the GPIOB1 and GPIOB9 pins. GPIOB7 3 Input/ Output (TXD0) Input/ Output (SCL22) Input/ Output 22The Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Transmit Data 0 — QSCI0 transmit data output or transmit / receive in single wire operation. Serial Clock — This pin serves as the I2C serial clock. After reset, the default state is GPIOB7. The peripheral functionality is controlled via the SIM. See Section 6.3.16. SCL signal is also brought out on the GPIOB0 and GPIOB8 pins. GPIOB8 54 Input/ Output (SCL23) Input/ Output (CANTX24) Open Drain Output Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Serial Clock 1 — This pin serves as the I2C serial clock. CAN Transmit Data — This is the SCAN interface output. After reset, the default state is GPIOB8. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 23 The SCL signal is also brought out on the GPIOB0 and GPIOB7 pins. 24 The CANTX signal is also brought out on the GPIOB12 pin. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 33 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB9 46 Type Input/ Output (SDA25) Input/ Output (CANRX26) Input State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Serial Data 1 — This pin serves as the I2C serial data line. CAN Receive Data — This is the MSCAN interface input. After reset, the default state is GPIOB9. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 25 The SDA signal is also brought out on the GPIOB1 and GPIOB6 pins. 26 The CANRX signal is also brought out on the GPIOB13 pin. GPIOB10 30 Input/ Output (TB027) Input/ Output (CMPAO) Output Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. TB0— Timer B, Channel 0. Comparator A Output— This is the output of comparator A. After reset, the default state is GPIOB10. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 27The TB0 signal is also brought out on the GPIOB4 pin. GPIOB11 60 Input/ Output (TB128) Input/ Output (CMPBO) Output Input, internal pull-up enabled Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. TB1— Timer B, Channel 1. Comparator B Output— This is the output of comparator B. After reset, the default state is GPIOB11. The peripheral functionality is controlled via the SIM. See Section 6.3.16. 28 The TB1 signal is also brought out on the GPIOA12 pin. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 34 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB12 57 Type Input/ Output State During Reset Input Open Drain Output (CANTX29) Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. CAN Transmit Data — This is the MSCAN interface output. After reset, the default state is GPIOB12. 29 The CANTX signal is also brought out on the GPIOB8 pin. GPIOB13 58 Input/ Output Input Input (CANRX30) Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. CAN Receive Data — This is the MSCAN interface input. After reset, the default state is GPIOB13. 30 The CANRX signal is also brought out on the GPIOB9 pin. GPIOC0 24 (ANA0 & CMPAI3) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA0 — Analog input to ADC A, Channel 0. Comparator A, Input 3 — This is an analog input to Comparator A. When used as an analog input, the signal goes to both ANA0 and CMPAI3. After reset, the default state is GPIOC0. GPIOC1 22 (ANA1) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA1 — Analog input to ADC A, Channel 1. After reset, the default state is GPIOC1. GPIOC2 20 Input/ Output Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANA2) Analog Input ANA2 — Analog input to ADC A, Channel 2. (VREFHA) Analog Input VREFHA — Analog reference voltage high (ADC A). After reset, the default state is GPIOC2. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 35 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC3 19 Type Input/ Output State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANA3) Analog Input ANA3 — Analog input to ADC A, Channel 3. (VREFLA) Analog Input VREFLA — Analog reference voltage low. (ADC A). After reset, the default state is GPIOC3. GPIOC4 10 (ANB0 & CMPBI3) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB0 — Analog input to ADC B, Channel 0. Comparator B, Input 3 — This is an analog input to Comparator B. Analog Input When used an analog input, the signal goes to both ANB0 and CMPB13. After reset, the default state is GPIOC4. GPIOC5 11 (ANB1) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB1 — Analog input to ADC B, Channel 1. After reset, the default state is GPIOC5. GPIOC6 13 Input/ Output (ANB2) Analog Input (VREFHB) Input Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB2 — Analog input to ADC B, Channel 2. VREFHx — Analog reference voltage high (ADC B). After reset, the default state is GPIOC6. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 36 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC7 14 Type Input/ Output (ANB3) Analog Input (VREFLB) Input State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3 — Analog input to ADC B, Channel 3. VREFLB — Analog reference voltage low (ADC B). After reset, the default state is GPIOC7. GPIOC8 26 Input/ Output Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANA4) Analog Input ANA4 — Analog input to ADC A, Channel 4. (TXD1) Input/ Output Transmit Data 1 — SCI1 transmit data output. After reset, the default state is GPIOC8. GPIOC9 21 (ANA5) Input/ Output Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA5 — Analog input to ADC A, Channel 5. Analog Input After reset, the default state is GPIOC9. GPIOC10 23 (ANA6) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA6 — Analog input to ADC A, Channel 6. After reset, the default state is GPIOC10. GPIOC11 25 (ANA7) Input/ Output Analog Input Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA7 — Analog input to ADC A, Channel 7. After reset, the default state is GPIOC11. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 37 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC12 9 Type Input/ Output State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANB4) Analog Input ANB4 — Analog input to ADC B, Channel 4. (RXD1) Input Receive Data 1 — SCI1 receive data input. After reset, the default state is GPIOC12. GPIOC13 12 (ANB5) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB5 — Analog input to ADC B, Channel 5. After reset, the default state is GPIOC13. GPIOC14 62 (ANB6) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB6 — Analog input to ADC B, Channel 6. After reset, the default state is GPIOC14. GPIOC15 61 (ANB7) Input/ Output Input Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB7 — Analog input to ADC B, Channel 7. After reset, the default state is GPIOC15. GPIOD4 53 (EXTAL) Input/ Output Analog Input Input Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Input — This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is being driven by an external clock source. After reset, the default state is GPIOD4. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 38 Freescale Semiconductor 56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOD5 52 Type Input/ Output (XTAL) Analog Input/ Output (CLKIN) Input State During Reset Input Signal Description Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal. External Clock Input — This pin serves as an external clock input. After reset, the default state is GPIOD5. GPIOD6 18 (DAC0) Input/ Output Analog Input Input, internal pull-up enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. DAC0— Digital-to-Analog Converter output 0. After reset, the default state is GPIOD6. GPIOD7 15 (DAC1) Input/ Output Analog Input Input, internal pull-up enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. DAC1— Digital-to-Analog Converter output 1. After reset, the default state is GPIOD7. TDI 59 (GPIOD0) Input Input, internal pull-up enabled Input/ Output Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. TDO 64 (GPIOD1) Output Input/ Output Output tri-stated, internal pull-up enabled Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDO. Return to Table 2-2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 39 Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type TCK 29 Input (GPIOD2) State During Reset Input, internal pull-up enabled Input/ Output Signal Description Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt trigger input is used for noise immunity. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TCK. TMS 63 (GPIOD3) Input Input/ Output Input, internal pull-up enabled Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. Note: Always tie the TMS pin to VDD through a 2.2K resistor. Return to Table 2-2 Part 3 OCCS 3.1 Overview The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32MHz. For details, see the OCCS chapter in the 56F802x and 56F803x Peripheral Reference Manual. 56F8037/56F8027 Data Sheet, Rev. 8 40 Freescale Semiconductor Features 3.2 Features The OCCS module interfaces to the oscillator and PLL and offers these features: • • • • • • • • • Internal relaxation oscillator Ability to power down the internal relaxation oscillator or crystal oscillator Ability to put the internal relaxation oscillator into Standby mode 3-bit postscaler provides control for the PLL output Ability to power down the PLL Provides a 2X system clock which operates at twice the system clock to the System Integration Module (SIM) Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules Safety shutdown feature is available if the PLL reference clock is lost Can be driven from an external clock source The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator. 3.3 Operating Modes In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be used to provide a reference clock to the SIM. The 2X system clock source output from the OCCS can be described by one of the following equations: 2X system frequency = oscillator frequency 2X system frequency = (oscillator frequency x 8) / (postscaler) where: postscaler = 1, 2, 4, 8, 16, or 32 The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle in the system clock output. The 56F8000 family devices’ on-chip clock synthesis module has the following registers: • • • • • Control Register (OCCS_CTRL) Divide-by Register (OCCS_DIVBY) Status Register (OCCS_STAT) Shutdown Register (OCCS_SHUTDN) Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference Manual. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 41 3.4 Internal Clock Source An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It is optimized for accuracy and programmability while providing several power-saving configurations which accommodate different operating conditions. The internal relaxation oscillator has very little temperature and voltage variability. To optimize power, the architecture supports a standby state and a power-down state. During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0). Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a changeover between internal and external clock sources is required at power-on, the user must ensure that the clock source is not switched until the desired external clock source is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved. The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the 56F802x and 56F803x Peripheral Reference Manual. 3.5 Crystal Oscillator The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. 56F8037/56F8027 Data Sheet, Rev. 8 42 Freescale Semiconductor Ceramic Resonator Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 K Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg  CL1 CL2 Figure 3-1 External Crystal Oscillator Circuit 3.6 Ceramic Resonator The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz. Figure 3-2 shows the typical 2 and 3 terminal ceramic resonators and their circuits. Follow the resonator supplier’s recommendations when selecting a resonator, since their parameters determine the component values required to provide maximum stability and reliable start up. The load capacitance values used in the resonator circuit design should include all stray layout capacitances. The resonator and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 3 Terminal 2 Terminal EXTAL XTAL Rz CL1 CL2 EXTAL XTAL Rz C1 Sample External Ceramic Resonator Parameters: Rz = 750 K C2 Figure 3-2 External Ceramic Resonator Circuit 3.7 External Clock Input - Crystal Oscillator Option The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated using a relatively low impedance driver. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 43 56F8037/56F8027 CLKMODE = 1 XTAL EXTAL External Clock GND or GPIO Figure 3-3 Connecting an External Clock Signal using XTAL 3.8 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external clock input. 56F8037/56F8027 GPIO External Clock Figure 3-4 Connecting an External Clock Signal using GPIO Part 4 Memory Maps 4.1 Introduction The 56F8037/56F8027 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both spaces and Flash memory is used only in Program space. This section provides memory maps for: • • Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. 56F8037/56F8027 Data Sheet, Rev. 8 44 Freescale Semiconductor Interrupt Vector Table Table 4-1 Chip Memory Configurations On-Chip Memory 56F8037 56F8027 Use Restrictions Program Flash (PFLASH) 32k x 16 or 64KB 16k x 16 or 32KB Erase / Program via Flash interface unit and word writes to CDBW Unified RAM (RAM) 4k x 16 or 8KB 2k x 16 or 4KB Usable by both the Program and Data memory spaces 4.2 Interrupt Vector Table Table 4-2 provides the 56F8037/56F8027’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.8 for the reset value of the VBA. By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Table 4-2 Interrupt Vector Table Contents1 Peripheral Vector Number Priority Level core Vector Base Address + P:$00 core Interrupt Function Reserved for Reset Overlay2 P:$02 Reserved for COP Reset Overlay core 2 3 P:$04 Illegal Instruction core 3 3 P:$06 SW Interrupt 3 core 4 3 P:$08 HW Stack Overflow core 5 3 P:$0A Misaligned Long Word Access core 6 1-3 P:$0C EOnCE Step Counter core 7 1-3 P:$0E EOnCE Breakpoint Unit core 8 1-3 P:$10 EOnCE Trace Buffer core 9 1-3 P:$12 EOnCE Transmit Register Empty core 10 1-3 P:$14 EOnCE Receive Register Full core 11 2 P:$16 SW Interrupt 2 core 12 1 P:$18 SW Interrupt 1 core 13 0 P:$1A SW Interrupt 0 14 Reserved 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 45 Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function LVI 15 1-3 P:$1E Low-Voltage Detector (Power Sense) PLL 16 1-3 P:$20 Phase-Locked Loop FM 17 0-2 P:$22 FM Access Error Interrupt FM 18 0-2 P:$24 FM Command Complete FM 19 0-2 P:$26 FM Command, Data, and Address Buffers Empty MSCAN 20 0-2 P:$28 MSCAN Error MSCAN 21 0-2 P:$2a MSCAN Receive MSCAN 22 0-2 P:$2C MSCAN Transmit MSCAN 23 0-2 P:$2E MSCAN Wake-Up GPIOD 24 0-2 P:$30 GPIOD GPIOC 25 0-2 P:$32 GPIOC GPIOB 26 0-2 P:$34 GPIOB GPIOA 27 0-2 P:$36 GPIOA QSPI0 28 0-2 P:$38 QSPI0 Receiver Full QSPI0 29 0-2 P:$3A QSPI0 Transmitter Empty QSPI1 30 0-2 P:$3C QSPI1 Receiver Full QSPI1 31 0-2 P:$3E QSPI1 Transmitter Empty QSCI0 32 0-2 P:$40 QSCI0 Transmitter Empty QSCI0 33 0-2 P:$42 QSCI0 Transmitter Idle QSCI0 34 0-2 P:$44 QSCI0 Receiver Error QSCI0 35 0-2 P:$46 QSCI0 Receiver Full QSCI1 36 0-2 P:$48 QSCI1 Transmitter Empty QSCI1 37 0-2 P:$4A QSCI1 Transmitter Idle QSCI1 38 0-2 P:$4C QSCI1 Receiver Error QSCI1 39 0-2 P:$4E QSCI1 Receiver Full I2C 40 0-2 P:$50 I2C Error I2C 41 0-2 P:$52 I2C General I2C 42 0-2 P:$54 I2C Receive I2C 43 0-2 P:$56 I2C Transmit I2C 44 0-2 P:$58 I2C Status TMRA 45 0-2 P:$5A Timer A, Channel 0 TMRA 46 0-2 P:$5C Timer A, Channel 1 TMRA 47 0-2 P:$5E Timer A, Channel 2 TMRA 48 0-2 P:$60 Timer A, Channel 3 TMRB 49 0-2 P:$62 Timer B, Channel 0 TMRB 50 0-2 P:$64 Timer B, Channel 1 TMRB 51 0-2 P:$66 Timer B, Channel 2 TMRB 52 0-2 P:$68 Timer B, Channel 3 56F8037/56F8027 Data Sheet, Rev. 8 46 Freescale Semiconductor Program Map Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function CMPA 53 0-2 P:$6A Comparator A CMPB 54 0-2 P:$6C Comparator B PIT0 55 0-2 P:$6E Interval Timer 0 PIT1 56 0-2 P:$70 Interval Timer 1 PIT2 57 0-2 P:$72 Interval Timer 2 ADC 58 0-2 P:$74 ADC A Conversion Complete ADC 59 0-2 P:$76 ADC B Conversion Complete ADC 60 0-2 P:$78 ADC Zero Crossing or Limit Error PWM 61 0-2 P:$7A Reload PWM PWM 62 0-2 P:$7C PWM Fault SWILP 63 -1 P:$7E SW Interrupt Low Priority 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses since the reset address would match the base of this vector table. 4.3 Program Map The Program Memory map is shown in Table 4-3 and Table 4-4. Table 4-3 Program Memory Map1 at Reset for 56F8037 Begin/End Address Memory Allocation P: $1F FFFF P: $00 9000 RESERVED P: $00 8FFF P: $00 8000 On-Chip RAM2 8KB P: $00 7FFF P: $00 0000 Internal Program Flash 64KB Cop Reset Address = $00 0002 Boot Location = $00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 47 Table 4-4 Program Memory Map1 at Reset for 56F8027 Begin/End Address Memory Allocation P: $1F FFFF P: $00 8800 RESERVED P: $00 87FF P: $00 8000 On-Chip RAM2 4KB P: $00 7FFF P: $00 4000 Internal Program Flash 32KB Cop Reset Address = $00 4002 Boot Location = $00 4000 P: $00 3FFF P: $00 0000 RESERVED 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-2. 4.4 Data Map Table 4-5 Data Memory Map for 56F80371 Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 9000 RESERVED X:$00 8FFF X:$00 8000 RESERVED X:$00 7FFF X:$00 1000 RESERVED X:$00 0FFF X:$00 0000 On-Chip Data RAM 8KB2 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-1. 56F8037/56F8027 Data Sheet, Rev. 8 48 Freescale Semiconductor Data Map Program Data EOnCE Reserved Reserved RAM Peripherals Dual Port RAM Reserved Flash RAM Figure 4-1 Dual Port RAM for 56F8037 Table 4-6 Data Memory Map for 56F80271 Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 9000 RESERVED X:$00 8FFF X:$00 8000 RESERVED X:$00 7FFF X:$00 0800 RESERVED X:$00 07FF X:$00 0000 On-Chip Data RAM 4KB2 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Program space starting at P: $00 8000; see Figure 4-2. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 49 Program Data EOnCE Reserved Reserved RAM Peripherals Flash Dual Port RAM Reserved Reserved RAM Figure 4-2 Dual Port RAM for 56F8027 4.5 EOnCE Memory Map Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE. Table 4-7 EOnCE Memory Map Address Register Acronym Register Name X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word Receive Register Upper Word X:$FF FFFE OTX / ORX (32 bits) Transmit Register Receive Register X:$FF FFFD OTXRXSR Transmit and Receive Status and Control Register X:$FF FFFC OCLSR Core Lock / Unlock Status Register X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 Reserved OCR Control Register X:$FF FF9F Instruction Step Counter X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter X:$FF FF9D OSR Status Register X:$FF FF9C OBASE Peripheral Base Address Register X:$FF FF9B OTBCR Trace Buffer Control Register X:$FF FF9A OTBPR Trace Buffer Pointer Register X:$FF FF99 Trace Buffer Register Stages X:$FF FF98 OTB (21 - 24 bits/stage) Trace Buffer Register Stages X:$FF FF97 X:$FF FF96 Breakpoint Unit Control Register OBCR (24 bits) X:$FF FF95 X:$FF FF94 X:$FF FF93 Breakpoint Unit Control Register Breakpoint Unit Address Register 1 OBAR1 (24 bits) Breakpoint Unit Address Register 1 Breakpoint Unit Address Register 2 56F8037/56F8027 Data Sheet, Rev. 8 50 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-7 EOnCE Memory Map (Continued) Address X:$FF FF92 Register Acronym OBAR2 (32 bits) Register Name Breakpoint Unit Address Register 2 X:$FF FF91 Breakpoint Unit Mask Register 2 X:$FF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2 X:$FF FF8F Reserved X:$FF FF8E OBCNTR EOnCE Breakpoint Unit Counter X:$FF FF8D Reserved X:$FF FF8C Reserved X:$FF FF8B Reserved X:$FF FF8A OESCR External Signal Control Register X:$FF FF89 - X:$FF FF00 Reserved 4.6 Peripheral Memory-Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read or written using word accesses only. Table 4-8 summarizes base addresses for the set of peripherals on the 56F8037/56F8027 device. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Table 4-8 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number Timer A TMRA X:$00 F000 4-9 Timer B TMRB X:$00 F040 4-10 ADC ADC X:$00 F080 4-11 PWM PWM X:$00 F0C0 4-12 ITCN ITCN X:$00 F0E0 4-13 SIM SIM X:$00 F100 4-14 COP COP X:$00 F120 4-15 CLK, PLL, OSC OCCS X:$00 F130 4-16 Power Supervisor PS X:$00 F140 4-17 GPIO Port A GPIOA X:$00 F150 4-18 GPIO Port B GPIOB X:$00 F160 4-19 GPIO Port C GPIOC X:$00 F170 4-20 GPIO Port D GPIOD X:$00 F180 4-21 PIT 0 PIT0 X:$00 F190 4-22 PIT 1 PIT1 X:$00 F1A0 4-23 PIT 2 PIT2 X:$00 F1B0 4-24 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 51 Table 4-8 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number DAC 0 DAC0 X:$00 F1C0 4-25 DAC 1 DAC1 X:$00 F1D0 4-26 Comparator A CMPA X:$00 F1E0 4-27 Comparator B CMPB X:$00 F1F0 4-28 QSCI 0 QSCI0 X:$00 F200 4-29 QSCI 1 QSCI1 X:$00 F210 4-30 QSPI 0 QSPI0 X:$00 F220 4-31 QSPI 1 QSPI1 X:$00 F230 4-32 I2C X:$00 F280 4-33 2 I C FM FM X:$00 F400 4-34 MSCAN CAN X:$00 F800 4-35 56F8037/56F8027 Data Sheet, Rev. 8 52 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-9 Quad Timer A Registers Address Map (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA0_COMP1 $0 Compare Register 1 TMRA0_COMP2 $1 Compare Register 2 TMRA0_CAPT $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCTRL $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_CSCTRL $A Comparator Status and Control Register TMRA0_FILT $B Input Filter Register Reserved TMRA0_ENBL $F Timer Channel Enable Register TMRA1_COMP1 $10 Compare Register 1 TMRA1_COMP2 $11 Compare Register 2 TMRA1_CAPT $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTRL $16 Control Register TMRA1_SCTRL $17 Status and Control Register TMRA1_CMPLD1 $18 Comparator Load Register 1 TMRA1_CMPLD2 $19 Comparator Load Register 2 TMRA1_CSCTRL $1A Comparator Status and Control Register TMRA1_FILT $1B Input Filter Register Reserved TMRA2_COMP1 $20 Compare Register 1 TMRA2_COMP2 $21 Compare Register 2 TMRA2_CAPT $22 Capture Register TMRA2_LOAD $23 Load Register TMRA2_HOLD $24 Hold Register TMRA2_CNTR $25 Counter Register TMRA2_CTRL $26 Control Register TMRA2_SCTRL $27 Status and Control Register TMRA2_CMPLD1 $28 Comparator Load Register 1 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 53 Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_CSCTRL $2A Comparator Status and Control Register TMRA2_FILT $2B Input Filter Register Reserved TMRA3_COMP1 $30 Compare Register 1 TMRA3_COMP2 $31 Compare Register 2 TMRA3_CAPT $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCTRL $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_CSCTRL $3A Comparator Status and Control Register TMRA3_FILT $3B Input Filter Register Reserved Table 4-10 Quad Timer B Registers Address Map (TMRB_BASE = $00 F040) Register Acronym Address Offset Register Description TMRB0_COMP1 $0 Compare Register 1 TMRB0_COMP2 $1 Compare Register 2 TMRB0_CAPT $2 Capture Register TMRB0_LOAD $3 Load Register TMRB0_HOLD $4 Hold Register TMRB0_CNTR $5 Counter Register TMRB0_CTRL $6 Control Register TMRB0_SCTRL $7 Status and Control Register TMRB0_CMPLD1 $8 Comparator Load Register 1 TMRB0_CMPLD2 $9 Comparator Load Register 2 TMRB0_CSCTRL $A Comparator Status and Control Register TMRB0_FILT $B Input Filter Register Reserved TMRB0_ENBL $F Timer Channel Enable Register TMRB1_COMP1 $10 Compare Register 1 TMRB1_COMP2 $11 Compare Register 2 TMRB1_CAPT $12 Capture Register 56F8037/56F8027 Data Sheet, Rev. 8 54 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-10 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F040) Register Acronym Address Offset Register Description TMRB1_LOAD $13 Load Register TMRB1_HOLD $14 Hold Register TMRB1_CNTR $15 Counter Register TMRB1_CTRL $16 Control Register TMRB1_SCTRL $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_CSCTRL $1A Comparator Status and Control Register TMRB1_FILT $1B Input Filter Register Reserved TMRB2_COMP1 $20 Compare Register 1 TMRB2_COMP2 $21 Compare Register 2 TMRB2_CAPT $22 Capture Register TMRB2_LOAD $23 Load Register TMRB2_HOLD $24 Hold Register TMRB2_CNTR $25 Counter Register TMRB2_CTRL $26 Control Register TMRB2_SCTRL $27 Status and Control Register TMRB2_CMPLD1 $28 Comparator Load Register 1 TMRB2_CMPLD2 $29 Comparator Load Register 2 TMRB2_CSCTRL $2A Comparator Status and Control Register TMRB2_FILT $2B Input Filter Register Reserved TMRB3_COMP1 $30 Compare Register 1 TMRB3_COMP2 $31 Compare Register 2 TMRB3_CAPT $32 Capture Register TMRB3_LOAD $33 Load Register TMRB3_HOLD $34 Hold Register TMRB3_CNTR $35 Counter Register TMRB3_CTRL $36 Control Register TMRB3_SCTRL $37 Status and Control Register TMRB3_CMPLD1 $38 Comparator Load Register 1 TMRB3_CMPLD2 $39 Comparator Load Register 2 TMRB3_CSCTRL $3A Comparator Status and Control Register TMRB3_FILT $3B Input Filter Register Reserved 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 55 Table 4-11 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_CTRL1 $0 Control Register 1 ADC_CTRL2 $1 Control Register 2 ADC_ZXCTRL $2 Zero Crossing Control Register ADC_CLIST 1 $3 Channel List Register 1 ADC_CLIST 2 $4 Channel List Register 2 ADC_CLIST 3 $5 Channel List Register 3 ADC_CLIST 4 $6 Channel List Register 4 ADC_SDIS $7 Sample Disable Register ADC_STAT $8 Status Register ADC_RDY $9 Conversion Ready Register ADC_LIMSTAT $A Limit Status Register ADC_ZXSTAT $B Zero Crossing Status Register ADC_RSLT0 $C Result Register 0 ADC_RSLT1 $D Result Register 1 ADC_RSLT2 $E Result Register 2 ADC_RSLT3 $F Result Register 3 ADC_RSLT4 $10 Result Register 4 ADC_RSLT5 $11 Result Register 5 ADC_RSLT6 $12 Result Register 6 ADC_RSLT7 $13 Result Register 7 ADC_RSLT8 $14 Result Register 8 ADC_RSLT9 $15 Result Register 9 ADC_RSLT10 $16 Result Register 10 ADC_RSLT11 $17 Result Register 11 ADC_RSLT12 $18 Result Register 12 ADC_RSLT13 $19 Result Register 13 ADC_RSLT14 $1A Result Register 14 ADC_RSLT15 $1B Result Register 15 ADC_LOLIM0 $1C Low Limit Register 0 ADC_LOLIM1 $1D Low Limit Register 1 ADC_LOLIM2 $1E Low Limit Register 2 ADC_LOLIM3 $1F Low Limit Register 3 ADC_LOLIM4 $20 Low Limit Register 4 ADC_LOLIM5 $21 Low Limit Register 5 ADC_LOLIM6 $22 Low Limit Register 6 ADC_LOLIM7 $23 Low Limit Register 7 56F8037/56F8027 Data Sheet, Rev. 8 56 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-11 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_HILIM0 $24 High Limit Register 0 ADC_HILIM1 $25 High Limit Register 1 ADC_HILIM2 $26 High Limit Register 2 ADC_HILIM3 $27 High Limit Register 3 ADC_HILIM4 $28 High Limit Register 4 ADC_HILIM5 $29 High Limit Register 5 ADC_HILIM6 $2A High Limit Register 6 ADC_HILIM7 $2B High Limit Register 7 ADC_OFFST0 $2C Offset Register 0 ADC_OFFST1 $2D Offset Register 1 ADC_OFFST2 $2E Offset Register 2 ADC_OFFST3 $2F Offset Register 3 ADC_OFFST4 $30 Offset Register 4 ADC_OFFST5 $31 Offset Register 5 ADC_OFFST6 $32 Offset Register 6 ADC_OFFST7 $33 Offset Register 7 ADC_PWR $34 Power Control Register ADC_CAL $35 Calibration Register Reserved Table 4-12 Pulse Width Modulator Registers Address Map (PWM_BASE = $00 F0C0) Register Acronym PWM_CTRL Address Offset Register Description $0 Control Register PWM_FCTRL $1 Fault Control Register PWM_FLTACK $2 Fault Status Acknowledge Register PWM_OUT $3 Output Control Register PWM_CNTR $4 Counter Register PWM_CMOD $5 Counter Modulo Register PWM_VAL0 $6 Value Register 0 PWM_VAL1 $7 Value Register 1 PWM_VAL2 $8 Value Register 2 PWM_VAL3 $9 Value Register 3 PWM_VAL4 $A Value Register 4 PWM_VAL5 $B Value Register 5 PWM_DTIM0 $C Dead Time Register 0 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 57 Table 4-12 Pulse Width Modulator Registers Address Map (Continued) (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description PWM_DTIM1 $D Dead Time Register 1 PWM_DMAP1 $E Disable Mapping Register 1 PWM_DMAP2 $F Disable Mapping Register 2 PWM_CNFG $10 Configure Register PWM_CCTRL $11 Channel Control Register PWM_PORT $12 Port Register PWM_ICCTRL $13 Internal Correction Control Register PWM_SCTRL $14 Source Control Register PWM_SYNC $15 Synchronization Window Register PWM_FFILT0 $16 Fault0 Filter Register PWM_FFILT1 $17 Fault1 Filter Register PWM_FFILT2 $18 Fault2 Filter Register PWM_FFILT3 $19 Fault3 Filter Register Table 4-13 Interrupt Control Registers Address Map (ITCN_BASE = $00 F0E0) Register Acronym Address Offset Register Description ITCN_IPR0 $0 Interrupt Priority Register 0 ITCN_IPR1 $1 Interrupt Priority Register 1 ITCN_IPR2 $2 Interrupt Priority Register 2 ITCN_IPR3 $3 Interrupt Priority Register 3 ITCN_IPR4 $4 Interrupt Priority Register 4 ITCN_IPR5 $5 Interrupt Priority Register 5 ITCN_IPR6 $6 Interrupt Priority Register 6 ITCN_VBA $7 Vector Base Address Register ITCN_FIM0 $8 Fast Interrupt Match 0 Register ITCN_FIVAL0 $9 Fast Interrupt Vector Address Low 0 Register ITCN_FIVAH0 $A Fast Interrupt Vector Address High 0 Register ITCN_FIM1 $B Fast Interrupt Match 1 Register ITCN_FIVAL1 $C Fast Interrupt Vector Address Low 1 Register ITCN_FIVAH1 $D Fast Interrupt Vector Address High 1 Register ITCN_IRQP0 $E IRQ Pending Register 0 ITCN_IRQP1 $F IRQ Pending Register 1 ITCN_IRQP2 $10 IRQ Pending Register 2 56F8037/56F8027 Data Sheet, Rev. 8 58 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-13 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F0E0) Register Acronym ITCN_IRQP3 Address Offset $11 Register Description IRQ Pending Register 3 Reserved ITCN_ICTRL $16 Interrupt Control Register Reserved Table 4-14 SIM Registers Address Map (SIM_BASE = $00 F100) Register Acronym Address Offset Register Description SIM_CTRL $0 Control Register SIM_RSTAT $1 Reset Status Register SIM_SWC0 $2 Software Control Register 0 SIM_SWC1 $3 Software Control Register 1 SIM_SWC2 $4 Software Control Register 2 SIM_SWC3 $5 Software Control Register 3 SIM_MSHID $6 Most Significant Half JTAG ID SIM_LSHID $7 Least Significant Half JTAG ID SIM_PWR $8 Power Control Register Reserved SIM_CLKOUT $A Clock Out Select Register SIM_PCR $B Peripheral Clock Rate Register SIM_PCE0 $C Peripheral Clock Enable Register 0 SIM_PCE1 $D Peripheral Clock Enable Register 1 SIM_SD0 $E Peripheral STOP Disable Register 0 SIM_SD1 $F Peripheral STOP Disable Register 1 SIM_IOSAHI $10 I/O Short Address Location High Register SIM_IOSALO $11 I/O Short Address Location Low Register SIM_PROT $12 Protection Register SIM_GPSA0 $13 GPIO Peripheral Select Register 0 for GPIOA SIM_GPSA1 $14 GPIO Peripheral Select Register 1 for GPIOA SIM_GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB SIM_GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB SIM_GPSCD $17 GPIO Peripheral Select Register for GPIOC and GPIOD SIM_IPS0 $18 Internal Peripheral Source Select Register 0 for PWM SIM_IPS1 $19 Internal Peripheral Source Select Register 1 for DACs SIM_IPS2 $1A Internal Peripheral Source Select Register 2 for TMRA Reserved 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 59 Table 4-15 Computer Operating Properly Registers Address Map (COP_BASE = $00 F120) Register Acronym Address Offset Register Description COP_CTRL $0 Control Register COP_TOUT $1 Time-Out Register COP_CNTR $2 Counter Register Table 4-16 Clock Generation Module Registers Address Map (OCCS_BASE = $00 F130) Register Acronym Address Offset Register Description OCCS_CTRL $0 Control Register OCCS_DIVBY $1 Divide-By Register OCCS_STAT $2 Status Register OCCS_OCTRL $5 Oscillator Control Register OCCS_CLKCHK $6 Clock Check Register OCCS_PROT $7 Protection Register Reserved Table 4-17 Power Supervisor Registers Address Map (PS_BASE = $00 F140) Register Acronym Address Offset Register Description PS_CTRL $0 Control Register PS_STAT $1 Status Register Reserved Table 4-18 GPIOA Registers Address Map (GPIOA_BASE = $00 F150) Register Acronym GPIOA_PUPEN Address Offset $0 Register Description Pull-up Enable Register GPIOA_DATA $1 Data Register GPIOA_DDIR $2 Data Direction Register GPIOA_PEREN $3 Peripheral Enable Register GPIOA_IASSRT $4 Interrupt Assert Register GPIOA_IEN $5 Interrupt Enable Register GPIOA_IPOL $6 Interrupt Polarity Register 56F8037/56F8027 Data Sheet, Rev. 8 60 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-18 GPIOA Registers Address Map (Continued) (GPIOA_BASE = $00 F150) Register Acronym GPIOA_IPEND Address Offset $7 Register Description Interrupt Pending Register GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register GPIOA_PPOUTM $9 Push-Pull Output Mode Control Register GPIOA_RDATA $A Raw Data Input Register GPIOA_DRIVE $B Output Drive Strength Control Register Table 4-19 GPIOB Registers Address Map (GPIOB_BASE = $00 F160) Register Acronym Address Offset Register Description GPIOB_PUPEN $0 Pull-up Enable Register GPIOB_DATA $1 Data Register GPIOB_DDIR $2 Data Direction Register GPIOB_PEREN $3 Peripheral Enable Register GPIOB_IASSRT $4 Interrupt Assert Register GPIOB_IEN $5 Interrupt Enable Register GPIOB_IPOL $6 Interrupt Polarity Register GPIOB_IPEND $7 Interrupt Pending Register GPIOB_IEDGE $8 Interrupt Edge-Sensitive Register GPIOB_PPOUTM $9 Push-Pull Output Mode Control Register GPIOB_RDATA $A Raw Data Input Register GPIOB_DRIVE $B Output Drive Strength Control Register Table 4-20 GPIOC Registers Address Map (GPIOC_BASE = $00 F170) Register Acronym Address Offset Register Description GPIOC_PUPEN $0 Pull-up Enable Register GPIOC_DATA $1 Data Register GPIOC_DDIR $2 Data Direction Register GPIOC_PEREN $3 Peripheral Enable Register GPIOC_IASSRT $4 Interrupt Assert Register GPIOC_IEN $5 Interrupt Enable Register GPIOC_IPOL $6 Interrupt Polarity Register GPIOC_IPEND $7 Interrupt Pending Register GPIOC_IEDGE $8 Interrupt Edge-Sensitive Register GPIOC_PPOUTM $9 Push-Pull Output Mode Control Register GPIOC_RDATA $A Raw Data Input Register GPIOC_DRIVE $B Output Drive Strength Control Register 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 61 Table 4-21 GPIOD Registers Address Map (GPIOD_BASE = $00 F180) Register Acronym Address Offset Register Description GPIOD_PUPEN $0 Pull-up Enable Register GPIOD_DATA $1 Data Register GPIOD_DDIR $2 Data Direction Register GPIOD_PEREN $3 Peripheral Enable Register GPIOD_IASSRT $4 Interrupt Assert Register GPIOD_IEN $5 Interrupt Enable Register GPIOD_IPOL $6 Interrupt Polarity Register GPIOD_IPEND $7 Interrupt Pending Register GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register GPIOD_PPOUTM $9 Push-Pull Output Mode Control Register GPIOD_RDATA $A Raw Data Input Register GPIOD_DRIVE $B Output Drive Strength Control Register Table 4-22 Programmable Interval Timer 0 Registers Address Map (PIT0_BASE = $00 F190) Register Acronym Address Offset Register Description PIT0_CTRL $0 Control Register PIT0_MOD $1 Modulo Register PIT0_CNTR $2 Counter Register Table 4-23 Programmable Interval Timer 1 Registers Address Map (PIT1_BASE = $00 F1A0) Register Acronym Address Offset Register Description PIT1_CTRL $0 Control Register PIT1_MOD $1 Modulo Register PIT1_CNTR $2 Counter Register Table 4-24 Programmable Interval Timer 2 Registers Address Map (PIT2_BASE = $00 F1B0) Register Acronym Address Offset Register Description PIT2_CTRL $0 Control Register PIT2_MOD $1 Modulo Register 56F8037/56F8027 Data Sheet, Rev. 8 62 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-24 Programmable Interval Timer 2 Registers Address Map (Continued) (PIT2_BASE = $00 F1B0) Register Acronym PIT2_CNTR Address Offset $2 Register Description Counter Register Table 4-25 Digital-to-Analog Converter 0 Registers Address Map (DAC0_BASE = $00 F1C0) Register Acronym Address Offset Register Description DAC0_CTRL $0 Control Register DAC0_DATA $1 Data Register DAC0_STEP $2 Step Register DAC0_MINVAL $3 Minimum Value Register DAC0_MAXVAL $4 Maximum Value Register Table 4-26 Digital-to-Analog Converter 0 Registers Address Map (DAC1_BASE = $00 F1D0) Register Acronym Address Offset Register Description DAC1_CTRL $0 Control Register DAC1_DATA $1 Data Register DAC1_STEP $2 Step Register DAC1_MINVAL $3 Minimum Value Register DAC1_MAXVAL $4 Maximum Value Register Table 4-27 Comparator A Registers Address Map (CMPA_BASE = $00 F1E0) Register Acronym Address Offset Register Description CMPA_CTRL $0 Control Register CMPA_STAT $1 Status Register CMPA_FILT $2 Filter Register Table 4-28 Comparator B Registers Address Map (CMPB_BASE = $00 F1F0) Register Acronym Address Offset Register Description CMPB_CTRL $0 Control Register CMPB_STAT $1 Status Register CMPB_FILT $2 Filter Register 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 63 Table 4-29 Queued Serial Communication Interface 0 Registers Address Map (QSCI0_BASE = $00 F200) Register Acronym Address Offset Register Description QSCI0_RATE $0 Baud Rate Register QSCI0_CTRL1 $1 Control Register 1 QSCI0_CTRL2 $2 Control Register 2 QSCI0_STAT $3 Status Register QSCI0_DATA $4 Data Register Table 4-30 Queued Serial Communication Interface 1 Registers Address Map (QSCI1_BASE = $00 F210) Register Acronym Address Offset Register Description QSCI1_RATE $0 Baud Rate Register QSCI1_CTRL1 $1 Control Register 1 QSCI1_CTRL2 $2 Control Register 2 QSCI1_STAT $3 Status Register QSCI1_DATA $4 Data Register Table 4-31 Queued Serial Peripheral Interface 0 Registers Address Map (QSPI0_BASE = $00 F220) Register Acronym Address Offset Register Description QSPI0_SCTRL $0 Status and Control Register QSPI0_DSCTRL $1 Data Size and Control Register QSPI0_DRCV $2 Data Receive Register QSPI0_DXMIT $3 Data Transmit Register QSPI0_FIFO $4 FIFO Control Register QSPI0_DELAY $5 Delay Register Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map (QSPI1_BASE = $00 F230) Register Acronym Address Offset Register Description QSPI1_SCTRL $0 Status and Control Register QSPI1_DSCTRL $1 Data Size and Control Register QSPI1_DRCV $2 Data Receive Register QSPI1_DXMIT $3 Data Transmit Register QSPI1_FIFO $4 FIFO Control Register 56F8037/56F8027 Data Sheet, Rev. 8 64 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map (QSPI1_BASE = $00 F230) Register Acronym QSPI1_DELAY Address Offset Register Description $5 Delay Register Table 4-33 I2C Registers Address Map (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description I2C_CTRL $0 Control Register I2C_TAR $2 Target Address Register I2C_SAR $4 Slave Address Register I2C_DATA $8 RX/TX Data Buffer and Command Register I2C_SSHCNT $A Standard Speed Clock SCL High Count Register I2C_SSLCNT $C Standard Speed Clock SCL Low Count Register I2C_FSHCNT $E Fast Speed Clock SCL High Count Register I2C_FSLCNT $10 Fast Speed Clock SCL Low Count Register I2C_ISTAT $16 Interrupt Status Register I2C_IMASK $18 Interrupt Mask Register I2C_RISTAT $1A Raw Interrupt Status Register I2C_RXFT $1C Receive FIFO Threshold Register I2C_TXFT $1E Transmit FIFO Threshold Register I2C_CLRINT $20 Clear Combined and Individual Interrupts Register I2C_CLRRXUND $22 Clear RX_UNDER Interrupt Register I2C_CLRRXOVR $24 Clear RX_OVER Interrupt Register I2C_CLRTXOVR $26 Clear TX_OVER Interrupt Register I2C_CLRRDREQ $28 Clear RD_REQ Interrupt Register I2C_CLRTXABRT $2A Clear TX_ABRT Interrupt Register I2C_CLRRXDONE $2C Clear RX_DONE Interrupt Register I2C_CLRACT $2E Clear Activity Interrupt Register I2C_CLRSTPDET $30 Clear STOP_DET Interrupt Register I2C_CLRSTDET $32 Clear START_DET Interrupt Register I2C_CLRGC $34 Clear GEN_CALL Interrupt Register I2C_ENBL $36 Enable Register I2C_STAT $38 Status Register I2C_TXFLR $3A Transmit FIFO Level Register I2C_RXFLR $3C Receive FIFO Level Register I2C_TXABRTSRC $40 Transmit Abort Status Register 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 65 Table 4-34 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FM_CLKDIV $0 Clock Divider Register FM_CNFG $1 Configuration Register $2 Reserved FM_SECHI $3 Security High Half Register FM_SECLO $4 Security Low Half Register $5 - $9 FM_PROT $10 Reserved Protection Register $11 - $12 Reserved FM_USTAT $13 User Status Register FM_CMD $14 Command Register $15 - $17 FM_DATA $18 Data Buffer Register $19 - $A FM_OPT1 FM_TSTSIG Reserved Reserved $1B Information Option Register 1 $1C Reserved $1D Test Array Signature Register Table 4-35 MSCAN Registers Address Map (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_CTRL0 $00 Control Register 0 MSCAN_CTRL1 $01 Control Register 1 MSCAN_BTR0 $02 Bus Timing Register 0 MSCAN_BTR1 $03 Bus Timing Register 1 MSCAN_RFLG $04 Receiver Flag Register MSCAN_RIER $05 Receiver Interrupt Enable Register MSCAN_TFLG $06 Transmitter Flag Register MSCAN_TIER $07 Transmitter Interrupt Enable Register MSCAN_TARQ $08 Transmitter Message Abort Request Register MSCAN_TAAK $09 Transmitter Message Abort Acknowledge Register MSCAN_TBSEL $0A Transmitter Buffer Selection Register MSCAN_IDAC $0B Identifier Acceptance Control Register Reserved MSCAN_MISC $0D Miscellaneous Register MSCAN_RXERR $0E Receive Error Register MSCAN_TXERR $0F Transmit Error Register 56F8037/56F8027 Data Sheet, Rev. 8 66 Freescale Semiconductor Peripheral Memory-Mapped Registers Table 4-35 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_IDAR0 $10 Identifier Acceptance Register 0 MSCAN_IDAR1 $11 Identifier Acceptance Register 1 MSCAN_IDAR2 $12 Identifier Acceptance Register 2 MSCAN_IDAR3 $13 Identifier Acceptance Register 3 MSCAN_IDMR0 $14 Identifier Mask Register 0 MSCAN_IDMR1 $15 Identifier Mask Register 1 MSCAN_IDMR2 $16 Identifier Mask Register 2 MSCAN_IDMR3 $17 Identifier Mask Register 3 MSCAN_IDAR4 $18 Identifier Acceptance Register 4 MSCAN_IDAR5 $19 Identifier Acceptance Register 5 MSCAN_IDAR6 $1A Identifier Acceptance Register 6 MSCAN_IDAR7 $1B Identifier Acceptance Register 7 MSCAN_IDMR4 $1C Identifier Mask Register 4 MSCAN_IDMR5 $1D Identifier Mask Register 5 MSCAN_IDMR6 $1E Identifier Mask Register 6 MSCAN_IDMR7 $1F Identifier Mask Register 7 MSCAN_RXFG0 $20 Foreground Receive Buffer 0 MSCAN_RXFG1 $21 Foreground Receive Buffer 1 MSCAN_RXFG2 $22 Foreground Receive Buffer 2 MSCAN_RXFG3 $23 Foreground Receive Buffer 3 MSCAN_RXFG4 $24 Foreground Receive Buffer 4 MSCAN_RXFG5 $25 Foreground Receive Buffer 5 MSCAN_RXFG6 $26 Foreground Receive Buffer 6 MSCAN_RXFG7 $27 Foreground Receive Buffer 7 MSCAN_RXFG8 $28 Foreground Receive Buffer 8 MSCAN_RXFG9 $29 Foreground Receive Buffer 9 MSCAN_RXFG10 $2A Foreground Receive Buffer 10 MSCAN_RXFG11 $2B Foreground Receive Buffer 11 MSCAN_RXFG12 $2C Foreground Receive Buffer 12 MSCAN_RXFG13 $2D Foreground Receive Buffer 13 MSCAN_RXFG14 $2E Foreground Receive Buffer 14 MSCAN_RXFG15 $2F Foreground Receive Buffer 15 MSCAN_TXFG0 $30 Foreground Transmit Buffer 0 MSCAN_TXFG1 $31 Foreground Transmit Buffer 1 MSCAN_TXFG2 $32 Foreground Transmit Buffer 2 MSCAN_TXFG3 $33 Foreground Transmit Buffer 3 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 67 Table 4-35 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_TXFG4 $34 Foreground Transmit Buffer 4 MSCAN_TXFG5 $35 Foreground Transmit Buffer 5 MSCAN_TXFG6 $36 Foreground Transmit Buffer 6 MSCAN_TXFG7 $37 Foreground Transmit Buffer 7 MSCAN_TXFG8 $38 Foreground Transmit Buffer 8 MSCAN_TXFG9 $39 Foreground Transmit Buffer 9 MSCAN_TXFG10 $3A Foreground Transmit Buffer 10 MSCAN_TXFG11 $3B Foreground Transmit Buffer 11 MSCAN_TXFG12 $3C Foreground Transmit Buffer 12 MSCAN_TXFG13 $3D Foreground Transmit Buffer 13 MSCAN_TXFG14 $3E Foreground Transmit Buffer 14 MSCAN_TXFG15 $3F Foreground Transmit Buffer 15 Reserved Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.2 Features The ITCN module design includes these distinctive features: • • • • Programmable priority levels for each IRQ Two programmable Fast Interrupts Notification to SIM module to restart clocks out of Wait and Stop modes Ability to drive initial address on the address bus after reset For further information, see Table 4-2, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority and number 63 is the lowest. 56F8037/56F8027 Data Sheet, Rev. 8 68 Freescale Semiconductor Functional Description 5.3.1 Normal Interrupt Handling Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0 and I1 bits in its status register. Table 5-1 Interrupt Mask Bit Definition SR[9] (I1) SR[8] (I0) Exceptions Permitted Exceptions Masked 0 0 Priorities 0, 1, 2, 3 None 0 1 Priorities 1, 2, 3 Priority 0 1 0 Priorities 2, 3 Priorities 0, 1 1 1 Priority 3 Priorities 0, 1, 2 The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E core. Table 5-2 Interrupt Priority Encoding 5.3.3 IPIC_VALUE[1:0] Current Interrupt Priority Level Required Nested Exception Priority 00 No interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priority 2 or 3 Priority 3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes Fast Interrupts before the core does. A Fast Interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 69 3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts its Fast Interrupt handling. 5.4 Block Diagram Priority Level INT1 2 -> 4 Decode any0 Level 0 64 -> 6 Priority Encoder 6 INT VAB CONTROL any3 Level 3 Priority Level INT64 IPIC IACK SR[9:8] 64 -> 6 Priority Encoder 6 PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 56F8037/56F8027 Data Sheet, Rev. 8 70 Freescale Semiconductor Operating Modes 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F0E0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.3 IPR3 $3 Interrupt Priority Register 3 5.6.4 IPR4 $4 Interrupt Priority Register 4 5.6.5 IPR5 $5 Interrupt Priority Register 5 5.6.6 IPR6 $6 Interrupt Priority Register 6 5.6.7 VBA $7 Vector Base Address Register 5.6.8 FIM0 $8 Fast Interrupt Match 0 Register 5.6.9 FIVAL0 $9 Fast Interrupt 0 Vector Address Low Register 5.6.10 FIVAH0 $A Fast Interrupt 0 Vector Address High 0 Register 5.6.11 FIM1 $B Fast Interrupt Match 1 Register 5.6.12 FIVAL1 $C Fast Interrupt 1 Vector Address Low Register 5.6.13 FIVAH1 $D Fast Interrupt 1 Vector Address High Register 5.6.14 IRQP0 $E IRQ Pending Register 0 5.6.15 IRQP1 $F IRQ Pending Register 1 5.6.16 IRQP2 $10 IRQ Pending Register 2 5.6.17 IRQP3 $11 IRQ Pending Register 3 5.6.18 Reserved ICTRL $16 Interrupt Control Register 5.6.19 Reserved 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 71 Add. Offset Register Name $0 IPR0 $1 IPR1 $2 IPR2 $3 IPR3 $4 IPR4 $5 IPR5 $6 IPR6 $7 VBA $8 FIM0 $9 FIVAL0 $A FIVAH0 $B FIM1 $C FIVAL1 $D FIVAH1 $E IRQP0 $F IRQP1 $10 IRQP2 $11 IRQP3 15 R W R W R W R W R W R W R 14 13 12 PLL IPL LVI IPL GPIOD IPL MSCAN_WK UP IPL QSCI0_XMIT IPL 11 10 0 0 9 8 6 5 4 0 BKPT_U IPL STPCNT IPL MSCAN_TX IPL MSCAN_RX IPL MSCAN_ERR IPL FM_CBE IPL FM_CC IPL FM_ERR IPL QSPI1_XMIT IPL QSPI1_RCV IPL QSPI0_XMIT IPL QSPI0_RCV IPL GPIOA IPL GPIOB IPL GPIOC IPL I2C_ERR IPL QSCI1_RCV IPL QSCI1_RER R IPL QSCI1_TIDL IPL QSCI1_XMIT IPL QSCI0_RCV IPL QSCI0_RERR IPL QSCI0_TIDL IPL TMRA_3 IPL TMRA_2 IPL TMRA_1 IPL TMRA_0 IPL I2C_STAT IPL I2C_TX IPL I2C_RX IPL I2C_GEN IPL PIT1 IPL PIT0 IPL COMPB IPL COMPA IPL TMRB_3 IPL TMRB_2 IPL TMRB_1 IPL TMRB_0 IPL 0 0 0 PWM_F IPL PWM_RL IPL ADC_ZC IPL ADCB_CC IPL ADCA_CC IPL PIT2 IPL 0 0 0 0 0 VECTOR_BASE_ADDRESS 0 0 0 R 0 0 0 0 0 FAST INTERRUPT 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH W FAST INTERRUPT 1 W R FAST INTERRUPT 1 VECTOR ADDRESS LOW W R 1 TRBUF IPL W R 2 TX_REG IPL W R 3 RX_REG IPL W R 7 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH W R 1 PENDING[16:2] W R PENDING[32:17] W R PENDING[48:33] W R PENDING[63:49] W Reserved $16 ICTRL R INT IPIC VAB W INT_ DIS 1 1 1 0 0 Reserved = Reserved Figure 5-2 ITCN Register Map Summary 56F8037/56F8027 Data Sheet, Rev. 8 72 Freescale Semiconductor Register Descriptions 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 Read 15 14 13 PLL IPL Write RESET 0 0 12 11 10 0 0 0 0 LVI IPL 0 0 9 8 RX_REG IPL 0 0 7 6 TX_REG IPL 0 0 5 4 TRBUF IPL 0 0 3 2 BKPT_U IPL 0 0 1 0 STPCNT IPL 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)—Bits 15–14 This field is used to set the interrupt priority levels for the PLL Loss of Reference or Change in Lock Status IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.2 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 13–12 This field is used to set the interrupt priority levels for the Low Voltage Detector IRQ. This IRQ is limited to priorities 1 through 3 and is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.3 Reserved—Bits 11–10 This bit field is reserved. Each bit must be set to 0. 5.6.1.4 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)— Bits 9–8 This field is used to set the interrupt priority level for the EOnCE Receive Register Full IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 73 5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.6 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 5–4 This field is used to set the interrupt priority level for the EOnCE Trace Buffer IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.7 EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)— Bits 3–2 This field is used to set the interrupt priority level for the EOnCE Breakpoint Unit IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.8 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)— Bits 1–0 This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 56F8037/56F8027 Data Sheet, Rev. 8 74 Freescale Semiconductor Register Descriptions 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read 15 14 GPIOD IPL Write RESET 0 0 13 12 11 MSCAN_WK UP IPL 0 0 10 MSCAN_TX IPL 0 0 9 8 MSCAN_RX IPL 0 0 7 6 MSCAN_ERR IPL 0 0 5 4 FM_CBE IPL 0 0 3 2 FM_CC IPL 0 0 1 0 FM_ERR IPL 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.2 MSCAN Wake Up Interrupt Priority Level (MSCAN_WKUP IPL)—Bits 13–12 This field is used to set the interrupt priority level for the MSCAN Wake Up IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.3 MSCAN Transmit Interrupt Priority Level (MSCAN_TX IPL)—Bits 11–10 This field is used to set the interrupt priority level for the MSCAN Transmit IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.4 MSCAN Receive Interrupt Priority Level (MSCAN_RX IPL)—Bits 9–8 This field is used to set the interrupt priority level for MSCAN Receive IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 75 • 11 = IRQ is priority level 2 5.6.2.5 MSCAN Error Interrupt Priority Level (MSCAN_ERR IPL)—Bits 7–6 This field is used to set the interrupt priority level for the MSCAN Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.6 FM Command, Data, Address Buffers Empty Interrupt Priority Level (FM_CBE IPL)—Bits 5–4 This field is used to set the interrupt priority level for the FM Command, Data Address Buffers Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.7 FM Command Complete Interrupt Priority Level (FM_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for the FM Command Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.8 FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 1–0 This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8037/56F8027 Data Sheet, Rev. 8 76 Freescale Semiconductor Register Descriptions 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $2 Read 15 14 13 QSCI0_XMIT IPL Write RESET 0 0 12 11 QSPI1_XMIT IPL 0 0 10 QSPI1_RCV IPL 0 0 9 8 QSPI0_XMIT IPL 0 0 7 6 QSPI0_RCV IPL 0 0 5 4 GPIOA IPL 0 0 3 2 GPIOB IPL 0 0 1 0 GPIOC IPL 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.1 QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)— Bits 15–14 This field is used to set the interrupt priority level for the QSCI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.2 QSPI 1 Transmitter Empty Interrupt Priority Level (QSPI1_XMIT IPL)— Bits 13–12 This field is used to set the interrupt priority level for the QSPI1 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.3 QSPI 1 Receiver Full Interrupt Priority Level (QSPI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for the QSPI1 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.4 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)— Bits 9–8 This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 77 • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.5 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6 This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for the GPIOA IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.7 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for the GPIOB IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.8 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0 This field is used to set the interrupt priority level for the GPIOC IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8037/56F8027 Data Sheet, Rev. 8 78 Freescale Semiconductor Register Descriptions 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 Read 15 14 I2C_ERR IPL Write RESET 0 0 13 12 QSCI1_RCV IPL 0 0 11 10 QSCI1_RER R IPL 0 0 9 8 QSCI1_TIDL IPL 0 0 7 6 QSCI1_XMIT IPL 0 0 5 4 QSCI0_RCV IPL 0 0 3 2 QSCI0_RERR IPL 0 0 1 0 QSCI0_TIDL IPL 0 0 Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.1 I2C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14 This field is used to set the interrupt priority level for the I2C Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.2 QSCI 1 Receiver Full Interrupt Priority Level (QSCI1_RCV IPL)— Bits 13–12 This field is used to set the interrupt priority level for the QSCI1 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.3 QSCI 1 Receiver Error Interrupt Priority Level (QSCI1_RERR IPL)— Bits 11–10 This field is used to set the interrupt priority level for the QSCI1 Receiver Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.4 QSCI 1 Transmitter Idle Interrupt Priority Level (QSCI1_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for the QSCI1 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 79 • 11 = IRQ is priority level 2 5.6.4.5 QSCI 1 Transmitter Empty Interrupt Priority Level (QSCI1_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for the QSCI1 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.6 QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)—Bits 5–4 This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.7 QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)— Bits 3–2 This field is used to set the interrupt priority level for the QSCI0 Receiver Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.8 QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)— Bits 1–0 This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8037/56F8027 Data Sheet, Rev. 8 80 Freescale Semiconductor Register Descriptions 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 TMRA_3 IPL Write RESET 0 0 13 12 TMRA_2 IPL 0 0 11 10 TMRA_1 IPL 0 0 9 8 TMRA_0 IPL 0 0 7 6 I2C_STAT IPL 0 0 5 4 I2C_TX IPL 0 0 3 2 I2C_RX IPL 0 0 1 0 I2C_GEN IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.2 Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)— Bits 13–12 This field is used to set the interrupt priority level for the Timer A, Channel 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.3 Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)— Bits 11–10 This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 81 5.6.5.4 Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.5 I2C Status Interrupt Priority Level (I2C_STAT IPL)—Bits 7–6 This field is used to set the interrupt priority level for the I2C Status IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.6 I2C Transmit Interrupt Priority Level (I2C_TX IPL)—Bits 5–4 This field is used to set the interrupt priority level for the I2C Transmit IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.7 I2C Receive Interrupt Priority Level (I2C_RX IPL)— Bits 3–2 This field is used to set the interrupt priority level for the I2C Receiver IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.8 I2C General Call Interrupt Priority Level (I2C_GEN IPL)—Bits 1–0 This field is used to set the interrupt priority level for the I2C General Call IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 56F8037/56F8027 Data Sheet, Rev. 8 82 Freescale Semiconductor Register Descriptions • • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 Read Write RESET 15 14 13 12 PIT1 IPL PIT0 IPL 0 0 0 0 11 10 COMPB IPL 0 0 9 8 COMPA IPL 0 0 7 6 TMRB_3 IPL 0 0 5 4 TMRB_2 IPL 0 0 3 2 TMRB_1 IPL 0 0 1 0 TMRB_0 IPL 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR6) 5.6.6.1 Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Programmable Interval Timer 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.2 Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)— Bits 13–12 This field is used to set the interrupt priority level for the Programmable Interval Timer 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.3 Comparator B Interrupt Priority Level (COMPB IPL)— Bits 11–10 This field is used to set the interrupt priority level for the Comparator B IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 83 5.6.6.4 Comparator A Interrupt Priority Level (COMPA IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.5 Timer B, Channel 3 Interrupt Priority Level (TMRB_3 IPL)—Bits 7–6 This field is used to set the interrupt priority level for the Timer B, Channel 3 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.6 Timer B, Channel 2 Interrupt Priority Level (TMRB_2 IPL)—Bits 5–4 This field is used to set the interrupt priority level for the Timer B, Channel 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.7 Timer B, Channel 1 Interrupt Priority Level (TMRB_1 IPL)—Bits 3–2 This field is used to set the interrupt priority level for the Timer B, Channel 1 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.8 Timer B, Channel 0 Interrupt Priority Level (TMRB_0 IPL)—Bits 1–0 This field is used to set the interrupt priority level for the Timer B, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 56F8037/56F8027 Data Sheet, Rev. 8 84 Freescale Semiconductor Register Descriptions • 11 = IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 Read 0 0 0 0 0 0 0 0 Write RESET 11 10 PWM_F IPL 0 9 8 PWM_RL IPL 0 0 0 7 6 ADC_ZC IPL 0 0 5 4 ADCB_CC IPL 0 0 3 2 ADCA_CC IPL 0 0 1 0 PIT2 IPL 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Reserved—Bits 15–12 This bit field is reserved. Each bit must be set to 0. 5.6.7.2 PWM Fault Interrupt Priority Level (PWM_F IPL)—Bits 11–10 This field is used to set the interrupt priority level for the PWM Fault Interrupt IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.4 ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 85 5.6.7.5 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 5–4 This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.6 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for the ADC A Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.7 Programmable Interval Timer 2 Interrupt Priority Level (PIT2 IPL)—Bits 1–0 This field is used to set the interrupt priority level for the Programmable Interval Timer 2 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8 Vector Base Address Register (VBA) Base + $7 15 14 Read 0 0 0 0 13 12 11 10 9 7 6 5 4 3 2 1 0 0 0 0 0 0 VECTOR_BASE_ADDRESS Write RESET1 8 0 0 0 0 0 0 0 0 0 1. The 56F8037 resets to a value of 0x0000. This corresponds to reset addresses of 0x000000. The 56F8027 resets to a value of 0x0080. This corresponds to reset addresses of 0x004000. Figure 5-10 Vector Base Address Register (VBA) 5.6.8.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 86 Freescale Semiconductor Register Descriptions 5.6.8.2 Vector Address Bus (VAB) Bits 13–0 The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the Core. 5.6.9 Fast Interrupt Match 0 Register (FIM0) Base + $8 15 14 13 12 11 10 9 8 7 6 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 2 1 0 0 0 FAST INTERRUPT 0 Write RESET 3 0 0 0 0 Figure 5-11 Fast Interrupt Match 0 Register (FIM0) 5.6.9.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 5.6.9.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0 These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. 5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $9 15 14 13 12 11 Read 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 87 5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $A 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH Write RESET 3 0 0 0 0 0 Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.11.1 Reserved—Bits 15–5 This bit field is reserved. Each bit must be set to 0. 5.6.11.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 5.6.12 Fast Interrupt 1 Match Register (FIM1) Base + $B 15 14 13 12 11 10 9 8 7 6 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 2 1 0 0 0 FAST INTERRUPT 1 Write RESET 3 0 0 0 0 Figure 5-14 Fast Interrupt 1 Match Register (FIM1) 5.6.12.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 5.6.12.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0 These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to the vector table. 5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $C 15 14 13 12 11 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS LOW Write RESET 10 0 0 0 0 0 0 0 0 0 0 0 Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 56F8037/56F8027 Data Sheet, Rev. 8 88 Freescale Semiconductor Register Descriptions 5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1) Base + $D 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 Write RESET 3 2 1 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 0 0 0 0 0 Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.14.1 Reserved—Bits 15–5 This bit field is reserved. Each bit must be set to 0. 5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.15 IRQ Pending Register 0 (IRQP0) Base + $E 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 PENDING[16:2] 0 1 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-17 IRQ Pending Register 0 (IRQP0) 5.6.15.1 IRQ Pending (PENDING)—Bits 16–2 This register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending IRQ numbers correspond to ascending bit locations. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.15.2 Reserved—Bit 0 This bit field is reserved. It must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 89 5.6.16 IRQ Pending Register 1 (IRQP1) Base + $F 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING[32:17] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-18 IRQ Pending Register 1 (IRQP1) 5.6.16.1 IRQ Pending (PENDING)—Bits 32–17 This register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending IRQ numbers correspond to ascending bit locations. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.17 IRQ Pending Register 2 (IRQP2) Base + $10 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING[48:33] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-19 IRQ Pending Register 2 (IRQP2) 5.6.17.1 IRQ Pending (PENDING)—Bits 48–33 This register bit values represent the pending IRQs for interrupt vector numbers 33 through 48. Ascending IRQ numbers correspond to ascending bit locations. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.18 IRQ Pending Register 3 (IRQP3) Base + $11 15 Read 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 PENDING[63:49] Write RESET 1 1 1 1 1 1 1 1 1 1 Figure 5-20 IRQ Pending Register 3 (IRQP3) 5.6.18.1 IRQ Pending (PENDING)—Bits 63–49 This register bit values represent the pending IRQs for interrupt vector numbers 49 through 63. Ascending IRQ numbers correspond to ascending bit locations. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 56F8037/56F8027 Data Sheet, Rev. 8 90 Freescale Semiconductor Register Descriptions 5.6.18.2 Reserved—Bit 15 This bit field is reserved. When it is read, it has a value of 1. 5.6.19 Interrupt Control Register (ICTRL) $Base + $16 15 Read INT 14 13 12 11 10 IPIC 9 8 7 6 VAB Write RESET 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INT_ DIS 1 1 1 0 0 0 1 1 1 0 0 Figure 5-21 Interrupt Control Register (ICTRL) 5.6.19.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • • 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: • • • • Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 00 = Required nested exception priority levels are 0, 1, 2, or 3 01 = Required nested exception priority levels are 1, 2, or 3 10 = Required nested exception priority levels are 2 or 3 11 = Required nested exception priority level is 3 Table 5-4 Interrupt Priority Encoding 5.6.19.3 IPIC_VALUE[1:0] Current Interrupt Priority Level Required Nested Exception Priority 00 No interrupt or SWILP Priorities 0, 1, 2, 3 01 Priority 0 Priorities 1, 2, 3 10 Priority 1 Priorities 2, 3 11 Priority 2 or 3 Priority 3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken. In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 91 when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • • 0 = Normal operation (default) 1 = All interrupts disabled 5.6.19.5 Reserved—Bits 4-2 This bit field is reserved. Each bit must be set to 1. 5.6.19.6 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 5.7 Resets 5.7.1 General Table 5-5 Reset Summary Reset Priority Core Reset 5.7.2 5.7.2.1 Source Characteristics RST Core reset from the SIM Description of Reset Operation Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in Figure 5-22. RES CLK VAB RESET_VECTOR_ADR PAB READ_ADR Figure 5-22 Reset Interface 56F8037/56F8027 Data Sheet, Rev. 8 92 Freescale Semiconductor 5.7.3 Introduction ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: • • • • • • • • Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System Integration Module’s functions are discussed in more detail in the following sections. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 93 6.2 Features The SIM has the following features: • • • • • • • • • • • • • • • • • • • Chip reset sequencing Core and peripheral clock control and distribution Stop/Wait mode control System status control Registers containing the JTAG ID of the chip Controls for programmable peripheral and GPIO connections Peripheral clocks for TMR and PWM with a high-speed (3X) option Power-saving clock gating for peripherals Three power modes (Run, Wait, Stop) to control power utilization — Stop mode shuts down the 56800E core, system clock, and peripheral clock — Wait mode shuts down the 56800E core and unnecessary system clock operation — Run mode supports full device operation Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection capability Controls the enable/disable functions of Large Regulator Standby mode with write protection capability Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts Controls for programmable peripheral and GPIO connections Software chip reset I/O short address base location control Peripheral protection control to provide runaway code protection for safety-critical applications Controls output of internal clock sources to CLKO pin Four general-purpose software control registers are reset only at power-on Peripherals Stop mode clocking control 56F8037/56F8027 Data Sheet, Rev. 8 94 Freescale Semiconductor Register Descriptions 6.3 Register Descriptions A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Acronym Base Address + Register Name Section Location CTRL $0 Control Register 6.3.1 RSTAT $1 Reset Status Register 6.3.2 SWC0 $2 Software Control Register 0 6.3.3 SWC1 $3 Software Control Register 1 6.3.3 SWC2 $4 Software Control Register 2 6.3.3 SWC3 $5 Software Control Register 3 6.3.3 MSHID $6 Most Significant Half of JTAG ID 6.3.4 LSHID $7 Least Significant Half of JTAG ID 6.3.5 PWR $8 Power Control Register 6.3.6 Reserved CLKOUT $A CLKO Select Register 6.3.7 PCR $B Peripheral Clock Rate Register 6.3.8 PCE0 $C Peripheral Clock Enable Register 0 6.3.9 PCE1 $D Peripheral Clock Enable Register 0 6.3.10 SD0 $E Stop Disable Register 0 6.3.11 SD1 $F Stop Disable Register 1 6.3.12 IOSAHI $10 I/O Short Address Location High Register 6.3.13 IOSALO $11 I/O Short Address Location Low Register 6.3.14 PROT $12 Protection Register 6.3.15 GPSA0 $13 GPIO Peripheral Select Register 0 for GPIOA 6.3.16 GPSA1 $14 GPIO Peripheral Select Register 1 for GPIOA 6.3.17 GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB 6.3.18 GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB 6.3.19 GPSCD $17 GPIO Peripheral Select Register for GPIOC and GPIOD 6.3.20 IPS0 $18 Internal Peripheral Source Select Register 0 for PWM 6.3.21 IPS1 $19 Internal Peripheral Source Select Register 1 for DACs 6.3.22 IPS2 $1A Internal Peripheral Source Select Register 2 for Quad Timer A 6.3.23 Reserved 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 95 Add. Offset Address Acronym $0 SIM_ CTRL $1 SIM_ RSTAT $2 SIM_SWC0 $3 SIM_SWC1 $4 SIM_SWC2 $5 SIM_SWC3 $6 SIM_MSHID $7 SIM_LSHID $8 SIM_PWR R 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 ONCE EBL0 SW RST 0 0 0 0 0 0 0 0 0 SWR W R 3 2 1 STOP_ DISABLE COP_ COP_ EXTR TOR LOR 0 WAIT_ DISABLE POR 0 0 W R Software Control Data 0 W R Software Control Data 1 W R Software Control Data 2 W R Software Control Data 3 W R 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRB_ TMRA_ PWM_C CR CR R I2C_ CR 0 0 CMPB W R W R LRSTDBY W Reserved $A SIM_ CLKOUT $B SIM_PCR $C SIM_PCE0 $D SIM_PCE1 $E SIM_SD0 $F SIM_SD1 $10 SIM_IOSAHI $11 SIM_IOSALO $12 SIM_PROT $13 SIM_GPSA0 $14 SIM_GPSA1 $15 SIM_GPSB0 $16 SIM_GPSB1 $17 SIM_GPSCD $18 SIM_IPS0 $19 SIM_IPS1 R W R W R W R 0 W R W R DAC1 DAC0 PIT2 PIT1 PIT0 CMPB_ CMPA_ DAC1_S DAC0_ SD SD D SD 0 ADC 0 0 0 0 0 0 0 0 0 0 0 ADC_ SD 0 0 CLKOSEL 0 CLK DIS 0 I2C TB3 TB2 0 0 I2C_ SD 0 0 0 0 QSCI1 QSCI0 QSPI1 QSPI0 TB1 TB0 TA3 TA2 QSCI1 QSCI0 QSPI1 QSPI0 _SD _SD _SD _SD 0 PIT2_ SD PIT1_S D PIT0_ SD 0 0 0 0 TB3_ SD TB2_ SD TB1_ SD TB0_ SD TA3_ SD TA2_ SD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPS_ A11 0 GPS_ A10 W R CMPA PWM3 PWM2 PWM1 PWM0 0 0 0 0 0 0 0 GPS_ A6 0 0 0 0 0 0 W R W R 0 W R GPS_A14 GPS_B6 GPS_A5 GPS_A4 GPS_A13 GPS_A12 GPS_B5 GPS_B4 PWM_ SD TA1_ SD TA0_ SD GPS_B3 GPS_B2 0 GIPSP 0 0 0 GPS_A9 GPS_A8 0 GPS_ B1 0 GPS_ B0 0 0 0 0 0 GPS_ B11 0 GPS_ B10 0 GPS_ B9 0 GPS_ B8 0 GPS_ B7 0 0 0 GPS_ D5 0 0 0 0 0 0 0 GPS_ C12 0 GPS_ C8 0 0 0 0 IPS0_ FAULT2 0 IPS0_ FAULT1 0 0 0 0 0 0 0 0 0 W R 0 0 W R TA0 0 W R TA1 PCEP W R PWM ISAL[21:6] W R 0 ISAL[23:22] W R 0 IPS0_PSRC2 0 0 W IPS0_PSRC1 IPS1_DSYNC1 IPS0_PSRC0 0 IPS1_DSYNC0 56F8037/56F8027 Data Sheet, Rev. 8 96 Freescale Semiconductor Register Descriptions $1A SIM_IPS2 R 0 0 0 IPS2_ TA3 W 0 0 0 IPS2_ TA2 0 0 0 0 IPS2_ TA1 0 0 0 Reserved 0 = Read as 0 = Read as 1 1 = Reserved Figure 6-1 SIM Register Map Summary 6.3.1 SIM Control Register (SIM_CTRL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 STOP_ DISABLE WAIT_ DISABLE 0 0 0 0 Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Reserved—Bits 15–6 This bit field is reserved. Each bit must be set to 0. 6.3.1.2 • • 0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled Note: Using default state “0” is recommended. 6.3.1.3 • • • • Stop Disable (STOP_DISABLE)—Bits 3–2 00 = Stop mode will be entered when the 56800E core executes a STOP instruction 01 = The 56800E STOP instruction will not cause entry into Stop mode 10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the STOP_DISABLE field is write-protected until the next reset 11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is write-protected until the next reset 6.3.1.5 • • • Software Reset (SWRST)—Bit 4 Writing 1 to this field will cause the device to reset Read is zero 6.3.1.4 • • • OnCE Enable (ONCEEBL)—Bit 5 Wait Disable (WAIT_DISABLE)—Bits 1–0 00 = Wait mode will be entered when the 56800E core executes a WAIT instruction 01 = The 56800E WAIT instruction will not cause entry into Wait mode 10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the WAIT_DISABLE field is write-protected until the next reset 11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is write-protected until the next reset 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 97 6.3.2 SIM Reset Status Register (SIM_RSTAT) This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On Reset has deasserted. Base + $1 Read 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 COP_ SWR TOR 4 3 2 1 0 COP_ LOR EXTR POR 0 0 0 0 1 0 0 Write RESET 0 0 Figure 6-3 SIM Reset Status Register (SIM_RSTAT) 6.3.2.1 Reserved—Bits 15–7 This bit field is reserved. Each bit must be set to 0. 6.3.2.2 Software Reset (SWR)—Bit 6 When set, this bit indicates that the previous system reset occurred as a result of a software reset (written 1 to SWRST bit in the SIM_CTRL register). 6.3.2.3 COP Time-Out Reset (COP_TOR)—Bit 5 When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used. 6.3.2.4 COP Loss of Reference Reset (COP_LOR)—Bit 4 When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly (COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing, the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used. 6.3.2.5 External Reset (EXTR)—Bit 3 When set, this bit indicates that the previous system reset was caused by an external reset. 6.3.2.6 Power-On Reset (POR)—Bit 2 This bit is set during a Power-On Reset. 56F8037/56F8027 Data Sheet, Rev. 8 98 Freescale Semiconductor Register Descriptions 6.3.2.7 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow. Base + $2 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Software Control Data 0 - 3 Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3) 6.3.3.1 Software Control Register 0 - 3 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to contain data that will be unaffected by the other reset sources (external reset, software reset, and COP reset). 6.3.4 Most Significant Half of JTAG ID (SIM_MSHID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F2. Base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 Write RESET Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID) 6.3.5 Least Significant Half of JTAG ID (SIM_LSHID) This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $801D. Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Write RESET Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 99 6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption. Refer to the overview of power-down modes and the overview of clock generation for more information on the use of large regulator standby. Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 1 0 LRSTDBY 0 0 Figure 6-7 SIM Power Control Register (SIM_PWR) 6.3.6.1 Reserved—Bits 15–2 6.3.6.2 Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0 This bit field is reserved. Each bit must be set to 0. • • • • 6.3.7 00 = Large regulator is in Normal mode 01 = Large regulator is in Standby (reduced-power) mode 10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset 11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset Clock Output Select Register (SIM_CLKOUT) The Clock Output Select register can be used to multiplex out selected clock sources generated inside the clock generation and SIM modules onto the muxed clock output pins. All functionality is for test purposes only. Glitches may be produced when the clock is enabled or switched. The delay from the clock source to the output is unspecified. The observability of the CLKO clock output signal at an output pad is subject to the frequency limitations of the associated IO cell. GPIOA[3:0] can function as GPIO, PWM, or as clock output pins. If GPIOA[3:0] are programmed to operate as peripheral outputs, then the choice is between PWM and clock outputs. The default state is for the peripheral function of GPIOA[3:0] to be programmed as PWM (selected by bits [9:6] of the Clock Output Select register). GPIOB4 can function as GPIO, or as other peripheral outputs, including clock output (CLKO). If GPIOB4 is programmed to operate as a peripheral output and CLKO is selected in the SIM_GPSB0 register, bits [4:0] decide if CLKO is enabled or disabled and which clock source is selected if CLKO is enabled. See Figure 6-8 for details. 56F8037/56F8027 Data Sheet, Rev. 8 100 Freescale Semiconductor Register Descriptions Base + $A 15 14 13 12 11 10 Read 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 9 8 PWM3 PWM2 0 0 7 6 PWM1 PWM0 0 0 5 4 3 CLK DIS 1 2 1 0 0 0 CLKOSEL 0 0 0 Figure 6-8 CLKO Select Register (SIM_CLKOUT) 6.3.7.1 Reserved—Bits 15–10 This bit field is reserved. Each bit must be set to 0. 6.3.7.2 • • 0 = Peripheral output function of GPIOA[3] is defined to be PWM3 1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock 6.3.7.3 • • PWM0—Bit 6 0 = Peripheral output function of GPIOA[0] is defined to be PWM0 1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock 6.3.7.6 • • PWM1—Bit 7 0 = Peripheral output function of GPIOA[1] is defined to be PWM1 1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock 6.3.7.5 • • PWM2—Bit 8 0 = Peripheral output function of GPIOA[2] is defined to be PWM2 1 = Peripheral output function of GPIOA[2] is defined to be the system clock 6.3.7.4 • • PWM3—Bit 9 Clockout Disable (CLKDIS)—Bit 5 0 = CLKOUT output function is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT output function is disabled 6.3.7.7 Clockout Select (CLKOSEL)—Bits 4–0 CLKOSEL selects clock to be muxed out on the CLKO pin as defined in the following. Internal delay to CLKO output is unspecified. Signal at the output pad is undefined when CLKO signal frequency exceeds the rated frequency of the I/O cell. CLKO may not operate as expected when CLKDIS and CLKOSEL settings are changed. • • • • 00000 = Continuous system clock 00001 = Continuous peripheral clock 00010 = 3X system clock 00100.....11111 = Reserved for factory test 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 101 6.3.8 Peripheral Clock Rate Register (SIM_PCR) By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz, if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be available. This register is used to enable high-speed clocking for those peripherals that support it. Note: Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be disabled before a peripheral clock is reconfigured. Base + $B Read Write RESET 15 14 13 TMRB_ TMRA_ PWM_ CR CR CR 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C_ CR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-9 Peripheral Clock Rate Register (SIM_PCR) 6.3.8.1 Quad Timer B Clock Rate (TMRB_CR)—Bit 15 This bit selects the clock speed for the Quad Timer B module. • • 0 = Quad Timer B clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = Quad Timer B clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.2 Quad Timer A Clock Rate (TMRA_CR)—Bit 14 This bit selects the clock speed for the Quad Timer A module. • • 0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.3 Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13 This bit selects the clock speed for the PWM module. • • 0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default) 1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.4 Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12 This bit selects the clock speed for the I2C run clock. • 0 = I2C module run clock rate equals the system clock rate, to a maximum 32MHz (default) • 1 = I2C module run clock rate equals 3X system clock rate, to a maximum 96MHz 6.3.8.5 Reserved—Bits 11–0 This bit field is reserved. Each bit must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 102 Freescale Semiconductor Register Descriptions 6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0) The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use. When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock is shut off. IPBus writes are not possible. Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register is set to 1. Note: The MSCAN module supports extended power management capabilities, including Sleep, Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. Refer to the 56F802x and 56F803x Peripheral Reference Manual for details. Base + $C Read Write RESET 15 14 13 12 CMPB CMPA DAC1 DAC0 0 0 0 0 11 0 10 ADC 0 0 9 8 7 0 0 0 0 0 0 6 5 4 3 2 I2C QSCI1 QSCI0 QSPI1 QSPI0 0 0 0 0 0 1 0 0 0 PWM 0 Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0) 6.3.9.1 • • 0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled) 1 = The clock is enabled to the Comparator B module 6.3.9.2 • • Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13 0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled) 1 = The clock is enabled to the DAC1 module 6.3.9.4 • • Comparator A Clock Enable (CMPA)—Bit 14 0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled) 1 = The clock is enabled to the Comparator A module 6.3.9.3 • • Comparator B Clock Enable (CMPB)—Bit 15 Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12 0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled) 1 = The clock is enabled to the DAC0 module 6.3.9.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.9.6 • • Analog-to-Digital Converter Clock Enable (ADC)—Bit 10 0 = The clock is not provided to the ADC module (the ADC module is disabled) 1 = The clock is enabled to the ADC module 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 103 6.3.9.7 Reserved—Bits 9–7 This bit field is reserved. Each bit must be set to 0. 6.3.9.8 Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6 • 0 = The clock is not provided to the I2C module (the I2C module is disabled) • 1 = The clock is enabled to the I2C module 6.3.9.9 • • QSCI 1 Clock Enable (QSCI1)—Bit 5 0 = The clock is not provided to the QSCI1 module (the QSCI1 module is disabled) 1 = The clock is enabled to the QSCI1 module 6.3.9.10 • • QSCI 0 Clock Enable (QSCI0)—Bit 4 0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled) 1 = The clock is enabled to the QSCI0 module 6.3.9.11 • • QSPI 1 Clock Enable (QSPI1)—Bit 3 0 = The clock is not provided to the QSPI1 module (the QSPI1 module is disabled) 1 = The clock is enabled to the QSPI1 module 6.3.9.12 • • QSPI 0 Clock Enable (QSPI0)—Bit 2 0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled) 1 = The clock is enabled to the QSPI0 module 6.3.9.13 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.9.14 • • PWM Clock Enable (PWM)—Bit 0 0 = The clock is not provided to the PWM module (the PWM module is disabled) 1 = The clock is enabled to the PWM module 6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1) See Section 6.3.9 for general information about Peripheral Clock Enable registers. Base + $D 15 Read 0 Write RESET 0 14 13 12 PIT2 PIT1 PIT0 0 0 0 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 TB3 TB2 TB1 TB0 TA3 TA2 TA1 TA0 0 0 0 0 0 0 0 0 Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1) 56F8037/56F8027 Data Sheet, Rev. 8 104 Freescale Semiconductor Register Descriptions 6.3.10.1 Reserved—Bit 15 This bit field is reserved. It must be set to 0. 6.3.10.2 • • 0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled) 1 = The clock is enabled to the PIT2 module 6.3.10.3 • • Programmable Interval Timer 1 Clock Enable (PIT1)—Bit 13 0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled) 1 = The clock is enabled to the PIT1 module 6.3.10.4 • • Programmable Interval Timer 2 Clock Enable (PIT2)—Bit 14 Programmable Interval Timer 0 Clock Enable (PIT0)—Bit 12 0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled) 1 = The clock is enabled to the PIT0 module 6.3.10.5 Reserved—Bits 11–8 This bit field is reserved. Each bit must be set to 0. 6.3.10.6 • • 0 = The clock is not provided to the Timer B3 module (the Timer B3 module is disabled) 1 = The clock is enabled to the Timer B3 module 6.3.10.7 • • Quad Timer B, Channel 1 Clock Enable (TB1)—Bit 5 0 = The clock is not provided to the Timer B1 module (the Timer B1 module is disabled) 1 = The clock is enabled to the Timer B1 module 6.3.10.9 • • Quad Timer B, Channel 2 Clock Enable (TB2)—Bit 6 0 = The clock is not provided to the Timer B2 module (the Timer B2 module is disabled) 1 = The clock is enabled to the Timer B2 module 6.3.10.8 • • Quad Timer B, Channel 3 Clock Enable (TB3)—Bit 7 Quad Timer B, Channel 0 Clock Enable (TB0)—Bit 4 0 = The clock is not provided to the Timer B0 module (the Timer B0 module is disabled) 1 = The clock is enabled to the Timer B0 module 6.3.10.10 Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3 • • 0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled) 1 = The clock is enabled to the Timer A3 module 6.3.10.11 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2 • • 0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled) 1 = The clock is enabled to the Timer A2 module 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 105 6.3.10.12 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1 • • 0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled) 1 = The clock is enabled to the Timer A1 module 6.3.10.13 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0 • • 0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled) 1 = The clock is enabled to the Timer A0 module 6.3.11 Stop Disable Register 0 (SD0) By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the system to return to Run mode, this feature is provided so that selected peripherals can be left operating in Stop mode for the purpose of generating a wake-up interrupt. For power-conscious applications, it is recommended that only a minimum set of peripherals be configured to remain operational during Stop mode. Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless their corresponding Stop Disable control is set to 1. Refer to the 56F802x and 56F803x Peripheral Reference Manual for further details. Reads and writes cannot be made to a module that has its clock disabled. Note: The MSCAN module supports extended power management capabilities including Sleep, Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. For details, refer to the 56F802x and 56F803x Peripheral Reference Manual. Base + $E Read Write RESET 15 14 13 12 11 CMPB_ CMPA_ DAC1_ DAC0_ SD SD SD SD 0 0 0 0 10 9 8 7 0 ADC_ SD 0 0 0 6 5 4 I2C_ SD QSCI1 _SD QSCI0 _SD 0 0 0 0 0 0 0 0 3 2 1 0 QSPI1 _SD QSPI0 _SD 0 PWM_ SD 0 0 0 0 Figure 6-12 Stop Disable Register 0 (SD0) 6.3.11.1 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.2 • • Comparator B Clock Stop Disable (CMPB_SD)—Bit 15 Comparator A Clock Stop Disable (CMPA_SD)—Bit 14 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 56F8037/56F8027 Data Sheet, Rev. 8 106 Freescale Semiconductor Register Descriptions 6.3.11.3 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.4 • • Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.11.6 • • Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.7 Reserved—Bits 9–7 This bit field is reserved. Each bit must be set to 0. 6.3.11.8 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.9 • • Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6 QSCI1 Clock Stop Disable (QSCI1_SD)—Bit 5 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.11 QSPI1 Clock Stop Disable (QSPI1_SD)—Bit 3 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2 Each bit controls clocks to the indicated peripheral. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 107 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.13 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.12 Stop Disable Register 1 (SD1) See Section 6.3.11 for general information about Stop Disable Registers. Base + $F 15 Read 0 PIT2_ SD 0 0 Write RESET 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIT1_ SD PIT0_ SD 0 0 0 0 TB3_ SD TB2_ SD TB1_ SD TB0_ SD TA3_ SD TA2_ SD TA1_ SD TA0_ SD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-13 Stop Disable Register 1 (SD1) 6.3.12.1 Reserved—Bit 15 This bit field is reserved. It must be set to 0. 6.3.12.2 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.3 • • Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.4 • • Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.5 Reserved—Bits 11–8 This bit field is reserved. Each bit must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 108 Freescale Semiconductor Register Descriptions 6.3.12.6 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.7 • • Quad Timer B, Channel 1 Clock Stop Disable (TB1_SD)—Bit 5 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.9 • • Quad Timer B, Channel 2 Clock Stop Disable (TB2_SD)—Bit 6 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.8 • • Quad Timer B, Channel 3 Clock Stop Disable (TB3_SD)—Bit 7 Quad Timer B, Channel 0 Clock Stop Disable (TB0_SD)—Bit 4 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.10 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.11 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.12 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.13 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.13 I/O Short Address Location Register High (SIM_IOSAHI) In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area in peripheral space with single word instruction. Short address location registers specify the upper 18 bits 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 109 of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address mode, regardless of the physical location of the peripheral, as shown in Figure 6-14. “Hard Coded” Address Portion Instruction Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_IOSALO Register 2 bits from SIM_IOSAHI Register Full 24-Bit for Short I/O Address Figure 6-14 I/O Short Address Determination With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its peripheral registers and then use the I/O short addressing mode to access them. Note: The default value of this register set points to the EOnCE registers. Note: The pipeline delay between setting this register set and using short I/O addressing with the new value is five instruction cycles. Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 1 0 ISAL[23:22] 1 1 Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI) 6.3.13.1 Reserved—Bits 15—2 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.3.13.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. 6.3.14 I/O Short Address Location Register Low (SIM_IOSALO) See Section 6.3.13 for general information about I/O short address location registers. 56F8037/56F8027 Data Sheet, Rev. 8 110 Freescale Semiconductor Register Descriptions Base + $11 15 14 13 12 11 10 9 8 Read 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO) 6.3.14.1 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.3.15 Protection Register (SIM_PROT) This register provides write protection of selected control fields for safety-critical applications. The primary purpose is to prevent unsafe conditions due to the unintentional modification of these fields between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP) field protects the SIM registers’ contents, which contain peripheral clock controls. Some peripherals provide additional safety features. Refer to the 56F802x and 56F803x Peripheral Reference Manual for details. Flexibility is provided so that write protection control values may themselves be optionally locked (write-protected). Protection controls in this register have two bit values which determine the setting of the control and whether the value is locked. While a protection control remains unlocked, protection can be disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by a chip reset, which restores its default non-locked value. Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 PCEP Write RESET 2 0 0 GIPSP 0 0 0 Figure 6-17 Protection Register (SIM_PROT) 6.3.15.1 Reserved—Bits 15–4 This bit field is reserved. Each bit must be set to 0. 6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2 These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module. • • • 00 = Write protection off (default) 01 = Write protection on 10 = Write protection off and locked until chip reset 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 111 • 11 = Write protection on and locked until chip reset 6.3.15.3 GPIO and Internal Peripheral Select Protection (GIPSP)—Bits 1–0 These bits enable write protection of GPSn and IPSn registers in the SIM module and write protect all GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules. • • • • 00 = Write protection off (default) 01 = Write protection on 10 = Write protection off and locked until chip reset 11 = Write protection on and locked until chip reset Note: The PWM fields in the CLKOUT register are also write protected by GIPSP. They are reserved for in-house test only. 6.3.16 SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0) Most I/O pins have an associated GPIO function. In addition to the GPIO function, I/O can be configured to be one of several peripheral functions. The GPIOx_PEREN register within the GPIO module controls the selection between peripheral or GPIO control of the I/O pins. The GPIO function is selected when the GPIOx_PEREN bit for the I/O is 0. When the GPIOx_PEREN bit of the GPIO is 1, the fields in the GPSn registers select which peripheral function has control of the I/O. Figure 6-18 illustrates the output path to an I/O pin when an I/O has two peripheral functions. Similar muxing is required on peripheral function inputs to receive input from the properly selected I/O pin. GPIOA6_PEREN Register SIM_GPSA0 Register PWM FAULT0 0 Timer A0 1 GPIOA6 0 GPIOA6 pin 1 Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a specific peripheral function. If the user wishes to use that function, only one of these I/O must be configured to control that peripheral function. If more than one I/O is configured to control the peripheral function, the peripheral output signal will fan out to each I/O, but the peripheral input signal will be the logical OR and AND of all the I/O signals. Complete lists of I/O muxings are provided in Table 2-3. The GPSn setting can be altered during normal operation, but a delay must be inserted between the time when one function is disabled and another function is enabled. 56F8037/56F8027 Data Sheet, Rev. 8 112 Freescale Semiconductor Register Descriptions Note: After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin. Base + $13 15 14 13 Read 0 0 0 0 0 0 Write RESET 12 11 GPS_A6 0 10 9 8 GPS_A5 GPS_A4 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0) 6.3.16.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 6.3.16.2 Configure GPIOA6 (GPS_A6)—Bit 12 This field selects the alternate function for GPIOA6. • • 0 = FAULT0 - PWM FAULT0 Input (default) 1 = TA0 - Timer A0 6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10 This field selects the alternate function for GPIOA5. • • • • 00 = PWM5 - PWM5 (default) 01 = FAULT2 - PWM FAULT2 Input 10 = TA3 - Timer A3 11 = Reserved 6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8 This field selects the alternate function for GPIOA4. • • • • 00 = PWM4 - PWM4 (default) 01 = FAULT1 - PWM FAULT1 Input 10 = TA2 - Timer A2 11 = Reserved 6.3.16.5 Reserved—Bits 7–0 This bit field is reserved. Each bit must be set to 0. 6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1) See Section 6.3.16 for general information about GPIO Peripheral Select Registers. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 113 Base + $14 15 14 Read 0 0 0 0 Write RESET 13 12 11 10 9 8 GPS_A14 GPS_A13 GPS_A12 0 0 0 0 0 0 7 6 5 4 0 GPS_ A11 0 GPS_ A10 0 0 0 0 3 2 1 0 GPS_A9 GPS_A8 0 0 0 0 Figure 6-20 GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1) 6.3.17.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 6.3.17.2 Configure GPIOA14 (GPS_A14)—Bits 13–12 This field selects the alternate function for GPIOA14. • • • • 00 = TB3 - Timer B3 (default) 01 = MOSI1 - QSPI1 Master Out/Slave In 10 = TA3 - Timer A3 11 = Reserved 6.3.17.3 Configure GPIOA13 (GPS_A13)—Bits 11–10 This field selects the alternate function for GPIOA13. • • • • 00 = TB2 - Timer B2 (default) 01 = MISO1 - QSPI1 Master In/Slave Out 10 = TA2 - Timer A2 11 = Reserved 6.3.17.4 Configure GPIOA12 (GPS_A12)—Bits 9–8 This field selects the alternate function for GPIOA12. • • • • 00 = TB1- Timer B1 (default) 01 = SCLK1 - QSPI1 Serial Clock 10 = TA1 - Timer A1 11 = Reserved 6.3.17.5 Reserved—Bit 7 This bit field is reserved. It must be set to 0. 6.3.17.6 Configure GPIOA11 (GPS_A11)—Bit 6 This field selects the alternate function for GPIOA11. • • 0 = CMPBI2 - Comparator B Input 2 (default) 1 = TB3 - Timer B3 56F8037/56F8027 Data Sheet, Rev. 8 114 Freescale Semiconductor Register Descriptions 6.3.17.7 Reserved—Bit 5 This bit field is reserved. It must be set to 0. 6.3.17.8 Configure GPIOA10 (GPS_A10)—Bit 4 This field selects the alternate function for GPIOA10. • • 0 = CMPAI2- Comparator A Input 2 (default) 1 = TB2 - Timer B2 6.3.17.9 Configure GPIOA9 (GPS_A9)—Bits 3–2 This field selects the alternate function for GPIOA9. • • • • 00 = FAULT2 - PWM FAULT2 Input (default) 01 = TA3 - Timer A3 10 = CMPBI1 - Comparator B Input 1 11 = Reserved 6.3.17.10 Configure GPIOA8 (GPS_A8)—Bits 1–0 This field selects the alternate function for GPIOA8. • • • • 00 = FAULT1 - PWM FAULT1 Input (default) 01 = TA2 - Timer A2 10 = CMPAI1 - Comparator A Input 1 11 = Reserved 6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0) See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Base + $15 15 Read 0 Write RESET 0 14 13 12 11 GPS_B6 GPS_B5 0 0 0 0 10 9 8 GPS_B4 0 0 0 7 6 5 4 GPS_B3 GPS_B2 0 0 0 0 3 2 1 0 0 GPS_ B1 0 GPS_ B0 0 0 0 0 Figure 6-21 GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0) 6.3.18.1 Reserved—Bit 15 This bit field is reserved. It must be set to 0. 6.3.18.2 Configure GPIOB6 (GPS_B6)—Bits 14–13 This field selects the alternate function for GPIOB6. • • 00 = RXD0 - QSCI0 Receive Data (default) 01 = SDA - I2C Serial Data 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 115 • • 10 = CLKIN - External Clock Input 11 = Reserved 6.3.18.3 Configure GPIOB5 (GPS_B5)—Bits 12–11 This field selects the alternate function for GPIOB5. • • • • 00 = TA1 - Timer A1 (default) 01 = FAULT3 - PWM FAULT3 Input 10 = CLKIN - External Clock Input 11 = Reserved 6.3.18.4 Configure GPIOB4(GPS_B4)—Bits 10–8 This field selects the alternate function for GPIOB4. • • • • • • • 000 = TA0 - Timer A0 (default) 001 = CLKO - Clock Output 010 = SS1 - QSPI1 Slave Select 011 = TB0 - Timer B0 100 = PSRC2 - PWM4 / PWM5 Pair External Source 11x = Reserved 1x1 = Reserved 6.3.18.5 Configure GPIOB3 (GPS_B3)—Bits 7–6 This field selects the alternate function for GPIOB3. • • • • 00 = MOSI0 - QSPI0 Master Out/Slave In (default) 01 = TA3 - Timer A3 10 = PSRC1 - PWM2 / PWM3 Pair External Source 11 = Reserved 6.3.18.6 Configure GPIOB2 (GPS_B2)—Bits 5–4 This field selects the alternate function for GPIOB2. • • • • 00 = MISO0 QSPI0 Master In/Slave Out (default) 01 = TA2 - Timer A2 10 = PSRC0 - PWM0 / PWM1 Pair External Source 11 = Reserved 6.3.18.7 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.18.8 Configure GPIOB1 (GPS_B1)—Bit 2 This field selects the alternate function for GPIOB1. 56F8037/56F8027 Data Sheet, Rev. 8 116 Freescale Semiconductor Register Descriptions • • 0 = SS0 - QSPI0 Slave Select (default) 1 = SDA - I2C Serial Data 6.3.18.9 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.18.10 Configure GPIOB0 (GPS_B0)—Bits 0 This field selects the alternate function for GPIOB0. • 0 = SCLK0 - QSPI0 Serial Clock (default) • 1 = SCL - I2C Serial Clock 6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1) See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 GPS_ B11 0 GPS_ B10 0 GPS_ B9 0 GPS_ B8 0 GPS_ B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET Figure 6-22 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1) 6.3.19.1 Reserved—Bits 15–9 This bit field is reserved. Each bit must be set to 0. 6.3.19.2 Configure GPIOB11 (GPS_B11)—Bit 8 This field selects the alternate function for GPIOB11. • • 0 = CMPBO - Comparator B Output (default) 1 = TB1 - Timer B1 6.3.19.3 Reserved—Bit 7 This bit field is reserved. It must be set to 0. 6.3.19.4 Configure GPIOB10 (GPS_B10)—Bit 6 This field selects the alternate function for GPIOB10. • • 0 = CMPAO - Comparator A Output (default) 1 = TB0 - Timer B0 6.3.19.5 Reserved—Bit 5 This bit field is reserved. It must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 117 6.3.19.6 Configure GPIOB9 (GPS_B9)—Bit 4 This field selects the alternate function for GPIOB9. • • 0 = SDA - I2C Serial Data (default) 1 = MSCANRX - MSCAN Receive Data 6.3.19.7 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.19.8 Configure GPIOB8 (GPS_B8)—Bit 2 This field selects the alternate function for GPIOB8. • • 0 = SCL - I2C Serial Clock (default) 1 = MSCANTX - MSCAN Transmit Data 6.3.19.9 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.19.10 Configure GPIOB7 (GPS_B7)—Bit 0 This field selects the alternate function for GPIOB7. • • 0 = TXD0 - QSCI0 Transmit Data (default) 1 = SCL - I2C Serial Clock 6.3.20 SIM GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD) See Section 6.3.16 for general information about GPIO Peripheral Select Registers. Base + $17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 GPS_ D5 0 0 0 0 0 0 0 GPS_ C12 0 GPS_ C8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD) 6.3.20.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 118 Freescale Semiconductor Register Descriptions 6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12 This field selects the alternate function for GPIOD5. • • 0 = XTAL - External Crystal Oscillator Output (default) 1 = CLKIN - External Clock Input 6.3.20.3 Reserved—Bits 11–5 This bit field is reserved. Each bit must be set to 0. 6.3.20.4 Configure GPIOC12 (GPS_C12)—Bit 4 This field selects the alternate function for GPIOC12. • • 0 = ANB4 - ADCB, Channel 4 (default) 1 = RXD1 - QSCI1 Receive Data 6.3.20.5 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.20.6 Configure GPIOC8 (GPS_C8)—Bit 2 This field selects the alternate function for GPIOC8. • • 0 = ANA4 - ADCA, Channel 4 (default) 1 = TXD1 - QSCI1 Transmit Data 6.3.20.7 Reserved—Bits 1—0 This bit field is reserved. Each bit must be set to 0. 6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width Modulator (SIM_IPS0) The internal integration of peripherals provides input signal source selection for peripherals where an input signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral type and provide a selection list for every peripheral input signal that has more than one alternative source to indicate which source is selected. If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control of the I/O. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 119 GPIOA5_PEREN Register SIM_GPSA0 Register GPIOA5 SIM_IPS0 Register PWM5 0 GPIOA5 pin 00 0 1 01 PWM FAULT2 Timer A3 10 1 Comparator A Output (Internal) Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control IPSn settings should not be altered while an affected peripheral is in an enabled (operational) configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details. Base + $18 15 14 13 12 11 10 9 Read 0 0 IPS0_ FAULT2 0 IPS0_ FAULT1 0 0 0 0 0 0 0 0 0 Write RESET 8 7 6 5 IPS0_PSRC2 0 0 4 3 2 IPS0_PSRC1 0 0 0 1 0 IPS0_PSRC0 0 0 0 0 Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0) 6.3.21.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 6.3.21.2 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)—Bit 13 This field selects the alternate input source signal to feed PWM input FAULT2. • • 0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default) 1 = CMPBO (Internal) - Use Comparator B Output 6.3.21.3 Reserved—Bit 12 This bit field is reserved. It must be set to 0. 6.3.21.4 Select Peripheral Input Source for FAULT1 (IPS0_FAULT1)—Bit 11 This field selects the alternate input source signal to feed PWM input FAULT1. • • 0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default) 1 = CMPAO (Internal) - Use Comparator A Output 56F8037/56F8027 Data Sheet, Rev. 8 120 Freescale Semiconductor Register Descriptions 6.3.21.5 Reserved—Bits 10–9 This bit field is reserved. Each bit must be set to 0. 6.3.21.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source (IPS0_PSRC2)—Bits 8–6 This field selects the alternate input source signal to feed PWM input PSRC2 as the PWM4/PWM5 pair source. • • • 000 = I/O Pin (External) - Use a PSRC2 input pin as PWM source (default) 001 = TA3 (Internal) - Use Timer A3 output as PWM source 010 = ADC SAMPLE2 (Internal) - Use ADC SAMPLE2 result as PWM source — If the ADC conversion result in SAMPLE2 is greater than the value programmed into the High Limit register HLMT2, then PWM4 is set to 0 and PWM5 is set to 1 — If the ADC conversion result in SAMPLE2 is less than the value programmed into the Low Limit register LLMT2, then PWM4 is set to 1 and PWM5 is set to 0 • • • • 011 = CMPAO (Internal) - Use Comparator A output as PWM source 100 = CMPBO (Internal) - Use Comparator B output as PWM source 11x = Reserved 1x1 = Reserved 6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)—Bits 5–3 This field selects the alternate input source signal to feed PWM input PSRC1 as the PWM2/PWM3 pair source. • • • 000 = I/O pin (External) - Use a PSRC1 input pin as PWM source (default) 001 = TA2 (Internal) - Use Timer A2 output as PWM source 010 = ADC SAMPLE1 (Internal) - Use ADC SAMPLE1 result as PWM source — If the ADC conversion result in SAMPLE1 is greater than the value programmed into the High Limit register HLMT1, then PWM2 is set to 0 and PWM3 is set to 1 — If the ADC conversion result in SAMPLE1 is less than the value programmed into the Low Limit register LLMT1, then PWM2 is set to 1 and PWM3 is set to 0 • • • • 011 = CMPAO (Internal) - Use Comparator A output as PWM source 100 = CMPBO (Internal) - Use Comparator B output as PWM source 11x = Reserved 1x1 = Reserved 6.3.21.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source (IPS0_PSRC0)—Bits 2–0 This field selects the alternate input source signal to feed PWM input PSRC0 as the PWM0/PWM1 pair source. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 121 • • • 000 = I/O pin (External) - Use a PSRC0 input pin as PWM source (default) 001 = TA0 (Internal) - Use Timer A0 output as PWM source 010 = ADC SAMPLE0 (Internal) - Use ADC SAMPLE0 result as PWM source — If the ADC conversion result in SAMPLE0 is greater than the value programmed into the High Limit register HLMT0, then PWM0 is set to 0 and PWM1 is set to 1 — If the ADC conversion result in SAMPLE0 is less than the value programmed into the Low Limit register LLMT0, then PWM0 is set to 1 and PWM1 is set to 0 • • • • 011 = CMPAO (Internal) - Use Comparator A output as PWM source 100 = CMPBO (Internal) - Use Comparator B output as PWM source 11x = Reserved 1x1 = Reserved 6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog Converters (SIM_IPS1) See Section 6.3.21 for general information about Internal Peripheral Source Select registers. Base + $19 15 14 13 12 11 10 9 8 7 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 4 0 0 3 2 0 IPS1_DSYNC1 Write RESET 5 0 1 0 IPS1_DSYNC0 0 0 0 0 Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1) 6.3.22.1 Reserved—Bits 15–7 This bit field is reserved. Each bit must be set to 0. 6.3.22.2 Select Input Peripheral Source for SYNC Input to DAC 1 (IPS1_DSYNC1)—Bits 6–4 This field selects the alternate input source signal to feed DAC1 SYNC input. • • • • • • • 000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default) 001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input 010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input 011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input 100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input 101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input 11x = Reserved 6.3.22.3 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 56F8037/56F8027 Data Sheet, Rev. 8 122 Freescale Semiconductor Register Descriptions 6.3.22.4 Select Peripheral Input Source for SYNC Input to DAC 0 (IPS1_DSYNC0)—Bits 2–0 This field selects the alternate input source signal to feed DAC0 SYNC input. • • • • • • • 000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default) 001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input 010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input 011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input 100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input 101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input 11x = Reserved 6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A (SIM_IPS2) See Section 6.3.21 for general information about Internal Peripheral Source Select registers. Base + $1A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 IPS2_ TA3 0 0 0 IPS2_ TA2 0 0 0 IPS2_ TA1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2) 6.3.23.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 6.3.23.2 Select Peripheral Input Source for TA3 (IPS2_TA3)—Bit 12 This field selects the alternate input source signal to feed Quad Timer A, input 3. • • 0 = I/O pin (External) - Use Timer A3 input/output pin 1 = PWM SYNC (Internal) - Use PWM reload synchronization signal 6.3.23.3 Reserved—Bits 11–9 This bit field is reserved. Each bit must be set to 0. 6.3.23.4 Select Peripheral Input Source for TA2 (IPS2_TA2)—Bit 8 This field selects the alternate input source signal to feed Quad Timer A, input 2. • • 0 = I/O pin (External) - Use Timer A2 input/output pin 1 = CMPBO (Internal) - Use Comparator B output 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 123 6.3.23.5 Reserved—Bits 7–5 This bit field is reserved. Each bit must be set to 0. 6.3.23.6 Select Peripheral Input Source for TA1 (IPS2_TA1)—Bit 4 This field selects the alternate input source signal to feed Quad Timer A, input 1. • • 0 = I/O pin (External) - Use Timer A1 input/output pin 1 = CMPAO (Internal) - Use Comparator A output 6.3.23.7 Reserved—Bits 3–0 This bit field is reserved. Each bit must be set to 0. For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A module must be identical, at either the system clock rate or 3X system clock rate. 6.4 Clock Generation Overview The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to produce a system clock at a maximum of 32MHz for the peripheral, core and memory. It divides the master clock by two and gates it with appropriate power mode and clock gating controls. A 3X system high-speed peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and can be an optional clock for PWM, Timer A, Timer B, and I2C modules. These clocks are generated by gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls. The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). An external clock can be operated at any frequency up to 64MHz. The crystal oscillator can be operated only at a maximum of 8MHz. The relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz using ROSB), or powered down (using ROPD). An 8MHz MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high-speed clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master clocks to the SIM. When the PLL is selected, both the 3X system clock and the 2X system clock are enabled. If the PLL is not selected, the 3X system clock is disabled and the master clock is MSTR_OSC. In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables, and clock rate controls to provide flexible control of clocking and power utilization. The clock rate controls enable the high-speed clocking option for the two quad timers (TMRA and TMRB) and PWM, but requires the PLL to be on and selected. Refer to the 56F802x and 56F803x Peripheral Reference Manual for further details. The peripheral clock enable controls can be used to disable an individual peripheral clock when it is not used. 6.5 Power-Saving Modes The 56F8037/56F8027 operates in one of five Power-Saving modes, as shown in Table 6-2. 56F8037/56F8027 Data Sheet, Rev. 8 124 Freescale Semiconductor Power-Saving Modes Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Peripheral Clocks Description Run Core and memory clocks enabled Peripheral clocks enabled Device is fully functional Wait Core and memory clocks disabled Peripheral clocks enabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications. Possible recoveries from Wait mode to Run mode are: 1. Any interrupt 2. Executing a Debug mode entry command during the 56800E core JTAG interface 3. Any reset (POR, external, software, COP) Stop Master clock generation in the OCCS remains operational, but the SIM disables the generation of system and peripheral clocks. Core executes STOP instruction to enter this mode. Possible recoveries from Stop mode to Run mode are: 1. Interrupt from any peripheral configured in the CTRL register to operate in Stop mode (TA0-3, QSCI0, PIT0-1, CAN, CMPA-B) 2. Low-voltage interrupt 3. Executing a Debug mode entry command using the 56800E core JTAG interface 4. Any reset (POR, external, software, COP) Standby The OCCS generates the master clock at a reduced frequency (400kHz). The PLL is disabled and the high-speed peripheral option is not available. System and peripheral clocks operate at 200kHz. The user configures the OCCS and SIM to select the relaxation oscillator clock source (PRECS), shut down the PLL (PLLPD), put the relaxation oscillator in Standby mode (ROSB), and put the large regulator in Standby (LRSTDBY). The device is fully operational, but operating at a minimum frequency and power configuration. Recovery requires reversing the sequence used to enter this mode (allowing for PLL lock time). Power-Down Master clock generation in the OCCS is completely shut down. All system and peripheral clocks are disabled. The user configures the OCCS and SIM to enter Standby mode as shown in the previous description, followed by powering down the oscillator (ROPD). The only possible recoveries from this mode are: 1. External Reset 2. Power-On Reset The power-saving modes provide additional power management options by disabling the clock, reconfiguring the voltage regulator clock generation to manage power utilization, as shown in Table 6-2. Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 125 possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction. A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables the device and minimizes its power utilization but is only recoverable via reset. When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator. All peripherals, except the COP/watchdog timer, run at the system clock frequency or optional 3X system clock for PWM, Timers, and I2C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of operation is 32MHz. 6.6 Resets The SIM supports five sources of reset, as shown in Figure 6-28. The two asynchronous sources are the external reset pin and the Power-On Reset (POR). The three synchronous sources are the software reset (SW reset), which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1, the COP time-out reset (COP_TOR), and the COP loss-of-reference reset (COP_LOR). The reset generation module has three reset detectors, which resolve into four primary resets. These are outlined in Table 6-3. The JTAG circuitry is reset by the Power-On Reset. Table 6-3 Primary System Resets Reset Sources Reset Signal POR External Software COP Comments EXTENDED_POR X CLKGEN_RST X X X X Released 32 OSC_CLK cycles after all reset sources, including EXTENDED_POR, have released PERIP_RST X X X X Releases 32 SYS_CLK cycles after the CLKGEN_RST is released CORE_RST X X X X Releases 32 SYS_CLK cycles after PERIP_RST is released Stretched version of POR released 64 OSC_CLK cycles after POR deasserts Figure 6-28 provides a graphic illustration of the details in Table 6-3. Note that the POR_Delay blocks use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset. 56F8037/56F8027 Data Sheet, Rev. 8 126 Freescale Semiconductor Clocks EXTENDED_POR JTAG POR Power-On Reset (active low) pulse shaper Delay 64 OSC_CLK Clock CLKGEN_RST Memory Subsystem OCCS COMBINED_RST External RESET IN (active low) pulse shaper COP_TOR (active low) SW Reset COP_LOR (active low) PERIP_RST Delay 32 OSC_CLK Clock RESET Delay 32 sys clocks pulse shaper Delay blocks assert immediately and deassert only after the programmed number of clock cycles. Peripherals 56800E Delay 32 sys clocks pulse shaper CORE_RST Figure 6-28 Sources of RESET Functional Diagram (Test modes not included) POR resets are extended 64 OSC_CLK clocks to stabilize the power supply and clock source. All resets are subsequently extended for an additional 32 OSC_CLK clocks and 64 system clocks as the various internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset from when power comes on to when code is running is 28µS. An external reset generation circuit may also be used. A description of how these resets are used to initialize the clocking system and system modules is included in Section 6.7. 6.7 Clocks The memory, peripheral and core clocks all operate at the same frequency (32MHz maximum) with the exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option to operate at 3X system clock. The SIM is responsible for clock distributions. While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks, the ADC standby and conversion clocks are generated by a direct interface between the ADC and the OCCS module. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 127 The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps: 1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of the POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset. This provides an additional time period for the clock source and power to stabilize. 3. A Combined reset consists of the OR of the extended POR reset, the external reset, the COP reset and Software reset. The entire device, except for the POR extender, is held reset as long as Combined reset is asserted. The release of Combined reset permits operation of the CTRL register, the Synchronous reset generator, and the CLKGEN reset extender. 4. The Synchronous reset generator generates a reset to the Software and COP reset logic. The COP and Software reset logic is released three OSC_CLK cycles after Combined reset deasserts. This provides a reasonable minimum duration to the reset for these specialized functions. 5. The CLKGEN reset extender generates the CLKGEN reset used by the clock generation logic. The CLKGEN reset is released 32 OSC_CLK cycles after Combined reset deasserts. This provides a window in which the SIM stabilizes the master clock inputs to the clock generator. 6. The release of CLKGEN reset permits operation of the clock generation logic and the Peripheral reset extender. The Peripheral reset extender generates the Peripheral reset, which is released 32 SYS_CLK cycles after CLKGEN reset. This provides a window in which peripheral and core logic remain clocked, but in reset, so that synchronous resets can be resolved. 7. The release of Peripheral reset permits operation of the peripheral logic and the Core reset extender. The Core reset extender generates the Core reset, which is released 32 SYS_CLK cycles after the Peripheral reset. This provides a window in which critical peripheral start-up functions, such as Flash Security in the Flash memory, can be implemented. 8. The release of Core reset permits execution of code by the 56800E core and marks the end of the system start-up sequence. Figure 6-29 illustrates clock relationships to one another and to the various resets as the device comes out of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external reset, COP and Software reset). In the 56F8037/56F8027, this signal will be stretched by the SIM for a period of time (up to 96 OSC_CLK clock cycles, depending upon the status of the POR) to create the clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active. 56F8037/56F8027 Data Sheet, Rev. 8 128 Freescale Semiconductor Interrupts Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay Switch on falling SYS_CLK PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Figure 6-29 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts. Part 7 Security Features The 56F8037/56F8027 offers security features intended to prevent unauthorized users from reading the contents of the flash memory (FM) array. The 56F8037/56F8027’s flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the flash array. After flash security is set, an authorized user is still able to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via serial communication peripherals, is included in the application software. 7.1 Operation with Security Enabled After the user has programmed flash with the application code, the 56F8037/56F8027 can be secured by programming the security word $0002 into program memory location $00 7FF7. This non-volatile word will keep the device secured through reset and through power-down of the device. Refer to the flash memory chapter in the 56F802x and 56F803x Peripheral Reference Manual for the details. When flash security mode is enabled, the 56F8037/56F8027 will disable the core EOnCE debug capabilities. Normal 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 129 program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability and access to the ID register, but proper implementation of flash security will block any attempt to access the internal flash memory via the EOnCE port when security is enabled. 7.2.2 Flash Lockout Recovery Using JTAG If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). This does not compromise security, as the entire contents of the user’s secured code stored in flash are erased before security is disabled on the device on the next reset or power-up sequence. To start the lockout recovery sequence via JTAG, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register. Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer to the 56F802x and 56F803x Peripheral Reference Manual for more details, or contact Freescale. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller and device to return to normal unsecured operation. Power-on reset will reset both too. 7.2.3 Flash Lockout Recovery using CodeWarrior CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration file. The command “Unlock_Flash_on_Connect 1” in the .cfg file accomplishes the same task as using the Debug menu. This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). 7.2.4 Flash Lockout Recovery without mass erase A user can un-secure a secured device by programming the word $0000 into program memory location $00 7FF7. After completing the programming, both the JTAG TAP controller and the device must be reset in order to return to normal unsecured operation. Power-on reset will also reset both. 56F8037/56F8027 Data Sheet, Rev. 8 130 Freescale Semiconductor Product Analysis The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. Note: Flash contents can only be programmed for 1s to 0s. 7.3 Product Analysis The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in section 7.2.4. The customer would need to supply Technical Support with the details of the protocol to access the subroutines in flash memory. An alternative method for performing analysis on a secured device would be to mass-erase and reprogram the flash with the original code, but modify the security word or not program the security word. Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F802x and 56F803x Peripheral Reference Manual and contains only chip-specific information. This information supersedes the generic information in the 56F802x and 56F803x Peripheral Reference Manual. 8.2 Configuration There are four GPIO ports defined on the 56F8037/56F8027. The width of each port, the associated peripheral and reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown in Table 8-2. Additional details are shown in Tables 2-2 and 2-3. Table 8-1 GPIO Ports Configuration GPIO Port Available Pins in 56F8037/56F 8027 A 15 PWM, Timer, QSPI, Comparator, Reset GPIO, RESET B 14 QSPI, I2C, PWM, Clock, MSCAN, Comparator, Timer GPIO C 16 ADC, Comparator, QSCI GPIO D 8 Clock, Oscillator, DAC, JTAG GPIO, JTAG Peripheral Function Reset Function 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 131 Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function LQFP Package Pin Notes GPIOA0 PWM0 56 Defaults to A0 GPIOA1 PWM1 55 Defaults to A1 GPIOA2 PWM2 47 Defaults to A2 GPIOA3 PWM3 48 Defaults to A3 GPIOA4 PWM4 / TA2 / FAULT1 43 SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 GPIOA5 PWM5 / TA3 / FAULT2 39 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2. Defaults to A5 GPIOA6 FAULT0 / TA0 34 SIM register SIM_GPS is used to select between FAULT0 and TA0. Defaults to A6 GPIOA7 RESET 31 Defaults to RESET GPIOA8 FAULT1 / TA2 / CMPAI1 36 SIM register SIM_GPS is used to select between FAULT1, TA2, and CMPAI1. Defaults to A8 GPIOA9 FAULT2 / TA3 / CMPBI1 5 SIM register SIM_GPS is used to select between FAULT2, TA3, and CMPBI1. Defaults to A9 GPIOA10 TB2 / CMPAI2 35 SIM register SIM_GPS is used to select between TB2 and CMPAI2. Defaults to A10 GPIOA11 TB3 / CMPBI2 6 SIM register SIM_GPS is used to select between TB3 and CMPBI2. Defaults to A11 GPIOA12 SCLK1 / TB1 / TA1 37 SIM register SIM_GPS is used to select between SCLK1, TB1, and TA1. Defaults to A12 GPIOA13 MISO1 / TB2 / TA2 44 SIM register SIM_GPS is used to select between MISO1, TB2, and TA2. Defaults to A13 GPIOA14 MOSI1 / TB3 / TA3 45 SIM register SIM_GPS is used to select between MOSI1, TB3, and TA3. Defaults to A14 56F8037/56F8027 Data Sheet, Rev. 8 132 Freescale Semiconductor Configuration Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB0 SCLK0 / SCL 42 SIM register SIM_GPS is used to select between SCLK and SCL. Defaults to B0 GPIOB1 SS0 / SDA 2 SIM register SIM_GPS is used to select between SS0 and SDA. Defaults to B1 GPIOB2 MISO0 / TA2 / PSRC0 33 SIM register SIM_GPS is used to select between MISO0, TA2, and PSRC0. Defaults to B2 GPIOB3 MOSI0 / TA3 / PSRC1 32 SIM register SIM_GPS is used to select between MOSI0, TA3 and PSRC1. Defaults to B3 GPIOB4 TA0 / CLKO / SS1 / TB0 / PSRC2 38 SIM register SIM_GPS is used to select between TA0, CLKO, SS1, TB0, and PSRC2. Defaults to B4 GPIOB5 TA1 / FAULT3 / CLKIN 4 SIM register SIM_GPS is used to select between TA1, FAULT3, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B5 GPIOB6 RXD0 / SDA / CLKIN 1 SIM register SIM_GPS is used to select between RXD0, SDA, and CLKIN. CLKIN functionality is enabled using the PLL Control Register within the OCCS block. Defaults to B6 GPIOB7 TXD0 / SCL 3 SIM register SIM_GPS is used to select between TXD0 and SCL. Defaults to B7 GPIOB8 SCL / CANTX 54 SIM register SIM_GPS is used to select between SCL and CANTX. Defaults to B8 GPIOB9 SDA / CANRX 46 SIM register SIM_GPS is used to select between SDA and CANRX. Defaults to B9 GPIOB10 TB0 / CMPAO 30 SIM register SIM_GPS is used to select between TB0 and CMPAO. Defaults to B10 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 133 Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB11 TB1 / CMPBO 60 SIM register SIM_GPS is used to select between TB1 and CMPBO. Defaults to B11 GPIOB12 CANTX 57 Defaults to B12 GPIOB13 CANRX 58 Defaults to B13 GPIOC0 ANA0 / CMPAI3 24 SIM register SIM_GPS is used to select between ANA0 and CMPAI3. Defaults to C0 GPIOC1 ANA1 22 Defaults to C1 GPIOC2 ANA2 / VREFHA 20 SIM register SIM_GPS is used to select between ANA2 and VREFHA. Defaults to C2 GPIOC3 ANA3 / VREFLA 19 SIM register SIM_GPS is used to select between ANA3 and VREFLA. Defaults to C3 GPIOC4 ANB0 / CMPBI3 10 SIM register SIM_GPS is used to select between ANB0 and CMPBI3. Defaults to C4 GPIOC5 ANB1 11 Defaults to C5 GPIOC6 ANB2 / VREFHB 13 SIM register SIM_GPS is used to select between ANB2 and VREFHB. Defaults to C6 GPIOC7 ANB3 / VREFLB 14 SIM register SIM_GPS is used to select between ANB3 and VREFLB. Defaults to C7 GPIOC8 ANA4 / TXD1 26 SIM register SIM_GPS is used to select between ANA4 and TXD1. Defaults to C8 GPIOC9 ANA5 21 Defaults to C9 GPIOC10 ANA6 23 Defaults to C10 GPIOC11 ANA7 25 Defaults to C11 GPIOC12 ANB4 / RXD1 9 SIM register SIM_GPS is used to select between ANB4 and RXD1. Defaults to C12 GPIOC13 ANB5 12 Defaults to C13 GPIOC14 ANB6 62 Defaults to C14 GPIOC15 ANB7 61 Defaults to C15 GPIOD0 TDI 59 Defaults to TDI GPIOD1 TDO 64 Defaults to TDO 56F8037/56F8027 Data Sheet, Rev. 8 134 Freescale Semiconductor Reset Values Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOD2 TCK 29 Defaults to TCK GPIOD3 TMS 63 Defaults to TMS GPIOD4 EXTAL 53 Defaults to D4 GPIOD5 XTAL / CLKIN 52 SIM register SIM_GPSCD is used to select between XTAL and CLKIN. Defaults to D5 GPIOD6 DAC0 18 Defaults to D6 GPIOD7 DAC1 15 Defaults to D7 8.3 Reset Values Tables 8-1 and 8-2 detail registers for the 56F8037/56F8027; Figures 8-1 through 8-4 summarize register maps and reset values. 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 135 Add. Offset Register Acronym $0 GPIOA_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE 15 R W RS 0 R W RS .0 0 0 R . 0. W RS 0 R W RS 0 R W RS 0 R W RS 0 R W RS 0 R W RS 0 R W RS 0 R W RS 0 R W RS 0 R W RS 0 R W 0 RS 0 0 14 0 0 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 X X X X X X 0 0 0 0 0 0 PU[15:0] 1 1 1 1 1 1 1 1 D[15:0] 0 0 0 0 0 0 0 0 DD[15:0] 0 0 0 0 0 0 0 0 PE[15:0] 0 0 0 0 0 0 0 0 IA[15:0] 0 0 0 0 0 0 0 0 IEN[15:0] 0 0 13 0 0 0 0 0 0 0 IEPOL[15:0] 0 0 0 0 0 0 0 0 IPR[15:0] 0 0 0 0 0 0 0 0 IES[15:0] 0 0 0 0 0 0 0 0 OEN[15:0] 1 1 1 1 1 1 1 1 RAW DATA[15:0] X X X X X X X X X DRIVE[15:0] 0 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-1 GPIOA Register Map Summary 56F8037/56F8027 Data Sheet, Rev. 8 136 Freescale Semiconductor Reset Values Add. Offset Register Acronym $0 GPIOB_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE 15 14 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W RS 0 0 0 0 R W 0 RS 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 X X X X X X 0 0 0 0 0 0 PU[15:0] 1 1 1 1 1 1 1 1 D[15:0] 0 0 0 0 0 0 0 0 DD[15:0] 0 0 0 0 0 0 0 0 PE[15:0] 0 0 0 0 0 0 0 0 IA[15:0] 0 0 0 0 0 0 0 0 IEN[15:0] 0 0 0 0 0 0 0 0 IEPOL[15:0] 0 0 0 0 0 0 0 0 IPR[15:0] 0 0 0 0 0 0 0 0 IES[15:0] 0 0 0 0 0 0 0 0 OEN[15:0] 1 1 1 1 1 1 1 1 RAW DATA[15:0] X X X X X X X X DRIVE[15:0] 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-2 GPIOB Register Map Summary 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 137 Add. Offset Register Acronym $0 GPIOC_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE 15 R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 X X X X X X X 0 0 0 0 0 0 0 PU[15:0] 1 1 1 1 1 1 1 1 1 D[15:0] 0 0 0 0 0 0 0 0 0 DD[15:0] 0 0 0 0 0 0 0 0 0 PE[15:0] 0 0 0 0 0 0 0 0 0 IA[15:0] 0 0 0 0 0 0 0 0 0 IEN[15:0] 0 0 0 0 0 0 0 0 0 IEPOL[15:0] 0 0 0 0 0 0 0 0 0 IPR[15:0] 0 0 0 0 0 0 0 0 0 IES[15:0] 0 0 0 0 0 0 0 0 0 OEN[15:0] 1 1 1 1 1 1 1 1 1 RAW DATA[15:0] X X X X X X X X X DRIVE[15:0] 0 0 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-3 GPIOC Register Map Summary 56F8037/56F8027 Data Sheet, Rev. 8 138 Freescale Semiconductor Reset Values Add. Offset Register Acronym $0 GPIOD_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE 15 R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS R W RS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 X X X 0 0 0 PU[15:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 D[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 DD[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 PE[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 1 IA[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 IEN[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 IEPOL[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 IPR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 IES[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 OEN[15:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 RAW DATA[15:0] 0 0 0 0 0 0 0 0 X X X X X DRIVE[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read as 0 Reserved Reset Figure 8-4 GPIOD Register Map Summary 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 139 Part 9 Joint Test Action Group (JTAG) 9.1 56F8037/56F8027 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802x and 56F803x Peripheral Reference Manual. Part 10 Specifications 10.1 General Characteristics The 56F8037/56F8027 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V  10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels, combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to 125ºC ambient temperature over the following supply ranges: VSS = VSSA = 0V, VDD = VDDA = 3.0–3.6V, CL < 50pF, fOP = 32MHz CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either VDD or VSS). 56F8037/56F8027 Data Sheet, Rev. 8 140 Freescale Semiconductor General Characteristics Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA - 0.3 4.0 V ADC High Voltage Reference VREFHx - 0.3 4.0 V Voltage difference VDD to VDDA VDD - 0.3 0.3 V Voltage difference VSS to VSSA VSS - 0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 - 0.3 6.0 V Oscillator Voltage Range VOSC Pin Group 4 - 0.4 4.0 V Analog Input Voltage Range VINA Pin Group 3 - 0.3 4.0 V Input clamp current, per pin (VIN < 0)1 VIC — -20.0 mA Output clamp current, per pin (VO < 0)1 VOC — -20.0 mA Output Voltage Range (Normal Push-Pull mode) VOUT Pin Group 1 - 0.3 4.0 V Output Voltage Range (Open Drain mode) VOUTOD Pin Group 2 - 0.3 6.0 V Output Voltage Range (DAC) VOUTDAC Pin Group 5 - 0.3 4.0 V TA - 40 105 °C TSTG - 55 150 °C Ambient Temperature Industrial Storage Temperature Range (Extended Industrial) 1. Continuous clamp current per pin is -2.0 mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC Analog Outputs 56F8037/56F8027 Data Sheet, Rev. 8 Freescale Semiconductor 141 10.1.1 ElectroStatic Discharge (ESD) Model Table 10-2 56F8037/56F8027 ESD Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 750 — — V Table 10-3 LQFP Package Thermal Characteristics6 Characteristic Comments Symbol Value (LQFP) Unit Notes RJA 41 °C/W 2 Junction to ambient Natural convection Single layer board (1s) Junction to ambient Natural convection Four layer board (2s2p) RJMA 34 °C/W 1, 2 Junction to ambient (@200 ft/min) Single layer board (1s) RJMA 34 °C/W 2 Junction to ambient (@200 ft/min) Four layer board (2s2p) RJMA 29 °C/W 1, 2 Junction to board RJB 24 °C/W 4 Junction to case RJC 8 °C/W 3 JT 2 °C/W 5 Junction to package top Natural Convection 1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. 2. Junction to ambient thermal resistance, Theta-JA (RJA), was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. 3. Junction to case thermal resistance, Theta-JC (RJC), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. Junction to board thermal resistance, Theta-JB (RJB), is a metric of the thermal resistance from the junction to the printed circuit board determined per JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal Characterization Parameter, Psi-JT (YJT), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2. YJT is a useful value to use to estimate junction temperature in steady state customer environments. 6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) 56F8037/56F8027 Data Sheet, Rev. 8 142 Freescale Semiconductor General Characteristics temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 7. See Section 12.1 for more details on thermal design considerations. Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V) Characteristic Symbol Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V VREFHx 3.0 VDDA V Voltage difference VDD to VDDA VDD -0.1 0 0.1 V Voltage difference VSS to VSSA VSS -0.1 0 0.1 V 1 0 32 32 MHz Supply voltage ADC Reference Voltage High Device Clock Frequency Using relaxation oscillator Using external clock source Notes FSYSCLK Input Voltage High (digital inputs) VIH Pin Groups 1, 2 2.0 5.5 V Input Voltage Low (digital inputs) VIL Pin Groups 1, 2 -0.3 0.8 V Oscillator Input Voltage High XTAL driven by an external clock source VIHOSC Pin Group 4 2.0 VDDA + 0.3 V Oscillator Input Voltage Low VILOSC Pin Group 4 -0.3 0.8 V RLD 3K — ohms CLD — 400 pF Pin Group 1 Pin Group 1 — — -4 -8 mA Pin Groups 1, 2 Pin Groups 1, 2 — — 4 8 mA -40 105 °C DAC Output Load Resistance DAC Output Load Capacitance min.)1 Output Source Current High at VOH When programmed for low drive strength When programmed for high drive strength IOH Output Source Current Low (at VOL max.)1 When programmed for low drive strength When programmed for high drive strength IOL Ambient Operating Temperature (Extended Industrial) TA Flash Endurance (Program Erase Cycles) NF TA = -40°C to 125°C 10,000 — cycles Flash Data Retention TR TJ