NXP Semiconductors
Data Sheet: Technical Data
MC56F82348
Document Number MC56F82348MLH
Rev. 2, 07/2020
MC56F82348MLH
Supports MC56F82348MLH
Features
• This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. Each device
combines, on a single chip, the processing power of a
DSP and the functionality of an MCU with a flexible
set of peripherals to support many target applications:
– Industrial control
– Home appliances
– Smart sensors
– Wireless charging
– Power distribution systems
– Motor control (ACIM, BLDC, PMSM, SR, stepper)
– Photovoltaic systems
– Circuit breaker
– Medical device/equipment
– Instrumentation
• DSC based on 32-bit 56800EX core
– Up to 50 MIPS at 50 MHz core frequency
– DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– Up to 64 KB flash memory
– Up to 8 KB data/program RAM
– On-chip flash memory and RAM can be mapped
into both program and data memory spaces
• Analog
– Two high-speed, 8-channel, 12-bit ADCs with
dynamic x1, x2, and x4 programmable amplifier
– Four analog comparators with integrated 6-bit DAC
references
– Up to two 12-bit digital-to-analog converters (DAC)
• One FlexPWM module with up to 8 PWM outputs
• Communication interfaces
– Up to two high-speed queued SCI (QSCI) modules
with LIN slave functionality
– Up to two queued SPI (QSPI) modules
– One I2C/SMBus port
– One Modular/Scalable Controller Area Network
(MSCAN) module
• Timers
– One 16-bit quad timer (1 x 4 16-bit timer)
– Two Periodic Interval Timers (PITs)
• Security and integrity
– Cyclic Redundancy Check (CRC) generator
– Windowed Computer operating properly (COP)
watchdog
– External Watchdog Monitor (EWM)
• Clocks
– Two on-chip relaxation oscillators: 8 MHz (400 kHz
at standby mode) and 200 kHz
– Crystal / resonator oscillator
• System
– DMA controller
– Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
– Inter-module crossbar connection
– JTAG/enhanced on-chip emulation (EOnCE) for
unobtrusive, real-time debugging
• Operating characteristics
– Single supply: 3.0 V to 3.6 V
– 5 V–tolerant I/O (except for RESETB pin which is a
3.3 V pin only)
• 64-pin LQFP package
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
Overview............................................................................................ 3
7.2
Moisture handling ratings........................................................28
1.1
MC56F82348MLH Product Features......................................3
7.3
ESD handling ratings.............................................................. 28
1.2
56800EX 32-bit Digital Signal Controller (DSC) core...........3
7.4
Voltage and current operating ratings..................................... 29
1.3
Operation Parameters.............................................................. 4
1.4
On-Chip Memory and Memory Protection............................. 5
8.1
General characteristics............................................................ 30
1.5
Interrupt Controller................................................................. 5
8.2
AC electrical characteristics....................................................31
1.6
Peripheral highlights............................................................... 6
8.3
Nonswitching electrical specifications....................................32
1.7
Block diagrams........................................................................11
8.4
Switching specifications..........................................................38
2
MC56F82348MLH signal and pin descriptions.................................14
8.5
Thermal specifications............................................................ 39
3
Signal groups......................................................................................22
4
Ordering parts.....................................................................................22
9.1
Core modules...........................................................................40
4.1
Determining valid orderable parts...........................................22
9.2
System modules.......................................................................41
Part identification............................................................................... 23
9.3
Clock modules.........................................................................42
5.1
Description.............................................................................. 23
9.4
Memories and memory interfaces........................................... 44
5.2
Format..................................................................................... 23
9.5
Analog..................................................................................... 46
5.3
Fields....................................................................................... 23
9.6
Timer....................................................................................... 51
Terminology and guidelines...............................................................23
9.7
Communication interfaces.......................................................52
5
6
7
8
9
General............................................................................................... 30
Peripheral operating requirements and behaviors.............................. 40
6.1
Definition: Operating requirement.......................................... 23
10 Design Considerations....................................................................... 58
6.2
Definition: Operating behavior............................................... 24
10.1 Thermal design considerations................................................58
6.3
Definition: Attribute................................................................24
10.2 Electrical design considerations.............................................. 60
6.4
Definition: Rating....................................................................25
10.3 Power-on Reset design considerations....................................61
6.5
Result of exceeding a rating.................................................... 25
11 Obtaining package dimensions.......................................................... 63
6.6
Relationship between ratings and operating requirements......25
12 Pinout................................................................................................. 63
6.7
Guidelines for ratings and operating requirements................. 26
12.1 Signal Multiplexing and Pin Assignments.............................. 63
6.8
Definition: Typical value........................................................ 26
12.2 Pinout diagrams.......................................................................65
6.9
Typical value conditions......................................................... 27
13 Product documentation.......................................................................66
Ratings................................................................................................28
14 Revision History.................................................................................67
7.1
Thermal handling ratings........................................................ 28
MC56F82348, Rev. 2, 07/2020
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Overview
1 Overview
1.1 MC56F82348MLH Product Features
The following table highlights features that differ among members of the family. Features
not listed are shared in common by all members of the family.
Table 1. MC56F82348MLH features
MC56F82348MLH
Core frequency (MHz)
50
Flash memory (KB)
64
RAM (KB)
8
Windowed Computer Operating Properly (WCOP)
1
Periodic Interrupt Timer (PIT)
1
Cyclic Redundancy Check (CRC)
1
Timer (TMR)
4
12-bit Cyclic ADC channels
2x8
PWMA with input capture:
High-resolution channels
1x8
Standard channels
0
12-bit DAC
2
DMA
Yes
Analog Comparators (CMP)
4
QSCI
2
QSPI
2
I2C/SMBus
1
MSCAN
1
GPIO
54
Package pin count
64 LQFP
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
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Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
As many as 50 million instructions per second (MIPS) at 50 MHz core frequency
162 basic instructions
Instruction set supports both fractional arithmetic and integer arithmetic
32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
32-bit arithmetic and logic multi-bit shifter
Four 36-bit accumulators, including extension bits
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions enable compact code
Enhanced bit manipulation instruction set
Efficient C compiler and local variable support
Software subroutine and interrupt stack, with the stack's depth limited only by
memory
Priority level setting for interrupt levels
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation Parameters
• Up to 50 MHz operation
• Operation ambient temperature:
-40 oC to 125oC
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
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Overview
1.4 On-Chip Memory and Memory Protection
• Dual Harvard architecture permits as many as three simultaneous accesses to
program and data memory
• Internal flash memory with security and protection to prevent unauthorized access
• Memory resource protection (MRP) unit to protect supervisor programs and
resources from user programs
• Programming code can reside in flash memory during flash programming
• The dual-port RAM controller supports concurrent instruction fetches and data
accesses, or dual data accesses by the core.
• Concurrent accesses provide increased performance.
• The data and instruction arrive at the core in the same cycle, reducing latency.
• On-chip memory
• Up to 32 KB program/data flash memory
• Up to4 KB dual port data/program RAM
1.5 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
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Peripheral highlights
1.6 Peripheral highlights
1.6.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Up to 100 MHz operation clock with PWM Resolution as fine as 10 ns
PWM module contains four identical submodules, with two outputs per submodule
16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
PWM outputs can be configured as complementary output pairs or independent
outputs
Dedicated time-base counter with period and frequency control per submodule
Independent top and bottom deadtime insertion for each complementary pair
Independent control of both edges of each PWM output
Enhanced input capture and output compare functionality on each input:
• Channels not used for PWM generation can be used for buffered output compare
functions.
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
Synchronization of submodule to external hardware (or other PWM) is supported.
Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
Multiple output trigger events can be generated per PWM cycle via hardware.
Support for double-switching PWM outputs
Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
Independently programmable PWM output polarity
Individual software control of each PWM output
All outputs can be programmed to change simultaneously via a FORCE_OUT event.
Option to supply the source for each complementary PWM signal pair from any of
the following:
• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit
registers
1.6.2 12-bit Analog-to-Digital Converter (Cyclic type)
• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 5-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
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Peripheral highlights
•
•
•
•
•
•
•
•
• Maximum ADC clock frequency up to 10 MHz, having period as low as 100 ns
• Single conversion time of 10 ADC clock cycles
• Additional conversion time of 8 ADC clock cycles
Support of analog inputs for single-ended and differential (including unipolar
differential) conversions
Sequential and parallel scan modes. Parallel mode includes simultaneous and
independent scan modes.
First 8 samples of each ADC have offset, limit and zero-crossing calculation
supported
ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
Support for hardware-triggering and software-triggering conversions
Support for a multi-triggering mode with a programmable number of conversions on
each trigger
Each ADC has ability to scan and store up to 8 conversion results.
Current injection protection
1.6.3 Inter-Module Crossbar and AND-OR-INVERT logic
• Provides generalized connections between and among on-chip peripherals: ADCs,
12-bit DAC, comparators, quad-timers, eFlexPWMs, EWM, and select I/O pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
• Write-once protection for all registers
• AND-OR-INVERT function provides a universal Boolean function generator that
uses a four-term sum-of-products expression, with each product term containing true
or complement values of the four selected inputs (A, B, C, D).
1.6.4 Comparator
•
•
•
•
•
•
•
Full rail-to-rail comparison range
Support for high and low speed modes
Selectable input source includes external pins and internal DACs
Programmable output polarity
6-bit programmable DAC as a voltage reference per comparator
Three programmable hysteresis levels
Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
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Peripheral highlights
1.6.5 12-bit Digital-to-Analog Converter
• 12-bit resolution
• Powerdown mode
• Automatic mode allows the DAC to automatically generate pre-programmed output
waveforms, including square, triangle, and sawtooth waveforms (for applications like
slope compensation)
• Programmable period, update rate, and range
• Output can be routed to an internal comparator, or optionally to an off-chip
destination
1.6.6 Quad Timer
• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters
• Up to 100 MHz operation clock
1.6.7 Queued Serial Communications Interface (QSCI) modules
•
•
•
•
•
•
•
•
Operating clock can be up to two times the CPU operating frequency
Four-word-deep FIFOs available on both transmit and receive buffers
Standard mark/space non-return-to-zero (NRZ) format
16-bit integer and 3-bit fractional baud rate selection
Full-duplex or single-wire operation
Programmable 8-bit or 9-bit data format
Error detection capability
Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
• Up to 6.25 Mbit/s baud rate at 100 MHz operation clock
1.6.8 Queued Serial Peripheral Interface (QSPI) modules
• Maximum 12.5 Mbit/s baud rate
• Selectable baud rate clock sources for low baud rate communication
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Peripheral highlights
•
•
•
•
•
•
•
Baud rate as low as the maximum Baud rate / 4096
Full-duplex operation
Master and slave modes
Double-buffered operation with separate transmit and receive registers
Four-word-deep FIFOs available on transmit and receive buffers
Programmable length transmissions (2 bits to 16 bits)
Programmable transmit and receive shift order (MSB as first bit transmitted)
1.6.9 Inter-Integrated Circuit (I2C)/System Management Bus (SMBus)
modules
•
•
•
•
•
•
•
•
Compatible with I2C bus standard
Support for System Management Bus (SMBus) specification, version 2
Multi-master operation
General call recognition
10-bit address extension
Start/Repeat and Stop indication flags
Support for dual slave addresses or configuration of a range of slave addresses
Programmable glitch input filter with option to clock up to 100 MHz
1.6.10 Modular/Scalable Controller Area Network (MSCAN) Module
•
•
•
•
•
•
•
•
•
•
•
Clock source from PLL or oscillator.
Implementation of the CAN protocol Version 2.0 A/B
Standard and extended data frames
0-to-8 bytes data length
Programmable bit rate up to 1 Mbit/s
Support for remote frames
Individual Rx Mask Registers per Message Buffer
Internal timer for time-stamping of received and transmitted messages
Listen-only mode capability
Programmable loopback mode supporting self-test operation
Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Low power modes, with programmable wakeup on bus activity
1.6.11 Windowed Computer Operating Properly (COP) watchdog
• Programmable windowed timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
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Peripheral highlights
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator / external clock source
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 50 MHz)
• 8 MHz / 400 kHz ROSC
• Support for interrupt triggered when the counter reaches the timeout value
1.6.12 External Watchdog Monitor (EWM)
•
•
•
•
Monitors external circuit as well as the software flow
Programmable timeout period
Interrupt capability prior to timeout
Independent output (EWM_OUT_b) that places external circuit (but not CPU and
peripheral) in a safe mode when EWM timeout occurs
• Selectable reference clock source in support of EN60730 and IEC61508
• Wait mode and Stop mode operation is not supported.
• Selectable clock sources:
• External crystal oscillator / external clock source
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 50 MHz)
• 8 MHz / 400 kHz ROSC
1.6.13 Power supervisor
• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;
CPU, peripherals, and JTAG/EOnCE controllers exit RESET state
• Brownout reset (VDD < 2.0 V)
• Critical warn low-voltage interrupt (LVI 2.2 V)
• Peripheral low-voltage warning interrupt (LVI 2.7 V)
1.6.14 Phase-locked loop
•
•
•
•
Wide programmable output frequency: 200 MHz to 400 MHz
Input reference clock frequency: 8 MHz to 16 MHz
Detection of loss of lock and loss of reference clock
Ability to power down
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Clock sources
1.6.15 Clock sources
1.6.15.1 On-chip oscillators
• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two
output)
• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT
1.6.15.2 Crystal oscillator (MC56F82316 only)
• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz
1.6.16 Cyclic Redundancy Check (CRC) Generator
•
•
•
•
•
•
Hardware CRC generator circuit with 16-bit shift register
High-speed hardware CRC calculation
Programmable initial seed value
CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
Error detection for all single, double, odd, and most multibit errors
Option to transpose input data or output data (CRC result) bitwise, which is required
for certain CRC standards
1.6.17 General Purpose I/O (GPIO)
•
•
•
•
•
•
•
5 V tolerance (except RESET_B )
Individual control of peripheral mode or GPIO mode for each pin
Programmable push-pull or open drain output
Configurable pullup or pulldown on all input pins
All pins (except JTAG, RESET_B ) default to be GPIO inputs
2 mA / 9 mA capability
Controllable output slew rate
1.7 Block diagrams
The 56800EX core is based on a modified dual Harvard-style architecture, consisting of
three execution units operating in parallel, and allowing as many as six operations per
instruction cycle. The MCU-style programming model and optimized instruction set
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Clock sources
enable straightforward generation of efficient and compact code for the DSP and control
functions. The instruction set is also efficient for C compilers, to enable rapid
development of optimized control applications.
The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 shows how the
56800EX system buses communicate with internal memories, and the IPBus interface
and the internal connections among the units of the 56800EX core. Figure 2 shows the
peripherals and control blocks connected to the IPBus bridge. See the specific device’s
Reference Manual for details.
DSP56800EX Core
Program Control Unit
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
LC
LC2
FISR
Address
Generation
Unit
(AGU)
Instruction
Decoder
Interrupt
Unit
ALU1
ALU2
R0
R1
R2
R2
R3
R3
R4
R4
R5
R5
N
M01
N3
Looping
Unit
Program
Memory
SP
XAB1
XAB2
PAB
PDB
Data/
Program
RAM
CDBW
CDBR
XDB2
A2
B2
C2
D2
BitManipulation
Unit
Enhanced
OnCE™
JTAG TAP
Y
A1
B1
C1
D1
Y1
Y0
X0
MAC and ALU
A0
B0
C0
D0
IPBus
Interface
Data
Arithmetic
Logic Unit
(ALU)
Multi-Bit Shifter
Figure 1. 56800EX basic block diagram
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Clock sources
56800EX CPU
Address
Generation
Unit (AGU)
Bit
Manipulation
Unit
Arithmetic
Logic Unit
(ALU)
Crystal OSC
CRC
Clock MUX
Internal
8 MHz
Internal
200 kHz
PLL
Core Data Bus
Secondary Data Bus
Platform Bus
Crossbar Swirch
Program
Controller
(PC)
Program Bus
Memory Resource
Protection Unit
4
EOnCE
Flash Controller
and Cache
JTAG
Program/Data Flash
Up to 32KB
Data/Program RAM
Up to 6KB
DMA Controller
Interrupt Controller
Windowed
Watchdog (WCOP)
Power Management
Controller (PMC)
Periodic Interrupt
Timer (PIT) 0, 1
System Integration
Module (SIM)
Peripheral Bus
I2C
0
QSPI
0
QSCI
0,1
Quad Timer
eFlexPWM
EWM
Package
Pins
ADC A ADC B
12bit 12bit
DACB
12bit
Comparators with
6bit DAC A,B,C
Inter Module Crossbar Inputs
GPIO & Peripheral MUX
Inter-Module
Crossbar B
AND-OR-INV
Logic
Peripheral Bus
Inter Module Crossbar Outputs
Inter Module connection
Inter-Module
Crossbar A
DACA
12bit
Peripheral Bus
Figure 2. System diagram
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MC56F82348MLH signal and pin descriptions
2 MC56F82348MLH signal and pin descriptions
After reset, each pin is configured for its primary function (listed first). Any alternative
functionality, shown in parentheses, must be programmed through the GPIO module
peripheral enable registers (GPIOx_PER) and the SIM module GPIO peripheral select
(GPSx) registers. All GPIO ports can be individually programmed as an input or output
(using bit manipulation).
• PWMA_FAULT0, PWMA_FAULT1, and similar signals are inputs used to disable
selected PWMA outputs, in cases where the fault conditions originate off-chip.
Table 2. Signal descriptions
Signal Name
VDD
64
LQFP
29
Type
State During
Reset
Signal Description
Supply
Supply
I/O Power — Supplies 3.3 V power to the chip I/O interface.
Supply
Supply
I/O Ground — Provide ground for the device I/O interface.
44
60
VSS
30
43
61
VDDA
22
Supply
Supply
Analog Power — Supplies 3.3 V power to the analog modules. It
must be connected to a clean analog power supply.
VSSA
23
Supply
Supply
Analog Ground — Supplies an analog ground to the analog modules.
It must be connected to a clean power supply.
VCAP
26
57
On-chip
regulator
output
On-chip
regulator
output
Connect a 2.2 µF or greater bypass capacitor between this pin and
VSS to stabilize the core voltage regulator output required for proper
device operation.
64
Input
Input, internal Test Data Input — It is sampled on the rising edge of TCK and has
pullup
an internal pullup resistor. After reset, the default state is TDI.
enabled
GPIO Port D0
TDI
(GPIOD0)
TDO
Input/
Output
62
(GPIOD1)
TCK
1
(GPIOD2)
TMS
Output
Output
Test Data Output — It is driven in the shift-IR and shift-DR controller
states, and it changes on the falling edge of TCK. After reset, the
default state is TDO
Input/
Output
Output
GPIO Port D1
Input
Input, internal Test Clock Input — The pin is connected internally to a pullup
pullup
resistor. A Schmitt-trigger input is used for noise immunity. After
enabled
reset, the default state is TCK
Input/
Output
63
Input
GPIO Port D2
Input, internal Test Mode Select Input — It is sampled on the rising edge of TCK
pullup
and has an internal pullup resistor. After reset, the default state is
enabled
TMS.
Table continues on the next page...
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MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
Type
State During
Reset
Signal Description
NOTE: Always tie the TMS pin to VDD through a 2.2 kΩ resistor if
need to keep on-board debug capability. Otherwise, directly
tie to VDD.
(GPIOD3)
RESET or
RESETB
Input/
Output
2
(GPIOD4)
GPIOA0
Input/
Opendrain
Output
13
(ANA0&CMPA_I
N3)
Output
14
(ANA1&CMPA_I
N0)
GPIOA2
15
16
Input/
Output
Input
12
(ANA4&CMPD_I
N0)
GPIOA5
Input/
Output
Input
(ANA3&VREFL
A&CMPA_IN2)
GPIOA4
Input/
Output
Input
(ANA2&VREFH
A&CMPA_IN1)
GPIOA3
Input/
Output
Input
(CMPC_O)
GPIOA1
Input
Input/
Output
Input
11
(ANA5&CMPD_I
N1)
Input/
Output
Input
GPIO Port D3
Input, internal Reset — A direct hardware reset on the processor. When RESET is
pullup
asserted low, the device is initialized and placed in the reset state. A
enabled
Schmitt-trigger input is used for noise immunity. The internal reset
signal is deasserted synchronous with the internal clocks after a
fixed number of internal clocks. After reset, the default state is
RESET. Recommended a capacitor of up to 0.1 µF for filtering noise.
GPIO Port D4 RESET functionality is disabled in this mode and the
device can be reset only through POR, COP reset, or software reset.
Input, internal GPIO Port A0
pullup
enabled
ANA0 is analog input to channel 0 of ADCA; CMPA_IN3 is positive
input 3 of analog comparator A. After reset, the default state is
GPIOA0.
Analog comparator C output
Input, internal GPIO Port A1: After reset, the default state is GPIOA1.
pullup
enabled
ANA1 is analog input to channel 1 of ADCA; CMPA_IN0 is negative
input 0 of analog comparator A. When used as an analog input, the
signal goes to ANA1 and CMPA_IN0. The ADC control register
configures this input as ANA1 or CMPA_IN0.
Input, internal GPIO Port A2: After reset, the default state is GPIOA2.
pullup
enabled
ANA2 is analog input to channel 2 of ADCA; VREFHA is analog
reference high of ADCA; CMPA_IN1 is negative input 1 of analog
comparator A. When used as an analog input, the signal goes to
both ANA2, VREFHA, and CMPA_IN1.
Input, internal GPIO Port A3: After reset, the default state is GPIOA3.
pullup
enabled
ANA3 is analog input to channel 3 of ADCA; VREFLA is analog
reference low of ADCA; CMPA_IN2 is negative input 2 of analog
comparator A.
Input, internal GPIO Port A4: After reset, the default state is GPIOA4.
pullup
enabled
ANA4 is Analog input to channel 4 of ADCA; CMPD_IN0 is input 0 to
comparator D.
Input, internal GPIO Port A5: After reset, the default state is GPIOA5.
pullup
enabled
ANA5 is analog input to channel 5 of ADCA; ANC9 is analog input to
channel 9 of ADCC; CMPD_IN1 is negative input 1 of analog
comparator D.
Table continues on the next page...
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
15
MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOA6
64
LQFP
10
(ANA6&CMPD_I
N2)
GPIOA7
9
Input/
Output
Input
24
(ANB0&CMPB_I
N3)
GPIOB1
Input/
Output
Input
(ANA7&CMPD_I
N3)
GPIOB0
Type
Input/
Output
Input
25
Input/
Output
(ANB1&CMPB_I
N0)
Input
DACB_O
Analog
Output
GPIOB2
27
(ANB2&VERFH
B&CMPC_IN3)
GPIOB3
Input
28
(ANB3&VREFL
B&CMPC_IN0)
GPIOB4
21
(ANB6&CMPB_I
N1)
Input/
Output
Input
20
(ANB5&CMPC_I
N2)
GPIOB6
Input/
Output
Input
(ANB4&CMPC_I
N1)
GPIOB5
Input/
Output
Input/
Output
Input
19
Input/
Output
Input
State During
Reset
Signal Description
Input, internal GPIO Port A6: After reset, the default state is GPIOA6.
pullup
enabled
ANA6 is analog input to channel 5 of ADCA; CMPD_IN2 is negative
input 2 of analog comparator D.
Input, internal GPIO Port A7: After reset, the default state is GPIOA7.
pullup
enabled
ANA7 is analog input to channel 7 of ADCA; CMPD_IN3 is negative
input 3 of analog comparator D.
Input, internal GPIO Port B0: After reset, the default state is GPIOB0.
pullup
enabled
ANB0 is analog input to channel 0 of ADCB; CMPB_IN3 is positive
input 3 of analog comparator B. When used as an analog input, the
signal goes to ANB0 and CMPB_IN3. The ADC control register
configures this input as ANB0.
Input, internal GPIO Port B1: After reset, the default state is GPIOB1.
pullup
enabled
ANB1 is analog input to channel 1 of ADCB; CMPB_IN0 is negative
input 0 of analog comparator B. When used as an analog input, the
signal goes to ANB1 and CMPB_IN0. The ADC control register
configures this input as ANB1.
12-bit digital-to-analog output
Input, internal GPIO Port B2: After reset, the default state is GPIOB2.
pullup
enabled
ANB2 is analog input to channel 2 of ADCB; VREFHB is analog
reference high of ADCB; CMPC_IN3 is positive input 3 of analog
comparator C. When used as an analog input, the signal goes to
both ANB2 and CMPC_IN3.
Input, internal GPIO Port B3: After reset, the default state is GPIOB3.
pullup
enabled
ANB3 is analog input to channel 3 of ADCB; VREFLB is analog
reference low of ADCB; CMPC_IN0 is negative input 0 of analog
comparator C.
Input, internal GPIO Port B4: After reset, the default state is GPIOB4.
pullup
enabled
ANB4 is analog input to channel 4 of ADCB; CMPC_IN1 is negative
input 1 of analog comparator C.
Input, internal GPIO Port B5: After reset, the default state is GPIOB5.
pullup
enabled
ANB5 is analog input to channel 5 of ADCB; CMPC_IN2 is negative
input 2 of analog comparator C.
Input, internal GPIO Port B6: After reset, the default state is GPIOB6.
pullup
enabled
ANB6 is analog input to channel 6 of ADCB; CMPB_IN1 is negative
input 1 of analog comparator B.
Table continues on the next page...
MC56F82348, Rev. 2, 07/2020
16
NXP Semiconductors
MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOB7
64
LQFP
17
(ANB7&CMPB_I
N2)
GPIOC0
Type
Input/
Output
Input
3
Input/
Output
(EXTAL)
Analog
Input
(CLKIN0)
Input
GPIOC1
4
(XTAL)
GPIOC2
Input/
Output
Input
5
Input/
Output
State During
Reset
Signal Description
Input, internal GPIO Port B7: After reset, the default state is GPIOB7.
pullup
enabled
ANB7 is analog input to channel 7 of ADCB; CMPB_IN2 is negative
input 2 of analog comparator B.
Input, internal GPIO Port C0: After reset, the default state is GPIOC0.
pullup
enabled
The external crystal oscillator input (EXTAL) connects the internal
crystal oscillator input to an external crystal or ceramic resonator.
External clock input 01
Input, internal GPIO Port C1: After reset, the default state is GPIOC1.
pullup
enabled
The external crystal oscillator output (XTAL) connects the internal
crystal oscillator output to an external crystal or ceramic resonator.
Input, internal GPIO Port C2: After reset, the default state is GPIOC2.
pullup
enabled
SCI0 transmit data output or transmit/receive in single wire operation
(TXD0)
Output
(XB_OUT11)
Output
Crossbar module output 11
(XB_IN2)
Input
Crossbar module input 2
(CLKO0)
Output
Buffered clock output 0: the clock source is selected by clockout
select (CLKOSEL) bits in the clock output select register (CLKOUT)
of the SIM.
GPIOC3
7
Input/
Output
Input, internal GPIO Port C3: After reset, the default state is GPIOC3.
pullup
enabled
Quad timer module A channel 0 input/output
(TA0)
Input/
Output
(CMPA_O)
Output
Analog comparator A output
(RXD0)
Input
SCI0 receive data input
(CLKIN1)
Input
External clock input 1
GPIOC4
8
Input/
Output
Input, internal GPIO Port C4: After reset, the default state is GPIOC4.
pullup
enabled
Quad timer module A channel 1 input/output
(TA1)
Input/
Output
(CMPB_O)
Output
Analog comparator B output
(XB_IN6)
Input
Crossbar module input 6
(EWM_OUT_B)
Output
External Watchdog Module output
GPIOC5
18
Input/
Output
(DACA_O)
Analog
Output
(XB_IN7)
Input
GPIOC6
31
(TA2)
Input/
Output
Input/
Output
Input, internal GPIO Port C5: After reset, the default state is GPIOC5.
pullup
enabled
12-bit digital-to-analog output
Crossbar module input 7
Input, internal GPIO Port C6: After reset, the default state is GPIOC6.
pullup
enabled
Quad timer module A channel 2 input/output
Table continues on the next page...
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
17
MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
Type
State During
Reset
Signal Description
(XB_IN3)
Input
Crossbar module input 3
(CMP_REF)
Analog
Input
Positive input 3 of analog comparator A and B and C.
(SS0_B)
Input/
Output
In slave mode, SS0_B indicates to the SPI module 0 that the current
transfer is to be received.
GPIOC7
32
Input/
Output
Input, internal GPIO Port C7: After reset, the default state is GPIOC7.
pullup enable
(SS0_B)
Input/
Output
In slave mode, SS0_B indicates to the SPI module 0 that the current
transfer is to be received.
(TXD0)
Output
SCI0 transmit data output or transmit/receive in single wire operation
(XB_IN8)
Input
Crossbar module input 8
GPIOC8
33
Input/
Output
Input, internal GPIO Port C8: After reset, the default state is GPIOC8.
pullup
enabled
Master in/slave out for SPI0 — In master mode, MISO0 pin is the
data input. In slave mode, MISO0 pin is the data output. The MISO
line of a slave device is placed in the high-impedance state if the
slave device is not selected.
(MISO0)
Input/
Output
(RXD0)
Input
SCI0 receive data input
(XB_IN9)
Input
Crossbar module input 9
(XB_OUT6)
Output
Crossbar module output 6
GPIOC9
34
Input/
Output
Input, internal GPIO Port C9: After reset, the default state is GPIOC9.
pullup
enabled
SPI0 serial clock. In master mode, SCLK0 pin is an output, clocking
slaved listeners. In slave mode, SCLK0 pin is the data clock input.
(SCLK0)
Input/
Output
(XB_IN4)
Input
Crossbar module input 4
(TXD0)
Output
SCI0 transmit data output or transmit/receive in single wire operation
(XB_OUT8)
GPIOC10
Output
35
Input/
Output
Crossbar module output 8
Input, internal GPIO Port C10: After reset, the default state is GPIOC10.
pullup
enabled
Master out/slave in for SPI0 — In master mode, MOSI0 pin is the
data output. In slave mode, MOSI0 pin is the data input.
(MOSI0)
Input/
Output
(XB_IN5)
Input
Crossbar module input 4
(MISO0)
Input/
Output
Master in/slave out for SPI0 — In master mode, MISO0 pin is the
data input. In slave mode, MISO0 pin is the data output. The MISO
line of a slave device is placed in the high-impedance state if the
slave device is not selected.
(XB_OUT9)
Output
Crossbar module output 9
GPIOC11
(CANTX)
(SCL0)
37
Input/
Output
Input, internal GPIO Port C11: After reset, the default state is GPIOC11.
pullup
Open-drain enabled
CAN transmit data output
Output
Input/
Open-drain
Output
I2C0 serial clock
Table continues on the next page...
MC56F82348, Rev. 2, 07/2020
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NXP Semiconductors
MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP
(TXD1)
GPIOC12
Type
Output
38
Input/
Output
State During
Reset
Signal Description
SCI1 transmit data output or transmit/receive in single wire operation
Input, internal GPIO Port C12: After reset, the default state is GPIOC12.
pullup
enabled
CAN receive data input
(CANRX)
Input
(SDA0)
Input/
Open-drain
Output
I2C0 serial data line
(RXD1)
Input
SCI1 receive data input
GPIOC13
49
Input/
Output
Input, internal GPIO Port C13: After reset, the default state is GPIOC13.
pullup
enabled
Quad timer module A channel 3 input/output
(TA3)
Input/
Output
(XB_IN6)
Input
Crossbar module input 6
(EWM_OUT_B)
Output
External Watchdog Module output
GPIOC14
55
Input/
Output
(SDA0)
Input/
Opendrain
Output
(XB_OUT4)
Output
(PWM_FAULT4)
GPIOC15
Input
56
Input/
Output
Input, internal GPIO Port C14: After reset, the default state is GPIOC14.
pullup
enabled
I2C0 serial data line
Crossbar module output 4
Disable PWMA output 4
Input, internal GPIO Port C15: After reset, the default state is GPIOC15.
pullup
enabled
I2C0 serial clock
(SCL0)
Input/
Open-drain
Output
(XB_OUT5)
Output
Crossbar module output 5
(PWM_FAULT5)
Input
Disable PWMA output 5
GPIOE0
45
(PWM_0B)
GPIOE1
Input/
Output
46
(PWM_0A)
GPIOE2
Input/
Output
Input/
Output
47
(PWMA_1B)
GPIOE3
Input/
Output
Input/
Output
Input/
Output
48
(PWMA_1A)
Input/
Output
Input/
Output
Input, internal GPIO Port E0: After reset, the default state is GPIOE0.
pullup
enabled
PWM module A (NanoEdge), submodule 0, output B or input capture
B
Input, internal GPIO Port E1: After reset, the default state is GPIOE1.
pullup
enabled
PWM module A (NanoEdge), submodule 0, output A or input capture
A
Input, internal GPIO Port E2: After reset, the default state is GPIOE2.
pullup
enabled
PWM module A (NanoEdge), submodule 1, output B or input capture
B
Input, internal GPIO Port E3: After reset, the default state is GPIOE3.
pullup
enabled
PWM module A (NanoEdge), submodule 1, output A or input capture
A
Table continues on the next page...
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
19
MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOE4
64
LQFP
51
Type
Input/
Output
(PWMA_2B)
Input/
Output
(XB_IN2)
Input
GPIOE5
52
Input/
Output
(PWMA_2A)
Input/
Output
(XB_IN3)
Input
GPIOE6
53
(PWMA_3B)
Input/
Output
(XB_IN4)
GPIOE7
Input/
Output
Input
54
Input/
Output
(PWMA_3A)
Input/
Output
(XB_IN5)
Input
GPIOF0
36
Input/
Output
(XB_IN6)
Input
(SCLK1)
Input/
Output
GPIOF1
50
Input/
Output
State During
Reset
Signal Description
Input, internal GPIO Port E4: After reset, the default state is GPIOE4.
pullup
enabled
PWM module A (NanoEdge), submodule 2, output B or input capture
B
Crossbar module input 2
Input, internal GPIO Port E5: After reset, the default state is GPIOE5.
pullup
enabled
PWM module A (NanoEdge), submodule 2, output A or input capture
A
Crossbar module input 3
Input, internal GPIO Port E6: After reset, the default state is GPIOE6.
pullup
enabled
PWM module A (NanoEdge), submodule 3, output B or input capture
B
Crossbar module input 4
Input, internal GPIO Port E7: After reset, the default state is GPIOE7.
pullup
enabled
PWM module A (NanoEdge), submodule 3, output A or input capture
A
Crossbar module input 5
Input, internal GPIO Port F0: After reset, the default state is GPIOF0.
pullup
enabled
Crossbar module input 6
SPI1 serial clock — In master mode, SCLK1 pin is an output,
clocking slaved listeners. In slave mode, SCLK1 pin is the data clock
input 0.
Input, internal GPIO Port F1: After reset, the default state is GPIOF1.
pullup
enabled
Buffered clock output 1: the clock source is selected by clockout
select (CLKOSEL) bits in the clock output select register (CLKOUT)
of the SIM.
(CLKO1)
Output
(XB_IN7)
Input
Crossbar module input 7
(CMPD_O)
Output
Analog comparator D output
GPIOF2
39
Input/
Output
Input, internal GPIO Port F2: After reset, the default state is GPIOF2.
pullup
enabled
I2C0 serial clock
(SCL0)
Input/
Opendrain
Output
(XB_OUT6)
Output
Crossbar module output 6
(MISO1)
Input/
Output
Master in/slave out for SPI1 —In master mode, MISO1 pin is the
data input. In slave mode, MISO1 pin is the data output. The MISO
line of a slave device is placed in the high-impedance state if the
slave device is not selected.
Table continues on the next page...
MC56F82348, Rev. 2, 07/2020
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NXP Semiconductors
MC56F82348MLH signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOF3
64
LQFP
40
Type
Input/
Output
State During
Reset
Signal Description
Input, internal GPIO Port F3: After reset, the default state is GPIOF3.
pullup
enabled
I2C0 serial data line
(SDA0)
Input/
Open-drain
Output
(XB_OUT7)
Output
Crossbar module output 7
(MOSI1)
Input/
Output
Master out/slave in for SPI1— In master mode, MOSI1 pin is the
data output. In slave mode, MOSI1 pin is the data input.
GPIOF4
41
Input/
Output
Input, internal GPIO Port F4: After reset, the default state is GPIOF4.
pullup
enabled
SCI1 transmit data output or transmit/receive in single wire operation
(TXD1)
Output
(XB_OUT8)
Output
Crossbar module output 8
(PWMA_0X)
Input/
Output
PWM module A (NanoEdge), submodule 0, output X or input capture
X
(PWMA_FAULT
6)
Input
Disable PWMA output 6
GPIOF5
42
Input/
Output
Input, internal GPIO Port F5: After reset, the default state is GPIOF5.
pullup
enabled
SCI1 receive data input
(RXD1)
Input
(XB_OUT9)
Output
Crossbar module output 9
(PWMA_1X)
Input/
Output
PWM module A (NanoEdge), submodule 1, output X or input capture
X
(PWMA_FAULT
7)
Input
Disable PWMA output 7
GPIOF6
58
Input/
Output
(PWMA_3X)
Input/
Output
(XB_IN2)
Input
GPIOF7
59
Input/
Output
Input, internal GPIO Port F6: After reset, the default state is GPIOF6.
pullup
enabled
PWM module A (NanoEdge), submodule 3, output X or input capture
X
Crossbar module input 2
Input, internal GPIO Port F7: After reset, the default state is GPIOF7.
pullup
enabled
Analog comparator C output
(CMPC_O)
Output
(SS1_B)
Input/
Output
In slave mode, SS1_B indicates to the SPI1 module that the current
transfer is to be received.
(XB_IN3)
Input
Crossbar module input 3
GPIOF8
6
Input/
Output
Input, internal GPIO Port F8: After reset, the default state is GPIOF8.
pullup
enabled
(RXD0)
Input
SCI0 receive data input
(XB_OUT10)
Output
Crossbar module output 10
(CMPD_O)
Output
Analog comparator D output
(PWMA_2X)
PWM module A (NanoEdge), submodule 2, output X or input capture
X
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
21
Signal groups
1. If CLKIN is selected as the device’s external clock input, then both the GPS_C0 bit (in GPS1) and the EXT_SEL bit (in
OCCS oscillator control register (OSCTL)) must be set. Also, the crystal oscillator should be powered down.
3 Signal groups
The input and output signals of the MC56F82348MLH are organized into functional
groups, as detailed in Table 3.
Table 3. Functional Group Pin Allocations
Functional Group
Number of
Pins in
64LQFP
Power Inputs (VDD, VDDA), Power output( VCAP)
6
Ground (VSS, VSSA)
4
Reset
1
eFlexPWM with NanoEdge ports not including fault pins (for 56F827xx)
8
eFlexPWM without NanoEdge ports not including fault pins
4
Queued Serial Peripheral Interface (QSPI0 and QSPI1) ports
9
Queued Serial Communications Interface (QSCI0 and QSCI1) ports
10
Inter-Integrated Circuit Interface
(I2C0)
ports
6
12-bit Analog-to-Digital Converter inputs
16
Analog Comparator inputs/outputs
17/5
12-bit Digital-to-Analog output
2
Quad Timer Module (TMRA and TMRB) ports
4
Controller Area Network (MSCAN)
2
Inter-Module Crossbar inputs/outputs
17/11
Clock inputs/outputs
2/2
JTAG / Enhanced On-Chip Emulation (EOnCE)
4
4 Ordering parts
4.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MC56F82
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NXP Semiconductors
Part identification
5 Part identification
5.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
5.2 Format
Part numbers for this device have the following format: Q 56F8 2 C F P T PP N
5.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• MC = Fully qualified, general market flow
• PC = Prequalification
56F8
DSC family with flash memory and DSP56800/
DSP56800E/DSP56800EX core
• 56F8
2
DSC subfamily
• 2
C
Maximum CPU frequency (MHz)
• 3 = 50 MHz
F
Primary program flash memory size
• 4 = 64 KB
P
Pin count
• 8 = 64
T
Temperature range (°C)
• M = –40 to 125
PP
Package identifier
• LH = 64LQFP
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
6 Terminology and guidelines
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
23
Terminology and guidelines
6.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
6.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
0.9
Max.
1.1
Unit
V
6.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
6.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
6.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
6.3.1 Example
This is an example of an attribute:
MC56F82348, Rev. 2, 07/2020
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NXP Semiconductors
Terminology and guidelines
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
6.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
6.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
6.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
25
Terminology and guidelines
6.6 Relationship between ratings and operating requirements
e
Op
ing
rat
r
(
ng
ati
n.
mi
ing
rat
e
Op
e
re
ir
qu
)
in.
t (m
n
me
ing
rat
e
Op
e
re
ir
qu
t (m
n
me
ax
.)
ing
rat
e
Op
(m
ng
ati
.)
ax
r
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
ng
dli
n
Ha
in
rat
n.)
mi
g(
–∞
)
ma
g(
ng
dli
n
Ha
in
rat
x.)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
∞
Handling (power off)
6.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
6.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
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Terminology and guidelines
6.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
6.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
6.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
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Ratings
7 Ratings
7.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.3 ESD handling ratings
Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification. During the
device qualification ESD stresses were performed for the human body model (HBM), the
machine model (MM), and the charge device model (CDM).
All latch-up testing is in conformity with AEC-Q100 Stress Test Qualification.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
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Ratings
Table 4. ESD/Latch-up Protection
Characteristic1
Min
Max
Unit
ESD for Human Body Model (HBM)
–2000
+2000
V
ESD for Machine Model (MM)
–200
+200
V
ESD for Charge Device Model (CDM)
–500
+500
V
Latch-up current at TA= 85°C (ILAT)
–100
+100
mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
7.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device
reliability or cause permanent damage to the device.
NOTE
If the voltage difference between VDD and VDDA or VSS and
VSSA is too large, then the device can malfunction or be
permanently damaged. The restrictions are:
• At all times, it is recommended that the voltage
difference of VDD - VSS be within +/-200 mV of the
voltage difference of VDDA - VSSA, including power
ramp up and ramp down; see additional requirements in
Table 6. Failure to do this recommendation may result in a
harmful leakage current through the substrate, between the
VDD/VSS and VDDA/VSSA pad cells. This harmful
leakage current could prevent the device from operating
after power up.
• At all times, to avoid permanent damage to the part, the
voltage difference between VDD and VDDA must
absolutely be limited to 0.3 V; see Table 5.
• At all times, to avoid permanent damage to the part, the
voltage difference between VSS and VSSA must
absolutely be limited to 0.3 V; see Table 5.
Table 5. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Symbol
Notes
Min
Max
Unit
Supply Voltage Range
VDD
-0.3
4.0
V
Analog Supply Voltage Range
VDDA
-0.3
4.0
V
Table continues on the next page...
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General
Table 5. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V) (continued)
Characteristic
Symbol
Min
Max
Unit
VREFHx
-0.3
4.0
V
Voltage difference VDD to VDDA
ΔVDD
-0.3
0.3
V
Voltage difference VSS to VSSA
ΔVSS
-0.3
0.3
V
ADC High Voltage Reference
Notes
Digital Input Voltage Range
VIN
Pin Group 1
-0.3
5.5
V
RESET Input Voltage Range
VIN_RESET
Pin Group 2
-0.3
4.0
V
Oscillator Input Voltage Range
VOSC
Pin Group 4
-0.4
4.0
V
Analog Input Voltage Range
VINA
Pin Group 3
-0.3
4.0
V
Input clamp current, per pin (VIN < VSS - 0.3 V),
VIC
—
-5.0
mA
Output clamp current, per pin
VOC
—
±20.0
mA
Contiguous pin DC injection current—regional limit sum
of 16 contiguous pins
IICont
-25
25
mA
Output Voltage Range (normal push-pull mode)
VOUT
Pin Group 1, 2
-0.3
4.0
V
VOUTOD
Pin Group 1
-0.3
5.5
V
VOUTOD_RE
Pin Group 2
-0.3
4.0
V
VOUT_DAC
Pin Group 5
-0.3
4.0
V
Ambient Temperature
TA
M temperature
-40
125
°C
Junction Temperature
Tj
M temperature
-40
135
°C
-55
150
°C
Output Voltage Range (open drain mode)
RESET Output Voltage Range
SET
DAC Output Voltage Range
Storage Temperature Range (Extended Industrial)
TSTG
8 General
8.1 General characteristics
The device is fabricated in high-density, low-power CMOS with 5 V–tolerant TTLcompatible digital inputs, except 3.3 V for RESET . The term “5 V–tolerant” refers to the
capability of an I/O pin, built on a 3.3 V–compatible process technology, to withstand a
voltage up to 5.5 V without damaging the device.
5 V–tolerant I/O is desirable because many systems have a mixture of devices designed
for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V– and 5 V–
compatible I/O voltage levels . This 5 V–tolerant capability therefore offers the power
savings of 3.3 V I/O levels combined with the ability to receive 5 V levels without
damage.
Absolute maximum ratings in Table 5 are stress ratings only, and functional operation at
the maximum is not guaranteed. Stress beyond these ratings may affect device reliability
or cause permanent damage to the device.
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Unless otherwise stated, all specifications within this chapter apply to the temperature
range specified in Table 5 over the following supply ranges: VSS=VSSA=0V,
VDD=VDDA=3.0V to 3.6V, CL≤50 pF, fOP=50MHz.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
8.2 AC electrical characteristics
Tests are conducted using the input levels specified in the section "Voltage and current
operating behaviors". Unless otherwise specified, propagation delays are measured from
the 50% to the 50% point, and rise and fall times are measured between the 10% and 90%
points, as shown in Figure 3.
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH – VIL)/2.
Figure 3. Input signal measurement references
Figure 4 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid
Data2 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 4. Signal states
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General
8.3 Nonswitching electrical specifications
8.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is less than 200 ms.
Table 6. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Characteristic
Supply voltage
ADC (Cyclic) Reference Voltage High
Symbol
Notes1
Min
Typ
VDD, VDDA
2.7
3.3
VREFHA
VDDA-0.6
Max
Unit
3.6
V
VDDA
V
VREFHB
Voltage difference VDD to VDDA
ΔVDD
-0.1
0
0.1
V
Voltage difference VSS to VSSA
ΔVSS
-0.1
0
0.1
V
5.5
V
VDD
V
0.3 x VDD
V
Input Voltage High (digital inputs)
RESET Input Voltage High
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
VIH
Pin Group 1
0.7 x VDD
VIH_RESET
Pin Group 2
0.7 x VDD
VIL
Pin Groups 1, 2
VIHOSC
Pin Group 4
2.0
VDD + 0.3
V
VILOSC
Pin Group 4
-0.3
0.8
V
IOH
Pin Group 1
—
-2
mA
Pin Group 1
—
-9
Pin Groups 1, 2
—
2
Pin Groups 1, 2
—
9
—
XTAL driven by an external clock source
Oscillator Input Voltage Low
Output Source Current High (at VOH min.)
• Programmed for low drive strength
• Programmed for high drive strength
Output Source Current Low (at VOL max.)2, 3
• Programmed for low drive strength
• Programmed for high drive strength
IOL
mA
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. When ambient temperature is below 105°C, total IO sink current and total IO source current are limited to 75 mA each
When ambient temperature is above 105°C, total IO sink current and total IO source current are limited to 36 mA combined
3. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive
injection currents of 16 contiguous pins—is 25 mA.
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8.3.2 LVD and POR operating requirements
Table 7. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Characteristic
POR Assert
Symbol
Voltage1
Min
Typ
Max
Unit
POR
2.0
V
POR
2.7
V
LVI_2p7 Threshold Voltage
2.73
V
LVI_2p2 Threshold Voltage
2.23
V
POR Release
Voltage2
1. During 3.3-volt VDD power supply ramp down
2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p7)
8.3.3 Voltage and current operating behaviors
The following table provides information about power supply requirements and I/O pin
characteristics.
Table 8. DC Electrical Characteristics at Recommended Operating Conditions
Symbol
Notes 1
Min
Typ
Max
Unit
Test Conditions
Output Voltage High
VOH
Pin Group 1
VDD - 0.5
—
—
V
IOH = IOHmax
Output Voltage Low
VOL
Pin Groups
1, 2
—
—
0.5
V
IOL = IOLmax
IIH
Pin Group 1
—
0
+/- 2.5
µA
VIN = 2.4 V to 5.5 V
Characteristic
Digital Input Current High
Pin Group 2
pull-up enabled or
disabled
Comparator Input Current
High
Oscillator Input Current
High
Digital Input Current Low
2, 3
VIN = 2.4 V to VDD
IIHC
Pin Group 3
—
0
+/- 2
µA
VIN = VDDA
IIHOSC
Pin Group 3
—
0
+/- 2
µA
VIN = VDDA
IIL
Pin Groups
1, 2
—
0
+/- 0.5
µA
VIN = 0V
RPull-Up
20
—
50
kΩ
—
RPull-Down
20
—
50
kΩ
—
pull-up disabled
Internal Pull-Up
Resistance
Internal Pull-Down
Resistance
Comparator Input Current
Low
IILC
Pin Group 3
—
0
+/- 2
µA
VIN = 0V
Oscillator Input Current
Low
IILOSC
Pin Group 3
—
0
+/- 2
µA
VIN = 0V
DAC Output Voltage
Range
VDAC
Pin Group 5
Typically
VSSA +
40mV
—
Typically
VDDA 40mV
V
RLD = 3 kΩ || CLD = 400 pF
IOZ
Pin Groups
1, 2
—
0
+/- 1
µA
—
Output Current 2, 3
High Impedance State
Table continues on the next page...
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General
Table 8. DC Electrical Characteristics at Recommended Operating Conditions (continued)
Characteristic
Schmitt Trigger Input
Hysteresis
Symbol
Notes 1
Min
Typ
Max
Unit
Test Conditions
VHYS
Pin Groups
1, 2
0.06 × VDD
—
—
V
—
I (uA)
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC
2. See the following figure "IIN/IOZ vs. VIN (typical; pull-up disabled) (design simulation)" .
3. To minimize the excessive leakage ( > 1 μA) current from digital pin, input signal should NOT stay between 1.1 V and 0.9
× VDD for prolonged time.
V (volt)
Figure 5. IIN/IOZ vs. VIN (typical; pull-up disabled) (design simulation)
8.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.
Table 9. Reset, stop, wait, and interrupt timing
Characteristic
Minimum RESET Assertion Duration
Symbol
Typical Min
Typical
Max
Unit
See
Figure
tRA
16
—
ns
—
Table continues on the next page...
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General
Table 9. Reset, stop, wait, and interrupt timing (continued)
Characteristic
Symbol
Typical Min
tRDA
865 x TOSC + 8 x T
tIF
361.3
RESET deassertion to First Address Fetch
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
Typical
Max
570.9
Unit
See
Figure
ns
—
ns
—
NOTE
In Table 9, T = system clock cycle and TOSC = oscillator clock
cycle. For an operating frequency of 50MHz, T=20 ns. At 4
MHz (used coming out of reset and stop modes), T=250 ns.
Table 10. Power mode transition behavior
Symbol
TPOR
Description
Min
Max
Unit
Notes
After a POR event, the amount of delay from when VDD reaches
2.7 V to when the first instruction executes (over the operating
temperature range).
199
225
µs
STOP mode to RUN mode
6.81
LPS mode to LPRUN mode
240.9
810
µs
VLPS mode to VLPRUN mode
1424
1459
µs
WAIT mode to RUN mode
0.570
0.620
µs
LPWAIT mode to LPRUN mode
237.2
810
µs
1
VLPWAIT mode to VLPRUN mode
1413
1500
µs
2
µs
1. CPU clock = 200 KHz and 8 MHz IRC on standby. Exit by an interrupt on PORTC GPIO.
2. Using 64 KHz external clock; CPU Clock = 32KHz. Exit by an interrupt on PortC GPIO.
8.3.5 Power consumption operating behaviors
Table 11. Current Consumption (mA)
Mode
RUN
Maximum
Frequency
50 MHz
Conditions1
•
•
•
•
•
50 MHz Core and Peripheral clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Continuous MAC instructions with fetches from Program
Flash
• All peripheral modules enabled. TMRs and SCIs using 1X
peripheral clock
• NanoEdge within eFlexPWM using 2X peripheral clock
Typical at
3.3 V, 25°C
Maximum
at 3.6V,
125°C
IDD1
IDDA
IDD1
IDDA
27.6
9.9
43.5
14.0
Table continues on the next page...
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General
Table 11. Current Consumption (mA) (continued)
Mode
Maximum
Frequency
Conditions1
Typical at
3.3 V, 25°C
Maximum
at 3.6V,
125°C
IDD1
IDDA
IDD1
IDDA
• ADC/DAC (only one 12-bit DAC and all 6-bit DACs)
powered on and clocked
• Comparator powered on
WAIT
50 MHz
•
•
•
•
•
•
•
•
•
50 MHz Core and Peripheral clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Processor Core in WAIT state
All Peripheral modules enabled.
TMRs and SCIs using 1X Clock
NanoEdge within PWMA using 2X clock
ADC/DAC (single 12-bit DAC, all 6-bit DACs), Comparator
powered off
24.0
—
41.3
—
STOP
4 MHz
•
•
•
•
•
•
•
4 MHz Device Clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
6.3
—
19.4
—
LPRUN
(LsRUN)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's (ROSC)
low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except NanoEdge and
cyclic ADCs. One 12-bit DAC and all 6-bit DACs enabled. 2
• Simple loop with running from platform instruction buffer
2.8
3.1
13.0
4.0
LPWAIT
(LsWAIT)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's (ROSC)
low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except NanoEdge and
cyclic ADCs. One 12-bit DAC and all 6-bit DACs enabled.2
• Processor core in wait mode
2.7
3.1
13.0
4.0
LPSTOP
(LsSTOP)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's (ROSC)
low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Only PITs and COP enabled; other peripheral modules
disabled and clocks gated off2
• Processor core in stop mode
1.2
—
12.0
—
VLPRUN
200 kHz
•
•
•
•
•
0.7
—
10.0
—
32 kHz Device Clock
Clocked by a 32 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Table continues on the next page...
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General
Table 11. Current Consumption (mA) (continued)
Mode
Maximum
Frequency
Conditions1
Typical at
3.3 V, 25°C
Maximum
at 3.6V,
125°C
IDD1
IDDA
IDD1
IDDA
•
•
•
•
Small regulator is disabled
PLL disabled
Repeat NOP instructions
All peripheral modules, except COP and EWM, disabled
and clocks gated off
• Simple loop running from platform instruction buffer
VLPWAIT
200 kHz
•
•
•
•
•
•
•
•
32 kHz Device Clock
Clocked by a 32 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Small regulator is disabled
PLL disabled
All peripheral modules, except COP, disabled and clocks
gated off
• Processor core in wait mode
0.7
—
10.0
—
VLPSTOP
200 kHz
•
•
•
•
•
•
•
•
0.7
—
10.0
—
32 kHz Device Clock
Clocked by a 32 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby.
Small regulator is disabled.
PLL disabled
All peripheral modules, except COP, disabled and clocks
gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads.
2. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 500 kHz due to
the fixed frequency ratio of 1:2 between the CPU clock and the flash clock when running with 2 MHz external clock input
and CPU running at 1 MHz.
8.3.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
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General
8.3.7 Capacitance attributes
Table 12. Capacitance attributes
Description
Symbol
Min.
Typ.
Max.
Unit
CIN
—
10
—
pF
COUT
—
10
—
pF
Input capacitance
Output capacitance
8.4 Switching specifications
8.4.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
0.001
50
MHz
0
50
—
50
Notes
Normal run mode
fSYSCLK
fBUS
Device (system and core) clock frequency
• using relaxation oscillator
• using external clock source
Bus clock
MHz
8.4.2 General switching timing
Table 14. Switching timing
Symbol
Description
GPIO pin interrupt pulse
Min
width1
Max
1.5
Synchronous path
Unit
Notes
IP Bus
Clock
Cycles
2
Port rise and fall time (high drive strength), slew disabled,
2.7V ≤ VDD ≤ 3.6V
5.5
15.1
ns
3
Port rise and fall time (high drive strength), slew enabled,
2.7V ≤ VDD ≤ 3.6V
1.5
6.8
ns
4
Port rise and fall time (low drive strength), slew disabled, 2.7V
≤ VDD ≤ 3.6V
8.2
17.8
ns
3
Port rise and fall time (low drive strength), slew enabled, 2.7V
≤ VDD ≤ 3.6V
3.2
9.2
ns
4
1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming
GPIOn_IPOLR and GPIOn_IENR.
2. The greater synchronous and asynchronous timing must be met.
3. 75 pF load
4. 15 pF load
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8.5 Thermal specifications
8.5.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
Description
Min
Max
Unit
TJ
Die junction temperature
–40
135
°C
TA
Ambient temperature
–40
125
°C
8.5.2 Thermal attributes
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board type
Symbol
Description
64 LQFP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
64
resistance, junction
to ambient (natural
convection)
°C/W
,
Four-layer (2s2p)
RθJA
Thermal
46
resistance, junction
to ambient (natural
convection)
°C/W
1,
Single-layer (1s)
RθJMA
Thermal
52
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,2
Four-layer (2s2p)
RθJMA
Thermal
39
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,2
—
RθJB
Thermal
28
resistance, junction
to board
°C/W
Table continues on the next page...
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Peripheral operating requirements and behaviors
Board type
Symbol
Description
64 LQFP
Unit
—
RθJC
Thermal
15
resistance, junction
to case
°C/W
—
ΨJT
Thermal
3
characterization
parameter, junction
to package top
outside center
(natural
convection)
°C/W
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions
—Forced Convection (Moving Air) with the board horizontal.
9 Peripheral operating requirements and behaviors
9.1 Core modules
9.1.1 JTAG timing
Table 16. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
fOP
DC
SYS_CLK/ 8
MHz
Figure 6
TCK clock pulse width
tPW
50
—
ns
Figure 6
TMS, TDI data set-up time
tDS
5
—
ns
Figure 7
TMS, TDI data hold time
tDH
5
—
ns
Figure 7
TCK low to TDO data valid
tDV
—
30
ns
Figure 7
TCK low to TDO tri-state
tTS
—
30
ns
Figure 7
1/fOP
VIH
TCK
(Input)
VM = VIL + (VIH – VIL)/2
tPW
tPW
VM
VM
VIL
Figure 6. Test clock input timing diagram
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TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
Figure 7. Test access port timing diagram
9.2 System modules
9.2.1 Voltage regulator specifications
The voltage regulator supplies approximately 1.2 V to the device's core logic. For proper
operations, the voltage regulator requires a minimum external 2.2 µF capacitor on each
VCAP pin with total capacitors on all VCAP pins at a minimum of 4.4µF. Ceramic and
tantalum capacitors tend to provide better performance tolerances. The output voltage can
be measured directly on the VCAP pin. The specifications for this regulator are shown in
Table 17.
Table 17. Regulator 1.2 V parameters
Characteristic
Output Voltage
1
Symbol
Min
Typ
Max
Unit
VCAP
—
1.22
—
V
Short Circuit Current 2
ISS
—
600
—
mA
Short Circuit Tolerance (VCAP shorted to ground)
TRSC
—
—
30
minute
1. Value is after trim
2. Guaranteed by design
Table 18. Bandgap electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Reference Voltage (after trim)
VREF
—
1.211
—
V
1. Typical value is trimmed at 25℃. There could be ±50 mV variation due to temperature change.
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System modules
9.3 Clock modules
9.3.1 External clock operation timing
Parameters listed are guaranteed by design.
Table 19. External clock operation timing requirements
Characteristic
Frequency of operation (external clock
Clock pulse
driver)1
width2
External clock input rise
External clock input fall
time3
time4
Symbol
Min
Typ
Max
Unit
fosc
—
—
50
MHz
tPW
8
trise
—
—
ns
1
ns
tfall
—
—
1
ns
Input high voltage overdrive by an external clock
Vih
0.85×VDD
—
—
V
Input low voltage overdrive by an external clock
Vil
—
—
0.3×VDD
V
1.
2.
3.
4.
See the "External clock timing" figure for details on using the recommended connection of an external clock driver.
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
External
Clock
90%
50%
10%
tPW
tfall
tPW
trise
VIH
90%
50%
10%
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 8. External clock timing
9.3.2 Phase-Locked Loop timing
Table 20. Phase-Locked Loop timing
Characteristic
PLL input reference
Symbol
frequency1
Min
Typ
Max
Unit
fref
8
8
16
MHz
PLL output frequency2
fop
200
—
400
MHz
PLL lock time3
tplls
35.5
73.2
µs
Allowed Duty Cycle of input reference
tdc
40
60
%
50
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 50 MHz. If the NanoEdge PWM is available, the PLL output must
be set to 400 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
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9.3.3 External crystal or resonator requirement
Table 21. Crystal or resonator requirement
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation
fXOSC
4
8
16
MHz
9.3.4 RC Oscillator Timing
Table 22. RC Oscillator Electrical Specifications
Characteristic
8 MHz Output
Symbol
Min
Typ
Max
Unit
0°C to 105°C
7.84
8
8.16
MHz
-40°C to 105°C
7.76
8
8.24
MHz
-40°C to 125°C
7.60
8
8.32
MHz
-40°C to 105°C
248
405
562
kHz
-40°C to 125°C
198
405
702
kHz
0°C to 105°C
±1.5
±2
%
-40°C to 105°C
±1.5
±3
%
-40°C to 125°C
±1.5
-5 to +4
%
Frequency1
Run Mode
Standby Mode (IRC
trimmed @ 8 MHz)
8 MHz Frequency Variation over 25°C
RUN Mode
200 kHz Output
Frequency2
RUN Mode
-40°C to 105°C
194
200
206
kHz
-40°C to 125°C
192
200
208
kHz
0°C to 85°C
±1.5
±2
%
-40°C to 105°C
±1.5
±3
%
-40°C to 125°C
±1.5
±4
%
0.12
-
µs
10
-
µs
50
52
%
200 kHz Output Frequency Variation over 25°C
RUN Mode
Stabilization Time
8 MHz
output3
200 kHz
output4
Output Duty Cycle
1.
2.
3.
4.
tstab
48
Frequency after factory trim
Frequency after factory trim
Standby to run mode transition
Power down to run mode transition
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System modules
Figure 9. RC Oscillator Temperature Variation (Typical) After Trim (Preliminary)
9.4 Memories and memory interfaces
9.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
9.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
thvpgm4
Longword Program high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
7.5
18
μs
—
Table continues on the next page...
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System modules
Table 23. NVM program/erase timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
thversscr
thversall
Notes
Sector Erase high-voltage time
—
13
113
ms
Erase All high-voltage time
—
52
452
ms
1
1. Maximum time based on expectations at cycling end-of-life.
9.4.1.2
Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
tpgm4
Program Longword execution time
—
65
145
μs
tersscr
Erase Flash Sector execution time
—
14
114
ms
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
70
575
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
—
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
9.4.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
9.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 26. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
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System modules
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
9.5 Analog
9.5.1 12-bit Cyclic Analog-to-Digital Converter (ADC) Parameters
Table 27. 12-bit ADC Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDDA
3
3.3
3.6
V
VREFH (in external reference mode)
Vrefhx
VDDA-0.6
VDDA
V
ADC Conversion Clock
fADCCLK
0.1
10
MHz
Recommended Operating Conditions
Conversion Range
RAD
Fully Differential
– (VREFH – VREFL)
Single Ended/Unipolar
Input Voltage Range (per input)
VREFH – VREFL
VREFH
VREFL
VADIN
External Reference
V
VREFL
VREFH
0
VDDA
Internal Reference
V
Timing and Power
Conversion Time
tADC
8
ADC Clock
Cycles
ADC Power-Up Time (from adc_pdn)
tADPU
13
ADC Clock
Cycles
ADC RUN Current (per ADC block)
IADRUN
1.8
mA
ADC Powerdown Current (adc_pdn
enabled)
IADPWRDWN
0.1
µA
IVREFH
190
225
µA
Integral non-Linearity
INL
+/- 1.5
+/- 2.5
LSB
Differential non-Linearity
DNL
+/- 0.5
+/- 0.8
LSB
VREFH Current (in external mode)
Accuracy (DC or Absolute)
Monotonicity
Offset
GUARANTEED
VOFFSET
mV
+/- 8
Fully Differential
+/- 12
Single Ended/Unipolar
Gain Error
EGAIN
0.996 to1.004
0.990 to 1.010
Signal to Noise Ratio
SNR
66
dB
Total Harmonic Distortion
THD
75
dB
SFDR
77
dB
AC Specifications
Spurious Free Dynamic Range
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Table 27. 12-bit ADC Electrical Specifications (continued)
Characteristic
Symbol
Min
Typ
Signal to Noise plus Distortion
SINAD
66
dB
Effective Number of Bits
ENOB
—
bits
Gain = 1x (Fully Differential/Unipolar)
10.6
Gain = 2x (Fully Differential/Unipolar)
—
Gain = 4x (Fully Differential/Unipolar)
10.3
Gain = 1x (Single Ended)
10.6
Gain = 2x (Single Ended)
10.4
Gain = 4x (Single Ended)
10.2
Variation across channels
0.1
Max
Unit
ADC Inputs
Input Leakage Current
IIN
1
nA
Temperature sensor slope
TSLOPE
1.3
mV/°C
Temperature sensor voltage at 25 °C
VTEMP25
0.82
V
Disturbance
Input Injection Current
Channel to Channel Crosstalk
IINJ
+/-3
mA
ISOXTLK
-82
dB
Memory Crosstalk
MEMXTLK
-71
dB
Input Capacitance
CADI
4.8
pF
Sampling Capacitor
9.5.1.1
Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, and
both S1 and S2 are dependent on
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
-12
(ADC ClockRate) x 4.8x10
+ 100 ohm + 50 ohm
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C1
Analog Input
1
Channel Mux
equivalent resistance
100Ohms
50 ESD
Resistor
S1
C1
S1
S/H
S1
2
C1
S1
S2
S2
(VREFHx - VREFLx ) / 2
C1
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock
frequency
S1
S2
Figure 10. Equivalent circuit for A/D loading
9.5.2 12-bit Digital-to-Analog Converter (DAC) parameters
Table 28. DAC parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
12
12
12
bits
—
1
—
—
11
µs
—
+/- 3
+/- 4
LSB
DC Specifications
Resolution
Settling time
At output load
µs
RLD = 3 kΩ
CLD = 400 pF
Power-up time
Time from release of PWRDWN
signal until DACOUT signal is valid
tDAPU
Accuracy
Integral non-linearity
Range of input digital words:
INL
410 to 3891 ($19A - $F33)
5% to 95% of full range
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Table 28. DAC parameters (continued)
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
Differential non-linearity
Range of input digital words:
DNL
—
+/- 0.8
+/- 0.9
LSB
410 to 3891 ($19A - $F33)
5% to 95% of full range
Monotonicity
> 6 sigma monotonicity,
guaranteed
—
< 3.4 ppm non-monotonicity
Offset error
Range of input digital words:
VOFFSET
—
+/- 25
+ /- 47
mV
EGAIN
—
+/- 0.5
+/- 1.5
%
VSSA +
0.04 V
—
VDDA - 0.04
V
V
410 to 3891 ($19A - $F33)
5% to 95% of full range
Gain error
Range of input digital words: 410 to
3891 ($19A - $F33) 5% to 95% of
full range
DAC Output
Output voltage range
Within 40 mV of either VSSA or VDDA
VOUT
AC Specifications
Signal-to-noise ratio
SNR
—
85
—
dB
Spurious free dynamic
range
SFDR
—
-72
—
dB
Effective number of bits
ENOB
—
11
—
bits
9.5.3 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
2.7
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
300
—
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
VAIN
Analog input voltage
VAIO
Analog input offset voltage
VH
—
36
—
μA
VSS
—
VDD
V
—
—
20
mV
• CR0[HYSTCTR] = 001
—
5
13
mV
• CR0[HYSTCTR] = 01
—
25
48
mV
• CR0[HYSTCTR] = 102
—
55
105
mV
112
—
80
148
mV
Analog comparator hysteresis
• CR0[HYSTCTR] =
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
Propagation delay, high-speed mode (EN=1,
PMODE=1)
—
25
50
ns
tDHS
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Table 29. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
tDLS
IDAC6b
Min.
Typ.
Max.
Unit
Propagation delay, low-speed mode (EN=1,
PMODE=0)3
—
60
200
ns
Analog comparator initialization delay4
—
40
—
μs
6-bit DAC current adder (enabled)
—
7
—
μA
VDDA
—
VDD
V
6-bit DAC reference inputs, Vin1 and Vin2
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB5
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1.
2.
3.
4.
Measured with input voltage range limited to 0 to VDD
Measured with input voltage range limited to 0.7≤Vin≤VDD-0.8
Input voltage range: 0.1VDD≤Vin≤0.9VDD, step = ±100mV, across all temperature. Does not include PCB and PAD delay.
Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
5. 1 LSB = Vreference/64
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Timer
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1.3
1.6
1.9
Vin level (V)
1
2.2
2.5
2.8
3.1
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
9.6 Timer
9.6.1 Quad Timer timing
Parameters listed are guaranteed by design.
Table 30. Timer timing
Characteristic
Symbol
Min1
Max
Unit
See Figure
Timer input period
PIN
2T + 10
—
ns
Figure 13
Timer input high/low period
PINHL
1T + 5
—
ns
Figure 13
Timer output period
POUT
2T-2
—
ns
Figure 13
Timer output high/low period
POUTHL
1T-2
—
ns
Figure 13
1. T = clock cycle. For 50 MHz operation, T = 20 ns.
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Timer
Timer Inputs
PIN
PINHL
PINHL
POUT
POUTHL
POUTHL
Timer Outputs
Figure 13. Timer timing
9.7 Communication interfaces
9.7.1 Queued Serial Peripheral Interface (SPI) timing
Parameters listed are guaranteed by design.
Table 31. SPI timing
Characteristic
Symbol
Min
Max
Unit
Cycle time
tC
60
—
ns
60
—
ns
Master
Slave
See Figure
Figure 14
Figure 15
Figure 16
Figure 17
Enable lead time
tELD
Master
—
—
ns
20
—
ns
—
—
ns
20
—
ns
—
ns
—
ns
Figure 17
Slave
Enable lag time
tELG
Master
Figure 17
Slave
Clock (SCK) high time
tCH
Master
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Clock (SCK) low time
tCL
Master
28
—
ns
28
—
ns
20
—
ns
Figure 17
Slave
Data set-up time required for inputs
tDS
Master
Figure 14
Figure 15
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Timer
Table 31. SPI timing (continued)
Characteristic
Symbol
Slave
Min
Max
Unit
See Figure
1
—
ns
Figure 16
Figure 17
Data hold time required for inputs
tDH
Master
1
—
ns
3
—
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Access time (time to data active
from high-impedance state)
tA
5
—
ns
tD
5
—
ns
tDV
—
ns
—
ns
Figure 17
Slave
Disable time (hold time to highimpedance state)
Figure 17
Slave
Data valid for outputs
Master
Slave (after enable edge)
Figure 14
Figure 15
Figure 16
Figure 17
Data invalid
tDI
Master
0
—
ns
0
—
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Rise time
tR
Master
—
1
ns
—
1
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Fall time
Master
tF
—
1
ns
—
1
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
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Timer
SS
(Input)
SS is held high on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
Bits 14–1
tDI
MOSI
(Output)
LSB in
tDI(ref)
tDV
Master MSB out
Bits 14–1
Master LSB out
tR
tF
Figure 14. SPI master timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tCL
SCLK (CPOL = 0)
(Output)
tR
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
MISO
(Input)
MSB in
tDI
tDV(ref)
MOSI
(Output)
Master MSB out
tDH
Bits 14–1
tDV
Bits 14– 1
tF
LSB in
tDI(ref)
Master LSB out
tR
Figure 15. SPI master timing (CPHA = 1)
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Timer
SS
(Input)
tC
tF
tCL
SCLK (CPOL = 0)
(Input)
tELG
tR
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tA
MISO
(Output)
Slave MSB out
tF
tR
Bits 14–1
tDS
Slave LSB out
tDV
tDI
tDH
MOSI
(Input)
MSB in
tD
Bits 14–1
tDI
LSB in
Figure 16. SPI slave timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tA
MISO
(Output)
Slave MSB out
Bits 14–1
tDS
tDV
tDH
MOSI
(Input)
tD
tF
MSB in
Bits 14–1
Slave LSB out
tDI
LSB in
Figure 17. SPI slave timing (CPHA = 1)
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55
Timer
9.7.2 Queued Serial Communication Interface (SCI) timing
Parameters listed are guaranteed by design.
Table 32. SCI timing
Characteristic
Symbol
Min
Max
Unit
See Figure
BR
—
(fMAX/16)
Mbit/s
—
RXD pulse width
RXDPW
0.965/BR
1.04/BR
μs
Figure 18
TXD pulse width
TXDPW
0.965/BR
1.04/BR
μs
Figure 19
-14
14
%
—
Baud
rate1
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH
clock rate before synchronization
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
-2
2
%
—
Minimum break character length
TBREAK
13
—
Master
node bit
periods
—
11
—
Slave node
bit periods
—
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.)50 MHz.
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 18. RXD pulse width
TXD
SCI transmit
data pin
(output)
TXDPW
Figure 19. TXD pulse width
9.7.3 Modular/Scalable Controller Area Network (MSCAN)
Table 33. MSCAN Timing Parameters
Characteristic
Symbol
Min
Max
Unit
Baud Rate
BRCAN
—
1
Mbit/s
CAN Wakeup dominant pulse filtered
TWAKEUP
—
1.5
µs
CAN Wakeup dominant pulse pass
TWAKEUP
5
—
µs
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NXP Semiconductors
Timer
CAN_RX
CAN receive
data pin
(Input)
TWAKEUP
Figure 20. Bus Wake-up Detection
NOTE
CAN wakeup is not supported when ROSC_8M is in standby
mode.
9.7.4 Inter-Integrated Circuit Interface (I2C) timing
Table 34. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
fSCL
0
100
0
400
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
tLOW
4.7
—
1.3
—
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
Data hold time for I2C bus devices
tHD; DAT
0
3.45
0
0.91
Unit
kHz
µs
µs
µs
µs
µs
Data set-up time
tSU; DAT
250
—
1002
—
ns
Rise time of SDA and SCL signals
tr
—
1000
20 +0.1Cb3,
300
ns
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb3,
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
4
4
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
4. Cb = total capacitance of the one bus line in pF.
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57
Design Considerations
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 21. Timing definition for fast and standard mode devices on the I2C bus
10 Design Considerations
10.1 Thermal design considerations
An estimate of the chip junction temperature (TJ) can be obtained from the equation:
TJ = TA + (RΘJA × PD)
where
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)
PD = Power dissipation in the package (W).
The junction-to-ambient thermal resistance is an industry-standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single-layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which TJ value is closer to the application depends on the power
dissipated by other components on the board.
• The TJ value obtained on a single layer board is appropriate for a tightly packed
printed circuit board.
• The TJ value obtained on a board with the internal planes is usually appropriate if the
board has low-power dissipation and if the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-tocase thermal resistance and a case-to-ambient thermal resistance:
RΘJA = RΘJC + RΘCA
where
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NXP Semiconductors
Design Considerations
RΘJA = Package junction-to-ambient thermal resistance (°C/W)
RΘJC = Package junction-to-case thermal resistance (°C/W)
RΘCA = Package case-to-ambient thermal resistance (°C/W).
RΘJC is device related and cannot be adjusted. You control the thermal environment to
change the case to ambient thermal resistance, RΘCA. For instance, you can change the
size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat
sinks are not used, the thermal characterization parameter (ΨJT) can be used to
determine the junction temperature with a measurement of the temperature at the top
center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where
TT = Thermocouple temperature on top of package (°C/W)
ΨJT = hermal characterization parameter (°C/W)
PD = Power dissipation in package (W).
The thermal characterization parameter is measured per JESD51–2 specification using a
40-gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
To determine the junction temperature of the device in the application when heat
sinks are used, the junction temperature is determined from a thermocouple inserted at
the interface between the case of the package and the interface material. A clearance slot
or hole is normally required in the heat sink. Minimizing the size of the clearance is
important to minimize the change in thermal performance caused by removing part of the
thermal interface to the heat sink. Because of the experimental difficulties with this
technique, many engineers measure the heat sink temperature and then back-calculate the
case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-tocase thermal resistance.
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59
Design Considerations
10.2 Electrical design considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the device:
• Provide a low-impedance path from the board power supply to each VDD pin on the
device and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as
near as possible to the package supply pins. The recommended bypass configuration
is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA.
Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VDD and VSS (GND) pins are as short as possible.
• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF
ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
• Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
• Using separate power planes for VDD and VDDA and separate ground planes for VSS
and VSSA are recommended. Connect the separate analog and digital power and
ground planes as near as possible to power supply outputs. If an analog circuit and
digital circuit are powered by the same power supply, then connect a small inductor
or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted
together.
• Physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. Place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,
or I2C, the designer should provide an interface to this port if in-circuit flash
programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value
should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of
0.1 µF–4.7 µF.
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NXP Semiconductors
Design Considerations
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
reset state during normal operation if JTAG converter is not present. Furthermore,
configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.
• During reset and after reset but before I/O initialization, all the GPIO pins are at tristate.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.
10.3 Power-on Reset design considerations
10.3.1 Improper power-up sequence between VDD/VSS and VDDA/
VSSA:
It is recommended that VDD be kept within 100 mV of VDDA at all times, including
power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may
cause a leakage current through the substrate, between the VDD and VDDA pad cells.
This leakage current could prevent operation of the device after it powers up. The voltage
difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid
permanent damage to the part (See Table 5). Also see Table 6.
10.3.2 Unnecessary protection circuit:
In many circuit designs, it is a general practice to add external clamping diodes on each
analog input pin; see diode D1 and D2 in Figure 22, to prevent the surge voltage from
damaging the analog input.
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61
Design Considerations
Reg1
DC
DC
200V ~300V
Reg3
12V
C6
+
DC
C5
Reg2
DC
3.3V
DC
C4
+
3.3V
DC
C2
+
R6
R3
C1
VDDA
R5
R4
C3
VDD
MC56F8xxxx
R2
D1
C8
ADC_IN
R1
D2
RESET
D1 and D2 are unnecessary,
because all analog
inputs already have the
internal current injection
protection circuit.
VSSA
VSS
+
C7
Figure 22. Protection Circuit Example
This device uses the 5V tolerance I/O. When the pin is configured to digital input, it can
accept 5V input. See Table 5. When the pin is configured to analog input, the internal
integrated current injection protection circuit is enabled. The current injection protection
circuit performs the same functions as external clamp diode D1 and D2 in Figure 22. As
long as the source or sink current for each analog pin is less than 3 mA, then there is no
damage to the device. See Table 27. Therefore, D1 and D2 clamping diodes are not
recommended to be used.
10.3.3 Heavy capacitive load on power supply output:
In some applications, the low cost DC/DC converter may not regulate the output voltage
well before it reaches the regulation point, which is roughly around 2.5V to 2.7V.
However, the device might exit power-on reset at around 2.3V. If the initialization code
enables the PLL to run the DSC at full speed right after reset, then the high current will
be pulled by DSC from the supply, which can cause the supply voltage to drop below the
operation voltage; see the captured graph (Figure 23). This can cause the DSC fail to start
up.
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NXP Semiconductors
Obtaining package dimensions
Figure 23. Supply Voltage Drop
A recommended initialization sequence during power-up is:
1. After POR is released, run a few hundred NOP instructions from the internal
relaxation oscillator; this gives time for the supply voltage to stabilize.
2. Configure the peripherals (except the ADC) to the desired settings; the ADC should
stay in low power mode.
3. Power up the PLL.
4. After the PLL locks, switch the clock from PLL prescale to postscale.
5. Configure the ADC.
11 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing's document number:
Drawing for package
Document number to be used
64-pin LQFP
98ASS23234W
12 Pinout
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NXP Semiconductors
63
Pinout
12.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The SIM's GPS registers are responsible
for selecting which ALT functionality is available on most pins.
NOTE
• The RESETB pin is a 3.3 V pin only.
• If the GPIOC1 pin is used as GPIO, the XOSC should be
powered down.
64
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
1
TCK
TCK
GPIOD2
2
RESETB
RESETB
GPIOD4
3
GPIOC0
GPIOC0
EXTAL
4
GPIOC1
GPIOC1
XTAL
5
GPIOC2
GPIOC2
TXD0
XB_OUT11
6
GPIOF8
GPIOF8
RXD0
XB_OUT10
7
GPIOC3
GPIOC3
TA0
CMPA_O
RXD0
CLKIN1
8
GPIOC4
GPIOC4
TA1
CMPB_O
XB_IN6
EWM_OUT_B
9
GPIOA7
GPIOA7
ANA7
10
GPIOA6
GPIOA6
ANA6
11
GPIOA5
GPIOA5
ANA5
12
GPIOA4
GPIOA4
ANA4
13
GPIOA0
GPIOA0
ANA0&CMPA_IN3
14
GPIOA1
GPIOA1
ANA1&CMPA_IN0
15
GPIOA2
GPIOA2
ANA2&VREFHA&CMPA_IN1
16
GPIOA3
GPIOA3
ANA3&VREFLA&CMPA_IN2
17
GPIOB7
GPIOB7
ANB7&CMPB_IN2
18
GPIOC5
GPIOC5
DACA_O
19
GPIOB6
GPIOB6
ANB6&CMPB_IN1
20
GPIOB5
GPIOB5
ANB5&CMPC_IN2
21
GPIOB4
GPIOB4
ANB4&CMPC_IN1
22
VDDA
VDDA
23
VSSA
VSSA
24
GPIOB0
GPIOB0
ANB0&CMPB_IN3
25
GPIOB1
GPIOB1
ANB1&CMPB_IN0
26
VCAP
VCAP
27
GPIOB2
GPIOB2
ANB2&VERFHB&CMPC_IN3
28
GPIOB3
GPIOB3
ANB3&VREFLB&CMPC_IN0
29
VDD
VDD
30
VSS
VSS
31
GPIOC6
GPIOC6
CMP_REF
SS0_B
TA2
CLKIN0
XB_IN2
CLKO0
PWM_2X
CMPC_O
XB_IN7
DACB_O
XB_IN3
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64
NXP Semiconductors
Pinout
64
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
32
GPIOC7
GPIOC7
SS0_B
TXD0
XB_IN8
33
GPIOC8
GPIOC8
MISO0
RXD0
XB_IN9
XB_OUT6
34
GPIOC9
GPIOC9
SCLK0
XB_IN4
TXD0
XB_OUT8
35
GPIOC10
GPIOC10
MOSI0
XB_IN5
MISO0
XB_OUT9
36
GPIOF0
GPIOF0
XB_IN6
37
GPIOC11
GPIOC11
SCL0
TXD1
38
GPIOC12
GPIOC12
SDA0
RXD1
39
GPIOF2
GPIOF2
SCL0
XB_OUT6
40
GPIOF3
GPIOF3
SDA0
XB_OUT7
41
GPIOF4
GPIOF4
TXD1
XB_OUT8
PWM_0X
PWM_FAULT6
42
GPIOF5
GPIOF5
RXD1
XB_OUT9
PWM_1X
PWM_FAULT7
43
VSS
VSS
44
VDD
VDD
45
GPIOE0
GPIOE0
PWM_0B
46
GPIOE1
GPIOE1
PWM_0A
47
GPIOE2
GPIOE2
PWM_1B
48
GPIOE3
GPIOE3
PWM_1A
49
GPIOC13
GPIOC13
TA3
XB_IN6
EWM_OUT_B
50
GPIOF1
GPIOF1
CLKO1
XB_IN7
51
GPIOE4
GPIOE4
PWM_2B
XB_IN2
52
GPIOE5
GPIOE5
PWM_2A
XB_IN3
53
GPIOE6
GPIOE6
PWM_3B
XB_IN4
54
GPIOE7
GPIOE7
PWM_3A
XB_IN5
55
GPIOC14
GPIOC14
SDA0
XB_OUT4
PWM_FAULT4
56
GPIOC15
GPIOC15
SCL0
XB_OUT5
PWM_FAULT5
57
VCAP
VCAP
58
GPIOF6
GPIOF6
PWM_3X
XB_IN2
59
GPIOF7
GPIOF7
CMPC_O
XB_IN3
60
VDD
VDD
61
VSS
VSS
62
TDO
TDO
GPIOD1
63
TMS
TMS
GPIOD3
64
TDI
TDI
GPIOD0
12.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams show
the default function. However, many signals may be multiplexed onto a single pin.
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
65
TDI
TMS
TDO
VSS
VDD
GPIOF7
GPIOF6
VCAP
GPIOC15
GPIOC14
GPIOE7
GPIOE6
GPIOE5
GPIOE4
GPIOF1
GPIOC13
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Product documentation
GPIOA7
9
40
GPIOF3
GPIOA6
10
39
GPIOF2
GPIOA5
11
38
GPIOC12
GPIOA4
12
37
GPIOC11
GPIOA0
13
36
GPIOF0
GPIOA1
14
35
GPIOC10
GPIOA2
15
34
GPIOC9
GPIOA3
16
33
GPIOC8
32
GPIOF4
GPIOC7
41
31
8
GPIOC6
GPIOC4
30
GPIOF5
VSS
42
29
7
VDD
GPIOC3
28
VSS
GPIOB3
43
27
6
GPIOB2
GPIOF8
26
VDD
VCAP
44
25
5
GPIOB1
GPIOC2
24
GPIOE0
GPIOB0
45
23
4
VSSA
GPIOC1
22
GPIOE1
VDDA
46
21
3
GPIOB4
GPIOC0
20
GPIOE2
GPIOB5
47
19
2
GPIOB6
RESETB
18
GPIOE3
GPIOC5
48
17
1
GPIOB7
TCK
Figure 24. 64-pin LQFP
NOTE
The RESETB pin is a 3.3 V pin only.
13 Product documentation
The documents listed in Table 35 are required for a complete description and proper
design with the device. Documentation is available from local NXP distributors, NXP
sales offices, or online at nxp.com.
Table 35. Device documentation
Topic
DSP56800E/DSP56800EX
Reference Manual
Reference Manual
Description
Detailed description of the 56800EX family architecture, 32-bit
digital signal controller core processor, and the instruction set
Detailed functional description and programming model
Document Number
DSP56800ERM
MC56F827XXRM
Table continues on the next page...
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NXP Semiconductors
Revision History
Table 35. Device documentation (continued)
Topic
Description
MC56F82348MLH Data Sheet
MC56F82xxx Errata
Electrical and timing specifications, pin descriptions, and
package information (this document)
Details any chip issues that might be present
Document Number
MC56F82348
MC56F82xxx_Errata
14 Revision History
The following table summarizes changes to this document since the release of the
previous version.
Table 36. Revision History
Rev. No.
Date
Substantial Changes
1
10/2013
First public release
1.1
11/2013
In Table 2, added DACB_O signal description
2
07/2020
Some updates, for a new public release.
• Some clarifications in sections "12-bit Analog-to-Digital Converter (Cyclic type)",
"Queued Serial Peripheral Interface (QSPI) modules", "Power supervisor" and
"Electrical design considerations".
• Added new sections "External Watchdog Monitor (EWM)" and "Power-on Reset design
considerations".
• Minor update in the table "Signal descriptions".
• Some updates in sections "Voltage and current operating ratings", "Voltage and current
operating requirements", "Voltage and current operating behaviors", the tables "12-bit
ADC Electrical Specifications" and "SCI timing".
MC56F82348, Rev. 2, 07/2020
NXP Semiconductors
67
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Document Number MC56F82348MLH
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