NXP Semiconductors
Data Sheet: Technical Data
MC56F827xx
Document Number MC56F827XXDS
Rev. 4.1, 11/2018
MC56F827XXDS
Supports MC56F82748VLH,
MC56F82748MLH, MC56F82746VLF,
MC56F82746MLF, MC56F82743VLC,
MC56F82743VFM, MC56F82738VLH,
MC56F82736VLF, MC56F82733VLC,
MC56F82733VFM, MC56F82733MFM,
MC56F82728VLH, MC56F82726VLF,
MC56F82723VLC, MC56F82723VFM
Features
• This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. On a single chip,
each device combines the processing power of a DSP
and the functionality of an MCU, with a flexible set of
peripherals to support many target applications:
– Industrial control
– Home appliances
– Smart sensors
– Wireless charging
– Switched-mode power supply and power
management
– Power distribution systems
– Motor control (ACIM, BLDC, PMSM, SR, stepper)
– Photovoltaic systems
– Circuit breaker
– Medical device/equipment
– Instrumentation
– Uninterruptible power supplies (UPS)
– Lighting
• Analog
– Two high-speed, 8-channel, 12-bit ADCs with
dynamic x1, x2, and x4 programmable amplifier
– Four analog comparators with integrated 6-bit DAC
references
– Up to two 12-bit digital-to-analog converters (DAC)
• One eFlexPWM module with up to 8 PWM outputs,
including 8 channels with high resolution NanoEdge
placement
• Communication interfaces
– Up to two high-speed queued SCI (QSCI) modules
with LIN slave functionality
– Up to two queued SPI (QSPI) modules
– One I2C/SMBus port
– One Modular/Scalable Controller Area Network
(MSCAN) module
• Timers
– One 16-bit quad timer (1 x 4 16-bit timer)
– Two Periodic Interval Timers (PITs)
• DSC based on 32-bit 56800EX core
– Up to 100 MIPS at 100 MHz core frequency in fast
mode
– DSP and MCU functionality in a unified, C-efficient
architecture
• Security and integrity
– Cyclic Redundancy Check (CRC) generator
– Windowed Computer operating properly (COP)
watchdog
– External Watchdog Monitor (EWM)
• On-chip memory
– Up to 64 KB flash memory
– Up to 8 KB data/program RAM
– On-chip flash memory and RAM can be mapped
into both program and data memory spaces
• Clocks
– Two on-chip relaxation oscillators: 8 MHz (400 kHz
at standby mode) and 200 kHz
– Crystal / resonator oscillator
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• System
– DMA controller
– Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module
– Inter-module crossbar connection
– JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, real-time debugging
• Operating characteristics
– Single supply: 3.0 V to 3.6 V
– 5 V–tolerant I/O (except for RESETB pin which is a 3.3 V pin only)
– Operation ambient temperature: V temperature option: -40°C to 105°C
– Operation ambient temperature: M temperature option: -40°C to 125°C
• 64-pin LQFP, 48-pin LQFP, 32-pin QFN, and 32-pin LQFP packages
MC56F827xx, Rev. 4.1, 11/2018
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NXP Semiconductors
Table of Contents
1
2
3
Overview............................................................................................ 4
6.1
Thermal handling ratings........................................................ 31
1.1
MC56F827xx Product Family.................................................4
6.2
Moisture handling ratings........................................................31
1.2
56800EX 32-bit Digital Signal Controller (DSC) core...........5
6.3
ESD handling ratings.............................................................. 31
1.3
Operation Parameters.............................................................. 6
6.4
Voltage and current operating ratings..................................... 32
1.4
On-Chip Memory and Memory Protection............................. 6
1.5
Interrupt Controller................................................................. 7
7.1
General characteristics............................................................ 34
1.6
Peripheral highlights............................................................... 7
7.2
AC electrical characteristics....................................................34
1.7
Block diagrams........................................................................13
7.3
Nonswitching electrical specifications....................................35
MC56F827xx signal and pin descriptions..........................................16
7.4
Switching specifications..........................................................42
2.1
7.5
Thermal specifications............................................................ 43
4
5
6
Signal groups...........................................................................25
Ordering parts.....................................................................................25
3.1
7
8
General............................................................................................... 34
Peripheral operating requirements and behaviors.............................. 44
Determining valid orderable parts...........................................25
8.1
Core modules...........................................................................44
Part identification............................................................................... 26
8.2
System modules.......................................................................45
4.1
Description.............................................................................. 26
8.3
Clock modules.........................................................................46
4.2
Format..................................................................................... 26
8.4
Memories and memory interfaces........................................... 48
4.3
Fields....................................................................................... 26
8.5
Analog..................................................................................... 50
4.4
Example...................................................................................27
8.6
PWMs and timers.................................................................... 56
Terminology and guidelines...............................................................27
8.7
Communication interfaces.......................................................57
5.1
Definition: Operating requirement.......................................... 27
9
Design Considerations....................................................................... 63
5.2
Definition: Operating behavior............................................... 27
9.1
Thermal design considerations................................................63
5.3
Definition: Attribute................................................................28
9.2
Electrical design considerations.............................................. 65
5.4
Definition: Rating....................................................................28
9.3
Power-on Reset design considerations....................................66
5.5
Result of exceeding a rating.................................................... 28
10 Obtaining package dimensions.......................................................... 68
5.6
Relationship between ratings and operating requirements......29
11 Pinout................................................................................................. 68
5.7
Guidelines for ratings and operating requirements................. 29
11.1 Signal Multiplexing and Pin Assignments.............................. 68
5.8
Definition: Typical value........................................................ 30
11.2 Pinout diagrams.......................................................................71
5.9
Typical value conditions......................................................... 31
12 Product documentation.......................................................................73
Ratings................................................................................................31
13 Revision History.................................................................................74
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3
Overview
1 Overview
1.1 MC56F827xx Product Family
The following table is the comparsion of features among members of the family.
Table 1. MC56F827xx Family
Feature
Part Number1
Core frequency
(MHz)
MC56F82
748V
LH
746V
LF
748M
LH
746M
LF
743V
LC
743V
FM
738V
LH
736V
LF
733V
LC
733V
FM
728V
LH
726V
LF
723V
LC
723V
FM
733M
FM
100/50 100/50 100/50 100/50 100/50 100/50 100/50 100/50 100/50 100/50 100/50 100/50
Flash memory
(KB)
64
64
64
64
48
48
48
48
32
32
32
32
RAM (KB)
8
8
8
8
8
8
8
8
6
6
6
6
Interrupt
Controller
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Windowed
Computer
Operating
Properly (WCOP)
1
1
1
1
1
1
1
1
1
1
1
1
External
Watchdog Monitor
(EWM)
1
1
1
1
1
1
1
1
1
1
1
1
Periodic Interrupt
Timer (PIT)
2
2
2
2
2
2
2
2
2
2
2
2
Cyclic
Redundancy
Check (CRC)
1
1
1
1
1
1
1
1
1
1
1
1
Quad Timer
(TMR)
1x4
1x4
1x4
1x4
1x4
1x4
1x4
1x4
1x4
1x4
1x4
1x4
12-bit Cyclic ADC
channels
2x8
2x5
2x3
2x3
2x8
2x5
2x3
2x3
2x8
2x5
2x3
2x3
Input capture
channels2
12
6
6
6
12
6
6
6
12
6
6
6
High-resolution
channels
8
6
6
6
8
6
6
6
8
6
6
6
Standard
channels
4
0
0
0
4
0
0
0
4
0
0
0
12-bit DAC
2
2
2
2
2
2
2
2
2
2
2
2
DMA
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PWM Module:
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
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Overview
Table 1. MC56F827xx Family (continued)
Feature
MC56F82
Part Number1
748V
LH
746V
LF
743V
LC
743V
FM
738V
LH
736V
LF
733V
LC
748M
LH
746M
LF
Analog
Comparators
(CMP)
4
4
3
3
4
4
3
QSCI
2
2
1
1
2
2
QSPI
2
1
1
1
2
I2C/SMBus
1
1
1
1
MSCAN
1
1
0
GPIO
54
39
Package pin
count
64
LQFP
AEC-Q1003
Yes
733V
FM
728V
LH
726V
LF
723V
LC
723V
FM
3
4
4
3
3
1
1
2
2
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
26
26
54
39
26
26
54
39
26
26
48
LQFP
32
LQFP
32
QFN
64
LQFP
48
LQFP
32
LQFP
32
QFN
64
LQFP
48
LQFP
32
LQFP
32
QFN
Yes
No
No
Yes
Yes
No
No
Yes
Yes
No
No
733M
FM
1. Temperature options
V: -40°C to 105°C
M: -40°C to 125°C
2. Input capture shares the pin with cooresponding PWM channels.
3. Qualification aligned to AEC-Q100
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
• As many as 100 million instructions per second (MIPS) at 100 MHz core frequency
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Four 36-bit accumulators, including extension bits
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Overview
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
• Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions enable compact code
• Enhanced bit manipulation instruction set
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack, with the stack's depth limited only by
memory
• Priority level setting for interrupt levels
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation Parameters
• Up to 50 MHz operation in normal mode and 100 MHz operation in fast mode
• Operation ambient temperature:
V Temperature option:-40 oC to 105oC
M Temperature option:-40 oC to 125oC
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 On-Chip Memory and Memory Protection
• Dual Harvard architecture permits as many as three simultaneous accesses to
program and data memory
• Internal flash memory with security and protection to prevent unauthorized access
• Memory resource protection (MRP) unit to protect supervisor programs and
resources from user programs
• Programming code can reside in flash memory during flash programming
• The dual-port RAM controller supports concurrent instruction fetches and data
accesses, or dual data accesses by the core.
• Concurrent accesses provide increased performance.
• The data and instruction arrive at the core in the same cycle, reducing latency.
• On-chip memory
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Peripheral highlights
• Up to 64 KB program/data flash memory
• Up to8 KB dual port data/program RAM
1.5 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
1.6 Peripheral highlights
1.6.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
• PWM outputs can be configured as complementary output pairs or independent
outputs
• Dedicated time-base counter with period and frequency control per submodule
• Independent top and bottom deadtime insertion for each complementary pair
• Independent control of both edges of each PWM output
• Enhanced input capture and output compare functionality on each input:
• Channels not used for PWM generation can be used for buffered output compare
functions.
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Peripheral highlights
•
•
•
•
•
•
•
•
•
•
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
Synchronization of submodule to external hardware (or other PWM) is supported.
Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
Multiple output trigger events can be generated per PWM cycle via hardware.
Support for double-switching PWM outputs
Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
Independently programmable PWM output polarity
Individual software control of each PWM output
All outputs can be programmed to change simultaneously via a FORCE_OUT event.
PWMX pin can optionally output a third PWM signal from each submodule
Option to supply the source for each complementary PWM signal pair from any of
the following:
• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit
registers
1.6.2 12-bit Analog-to-Digital Converter (Cyclic type)
• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 8-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
• Maximum ADC clock frequency up to 10 MHz, having period as low as 100-ns
• Single conversion time of 10 ADC clock cycles
• Additional conversion time of 8 ADC clock cycles
• Support of analog inputs for single-ended and differential, including unipolar
differential, conversions
• Sequential, parallel, and independent scan mode
• First 8 samples have offset, limit and zero-crossing calculation supported
• ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for simultaneous triggering and software-triggering conversions
• Support for a multi-triggering mode with a programmable number of conversions on
each trigger
• Each ADC has ability to scan and store up to 8 conversion results.
• Current injection protection
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Peripheral highlights
1.6.3 Periodic Interrupt Timer (PIT) Modules
• 16-bit counter with programmable count modulo
• PIT0 is master and PIT1 is slave (if synchronizing both PITs)
• The output signals of both PIT0 and PIT1 are internally connected to a peripheral
crossbar module
• Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from
Wait/Stop modes.
• In addition to its existing bus clock (up to 50 MHz), 3 alternate clock sources for the
counter clock are available:
• Crystal oscillator output
• 8 MHz / 400 kHz ROSC (relaxation oscillator output)
• On-chip low-power 200 kHz oscillator
1.6.4 Inter-Module Crossbar and AND-OR-INVERT logic
• Provides generalized connections between and among on-chip peripherals: ADCs,
12-bit DAC, comparators, quad-timers, eFlexPWMs, EWM, and select I/O pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
• Write-once protection for all registers
• AND-OR-INVERT function provides a universal Boolean function generator that
uses a four-term sum-of-products expression, with each product term containing true
or complement values of the four selected inputs (A, B, C, D).
1.6.5 Comparator
•
•
•
•
•
•
•
Full rail-to-rail comparison range
Support for high and low speed modes
Selectable input source includes external pins and internal DACs
Programmable output polarity
6-bit programmable DAC as a voltage reference per comparator
Three programmable hysteresis levels
Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
1.6.6 12-bit Digital-to-Analog Converter
• 12-bit resolution
• Powerdown mode
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Peripheral highlights
• Automatic mode allows the DAC to automatically generate pre-programmed output
waveforms, including square, triangle, and sawtooth waveforms (for applications like
slope compensation)
• Programmable period, update rate, and range
• Output can be routed to an internal comparator, ADC, or optionally to an off-chip
destination
1.6.7 Quad Timer
• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters
• Up to 100 MHz operation clock
1.6.8 Queued Serial Communications Interface (QSCI) modules
•
•
•
•
•
•
•
•
Operating clock can be up to two times the CPU operating frequency
Four-word-deep FIFOs available on both transmit and receive buffers
Standard mark/space non-return-to-zero (NRZ) format
16-bit integer and 3-bit fractional baud rate selection
Full-duplex or single-wire operation
Programmable 8-bit or 9-bit data format
Error detection capability
Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
• Up to 6.25 Mbit/s baud rate at 100 MHz operation clock
1.6.9 Queued Serial Peripheral Interface (QSPI) modules
•
•
•
•
•
•
•
Maximum 12.5 Mbit/s baud rate
Selectable baud rate clock sources for low baud rate communication
Baud rate as low as Baudrate_Freq_in / 8192
Full-duplex operation
Master and slave modes
Double-buffered operation with separate transmit and receive registers
Four-word-deep FIFOs available on transmit and receive buffers
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Peripheral highlights
• Programmable length transmissions (2 bits to 16 bits)
• Programmable transmit and receive shift order (MSB as first bit transmitted)
1.6.10 Inter-Integrated Circuit (I2C)/System Management Bus
(SMBus) modules
•
•
•
•
•
•
•
•
Compatible with I2C bus standard
Support for System Management Bus (SMBus) specification, version 2
Multi-master operation
General call recognition
10-bit address extension
Start/Repeat and Stop indication flags
Support for dual slave addresses or configuration of a range of slave addresses
Programmable glitch input filter with option to clock up to 100 MHz
1.6.11 Modular/Scalable Controller Area Network (MSCAN) Module
•
•
•
•
•
•
•
•
•
•
•
Clock source from PLL or oscillator.
Implementation of the CAN protocol Version 2.0 A/B
Standard and extended data frames
0-to-8 bytes data length
Programmable bit rate up to 1 Mbit/s
Support for remote frames
Individual Rx Mask Registers per Message Buffer
Internal timer for time-stamping of received and transmitted messages
Listen-only mode capability
Programmable loopback mode supporting self-test operation
Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Low power modes, with programmable wakeup on bus activity
1.6.12 Windowed Computer Operating Properly (COP) watchdog
• Programmable windowed timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator/external clock source
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Peripheral highlights
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 50 MHz)
• 8 MHz / 400 kHz ROSC
• Support for interrupt triggered when the counter reaches the timeout value
1.6.13 External Watchdog Monitor (EWM)
•
•
•
•
Monitors external circuit as well as the software flow
Programmable timeout period
Interrupt capability prior to timeout
Independent output (EWM_OUT_b) that places external circuit (but not CPU and
peripheral) in a safe mode when EWM timeout occurs
• Selectable reference clock source in support of EN60730 and IEC61508
• Wait mode and Stop mode operation is not supported.
• Selectable clock sources:
• External crystal oscillator/external clock source
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 50 MHz)
• 8 MHz / 400 kHz ROSC
1.6.14 Power supervisor
• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;
CPU, peripherals, and JTAG/EOnCE controllers exit RESET state
• Brownout reset (VDD < 2.0 V)
• Critical warn low-voltage interrupt (LVI 2.2 V)
• Peripheral low-voltage warning interrupt (LVI 2.7 V)
1.6.15 Phase-locked loop
•
•
•
•
Wide programmable output frequency: 200 MHz to 400 MHz
Input reference clock frequency: 8 MHz to 16 MHz
Detection of loss of lock and loss of reference clock
Ability to power down
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Clock sources
1.6.16 Clock sources
1.6.16.1 On-chip oscillators
• Tunable 8 MHz relaxation oscillator with 400 kHz at standby mode (divide-by-two
output)
• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT
1.6.16.2 Crystal oscillator
• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz
1.6.17 Cyclic Redundancy Check (CRC) Generator
•
•
•
•
•
•
Hardware CRC generator circuit with 16-bit shift register
High-speed hardware CRC calculation
Programmable initial seed value
CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
Error detection for all single, double, odd, and most multibit errors
Option to transpose input data or output data (CRC result) bitwise, which is required
for certain CRC standards
1.6.18 General Purpose I/O (GPIO)
•
•
•
•
•
•
•
5 V tolerance (except RESETB pin)
Individual control of peripheral mode or GPIO mode for each pin
Programmable push-pull or open drain output
Configurable pullup or pulldown on all input pins
All pins (except JTAG and RESETB) default to be GPIO inputs
2 mA / 9 mA source/sink capability
Controllable output slew rate
1.7 Block diagrams
The 56800EX core is based on a modified dual Harvard-style architecture, consisting of
three execution units operating in parallel, and allowing as many as six operations per
instruction cycle. The MCU-style programming model and optimized instruction set
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13
Clock sources
enable straightforward generation of efficient and compact code for the DSP and control
functions. The instruction set is also efficient for C compilers, to enable rapid
development of optimized control applications.
The device's basic architecture appears in Figure 1 and Figure 2. Figure 1 shows how the
56800EX system buses communicate with internal memories, and the IPBus interface
and the internal connections among the units of the 56800EX core. Figure 2 shows the
peripherals and control blocks connected to the IPBus bridge. See the specific device’s
Reference Manual for details.
DSP56800EX Core
Program Control Unit
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
LC
LC2
FISR
Address
Generation
Unit
(AGU)
Instruction
Decoder
Interrupt
Unit
ALU1
ALU2
R0
R1
R2
R2
R3
R3
R4
R4
R5
R5
N
M01
N3
Looping
Unit
Program
Memory
SP
XAB1
XAB2
PAB
PDB
Data/
Program
RAM
CDBW
CDBR
XDB2
A2
B2
C2
D2
BitManipulation
Unit
Enhanced
OnCE™
JTAG TAP
Y
A1
B1
C1
D1
Y1
Y0
X0
MAC and ALU
A0
B0
C0
D0
IPBus
Interface
Data
Arithmetic
Logic Unit
(ALU)
Multi-Bit Shifter
Figure 1. 56800EX basic block diagram
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Clock sources
56800EX CPU
Address
Generation
Unit (AGU)
Bit
Manipulation
Unit
Arithmetic
Logic Unit
(ALU)
Crystal OSC
CRC
Clock MUX
Internal
8 MHz
Internal
200 kHz
PLL
Core Data Bus
Secondary Data Bus
Platform Bus
Crossbar Swirch
Program
Controller
(PC)
Program Bus
Memory Resource
Protection Unit
4
EOnCE
Flash Controller
and Cache
JTAG
Program/Data Flash
Up to 64KB
Data/Program RAM
Up to 8KB
DMA Controller
Interrupt Controller
Windowed
Watchdog (WCOP)
Power Management
Controller (PMC)
Periodic Interrupt
Timer (PIT) 0, 1
System Integration
Module (SIM)
Peripheral Bus
MSCAN
I2C
0
QSPI
0,1
QSCI
0,1
eFlexPWM
NanoEdge
Quad Timer
EWM
Package
Pins
ADC A ADC B
12bit 12bit
DACB
12bit
Comparators with
6bit DAC A,B,C,D
Inter Module Crossbar Inputs
GPIO & Peripheral MUX
Inter-Module
Crossbar B
AND-OR-INV
Logic
Peripheral Bus
Inter Module Crossbar Outputs
Inter Module connection
Inter-Module
Crossbar A
DACA
12bit
Peripheral Bus
Figure 2. System diagram
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
15
MC56F827xx signal and pin descriptions
2 MC56F827xx signal and pin descriptions
After reset, each pin is configured for its primary function (listed first). Any alternative
functionality, shown in parentheses, must be programmed through the GPIO module
peripheral enable registers (GPIOx_PER) and the SIM module GPIO peripheral select
(GPSx) registers. All GPIO ports can be individually programmed as an input or output
(using bit manipulation).
• PWMA_FAULT0, PWMA_FAULT1, and similar signals are inputs used to disable
selected PWMA outputs, in cases where the fault conditions originate off-chip.
For the MC56F827xx products, which use 64-pin LQFP, 48-pin LQFP and 32-pin
packages:
Table 2. Signal descriptions
Signal Name
VDD
64 LQFP 48 LQFP 32 LQFP
29
—
—
44
32
—
60
44
28
30
22
14
43
31
—
61
45
29
VDDA
22
15
VSSA
23
VCAP
VSS
Type
State During
Reset
Signal Description
Supply
Supply
I/O Power — Supplies 3.3 V power to
the chip I/O interface.
Supply
Supply
I/O Ground — Provide ground for the
device I/O interface.
9
Supply
Supply
Analog Power — Supplies 3.3 V power
to the analog modules. It must be
connected to a clean analog power
supply.
16
10
Supply
Supply
Analog Ground — Supplies an analog
ground to the analog modules. It must
be connected to a clean power supply.
26
19
—
57
43
27
On-chip
regulator
output
On-chip
regulator
output
Connect a 2.2 µF bypass capacitor
between this pin and VSS to stabilize the
core voltage regulator output required for
proper device operation.
NOTE: The total bypass capacitor
value between all VCAP pin and
VSS should not exceed 4.7 µF.
TDI
64
48
32
(GPIOD0)
TDO
Input
Input, internal Test Data Input — It is sampled on the
pullup enabled rising edge of TCK and has an internal
pullup resistor. After reset, the default
state is TDI.
Input/Output
62
46
30
Output
GPIO Port D0
Output
Test Data Output — It is driven in the
shift-IR and shift-DR controller states,
and it changes on the falling edge of
TCK. After reset, the default state is
TDO
Table continues on the next page...
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16
NXP Semiconductors
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
(GPIOD1)
TCK
1
1
1
(GPIOD2)
TMS
Type
State During
Reset
Input/Output Output
GPIO Port D1
Input
Test Clock Input — The pin is connected
internally to a pulldown resistor. A
Schmitt-trigger input is used for noise
immunity. After reset, the default state is
TCK
Input, internal
pulldown
enabled
Input/Output
63
47
31
Signal Description
Input
GPIO Port D2
Input, internal Test Mode Select Input — It is sampled
pullup enabled on the rising edge of TCK and has an
internal pullup resistor. After reset, the
default state is TMS.
NOTE: Always tie the TMS pin to VDD
through a 2.2 kΩ resistor if need
to keep on-board debug
capability. Otherwise, directly
tie to VDD.
(GPIOD3)
RESET or
RESETB
Input/Output
2
2
2
(GPIOD4)
Input
GPIO Port D3
Input, internal Reset — A direct hardware reset on the
pullup enabled processor. When RESET is asserted
low, the device is initialized and placed
in the reset state. A Schmitt-trigger input
is used for noise immunity. The internal
reset signal is deasserted synchronous
with the internal clocks after a fixed
number of internal clocks. After reset,
the default state is RESET.
Recommended a capacitor of up to 0.1
µF for filtering noise.
Input/
Opendrain
Output
GPIO Port D4 RESET functionality is
disabled in this mode and the device can
be reset only through POR, COP reset,
or software reset.
Input/Output Input
GPIO Port A0
(ANA0&CMPA_IN
3)
Input
ANA0 is analog input to channel 0 of
ADCA; CMPA_IN3 is positive input 3 of
analog comparator A. After reset, the
default state is GPIOA0.
(CMPC_O)
Output
Analog comparator C output
Input/Output Input
GPIO Port A1: After reset, the default
state is GPIOA1.
Input
ANA1 is analog input to channel 1 of
ADCA; CMPA_IN0 is negative input 0 of
analog comparator A. When used as an
analog input, the signal goes to ANA1
and CMPA_IN0. The ADC control
register configures this input as ANA1 or
CMPA_IN0.
Input/Output Input
GPIO Port A2: After reset, the default
state is GPIOA2.
GPIOA0
GPIOA1
13
14
9
10
6
7
(ANA1&CMPA_IN
0)
GPIOA2
15
11
8
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NXP Semiconductors
17
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
(ANA2&VREFHA
&CMPA_IN1)
GPIOA3
16
12
—
(ANA3&VREFLA&
CMPA_IN2)
GPIOA4
12
8
—
(ANA4&CMPD_IN
0)
GPIOA5
11
—
—
(ANA5&CMPD_IN
1)
GPIOA6
10
—
—
(ANA6&CMPD_IN
2)
GPIOA7
9
—
—
(ANA7&CMPD_IN
3)
GPIOB0
24
17
11
(ANB0&CMPB_IN
3)
GPIOB1
(ANB1&CMPB_IN
0)
25
18
12
Type
State During
Reset
Signal Description
Input
ANA2 is analog input to channel 2 of
ADCA; VREFHA is analog reference
high of ADCA; CMPA_IN1 is negative
input 1 of analog comparator A. When
used as an analog input, the signal goes
to both ANA2, VREFHA, and
CMPA_IN1.
Input/Output Input
GPIO Port A3: After reset, the default
state is GPIOA3.
Input
ANA3 is analog input to channel 3 of
ADCA; VREFLA is analog reference low
of ADCA; CMPA_IN2 is negative input 2
of analog comparator A.
Input/Output Input
GPIO Port A4: After reset, the default
state is GPIOA4.
Input
ANA4 is Analog input to channel 4 of
ADCA; CMPD_IN0 is input 0 to
comparator D.
Input/Output Input
GPIO Port A5: After reset, the default
state is GPIOA5.
Input
ANA5 is analog input to channel 5 of
ADCA; ANC9 is analog input to channel
9 of ADCC; CMPD_IN1 is negative input
1 of analog comparator D.
Input/Output Input
GPIO Port A6: After reset, the default
state is GPIOA6.
Input
ANA6 is analog input to channel 5 of
ADCA; CMPD_IN2 is negative input 2 of
analog comparator D.
Input/Output Input
GPIO Port A7: After reset, the default
state is GPIOA7.
Input
ANA7 is analog input to channel 7 of
ADCA; CMPD_IN3 is negative input 3 of
analog comparator D.
Input/Output Input
GPIO Port B0: After reset, the default
state is GPIOB0.
Input
ANB0 is analog input to channel 0 of
ADCB; CMPB_IN3 is positive input 3 of
analog comparator B. When used as an
analog input, the signal goes to ANB0
and CMPB_IN3. The ADC control
register configures this input as ANB0.
Input/Output Input
GPIO Port B1: After reset, the default
state is GPIOB1.
Input
ANB1 is analog input to channel 1 of
ADCB; CMPB_IN0 is negative input 0 of
analog comparator B. When used as an
analog input, the signal goes to ANB1
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
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NXP Semiconductors
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
Type
State During
Reset
Signal Description
and CMPB_IN0. The ADC control
register configures this input as ANB1.
DACB_O
Analog
Output
12-bit digital-to-analog output
Input/Output Input
GPIO Port B2: After reset, the default
state is GPIOB2.
Input
ANB2 is analog input to channel 2 of
ADCB; VREFHB is analog reference
high of ADCB; CMPC_IN3 is positive
input 3 of analog comparator C. When
used as an analog input, the signal goes
to both ANB2 and CMPC_IN3.
Input/Output Input
GPIO Port B3: After reset, the default
state is GPIOB3.
Input
ANB3 is analog input to channel 3 of
ADCB; VREFLB is analog reference low
of ADCB; CMPC_IN0 is negative input 0
of analog comparator C.
Input/Output Input
GPIO Port B4: After reset, the default
state is GPIOB4.
Input
ANB4 is analog input to channel 4 of
ADCB; CMPC_IN1 is negative input 1 of
analog comparator C.
Input/Output Input
GPIO Port B5: After reset, the default
state is GPIOB5.
Input
ANB5 is analog input to channel 5 of
ADCB; CMPC_IN2 is negative input 2 of
analog comparator C.
Input/Output Input
GPIO Port B6: After reset, the default
state is GPIOB6.
Input
ANB6 is analog input to channel 6 of
ADCB; CMPB_IN1 is negative input 1 of
analog comparator B.
Input/Output Input
GPIO Port B7: After reset, the default
state is GPIOB7.
Input
ANB7 is analog input to channel 7 of
ADCB; CMPB_IN2 is negative input 2 of
analog comparator B.
Input/Output Input
GPIO Port C0: After reset, the default
state is GPIOC0.
(EXTAL)
Analog Input
The external crystal oscillator input
(EXTAL) connects the internal crystal
oscillator input to an external crystal or
ceramic resonator.
(CLKIN0)
Input
External clock input 01
Input/Output Input
GPIO Port C1: After reset, the default
state is GPIOC1.
GPIOB2
27
20
13
(ANB2&VERFHB
&CMPC_IN3)
GPIOB3
28
21
—
(ANB3&VREFLB&
CMPC_IN0)
GPIOB4
21
14
—
(ANB4&CMPC_IN
1)
GPIOB5
20
—
—
(ANB5&CMPC_IN
2)
GPIOB6
19
—
—
(ANB6&CMPB_IN
1)
GPIOB7
17
—
—
(ANB7&CMPB_IN
2)
GPIOC0
GPIOC1
3
4
3
4
—
—
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
19
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
(XTAL)
Type
State During
Reset
Signal Description
Input
The external crystal oscillator output
(XTAL) connects the internal crystal
oscillator output to an external crystal or
ceramic resonator.
Input/Output Input
GPIO Port C2: After reset, the default
state is GPIOC2.
(TXD0)
Output
SCI0 transmit data output or transmit/
receive in single wire operation
(XB_OUT11)
Output
Crossbar module output 11
(XB_IN2)
Input
Crossbar module input 2
(CLKO0)
Output
Buffered clock output 0: the clock source
is selected by clockout select
(CLKOSEL) bits in the clock output
select register (CLKOUT) of the SIM.
Input/Output Input
GPIO Port C3: After reset, the default
state is GPIOC3.
(TA0)
Input/Output
Quad timer module A channel 0 input/
output
(CMPA_O)
Output
Analog comparator A output
(RXD0)
Input
SCI0 receive data input
(CLKIN1)
Input
External clock input 1
Input/Output Input
GPIO Port C4: After reset, the default
state is GPIOC4.
(TA1)
Input/Output
Quad timer module A channel 1 input/
output
(CMPB_O)
Output
Analog comparator B output
(XB_IN6)
Input
Crossbar module input 6
(EWM_OUT_B)
Output
External Watchdog Module output
Input/Output Input
GPIO Port C5: After reset, the default
state is GPIOC5.
(DACA_O)
Analog
Output
12-bit digital-to-analog output
(XB_IN7)
Input
Crossbar module input 7
Input/Output Input
GPIO Port C6: After reset, the default
state is GPIOC6.
(TA2)
Input/Output
Quad timer module A channel 2 input/
output
(XB_IN3)
Input
Crossbar module input 3
(CMP_REF)
Analog Input
Positive input 3 of analog comparator A
and B and C.
(SS0_B)
Input/Output
In slave mode, SS0_B indicates to the
SPI module 0 that the current transfer is
to be received.
GPIOC2
GPIOC3
GPIOC4
GPIOC5
GPIOC6
5
7
8
18
31
5
6
7
13
23
3
4
5
—
15
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
20
NXP Semiconductors
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
GPIOC7
64 LQFP 48 LQFP 32 LQFP
(SS0_B)
Input/Output
In slave mode, SS0_B indicates to the
SPI module 0 that the current transfer is
to be received.
(TXD0)
Output
SCI0 transmit data output or transmit/
receive in single wire operation
(XB_IN8)
Input
Crossbar module input 8
Input/Output Input
GPIO Port C8: After reset, the default
state is GPIOC8.
(MISO0)
Input/Output
Master in/slave out for SPI0 — In master
mode, MISO0 pin is the data input. In
slave mode, MISO0 pin is the data
output. The MISO line of a slave device
is placed in the high-impedance state if
the slave device is not selected.
(RXD0)
Input
SCI0 receive data input
(XB_IN9)
Input
Crossbar module input 9
Output
Crossbar module output 6
Input/Output Input
GPIO Port C9: After reset, the default
state is GPIOC9.
(SCLK0)
Input/Output
SPI0 serial clock. In master mode,
SCLK0 pin is an output, clocking slaved
listeners. In slave mode, SCLK0 pin is
the data clock input.
(XB_IN4)
Input
Crossbar module input 4
(TXD0)
Output
SCI0 transmit data output or transmit/
receive in single wire operation
(XB_OUT8)
Output
Crossbar module output 8
Input/Output Input
GPIO Port C10: After reset, the default
state is GPIOC10.
(MOSI0)
Input/Output
Master out/slave in for SPI0 — In master
mode, MOSI0 pin is the data output. In
slave mode, MOSI0 pin is the data input.
(XB_IN5)
Input
Crossbar module input 4
(MISO0)
Input/Output
Master in/slave out for SPI0 — In master
mode, MISO0 pin is the data input. In
slave mode, MISO0 pin is the data
output. The MISO line of a slave device
is placed in the high-impedance state if
the slave device is not selected.
(XB_OUT9)
Output
Crossbar module output 9
Input/Output Input
GPIO Port C11: After reset, the default
state is GPIOC11.
Open-drain
Output
CAN transmit data output
25
—
Signal Description
GPIO Port C7: After reset, the default
state is GPIOC7.
33
24
State During
Reset
Input/Output Input
GPIOC8
32
Type
16
(XB_OUT6)
GPIOC9
GPIOC10
GPIOC11
34
35
37
(CANTX)
26
27
29
17
18
—
Table continues on the next page...
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NXP Semiconductors
21
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
Type
State During
Reset
Signal Description
(SCL0)
Input/Opendrain Output
I2C0 serial clock
(TXD1)
Output
SCI1 transmit data output or transmit/
receive in single wire operation
Input/Output Input
GPIO Port C12: After reset, the default
state is GPIOC12.
(CANRX)
Input
CAN receive data input
(SDA0)
Input/Opendrain Output
I2C0 serial data line
(RXD1)
Input
SCI1 receive data input
Input/Output Input
GPIO Port C13: After reset, the default
state is GPIOC13.
(TA3)
Input/Output
Quad timer module A channel 3 input/
output
(XB_IN6)
Input
Crossbar module input 6
(EWM_OUT_B)
Output
External Watchdog Module output
Input/Output Input
GPIO Port C14: After reset, the default
state is GPIOC14.
(SDA0)
Input/
Opendrain
Output
I2C0 serial data line
(XB_OUT4)
Output
Crossbar module output 4
(PWM_FAULT4)
Input
Disable PWMA output 4
Input/Output Input
GPIO Port C15: After reset, the default
state is GPIOC15.
(SCL0)
Input/Opendrain Output
I2C0 serial clock
(XB_OUT5)
Output
Crossbar module output 5
(PWM_FAULT5)
Input
Disable PWMA output 5
Input/Output Input
GPIO Port E0: After reset, the default
state is GPIOE0.
Input/Output
PWM module A (NanoEdge), submodule
0, output B or input capture B
Input/Output Input
GPIO Port E1: After reset, the default
state is GPIOE1.
Input/Output
PWM module A (NanoEdge), submodule
0, output A or input capture A
Input/Output Input
GPIO Port E2: After reset, the default
state is GPIOE2.
Input/Output
PWM module A (NanoEdge), submodule
1, output B or input capture B
Input/Output Input
GPIO Port E3: After reset, the default
state is GPIOE3.
GPIOC12
GPIOC13
GPIOC14
GPIOC15
GPIOE0
38
49
55
56
45
30
37
41
42
33
—
—
—
—
21
(PWM_0B)
GPIOE1
46
34
22
(PWM_0A)
GPIOE2
47
35
23
(PWMA_1B)
GPIOE3
48
36
24
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
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NXP Semiconductors
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
(PWMA_1A)
Type
State During
Reset
Signal Description
Input/Output
PWM module A (NanoEdge), submodule
1, output A or input capture A
Input/Output Input
GPIO Port E4: After reset, the default
state is GPIOE4.
(PWMA_2B)
Input/Output
PWM module A (NanoEdge), submodule
2, output B or input capture B
(XB_IN2)
Input
Crossbar module input 2
Input/Output Input
GPIO Port E5: After reset, the default
state is GPIOE5.
(PWMA_2A)
Input/Output
PWM module A (NanoEdge), submodule
2, output A or input capture A
(XB_IN3)
Input
Crossbar module input 3
Input/Output Input
GPIO Port E6: After reset, the default
state is GPIOE6.
(PWMA_3B)
Input/Output
PWM module A (NanoEdge), submodule
3, output B or input capture B
(XB_IN4)
Input
Crossbar module input 4
Input/Output Input
GPIO Port E7: After reset, the default
state is GPIOE7.
(PWMA_3A)
Input/Output
PWM module A (NanoEdge), submodule
3, output A or input capture A
(XB_IN5)
Input
Crossbar module input 5
Input/Output Input
GPIO Port F0: After reset, the default
state is GPIOF0.
(XB_IN6)
Input
Crossbar module input 6
(SCLK1)
Input/Output
SPI1 serial clock — In master mode,
SCLK1 pin is an output, clocking slaved
listeners. In slave mode, SCLK1 pin is
the data clock input 0.
Input/Output Input
GPIO Port F1: After reset, the default
state is GPIOF1.
(CLKO1)
Output
Buffered clock output 1: the clock source
is selected by clockout select
(CLKOSEL) bits in the clock output
select register (CLKOUT) of the SIM.
(XB_IN7)
Input
Crossbar module input 7
(CMPD_O)
Output
Analog comparator D output
Input/Output Input
GPIO Port F2: After reset, the default
state is GPIOF2.
(SCL0)
Input/Opendrain Output
I2C0 serial clock
(XB_OUT6)
Output
Crossbar module output 6
(MISO1)
Input/Output
Master in/slave out for SPI1 —In master
mode, MISO1 pin is the data input. In
slave mode, MISO1 pin is the data
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOF0
GPIOF1
GPIOF2
51
52
53
54
36
50
39
39
40
—
—
28
38
—
25
26
—
—
—
—
19
Table continues on the next page...
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NXP Semiconductors
23
MC56F827xx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
Type
State During
Reset
Signal Description
output. The MISO line of a slave device
is placed in the high-impedance state if
the slave device is not selected.
GPIOF3
Input/Output Input
GPIO Port F3: After reset, the default
state is GPIOF3.
(SDA0)
Input/Opendrain Output
I2C0 serial data line
(XB_OUT7)
Output
Crossbar module output 7
(MOSI1)
Input/Output
Master out/slave in for SPI1— In master
mode, MOSI1 pin is the data output. In
slave mode, MOSI1 pin is the data input.
Input/Output Input
GPIO Port F4: After reset, the default
state is GPIOF4.
(TXD1)
Output
SCI1 transmit data output or transmit/
receive in single wire operation
(XB_OUT8)
Output
Crossbar module output 8
(PWMA_0X)
Input/Output
PWM module A (NanoEdge), submodule
0, output X or input capture X
(PWMA_FAULT6)
Input
Disable PWMA output 6
Input/Output Input
GPIO Port F5: After reset, the default
state is GPIOF5.
(RXD1)
Input
SCI1 receive data input
(XB_OUT9)
Output
Crossbar module output 9
(PWMA_1X)
Input/Output
PWM module A (NanoEdge), submodule
1, output X or input capture X
(PWMA_FAULT7)
Input
Disable PWMA output 7
Input/Output Input
GPIO Port F6: After reset, the default
state is GPIOF6.
(PWMA_3X)
Input/Output
PWM module A (NanoEdge), submodule
3, output X or input capture X
(XB_IN2)
Input
Crossbar module input 2
Input/Output Input
GPIO Port F7: After reset, the default
state is GPIOF7.
(CMPC_O)
Output
Analog comparator C output
(SS1_B)
Input/Output
In slave mode, SS1_B indicates to the
SPI1 module that the current transfer is
to be received.
(XB_IN3)
Input
Crossbar module input 3
Input/Output Input
GPIO Port F8: After reset, the default
state is GPIOF8.
(RXD0)
Input
SCI0 receive data input
(XB_OUT10)
Output
Crossbar module output 10
(CMPD_O)
Output
Analog comparator D output
GPIOF4
GPIOF5
GPIOF6
GPIOF7
GPIOF8
40
41
42
58
59
6
—
—
—
—
—
—
20
—
—
—
—
—
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
24
NXP Semiconductors
Ordering parts
Table 2. Signal descriptions (continued)
Signal Name
64 LQFP 48 LQFP 32 LQFP
Type
State During
Reset
(PWMA_2X)
Signal Description
PWM module A (NanoEdge), submodule
2, output X or input capture X
1. If CLKIN is selected as the device’s external clock input, then both the GPS_C0 bit (in GPS1) and the EXT_SEL bit (in
OCCS oscillator control register (OSCTL)) must be set. Also, the crystal oscillator should be powered down.
2.1 Signal groups
The input and output signals of the MC56F827xx are organized into functional groups, as
detailed in the following table.
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins
32QFN
32LQFP
48LQFP
64LQFP
Power Inputs (VDD, VDDA), Power output( VCAP)
3
3
5
6
Ground (VSS, VSSA)
3
3
4
4
Reset
1
1
1
1
eFlexPWM with NanoEdge ports not including fault pins (for 56F827xx)
6
6
6
8
eFlexPWM without NanoEdge ports not including fault pins
0
0
0
4
Queued Serial Peripheral Interface (QSPI0 and QSPI1) ports
4
4
5
9
Queued Serial Communications Interface (QSCI0 and QSCI1) ports
4
4
7
10
Inter-Integrated Circuit Interface (I2C0) ports
2
2
4
6
12-bit Analog-to-Digital Converter inputs
6
6
10
16
Analog Comparator inputs/outputs
7/3
7/3
11/4
17/5
12-bit Digital-to-Analog output
2
2
2
2
Quad Timer Module (TMRA and TMRB) ports
3
3
4
4
Controller Area Network (MSCAN)
0
0
2
2
Inter-Module Crossbar inputs/outputs
8/4
8/4
12/6
17/11
Clock inputs/outputs
1/1
1/1
2/2
2/2
JTAG / Enhanced On-Chip Emulation (EOnCE)
4
4
4
4
3 Ordering parts
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25
Part identification
3.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MC56F82
4 Part identification
4.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
4.2 Format
Part numbers for this device have the following format: Q 56F8 2 C F P T PP N
4.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• MC = Fully qualified, general market flow
• PC = Prequalification
56F8
DSC family with flash memory and DSP56800/
DSP56800E/DSP56800EX core
• 56F8
2
DSC subfamily
• 2
C
Maximum CPU frequency (MHz)
• 7 = 100 MHz
F
Primary program flash memory size
•
•
•
•
P
Pin count
• 3 = 32
• 6 = 48
• 8 = 64
T
Temperature range (°C)
• V = –40 to 105
• M = –40 to 125
PP
Package identifier
• LC = 32LQFP
• FM = 32QFN
1 = 16 KB
2 = 32 KB
3 = 48 KB
4 = 64 KB
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
26
NXP Semiconductors
Terminology and guidelines
Field
Description
Values
• LF = 48LQFP
• LH = 64LQFP
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
4.4 Example
This is an example part number: MC56F82748VLH
5 Terminology and guidelines
5.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
5.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
5.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
5.2.1 Example
This is an example of an operating behavior:
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27
Terminology and guidelines
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
5.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
5.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
5.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
5.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
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Terminology and guidelines
5.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
5.6 Relationship between ratings and operating requirements
O
ra
pe
tin
gr
(
ing
at
)
in.
m
ra
pe
e
gr
tin
em
ir
qu
t
en
)
in.
(m
O
gr
tin
O
ra
pe
em
e
ir
qu
t
en
(m
ax
.)
at
gr
tin
O
ra
pe
x.)
ma
(
ing
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
ng
dli
n
Ha
r
ng
ati
)
in.
(m
ng
dli
n
Ha
ng
ati
.)
ax
(m
r
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
Handling (power off)
∞
5.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
MC56F827xx, Rev. 4.1, 11/2018
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29
Terminology and guidelines
5.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
5.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
5.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
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Ratings
5.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
6 Ratings
6.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
6.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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31
Ratings
6.3 ESD handling ratings
Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification. During the
device qualification ESD stresses were performed for the human body model (HBM), the
machine model (MM), and the charge device model (CDM).
All latch-up testing is in conformity with AEC-Q100 Stress Test Qualification.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 4. ESD/Latch-up Protection
Characteristic1
Min
Max
Unit
ESD for Human Body Model (HBM)
–2000
+2000
V
ESD for Machine Model (MM)
–200
+200
V
ESD for Charge Device Model (CDM)
–500
+500
V
Latch-up current at TA= 85°C (ILAT)
–100
+100
mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
6.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device
reliability or cause permanent damage to the device.
NOTE
If the voltage difference between VDD and VDDA or VSS and
VSSA is too large, then the device can malfunction or be
permanently damaged. The restrictions are:
• At all times, it is recommended that the voltage
difference of VDD - VSS be within +/-200 mV of the
voltage difference of VDDA - VSSA, including power
ramp up and ramp down; see additional requirements in
Table 6. Failure to do this recommendation may result in a
MC56F827xx, Rev. 4.1, 11/2018
32
NXP Semiconductors
Ratings
harmful leakage current through the substrate, between the
VDD/VSS and VDDA/VSSA pad cells. This harmful
leakage current could prevent the device from operating
after power up.
• At all times, to avoid permanent damage to the part, the
voltage difference between VDD and VDDA must
absolutely be limited to 0.3 V; see Table 5.
• At all times, to avoid permanent damage to the part, the
voltage difference between VSS and VSSA must
absolutely be limited to 0.3 V; see Table 5.
Table 5. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Symbol
Notes1
Min
Max
Unit
Supply Voltage Range
VDD
-0.3
4.0
V
Analog Supply Voltage Range
VDDA
-0.3
4.0
V
ADC High Voltage Reference
VREFHx
-0.3
4.0
V
Voltage difference VDD to VDDA
ΔVDD
-0.3
0.3
V
Voltage difference VSS to VSSA
ΔVSS
-0.3
0.3
V
Digital Input Voltage Range
VIN
Pin Group 1
-0.3
5.5
V
RESET Input Voltage Range
VIN_RESET
Pin Group 2
-0.3
4.0
V
VOSC
Pin Group 4
-0.4
4.0
V
VINA
Pin Group 3
-0.3
4.0
V
Oscillator Input Voltage Range
Analog Input Voltage Range
Input clamp current, per pin (VIN < VSS - 0.3
V), 2, 3
VIC
—
-5.0
mA
pin4
VOC
—
±20.0
mA
Contiguous pin DC injection current—regional limit sum
of 16 contiguous pins
IICont
-25
25
mA
Output Voltage Range (normal push-pull mode)
VOUT
Pin Group 1, 2
-0.3
4.0
V
VOUTOD
Pin Group 1
-0.3
5.5
V
VOUTOD_RE
Pin Group 2
-0.3
4.0
V
VOUT_DAC
Pin Group 5
-0.3
4.0
V
TA
V temperature
-40
105
°C
-40
125
-40
115
°C
-40
135
°C
-55
150
°C
Output clamp current, per
Output Voltage Range (open drain mode)
RESET Output Voltage Range
SET
DAC Output Voltage Range
Ambient Temperature
M temperature
Junction Temperature
Tj
V temperature
M temperature
Storage Temperature Range (Extended Industrial)
TSTG
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Continuous clamp current
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33
General
3. All 5 volt tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode
connection to VDD. If VIN greater than VDIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current
limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required.
4. I/O is configured as push-pull mode.
7 General
7.1 General characteristics
The device is fabricated in high-density, low-power CMOS with 5 V–tolerant TTLcompatible digital inputs, except for the RESET pin which is 3.3V only. The term “5 V–
tolerant” refers to the capability of an I/O pin, built on a 3.3 V–compatible process
technology, to withstand a voltage up to 5.5 V without damaging the device.
5 V–tolerant I/O is desirable because many systems have a mixture of devices designed
for 3.3 V and 5 V power supplies. In such systems, a bus may carry both 3.3 V– and 5 V–
compatible I/O voltage levels (a standard 3.3 V I/O is designed to receive a maximum
voltage of 3.3 V ± 10% during normal operation without causing damage). This 5 V–
tolerant capability therefore offers the power savings of 3.3 V I/O levels combined with
the ability to receive 5 V levels without damage.
Absolute maximum ratings in Table 5 are stress ratings only, and functional operation at
the maximum is not guaranteed. Stress beyond these ratings may affect device reliability
or cause permanent damage to the device.
Unless otherwise stated, all specifications within this chapter apply to the temperature
range specified in Table 5 over the following supply ranges: VSS=VSSA=0V,
VDD=VDDA=3.0V to 3.6V, CL≤50 pF, fOP=50MHz.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
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NXP Semiconductors
General
7.2 AC electrical characteristics
Tests are conducted using the input levels specified in Table 8. Unless otherwise
specified, propagation delays are measured from the 50% to the 50% point, and rise and
fall times are measured between the 10% and 90% points, as shown in Figure 3.
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH – VIL)/2.
Figure 3. Input signal measurement references
Figure 4 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid
Data2 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 4. Signal states
7.3 Nonswitching electrical specifications
7.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is less than 200 ms.
Table 6. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Characteristic
Supply voltage
Symbol
Notes1
VDD, VDDA
Min
Typ
Max
Unit
2.7
3.3
3.6
V
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
35
General
Table 6. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V) (continued)
Characteristic
ADC (Cyclic) Reference Voltage High
Notes1
Symbol
Min
VREFHA
Typ
VDDA-0.6
Max
Unit
VDDA
V
VREFHB
Voltage difference VDD to VDDA
ΔVDD
-0.1
0
0.1
V
Voltage difference VSS to VSSA
ΔVSS
-0.1
0
0.1
V
5.5
V
VDD
V
0.35 x VDD
V
Input Voltage High (digital inputs)
RESET Voltage High
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
VIH
Pin Group 1
0.7 x VDD
VIH_RESET
Pin Group 2
0.7 x VDD
VIL
Pin Groups 1, 2
VIHOSC
Pin Group 4
2.0
VDD + 0.3
V
VILOSC
Pin Group 4
-0.3
0.8
V
IOH
Pin Group 1
—
-2
mA
Pin Group 1
—
-9
Pin Groups 1, 2
—
2
Pin Groups 1, 2
—
9
—
XTAL driven by an external clock source
Oscillator Input Voltage Low
Output Source Current High (at VOH min.)
• Programmed for low drive strength
• Programmed for high drive strength
Output Source Current Low (at VOL max.)2, 3
• Programmed for low drive strength
• Programmed for high drive strength
IOL
mA
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Total IO sink current and total IO source current are limited to 75 mA each
3. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive
injection currents of 16 contiguous pins—is 25 mA.
7.3.2 LVD and POR operating requirements
Table 7. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Characteristic
POR Assert
Symbol
Voltage1
Min
Typ
Max
Unit
POR
2.0
V
POR
2.7
V
LVI_2p7 Threshold Voltage
2.73
V
LVI_2p2 Threshold Voltage
2.23
V
POR Release
Voltage2
1. During 3.3-volt VDD power supply ramp down
2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p7)
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NXP Semiconductors
General
7.3.3 Voltage and current operating behaviors
The following table provides information about power supply requirements and I/O pin
characteristics.
Table 8. DC Electrical Characteristics at Recommended Operating Conditions
Symbol
Notes 1
Min
Typ
Max
Unit
Test Conditions
Output Voltage High
VOH
Pin Group 1
VDD - 0.5
—
—
V
IOH = IOHmax
Output Voltage Low
VOL
Pin Groups
1, 2
—
—
0.5
V
IOL = IOLmax
IIH
Pin Group 1
—
0
+/- 2.5
µA
VIN = 2.4 V to 5.5 V
Characteristic
Digital Input Current High
Pin Group 2
pull-up enabled or
disabled
Comparator Input Current
High
Oscillator Input Current
High
Digital Input Current Low
2, 3
VIN = 2.4 V to VDD
IIHC
Pin Group 3
—
0
+/- 2
µA
VIN = VDDA
IIHOSC
Pin Group 3
—
0
+/- 2
µA
VIN = VDDA
IIL
Pin Groups
1, 2
—
0
+/- 0.5
µA
VIN = 0V
RPull-Up
20
—
50
kΩ
—
RPull-Down
20
—
50
kΩ
—
pull-up disabled
Internal Pull-Up
Resistance
Internal Pull-Down
Resistance
Comparator Input Current
Low
IILC
Pin Group 3
—
0
+/- 2
µA
VIN = 0V
Oscillator Input Current
Low
IILOSC
Pin Group 3
—
0
+/- 2
µA
VIN = 0V
DAC Output Voltage
Range
VDAC
Pin Group 5
Typically
VSSA +
40mV
—
Typically
VDDA 40mV
V
RLD = 3 kΩ || CLD = 400 pF
IOZ
Pin Groups
1, 2
—
0
+/- 1
µA
—
VHYS
Pin Groups
1, 2
0.06 × VDD
—
—
V
—
Output Current 2, 3
High Impedance State
Schmitt Trigger Input
Hysteresis
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC
2. See the following figure "IIN/IOZ vs. VIN (typical; pull-up disabled)" .
3. To minimize the excessive leakage current from digital pin, input signal should not stay between 1.1 V and 0.7 × VDD for
prolonged time.
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NXP Semiconductors
37
General
Figure 5. IIN/IOZ vs. VIN (typical; pull-up disabled) (design simulation)
7.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.
Table 9. Reset, stop, wait, and interrupt timing
Characteristic
Symbol
Typical Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration
tRA
161
—
ns
—
RESET deassertion to First Address Fetch
tRDA
865 x TOSC + 8 x T
ns
—
tIF
361.3
ns
—
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
570.9
1. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns. Recommended a capacitor of up to 0.1 µF on RESET.
NOTE
In Table 9, T = system clock cycle and TOSC = oscillator clock
cycle. For an operating frequency of 50MHz, T=20 ns. At 4
MHz (used coming out of reset and stop modes), T=250 ns.
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NXP Semiconductors
General
Table 10. Power mode transition behavior
Symbol
TPOR
Notes1
Description
Min
Max
Unit
After a POR event, the amount of delay from when VDD reaches
2.7 V to when the first instruction executes (over the operating
temperature range).
199
225
µs
STOP mode to RUN mode
6.79
7.27.31
µs
2
LPS mode to LPRUN mode
240.9
551
µs
3
VLPS mode to VLPRUN mode
1424
1459
µs
4
WAIT mode to RUN mode
0.570
0.620
µs
5
LPWAIT mode to LPRUN mode
237.2
554
µs
3
VLPWAIT mode to VLPRUN mode
1413
1500
µs
4
1. Wakeup times are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from
respective stop/wait mode.
2. Clock configuration: CPU clock=4 MHz. System clock source is 8 MHz IRC in normal mode.
3. CPU clock = 200 KHz and 8 MHz IRC on standby. Exit by an interrupt on PORTC GPIO.
4. Using 64 KHz external clock; CPU Clock = 32KHz. Exit by an interrupt on PortC GPIO.
5. Clock configuration: CPU and system clocks= 100 MHz. Bus Clock = 50 MHz. .Exit by interrupt on PORTC GPIO
7.3.5 Power consumption operating behaviors
Table 11. Current Consumption (mA)
Mode
RUN1
Maximum
Frequency
100 MHz
Conditions
•
•
•
•
•
•
•
•
•
•
RUN2
50 MHz
100 MHz Core
50 MHz Peripheral clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Continuous MAC instructions with fetches from
Program Flash
All peripheral modules enabled. TMRs and SCIs
using 1X peripheral clock
NanoEdge within eFlexPWM using 2X peripheral
clock
ADC/DAC (only one 12-bit DAC and all 6-bit DACs)
powered on and clocked
Comparator powered on
•
•
•
•
•
50 MHz Core and Peripheral clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Continuous MAC instructions with fetches from
Program Flash
• All peripheral modules enabled. TMRs and SCIs
using 1X peripheral clock
• NanoEdge within eFlexPWM using 2X peripheral
clock
Typical at
3.3 V,
25°C
Maximum
at 3.6 V,
105°C
Maximum
at 3.6V,
125°C
IDD1
IDDA
IDD1
IDD1
38.1
9.9
53.5 13.2 53.5 13.2
27.6
9.9
43.5 13.2 43.5 14.0
IDDA
IDDA
Table continues on the next page...
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General
Table 11. Current Consumption (mA) (continued)
Mode
Maximum
Frequency
Conditions
Typical at
3.3 V,
25°C
Maximum
at 3.6 V,
105°C
Maximum
at 3.6V,
125°C
IDD1
IDDA
IDD1
IDDA
IDD1
IDDA
• ADC/DAC (only one 12-bit DAC and all 6-bit DACs)
powered on and clocked
• Comparator powered on
WAIT
50 MHz
•
•
•
•
•
•
•
•
•
50 MHz Core and Peripheral clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered on
Processor Core in WAIT state
All Peripheral modules enabled.
TMRs and SCIs using 1X Clock
NanoEdge within PWMA using 2X clock
ADC/DAC (single 12-bit DAC, all 6-bit DACs),
Comparator powered off
24.0
—
41.3
—
41.3
—
STOP
4 MHz
•
•
•
•
•
•
•
4 MHz Device Clock
Regulators are in full regulation
Relaxation Oscillator on
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
6.3
—
19.4
—
19.4
—
LPRUN
(LsRUN)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's
(ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs. One 12-bit DAC and all 6-bit
DACs enabled.
• Simple loop with running from platform instruction
buffer
2.8
3.1
11.1
4.0
13.0
4.0
LPWAIT
(LsWAIT)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's
(ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs. One 12-bit DAC and all 6-bit
DACs enabled.2
• Processor core in wait mode
2.7
3.1
11.1
4.0
13.0
4.0
LPSTOP
(LsSTOP)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's
(ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Only PITs and COP enabled; other peripheral
modules disabled and clocks gated off2
• Processor core in stop mode
1.2
—
9.1
—
12.0
—
VLPRUN
200 kHz
• 32 kHz Device Clock
• Clocked by a 64 kHz external clock source
0.7
—
7.5
—
10.0
—
Table continues on the next page...
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Table 11. Current Consumption (mA) (continued)
Mode
Maximum
Frequency
Conditions
Typical at
3.3 V,
25°C
Maximum
at 3.6 V,
105°C
Maximum
at 3.6V,
125°C
IDD1
IDDA
IDD1
IDDA
IDD1
IDDA
•
•
•
•
•
•
•
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Small regulator is disabled
PLL disabled
Repeat NOP instructions
All peripheral modules, except COP and EWM,
disabled and clocks gated off
• Simple loop running from platform instruction buffer
VLPWAIT
200 kHz
•
•
•
•
•
•
•
•
32 kHz Device Clock
Clocked by a 64 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby
Small regulator is disabled
PLL disabled
All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in wait mode
0.7
—
7.5
—
10.0
—
VLPSTOP
200 kHz
•
•
•
•
•
•
•
•
0.7
—
7.5
—
10.0
—
32 kHz Device Clock
Clocked by a 64 kHz external clock source
Oscillator in power down
All ROSCs disabled
Large regulator is in standby.
Small regulator is disabled.
PLL disabled
All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads.
2. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 500 kHz due to
the fixed frequency ratio of 1:2 between the CPU clock and the flash clock when running with 2 MHz external clock input
and CPU running at 1 MHz.
7.3.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
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General
7.3.7 Capacitance attributes
Table 12. Capacitance attributes
Description
Symbol
Min.
Typ.
Max.
Unit
CIN
—
10
—
pF
COUT
—
10
—
pF
Input capacitance
Output capacitance
7.4 Switching specifications
7.4.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
0.001
100
MHz
0
100
—
50
Notes
Normal run mode
fSYSCLK
fBUS
Device (system and core) clock frequency
• using relaxation oscillator
• using external clock source
Bus clock
MHz
7.4.2 General switching timing
Table 14. Switching timing
Symbol
Description
GPIO pin interrupt pulse
Min
width1
Max
1.5
Unit
Notes
IP Bus
Clock
Cycles
Synchronous path
Port rise and fall time (high drive strength), Slew disabled 2.7
≤ VDD ≤ 3.6V.
5.5
15.1
ns
Port rise and fall time (high drive strength), Slew enabled 2.7
≤ VDD ≤ 3.6V.
1.5
6.8
ns
Port rise and fall time (low drive strength). Slew disabled . 2.7
≤ VDD ≤ 3.6V
8.2
17.8
ns
Port rise and fall time (low drive strength). Slew enabled . 2.7
≤ VDD ≤ 3.6V
3.2
9.2
ns
2
3
1. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming
GPIOn_IPOLR and GPIOn_IENR.
2. 75 pF load
3. 15 pF load
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7.5 Thermal specifications
7.5.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
Description
TJ
Die junction temperature
TA
Ambient temperature
Min
Max
Unit
V
–40
115
°C
M
–40
135
°C
V
–40
105
°C
M
–40
125
°C
7.5.2 Thermal attributes
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board
type
Symbol
Descriptio
n
32 QFN
32 LQFP
48 LQFP
64 LQFP
Unit
Notes
Single-layer RθJA
(1s)
Thermal
resistance,
junction to
ambient
(natural
convection)
96
83
70
64
°C/W
,
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient
(natural
convection)
33
55
46
46
°C/W
1,
Thermal
resistance,
junction to
ambient
80
70
57
52
°C/W
1,2
RθJA
Single-layer RθJMA
(1s)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Board
type
Symbol
Descriptio
n
32 QFN
32 LQFP
48 LQFP
64 LQFP
Unit
Notes
(200 ft./min.
air speed)
Four-layer
(2s2p)
RθJMA
Thermal
27
resistance,
junction to
ambient
(200 ft./min.
air speed)
49
39
39
°C/W
—
RθJB
Thermal
resistance,
junction to
board
12
31
23
28
°C/W
—
RθJC
Thermal
resistance,
junction to
case
1.8
22
17
15
°C/W
—
ΨJT
Thermal
6
characteriza
tion
parameter,
junction to
package top
outside
center
(natural
convection)
5
3
3
°C/W
1,2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions
—Forced Convection (Moving Air) with the board horizontal.
8 Peripheral operating requirements and behaviors
8.1 Core modules
8.1.1 JTAG timing
Table 16. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
fOP
DC
SYS_CLK/ 8
MHz
Figure 6
TCK clock pulse width
tPW
50
—
ns
Figure 6
TMS, TDI data set-up time
tDS
5
—
ns
Figure 7
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Table 16. JTAG timing (continued)
Characteristic
Symbol
Min
Max
Unit
See
Figure
TMS, TDI data hold time
tDH
5
—
ns
Figure 7
TCK low to TDO data valid
tDV
—
30
ns
Figure 7
TCK low to TDO tri-state
tTS
—
30
ns
Figure 7
1/fOP
VIH
TCK
(Input)
tPW
tPW
VM
VM
VIL
VM = VIL + (VIH – VIL)/2
Figure 6. Test clock input timing diagram
TCK
(Input)
tDS
TDI
TMS
(Input)
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
Figure 7. Test access port timing diagram
8.2 System modules
8.2.1 Voltage regulator specifications
The voltage regulator supplies approximately 1.2 V to the MC56F82xxx’s core logic. For
proper operations, the voltage regulator requires an external 2.2 µF capacitor on each
VCAP pin. Ceramic and tantalum capacitors tend to provide better performance
tolerances. The output voltage can be measured directly on the VCAP pin. The
specifications for this regulator are shown in Table 17.
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Table 17. Regulator 1.2 V parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage1
VCAP
—
1.22
—
V
Short Circuit Current2
ISS
—
600
—
mA
Short Circuit Tolerance (VCAP shorted to ground)
TRSC
—
—
30
Minutes
1. Value is after trim
2. Guaranteed by design
Table 18. Bandgap electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Reference Voltage (after trim)
VREF
—
1.21
—
V
8.3 Clock modules
8.3.1 External clock operation timing
Parameters listed are guaranteed by design.
Table 19. External clock operation timing requirements
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)1
fosc
—
—
50
MHz
Clock pulse width2
tPW
8
trise
—
—
1
ns
tfall
—
—
1
ns
Input high voltage overdrive by an external clock
Vih
0.85VDD
—
—
V
Input low voltage overdrive by an external clock
Vil
—
—
0.3VDD
V
External clock input rise
External clock input fall
1.
2.
3.
4.
time3
time4
ns
See Figure 1 for detail on using the recommended connection of an external clock driver.
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
External
Clock
90%
50%
10%
tPW
tPW
tfall
trise
VIH
90%
50%
10%
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 8. External clock timing
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8.3.2 Phase-Locked Loop timing
Table 20. Phase-Locked Loop timing
Characteristic
PLL input reference
PLL output
frequency1
frequency2
PLL lock
time3
Allowed Duty Cycle of input reference
Symbol
Min
Typ
Max
Unit
fref
8
8
16
MHz
fop
200
—
400
MHz
tplls
35.5
73.2
µs
tdc
40
60
%
50
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must
be set to 400 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
8.3.3 External crystal or resonator requirement
Table 21. Crystal or resonator requirement
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation
fXOSC
4
8
16
MHz
8.3.4 Relaxation Oscillator Timing
Table 22. Relaxation Oscillator Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
0°C to 105°C
7.84
8
8.16
MHz
-40°C to 105°C
7.76
8
8.24
MHz
-40°C to 125°C
7.60
8
8.32
MHz
-40°C to 105°C
248
405
562
kHz
-40°C to 125°C
198
405
702
kHz
0°C to 105°C
+/-1.5
+/-2
%
-40°C to 105°C
+/-1.5
+/-3
%
-40°C to 125°C
+/-1.5
-5 to +4
%
8 MHz Output Frequency1
Run Mode
Standby Mode (IRC
trimmed @ 8 MHz)
8 MHz Frequency Variation over 25°C
RUN Mode
200 kHz Output
Frequency1
RUN Mode
-40°C to 105°C
194
200
206
kHz
-40°C to 125°C
192
200
208
kHz
200 kHz Output Frequency Variation over 25°C
Table continues on the next page...
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Table 22. Relaxation Oscillator Electrical Specifications
(continued)
Characteristic
RUN Mode
Stabilization Time
Symbol
Typ
Max
Unit
0°C to 85°C
+/-1.5
+/-2
%
-40°C to 105°C
+/-1.5
+/-3
%
-40°C to 125°C
+/-1.5
+/-4
%
8 MHz
output2
Min
tstab
200 kHz output3
Output Duty Cycle
48
0.12
µs
10
µs
50
52
%
1. Frequency after factory trim
2. Standby to run mode transition
3. Power down to run mode transition
Figure 9. Relaxation Oscillator Temperature Variation (Typical) After Trim (Preliminary)
8.4 Memories and memory interfaces
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8.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
8.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
52
452
ms
1
1. Maximum time based on expectations at cycling end-of-life.
8.4.1.2
Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
70
575
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
8.4.1.3
Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
Average current adder during high voltage
flash programming operation
Min.
Typ.
Max.
Unit
—
2.5
6.0
mA
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Table 25. Flash high voltage current behaviors (continued)
Symbol
Description
IDD_ERS
Average current adder during high voltage
flash erase operation
8.4.1.4
Symbol
Min.
Typ.
Max.
Unit
—
1.5
4.0
mA
Reliability specifications
Table 26. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
8.5 Analog
8.5.1 12-bit Cyclic Analog-to-Digital Converter (ADC) Parameters
Table 27. 12-bit ADC Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
VDDA
3
3.3
3.6
V
Vrefhx
VDDA-0.6
VDDA
V
fADCCLK
0.1
10
MHz
Recommended Operating Conditions
Supply Voltage1
VREFH (in external reference mode)
ADC Conversion
Conversion
Clock2
Range3
RAD
Fully Differential
– (VREFH – VREFL)
Single Ended/Unipolar
Input Voltage Range (per input)4
VREFH – VREFL
VREFH
VREFL
VADIN
External Reference
V
VREFL
VREFH
0
VDDA
Internal Reference
V
Timing and Power
Conversion Time5
tADC
8
ADC Clock
Cycles
ADC Power-Up Time (from adc_pdn)
tADPU
13
ADC Clock
Cycles
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Table 27. 12-bit ADC Electrical Specifications (continued)
Characteristic
Symbol
ADC RUN Current (per ADC block)
IADRUN
1.8
mA
ADC Powerdown Current (adc_pdn
enabled)
IADPWRDWN
0.1
µA
IVREFH
190
225
µA
Integral non-Linearity6
INL
+/- 1.5
+/- 2.2
LSB7
Differential non-Linearity6
DNL
+/- 0.5
+/- 0.8
LSB7
VREFH Current (in external mode)
Min
Typ
Max
Unit
Accuracy (DC or Absolute)
Monotonicity
GUARANTEED
Offset8
VOFFSET
mV
+/- 8
Fully Differential
+/- 12
Single Ended/Unipolar
Gain Error
EGAIN
0.996 to1.004
0.990 to 1.010
Signal to Noise Ratio
SNR
66
dB
Total Harmonic Distortion
THD
75
dB
Spurious Free Dynamic Range
SFDR
77
dB
Signal to Noise plus Distortion
SINAD
66
dB
Effective Number of Bits
ENOB
—
bits
AC Specifications9
Gain = 1x (Fully Differential/Unipolar)
10.6
Gain = 2x (Fully Differential/Unipolar)
—
Gain = 4x (Fully Differential/Unipolar)
10.3
Gain = 1x (Single Ended)
10.6
Gain = 2x (Single Ended)
10.4
Gain = 4x (Single Ended)
10.2
Variation across channels10
0.1
ADC Inputs
Input Leakage Current
IIN
1
nA
Temperature sensor slope
TSLOPE
1.7
mV/°C
Temperature sensor voltage at 25 °C
VTEMP25
0.82
V
Disturbance
Input Injection Current 11
Channel to Channel
Crosstalk12
Memory Crosstalk13
Input Capacitance
IINJ
+/-3
mA
ISOXTLK
-82
dB
MEMXTLK
-71
dB
CADI
4.8
pF
Sampling Capacitor
1.
2.
3.
4.
5.
6.
The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed
ADC clock duty cycle is 45% ~ 55%
Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
In unipolar mode, positive input must be ensured to be always greater than negative input.
First conversion takes 10 clock cycles.
INL/DNL is measured from VIN = VREFL to VIN = VREFH using Histogram method at x1 gain setting
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7. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain Setting
8. Offset measured at 2048 code
9. Measured converting a 1 kHz input full scale sine wave
10. When code runs from internal RAM
11. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
ADC
12. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk)
13. From a previously sampled channel with 50 kHz full-scale input to the channel being sampled with DC input (memory
crosstalk).
8.5.1.1
Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, and
both S1 and S2 are dependent on
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
-12
(ADC ClockRate) x
4.8x10
+ 100 ohm + 50 ohm
C1
Analog Input
1
50 ESD
Resistor
Channel Mux
equivalent resistance
100Ohms
S1
C1
S1
S/H
S1
2
C1
S2
S1
S2
(VREFHx - VREFLx ) / 2
C1
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock
frequency
S1
S2
Figure 10. Equivalent circuit for A/D loading
32
52
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System modules
8.5.2 12-bit Digital-to-Analog Converter (DAC) parameters
Table 28. DAC parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
12
12
12
bits
—
1
—
—
11
µs
INL
—
+/- 3
+/- 4
LSB3
DNL
—
+/- 0.8
+/- 0.9
LSB3
DC Specifications
Resolution
Settling
time1
At output load
µs
RLD = 3 kΩ
CLD = 400 pF
Power-up time
Time from release of PWRDWN
signal until DACOUT signal is valid
tDAPU
Accuracy
Integral non-linearity2
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
Differential nonlinearity2
Range of input digital words:
Monotonicity
> 6 sigma monotonicity,
Offset error2
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
guaranteed
—
< 3.4 ppm non-monotonicity
VOFFSET
—
+/- 25
+ /- 43
mV
EGAIN
—
+/- 0.5
+/- 1.5
%
VSSA +
0.04 V
—
VDDA - 0.04
V
V
410 to 3891 ($19A - $F33)
5% to 95% of full range
Gain
error2
Range of input digital words: 410 to
3891 ($19A - $F33) 5% to 95% of
full range
DAC Output
Output voltage range
Within 40 mV of either VSSA or VDDA
VOUT
AC Specifications
Signal-to-noise ratio
SNR
—
85
—
dB
Spurious free dynamic
range
SFDR
—
-72
—
dB
Effective number of bits
ENOB
—
11
—
bits
1. Settling time is swing range from VSSA to VDDA
2. No guaranteed specification within 5% of VDDA or VSSA
3. LSB = 0.806 mV
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System modules
8.5.3 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
2.7
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
300
—
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
36
—
μA
VAIN
Analog input voltage
VSS
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 001
—
5
13
mV
• CR0[HYSTCTR] = 01
VH
Analog comparator hysteresis
—
25
48
mV
• CR0[HYSTCTR] =
102
—
55
105
mV
• CR0[HYSTCTR] =
112
—
80
148
mV
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
—
25
50
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)3
—
60
200
ns
Analog comparator initialization delay4
—
40
—
μs
6-bit DAC current adder (enabled)
—
7
—
μA
VDDA
—
VDD
V
IDAC6b
6-bit DAC reference inputs, Vin1 and Vin2
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB5
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1.
2.
3.
4.
Measured with input voltage range limited to 0 to VDD
Measured with input voltage range limited to 0.7≤Vin≤VDD-0.8
Input voltage range: 0.1VDD≤Vin≤0.9VDD, step = ±100mV, across all temperature. Does not include PCB and PAD delay.
Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
5. 1 LSB = Vreference/64
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System modules
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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PWMs and timers
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1.3
1.6
1.9
Vin level (V)
1
2.2
2.5
2.8
3.1
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
8.6 PWMs and timers
8.6.1 Enhanced NanoEdge PWM characteristics
Table 30. NanoEdge PWM timing parameters
Characteristic
Symbol
Min
PWM clock frequency
NanoEdge Placement (NEP) Step
Typ
100
Size1, 2
pwmp
Delay for fault input activating to PWM output deactivated
Power-up Time3
Unit
MHz
312
ps
25
µs
1
tpu
Max
ns
1. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
8.6.2 Quad Timer timing
Parameters listed are guaranteed by design.
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PWMs and timers
Table 31. Timer timing
Characteristic
Symbol
Min1
Max
Unit
See Figure
Timer input period
PIN
2T + 6
—
ns
Figure 13
Timer input high/low period
PINHL
1T + 3
—
ns
Figure 13
Timer output period
POUT
2T-2
—
ns
Figure 13
Timer output high/low period
POUTHL
1T-2
—
ns
Figure 13
1. T = clock cycle. For 100 MHz operation, T = 10 ns.
Timer Inputs
PIN
PINHL
PINHL
POUT
POUTHL
POUTHL
Timer Outputs
Figure 13. Timer timing
8.7 Communication interfaces
8.7.1 Queued Serial Peripheral Interface (SPI) timing
Parameters listed are guaranteed by design.
Table 32. SPI timing
Characteristic
Symbol
Min
Max
Unit
Cycle time
tC
60
—
ns
60
—
ns
Master
Slave
See Figure
Figure 14
Figure 15
Figure 16
Figure 17
Enable lead time
tELD
Master
—
—
ns
20
—
ns
—
—
ns
20
—
ns
Figure 17
Slave
Enable lag time
Master
tELG
Figure 17
Slave
Table continues on the next page...
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PWMs and timers
Table 32. SPI timing (continued)
Characteristic
Symbol
Clock (SCK) high time
tCH
Min
Master
Max
Unit
—
ns
—
ns
Slave
See Figure
Figure 14
Figure 15
Figure 16
Figure 17
Clock (SCK) low time
tCL
Master
28
—
ns
28
—
ns
20
—
ns
1
—
ns
Figure 17
Slave
Data set-up time required for inputs
tDS
Master
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Data hold time required for inputs
tDH
Master
1
—
ns
3
—
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Access time (time to data active
from high-impedance state)
tA
5
—
ns
tD
5
—
ns
tDV
—
ns
—
ns
Figure 17
Slave
Disable time (hold time to highimpedance state)
Figure 17
Slave
Data valid for outputs
Master
Slave (after enable edge)
Figure 14
Figure 15
Figure 16
Figure 17
Data invalid
tDI
Master
0
—
ns
0
—
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Rise time
tR
Master
—
1
ns
—
1
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
Fall time
Master
tF
—
1
ns
—
1
ns
Slave
Figure 14
Figure 15
Figure 16
Figure 17
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PWMs and timers
SS
(Input)
SS is held high on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
Bits 14–1
tDI
MOSI
(Output)
LSB in
tDI(ref)
tDV
Master MSB out
Bits 14–1
Master LSB out
tR
tF
Figure 14. SPI master timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tCL
SCLK (CPOL = 0)
(Output)
tR
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
MISO
(Input)
MSB in
tDI
tDV(ref)
MOSI
(Output)
Master MSB out
tDH
Bits 14–1
tDV
Bits 14– 1
tF
LSB in
tDI(ref)
Master LSB out
tR
Figure 15. SPI master timing (CPHA = 1)
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PWMs and timers
SS
(Input)
tC
tF
tCL
SCLK (CPOL = 0)
(Input)
tELG
tR
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tA
MISO
(Output)
Slave MSB out
tF
tR
Bits 14–1
tDS
Slave LSB out
tDV
tDI
tDH
MOSI
(Input)
MSB in
tD
Bits 14–1
tDI
LSB in
Figure 16. SPI slave timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tA
MISO
(Output)
Slave MSB out
Bits 14–1
tDS
tDV
tDH
MOSI
(Input)
tD
tF
MSB in
Bits 14–1
Slave LSB out
tDI
LSB in
Figure 17. SPI slave timing (CPHA = 1)
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PWMs and timers
8.7.2 Queued Serial Communication Interface (SCI) timing
Parameters listed are guaranteed by design.
Table 33. SCI timing
Characteristic
Symbol
Min
Max
Unit
See Figure
BR
—
(fMAX/16)
Mbit/s
—
RXD pulse width
RXDPW
0.965/BR
1.04/BR
μs
Figure 18
TXD pulse width
TXDPW
0.965/BR
1.04/BR
μs
Figure 19
-14
14
%
—
Baud
rate1
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH
clock rate before synchronization
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
-2
2
%
—
Minimum break character length
TBREAK
13
—
Master
node bit
periods
—
11
—
Slave node
bit periods
—
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.50 MHz
depending on part number) or 2x bus clock (max. 100 MHz) for the devices.
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 18. RXD pulse width
TXD
SCI transmit
data pin
(output)
TXDPW
Figure 19. TXD pulse width
8.7.3 Modular/Scalable Controller Area Network (MSCAN)
Table 34. MSCAN Timing Parameters
Characteristic
Symbol
Min
Max
Unit
Baud Rate
BRCAN
—
1
Mbit/s
CAN Wakeup dominant pulse filtered
TWAKEUP
—
1.5
µs
CAN Wakeup dominant pulse pass
TWAKEUP
5
—
µs
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PWMs and timers
CAN_RX
CAN receive
data pin
(Input)
TWAKEUP
Figure 20. Bus Wake-up Detection
NOTE
CAN wakeup is not supported when ROSC_8M is in standby
mode.
8.7.4 Inter-Integrated Circuit Interface (I2C) timing
Table 35. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
fSCL
0
100
0
400
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
tLOW
4.7
—
1.3
—
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
Data hold time for I2C bus devices
tHD; DAT
01
3.452
03
0.91
Unit
kHz
µs
µs
µs
µs
µs
Data set-up time
tSU; DAT
2504
—
1002, 5
—
ns
Rise time of SDA and SCL signals
tr
—
1000
20 +0.1Cb6
300
ns
Fall time of SDA and SCL signals
tf
—
300
20 +0.1Cb5
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF.
4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
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Design Considerations
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 21. Timing definition for fast and standard mode devices on the I2C bus
9 Design Considerations
9.1 Thermal design considerations
An estimate of the chip junction temperature (TJ) can be obtained from the equation:
TJ = TA + (RΘJA x PD)
Where,
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)
PD = Power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single-layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which TJ value is closer to the application depends on the power
dissipated by other components on the board.
• The TJ value obtained on a single layer board is appropriate for a tightly packed
printed circuit board.
• The TJ value obtained on a board with the internal planes is usually appropriate if the
board has low-power dissipation and if the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-tocase thermal resistance and a case-to-ambient thermal resistance:
RΘJA = RΘJC + RΘCA
Where,
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Design Considerations
RΘJA = Package junction-to-ambient thermal resistance (°C/W)
RΘJC = Package junction-to-case thermal resistance (°C/W)
RΘCA = Package case-to-ambient thermal resistance (°C/W)
RΘJC is device related and cannot be adjusted. You control the thermal environment to
change the case to ambient thermal resistance, RΘCA. For instance, you can change the
size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat
sinks are not used, the thermal characterization parameter (YJT) can be used to
determine the junction temperature with a measurement of the temperature at the top
center of the package case using the following equation:
TJ = TT + (ΨJT x PD)
Where,
TT = Thermocouple temperature on top of package (°C/W)
ΨJT = hermal characterization parameter (°C/W)
PD = Power dissipation in package (W)
The thermal characterization parameter is measured per JESD51–2 specification using a
40-gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
To determine the junction temperature of the device in the application when heat
sinks are used, the junction temperature is determined from a thermocouple inserted at
the interface between the case of the package and the interface material. A clearance slot
or hole is normally required in the heat sink. Minimizing the size of the clearance is
important to minimize the change in thermal performance caused by removing part of the
thermal interface to the heat sink. Because of the experimental difficulties with this
technique, many engineers measure the heat sink temperature and then back-calculate the
case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-tocase thermal resistance.
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Design Considerations
9.2 Electrical design considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the device:
• Provide a low-impedance path from the board power supply to each VDD pin on the
device and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as
near as possible to the package supply pins. The recommended bypass configuration
is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA.
Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VDD and VSS (GND) pins are as short as possible.
• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF
ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
• Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
• Using separate power planes for VDD and VDDA and separate ground planes for VSS
and VSSA are recommended. Connect the separate analog and digital power and
ground planes as near as possible to power supply outputs. If an analog circuit and
digital circuit are powered by the same power supply, then connect a small inductor
or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted
together.
• Physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. Place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,
or I2C, the designer should provide an interface to this port if in-circuit flash
programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value
should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of
0.22 µF–4.7 µF.
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Design Considerations
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
restate during normal operation if JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at tri-state.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.
9.3 Power-on Reset design considerations
9.3.1 Improper power-up sequence between VDD/VSS and VDDA/
VSSA:
It is recommended that VDD be kept within 100 mV of VDDA at all times, including
power ramp-up and ramp-down. Failure to keep VDDA within 100 mV of VDDA may
cause a leakage current through the substrate, between the VDD and VDDA pad cells.
This leakage current could prevent operation of the device after it powers up. The voltage
difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid
permanent damage to the part (See Table 5). Also see Table 6.
9.3.2 Unnecessary protection circuit:
In many circuit designs, it is a general practice to add external clamping diodes on each
analog input pin; see diode D1 and D2 in Figure 22, to prevent the surge voltage from
damaging the analog input.
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Design Considerations
Reg1
DC
DC
200V ~300V
Reg3
12V
C6
+
DC
C5
Reg2
DC
3.3V
DC
C4
+
3.3V
DC
C2
+
R6
R3
C1
VDDA
R5
R4
C3
VDD
MC56F8xxxx
R2
D1
C8
ADC_IN
R1
D2
RESET
D1 and D2 are unnecessary,
because all analog
inputs already have the
internal current injection
protection circuit.
VSSA
VSS
+
C7
Figure 22. Protection Circuit Example
MC56F8xxxx DSC uses the 5V tolerance I/O. When the pin is configured to digital input,
it can accept 5V input. See Table 5. When the pin is configured to analog input, the
internal integrated current injection protection circuit is enabled. The current injection
protection circuit performs the same functions as external clamp diode D1 and D2 in
Figure 22. As long as the source or sink current for each analog pin is less than 3 mA,
then there is no damage to the device. See Table 27. Therefore, D1 and D2 clamping
diodes are not recommended to be used.
9.3.3 Heavy capacitive load on power supply output:
In some applications, the low cost DC/DC converter may not regulate the output voltage
well before it reaches the regulation point, which is roughly around 2.5V to 2.7V.
However, the MC56F8xxxx DSC will exit power-on reset at around 2.3V. If the
initialization code enables the PLL to run the DSC at full speed right after reset, then the
high current will be pulled by DSC from the supply, which can cause the supply voltage
to drop below the operation voltage; see the captured graph (Figure 23). This can cause
the DSC fail to start up.
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Obtaining package dimensions
Figure 23. Supply Voltage Drop
A recommended initialization sequence during power-up is:
1. After POR is released, run a few hundred NOP instructions from the internal
relaxation oscillator; this gives time for the supply voltage to stabilize.
2. Configure the peripherals (except the ADC) to the desired settings; the ADC should
stay in low power mode.
3. Power up the PLL.
4. After the PLL locks, switch the clock from PLL prescale to postscale.
5. Configure the ADC.
10 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing's document number:
Drawing for package
Document number to be used
32LQFP
98ASH70029A
32QFN
98ASA00473D
48-pin LQFP
98ASH00962A
64-pin LQFP
98ASS23234W
11 Pinout
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Pinout
11.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The SIM's GPS registers are responsible
for selecting which ALT functionality is available on most pins.
•
•
•
•
64
48
32
LQFP LQFP LQFP
NOTE
The RESETB pin is a 3.3 V pin only.
If the GPIOC1 pin is used as GPIO, the XOSC should be
powered down.
Not all CMPD pins are available on 48 LQFP, 32 LQFP,
and 32 QFN packages.
QSPI signals—including MISO1, MOSI1, SCLK1, and
SS0_B—are not available on the 48 LQFP, 32 LQFP, and
32 QFN packages.
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
1
1
1
TCK
TCK
GPIOD2
2
2
2
RESETB
RESETB
GPIOD4
3
3
—
GPIOC0
GPIOC0
EXTAL
4
4
—
GPIOC1
GPIOC1
XTAL
5
5
3
GPIOC2
GPIOC2
TXD0
XB_OUT11
XB_IN2
CLKO0
6
—
—
GPIOF8
GPIOF8
RXD0
XB_OUT10
CMPD_O
PWM_2X
7
6
4
GPIOC3
GPIOC3
TA0
CMPA_O
RXD0
CLKIN1
8
7
5
GPIOC4
GPIOC4
TA1
CMPB_O
XB_IN6
EWM_OUT_B
9
—
—
GPIOA7
GPIOA7
ANA7&CMPD_IN3
10
—
—
GPIOA6
GPIOA6
ANA6&CMPD_IN2
11
—
—
GPIOA5
GPIOA5
ANA5&CMPD_IN1
12
8
—
GPIOA4
GPIOA4
ANA4&CMPD_IN0
13
9
6
GPIOA0
GPIOA0
ANA0&CMPA_IN3
14
10
7
GPIOA1
GPIOA1
ANA1&CMPA_IN0
15
11
8
GPIOA2
GPIOA2
ANA2&VREFHA&CMPA_
IN1
16
12
—
GPIOA3
GPIOA3
ANA3&VREFLA&CMPA_
IN2
17
—
—
GPIOB7
GPIOB7
ANB7&CMPB_IN2
18
13
—
GPIOC5
GPIOC5
DACA_O
19
—
—
GPIOB6
GPIOB6
ANB6&CMPB_IN1
20
—
—
GPIOB5
GPIOB5
ANB5&CMPC_IN2
21
14
—
GPIOB4
GPIOB4
ANB4&CMPC_IN1
22
15
9
VDDA
VDDA
23
16
10
VSSA
VSSA
24
17
11
GPIOB0
GPIOB0
CLKIN0
CMPC_O
XB_IN7
ANB0&CMPB_IN3
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
69
Pinout
64
48
32
LQFP LQFP LQFP
Pin Name
Default
ALT0
ANB1&CMPB_IN0
ALT1
ALT2
ALT3
25
18
12
GPIOB1
GPIOB1
DACB_O
26
19
—
VCAP
VCAP
27
20
13
GPIOB2
GPIOB2
ANB2&VERFHB&CMPC_
IN3
28
21
—
GPIOB3
GPIOB3
ANB3&VREFLB&CMPC_
IN0
29
—
—
VDD
VDD
30
22
14
VSS
VSS
31
23
15
GPIOC6
GPIOC6
TA2
XB_IN3
CMP_REF
32
24
—
GPIOC7
GPIOC7
SS0_B
TXD0
XB_IN8
33
25
16
GPIOC8
GPIOC8
MISO0
RXD0
XB_IN9
XB_OUT6
34
26
17
GPIOC9
GPIOC9
SCLK0
XB_IN4
TXD0
XB_OUT8
35
27
18
GPIOC10
GPIOC10
MOSI0
XB_IN5
MISO0
XB_OUT9
36
28
—
GPIOF0
GPIOF0
XB_IN6
37
29
—
GPIOC11
GPIOC11
CANTX
SCL0
TXD1
38
30
—
GPIOC12
GPIOC12
CANRX
SDA0
RXD1
39
—
19
GPIOF2
GPIOF2
SCL0
XB_OUT6
MISO1
40
—
20
GPIOF3
GPIOF3
SDA0
XB_OUT7
MOSI1
41
—
—
GPIOF4
GPIOF4
TXD1
XB_OUT8
PWM_0X
PWM_FAULT6
42
—
—
GPIOF5
GPIOF5
RXD1
XB_OUT9
PWM_1X
PWM_FAULT7
43
31
—
VSS
VSS
44
32
—
VDD
VDD
45
33
21
GPIOE0
GPIOE0
PWM_0B
46
34
22
GPIOE1
GPIOE1
PWM_0A
47
35
23
GPIOE2
GPIOE2
PWM_1B
48
36
24
GPIOE3
GPIOE3
PWM_1A
49
37
—
GPIOC13
GPIOC13
TA3
XB_IN6
EWM_OUT_B
50
38
—
GPIOF1
GPIOF1
CLKO1
XB_IN7
CMPD_O
51
39
25
GPIOE4
GPIOE4
PWM_2B
XB_IN2
52
40
26
GPIOE5
GPIOE5
PWM_2A
XB_IN3
53
—
—
GPIOE6
GPIOE6
PWM_3B
XB_IN4
54
—
—
GPIOE7
GPIOE7
PWM_3A
XB_IN5
55
41
—
GPIOC14
GPIOC14
SDA0
XB_OUT4
PWM_FAULT4
56
42
—
GPIOC15
GPIOC15
SCL0
XB_OUT5
PWM_FAULT5
57
43
27
VCAP
VCAP
58
—
—
GPIOF6
GPIOF6
PWM_3X
59
—
—
GPIOF7
GPIOF7
CMPC_O
60
44
28
VDD
VDD
61
45
29
VSS
VSS
62
46
30
TDO
TDO
GPIOD1
63
47
31
TMS
TMS
GPIOD3
64
48
32
TDI
TDI
GPIOD0
SS0_B
SCLK1
XB_IN2
SS1_B
XB_IN3
MC56F827xx, Rev. 4.1, 11/2018
70
NXP Semiconductors
Pinout
11.2 Pinout diagrams
TDI
TMS
TDO
VSS
VDD
GPIOF7
GPIOF6
VCAP
GPIOC15
GPIOC14
GPIOE7
GPIOE6
GPIOE5
GPIOE4
GPIOF1
GPIOC13
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
The following diagrams show pinouts for the packages. For each pin, the diagrams show
the default function. However, many signals may be multiplexed onto a single pin.
GPIOA7
9
40
GPIOF3
GPIOA6
10
39
GPIOF2
GPIOA5
11
38
GPIOC12
GPIOA4
12
37
GPIOC11
GPIOA0
13
36
GPIOF0
GPIOA1
14
35
GPIOC10
GPIOA2
15
34
GPIOC9
GPIOA3
16
33
GPIOC8
32
GPIOF4
GPIOC7
41
31
8
GPIOC6
GPIOC4
30
GPIOF5
VSS
42
29
7
VDD
GPIOC3
28
VSS
GPIOB3
43
27
6
GPIOB2
GPIOF8
26
VDD
VCAP
44
25
5
GPIOB1
GPIOC2
24
GPIOE0
GPIOB0
45
23
4
VSSA
GPIOC1
22
GPIOE1
VDDA
46
21
3
GPIOB4
GPIOC0
20
GPIOE2
GPIOB5
47
19
2
GPIOB6
RESETB
18
GPIOE3
GPIOC5
48
17
1
GPIOB7
TCK
Figure 24. 64-pin LQFP
NOTE
The RESETB pin is a 3.3 V pin only.
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
71
TDI
TMS
TDO
VSS
VDD
VCAP
GPIOC15
GPIOC14
GPIOE5
GPIOE4
GPIOF1
GPIOC13
48
47
46
45
44
43
42
41
40
39
38
37
Pinout
GPIOC4
7
30
GPIOC12
GPIOA4
8
29
GPIOC11
GPIOA0
9
28
GPIOF0
GPIOA1
10
27
GPIOC10
GPIOA2
11
26
GPIOC9
GPIOA3
12
25
GPIOC8
24
VSS
GPIOC7
31
23
6
GPIOC6
GPIOC3
22
VDD
VSS
32
21
5
GPIOB3
GPIOC2
20
GPIOE0
GPIOB2
33
19
4
VCAP
GPIOC1
18
GPIOE1
GPIOB1
34
17
3
GPIOB0
GPIOC0
16
GPIOE2
VSSA
35
15
2
VDDA
RESETB
14
GPIOE3
GPIOB4
36
13
1
GPIOC5
TCK
Figure 25. 48-pin LQFP
NOTE
The RESETB pin is a 3.3 V pin only.
MC56F827xx, Rev. 4.1, 11/2018
72
NXP Semiconductors
TDI
TMS
TDO
VSS
VDD
VCAP
GPIOE5
GPIOE4
32
31
30
29
28
27
26
25
Product documentation
4
21
GPIOE0
GPIOC4
5
20
GPIOF3
GPIOA0
6
19
GPIOF2
GPIOA1
7
18
GPIOC10
GPIOA2
8
17
GPIOC9
VSSA
9
VDDA
16
GPIOC3
GPIOC8
GPIOE1
15
22
GPIOC6
3
14
GPIOC2
VSS
GPIOE2
13
23
GPIOB2
2
12
RESETB
GPIOB1
GPIOE3
11
24
GPIOB0
1
10
TCK
Figure 26. 32-pin LQFP and QFN
NOTE
The RESETB pin is a 3.3 V pin only.
12 Product documentation
The documents listed in Table 36 are required for a complete description and to
successfully design using the device. Documentation is available from local NXP
distributors, NXP sales offices, or online at www.nxp.com.
Table 36. Device documentation
Topic
DSP56800E/DSP56800EX
Reference Manual
Description
Detailed description of the 56800EX family architecture, 32-bit
digital signal controller core processor, and the instruction set
Document Number
DSP56800ERM
MC56F827xx Reference Manual
Detailed functional description and programming model
MC56F827XXRM
MC56F827xx Data Sheet
Electrical and timing specifications, pin descriptions, and
package information (this document)
MC56F827XXDS
MC56F82xxx Errata
Details any chip issues that might be present
MC56F82xxx_Errata
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
73
Revision History
13 Revision History
The following table summarizes changes to this document since the release of the
previous version.
Table 37. Revision History
Rev. No.
Date
Substantial Changes
2
10/2013
2.1
11/2013
2.2
03/2016 05/2016
• Corrected document part number MC56F827XXDS to MC56F827XX.
• In "12-bit ADC Electrical Specifications" table, corrected Max Gain Error to 0.990 to
1.010.
• In "Part identification" section, in "part number fields" table, added the 32QFN package
identifier.
• In "Electrical design considerations" section, added additional section "Power-on Reset
design considerations".
• Added new section "Power-on Reset design considerations".
• In "Peripheral highlights" section, added
• Periodic Interrupt Timer (PIT) Modules
• External Watchdog Monitor (EWM)
3.0
09/2016
• Added products: 56F82746MLF, 56F82733MFM
• Removed PDB (Programmable Delay Block) mentions, because PDBs are not present
in these devices.
• Added V and M temperature options to operating characteristics.
• Moved "Signal groups" section under "MC56F827xx signal and pin descriptions"
section.
• In "Voltage and current operating ratings" section: updated note; in "Absolute Maximum
Ratings" table, updated Ambient and Junction Temperature rows, also fixed broken
footnotes.
• In "Power consumption operating behaviors" section, in "Current Consumption" table:
added columns and data for Maximum at 3.6V, 125°C", fixed broken footnotes.
• In "Thermal operating requirements" section, updated Die junction temperature and
Ambient temperature requirements.
• In "Relaxation Oscillator Timing" section, in "Relaxation Oscillator Electrical
Specifications" table:
• Added data for "-40°C to 125°C" temperature range.
• For "8 MHz Output Frequency, Standby Mode frequency", 2 corrections were
made.
• Fixed broken footnotes.
4
07/2018
• Some updates in "Signal descriptions" table, e.g. VCAP description, TCK row, GPIO
rows "State During Reset" collum corrected.
• In "Voltage and current operating requirements" table, updated the note.
• In "DC Electrical Characteristics at Recommended Operating Conditions" table, added
a new row for IIL and some footnotes (also with a new figure).
• In "SCI timing" table, typo fix for the Unit of pulse width.
• Thorough updates in "Power-on Reset design considerations" section, the second subsection now named as "Unnecessary protection circuit" and contents clarified.
• In "Signal Multiplexing and Pin Assignments" section, typo fix in the "Not all CMPD pins
…" item.
• Minor editorial updates.
First public release
• In Table 2, added DACB_O signal description.
• In Obtaining package dimensions, changed 32-QFN's document number from
'98ARE10566D' to '98ASA00473D'.
Table continues on the next page...
MC56F827xx, Rev. 4.1, 11/2018
74
NXP Semiconductors
Revision History
Table 37. Revision History (continued)
Rev. No.
Date
4.1
11/2018
Substantial Changes
• Added new part number MC56F82748MLH.
• Some updates in the "Power supervisor" section.
MC56F827xx, Rev. 4.1, 11/2018
NXP Semiconductors
75
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