MC68302FC25C

March 20, 1997 5:12 pm 2 1 5A 2,3 1 Clock high to FC, address valid EXTAL to Clock delay Clock pulse width Cycle period tchadz tchfcadv tcd tcl,tch tcyc 0 - 0 2 15 30 15 - 25 27 11 Table 1: 3 6 Clock high to Address, Data Hi-z tchafi 3 - 33MHz Max 4 7 Clock high to Address, FC invalid (Minimum) tchsl 8 15 33MHz Min 5 8 Clock high to AS, DS asserted tafcvsl - Spec Name UM 6 9 Address, FC Valid to AS, DS Assert (read) AS assert (Write) tclsn Description 7 11 Clock low to AS, DS negate - For More Information On This Product, Go to: www.freescale.com Spec No. 8 12 8 # 9 tshafi - AS, DS Negated to Address FC Invalid 30 - 13 tdsl 30 25 10 DS width asserted, write tsh - - - 14A AS, DS width negate tchca 8 15 60 12 15 Clock high to Control Bus Hi-z tshrh - tsl 13 16 AS, DS Negated to R/W Invalid tchrh AS (and DS read) width asserted 14 17 Clock high to R/W hi 14 15 18 11 16 Page 1 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 27 26 25 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 23 22 21 20A 20 HALT,RESET in transition time DTACK assert to Data-In valid AS, DS negated to BERR negated AS, DS Negated to Data In invalid AS, DS negate to DTACK negate Data in to Clock low Data-out valid to DS Asserted (Write) AS, DS Negated to Data-out invalid Clock low to data valid R/W low to DS assert (write) Address FC Valid to R/W Low (Write) AS Asserted to R/W Low (Write) Clock high to R/W lo tchgl trhr, trhf tdaldi tshbeh tshdii tshdah tdicl tdosl tcldo tcldo trasa tafcvrl tasrv tchrl - - - - 0 0 0 4 8 - - 8 - - 33MHz Min 4.5 clks 15 15 25 - - 65 - - 15 15 - 7 15 33MHz Max Table 1: 28 32 Clock high to BG assert tchgh 2.5 clks 2.5 clks Spec Name UM 29 33 Clock high to BG negate tbrlgl 1.5 clks Description 30 34 BR assert to BG assert tbrhgh Spec No. 31 35 BR negate to BG negate For More Information On This Product, Go to: www.freescale.com # 32 36 150 33 Page 2 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 46 45 44 43 42 41 40 39 38 37 36 35 34 57 56 55 53 48 47 46 44 41 40 39 38 37A 37 BGACK negate to FC BGACK negate to AS, DS, RW driven HALT/RESET pulse width R/W assert to Data bus impedance change Data-out hold from clk high BERR assert to DTACK assert Async input setup time BGACK width low AS, DS negate to AVEC negate BGACK assert to AS assert BGACK assert to Address valid BG width negate BG assert to Addr, Data, etc. hi-z BGACK assert to BR negate BGACK assert to BG negate trhsd tgafd tgasd thrpw trldbd tchdoi tbeldal tasi tgal tshvph tgalasa tgalav tgh tglz tgalbrh tgalgh Spec Name UM 1 clk 1.5 clks 1 clk 1.5 clks 10 clks 0 0 7 7 1.5 clks 0 - 15 1.5 clks - 10 ns 2.5 clks 33MHz Min - - - - - - - - 1.5 clks 25 20 - - 25 1.5 clks 4.5 clks 33MHz Max Table 1: 47 57A BR negate to AS, DS, RW driven trhfd Description 48 58 BR negate to FC Spec No. 49 58A For More Information On This Product, Go to: www.freescale.com # 50 Page 3 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 57 56 55 54 53 52 51 82 81 80 64 63 62 61 60 Clock high to BR low DREQ low to BR low DREQ width low DREQ asynchronous set up time RMC negate to BG assert Clock high to RMC negate Clock low to RMC assert Clock high to BCLRO hi-z Clock high to BCLR assert tchbrz tchbrl treqlbrl treql treqasi trmhgl tchrmh tclrml tchbcn tchbca 15 - - - 2 clks 10 - - - - - 33MHz Min 15 - 15 15 2 clks - - 15 17 17 15 15 33MHz Max Table 1: 58 83 Clock high to BR hi-z tbklbrz - Spec Name UM 59 84 BGACK low to BR hi-z tchbkl Description 60 85 Clock high to BGACK low Spec No. 61 86 1.5 clks For More Information On This Product, Go to: www.freescale.com # 62 tabhbkl 1.5 clks AS and BGACK high to BGACK low tbglbkl trhbgh 2.5 clks + 20 ns 87 BG low to BGACK low BR hi-z to BG high - 63 88 89 0 2.5 clks + 20 ns 64 65 Page 4 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 72 71 70 69 68 67 97 96 95 94 93 92 91 90 RW valid to DS low DONE input low to clock high Clock low to DONE hi-z Clock high to DONE low (output) Clock low to DACK high Clock high to DACK low Clock low to BGACK hi-z Clock high to BGACK high Clock on which BGACK low to clock on which AS low tdsldiv trwvdsl tdnltch tcldnz tchdnl tclackh tchackl tclbkz tchbkh tclbklal Spec Name UM 0 - 0 10 - - - - - - 2 clks 33MHz Min - - 15 - - 15 15 15 15 10 15 2 clks 33MHz Max Table 1: 73 100 DS low to Data-in valid tdkldh 0 Description 74 101 DTACK low to Data in hold time tasvdsl Spec No. 75 102 AS valid to DS low # 76 103 81 80 79 78 108 107 106 105 104 DS high to data hi-z DS high to RW high DS inactive to AS inactive DS high to DTACK high DTACK low to AS, DS high tdshdz tdshrwh tdsiasi tdshdkh tdkldsh - 0 0 - 0 25 - - 25 - For More Information On This Product, Go to: www.freescale.com 66 77 82 Page 5 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 95 94 93 92 91 90 89 88 87 86 85 84 83 # 121 120 119 118 117 116 115 114 113 112 111 110 109A 108A Spec No. Clock low to DTACK low (1 wait state) AS low to DTACK low (0 wait states) AS high to IAC low AS low to IAC high Clock high to RW high RW valid to clock high Clock low to UDS/LDS high UDS/LDS low to clock high AS inactive time AS high to address hold time on write Clock low to AS high AS low to clock high Address valid to AS low Data out valid to DTACK low DS high to data out hold time tashdth tcldtl tasldtl tashial tasliah tchrwh trwvch tclsh tslch tash tashah tclash taslch tavasl tdovdkl tdshdh - - - - - - - 15 - 21 1 clk 0 - 15 8 10 0 33MHz Min 10 20 15 25 21 21 20 - 20 - - - 25 - - - - 33MHz Max March 20, 1997 5:12 pm 96 122 AS high to DTACK high tdthdtz Table 1: 97 123 DTACK high to DTACK hi-z Spec Name UM 98 124 For More Information On This Product, Go to: www.freescale.com Description 99 Page 6 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 110 109 108 107 106 105 104 103 102 101 100 144 143 142 141 140 131 130 129 128 127 126 125 AS high to data out hold time Clock high to data out valid Clock low to DTACK high Clock high to DTACK low Clock low to IAC low Clock high to IAC high Clock low to data in hold time Data in valid to clock low UDS/LDS inactive time AS high to address hold time on read AS high to data out hold time AS high to data hi-z Clock high to data out valid tchcsiakl tashdoh tchdov tcldth tchdtl tclial tchiah tcldih tcldiv tsh tashai tashdoi tashdz tchdov 0 0 0 - - - - 10 15 1 clk 0 0 - - 33MHz Min - 20 20 - 15 22 25 21 - - - - - 25 15 33MHz Max Table 1: 111 145 Clock high to CS, IACK low tclcsiakh 30 25 Spec Name UM 112 150 Clock low to CS, IACK high tcsh - Description 113 151 CS width negated tchdtkl Spec No. 114 152 Clock high to DTACK low (0 wait states) For More Information On This Product, Go to: www.freescale.com # 115 153 21 116 Page 7 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 128 127 126 125 124 123 122 121 120 119 118 117 168 167 165 164 163 162 161 160 158 157 156 155 154 AS high to BERR hi-z AS low to BERR low AS high to DTACK high AS low to DTACK low (0 wait states) AS negated to address hold time RW valid to AS low Address valid to AS low AS high to CS high AS low to CS low DTACK high to DTACK hi-z Clock low to BERR hi-z Clock high to BERR low Clock low to DTACK high Clock low to DTACK low (1-6 wait states) tidhcl tashberh taslberl tashdtkh tasldtkl tashai trwvasl tavasl tashcsh taslcsl tdtkhdtkz tclberh tchberl tcldtkh tcldtkh 7 5 - - - - 0 8 8 - - - - - - - 33MHz Min - - - 18 18 18 25 - - - 16 16 10 20 20 20 15 33MHz Max Table 1: 129 169 Input data hold time from S6 low tcsndoi 15 Spec Name UM 130 171 CS negated to data out invalid (write) tafvcsa Description 131 172 Address, FC valid to CS asserted Spec No. 132 173 For More Information On This Product, Go to: www.freescale.com # 133 Page 8 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 145 144 143 142 141 140 139 138 137 136 135 134 202 201 200 191 190 182 181 180 178 177 176 175 174 TIN clock cycle time TIN clock high pulse width and input capture high pulse width TIN clock low pulse width Timer input capture pulse width Minimum time between active edges Interrupt Pulse Width low IRQ Clock high to data out valid input data hold time Input data setup time CS negate to data in invalid CS assert to RW low (Write) CS negate to RW invalid CS low time (0 wait states) CS negated to address, FC invalid tchtov tcyc tticht tticlt ttpw taemt tipw tchdov tdh tdsu tcsndii tcsarwl tcsnrwi tcslt tcsnafi 14 - 3 clks 2 clks 28 28 3 clks 28 - - 14 0 - 7 60 12 33MHz Min - - 24 - - - - - - 20 19 - - 8 - - - 33MHz Max Table 1: 146 203 Clock high to TOUT valid tfrzsu 7 Spec Name UM 147 204 FRZ input setup time (to clock high) tfrzht Description 148 205 FRZ input setup time (from clock high) Spec No. 149 206 For More Information On This Product, Go to: www.freescale.com # 150 Page 9 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 159 158 157 156 155 154 153 152 151 264 263 262 261 260 254 253 252 251 250 L1SY1 (sync) hold time (to L1CLK falling edge) L1SY1 (sync) setup time (to L1CLK falling edge) L1TXD, L1RQ, SDS1-SDS2 rise/fall time L1CLK width high L1CLK width low L1CLK (IDL Clock) frequency SCP receive hold time SCP receive setup time Delay from SPCLK to transmit SPCLK clock output rise/fall time SPCLK clock output period 0 28 15 - P+10 28 - 6 20 0 0 4 clks 33MHz Min 40 - - - 12 - - 13.3 MHz - - 20 6 64 clks 33MHz Max Table 1: 160 265 L1SY1 (sync) inactive before 4th L1CLK 0 26 Spec Name UM 161 266 L1TXD active delay (from L1CLK falling edge) 0 - Description 162 267 L1TXD to hi-z (from L1CLK rising edge) 26 Spec No. 163 268 L1RXD setup time (to L1CLK falling edge) For More Information On This Product, Go to: www.freescale.com # 164 269 - 165 26 270 L1RXD hold time (from L1CLK falling edge) 166 Time between successive IDL syncs - 271 20 L1CLKS 167 Page 10 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 172 171 170 169 168 280 276 275 274 273 272 L1CLK width low/high normal mode L1CLK clock period normal mode SDS1-SDS2 inactive delay from L1CLK falling edge SDS1-SDS2 active delay from L1CLK rising edge L1GR hold time (from L1SY1 falling edge) L1GR setup time (to L1SY1 falling edge) L1RQ valid before falling edge of L1SY1 - 840 1800 7 7 26 26 1 L1CLKS 33MHz Min - - 1450 2100 40 40 - - - 33MHz Max Table 1: 173 281 L1CLK rise/fall time Normal mode 150 - Spec Name UM 174 282 L1CLK clock period MUX mode 55 Description 175 280 L1CLK width low/high MUX mode Spec No. 176 281 - For More Information On This Product, Go to: www.freescale.com # 177 P+10 - L1CLK width high MUX mode 15 - 281A L1SY1 sync setup time to L1CLK falling edge 26 55 178 283 L1SY1 sync hold time (from L1CLK falling edge) 0 55 - 180 284 L1TxD active delay (from L1ClK rising edge) 0 - - 181 285 L1TXD active delay (from L1SY1 rising edge) 14 L1CLK rise/fall time MUX mode 182 286 L1RXD Setup time to L1CLK rising edge 282 183 287 179 184 Page 11 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 195 194 193 192 191 190 189 188 187 186 185 304 303 302 301A 301 300 293 292 291 290 289 288 Time between successive sync signals L1SY0-L1SY1 width low L1SY0-L1SY1 hold time L1SY0-L1SY1 setup time L1CLK width high L1CLK width low L1CLK (PCM clock) frequency GCIDCL (GCI data clock) active delay SDS1-SDS2 inactive delay from L1CLK falling edge SDS1-SDS2 active delay from L1SY1 rising edge SDS1-SDS2 active delay from L1CLK rising edge Time between successive L1SY1 L1RXD hold time from L1CLK rising edge 0 8 L1CLK 1 L1CLK 20 0 P+10 27 - 0 7 7 7 64 L1CLK 192 L1CLK 26 33MHz Min 26 40 - - - - - - 13.2 MHz 26 45 45 45 - - 33MHz Max Table 1: 196 305 L1TXD data valid after L1CLK rising edge 0 - Spec Name UM 197 306 L1TXD to hi-z (from L1CLK rising edge) 11 Description 198 307 L1RXD setup time (to L1CLK falling edge) Spec No. 199 308 For More Information On This Product, Go to: www.freescale.com # 200 Page 12 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. March 20, 1997 5:12 pm 201 315 309 RCLK1 and TCLK1 low RCLK1 and TCLK1 frequency L1RXD hold time (from L1CLK falling edge) Internal clk External clk Internal clk External clk Internal clk External clk - 35 25 35ns P+10 - 26 33MHz Min 20 30 11 - - - 11 MHz 13.2 MHz - 33MHz Max Table 1: 202 316 RCLK1 and TCLK1 high Internal clk External clk 0 0 20 50 Spec Name UM 203 316A RCLK1 and TCLK1 rise/fall time Internal clk External clk 0 0 Description 204 317 RXD1 active delay from TCLK1 falling edge Internal clk External clk Spec No. 205 318 RTS1 active/inactive delay from TCLK1 falling edge For More Information On This Product, Go to: www.freescale.com # 206 319 - 207 30 7 - Internal clk External clk 7 30 - 30 7 RXD1 setup time to RCLK1 rising edge Internal clk External clk 30 7 Internal clk External clk 321 RXD1 hold time from RCLK1 rising edge Internal clk External clk CTS1 setup time to TCLK1 rising edge 209 322 CD1 setup time to RCLK1 rising edge 320 210 323 208 211 Page 13 of 13 MC68302 Document Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.