Freescale Semiconductor
Order this document
by MC68334TS/D REV. 1
MC68334
Technical Summary
32-Bit Modular Microcontroller
1 Introduction
The MC68334, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that
interface through a common intermodule bus (IMB). Standardization facilitates rapid development of
devices tailored for specific applications.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), an 8/10-bit analogto-digital converter (ADC), a time processor unit (TPU) and a 1-Kbyte static RAM module with TPU emulation capability (TPURAM).
The MCU can either synthesize an internal clock signal from an external reference or use an external
clock input directly. Operation with a 32.768-kHz reference frequency is standard. The maximum system clock speed is 20.97 MHz. System hardware and software allow changes in clock rate during operation. Because MCU operation is fully static, register and memory contents are not affected by clock
rate changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The
CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this
capability.
This document contains information about a new product. Specifications and information herein are
subject to change without notice.
Table 1 Ordering Information
Package Type
132-Pin PQFP
TPU Type
Motion Control
Temperature
–40 to +85 °C
–40 to +105 °C
–40 to +125 °C
SP Prefix
2-Piece
Tray
Order Quantity
No Affix
36-Piece
Tray
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Frequency
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
B1 Suffix
180
(5 Trays)
Order Number
MC68334GCFC16
MC68334GCFC20
MC68334GVFC16
MC68334GVFC20
MC68334GMFC16
MC68334GMFC20
TABLE OF CONTENTS
Section
1
Page
8
Introduction
1
Features ......................................................................................................................................3
Block Diagram .............................................................................................................................3
Pin Assignments ..........................................................................................................................5
Address Map ...............................................................................................................................6
Intermodule Bus ..........................................................................................................................6
Signal Descriptions
7
Pin Characteristics ......................................................................................................................7
MCU Power Connections ............................................................................................................8
MCU Driver Types .......................................................................................................................8
Signal Characteristics ..................................................................................................................9
Signal Function ..........................................................................................................................10
System Integration Module
11
Overview ...................................................................................................................................11
System Configuration and Protection Block ..............................................................................13
System Clock ............................................................................................................................19
External Bus Interface ...............................................................................................................24
Chip Selects ..............................................................................................................................28
General-Purpose Input/Output ..................................................................................................35
Resets .......................................................................................................................................37
Interrupts ...................................................................................................................................40
Factory Test Block .....................................................................................................................42
Central Processor Unit
43
Overview ...................................................................................................................................43
Programming Model ..................................................................................................................43
Status Register ..........................................................................................................................44
Data Types ................................................................................................................................45
Addressing Modes .....................................................................................................................45
Instruction Set Summary ...........................................................................................................46
Background Debugging Mode ...................................................................................................49
Time Processor Unit
51
Overview ...................................................................................................................................51
Programmer's Model .................................................................................................................51
TPU Components ......................................................................................................................52
TPU Operation ..........................................................................................................................54
Emulation Support .....................................................................................................................55
Time Functions ..........................................................................................................................55
TPU Registers ...........................................................................................................................57
Analog-to-Digital Converter Module
63
Analog Subsystem ....................................................................................................................63
Digital Control Subsystem .........................................................................................................63
ADC Address Map .....................................................................................................................64
ADC Registers ...........................................................................................................................66
Standby RAM with TPU Emulation
72
Overview ...................................................................................................................................72
TPURAM Register Block ...........................................................................................................72
TPURAM Registers ...................................................................................................................72
TPURAM Operation ..................................................................................................................73
Summary of Changes
74
2
MC68334
MC68334TS/D REV. 1
2
3
4
5
6
7
1.1
1.2
1.3
1.4
1.5
2.1
2.2
2.3
2.4
2.5
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.1
6.2
6.3
6.4
7.1
7.2
7.3
7.4
1.1 Features
• Central Processing Unit (CPU32)
— 32-Bit Architecture
— Virtual Memory Implementation
— Table Lookup and Interpolate Instruction
— Improved Exception Handling for Controller Applications
— High-Level Language Support
— Background Debugging Mode
— Fully Static Operation
• System Integration Module (SIM)
— External Bus Support
— Programmable Chip-Select Outputs
— System Protection Logic
— Watchdog Timer, Clock Monitor, and Bus Monitor
— Two 8-Bit Dual Function Input/Output Ports
— One 7-Bit Dual Function Output Port
— Phase-Locked Loop (PLL) Clock System
• 8/10-Bit Analog-to-Digital Converter (ADC)
— Seven Analog/Digital Input Pins (Eighth Channel Connected to VSSA)
— Eight Result Registers
— Eight Conversion Modes
— Three Result Alignment Modes
— One 7-Bit Digital Input Port
• Time Processor Unit (TPU)
— Dedicated Microengine Operating Independently of CPU32
— 16 Independent, Programmable Channels and Pins
— Any Channel can Perform any Microcoded Time Function
— Two Timer Count Registers with Programmable Prescalers
— Selectable Channel Priority Levels
• 1-Kbyte Standby RAM with TPU Emulation (TPURAM)
— External Standby Voltage Supply Input
— Can be Used as Standby RAM or TPU Microcode Emulation RAM
1.2 Block Diagram
MC68334
MC68334TS/D
3
VSTBY
CHIP
SELECTS
TPUCH[15:0]
TPUCH[15:0]
T2CLK
FC2
FC1
FC0
TPURAM
1 KBYTE
TPU
ADDR[23:19]
T2CLK
CONTROL
PORT C
BR
BG
BGACK
CS[10:0]
VRH
VRL
ADDR[18:0]
SIZ1
SIZ0
EBI
AS
DS
RMC
AVEC
DSACK1
DSACK0
PE7/SIZ1
PE6/SIZ0
PE5/AS
PE4/DS
PE3/RMC
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
DATA[15:0]
PORT AD
CONTROL
DATA[15:0]
IRQ[7:1]
ADC
CPU 32
CONTROL
PORT F
AN6/PADA6
AN5/PADA5
AN4/PADA4
AN3/PADA3
AN2/PADA2
AN1/PADA1
AN0/PADA0
ADDR[23:0]
CONTROL
PORT E
IMB
MODCLK
BKPT
IFETCH
IPIPE
DSI
DSO
DSCLK
FREEZE
CLOCK
QUOT
TSC
CONTROL
CONTROL
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
XFC
VDDSYN
TEST
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
CSBOOT
ECLK/ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
FREEZE/QUOT
334 BLOCK
Figure 1 MC68334 Block Diagram
4
MC68334
MC68334TS/D
PC7/ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
VSS
TPUCH12
TPUCH13
TPUCH14
TPUCH15
T2CLK
VSS
VDD
TPUCH8
TPUCH9
TPUCH10
TPUCH11
VSS
VDD
TPUCH0
TPUCH1
TPUCH2
TPUCH3
TPUCH4
TPUCH5
TPUCH6
TPUCH7
VSS
VDD
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
VSS
1.3 Pin Assignments
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MC68334
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
VDD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
VDD
VSS
DATA4
DATA5
DATA6
DATA7
VSS
DATA8
DATA9
DATA10
DATA11
VDD
VSS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE4/DS
VDD
EXTAL
VDD
XFC
VDD
CLKOUT
VSS
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
R/W
PE7/SIZ1
PE6/SIZ0
PE5/AS
VSS
VRL
AN5/PADA5
AN6/PADA6
IPIPE/DSO
IFETCH/DSI
BKPT/DSCLK
TSC
FREEZE/QUOT
VSS
XTAL
VDDSYN
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
VDD
VSTBY
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
VDD
VSS
ADDR9
ADDR10
ADDR11
ADDR12
VSS
ADDR13
ADDR14
ADDR15
ADDR16
VDD
VSS
ADDR17
ADDR18
VDD
VSS
AN0/PADA0
AN1/PADA1
AN2/PADA2
AN3/PADA3
AN4/PADA4
VRH
334 132-PIN QFP
Figure 2 MC68334 132-Pin QFP Pin Assignments
MC68334
MC68334TS/D
5
1.4 Address Map
The following figure is a map of the MCU internal addresses. The RAM array is positioned by the base
address registers in the associated RAM control block. Unimplemented blocks are mapped externally.
$YFF000
TPURAM ARRAY
UPPER 1 KBYTES
OF 2-KBYTE BLOCK
$YFF700
$YFF740
ADC
RESERVED
$YFFA00
SIM
$YFFA80
$YFFB00
RESERVED
TPURAM CONTROL
$YFFB40
RESERVED
$YFFE00
TPU
$YFFFFF
Y = M111, where M is the signal state of the module mapping (MM) bit in the SIM
configuration register (Y = $7 or Y = $F).
334 ADDRESS MAP
Figure 3 MC68334 Address Map
1.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of
modular microcontrollers. It contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another and with external components through the IMB. The IMB in the MCU uses 24
address lines and 16 data lines.
6
MC68334
MC68334TS/D
2 Signal Descriptions
2.1 Pin Characteristics
The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All
inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin
function. Refer to the table MCU Driver Types for a description of output drivers. An entry in the discrete
I/O column of the MCU Pin Characteristics table indicates that a pin has an alternate I/O function. The
port designation is given when it applies. Refer to the MCU Block Diagram for information about port
organization.
Table 2 MCU Pin Characteristics
Pin
Mnemonic
ADDR23/CS10/ECLK
ADDR[22:19]/CS[9:6]
ADDR[18:0]
AN[6:0]
Output
Driver
A
A
A
—
Input
Hysteresis
N
N
N
Y
Discrete
I/O
—
O
—
I
Port
Designation
—
PC[6:3]
—
PADA[6:0]
AS
AVEC
B
B
B
Y1
Y
Y
Y
N
N
N
I/O
I/O
—
PE5
PE2
—
B
B
—
B
A
B
Aw
—
Y
Y
Y
—
—
Y
—
N
Y
N
—
—
N
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
B
B
A
A
—
Y
Y
Y
Y
—
—
N
N
N
Y
—
—
I/O
I/O
I/O
—
—
—
PE4
PE1
PE0
—
—
—
A
A
Bo
Y
—
Y
—
—
N
O
—
—
PC[2:0]
—
—
B
B
Y
Y
Y
N
I/O
I/O
PF[7:1]
PF0
VRH4
A
Bo
B
B
A
—
A
—
Y
Y
Y
Y
Y
Y
Y
—
N
Y
N
N
Y
Y
Y
—
—
—
I/O
I/O
—
—
—
—
—
—
PE3
PE[7:6]
—
—
—
—
VRL4
—
—
—
—
—
BERR2
BG/CS1
BGACK/CS2
BKPT/DSCLK
BR/CS0
CLKOUT
CSBOOT
DATA[15:0]1
DS
DSACK1
DSACK0
DSI/IFETCH
DSO/IPIPE
EXTAL3
FC[2:0]/CS[5:3]
FREEZE/QUOT
HALT2
IRQ[7:1]
MODCLK1
R/W
RESET
RMC
SIZ[1:0]
TPUCH[15:0]
TSC
T2CLK
Input
Synchronized
Y
Y
Y
XFC3
—
—
—
—
—
XTAL3
—
—
—
—
—
R/W
A
Y
N
—
—
MC68334
MC68334TS/D
7
Table 2 MCU Pin Characteristics
Pin
Mnemonic
RESET
RMC
SIZ[1:0]
TPUCH[15:0]
TSC
T2CLK
VRH4
Output
Driver
Bo
B
B
A
—
A
—
Input
Synchronized
Y
Y
Y
Y
Y
Y
—
Input
Hysteresis
Y
N
N
Y
Y
Y
—
Discrete
I/O
—
I/O
I/O
—
—
—
—
Port
Designation
—
PE3
PE[7:6]
—
—
—
—
VRL4
—
—
—
—
—
XFC3
—
—
—
—
—
XTAL3
—
—
—
—
—
NOTES
1. DATA[15:0] are synchronized during reset only. MODCLK and ADC pins are synchronized only when used
as input port pins.
2. BERR, HALT only synchronized if late BERR or HALT.
3. EXTAL, XFC, and XTAL are clock reference connections.
4. VRH and VRL are ADC reference voltage points.
2.2 MCU Power Connections
Table 3 MCU Power Connections
Pin
VSTBY
VDDSYN
VDDA/VSSA
VRH/VRL
VSSE/VDDE
VSSI/VDDI
Description
Standby RAM Power/Clock Synthesizer Power
Clock Synthesizer Power
A/D Converter Power
A/D Reference Voltage
External Periphery Power (Source and Drain)
Internal Module Power (Source and Drain)
2.3 MCU Driver Types
Table 4 MCU Driver Types
8
Type
I/O
A
O
Description
Output-only signals that are always driven. No external pull-up required.
Aw
O
Type A output with weak P-channel pull-up during reset.
B
O
Three-state output that includes circuitry to pull up asserted output before high
impedance is established, to ensure rapid rise time. An external holding resistor is
required to maintain logic level while in the high-impedance state. Pins with this type of
driver may only go into high-impedance state under certain conditions. The TSC signal
can put all pins with this type of driver in high-impedance state.
Bo
O
Type B output that can be operated in an open-drain mode.
MC68334
MC68334TS/D
2.4 Signal Characteristics
Table 5 MCU Signal Characteristics
MC68334
MC68334TS/D
Signal Name
ADDR[23:0]
AN[6:0]
AS
AVEC
BERR
BG
BGACK
BKPT
BR
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
DSACK[1:0]
DSCLK
DSI
DSO
ECLK
EXTAL
FC[2:0]
FREEZE
HALT
IFETCH
IPIPE
IRQ[7:1]
MODCLK
PADA[6:0]
PC[6:0]
PE[7:0]
PF[7:0]
QUOT
R/W
RESET
RMC
SIZ[1:0]
TPUCH[15:0]
TSC
T2CLK
VRH
MCU Module
SIM
ADC
SIM
SIM
SIM
SIM
SIM
CPU32
SIM
SIM
SIM
SIM
SIM
SIM
SIM
CPU32
CPU32
CPU32
SIM
SIM
SIM
SIM
SIM
CPU32
CPU32
SIM
SIM
ADC
SIM
SIM
SIM
SIM
SIM
SIM
SIM
SIM
TPU
SIM
TPU
ADC
Signal Type
Bus
Input
Output
Input
Input
Output
Input
Input
Input
Output
Output
Output
Bus
Output
Input
Input
Input
Output
Output
Input
Output
Output
Input/Output
Output
Output
Input
Input
Input
Output
Input/Output
Input/Output
Output
Output
Input/Output
Input/Output
Output
Input/Output
Input
Input
Input
Active State
1/0
—
0
0
0
0
0
0
0
—
0
0
1/0
0
0
Serial Clock
Serial Data
Serial Data
—
—
1/0
1
0
0
0
0
—
(Port)
(Port)
(Port)
(Port)
—
1/0
0
0
1
—
1
—
—
VRL
ADC
Input
—
XFC
XTAL
SIM
SIM
Input
Output
—
—
9
2.5 Signal Function
Table 6 MCU Signal Function
Mnemonic
ADDR[23:0]
AN[6:0]
AS
AVEC
BERR
BG
BGACK
BKPT
BR
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
Signal Name
Address Bus
ADC Analog Input
Address Strobe
Autovector
Bus Error
Bus Grant
Bus Grant Acknowledge
Breakpoint
Bus Request
System Clockout
Chip Selects
Boot Chip Select
Data Bus
Data Strobe
DSACK[1:0]
Data and Size
Acknowledge
Development Serial In,
Out, Clock
E-Clock
Crystal Oscillator
DSI, DSO, DSCLK
ECLK
EXTAL, XTAL
FC[2:0]
FREEZE
HALT
IFETCH
IPIPE
IRQ[7:1]
MODCLK
PADA[6:0]
PC[6:0]
PE[7:0]
PF[7:0]
QUOT
RESET
RMC
R/W
SIZ[1:0]
TPUCH[15:0]
TSC
T2CLK
VRH, VRL
XFC
10
Function
24-bit address bus used by CPU32
Inputs to ADC multiplexer
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
System clock output
Select external devices at programmed addresses
Chip select for external boot start-up ROM
16-bit data bus
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
Provide asynchronous data transfers and dynamic bus sizing
Serial I/O and clock for background debugging mode
External M6800 bus clock output
Connections for clock synthesizer circuit reference;
a crystal or an external oscillator can be used
Function Codes
Identify processor state and current address space
Freeze
Indicates that the CPU has entered background mode
Halt
Suspend external bus activity
Instruction Fetch
Identifies bus cycles in which operand is loaded into pipeline
Instruction Pipeline
Indicates instruction pipeline activity
Interrupt Request Level Provide prioritized interrupts to the CPU
Clock Mode Select
Selects the source and type of system clock
Port ADA
ADC digital input port signals
Port C
SIM digital output port signals
Port E
SIM digital I/O port signals
Port F
SIM digital I/O port signals
Quotient Out
Provides the quotient bit of the polynomial divider
Reset
System reset
Read-Modify-Write Cycle Indicates an indivisible read-modify-write instruction
Read/Write
Indicates the direction of data transfer on the bus
Size
Indicates the number of bytes to be transferred during a bus cycle
TPU I/O Channels
Bidirectional TPU channels
Three-State Control
Places all output drivers in a high-impedance state
TCR2 Clock
TPU clock input
ADC Reference Voltage Provide precise reference for A/D conversion
External Filter Capacitor Connection for external phase-locked loop filter capacitor
MC68334
MC68334TS/D
3 System Integration Module
The MCU system integration module (SIM) consists of five functional blocks that control system startup, initialization, configuration, and external bus.
SYSTEM CONFIGURATION
AND PROTECTION
CLOCK SYNTHESIZER
CHIP SELECTS
CLKOUT
EXTAL
MODCLK
CHIP SELECTS
EXTERNAL BUS
EXTERNAL BUS INTERFACE
RESET
FACTORY TEST
TSC
FREEZE/QUOT
S(C)IM BLOCK
Figure 4 SIM Block Diagram
3.1 Overview
The system configuration and protection block controls MCU configuration and operating mode. The
block also provides bus and software watchdog monitors.
The system clock generates clock signals used by the SIM, other IMB modules, and external devices.
In addition, a periodic interrupt generator supports execution of time-critical control routines.
The external bus interface handles the transfer of information between IMB modules and external address space.
The chip-select block provides eleven general-purpose chip-select signals and a boot ROM chip select
signal. Both general-purpose and boot ROM chip-select signals have associated base address registers and option registers.
The system test block incorporates hardware necessary for testing the MCU. It is used to perform factory tests, and its use in normal applications is not supported.
The SIM control register address map occupies 128 bytes. Unused registers within the 128-byte address space return zeros when read. The “Access” column in the SIM address map below indicates
which registers are accessible only at the supervisor privilege level and which can be assigned to either
the supervisor or user privilege level, according to the value of the SUPV bit in the SIMCR.
MC68334
MC68334TS/D REV. 1
11
Table 7 SIM Address Map
Access
S
S
S
S
S
S
S
S
S/U
S/U
S/U
S
S/U
S/U
S/U
S
S
Address
$YFFA00
$YFFA02
$YFFA04
$YFFA06
$YFFA08
$YFFA0A
$YFFA0C
$YFFA0E
$YFFA10
$YFFA12
$YFFA14
$YFFA16
$YFFA18
$YFFA1A
$YFFA1C
$YFFA1E
$YFFA20
S
S
S
S
S
S
S
S
S
S
S
S
S/U
$YFFA22
$YFFA24
$YFFA26
$YFFA28
$YFFA2A
$YFFA2C
$YFFA2E
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
$YFFA3C
$YFFA3E
$YFFA40
$YFFA42
$YFFA44
$YFFA46
$YFFA48
$YFFA4A
$YFFA4C
$YFFA4E
$YFFA50
$YFFA52
$YFFA54
$YFFA56
$YFFA58
$YFFA5A
$YFFA5C
S/U
S
S
S
S
S
S
S
S
S
S
S
S
S
12
15
8 7
0
SIM MODULE CONFIGURATION REGISTER (SIMCR)
FACTORY TEST REGISTER (SIMTR)
CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR)
NOT USED
RESET STATUS REGISTER (RSR)
MODULE TEST E (SIMTRE)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PORT E DATA (PORTE0)
NOT USED
PORT E DATA (PORTE1)
NOT USED
PORT E DATA DIRECTION (DDRE)
NOT USED
PORT E PIN ASSIGNMENT (PEPAR)
NOT USED
PORT F DATA (PORTF0)
NOT USED
PORT F DATA (PORTF1)
NOT USED
PORT F DATA DIRECTION (DDRF)
NOT USED
PORT F PIN ASSIGNMENT (PFPAR)
NOT USED
SYSTEM PROTECTION CONTROL
(SYPCR)
PERIODIC INTERRUPT CONTROL REGISTER (PICR)
PERIODIC INTERRUPT TIMING REGISTER (PITR)
NOT USED
SOFTWARE SERVICE (SWSR)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
TEST MODULE MASTER SHIFT A (TSTMSRA)
TEST MODULE MASTER SHIFT B (TSTMSRB)
TEST MODULE SHIFT COUNT (TSTSC)
TEST MODULE REPETITION COUNTER (TSTRC)
TEST MODULE CONTROL (CREG)
TEST MODULE DISTRIBUTED REGISTER (DREG)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PORT C DATA (PORTC)
NOT USED
NOT USED
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
CHIP-SELECT BASE BOOT (CSBARBT)
CHIP-SELECT OPTION BOOT (CSORBT)
CHIP-SELECT BASE 0 (CSBAR0)
CHIP-SELECT OPTION 0 (CSOR0)
CHIP-SELECT BASE 1 (CSBAR1)
CHIP-SELECT OPTION 1 (CSOR1)
CHIP-SELECT BASE 2 (CSBAR2)
CHIP-SELECT OPTION 2 (CSOR2)
CHIP-SELECT BASE 3 (CSBAR3)
CHIP-SELECT OPTION 3 (CSOR3)
CHIP-SELECT BASE 4 (CSBAR4)
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Table 7 SIM Address Map
Access
S
S
S
S
S
S
S
S
S
S
S
S
S
Address
$YFFA5E
$YFFA60
$YFFA62
$YFFA64
$YFFA66
$YFFA68
$YFFA6A
$YFFA6C
$YFFA6E
$YFFA70
$YFFA72
$YFFA74
$YFFA76
15
8 7
CHIP-SELECT OPTION 4 (CSOR4)
CHIP-SELECT BASE 5 (CSBAR5)
CHIP-SELECT OPTION 5 (CSOR5)
CHIP-SELECT BASE 6 (CSBAR6)
CHIP-SELECT OPTION 6 (CSOR6)
CHIP-SELECT BASE 7 (CSBAR7)
CHIP-SELECT OPTION 7 (CSOR7)
CHIP-SELECT BASE 8 (CSBAR8)
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
CHIP-SELECT OPTION 10 (CSOR10)
0
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
3.2 System Configuration and Protection Block
This functional block provides configuration control for the entire MCU. It also performs interrupt arbitration, bus monitoring, and system test functions. MCU system protection includes a bus monitor, a
HALT monitor, a spurious interrupt monitor, and a software watchdog timer. These functions have been
made integral to the microcontroller to reduce the number of external components in a complete control
system.
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13
MODULE CONFIGURATION
AND TEST
RESET STATUS
HALT MONITOR
RESET REQUEST
BUS MONITOR
BERR
SPURIOUS INTERRUPT MONITOR
SOFTWARE WATCHDOG TIMER
CLOCK
RESET REQUEST
29
PRESCALER
IRQ [7:1]
PERIODIC INTERRUPT TIMER
SYS PROTECT BLOCK
Figure 5 System Configuration and Protection Block
3.2.1 System Configuration
The SIM controls MCU configuration during normal operation and during internal testing.
SIMCR — SIM Configuration Register
$YFFA00
15
14
13
12
11
10
EXOFF
FRZSW
FRZBM
0
SLVEN
0
0
0
DATA11
0
9
8
SHEN
7
6
5
4
SUPV
MM
0
0
1
1
0
0
3
2
1
0
1
1
IARB
RESET:
0
0
0
0
1
1
The SIM configuration register controls system configuration. It can be read or written at any time, except for the module mapping (MM) bit, which can be written only once.
14
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EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts during software debug.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
This bit is a read-only status bit that reflects the state of DATA11 during reset.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations. A
show cycle allows internal transfers to be externally monitored. The table below shows whether show
cycle data is driven externally, and whether external bus arbitration can occur. To prevent bus conflict,
external peripherals must not be enabled during show cycles.
SHEN
00
01
10
11
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled,
internal activity is halted by a bus grant
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or supervisor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request. An IARB field must have a nonzero value for contention to take place.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU processes a spurious interrupt exception. Because the SIM routes external interrupt requests to the CPU,
the SIM IARB field value is used for arbitration between internal and external interrupts of the same priority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is
%0000, which prevents SIM interrupts from being discarded during initialization.
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15
3.2.2 System Protection Control Register
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. This register can be written only once following power-on or reset,
but can be read at any time.
SYPCR — System Protection Control Register
15
14
13
12
11
10
9
$YFFA21
8
NOT USED
7
6
SWE
SWP
1
MODCLK
5
4
SWT
3
2
HME
BME
0
0
1
0
BMT
RESET:
0
0
0
0
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following table gives the ratio for each combination of SWP and SWT bits.
SWP
0
SWT
00
Ratio
0
01
211
0
10
213
0
11
215
1
00
218
1
01
220
1
10
222
1
11
224
29
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
BMT
00
01
10
11
16
Bus Monitor Time-out Period
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
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3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cycle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhibited by the HME bit in the SYPCR.
3.2.5 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-acknowledge cycle.
3.2.6 Software Watchdog
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog times out and issues a reset. This register can be written at any time, but returns zeros when read.
SWSR — Software Service Register
15
14
13
12
11
$YFFA27
10
9
8
NOT USED
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
Register shown with read value
Perform a software watchdog service sequence as follows:
• Write $55 to SWSR.
• Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be executed between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
MODCLK
0
1
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SWP
1
0
17
3.2.7 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
PICR — Periodic Interrupt Control Register
15
14
13
12
11
0
0
0
0
0
0
0
0
0
10
$YFFA22
9
8
7
6
5
4
PIRQL
3
2
1
0
1
1
1
1
PIV
RESET:
0
0
0
0
0
0
0
0
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
The following table shows what interrupt request level is asserted when a periodic interrupt is generated. If a PIT interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT interrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.
PIRQL
000
001
010
011
100
101
110
111
Interrupt Request Level
Periodic Interrupt Disabled
Interrupt Request Level 1
Interrupt Request Level 2
Interrupt Request Level 3
Interrupt Request Level 4
Interrupt Request Level 5
Interrupt Request Level 6
Interrupt Request Level 7
PIV[7:0] — Periodic Interrupt Vector
The bits of this field contain the vector generated in response to an interrupt from the periodic timer.
When the SIM responds, the periodic interrupt vector is placed on the bus.
PITR — Periodic Interrupt Timer Register
$YFFA24
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
PTP
0
0
0
0
0
0
MODCLK
7
6
5
4
3
2
1
0
0
0
0
0
PITM
RESET:
0
0
0
0
0
The PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This
register can be read or written at any time.
PTP — Periodic Timer Prescaler Control
0 = Periodic timer clock not prescaled
1 = Periodic timer clock prescaled by a value of 512
The reset state of PTP is the complement of the state of the MODCLK signal during reset.
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PITM[7:0] — Periodic Interrupt Timing Modulus Field
This is an 8-bit timing modulus. The period of the timer can be calculated as follows:
( PITM ) ( Prescale ) ( 4 )
PIT Period = -------------------------------------------------------EXTAL Frequency
where
PIT Period = Periodic interrupt timer period
PITM = Periodic interrupt timer register modulus (PITR[7:0])
EXTAL Frequency = Crystal frequency
Prescale = 512 or 1 depending on the state of the PTP bit in the PITR
3.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral
bus. Because the MCU is a fully static design, register and memory contents are not affected when the
clock rate changes. System hardware and software support changes in clock rate during operation.
The system clock signal can be generated in one of three ways. An internal phase-locked loop can synthesize the clock from either an internal reference or an external reference, or the clock signal can be
input from an external frequency source. Keep these clock sources in mind while reading the rest of this
section. The figure below is a block diagram of the system clock.
EXTAL
XTAL
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
XFC
VDDSYN
LOW-PASS
FILTER
VCO
FEEDBACK DIVIDER
SYSTEM CLOCK CONTROL
CLKOUT
W
Y
X
SYSTEM
CLOCK
32 PLL BLOCK
Figure 6 System Clock Block Diagram
3.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source. When MODCLK is
held high during reset, the clock synthesizer generates a clock signal from either an internal or an external reference frequency — the clock synthesizer control register (SYNCR) determines operating frequency and mode of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled and an external system clock signal must be applied — SYNCR control bits have no effect.
To generate a reference frequency using the internal oscillator a reference crystal must be connected
between the EXTAL and XTAL pins. The figure below shows a recommended circuit.
MC68334
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19
C1
22 pF*
R1
330k
XTAL
VSSI
C2
22 pF*
EXTAL
* RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
32 OSCILLATOR
Figure 7 System Clock Oscillator Circuit
If an external reference signal or an external system clock signal is applied via the EXTAL pin, the XTAL
pin must be left floating. External reference signal frequency must be less than or equal to maximum
specified reference frequency. External system clock signal frequency must be less than or equal to
maximum specified system clock frequency.
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during reset), the duty
cycle of the input is critical, especially at operating frequencies close to maximum. The relationship between clock signal duty cycle and clock signal period is expressed:
Minimum External Clock Period =
Minimum External Clock High § Low Time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------50% – Percentage Variation of External Clock Input Duty Cycle
3.3.2 Clock Synthesizer Operation
VDDSYN is used to power the clock circuits when either an internal or an external reference frequency
is applied. A separate power source increases MCU noise immunity and can be used to run the clock
when the MCU is powered down. A quiet power supply must be used as the VDDSYN source. Adequate
external bypass capacitors should be placed as close as possible to the VDDSYN pin to assure stable
operating frequency. When an external system clock signal is applied and the PLL is disabled, VDDSYN
should be connected to the VDD supply. Refer to the SIM Reference Manual (SIMRM/AD) for more information regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty
cycle, VCO frequency is either two or four times system clock frequency, depending on the state of the
X bit in SYNCR. A portion of the clock signal is fed back to a divider/counter. The divider controls the
frequency of one input to a phase comparator. The other phase comparator input is a reference signal,
either from the crystal oscillator or from an external source. The comparator generates a control signal
proportional to the difference in phase between the two inputs. The signal is low-pass filtered and used
to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock stability. The figure below shows two recommended filters. XFC pin leakage must be kept within specified limits to maintain optimum stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock signal
is applied and the PLL is disabled. The XFC pin must be left floating in this case.
20
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MC68334TS/D REV. 1
C1
0.1µF
C3
0.1µF
C3
0.1µF
C1
0.1µF R1
18kΩ
XFC1
VDDSYN
VSSI
C4
0.01µF
VSSI
NORMAL OPERATING
ENVIRONMENT
XFC1, 2
C2
0.01µF
C4
0.01µF
VDDSYN
HIGH-STABILITY OPERATING
ENVIRONMENT
1. MAINTAIN LOW LEAKAGE ON THE XFC NODE.
2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW-FREQUENCY NOISE.
16/32 XFC CONN
Figure 8 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time is affected by the
filter time constant and by the amount of difference between the two comparator inputs. Whenever comparator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in SYNCR.
During power-up, the MCU does not come out of reset state until the synthesizer locks. Crystal type,
characteristic frequency, and layout of external oscillator circuitry affect lock time.
When the clock synthesizer is used, control register SYNCR determines operating frequency and various modes of operation. The SYNCR W bit controls a three-bit prescaler in the feedback divider. Setting
W increases VCO speed by a factor of four. The SYNCR Y field determines the count modulus for a
modulo 64 down counter, causing it to divide by a value of Y + 1. When W or Y values change, VCO
frequency changes, and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit
that is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is enabled, and system
clock frequency is one-fourth VCO frequency; setting X disables the divider, doubling clock speed without changing VCO speed. There is no relock delay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
F SYSTEM = F REFERENCE [ 4 ( Y + 1 ) ( 2
2W + X
)]
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by the W, X, and Y bits
must be within the limits specified for the MCU. Do not use a combination of bit values that selects either
an operating frequency or a VCO frequency greater than the maximum specified values.
3.3.3 External Bus Clock
The state of the external clock division bit (EDIV) in SYNCR determines clock rate for the external bus
clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can be set to system clock frequency divided by eight or system clock frequency
divided by sixteen. The clock is enabled by the CS10 field in chip select pin assignment register 1
(CSPAR1). ECLK operation during low-power stop is described in the following paragraph. Refer to 3.5
Chip Selects for more information about the external bus clock.
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21
3.3.4 Low-Power Operation
Low-power operation is initiated by the CPU32. To reduce power consumption selectively, the CPU can
set the STOP bits in each module configuration register. To minimize overall microcontroller power consumption, the CPU can execute the LPSTOP instruction, which causes the SIM to turn off the system
clock.
When individual module STOP bits are set, clock signals inside each module are turned off, but module
registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt
mask into the clock control logic. The SIM brings the MCU out of low-power operation when either an
interrupt of higher priority than the stored mask or a reset occurs.
During a low-power stop, unless the system clock signal is supplied by an external source and that
source is removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate.
The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK. The
SIM can also continue to generate the CLKOUT signal while in low-power mode.
The stop mode system integration module clock (STSIM) and stop mode external clock (STEXT) bits in
SYNCR determine clock operation during low-power stop. The table below summarizes the effects of
STSIM and STEXT. MODCLK value is the logic level on the MODCLK pin during the last reset before
LPSTOP execution. Any clock in the off state is held low. If the synthesizer VCO is turned off during
LPSTOP, there is a PLL relock delay after the VCO is turned back on.
Table 8 Clock Control
Mode
LPSTOP
No
Pins
MODCLK
0
Yes
0
Yes
0
Yes
0
Yes
0
No
1
Yes
1
Yes
1
Yes
1
Yes
1
EXTAL
External
Clock
External
Clock
External
Clock
External
Clock
External
Clock
Crystal or
Reference
Crystal or
Reference
Crystal or
Reference
Crystal or
Reference
Crystal or
Reference
SYNCR Bits
STSIM
STEXT
X
X
0
0
0
1
1
0
1
1
X
X
0
0
0
1
1
1
SIMCLK
External
Clock
External
Clock
External
Clock
External
Clock
External
Clock
VCO
Clock Status
CLKOUT
External
Clock
Off
ECLK
External
Clock
Off
External
Clock
Off
External
Clock
Off
External
Clock
VCO
External
Clock
VCO
Off
Off
Crystal/
Reference
Off
Off
0
Crystal or
Reference
Crystal or
Reference
VCO
1
VCO
VCO
VCO
Off
3.3.5 Loss of Reference Signal
The state of the reset enable (RSTEN) bit in SYNCR determines what happens when clock logic detects
a reference failure.
When RSTEN is cleared (default state out of reset), the clock synthesizer is forced into an operating
condition referred to as limp mode. Limp mode frequency varies from device to device, but maxi-
22
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MC68334TS/D REV. 1
mum limp frequency does not exceed one half maximum system clock when X = 0, or maximum
system clock frequency when X = 1.
When RSTEN is set, the SIM resets the MCU.
The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a reference signal. It is set
when a reference failure is detected.
3.3.6 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circumstances, such as following loss of synthesizer reference or during low-power operation. Clock source is
determined by the logic state of the MODCLK pin during reset.
SYNCR — Clock Synthesizer Control Register
15
14
W
X
13
12
11
10
9
$YFFA04
8
Y
7
6
5
4
3
2
1
0
EDIV
0
0
SLIMP
SLOCK
RSTEN
STSIM
STEXT
0
0
0
U
U
0
0
0
RESET:
0
0
1
1
1
1
1
1
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.
The SYNCR can be read or written only when the CPU is operating at the supervisor privilege level.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X — Frequency Control Bit (Prescale)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting the bit
doubles clock speed without changing the VCO speed. There is no VCO relock delay.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from 0 to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.5 Chip Selects for more
information.
SLIMP — Limp Mode Flag
0 = External crystal is VCO reference.
1 = Loss of crystal reference.
When the on-chip synthesizer is used, loss of reference frequency causes SLIMP to be set. The VCO
continues to run using the base control voltage. Maximum limp frequency is maximum specified system
clock frequency. X-bit state affects limp frequency.
SLOCK — Synthesizer Lock Flag
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency (or system clock is external).
The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer
lock status until after the user writes to SYNCR.
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23
RSTEN — Reset Enable
0 = Loss of crystal causes the MCU to operate in limp mode.
1 = Loss of crystal causes system reset.
STSIM — Stop Mode SIM Clock
0 = When LPSTOP is executed, the SIM clock is driven from the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SIM clock is driven from the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven from the SIM clock, as determined by
the state of the STSIM bit.
3.4 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external devices. The external bus has 24 address lines and 16 data lines.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). Multiple bus cycles
may be required for a transfer to or from an 8-bit port.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic can be synchronized with EBI transfers. Chip-select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.5 Chip Selects for more information.
3.4.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The following table shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only changes state when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two
consecutive write cycles.
Table 9 Size Signal Encoding
SIZ1
0
1
1
0
24
SIZ0
1
0
1
0
Transfer Size
Byte
Word
3 Byte
Long Word
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3.4.2 Function Codes
The CPU32 automatically generates function code signals FC[2:0]. The function codes can be considered address extensions that automatically select one of eight address spaces to which an address applies. These spaces are designated as either user or supervisor, and program or data spaces. Address
space seven is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 10 CPU32 Address Space Encoding
FC2
0
0
0
0
1
1
1
1
FC1
0
0
1
1
0
0
1
1
FC0
0
1
0
1
0
1
0
1
Address Space
Reserved
User Data Space
User Program Space
Reserved
Reserved
Supervisor Data Space
Supervisor Program Space
CPU Space
3.4.3 Address Bus
Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted.
3.4.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and the validity of many
control signals. It is asserted one-half clock after the beginning of a bus cycle.
3.4.5 Data Bus
Data bus signals DATA[15:0] make up a bidirectional, nonmultiplexed parallel bus that transfers data to
or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During a
read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For a
write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MCU
places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.4.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
3.4.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1
and DSACK0). During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data.
During a write cycle, the signals indicate that an external device has successfully stored data and that
the cycle can end. These signals also indicate to the MCU the size of the port for the bus cycle just completed. (Refer to 3.4.9 Dynamic Bus Sizing).
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT
are asserted simultaneously, the CPU takes a bus error exception.
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25
Autovector signal (AVEC) can terminate external IRQ pin interrupt acknowledge cycles. AVEC indicates
that the MCU will internally generate a vector number to locate an interrupt handler routine. If it is continuously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored
during all other bus cycles.
3.4.8 Data Transfer Mechanism
The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge
inputs (DSACK1 and DSACK0).
3.4.9 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0
and DSACK1 inputs, as shown in the following table.
Table 11 Effect of DSACK Signals
DSACK1
1
1
0
0
DSACK0
1
0
1
0
Result
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word operation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are designated as shown in the following figure. OP0 is the most significant byte of a long-word operand, and
OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and
OP1. The single byte of a byte-length operand is OP0.
Operand
Byte Order
31
Long Word
Three Byte
Word
24
OP0
23
16
15
8
7
0
OP1
OP2
OP3
OP0
OP1
OP2
OP0
Byte
OP1
OP0
Figure 9 Operand Byte Order
26
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3.4.10 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the
remaining number of bytes to be transferred during the current bus cycle. The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base.
3.4.11 Misaligned Operands
CPU32 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address
is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is
misaligned at an odd address. The MCU does not support misaligned operand transfers.
The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU
transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the
first bus cycle and the least significant operand word on a following bus cycle.
3.4.12 Operand Transfer Cases
The following table summarizes how operands are aligned for various types of transfers. OPn entries
are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,
SIZ0, and ADDR0 for that bus cycle.
Table 12 Operand Alignment
Transfer Case
SIZ1
SIZ0
ADDR0
DSACK1
DSACK0
0
0
0
1
1
1
1
1
0
0
X
0
1
0
1
1
0
0
1
1
Word to 16-Bit Port (Misaligned)2
1
1
0
0
0
1
3 Byte to 8-Bit Port (Aligned)3
1
1
3 Byte to 8-Bit Port (Misaligned)2, 3
1
1
3 Byte to 16-Bit Port (Aligned)3
1
3 Byte to 16-Bit Port (Misaligned)2, 3
1
Long Word to 8-Bit Port (Aligned)
Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)2
Word to 16-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)2
Long Word to 16-Bit Port (Aligned)
Long Word to 16-Bit Port (Misaligned)2
0
X
X
0
0
DATA
[15:8]
OP0
OP0
(OP0)
OP0
OP0
DATA
[7:0]
(OP0)1
(OP0)
OP0
(OP1)
(OP0)
0
0
X
X
OP0
(OP0)
OP1
OP0
0
1
0
OP0
(OP1)
1
1
0
OP0
(OP0)
1
0
0
X
OP0
OP1
1
1
0
X
(OP0)
OP0
0
1
0
0
0
1
1
1
0
0
OP0
OP0
(OP1)
(OP0)
0
1
0
0
0
1
0
0
X
X
OP0
(OP0)
OP1
OP0
1. Operands in parentheses are ignored by the CPU32 during read cycles.
2. The CPU32 does not support misaligned word or long-word transfers.
3. Three-byte transfer cases occur only as a result of a long word to byte transfer.
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27
3.5 Chip Selects
Typical microcontrollers require additional hardware to provide external chip-select and address decode signals. The MCU includes 12 programmable chip-select circuits that can provide 2- to 20-clockcycle access to external memory and peripherals. Address block sizes of two Kbytes to one Mbyte can
be selected. The figure below is a functional diagram of a chip-select circuit.
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobe, or interrupt acknowledge signals. Chip select logic can also generate DSACK and AVEC signals
internally. Each signal can also be synchronized with the ECLK signal available on ADDR23.
INTERNAL
SIGNALS
BASE ADDRESS REGISTER
ADDRESS
ADDRESS COMPARATOR
BUS CONTROL
OPTION COMPARE
TIMING
AND
CONTROL
PIN
OPTION REGISTER
AVEC
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
DSACK
CHIP SEL BLOCK
Figure 10 Chip-Select Circuit Block Diagram
When a memory access occurs, chip-select logic compares address space type, address, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select signals are active low. If a chip-select function is given the same address as a microcontroller module or
an internal memory array, an access to that address goes to the module or array, and the chip-select
signal is not asserted. The external address and data buses do not reflect the internal access.
All chip-select circuits are configured for operation out of reset. However, all chip-select signals except
CSBOOT are disabled, and cannot be asserted until the BYTE field in the corresponding option register
is programmed to a nonzero value, selecting a transfer size. The chip-select option register must not be
written until a base address has been written to a proper base address register. CSBOOT is automatically asserted out of reset. Alternate functions for chip-select pins are enabled if appropriate data bus
pins are held low at the release of the reset signal.
The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.
28
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Table 13 Chip Select Allocation
Pin
CSBOOT
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
Discrete Outputs
—
—
—
—
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
3.5.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Chip-select pin assignment registers (CSPAR[0:1]) determine functions of the pins. Pin assignment registers also determine port size (8- or 16bit) for dynamic bus allocation. A pin data register (PORTC) latches data for chip-select pins that are
used for discrete output.
Blocks of addresses are assigned to each chip-select function. Block sizes of two Kbytes to one Mbyte
can be selected by writing values to the appropriate base address register (CSBAR[0:10], CSBARBT).
Address blocks for separate chip-select functions can overlap.
Chip select option registers (CSOR[0:10], CSORBT) determine timing of and conditions for assertion of
chip-select signals. Eight parameters, including operating mode, access size, synchronization, and wait
state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the chip-select circuits. A set of special chip-select functions and registers (CSORBT, CSBARBT) is provided to support
bootstrap operation.
3.5.2 Pin Assignment Registers
The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that determine functions of the chip-select pins. Each pin has two or three possible functions, as shown below.
Table 14 Chip-Select Pin Functions
Assignment
Register
CSPAR0
CSPAR1
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16-Bit
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
8-Bit
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
Alternate
Function
CSBOOT
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
Discrete Output
—
—
—
—
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
29
The table below shows pin assignment field encoding. Pins that have no discrete output function do not
use the %00 encoding.
Table 15 Pin Assignment Encodings
Bit Field
00
01
10
11
Description
Discrete Output
Alternate Function
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
CSPAR0 — Chip Select Pin Assignment Register 0
15
14
0
0
13
12
CSPA0[6]
11
10
CSPA0[5]
9
8
CSPA0[4]
$YFFA44
7
6
CSPA0[3]
5
4
CSPA0[2]
3
2
CSPA0[1]
1
0
CSBOOT
RESET:
0
0
DATA2
1
DATA2
1
DATA2
1
DATA1
1
DATA1
1
DATA1
1
1
DATA0
CSPAR0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR0[15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always
reads one; writes to CSPAR0 bit 1 have no effect.
Table 16 CSPAR0 Pin Assignments
CSPAR0 Field
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
Chip Select Signal
CS5
CS4
CS3
CS2
CS1
CS0
CSBOOT
Alternate Signal
FC2
FC1
FC0
BGACK
BG
BR
—
Discrete Output
PC2
PC1
PC0
—
—
—
—
CSPAR1 — Chip Select Pin Assignment Register 1
15
14
13
12
11
10
9
8
0
0
0
0
0
0
CSPA1[4]
0
0
0
0
0
$YFFA46
7
6
CSPA1[3]
5
4
CSPA1[2]
3
2
CSPA1[1]
1
0
CSPA1[0]
RESET:
0
DATA7
1
DATA
[7:6]
1
DATA
[7:5]
1
DATA
[7:4]
1
DATA
[7:3]
1
CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR1[15:10] are not used. These bits always read zero; writes have no effect.
Table 17 CSPAR1 Pin Assignments
CSPAR1 Field
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
30
Chip Select Signal
CS10
CS9
CS8
CS7
CS6
Alternate Signal
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
Discrete Output
ECLK
PC6
PC5
PC4
PC3
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Port size determines the way in which bus transfers to an external address are allocated. Port size of
eight bits or sixteen bits can be selected when a pin is assigned as a chip select. Port size and transfer
size affect how the chip-select signal is asserted. Refer to 3.5.4 Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin.
These pins have weak internal pull-up drivers, but can be held low by external devices. Either 16-bit
chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the
boot ROM select pin (CSBOOT) are disabled out of reset. There are twelve chip-select functions and
only eight associated data bus pins. There is not a one-to-one correspondence. The table below shows
reset states.
Table 18 Reset Pin Function of CS[10:6]
DATA7
1
1
1
1
1
0
Data Bus Pins at Reset
DATA6
DATA5
DATA4
1
1
1
1
0
X
1
1
1
0
X
X
1
1
0
X
X
X
DATA3
1
0
X
X
X
X
Chip-Select/Address Bus Pin Function
CS10/
CS9/
CS8/
CS7/
CS6/
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
CS10
CS9
CS8
CS7
CS6
CS10
CS9
CS8
CS7
ADDR19
CS10
CS9
CS8
ADDR20 ADDR19
CS10
CS9
ADDR21 ADDR20 ADDR19
CS10
ADDR22 ADDR21 ADDR20 ADDR19
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
The CSBOOT signal is normally enabled out of reset. The state of the DATA0 line during reset determines what port width CSBOOT uses. If DATA0 is held high (either by the weak internal pull-up driver
or by an external pull-up device), 16-bit width is selected. If DATA0 is held low, 8-bit port size is selected.
A pin programmed as a discrete output drives an external signal to the value specified in the pin data
register. No discrete output function is available on pins CSBOOT, BR, BG, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select logic still functions and can be used to generate DSACK or AVEC internally on an address and control signal match.
3.5.3 Base Address Registers
Each chip select has an associated base address register. A base address is the lowest address in the
block of addresses enabled by a chip select. Block size is the extent of the address block above the
base address. Block size is determined by the value contained in a BLKSZ field. Block addresses for
different chip selects can overlap.
The BLKSZ field determines which bits in the base address field are compared to corresponding bits on
the address bus during an access. Provided other constraints determined by option register fields are
also satisfied, when a match occurs, the associated chip-select signal is asserted.
The chip-select address compare logic uses only the most significant bits to match an address within a
block. The value of the base address must be a multiple of block size. Base address register diagrams
show how base register bits correspond to address lines.
After reset, the MCU fetches the initialization routine from the address contained in the reset vector, located beginning at address $000000 of program space. To support bootstrap operation from reset, the
base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros.
A memory device containing the reset vector and initialization routine can be automatically enabled by
CSBOOT after a reset. The block size field in CSBARBT has a reset value of 512 Kbytes.
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31
CSBARBT — Chip-Select Base Address Register Boot ROM
$YFFA48
15
14
13
12
11
10
9
8
7
6
5
4
3
2
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
0
0
0
0
0
0
0
0
0
0
0
0
1
0
BLKSZ
RESET:
0
CSBAR[10:0] — Chip-Select Base Address Registers
1
1
1
$YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
2
0
0
0
0
0
0
0
0
0
0
0
1
0
BLKSZ
RESET:
0
0
0
0
0
BLKSZ — Block Size Field
This field determines the size of the block that must be enabled by the chip select. The following table
shows bit encoding for the base address registers block size field.
Block Size Field
000
001
010
011
100
101
110
111
Block Size
2 Kbytes
8 Kbytes
16 Kbytes
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
1 Mbyte
Address Lines Compared
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
ADDR[23:11] — Base Address Field
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to address lines.
3.5.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chipselect signals. To assert a chip-select signal, and to provide DSACK or autovector support, other constraints set by fields in the option register and in the base address register must also be satisfied.
CSORBT — Chip-Select Option Register Boot ROM
15
14
MODE
13
12
BYTE
11
R/W
10
9
8
$YFFA4A
7
6
5
DSACK
STRB
4
3
SPACE
2
1
0
AVEC
IPL
RESET:
0
1
1
1
1
0
1
1
0
1
1
1
0
CSOR[10:0] — Chip-Select Option Registers
15
14
MODE
13
12
BYTE
11
R/W
10
9
0
0
$YFFA4E–$YFFA76
8
7
6
5
DSACK
STRB
0
4
3
SPACE
2
1
0
AVEC
IPL
RESET:
0
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC68334
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CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap operations from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected (chip-select assertion determined by internal or external bus control signals)
1 = Synchronous mode selected (chip-select assertion synchronized with ECLK signal)
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
The DSACK field is not used in synchronous mode because a bus cycle is only performed as a synchronous operation. When a match condition occurs on a chip select programmed for synchronous operation, the chip select signals the EBI that an ECLK cycle is pending.
BYTE — Upper/Lower Byte Option
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
Byte
00
01
10
11
Description
Disable
Lower Byte
Upper Byte
Both Bytes
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
Refer to the following table for options available.
R/W
00
01
10
11
Description
Reserved
Read Only
Write Only
Read/Write
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe causes chip select to be asserted synchronized with data strobe.
DSACK — Data and Size Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application. The following table shows the DSACK field encoding. The
fast termination encoding (1110) is used for two-cycle access to external memory.
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DSACK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
No Wait States
1 Wait State
2 Wait States
3 Wait States
4 Wait States
5 Wait States
6 Wait States
7 Wait States
8 Wait States
9 Wait States
10 Wait States
11 Wait States
12 Wait States
13 Wait States
Fast Termination
External DSACK
SPACE — Address Space
Use this option field to select an address space for the chip-select logic. The CPU32 normally operates
in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space.
Space
00
01
10
11
Address Space
CPU Space
User Space
Supervisor Space
Supervisor/User Space
IPL — Interrupt Priority Level
If the space field is set for CPU space (00), chip-select logic can be used for interrupt acknowledge.
During an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the
value in the IPL field. If the values are the same, a chip select is asserted, provided that other option
register conditions are met. The following table shows IPL field encoding.
IPL
000
001
010
011
100
101
110
111
Description
Any Level
IPL1
IPL2
IPL3
IPL4
IPL5
IPL6
IPL7
This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.
Any level means that chip select is asserted regardless of the level of the interrupt acknowledge cycle.
AVEC — Autovector Enable
0 = External interrupt vector enabled
1 = Autovector enabled
This field selects one of two methods of acquiring an interrupt vector number during an external interrupt
acknowledge cycle.
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If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE = 00) and the AVEC
field is set to one, the chip select circuit generates an internal AVEC signal in response to an external
interrupt cycle, and the SIM supplies an automatic vector number. Otherwise, the vector number must
be supplied by the requesting device. An internal autovector is generated only in response to interrupt
requests from the SIM IRQ pins — interrupt requests from other IMB modules are ignored.
The AVEC bit must not be used in synchronous mode, as autovector response timing can vary because
of ECLK synchronization.
3.5.5 Port C Data Register
Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is assigned as a discrete output, the value in this register appears at the output. This is a read/write register.
Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read.
PORTC — Port C Data Register
15
14
13
12
11
$YFFA41
10
9
8
NOT USED
7
6
5
4
3
2
1
0
0
PC6
PC5
PC4
PC3
PC2
PC1
PC0
0
1
1
1
1
1
1
1
RESET:
3.6 General-Purpose Input/Output
SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs describe registers that control the ports.
PORTE0, PORTE1 — Port E Data Register
15
14
13
12
11
10
9
$YFFA11, $YFFA13
8
NOT USED
7
6
5
4
3
2
1
0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
U
U
U
U
U
U
U
U
RESET:
A write to the port E data register is stored in the internal data latch and, if any port E pin is configured
as an output, the value stored for that bit is driven on the pin. A read of the port E data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port E data register is a single register that can be accessed in two locations. When accessed at
$YFFA11, the register is referred to as PORTE0; when accessed at $YFFA13, the register is referred
to as PORTE1. The register can be read or written at any time. It is unaffected by reset.
DDRE — Port E Data Direction Register
15
14
13
12
11
NOT USED
10
$YFFA15
9
8
7
6
5
4
3
2
1
0
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
0
0
0
0
0
0
0
0
RESET:
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time.
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PEPAR — Port E Pin Assignment Register
15
14
13
12
11
10
$YFFA17
9
8
NOT USED
7
6
5
4
3
2
1
0
PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
RESET:
DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8
The bits in this register control the function of each port E pin. Any bit set to one configures the corresponding pin as a bus control signal, with the function shown in the following table. Any bit cleared to
zero defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
Data bus bit 8 controls the state of this register following reset. If DATA8 is set to one during reset, the
register is set to $FF, which defines all port E pins as bus control signals. If DATA8 is cleared to zero
during reset, this register is set to $00, configuring all port E pins as I/O pins.
Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the
corresponding pin to be a bus control signal.
Table 19 Port E Pin Assignments
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
Port E Signal
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Bus Control Signal
SIZ1
SIZ0
AS
DS
RMC
AVEC
DSACK1
DSACK0
PORTF0, PORTF1 — Port F Data Register
15
14
13
12
11
10
$YFFA19, $YFFA1B
9
8
NOT USED
7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
U
U
U
U
U
U
U
U
RESET:
The write to the port F data register is stored in the internal data latch, and if any port F pin is configured
as an output, the value stored for that bit is driven onto the pin. A read of the port F data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port F data register is a single register that can be accessed in two locations. When accessed at
$YFFA19, the register is referred to as PORTF0; when accessed at $YFFA1B, the register is referred
to as PORTF1. The register can be read or written at any time. It is unaffected by reset.
DDRF — Port F Data Direction Register
15
14
13
12
11
NOT USED
10
$YFFA1D
9
8
7
6
5
4
3
2
1
0
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
0
0
0
0
0
0
0
0
RESET:
The bits in this register control the direction of the pin drivers when the pins are configured for I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input.
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PFPAR — Port F Pin Assignment Register
15
14
13
12
11
NOT USED
10
$YFFA1F
9
8
7
6
5
4
3
2
1
0
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
RESET:
DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9
The bits in this register control the function of each port F pin. Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request
signal or MODCLK. The MODCLK signal has no function after reset.
Table 20 Port F Pin Assignments
PFPAR Field
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
Port F Signal
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Alternate Signal
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
MODCLK
Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the
register is set to $FF, which defines all port F pins as interrupt request inputs. If DATA9 is cleared to
zero during reset, this register is set to $00, defining all port F pins as I/O pins.
3.7 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU performs resets with a combination of hardware and software. The system integration module determines
whether a reset is valid, asserts control signals, performs basic system configuration based on hardware mode-select inputs, then passes control to the CPU.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU32 exception. Any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
3.7.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition,
the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines
what happens during subsequent breakpoint assertions. The following table is a summary of reset
mode selection options.
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Table 21 Reset Mode Selection
Mode Select Pin
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA11
MODCLK
BKPT
Default Function
(Pin Left High)
CSBOOT 16-Bit
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
DSACK0, DSACK1,
AVEC, DS, AS,
SIZ[1:0]
IRQ[7:1]
MODCLK
Test Mode Disabled
VCO = System Clock
Background Mode Disabled
Alternate Function
(Pin Pulled Low)
CSBOOT 8-Bit
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
PORTE
PORTF
Test Mode Enabled
EXTAL = System Clock
Background Mode Enabled
Data lines have weak internal pull-up drivers. External bus loading can overcome the weak internal pullup drivers on data bus lines, and hold pins low during reset. Use an active device to hold data bus lines
low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent
conflict with external memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is
released. If external mode selection logic causes a conflict of this type, an isolation resistor on the driven
lines may be required.
3.7.2 Functions of Pins for Other Modules During Reset
Generally, pins associated with modules other than the SIM default to port functions, and input/output
ports are set to input state. This is accomplished by disabling pin functions in the appropriate control
registers, and by clearing the appropriate port data direction registers. Refer to individual module sections in this manual for more information. The following table is a summary of module pin function out
of reset.
Table 22 Module Pin Functions
Module
Pin Mnemonic
Function
CPU32
DSI/IFETCH
DSI/IFETCH
TPU
ADC
DSO/IPIPE
DSO/IPIPE
BKPT/DSCLK
BKPT/DSCLK
TPUCH[15:0]
TPU Input
T2CLK
TCR2 Clock
AN[6:0]/PADA[6:0]
Analog Input
3.7.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.
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When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cycles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the reset input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to highimpedance state for ten cycles, then it is tested again. The process repeats until RESET is released.
3.7.4 Power-On Reset
When the SIM clock synthesizer is used to generate the system clock, power-on reset involves special
circumstances related to application of system and clock synthesizer power. Regardless of clock
source, voltage must be applied to clock synthesizer power input pin VDDSYN in order for the MCU to
operate. The following discussion assumes that VDDSYN is applied before and during reset. This minimizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific
crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.
During power-on reset, an internal circuit in the SIM drives the internal IMB and external reset lines. The
circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SIM pins
are initialized. As VDD reaches specified minimum value, the clock synthesizer VCO begins operation
and clock frequency ramps up to specified limp mode frequency. The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and
VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15
milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buffers or isolation resistors to prevent conflict.
3.7.5 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for ten clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-on reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-up
time affects how long the ten cycles take. Worst case is approximately 20 ms from TSC assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-impedance
state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.
When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode
selection. Once the output drivers change state, the MCU must be powered down and restarted before
normal operation can resume.
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3.8 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
system integration module, and a device or module requesting interrupt service.
The CPU32 provides eight levels of interrupt priority. All interrupts with priorities less than seven can be
masked by the interrupt priority (IP) field in status register.
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally on the IMB, and
there are corresponding pins for external interrupt service requests. The CPU treats all interrupt requests as though they come from internal modules — external interrupt requests are treated as interrupt
service requests from the SIM. Each of the interrupt request signals corresponds to an interrupt priority
level. IRQ1 has the lowest priority and IRQ7 the highest.
Interrupt recognition is determined by interrupt priority level and interrupt priority mask value. The interrupt priority mask consists of three bits in the CPU32 status register. Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask
value from being recognized and processed. IRQ7, however, is always recognized, even if the mask
value is %111.
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted until an interrupt
acknowledge cycle corresponding to that level is detected.
IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling
edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A
nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask
changes from%111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete.
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request with a priority equal to or lower than the current IP mask value is made,
the CPU32 does not recognize the occurrence of the request. If simultaneous interrupt requests of different priorities are made, and both have a priority greater than the mask value, the CPU32 recognizes
the higher-level request.
3.8.1 Interrupt Acknowledge and Arbitration
When the CPU32 detects one or more interrupt requests of a priority higher than the interrupt priority
mask value, it places the interrupt request level on the address bus and initiates a CPU space read cycle. The request level serves two purposes: it is decoded by modules or external devices that have requested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to
them, and it is latched into the interrupt priority mask field in the CPU32 status register, to preclude further interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the interrupt priority
mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority
of the service request corresponds to the mask value. However, before modules or external devices
respond, interrupt arbitration takes place.
Arbitration is performed by means of serial contention between values stored in individual module interrupt arbitration (IARB) fields. Each module that can make an interrupt service request, including the
SIM, has an IARB field in its configuration register. IARB fields can be assigned values from %0000 to
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%1111. In order to implement an arbitration scheme, each module that can initiate an interrupt service
request must be assigned a unique, non-zero IARB field value during system initialization. Arbitration
priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an interrupt service
request from a source that has an IARB field value of %0000, a spurious interrupt exception is processed.
WARNING
Do not assign the same arbitration priority to more than one module. When two or
more IARB fields have the same nonzero value, the CPU32 interprets multiple vector numbers at the same time, with unpredictable consequences.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the
reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same priority, it always takes
place, even when a single source is requesting service. This is important for two reasons: the EBI does
not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention,
and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error.
When arbitration is complete, the module with the highest arbitration priority must terminate the bus
cycle. Internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination signals. In the case of an external interrupt request, after the interrupt acknowledge cycle is transferred to the external bus, the appropriate external device must decode the mask
value and respond with a vector number, then generate data and size acknowledge (DSACK) termination signals, or it must assert the autovector (AVEC) request signal. If the device does not respond in
time, the EBI bus monitor asserts the bus error signal BERR, and a spurious interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in response to interrupt
requests from external devices. Chip-select address match logic functions only after the EBI transfers
an interrupt acknowledge cycle to the external bus following IARB contention. If a module makes an
interrupt request of a certain priority, and the appropriate chip-select registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chipselect logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a
vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PICR) determines
PIT priority level. A PIRQ value of %000 means that PIT interrupts are inactive. By hardware convention, when the CPU32 receives simultaneous interrupt requests of the same level from more than one
SIM source (including external devices), the periodic interrupt timer is given the highest priority, followed
by the IRQ pins. Refer to 3.2.7 Periodic Interrupt Timer for more information.
3.8.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. The processor state is stacked. The S bit in the status register is set, establishing supervisor
access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
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3.
D.
E.
F.
G.
The request level is latched from the address bus into the interrupt priority mask field in the
status or condition code register.
Modules that have requested interrupt service decode the priority value in ADDR[3:1]. If request
priority is the same as acknowledged priority, arbitration by IARB contention takes place.
After arbitration, the interrupt acknowledge cycle is completed in one of the following ways:
1. When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR,
and the CPU generates the spurious interrupt vector number.
2. The dominant interrupt source supplies a vector number and DSACK signals appropriate
to the access. The CPU acquires the vector number.
3. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source
or the pin can be tied low), and the CPU generates an autovector number corresponding
to interrupt priority.
4. The bus monitor asserts BERR and the CPU32 generates the spurious interrupt vector
number.
The vector number is converted to a vector address.
The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.9 Factory Test Block
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production testing.
Test submodule registers are intended for Freescale use. Register names and addresses are provided
to indicate that these addresses are occupied.
SIMTR — System Integration Test Register
$YFFA02
SIMTRE — System Integration Test Register (E Clock)
$YFFA08
TSTMSRA — Master Shift Register A
$YFFA30
TSTMSRB — Master Shift Register B
$YFFA32
TSTSC — Test Module Shift Count
$YFFA34
TSTRC — Test Module Repetition Count
$YFFA36
CREG — Test Module Control Register
$YFFA38
DREG — Test Module Distributed Register
$YFFA3A
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4 Central Processor Unit
Based on the powerful MC68020, the CPU32 processing module provides enhanced system performance and also uses the extensive software base for the Freescale M68000 family.
4.1 Overview
The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calculation-intensive algorithms and supporting high-level languages. The CPU32 supports all of the
MC68010 and most of the MC68020 enhancements, such as virtual memory support, loop mode operation, instruction pipeline, and 32-bit mathematical operations. Powerful addressing modes provide
compatibility with existing software programs and increase the efficiency of high-level language compilers. Special instructions, such as table lookup and interpolate and low-power stop, support the specific
requirements of controller applications. Also included is the background debugging mode, an alternate
operating mode that suspends normal operation and allows the CPU to accept debugging commands
from the development system.
Ease of programming is an important consideration in using a microcontroller. The CPU32 instruction
set is optimized for high performance. The eight 32-bit general-purpose data registers readily support
8-bit (byte), 16-bit (word), and 32-bit (long word) operations. Ease of program checking and diagnosis
is further enhanced by trace and trap capabilities at the instruction level.
Use of high-level languages is increasing as controller applications become more complex and control
programs become larger. High-level languages aid rapid development of software, with less error, and
are readily portable. The CPU32 instruction set supports high-level languages.
4.2 Programming Model
The CPU32 has sixteen 32-bit general registers, a 32-bit program counter, one 32-bit supervisor stack
pointer, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register.
The programming model of the CPU32 consists of a user model and supervisor model, corresponding
to the user and supervisor privilege levels. Some instructions available at the supervisor level are not
available at the user level, allowing the supervisor to protect system resources from uncontrolled access. Bit S in the status register determines the privilege level.
The user programming model remains unchanged from previous M68000 Family microprocessors. Application software written to run at the non-privileged user level migrates without modification to the
CPU32 from any M68000 platform. The move from SR instruction, however, is privileged in the CPU32.
It is not privileged in the M68000.
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User Programming Model
31
16 15
8 7
0
D0
D1
D2
D3
Data Registers
D4
D5
D6
D7
31
16
15
0
A0
A1
A2
A3
Address Registers
A4
A5
A6
31
16
15
0
31
A7 (USP)
User Stack Pointer
PC
Program Counter
CCR
Condition Code Register
0
7
0
Supervisor Programming Model Supplement
31
16 15
15
0
8 7
A7' (SSP)
Supervisor Stack Pointer
SR
Status Register
VBR
Vector Base Register
SFC
Alternate Function
DFC
Code Registers
0
(CCR)
31
0
2
0
4.3 Status Register
The status register contains the condition codes that reflect the results of a previous operation and can
be used for conditional instruction execution in a program. The lower byte containing the condition
codes is the only portion of the register available at the user privilege level; it is referenced as the condition code register (CCR) in user programs. At the supervisor privilege level, software can access the
full status register, including the interrupt priority mask and additional control bits.
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SR — Status Register
15
14
13
12
11
T1
T0
S
0
0
0
1
0
0
10
9
8
IP
7
6
5
4
3
2
1
0
0
0
0
X
N
Z
V
C
0
0
0
U
U
U
U
U
RESET:
0
1
1
1
System Byte
T[1:0] — Trace Enable
S — Supervisor/User State
Bits [12:11] — Unimplemented
IP[2:0] — Interrupt Priority Mask
User Byte (Condition Code Register)
Bits [7:5] — Unimplemented
X — Extend
N — Negative
Z — Zero
V — Overflow
C — Carry
4.4 Data Types
Six basic data types are supported:
• Bits
• Packed Binary Coded Decimal Digits
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
4.5 Addressing Modes
Addressing in the CPU32 is register-oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory. This flexibility eliminates the need for extra
instructions to store register contents in memory. The CPU32 supports seven basic addressing modes:
• Register direct
• Register indirect
• Register indirect with index
• Program counter indirect with displacement
• Program counter indirect with index
• Absolute
• Immediate
Included in the register indirect addressing modes are the capabilities to post-increment, predecrement,
and offset. The program counter relative mode also has index and offset capabilities. In addition to
these addressing modes, many instructions implicitly specify the use of the status register, stack pointer, or program counter.
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45
4.6 Instruction Set Summary
Table 23 Instruction Set Summary
Instruction
ABCD
Syntax
Dn, Dn
– (An), – (An)
Dn, 〈ea〉
〈ea〉, Dn
〈ea〉, An
#〈data〉, 〈ea〉
#〈data〉, 〈ea〉
Dn, Dn
– (An), – (An)
〈ea〉, Dn
Dn, 〈ea〉
#〈data〉, 〈ea〉
#〈data〉, CCR
#〈data〉, SR
Operand Size
8
8
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8
16
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
BGND
〈label〉
Dn, 〈ea〉
#〈data〉, 〈ea〉
Dn, 〈ea〉
#〈data〉, 〈ea〉
none
8, 16, 32
8, 32
8, 32
8, 32
8, 32
none
BKPT
#〈data〉
none
BRA
BSET
CHK
CHK2
〈label〉
Dn, 〈ea〉
#〈data〉, 〈ea〉
〈label〉
Dn, 〈ea〉
#〈data〉, 〈ea〉
〈ea〉, Dn
〈ea〉, Rn
8, 16, 32
8, 32
8, 32
8, 16, 32
8, 32
8, 32
16, 32
8, 16, 32
CLR
CMP
CMPA
CMPI
CMPM
CMP2
〈ea〉
〈ea〉, Dn
〈ea〉, An
#〈data〉, 〈ea〉
(An) +, (An) +
〈ea〉, Rn
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR1
ASL
ASR
Bcc
BCHG
BCLR
BSR
BTST
46
Operation
Source10 + Destination10+ X ⇒ Destination
Source + Destination ⇒ Destination
Source + Destination ⇒ Destination
Immediate data + Destination ⇒ Destination
Immediate data + Destination ⇒ Destination
Source + Destination + X ⇒ Destination
Source ∗ Destination ⇒ Destination
Data ∗ Destination ⇒ Destination
Source ∗ CCR ⇒ CCR
Source ∗ SR ⇒ SR
X/C
0
X/C
If condition true, then PC + d ⇒ PC
(〈bit number〉 of destination) ⇒ Z ⇒
bit of destination
(〈bit number〉 of destination) ⇒ Z;
0 ⇒ bit of destination
If background mode enabled, then enter
background mode, else format/vector offset ⇒
– (SSP);
PC ⇒ – (SSP); SR ⇒ – (SSP); (vector) ⇒ PC
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
PC + d ⇒ PC
(〈bit number〉 of destination) ⇒ Z;
1 ⇒ bit of destination
SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC
(〈bit number〉 of destination) ⇒ Z
If Dn < 0 or Dn < (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
0 ⇒ Destination
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
(Destination – Data), CCR shows results
(Destination – Source), CCR shows results
Lower bound ≤ Rn ≤ Upper bound, CCR shows result
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Table 23 Instruction Set Summary
Instruction
DBcc
Syntax
Dn, 〈label〉
DIVS/DIVU
〈ea〉, Dn
DIVSL/DIVUL
〈ea〉, Dr: Dq
〈ea〉, Dq
〈ea〉, Dr : Dq
Dn, 〈ea〉
#〈data〉, 〈ea〉
#〈data〉, CCR
#〈data〉, SR
EOR
EORI
EORI to CCR
EORI to SR1
EXG
EXT
Operand Size
16
Operation
If condition false, then Dn – 1 ⇒ PC;
if Dn ≠ (– 1), then PC + d ⇒ PC
32/16 ⇒ 16: 16 Destination / Source ⇒ Destination
(signed or unsigned)
64/32 ⇒ 32 : 32 Destination / Source ⇒ Destination
(signed or unsigned)
32/32 ⇒ 32
32/32 ⇒ 32 : 32
8, 16, 32
Source ⊕ Destination ⇒ Destination
8, 16, 32
Data ⊕ Destination ⇒ Destination
8
Source ⊕ CCR ⇒ CCR
16
Source ⊕ SR ⇒ SR
Rn ⇒ Rn
Sign extended Destination ⇒ Destination
Rn, Rn
Dn
Dn
Dn
none
32
8 ⇒ 16
16 ⇒ 32
8 ⇒ 32
none
〈ea〉
〈ea〉
〈ea〉, An
An, #〈d〉
#〈data〉
none
none
32
16, 32
none
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
〈ea〉, 〈ea〉
〈ea〉, An
USP, An
An, USP
CCR, 〈ea〉
8, 16, 32
16, 32 ⇒ 32
32
32
16
MOVE from SR1
〈ea〉, CCR
SR, 〈ea〉
16
16
Source ⇒ CCR
SR ⇒ Destination
MOVE to SR1
〈εα〉, SR
16
Source ⇒ SR
MOVE USP1
USP, An
An, USP
Rc, Rn
Rn, Rc
list, 〈ea〉
〈ea〉, list
Dn, (d16, An)
32
32
32
32
16, 32
16, 32 ⇒ 32
16, 32
EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP1
LSL
LSR
MOVE
MOVEA
MOVEA1
MOVE from
CCR
MOVE to CCR
MOVEC1
MOVEM
MOVEP
(d16, An), Dn
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Sign extended Destination ⇒ Destination
SSP – 2 ⇒ SSP; vector offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP);
SSP – 2 ⇒ SSP; SR ⇒ (SSP);
illegal instruction vector address ⇒ PC
Destination ⇒ PC
SP – 4 ⇒ SP; PC ⇒ (SP); destination ⇒ PC
〈ea〉 ⇒ An
SP – 4 ⇒ SP, An ⇒ (SP); SP ⇒ An, SP + d ⇒ SP
Data ⇒ SR; interrupt mask ⇒ EBI; STOP
X/C
0
0
X/C
Source ⇒ Destination
Source ⇒ Destination
USP ⇒ An
An ⇒ USP
CCR ⇒ Destination
USP ⇒ An
An ⇒ USP
Rc ⇒ Rn
Rn ⇒ Rc
Listed registers ⇒ Destination
Source ⇒ Listed registers
Dn [31:24] ⇒ (An + d); Dn [23:16] ⇒ (An + d + 2);
Dn [15:8] ⇒ (An + d + 4); Dn [7:0] ⇒ (An + d + 6)
(An + d) ⇒ Dn [31:24]; (An + d + 2) ⇒ Dn [23:16];
(An + d + 4) ⇒ Dn [15:8]; (An + d + 6) ⇒ Dn [7:0]
47
Table 23 Instruction Set Summary
Instruction
MOVEQ
MOVES1
MULS/MULU
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR1
PEA
RESET1
ROL
Syntax
#〈data〉, Dn
Rn, 〈ea〉
〈ea〉, Rn
〈ea〉, Dn
〈ea〉, Dl
〈ea〉, Dh:Dl
〈ea〉
Operand Size
8 ⇒ 32
8, 16, 32
Operation
Immediate data ⇒ Destination
Rn ⇒ Destination using DFC
Source using SFC ⇒ Rn
Source ∗ Destination ⇒ Destination
(signed or unsigned)
〈ea〉
〈ea〉
none
〈ea〉
〈ea〉, Dn
Dn, 〈ea〉
#〈data〉, 〈ea〉
#〈data〉, CCR
#〈data〉, SR
16 ∗ 16 ⇒ 32
32 ∗ 32 ⇒ 32
32 ∗ 32 ⇒ 64
8
8
8, 16, 32
8, 16, 32
none
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
16
〈ea〉
none
32
none
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
0 – Destination10 – X ⇒ Destination
0 – Destination ⇒ Destination
0 – Destination – X ⇒ Destination
PC + 2 ⇒ PC
Destination ⇒ Destination
Source; Destination ⇒ Destination
Data; Destination ⇒ Destination
Source; CCR ⇒ SR
Source; SR ⇒ SR
SP – 4 ⇒ SP; 〈ea〉 ⇒ SP
Assert RESET line
C
ROR
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
C
ROXL
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
C
ROXR
Dn, Dn
#〈data〉, Dn
〈ea〉
X
8, 16, 32
8, 16, 32
16
X
RTD
RTE1
#〈d〉
none
16
none
RTR
none
none
RTS
SBCD
none
Dn, Dn
– (An), – (An)
〈ea〉
none
8
8
8
#〈data〉
16
〈ea〉, Dn
Dn, 〈ea〉
8, 16, 32
Scc
STOP1
SUB
48
C
(SP) ⇒ PC; SP + 4 + d ⇒ SP
(SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP;
restore stack according to format
(SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP
(SP) ⇒ PC; SP + 4 ⇒ SP
Destination10 – Source10 – X ⇒ Destination
If condition true, then destination bits are set to one;
else, destination bits are cleared to zero
Data ⇒ SR; STOP
Destination – Source ⇒ Destination
MC68334
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Table 23 Instruction Set Summary
Instruction
SUBA
SUBI
SUBQ
SUBX
SWAP
Syntax
〈ea〉, An
#〈data〉, 〈ea〉
#〈data〉, 〈ea〉
Dn, Dn
– (An), – (An)
Dn
Operand Size
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
Operation
Destination – Source ⇒ Destination
Destination – Data ⇒ Destination
Destination – Data ⇒ Destination
Destination – Source – X ⇒ Destination
MSW
TBLS/TBLU
〈ea〉, Dn
Dym : Dyn, Dn
8, 16, 32
TBLSN/TBLUN
〈ea〉, Dn
Dym : Dyn, Dn
8, 16, 32
TRAP
#〈data〉
none
TRAPcc
none
#〈data〉
none
〈ea〉
An
none
16, 32
none
8, 16, 32
32
TRAPV
TST
UNLK
LSW
Dyn – Dym ⇒ Temp
(Temp ∗ Dn [7:0]) ⇒ Temp
(Dym ∗ 256) + Temp ⇒ Dn
Dyn – Dym ⇒ Temp
(Temp ∗ Dn [7:0]) / 256 ⇒ Temp
Dym + Temp ⇒ Dn
SSP – 2 ⇒ SSP; format/vector offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);
vector address ⇒ PC
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Source – 0, to set condition codes
An ⇒ SP; (SP) ⇒ An, SP + 4 ⇒ SP
NOTE:
1. Privileged instruction
4.7 Background Debugging Mode
The background debugger on the CPU32 is implemented in CPU microcode. The background debugging commands are summarized below.
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49
Table 24 Background Debugging Command Summary
Command
Read D/A Register
Write D/A Register
Read System Register
Write System Register
Read Memory Location
Write Memory Location
Dump Memory Block
Fill Memory Block
Resume Execution
Patch User Code
Reset Peripherals
No Operation
50
Mnemonic
RDREG/RAREG
Description
Read the selected address or data register and return
the results through the serial interface.
WDREG/WAREG The data operand is written to the specified address
or data register.
RSREG
The specified system control register is read. All registers that can be read in supervisor mode can be
read in background mode.
WSREG
The operand data is written into the specified system
control register.
READ
Read the sized data at the memory location specified
by the long-word address. The source function code
register (SFC) determines the address space accessed.
WRITE
Write the operand data to the memory location specified by the long-word address. The destination function code (DFC) register determines the address
space accessed.
DUMP
Used in conjunction with the READ command to
dump large blocks of memory. An initial READ is executed to set up the starting address of the block and
retrieve the first result. Subsequent operands are retrieved with the DUMP command.
FILL
Used in conjunction with the WRITE command to fill
large blocks of memory. Initially, a WRITE is executed to set up the starting address of the block and supply the first operand. The FILL command writes
subsequent operands.
GO
The pipe is flushed and refilled before resuming instruction execution at the current PC.
CALL
Current program counter is stacked at the location of
the current stack pointer. Instruction execution begins
at user patch code.
RST
Asserts RESET for 512 clock cycles. The CPU is not
reset by this command. Synonymous with the CPU
RESET instruction.
NOP
NOP performs no operation and can be used as a null
command.
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5 Time Processor Unit
The time processor unit (TPU) is an intelligent, semi-autonomous microcontroller designed for timing
control. The TPU operates simultaneously with the CPU; it processes ROM instructions, schedules
tasks, performs input and output, and accesses shared data without CPU intervention. Consequently,
setup and service time for each timer event are minimized. The figure below is a simplified block diagram of the TPU.
HOST
INTERFACE
CONTROL
SCHEDULER
SERVICE REQUESTS
TIMER
CHANNELS
CHANNEL 0
IMB
CHANNEL
SYSTEM
CONFIGURATION
TCR1
CHANNEL 1
TCR2
T2CLK
DEVELOPMENT
SUPPORT AND TEST
PINS
MICROENGINE
CHANNEL
CONTROL
PARAMETER
RAM DATA
DATA
CONTROL
STORE
CONTROL AND DATA
EXECUTION
UNIT
CHANNEL 15
TPU BLOCK
Figure 11 TPU Block Diagram
5.1 Overview
The TPU can be viewed as a special-purpose microcomputer that performs a programmable series of
two operations, match and capture. Each occurrence of either operation is called an event. A programmed series of events is called a function. TPU functions replace software functions that would require host CPU interrupt service. Two sets of mask-programmed functions are currently available. Refer
to 5.6 Time Functions for more information.
5.2 Programmer's Model
The TPU control register address map occupies 512 bytes. The “Access” column in the TPU address
map below indicates which registers are accessible only at the supervisor privilege level and which can
be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the
TPUMCR.
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51
Table 25 TPU Address Map
Access
Address
15
8
7
0
S
$YFFE00
TPU MODULE CONFIGURATION REGISTER (TPUMCR)
S
$YFFE02
TEST CONFIGURATION REGISTER (TCR)
S
$YFFE04
DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)
S
$YFFE06
DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)
S
$YFFE08
TPU INTERRUPT CONFIGURATION REGISTER (TICR)
S
$YFFE0A
CHANNEL INTERRUPT ENABLE REGISTER (CIER)
S
$YFFE0C
CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)
S
$YFFE0E
CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)
S
$YFFE10
CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)
S
$YFFE12
CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)
S/U
$YFFE14
HOST SEQUENCE REGISTER 0 (HSQR0)
S/U
$YFFE16
HOST SEQUENCE REGISTER 1 (HSQR1)
S/U
$YFFE18
HOST SERVICE REQUEST REGISTER 0 (HSRR0)
S/U
$YFFE1A
HOST SERVICE REQUEST REGISTER 1 (HSRR1)
S
$YFFE1C
CHANNEL PRIORITY REGISTER 0 (CPR0)
S
$YFFE1E
CHANNEL PRIORITY REGISTER 1 (CPR1)
S
$YFFE20
CHANNEL INTERRUPT STATUS REGISTER (CISR)
S
$YFFE22
LINK REGISTER (LR)
S
$YFFE24
SERVICE GRANT LATCH REGISTER (SGLR)
S
$YFFE26
DECODED CHANNEL NUMBER REGISTER (DCNR)
Y = M111, where M represents the logic state of the MM bit in the SIMCR.
5.3 TPU Components
The TPU module consists of two 16-bit time bases, sixteen independent timer channels, a task scheduler, a microengine, and a host interface. In addition, a dual-port parameter RAM is used to pass parameters between the module and the host CPU.
5.3.1 Time Bases
Two 16-bit counters provide reference time bases for all output compare and input capture events.
Prescalers for both time bases are controlled by the host CPU via bit fields in the TPU module configuration register (TPUMCR). Timer count registers TCR1 and TCR2 provide access to current counter
values. TCR1 and TCR2 can be read/write accessed in microcode, but are not directly available to the
host CPU. The TCR1 clock is derived from the system clock. The TCR2 clock can be derived from the
system clock or from an external clock input via the T2CLK pin.
5.3.2 Timer Channels
The TPU has 16 independent channels, each connected to an MCU pin. The channels have identical
hardware. Each channel consists of an event register and pin control logic. The event register contains
a 16-bit capture register, a 16-bit compare/match register, and a 16-bit greater-than-or-equal-to comparator. The direction of each pin, either output or input, is determined by the TPU microengine. Each
channel can either use the same time base for match and capture, or can use one time base for match
and the other for capture.
52
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5.3.3 Scheduler
When a service request is received, the scheduler determines which TPU channel is serviced by the
microengine. A channel can request service for one of four reasons: for host service, for a link to another
channel, for a match event, or for a capture event. The host system assigns each active channel one
of three priorities: high, middle, or low. When multiple service requests are received simultaneously, a
priority-scheduling mechanism grants service based on channel number and assigned priority.
5.3.4 Microengine
The microengine is composed of a control store and an execution unit. Control-store ROM holds the
microcode for each factory-masked time function. When assigned to a channel by the scheduler, the
execution unit executes microcode for a function assigned to that channel by the host CPU. Microcode
can also be executed from the TPURAM module instead of the control store. The TPURAM module allows emulation and development of custom TPU microcode without the generation of a microcode ROM
mask. Refer to 5.5 Emulation Support for more information.
5.3.5 Host Interface
Host interface registers allow communication between the host CPU and the TPU, both before and during execution of a time function. The registers are accessible from the IMB through the TPU bus interface unit.
5.3.6 Parameter RAM
Parameter RAM occupies 256 bytes at the top of the system address map. Channel parameters are
organized as 128 16-bit words. Although all parameter word locations in RAM can be accessed by all
channels, only 100 are normally used: channels 0 to 13 use six parameter words, while channels 14
and 15 each use eight parameter words. The parameter RAM address map shows how parameter
words are organized in memory.
The host CPU specifies function parameters by writing the appropriate RAM address. The TPU reads
the RAM to determine channel operation. The TPU can also store information to be read by the CPU in
RAM. Detailed descriptions of the parameters required by each time function are beyond the scope of
this technical summary. Refer to the TPU Reference Manual (TPURM/AD) for more information.
For pre-programmed functions, one of the parameter words associated with each channel contains
three channel control fields. These fields perform the following functions:
PSC — Forces the output level of the pin.
PAC — For input capture, PAC specifies the edge transition to be detected. For output comparison,
PAC specifies the logic level to be output when a match occurs.
TBS — Specifies channel direction (input or output) and assigns a time base to the input capture
and output compare functions of the channel.
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53
Table 26 TPU Parameter RAM Address Map
Channel
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Base
Address
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
$YFFFF##
0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
1
02
12
22
32
42
52
62
72
82
92
A2
B2
C2
D2
E2
F2
2
04
14
24
34
44
54
64
74
84
94
A4
B4
C4
D4
E4
F4
Parameter Address
3
4
06
08
16
18
26
28
36
38
46
48
56
58
66
68
76
78
86
88
96
98
A6
A8
B6
B8
C6
C8
D6
D8
E6
E8
F6
F8
5
0A
1A
2A
3A
4A
5A
6A
7A
8A
9A
AA
BA
CA
DA
EA
FA
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EC
FC
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EE
FE
— = Not Implemented
Y = M111, where M represents the logic state of the MM bit in the SIMCR.
5.4 TPU Operation
All TPU functions are related to one of the two 16-bit free-running timebases. Functions are synthesized
by combining sequences of match events and capture events. Because the primitives are implemented
in hardware, the TPU can determine precisely when a match or capture event occurs, and respond rapidly. An event register for each channel provides for simultaneity of match/capture event occurrences
on all channels.
When a match or input capture event requiring service occurs, the affected channel generates a service
request to the scheduler. The scheduler determines the priority of the request and assigns the channel
to the microengine at the first available time. The microengine performs the function defined by the content of the control store or emulation RAM, using parameters from the parameter RAM.
5.4.1 Event Timing
Match and capture events are handled by independent channel hardware. This provides an event accuracy of one time-base clock period, regardless of the number of channels that are active. An event
normally causes a channel to request service. However, before an event can be serviced, any pending
previous requests must be serviced. The time needed to respond to and service an event is determined
by the number of channels requesting service, the relative priorities of the channels requesting service,
and the microcode execution time of the active functions. Worst-case event service time (latency) determines TPU performance in a given application. Latency can be closely estimated — see Freescale
TPU Reference Manual (TPURM/AD) for more information.
5.4.2 Channel Orthogonality
Most timer systems are limited by the fixed number of functions assigned to each pin. All TPU channels
contain identical hardware and are functionally equivalent in operation, so that any channel can be configured to perform any time function. Any function can operate on the calling channel, and, under program control, on another channel determined by the program or by a parameter. The user controls the
combination of time functions.
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5.4.3 Interchannel Communication
The autonomy of the TPU is enhanced by the ability of a channel to affect the operation of one or more
other channels without CPU intervention. Interchannel communication can be accomplished by issuing
a link service request to another channel, by controlling another channel directly, or by accessing the
parameter RAM of another channel.
5.4.4 Programmable Channel Service Priority
The TPU provides a programmable service priority level to each channel. Three priority levels are available. When more than one channel of a given priority requests service at the same time, arbitration is
accomplished according to channel number. To prevent a single high-priority channel from permanently
blocking other functions, other service requests of the same priority are performed in channel order after
the lowest-numbered, highest-priority channel is serviced.
5.4.5 Coherency
For data to be coherent, all available portions of it must be identical in age, or must be logically related.
As an example, consider a 32-bit counter value that is read and written as two 16-bit words. The 32-bit
value is read-coherent only if both 16-bit portions are updated at the same time, and write-coherent only
if both portions take effect at the same time. Parameter RAM hardware supports coherent access of two
adjacent 16-bit parameters. The host CPU must use a long-word operation to guarantee coherency.
5.5 Emulation Support
Although factory-programmed time functions can perform a wide variety of control tasks, they may not
be ideal for all applications. The TPU provides emulation capability that allows the user to develop new
time functions. Emulation mode is entered by setting the EMU bit in the TPUMCR. In emulation mode,
an auxiliary bus connection is made between TPURAM and the TPU module, and access to TPURAM
via the intermodule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer
information between the modules. To ensure exact emulation, RAM module access timing remains consistent with access timing of the TPU ROM control store.
To support changing TPU application requirements, Freescale has established a TPU function library.
The function library is a collection of TPU functions written for easy assembly in combination with each
other or with custom functions. Refer to Freescale Programming Note TPUPN00/D,Using the TPU Function Library and TPU Emulation Mode for information about developing custom functions and accessing
the TPU function library. Refer to the TPU Reference Manual (TPURM/AD) for more information about
specific functions.
5.6 Time Functions
The following paragraphs describe factory-programmed time functions implemented in the TPU microcode ROM. A complete description of the functions is beyond the scope of this summary. Refer to the
TPU Reference Manual (TPURM/AD) for additional information.
5.6.1 Table Stepper Motor (TSM)
The TSM function provides for acceleration and deceleration control of a stepper motor with a programmable number of step rates up to 58. TSM uses a table in parameter RAM, rather than an algorithm, to
define the stepper motor acceleration profile, allowing the user to fully define the profile. In addition, a
slew rate parameter allows fine control of the terminal running speed of the motor independent of the
acceleration table. The CPU need only write a desired position, and the TPU accelerates, slews, and
decelerates the motor to the required position. Full and half step support is provided for two-phase motors. In addition, a slew rate parameter allows fine control of the terminal running speed of the motor
independent of the acceleration table.
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5.6.2 Input Capture/Transition Counter (ITC)
Any channel of the TPU can capture the value of a specified TCR or any specified location in parameter
RAM upon the occurrence of each transition or specified number of transitions, and then generate an
interrupt request to notify the bus master. The times of the most recent two transitions are maintained
in parameter RAM. A channel can perform input captures continually, or a channel can detect a single
transition or specified number of transitions, ceasing channel activity until reinitialization. After each
transition or specified number of transitions, the channel can generate a link to other channels.
5.6.3 Queued Output Match (QOM)
QOM can generate single or multiple output match events from a table of offsets in parameter RAM.
Loop modes allow complex pulse trains to be generated once, a specified number of times, or continuously. The function can be triggered by a link from another TPU channel. In addition, the reference time
for the sequence of matches can be obtained from another channel. QOM can generate pulse-width
modulated waveforms, including waveforms with high times of 0% or 100%. QOM also allows a TPU
channel to be used as a discrete output pin.
5.6.4 Programmable Time Accumulator (PTA)
PTA accumulates a 32-bit sum of the total high time, low time, or period of an input signal over a programmable number of periods or pulses. The accumulation can start on a rising or falling edge. After
the specified number of periods or pulses, the PTA generates an interrupt request and optionally generates links to other channels.
From 1 to 255 period measurements can be made and summed with the previous measurement(s) before the TPU interrupts the CPU, providing instantaneous or average frequency measurement capability, and the latest complete accumulation (over the programmed number of periods).
5.6.5 Multichannel Pulse-Width Modulation (MCPWM)
MCPWM generates pulse-width modulated outputs with full 0% to 100% duty cycle range independent
of other TPU activity. This capability requires two TPU channels plus an external gate for one PWM
channel. (A simple one-channel PWM capability is supported by the QOM function.)
Multiple PWMs generated by MCPWM have two types of high time alignment: edge aligned and center
aligned. Edge aligned mode uses n + 1 TPU channels for n PWMs; center aligned mode uses 2n + 1
channels. Center aligned mode allows a user defined ‘dead time’ to be specified so that two PWMs can
be used to drive an H-bridge without destructive current spikes. This feature is important for motor control applications.
5.6.6 Fast Quadrature Decode (FQD)
FQD is a position feedback function for motor control. It decodes the two signals from a slotted encoder
to provide the CPU with a 16-bit free running position counter. FQD incorporates a “speed switch” which
disables one of the channels at high speed, allowing faster signals to be decoded. A time stamp is provided on every counter update to allow position interpolation and better velocity determination at low
speed or when low resolution encoders are used. The third index channel provided by some encoders
is handled by the ITC function.
5.6.7 Universal Asynchronous Receiver/Transmitter (UART)
The UART function uses one or two TPU channels to provide asynchronous communications. Data
word length is programmable from 1 to 14 bits. The function supports detection or generation of even,
odd, and no parity. Baud rate is freely programmable and can be higher than 100 Kbaud. Eight bidirectional UART channels running in excess of 9600 baud could be implemented on the TPU.
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5.6.8 Brushless Motor Commutation (COMM)
This function generates the phase commutation signals for a variety of brushless motors, including
three-phase brushless direct current. It derives the commutation state directly from the position decoded in FQD, thus eliminating the need for hall effect sensors.
The state sequence is implemented as a user-configurable state machine, thus providing a flexible approach with other general applications. A CPU offset parameter is provided to allow all the switching
angles to be advanced or retarded on the fly by the CPU. This feature is useful for torque maintenance
at high speeds.
5.6.9 Frequency Measurement (FQM)
FQM counts the number of input pulses to a TPU channel during a user-defined window period. The
function has single shot and continuous modes. No pulses are lost between sample windows in continuous mode. The user selects whether to detect pulses on the rising or falling edge. This function is intended for high speed measurement; measurement of slow pulses with noise rejection can be made
with PTA.
5.6.10 Hall Effect Decode (HALLD)
This function decodes the sensor signals from a brushless motor, along with a direction input from the
CPU, into a state number. The function supports two- or three-sensor decoding. The decoded state
number is written into a COMM channel, which outputs the required commutation drive signals. In addition to brushless motor applications, the function can have more general applications, such as decoding “option” switches.
5.7 TPU Registers
The TPU memory map contains three groups of registers:
System Configuration Registers
Channel Control and Status Registers
Development Support and Test Verification Registers
5.7.1 System Configuration Registers
TPUMCR — TPU Module Configuration Register
15
14
STOP
13
12
TCR1P
11
TCR2P
$YFFE00
10
9
8
7
6
5
4
EMU
T2CG
STF
SUPV
PSCK
0
0
0
0
0
1
0
0
0
3
2
1
0
0
0
IARB
RESET:
0
0
0
0
0
0
0
STOP — Stop Bit
0 = TPU operating normally
1 = Internal clocks shut down
TCR1P — Timer Count Register 1 Prescaler Control
TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal TPU system clock
divided by either 4 or 32, depending on the value of the PSCK bit. The prescaler divides this input by 1,
2, 4, or 8. Channels using TCR1 have the capability to resolve down to the TPU system clock divided
by 4.
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÷2
SYSTEM
CLOCK
÷4
DIV2 CLOCK
DIV4 CLOCK
PSCK
MUX
÷ 32
DIV32 CLOCK
TCR1
PRESCALER
00 ÷ 1
01 ÷ 2
10 ÷ 4
11 ÷ 8
CSEL
MUX
0
15
TCR1
0 – TCR1 PRESCALER
1 – DIV2
0 – DIV32 CLOCK
1 – DIV4 CLOCK
TPU PRE BLOCK 1
Figure 12 Prescaler Control 1
TCR1 Prescaler
Divide
By
1
2
4
8
00
01
10
11
PSCK = 0
Number of
Rate at
Clocks
16 MHz
32
2 ms
64
4 ms
128
8 ms
256
16 ms
PSCK = 1
Number of
Rate at
Clocks
16 MHz
4
250 ns
8
500 ns
16
1 ms
32
2 ms
TCR2P — Timer Count Register 2 Prescaler Control
TCR2 is clocked from the output of a prescaler. If T2CG = 0, the input to the TCR2 prescaler is the external TCR2 clock source. If T2CG = 1, the input is the TPU system clock divided by eight. The TCR2P
field specifies the value of the prescaler: 1, 2, 4, or 8. Channels using TCR2 have the capability to resolve down to the TPU system clock divided by 8. The following table is a summary of prescaler output.
TCR2 Prescaler
Divide By
Internal Clock
Divided By
External Clock
Divided By
00
1
8
1
01
2
16
2
10
4
32
4
11
8
64
8
EMU — Emulation Control
In emulation mode, the TPU executes microinstructions from MCU TPURAM exclusively. Access to the
TPURAM module through the IMB by a host is blocked, and the TPURAM module is dedicated for use
by the TPU. After reset, this bit can be written only once.
0 = TPU and TPURAM not in emulation mode
1 = TPU and TPURAM in emulation mode
T2CG — TCR2 Clock/Gate Control
When the T2CG bit is set, the external TCR2 pin functions as a gate of the DIV8 clock (the TPU system
clock divided by 8). In this case, when the external TCR2 pin is low, the DIV8 clock is blocked, preventing it from incrementing TCR2. When the external TCR2 pin is high, TCR2 is incremented at the frequency of the DIV8 clock. When T2CG is cleared, an external clock from the TCR2 pin, which has been
synchronized and fed through a digital filter, increments TCR2.
0 = TCR2 pin used as clock source for TCR2
1 = TCR2 pin used as gate of DIV8 clock for TCR2
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0–A
1–B
T2C FILTER BIT
DIGITAL
FILTER
0–A
1–B
T2CG CONTROL BIT
A
A
MUX
T2CLK
PIN
TCR2
PRESCALER
PROGRAMMABLE B
DIGITAL
FILTER
SYNCHRONIZER
0
15
00 ÷ 1
01 ÷ 2
10 ÷ 4
11 ÷ 8
MUX
B
INT CLK ÷ 8
TCR2
TPU PRE BLOCK 2
Figure 13 Prescaler Control 2
STF — Stop Flag
0 = TPU operating
1 = TPU stopped (STOP bit has been asserted)
SUPV — Supervisor Data Space
0 = Assignable registers are unrestricted (FC2 is ignored)
1 = Assignable registers are restricted (FC2 is decoded)
PSCK — Prescaler Clock
0 = System clock/32 is input to TCR1 prescaler
1 = System clock/4 is input to TCR1 prescaler
IARB — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, nonzero IARB field value. Refer to 3.8 Interrupts for more information.
TICR — TPU Interrupt Configuration Register
15
14
13
12
11
10
NOT USED
9
$YFFE08
8
7
6
CIRL
5
4
CIBV
3
2
1
0
NOT USED
RESET:
0
0
0
0
0
0
0
CIRL — Channel Interrupt Request Level
The interrupt request level for all channels is specified by this 3-bit encoded field. Level seven for this
field indicates a nonmaskable interrupt; level zero indicates that all channel interrupts are disabled.
CIBV — Channel Interrupt Base Vector
The TPU is assigned 16 unique interrupt vector numbers, one vector number for each channel. The
CIBV field specifies the most significant nibble of all 16 TPU channel interrupt vector numbers. The lower nibble of the TPU interrupt vector number is determined by the channel number on which the interrupt
occurs.
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59
5.7.2 Channel Control Registers
CIER — Channel Interrupt Enable Register
$YFFE0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
CH[15:0] — Channel Interrupt Enable/Disable
0 = Channel interrupts disabled
1 = Channel interrupts enabled
CISR — Channel Interrupt Status Register
$YFFE20
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
CH[15:0] — Channel Interrupt Status Bit
0 = Channel interrupt not asserted
1 = Channel interrupt asserted
CFSR0 — Channel Function Select Register 0
15
14
13
12
11
CHANNEL15
10
9
$YFFE0C
8
7
CHANNEL14
6
5
4
3
CHANNEL13
2
1
0
CHANNEL12
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFSR1 — Channel Function Select Register 1
15
14
13
12
11
CHANNEL11
10
9
0
0
$YFFE0E
8
7
CHANNEL10
6
5
4
3
CHANNEL9
2
1
0
CHANNEL8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFSR2 — Channel Function Select Register 2
15
14
13
12
11
CHANNEL7
10
9
0
0
$YFFE10
8
7
CHANNEL6
6
5
4
3
CHANNEL5
2
1
0
CHANNEL4
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFSR3 — Channel Function Select Register 3
15
14
13
12
11
CHANNEL3
10
9
0
0
$YFFE12
8
7
CHANNEL2
6
5
4
3
CHANNEL1
2
1
0
CHANNEL0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHANNEL[15:0] — Encoded Time Function for each Channel
Encoded 4-bit fields in the channel function select registers specify one of 16 time functions to be executed on the corresponding channel.
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HSQR0 — Host Sequence Register 0
15
14
13
CH 15
12
11
CH 14
10
$YFFE14
9
CH 13
8
7
CH 12
6
5
CH 11
4
3
CH 10
2
1
CH 9
0
CH 8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSQR1 — Host Sequence Register 1
15
14
13
CH 7
12
11
10
CH 6
0
0
$YFFE16
9
CH 5
8
7
CH 4
6
5
CH 3
4
3
CH 2
2
1
CH 1
0
CH 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH[15:0] — Encoded Host Sequence
The host sequence field selects the mode of operation for the time function selected on a given channel.
The meaning of the host sequence bits depends on the time function specified.
HSRR0 — Host Service Request Register 0
15
14
13
CH 15
12
11
CH 14
10
$YFFE18
9
CH 13
8
7
CH 12
6
5
CH 11
4
3
CH 10
2
1
CH 9
0
CH 8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSRR1 — Host Service Request Register 1
15
14
13
CH 7
12
11
CH 6
10
0
$YFFE1A
9
CH 5
0
8
7
CH 4
6
5
CH 3
4
3
CH 2
2
1
CH 1
0
CH 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH[15:0] — Encoded Type of Host Service
The host service request field selects the type of host service request for the time function selected on
a given channel. The meaning of the host service request bits depends on the time function specified.
A host service request field cleared to %00 signals the host that service is completed by the microengine
on that channel. The host can request service on a channel by writing the corresponding host service
request field to one of three nonzero states. The CPU should monitor the host service request register
until the TPU clears the service request to %00 before the CPU changes any parameters or issues a
new service request to the channel.
CPR0 — Channel Priority Register 0
15
14
13
CH 15
12
$YFFE1C
11
CH 14
10
9
CH 13
8
7
CH 12
6
5
CH 11
4
3
CH 10
2
1
CH 9
0
CH 8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPR1 — Channel Priority Register 1
15
14
13
CH 7
12
11
CH 6
0
0
$YFFE1E
10
9
CH 5
8
7
CH 4
6
5
CH 3
4
3
CH 2
2
1
CH 1
0
CH 0
RESET:
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
61
CH[15:0] — Encoded One of Three Channel Priority Levels
CHX[1:0]
00
01
10
11
Service
Disabled
Low
Middle
High
Guaranteed Time Slots
—
4 out of 7
2 out of 7
1 out of 7
5.7.3 Development Support and Test Registers
These registers are used for custom microcode development or for factory test. Describing the use of
the registers is beyond the scope of this technical summary. Register names and addresses are given
for reference only. Refer to the TPU Reference Manual (TPURM/AD) for more information.
DSCR — Development Support Control Register
$YFFE04
DSSR — Development Support Status Register
$YFFE06
LR — Link Register
$YFFE22
SGLR — Service Grant Latch Register
$YFFE24
DCNR — Decoded Channel Number Register
$YFFE26
TCR — Test Configuration Register
$YFFE02
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6 Analog-to-Digital Converter Module
The analog-to-digital converter (ADC) is a unipolar, successive-approximation converter with eight
modes of operation. It has selectable 8- or 10-bit resolution. Accuracy is ±1 count (1 LSB) in 8-bit mode
and ±4 counts (2 LSB) in 10-bit mode. Monotonicity is guaranteed in both modes. The ADC can perform
an 8-bit single conversion (4-clock sample) in 10 microseconds and a 10-bit single conversion in 11 microseconds.
The ADC consists of an analog and a digital subsystem. A block diagram of the converter appears on
the following page.
6.1 Analog Subsystem
The analog front end consists of a multiplexer, a buffer amplifier, a resistor-capacitor array, and a highgain comparator. The multiplexer selects one of eight internal or seven external signal sources for conversion. The resistor capacitor digital-to-analog converter (RC DAC) array performs two functions: it
acts as a sample/hold circuit, and it provides the digital-to-analog comparison output necessary for successive approximation conversion. The comparator indicates whether each successive output of the
RC DAC array is higher or lower than the sampled input.
6.2 Digital Control Subsystem
The digital control section includes conversion sequence control logic, channel and reference select
logic, a successive approximation register, eight result registers, a port data register, and control/status
registers. It controls the multiplexer and the output of the RC DAC array during the sample and conversion periods, stores the results of comparison in the successive-approximation register, and transfers
the result to a result register.
The ADC bus interface unit (ABIU) contains logic necessary to interface the ADC to the intermodule
bus. The ADC is designed to act as a slave device on the bus. The interface must respond with appropriate bus cycle termination signals and supply appropriate interface timing to the other submodules.
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63
VDDA
VSSA SUPPLY
RC DAC ARRAY
AND
COMPARATOR
SAR
MODE
AND
TIMING
CONTROL
RESULT 0
RESULT 1
RESULT 2
RESULT 3
VRH
VRL
ANALOG
MUX
AND SAMPLE
BUFFER AMP
RESERVED
RESERVED
RESERVED
RESERVED
V RH
V RL
(V RH–VRL )/2
RESERVED
REFERENCE
AN6/PADA6
AN5/PADA5
AN4/PADA4
AN3/PADA3
AN2/PADA2
AN1/PADA1
AN0/PADA0
INTERNAL
CONNECTIONS
PORT ADA DATA
REGISTER
RESULT 4
RESULT 5
RESULT 6
RESULT 7
CLK SELECT/
PRESCALE
ADC BUS
INTERFACE UNIT
INTERMODULE BUS (IMB)
ADC BLOCK 7CHAN
Figure 14 Analog-to-Digital Converter Block Diagram
6.3 ADC Address Map
The ADC control register address map occupies 64 bytes. The “Access” column in the ADC address
map below indicates which registers are accessible only at the supervisor privilege level and which can
be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the
ADCMCR.
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Table 27 ADC Module Address Map
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Address
$YFF700
$YFF702
$YFF704
$YFF706
$YFF708
$YFF70A
$YFF70C
$YFF70E
$YFF710
$YFF712
$YFF714
$YFF716
$YFF718
$YFF71A
$YFF71C
$YFF71E
$YFF720
$YFF722
$YFF724
$YFF726
$YFF728
$YFF72A
$YFF72C
$YFF72E
$YFF730
$YFF732
$YFF734
$YFF736
$YFF738
$YFF73A
$YFF73C
$YFF73E
15
8 7
ADC MODULE CONFIGURATION REGISTER (ADCMCR)
ADC FACTORY TEST REGISTER (ADTEST)
(RESERVED)
PORT ADA DATA (PORTADA)
(RESERVED)
ADC CONTROL 0 (ADCTL0)
ADC CONTROL 1 (ADCTL1)
ADC STATUS (ADSTAT)
RIGHT-JUSTIFIED UNSIGNED RESULT 0 (RJURR0)
RIGHT-JUSTIFIED UNSIGNED RESULT 1 (RJURR1)
RIGHT-JUSTIFIED UNSIGNED RESULT 2 (RJURR2)
RIGHT-JUSTIFIED UNSIGNED RESULT 3 (RJURR3)
RIGHT-JUSTIFIED UNSIGNED RESULT 4 (RJURR4)
RIGHT-JUSTIFIED UNSIGNED RESULT 5 (RJURR5)
RIGHT-JUSTIFIED UNSIGNED RESULT 6 (RJURR6)
RIGHT-JUSTIFIED UNSIGNED RESULT 7 (RJURR7)
LEFT-JUSTIFIED SIGNED RESULT 0 (LJSRR0)
LEFT-JUSTIFIED SIGNED RESULT 1 (LJSRR1)
LEFT-JUSTIFIED SIGNED RESULT 2 (LJSRR2)
LEFT-JUSTIFIED SIGNED RESULT 3 (LJSRR3)
LEFT-JUSTIFIED SIGNED RESULT 4 (LJSRR4)
LEFT-JUSTIFIED SIGNED RESULT 5 (LJSRR5)
LEFT-JUSTIFIED SIGNED RESULT 6 (LJSRR6)
LEFT-JUSTIFIED SIGNED RESULT 7 (LJSRR7)
LEFT-JUSTIFIED UNSIGNED RESULT 0 (LJURR0)
LEFT-JUSTIFIED UNSIGNED RESULT 1 (LJURR1)
LEFT-JUSTIFIED UNSIGNED RESULT 2 (LJURR2)
LEFT-JUSTIFIED UNSIGNED RESULT 3 (LJURR3)
LEFT-JUSTIFIED UNSIGNED RESULT 4 (LJURR4)
LEFT-JUSTIFIED UNSIGNED RESULT 5 (LJURR5)
LEFT-JUSTIFIED UNSIGNED RESULT 6 (LJURR6)
LEFT-JUSTIFIED UNSIGNED RESULT 7 (LJURR7)
0
Y = M111, where M is the logic state of the MM bit in the SIMCR
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6.4 ADC Registers
ADCMCR — ADC Module Configuration Register
15
14
STOP
13
12
11
FRZ
10
9
$YFF700
8
NOT USED
7
6
5
4
SUPV
3
2
1
0
NOT USED
RESET:
1
0
0
0
The ADCMCR is used to initialize the ADC.
STOP — STOP Mode
0 = Normal operation
1 = Low-power operation
STOP places the ADC in low-power state by disabling the ADC clock and powering down the analog
circuitry. Setting STOP aborts any conversion in progress. STOP is set to logic level one at reset, and
may be cleared to logic level zero by the CPU.
Clearing STOP enables normal ADC operation. However, because analog circuitry bias current has
been turned off, there is a period of recovery before output stabilization.
FRZ[1:0] — Freeze 1
The FRZ field is used to determine ADC response to assertion of the FREEZE signal. The following
table shows possible responses.
FRZ
00
01
10
11
Response
Ignore FREEZE
Reserved
Finish conversion, then freeze
Freeze immediately
SUPV — Supervisor/Unrestricted
0 = Unrestricted access
1 = Supervisor access
SUPV defines access to assignable ADC registers.
ADTEST — ADC Test Register
$YFF702
ADTEST is used during factory test of the ADC.
PORTADA — Port ADA Data Register
15
14
13
12
11
NOT USED
10
$YFF706
9
8
7
6
5
4
3
2
1
0
PORT ADA DATA
RESET:
Reflects state of the input pins
Port ADA is an input port that shares pins with the A/D converter inputs. The port ADA data register
resides in the lower half of the PDR. Bit 7 always returns zero when read.
PDR[6:0] — Port ADA Data
A read of PDR[6:0] will return the logic level of the port A pins. If the input is outside the defined voltage
range, the result of the read will be indeterminate. Use of a port A pin for digital input does not preclude
use as an analog input.
66
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ADCTL0 — A/D Control Register 0
15
14
13
12
11
$YFF70A
10
9
NOT USED
8
7
6
RES10
5
4
3
STS
2
1
0
1
1
PRS
RESET:
0
0
0
0
0
0
ADCTL0 is used to select ADC clock source and to set up prescaling. Writes to it have immediate effect.
RES10 — 10-Bit Resolution
0 = 8-bit resolution
1 = 10-bit resolution
Conversion results are appropriately aligned in result registers to reflect conversion status.
STS[1:0] — Sample Time Select
Total conversion time depends on initial sample time, transfer time, final sample time, and resolution
time. Initial sample time is fixed at two clocks. Transfer time is fixed at two clocks. Resolution time is
fixed at ten ADC clock cycles for an 8-bit conversion and twelve ADC clock cycles for a 10-bit conversion. Final sample time depends on the STS field, as shown below.
STS[1:0]
00
01
10
11
Sample Time
2 A/D Clock Periods
4 A/D Clock Periods
8 A/D Clock Periods
16 A/D Clock Periods
PRS[4:0] — Prescaler Rate Selection Field
ADC clock is generated from system clock using a modulo counter and a divide-by-two circuit. The binary value of this field is the counter modulus. System clock is divided by the PRS value plus one, then
sent to the divide-by-two circuit, as shown in the following table. Maximum ADC clock rate is 2 MHz.
Reset value of PRS is a divisor value of eight, resulting in a nominal 2-MHz ADC clock.
PRS[4:0]
00000
00001
00010
...
11101
11110
11111
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Divisor Value
4
4
6
...
60
62
64
67
ADCTL1 — A/D Control Register 1
15
14
13
12
11
NOT USED
$YFF70C
10
9
8
7
6
5
4
3
2
1
0
SCAN
MULT
S8CM
CD
CC
CB
CA
0
0
0
0
0
0
0
RESET:
ADCTL1 is used to initiate an A/D conversion and to select conversion modes and a conversion channel. It can be written or read at any time. A write to ADCTL1 initiates a conversion sequence. If a conversion sequence is already in progress, a write to ADCTL1 aborts it and resets the SCF and CCF flags
in the ADC status register.
SCAN — Scan Mode Selection Bit
0 = Single conversion sequence
1 = Continuous conversion
Length of conversion sequence(s) is determined by S8CM.
MULT — Multichannel Conversion Bit
0 = Conversion sequence(s) run on single channel (channel selected via [CD:CA])
1 = Sequential conversion of a block of four or eight channels (block selected via [CD:CA])
Length of conversion sequence(s) is determined by S8CM.
S8CM — Select Eight-Conversion Sequence Mode
0 = Four-conversion sequence
1 = Eight-conversion sequence
This bit determines the number of conversions in a conversion sequence.
CD:CA — Channel Selection Field
The bits in this field are used to select an input or block of inputs for A/D conversion.
The following table summarizes the operation of S8CM and CD:CA when MULT is cleared (single channel mode). Number of conversions per channel is determined by SCAN.
68
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S8CM
0
0
0
0
0
0
0
0
0
0
0
0
0
CD
0
0
0
0
0
0
0
0
1
1
1
1
1
CC
0
0
0
0
1
1
1
1
0
0
0
0
1
CB
0
0
1
1
0
0
1
1
0
0
1
1
0
CA
0
1
0
1
0
1
0
1
0
1
0
1
0
Input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7*
Reserved
Reserved
Reserved
Reserved
VRH
Result Register
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
0
1
1
0
1
VRL
RSLT0 – RSLT3
0
1
1
1
0
(VRH – VRL) / 2
RSLT0 – RSLT3
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Test/Reserved
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7*
Reserved
Reserved
Reserved
Reserved
VRH
RSLT0 – RSLT3
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
1
1
1
0
1
VRL
RSLT0 – RSLT7
1
1
1
1
0
(VRH – VRL) / 2
RSLT0 – RSLT7
1
1
1
1
1
Test/Reserved
RSLT0 – RSLT7
* Since the ADC in the MCU has only seven external analog inputs, AN7 is connected to VSSA.
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69
The following table summarizes the operation of S8CM and CD:CA when MULT is set (multichannel
mode). Number of conversions per channel is determined by SCAN. Channel numbers are given in order of conversion.
S8CM
0
CD
0
CC
0
CB
X
CA
X
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
X
X
X
1
1
X
X
X
Input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7*
Reserved
Reserved
Reserved
Reserved
VRH
Result Register
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
VRL
RSLT1
(VRH – VRL) / 2
RSLT2
Test/Reserved
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7*
Reserved
Reserved
Reserved
Reserved
VRH
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT4
RSLT5
RSLT6
RSLT7
RSLT0
RSLT1
RSLT2
RSLT3
RSLT4
VRL
RSLT5
(VRH – VRL) / 2
RSLT6
Test/Reserved
RSLT7
* Since the ADC in the MCU has only seven external analog inputs, AN7 is connected to VSSA.
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ADSTAT — ADC Status Register
15
SCF
14
13
12
11
$YFF70E
10
NOT USED
9
8
7
6
5
4
CCTR
3
2
1
0
0
0
0
0
CCF
RESET:
0
0
0
0
0
0
0
0
ADSTAT contains information related to the status of a conversion sequence.
SCF — Sequence Complete Flag
0 = Sequence not complete
1 = Sequence complete
SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first
conversion sequence when SCAN is set. SCF is cleared when ADCTL1 is written and a new conversion
sequence begins.
CCTR[2:0] — Conversion Counter Field
This field reflects the contents of the conversion counter pointer in either four or eight count conversion
sequence. The value corresponds to the number of the next result register to be written, and thus indicates which channel is being converted.
CCF[7:0] — Conversion Complete Field
Each bit in this field corresponds to an A/D result register (CCF7 to RSLT7, etc.). A bit is set when conversion for the corresponding channel is complete, and remains set until the result register is read.
RSLT[7:0] — A/D Result Registers
$YFF710–$YFF73E
The result registers store data after conversion is complete. Each register can be read from three different addresses in the register block. Data format depends on the address from which the result register is read.
RJURR — Unsigned Right-Justified Format
$YFF710–$YFF71F
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution, bits [7:0] are
used for 8-bit resolution (bits [9:8] are zero). Bits [15:10] always return zero when read.
LJSRR — Signed Left-Justified Format
$YFF720–$YFF72F
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are
used for 8-bit resolution (bits [7:6] are zero). Although the ADC is unipolar, it is assumed that the zero
point is halfway between low and high reference when this format is used. For positive input, bit 15 = 0,
for negative input, bit 15 = 1. Bits [5:0] always return zero when read.
LJURR — Unsigned Left-Justified Format
$YFF730–$YFF73F
Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are
used for 8-bit resolution (bits [7:6] are zero). Bits [5:0] always return zero when read.
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7 Standby RAM with TPU Emulation
The TPURAM module contains a 1-Kbyte array of fast (two bus cycle) static RAM, which is especially
useful for system stacks and variable storage. Alternately, it can be used by the TPU as emulation RAM
for new timer algorithms.
7.1 Overview
The 1-Kbyte TPURAM array occupies the top 1024 bytes of a 2-Kbyte block (addresses $400 to $7FF
when the ADDR11 bit in TRAMBAR = 0; addresses $0C00 to $0FFF when the ADDR11 bit in TRAMBAR = 1). The block can be mapped to any 2-Kbyte boundary in the address map, but must not overlap
the module control registers (overlap makes the registers inaccessible). Data can be read or written in
bytes, word, or long words. TPURAM responds to both program and data space accesses. Data can be
read or written in bytes, word, or long words. The TPURAM is powered by VDD in normal operation.
During power-down, the TPURAM contents are maintained by power on standby voltage pin VSTBY.
Power switching between sources is automatic.
Access to the TPURAM array is controlled by the RASP field in TRAMMCR. This field can be encoded
so that TPURAM responds to both program and data space accesses. This allows code to be executed
from TPURAM, and permits the use of program counter relative addressing mode for operand fetches
from the array.
An address map of the TPURAM control registers follows. All TPURAM control registers are located in
supervisor data space.
Table 28 TPURAM Control Register Address Map
Access
S
S
S
Address
$YFFB00
$YFFB02
$YFFB04
$YFFB06–
$YFFB3F
15
8 7
TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR)
TPURAM TEST REGISTER (TRAMTST)
TPURAM BASE ADDRESS REGISTER (TRAMBAR)
NOT USED
0
Y = M111, where M is the logic state of the MM bit in the SIMCR.
7.2 TPURAM Register Block
There are three TPURAM control registers: the TPURAM module configuration register (TRAMMCR),
the TPURAM test register (TRAMTST), and the TPURAM array base address registers (TRAMBAR).
There is an 8-byte minimum register block size for the module. Unimplemented register addresses are
read as zeros, and writes have no effect.
7.3 TPURAM Registers
TRAMMCR — TPURAM Module Configuration Register
15
14
13
12
11
10
9
8
STOP
0
0
0
0
0
0
RASP
0
0
0
0
0
0
1
$YFFB00
7
6
5
4
3
2
1
0
NOT USED
RESET:
0
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STOP — Stop Control
0 = TPURAM array operates normally.
1 = TPURAM array enters low-power stop mode.
This bit controls whether the TPURAM array is in stop mode or normal operation. Reset state is zero,
for normal operation. In stop mode, the array retains its contents, but cannot be read or written by the
CPU.
RASP — RAM Array Space Field
0 = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space
TRAMTST — TPURAM Test Register
$YFFB02
TRAMTST is used for factory testing of the TPURAM module.
TRAMBAR — TPURAM Base Address and Status Register
$YFFB04
15
14
13
12
11
10
9
8
7
6
5
4
3
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
0
0
0
0
0
0
0
0
0
0
0
2
1
NOT USED
0
RAMD
S
RESET:
0
0
0
ADDR[23:11] — RAM Array Base Address
This field specifies ADDR[23:11] of the TPURAM array base address when the array is enabled.
ADDR11 determines the 2-Kbyte boundary that the block of addresses containing the array is mapped
to. The array occupies only the upper 1024 bytes of the 2-Kbyte block of addresses. When ADDR11 bit
is set, valid array addresses range from $0C00 to%0FFFF; when the ADDR11 bit is cleared, valid array
addresses range from $0400 to $07FF.
RAMDS — RAM Array Disable
0 = TPURAM array is enabled
1 = TPURAM array is disabled
The TPURAM array is disabled by internal logic after a master reset. Writing a valid base address to
the TPURAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the TPURAM
array.
7.4 TPURAM Operation
There are six TPURAM operating modes, as follows:
• The TPURAM module is in normal mode when powered by VDD. The array can be accessed by
byte, word, or long word. A byte or aligned word (high-order byte is at an even address) access
only takes one bus cycle or two system clocks. A long word or misaligned word access requires
two bus cycles.
• Standby mode is intended to preserve TPURAM contents when VDD is removed. TPURAM contents are maintained by VSTBY. Circuitry within the TPURAM module switches to the higher of
VDD or VSTBY with no loss of data. When TPURAM is powered by VSTBY, access to the array is
not guaranteed.
• Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous reset occurs while a byte or word TPURAM access is in progress, the access will be completed. If reset occurs during the first word access of a long-word operation, only the first word
access will be completed. If reset occurs during the second word access of a long word operation,
the entire access will be completed. Data being read from or written to the RAM may be corrupted
by asynchronous reset.
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73
• Test mode functions in conjunction with the SIM test functions. Test mode is used during factory
test of the MCU.
• Writing the STOP bit of TRAMMCR causes the TPURAM module to enter stop mode. The
TPURAM array is disabled (which allows external logic to decode TPURAM addresses, if necessary), but all data is retained. If VDD falls below VSTBY during stop mode, internal circuitry switches to VSTBY, as in standby mode. Stop mode is exited by clearing the STOP bit.
• The TPURAM array may be used to emulate the microcode ROM in the TPU module. This provides a means of developing custom TPU code. The TPU selects TPU emulation mode. While in
TPU emulation mode, the access timing of the TPURAM module matches the timing of the TPU
microinstruction ROM to ensure accurate emulation. Normal accesses via the IMB are inhibited
and the control registers have no effect, allowing external RAM to emulate the TPURAM at the
same addresses.
8 Summary of Changes
This is a partial revision. Most of the publication remains the same, but the following changes were
made to improve it. Typographical errors that do not affect content are not annotated.
74
Page 2
Ordering Information revised to reflect new quantities, TPU mask options.
Page 7
Address map revised to reflect TPURAM array mapping.
Pages 11-42
Expanded and revised SIM section. Added new information to 3.3 System Clock,
3.5 Chip Selects, 3.7 Resets, and 3.8 Interrupts.
Page 72-74
Revised Standby RAM with TPU Emulation section to include details of array mapping to upper half of 2-Kbyte address block.
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