MC68882CEI20A

..,,f,i .. . ,.:.:,;ri, ,..:. , ,,..:,+:. . . . ...4.,, ? >..,“ .s, ,.. .,. ., c .,. , ,. $ ..., ,. . ., s .,, ...,..., ! .,,.,..,,.. : ..”,>.... . .. . . .. . . . ,., ,,, . . . ... . ... . . ., ., ,,, .,,.,, ,, .. . . byBR5091D SEMICONDUCTOR - TECHNICAL DATA .— .“.,., MC68882 :,, .:..$ .,.:1. 3 Floating-Point Freescale Semiconductor, Inc... . Order this document Freescale Semiconductor, Inc. MOTOROLA . $. “ :’:~.+i ‘!?< :::,., ,,::? \,}txi\\/.. .,1., ,i..:.:,. ..-..,.3 . >ii}}. ,;.:, Coprocessor The MC68882 floating-point coprocessor fully implements the IEEE Standard for Binary Floatin~_+’’,i~’C Point Arithmetic (ANSI-IEEE Standard 754-1985) for use with the Motorola M68000 Family of ,,~f@&~i$ processors. An upgrade of the MC68881, it is pin and software compatible with an optimiz$d ~~$~ interface providing in excess of 1.5 times the performance of the MC68881. It is implem~~~,, ui;ng VLSI technology to give systems designers the highest possible functionality in a ph~:W&~&mali .!.},., ~,,,*.,,,* device. \$.i,,, >$ Intended primarily for use as a coprocessor to the MC68020 or MC68030 32-bi~,~$&@’rocessor unit (MPU), the MC68882 provides a logical extension to the main MPU integer ~~$~~rocessing capabilities. This extension is achieved by providing a very high performan~~oatlng-point arithmetic unit and a set of floating-point data registers which are analogoust$~~t~ &se of the integer data registers. The MC68882 instruction set is a natural extension of a~j $afi~r members of the M68000 Family, and it supports all of the addressing modes of the ~$’~~~. Due to the flexible bus interface of the M68000 Family, the MC68882 can be used wj~~ ari~,of the MPU devices of the M68000 Family and as a peripheral to non-M68000 processors{,{~~ :&+, .,$>. . *), >. $ The major features of the MC68882 are: . :;:,>..+ ..:.?: . ● Eight general purpose floating-point data register%!,,,*..l,k*, ?P~M.8’tipporting a full 80-bit extended ,,**. precision real data format (a 64-bit mantissa plus ~~,~~ bit, and a 15-bit signed exponent). “ -~, . ,J unit to allow very fast cal$ula~~ons~ with intermediate precision greater .3*$;; . format. “ “:*\. etc.). . A 67-bit barrel shifter for high-speed s~jfl~~b d~erations (for normalizing o Special purpose hardware for high-#~~&k~”&nversion of binary real memory operands to and ● A 67-bit arithmetic than the extended from” the internal precision extended . Reduced coprocessor . instructions, . . Forty-six forma~J~$,,~#> interfac$~~wad to increase throughput. includ~n@~~5Jarith metic operations. ~,, \ ,...>.{,., ‘~. Full conformation to the.#~$~}FEE 754 standard, including all requirements and suggestions, .’:’!.., Support of functionsA@”%+,@#ned by the IEEE standard, including a full set of trigonometric and transcendenta~,:t ‘.’:*w, f&ct~ns, .,:s ● Seven data type$$.’b~e, word and long word integers; single, double, ~$% ,:+ real number$),$ndp-acked binary coded decimal string real numbers. ● Twenty-t~t~&$,~~tants ● Virtual @&@@rY/machine available in the on-chip ROM, including and extended n, e, and powers precision of 10, operations. Effi~~ Y}i:,,,, $ I*> .. ,. ;7 :?, ‘:.? > This document contains information on a new product. Specifications and information For More Information On This Product, Go to: www.freescale.com @MoToRoLA INC., 1988 . . .. .. ,. herein are subject to change without notice. .. . MOTOROLA @ BRW/Rev. 3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THE COPROCESSOR CONCEPT The MC68882 functions as a coprocessor in systems where the MC68020 or MC68030 is the main processor via the M68000 coprocessor interface. It functions as a peripheral processor in systems where the main processor is the MC68000, MC68008, or MC68010. The MC68882 utilizes the M68000 Family coprocessor interface to provide a logical extension of the MC68020 or MC68030 registers and instruction set in a manner which is transparent to the programmer. The programmer perceives the MPU/FPCP execution model as if both devices are implemented on one chip. A fundamental goal of the M68000 Family coprocessor interface is to provide the programmer with an execution model based upon sequential instruction execution by the MC68020 or MC68030 and the MC68882. For optimum performante, however, the coprocessor interface allows concurrent operations in the MC68882 with respect to the MC68020 or MC68030 whenever possible. In order to simplify the programmer’s model, the coprocessor interface is designed to emulate, as closely as possible, non-concurrent operation between the MC68020 or MC68030 and the MC68882. The MC68882 is a non-DMA type coprocessor which uses a subset of the general purpose coprocessor interface supported by the MC68020 or MC68030. Features of the interface implemented in the MC68882 are as follows: HARDWARE OVERVIEW The MC68882 is a high performance floating-point device designed to interface with the MC68020 or MC68030 as a coprocessor. This device fully supports the MC68020 or MC68030 virtual machine architecture and is implemented in HCMOS, Motorola’s low power, small geometry process. This process allows CMOS and HMOS (high density NMOS) gates to be combined on the sa,,~ creases speed performance whi~g%~!$g low power consumption, yet still confines th~’~~~~~~1 to .,a reason‘~.s,~;. ,“..t+~ ,,j,,’.J-,$\\ I..\.. ably small die size. ,*~-. !~ ‘k The MC68882 can also Qf ~~,$as a peripheral processor in systems where t@@~~C68020 or MC68030 is not the main processor (e,&};,W&OOO, MC68008, MC68010). The configuration o~$~ ,@68882 as a peripheral processor or coprocqs$@~’m#y be completely transparent to ~,..s ,,,‘,~ ‘ user software (i.e.;%~~’%ame object code maybe executed in either co~~$~::atfon). The ar~&$,~~’re of the MC68882 appears to the user as a lo~i~.,1, e~tension of the M68000 Family architecture, Beca~$@o~the coupling of the coprocessor interface, the ~~fi80’* or MC68030 programmer can view the MC68882 .,.~eg$~ters as though the registers are resident in the #“~68020 or MC68030. Thus, a MC68020 or MC68030 and ‘ “$~e~ MC68882 device pair functions as one processor with . The main processor(s) and MC68882 communicat~~~~jw’ ~~ eight integer data registers, eight address registers, and ~**. via standard M68000 bus cycles. .!> eight floating-point data registers supporting seven float. The main processor(s) and MC68882 cO.~mUti:iing-point and integer data types. cations are not dependent upon the a~@:a&cture The MC68882 programming model is shown in Figures of the individual devices (e.g., instruc@~$~ip&s or 1 through 6 and consists of the following: V;>!]*Q, caches, addressing modes). “..i. , ~).:t.x, ‘:. .* +f{”i,~ ● Eight 80-bit floating-point data registers (FPO-FP7). ● The main processor(s) and MC6@~~~@ay operate These registers are analogous to the integer data ,“~.!.. . ~’x$:’~kl, ,.~\ ~:.,?..:,.. {,m ‘+< at different clock speeds. .?,$:,,, 7* “’’”.: registers (DO-D7) and are completely general pur● MC68882 instructions util,i~~,a$~~ddressing modes pose (i.e., any instruction can use any register). provided by the main @#o9. cessor at the request of the MC68882. ~lt~. .;. > ● Support of virtual memory/virtual machine systerns is provided via the FSAVE and FRESTORE instructions. ● Up to eight coprocessor simultaneously. Multiple type are allowed. may reside in a system coprocessor of the same . Systems may use software emulation of the MC68882 without reassembling or relinking user software. ● .. ,..- A 32-bit status register that contains floating-point condition codes, quotient bits, and exception status information. ● A 32-bit instruction address register that contains the main processor memory address of the last floating-point instruction that was executed. This address is used in exception handling to locate the instruction that caused the exception, The connection between the MC68020 or MC68030 and the MC68882 is a simple extension of the M68000 bus interface. The MC68882 is connected as a coprocessor to the MC68020 or MC68030, and the selection of the MC68882 is based on a chip select which is decoded from the MC68020 or MC68030 function codes and address bus. Figure 7 illustrates the MPU/coprocessor configuration. As shown in Figure 8, the MC68882 is internally divided into three processing elements: the bus interface unit For More Information On This Product, Go to: www.freescale.com MOTOROU 2 ,p p \.; M~ BRW/Rev. 3 ,. -, ,~, ‘./ Freescale Semiconductor, Inc. 7 I FPO I t FP1 \ I I FP2 I , I FP3 r FP4 I FLOATING POINT DATA REGISTERS Freescale Semiconductor, Inc... FP5 ~ ROUNOING 00 01 10 11 MOOE: TO NEAREST TOWARD ZERO TOWARD MINUS INFINIW TOWARD PLUS INFINIV ROUNDING PRECISION: 00 EXTENDED 01 SINGLE 10 DOUBLE 11 (UNDEFINEO, RESERVEO) Figure 3. Mode Control B~e For More Information On This Product, Go to: www.freescale.com MCBRW/Rev, MOTOROM 3 3 Freescale Semiconductor, Inc. 31 30 29 2a 27 26 25 24 N z I NAN o [ NOT A NUMBER lNFINl~ ZERO NEGATIVE Figure 4. Condition Code B~e 23 I s 22 21 20 19 la 17 16 QUOTIENT I Freescale Semiconductor, Inc... 1 Figure 5, Quotient B~e For More Information On This Product, Go to: www.freescale.com OR UNORDERED Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. (BIU), the conversion unit (CU), and the arithmetic proccycle. (The function codes are generated by the M68000 essing unit (APU). The BIU communicates with the Family processors to identify eight separate address MC68620 or MC68030, the CU performs data conversion spaces.)” Thus, the memory-mapped coprocessor interFor binary real data formats, and the APU executes all face registers do not infringe upon instruction or data MC68882 instructions. address spaces. The MC68020 or MC68030 places a coThe BIU contains the coprocessor interface registers processor ID field from the coprocessor instruction onto three of the upper address lines during coprocessor ac(CIRS). In addition to these registers, the register select and DSACK timing control logic is contained in the BIU. cesses. This ID, along with the CPU address space funcFinally, the status flags used to monitor the status of tion code, is decoded to select one of eight coprocessor communications with the main processor are contained in the system. ~~~~.~l, in the BIU. Since the coprocessor interface protocol is ba~~wlely The CU contains special purpose hardware that peron bus transfers, the protocol is easily ernu~?~q~~y softforms data format conversions between binary real data ware when the MC68882 is used as a perl,~~:~~ktiith any formats to and from ‘the internal extended format. The processor capable of memory-mapped @+@yaTan M68000 CU relieves the APU of a significant work load and allows style bus. When used as a periphe$$.@r@ssor with the the MC68882 to execute data movement and preparation 8-bit MC68008, the 16-bit MC68,R{:~$r?he .MC68010, all functions concurrently with arithmetic and transcendenMC68882 instructions are trapp~$:$ the main processor tal calculations, to an exception handler at g$$cut?~n time. Thus, the softThe eight 80-bit floating-point data registers (FPO-FP7) ware emulation of the c~~~~~$~or interface protocol can and the 32-bit control, status, and instruction address be totally transparent%~~:t~&Wser. The MC68882 can preregisters (FPCR, FPSR and FPIAR) are located in the APU. vide a performancetW~~.@ for MC68000-based designs In addition to these registers, the APU contains a highby changing the ‘T~%~@’*processors to the MC68020 or speed 67-bit arithmetic unit used for both mantissa and MC68030. Th,~~pftMre migrates without change to the exponent calculations, a barrel shifter that can shift from next gener&k$&#$eq uipment using the MC68020 or 1 bit to 67 bits in one machine cycle, and ROM constants MC6803@s”’:?JW’ (for use by the internal algorithms or user programs). Sin@’J%&$s is asynchronous, the MC68882 need not The control section of the APU contains the clock genru~.at~g same clock speed as the main processor. Total erator, a two-level microcode sequencer, the microcode ,J,~$&~~mperformance may therefore be customized. For a : Weti CPU performance requirement, the floating-point ROM, and self-test circuitry. The built-in self-test capabilities of the MC68882 enhance reliability and ease man- S+~&.$@’iformance can be selected to meet Particular Price/ ufacturing requirements; however, these diagnost~~~%k~ performance specifications, running the MC68882 at functions are not accessible outside of the special test ‘t slower (or faster) clock speeds than the MPU clock. COPROCESSOR INTERFACE ,, s~i;,y+,.>~. All communications between the MC68@~~OFWC68030 and the MC68882 occur via standard M@~~Q:@>amily bus The MC68882 is design,~t~~~~~erate on 8-, transfers, :f},\,.*7.~: >~$iy, .\\, ,t!, COMMAND/CONDITION STATUS FLAGS t h I RESPOWE CIR ................................................................. RESPONSE PLA 1 .?.%$!,? .l.~~:~ ..,, 1 L .,,,,,\:{.’ f,,, %*,$\$r. ....., *,*\,>~\ .a*t&\ i::,, .St,, $.,,, .,. >1> .,>> :~; MONADIC OPERATIONS o~a program. These moves are also useful at the start and end of a procedure to save and restore the register Monadic operations have one operand. This operand set of the calling routine, In order to reduce procedure may be in a floating-point data register, memory, or in call overhead, the list of registers to be saved or restored an MC68020 or MC68030 data register. The result is alcan be contained in a data register thus enabling runways stored in a floating-point data register. For example, time optimization by allowing a called routine to save as the syntax for square root is: few registers as possible, Note that no rounding or ovFSQRT. ,FPn or, erflow/underflow checking is performed by these operFSQRT.X FPm,FPn or, ations, FSQRT.X FPn For More Information On This Product, Go to: www.freescale.com \ Freescale Semiconductor, Inc. The MC68882 monadic operations available are as fol- Freescale Semiconductor, Inc... lows: FABS FACOS FASIN FATAN FATANH FCOS FCOSH FETOX FETOXMI FGETEXP FGETMAN FINT FLINTRZ FLOGIO FLOG2 FLOGN FLOGNPI FNEG FSIN FSINCOS FSINH FSQRT FTAN FTANH FTENTOX FTST FTWOTOX Absolute Value Arc Cosine Arc Sine Arc Tanqent Hyperb&ic Arc Tangent Cosine Hyperbolic Cosine e to the x Power e to the X Power –1 Get Exponent Get Mantissa Integer Part Integer Part (Truncated) Log Base 10 Log Base 2 Log Base e Log Base e of(x + 1) Negate Sine Simultaneous Sine and Cosine Hyperbolic Sine Square Root Tangent Hyperbolic Tangent 10 to the x Power Test 2 to the x Power the necessary condition checking and reports to the MC68020 or MC68030 whether the condition is true or false. The MC68020 or MC68030 then takes the appropriate action. Since the MC68882 and MC68020 or MC68030 are closely coupled, the floating-point branch operations execute very quickly. The MC68882 conditional operations are: Branch FBCC Decrement and Branch,. ~$:~/. ~!?L.:i::~ ,7.. ,} \;h \,,y~\ ~... ~.:...> Definition Mnemo@$”~,,,:,,, “,,, .:\’.$$..\.\ ‘::,,. . -~ *L ,$, \~,.i~ NOTE \ ~.~~,.a ,,.,{: T@~$@lFB~lngconditional tests do not set the BSUN bit .%&int~g, status register exception byte under any circum‘%$~tances. >;):.’. . False f:.. j F“ &;i ,ih;,~.. ‘~>’ Ordered Greater Than OGT ~~ ..*: ,.,, Ordered Greater Than or Equal OGE .... .J,, ~.+is Ordered Less ,Tha.n OLT DYADIC OPERATIONS ~~,’:~ ::\. Ordered Less Than or’ Equal OLE Dyadic operations have two operands e~$~$~’~~ first Ordered Greater or Less Than OGL operand is in a floating-point data regis\@Y, %?~orYt or Ordered OR an MC68020 or MC68030 data registe~~’$:~~.:;~cond oPUnordered UN erand is the contents of a floating-p~~f$~~~% register. The Unordered or Equal UEQ Unordered or Greater Than UGT destination is the same floating-p~$~%.~%ta register used Unordered or Greater or Equal UGE for the second operand. For ex~&~l,~the syntax for float*,W,, , , i.. Unordered or Less Than ULT ing-point add is: Unordered or Less or Equal ULE ,:2$ follows: NOTE ,Fi:}’~”h . Signaling False SF i$y~~ Multiply Signaling Equal SEQ IEEE Remainder ik~5Q$M Greater Than GT Scale Exponent *$~*FSCALE Greater Than or Equal GE ?**T::... ~...(i:,$.’ kecuted ~~,,o +t’:s ..*1,> . .:.~! ,t>.?:.~~$ \\‘. ., erand). ~s? low” and “active-high” signals. The term assert or :~:.,., The orthogonal instruction set of the MC6~$&~$the assertion is used to indicate that a signal is active flexible branches and addressing modes o&~~~~r68020/ or true, independent of whether that level is repMC68030 allow a programmer or a cQ~p~&’’writer to resented by a high or low voltage. The term negate think of the MC68882 as though it is,,~~$~fithe MC68020 or negation is used to indicate that a signal is inor MC68030. There are no specia~ ‘~~t~$cllons imposed active or false. by the coprocessor interface, ~~’~;~$j~ating-point arithmetic is coded exactly like inta$erjarithmetic. ADDRESS BUS (AO through A4) ,,,,:s.,:,.id.:,~,\. !::,’‘~*,*., ~.~ These active-high address line inputs are used by the \.$~ ,,‘:*1** ,i.$l+ ,~t. ,’.,.1, . ‘.-, .:,:, main processor to select the coprocessor interface reg.~,\p\+ ister locations located in the CPU address space. These MC6W8PQ6MPATIBILITY .>$:,.d~” lines control the register selection ‘as listed in Table 3. ,,~ :,:-: ..,“+ Using the ~~~,~~~~n an existing MC68881 socket does not require&@~~*are changes nor user-software modi“Cc / 7 AO-A4 fications; * SENSE DSACK1 > BIU flag word from the top of the saved idle state frame + * are 32 bytes more than that of the MC68881. However, a unique format word is generated by the MC68882 ensbling the system software to detect this difference. The Figure 10. MC68882 Input/Output Signals For More Information On This Product, Go to: www.freescale.com MCBRW/Rev. 3 ,.,,, .7.. .,.,.,.,,,........... ... .... . ..... ...... .,,.,,...,, . ......... . .. .. ..,, .,.,,. .. ........ . ., ..,,, ,, .,. ,,” MOTOROLA 11 ... . . . ,,, ,,.. .. .. . ,,. .. ..... . . .,, .. .. . ...... . .... . >..,..,,.. ............... ..... .,..”...,., ,,,..,.,,, .,...,.. .,.................;,..,.,,, ,, ,,, ,., . ,,,. .;, ., ..< ,., ....- Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 3. Coprocessor Intetiace Register Selection This active-low input signal indicates that there is a valid address on the address bus, and both the chip select (CS) and read/write (R~) signal lines are valid. A4-AO Offset Oooox $00 16 Read Response Ooolx $02 16 Write Control CHIP SELECT (CS) Oolox $04 16 Read Save Oollx $06 16 R~ Oloox $08 16 – (Reserved) Ololx $OA 16 Write Command Ollox $Oc 16 – (Reserved) Olllx $OE 16 Write Condition 1Ooxx $10 32 Rfi Operand 101OX $14 16 Read Register Select Iollx $16 16 11Oxx $18 32 Read Instruction Address Illxx $lC 32 RR Operand Address This active-low input signal enables the main processor access to the MC68882 coprocessor interface registers. When operating the MC68882 as a peripheral pro$essor, the chip select decode is system dependent (i.~~~j~$the “..., .\\!.+’*: >},i,~ ?? chip select on any peripheral). ..$’s,*k. ~;, .?;.l\ .,,.\$, ~\...:~ *;>K:,, ‘:3,.“~~ ‘%$,, READ/WRITE (R/~) ,h+.t.::~, . !,.’.t..i~..,! This input signal indicates the di~~8]o~#@Y a bus transaction (read/write) by the main~f~~~sbr. A logic high (1) indicates a read from the @8,@~, an~ a logic low (0) indicates a w~te to the ~~~8&The RN signal must be valid when AS is ass@Xl@+~j: ~..+ “.**,?,)$.!+ .‘X., ,,\ -$: ~:t,, . ,>+f, This active-lowin:~~~ignal indicates that there is valid Mdth Register ADDRESS STROBE (AS) Type – Restore (Reserved) data on the d~~~:~ys When the MC68882 is configured to operate over an 8bit data bus, the AO pin is used as an address signal for byte accesses of the coprocessor interface registers. When the MC68882 is configured to operate over a f16- or 32bit system data bus, both the AO and the SIZE pins are strapped high and/or low as listed in Table 4. r .::.:Y during a write bus cycle. ‘?, ~Kese active-low, three-state output signals indicate ..?~,,c&hpletion of a bus cycle to the main processor. The i$$it,~@8882 asserts b~h the DSACKO and DSACKI signals *$rS$$upon assertion of CS. Table 4. System Data Bus Size Configuration ‘-l?+ If the bus cycle is a main processor read, the MC68882 ~i$t Data Bus ~ ,:’ AO SIZE asserts DSACKO and DSACKI signals to indicate that the ,$~$’ .; ‘>:,}, information on the data bus is valid. (Both DSACK signals — 8-Bit Low .tt,. *>:.,. ..*.,,,* ,,.,,, may be asserted in advance of the valid data being placed 16-Bi~$$’Q$y‘?’ Low High on the bus. ) If the bus cycle is a main processor write to .,?, ... :. 3~*qk$;,.~’ High High the MC68882, DSACKO and DSACKI are used to acknowl.~~,;~y$. edge acceptance of the data by the MC68882. ,. ‘\\.~J~.\ .’~:i,> ,,..:.. The MC68882 also uses DSACKO and DSACKI signals ,,,4). > ‘ ‘%;V, $~$ to dynamically indicate to the MC68020/MC68030 the DATA BUS (DO through D31 ) ~~” ‘“~~ “port” size (system data bus width) on a cycle-by-cycle This 32-bit, bidirectional, +~k~%%~bte bus serves as the basis, Depending upon which of the two DSACK pins are general purpose data,~~~h,~etween the MC68020/ asserted in a given bus cycle, the MC68020/MC68030 asMC68030 and the MC~~&~.’’’Regardless of whether the sumes data has been transferred to/from an 8-, 16-, or MC68882 is operat~d a~$~’coprocessor or a peripheral 32-bit wide data port. Table 5 lists the DSACK assertions processor, all in~,@$@o,gessor transfers of instruction inthat are used by the MC68882 for the various bus cycles formation, op~r,~~d$$~ata, status information, and reover the various system data bus configurations. quests for $~~J~@’&ccur as standard M68000 bus cycles. Table 5 indicates that all accesses over a 32-bit bus The MQ@,*~will operate over an 8-, 16-, or 32-bit where A4 equals zero are to 16-bit registers, The MC68882 syste~%at%~,bbs. Depending upon the system data bus implements all 16-bit coprocessor interface registers on conJ~@~~{a@n, both the AO and SIZE pins are configured data lines D16-D31 (to eliminate the need for on-chip s~:~?t~a”lly for the applicable bus configuration. (Refer to multi plexers); however, the MC68020/MC68030 expects :$Q~*ESS BUS (AO through A4) and SIZE (SIZE) for fur16-bit registers that are located in a 32-bit port at odd ‘&#rdetails). word addresses (Al = 1) to be implemented on data lines $$j DO-DI 5. For accesses to these registers when configured SIZE (SIZE) for 32-bit bus operation, the MC68882 generates DSACK signals as listed in Table 5 to inform the MC68020/ This active-low input signal is used in conjunction with MC68030 of valid data on D16-D31 instead of DO-D15. the AO pin to configure the MC68882 for operation over An external holding resistor is required to maintain an 8-, 16-, or 32-bit system data bus. When the MC68882 both DSACKO and DSACKI high between bus cycles. In is configured t~erate over a 16- or 32-bit system data order to reduce the signal rise time, the DSACKO and bus, both the SIZE and AO pins are strapped high and/or DSACKI lines are actively pulled up (negated) by the low as listed in Table 4. For More Information On This Product, Go to: www.freescale.com ~:- ... Freescale Semiconductor, Inc. Table 5. DSACK Assertions Data bus A4 DSACKI DSACKO 32-Bit 1 Low Low Valid Data on D31-DO 32-Bit o Low High Valid Data on D31-D16 16-Bit x Low High Valid Data on D31-D16 or D15-DO 8-Bit x High Low Valid Data on D31-D24,.D23-D16, All x High High Insert Wait States in Current Comments D15-D8, or D7-DO Bus Cycle ~~~~.j, .:J;:::{:.Jy$*s ‘~;$,::::b%?$: I;,,...-ho CONNECT (NC) with all M68000 Family devices, 10 clock cycles should be used as the minimum. .,.,’ t!;:>\ )~ SIZE Input/Output Input Low — G Input Low — m Input Low — Rim Input High/Low — m Input Low — DSACKO, DSACK1 output Low Yes Reset RESET Input Low — Clock CLK Input — — Low No Input — — Input — — ?~$?$s~tro be , , ‘&i,@S-elect ~,t:,)...~ ,> ‘@:J;~ ‘:’%ad/Write .$~,+,)?:., ~\ ‘~3 ‘“.,t{,!~ ‘$~’ Data Strobe ~.~ Data Transfer Sense Device Power Input Ground MCBR=/Rev. . .... .. ... .... . ... ,, ... .,, .,.., ,.” Mnemonic and Size Acknowledge SENSE Vcc GND Input/Output For More Information On This Product, Go to: www.freescale.com MOTOROLA 13 3 .. . . .. , ,,, . .. .. . . . . .. . . ,,. . . . . .. ., ,’ ,.. . ,,, ..,. Freescale Semiconductor, Inc. INTERFACING METHODS MC68882/MC6801 I O OR MC68030 INTERFACING The following paragraphs describe how to connect the MC68882 to an MC68020 or MC68030 for coprocessor operation via an 8-, 16-, or 32-bit data bus, v. A16-A19 ~ DEcoDE I - SIZE 32-Bit Data Bus Coprocessor Connection Figure 11 illustrates the coprocessor interface connection of an MC68882 to an MC68020/MC68030 via a 32-bit data bus. The MC68882 is configured to operate over a 32-bit data bus when both the AO and SIZE pins are connetted to VCC. FCO-FC2 a- A20-A31 — Freescale Semiconductor, Inc... A16-A19 A13-A15 ~ ~ 8 z E 0 ~ 0 z z A5-A12 — A1-A4 ~ AO CHIP SELECT OECODE E Vcc SIZE A1-A4 E E R~ D24-031 D24-D31 016-D23 D16-D23 FCO-FC2 D8-D15 D8-D15 DO-D? DO-D7 DSACKO DSACK1 MAIN PROCESSOR CLOCK ./,:, ,,. . ,,,,,$:/; 16-Bit Data Bus @+@oce&sor Connection Figure 12 ill.y~~~#’the coprocessor interface connection of an M~m2 to an MC68020/MC68030 via a 16-bit data bu~i,~k~WC68882 is configured to operate over a 16-bit,@~d~~ bus when the SIZE pin is connected to VCC, and. t~e ~0 pin is connected to GND. The sixteen leasts~~k~?arit data pins (DO-D15) must be connected to the $:a~~~~en most-significant data pins (D1 6-D31 ) when the !&&8882 is configured to operate over a 16-bit data bus ~.e., connect DO to D16, DI to D17, . . . and D15 to D31). The DSACK pins of the two devices are directly connected, although it is not necessary to connect the DSACKO pin since the MC68882 never asserts it in this configuration. 08-015 Da-D15 =H J + MAIN PROCESSOR CLOCK figure 13. 8-Bit Data Bus Coprocessor DO-07 DSACKO OSACK1 \ ? COPROCESSOR CLOCK Connection bus. The MC68882 is configured to operate over an 8-bit data bus when the SIZE pin is connected to GND. The twenty-four least-significant data pins (DO-D23) must be connected to the eight most-significant data pins (D24- Figure 13 illustrates the connect of an MC68882 to an MC68020/MC68030 as a coprocessor over an 8-bit data ,., D24-D31 D16-D23 DO-D7 m 8-Bit Data Bus Coprocessor Connection MOTOROU 14 D24-D31 D16-D23 For More Information On This Product, Go to: www.freescale.com MCBRW/Rav. ,, .. 3 . . ....,,,. . . .. . .. ,,. - Freescale Semiconductor, Inc. D31) when the MC68882 is configured to operate over an 8-bit data bus (i.e., connect DO to D8, D16 and D24; DI to D9, D17, and D25; . . . and D7 to D15, D23 and D31). The DSACK pins of the two devices are directly connetted, although it is not necessary to connect the DSACKI pin since the MC68882 never asserts it in this configuration. MC68882-MC68000/MC68008/MC68010 INTERFACING The following paragraphs describe how to connect the MC68882 to an MC68000, MC68008, or MC6801 O processor for opertion as a peripheral via an 8- or 16-bit data bus. 16-Bit Data BUS Peripheral Processor Connection Freescale Semiconductor, Inc... Figure 14 illustrates the connection of an MC68882 to an MC68000 or MC68010 as a peripheral processor over a 16-bit data bus. The MC68882 is configured to operate over a 16-bit data bus when the SIZE pin is connected to Vcc, and the AO pin is connected to GND. The sixteen least-significant data pins (DO-DI 5) must be connected to the sixteen most-significant data pins (D16-D31 ) when the MC68882 is configured to operate over a 16-bit data bus (i.e., connect DO to D16, DI to D17, ,.. and D15 to D31). The DSACKI pin of the MC68882 is connected to the DTACK pin of the main processor, and the DSACKO pin is not used. When connected as a peripheral processor, the MC68882 chip select (CS) decode, is system dependent. If the MC68000 is used as the main processor, the MC68882 CS must be decoded in the supervisor or user data spaces, However, if the MC68010 is used for the main processor, the MOVES instruction may be used to emulate any CPU space access that the MC68020/MC68030 generates for coprocessor communications. Thus, the CS decode logic for such systems may be the same as in an MC68020/ MC68030 system, such that the MC68882 will not-’hse any .,;*s.t::\~& k};* .g ~,., Symbol Max Characteristic Min Unit ,,.,...... > lnpu#Wg~+oltage vlH Vcc 2.0 v ● ?k~:~’:~dw \,oltage — ~~ Leakage Current @t5.25 V $ ~ji~t —— —— CLK, RESET, R/~, AO-A4, CS, DS, AS, SIZE ~Hi-Z (Off State) ,Input Current ~1.2.4 V/O.4V vlL GND –0,5 0.8 v Iin — 10 WA ~, m, DO-D31 ITSI — 20 FA Output High Voltage (IOH = -400 wA) ~, m, DO-D31 vOH 2.4 — v Output Low Voltage (iOL = 5,3 mA) ~, ~, DO-D31 vOL — 0.5 v SENSE IOL — 500 PA Output Low Current (VOL= GND) Power Dissipation pD — 0.75 w Capacitance* (Vin =0, TA=250C, f= 1 MHz) Cin 20 pF Output Load Capacitance CL — — 130 pF *Capacitance is periodically sampled rather than 10070tested. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AC ELECTRICAL — CLOCK INPUT CHARACTERISTICS (VCC=5.O Vdc* 570; GND=O Vdc; TA=O to 70°C; refer to Figure 16) 16.67 MHz Num Characteristic Frequency Freescale Semiconductor, Inc... 1 of Operation Cycle Time 2,3 Clock Pulse Width for 33 MHz) 4,5 Rise and Fall Times (VCC=5.O Vdc* (Measured 5%; GND=O Vdc; TA=O 65 Address Valid to ~ 6A5 Address 6B5 Address Valid to ~*As~~ed \ Valid ~“~~k~setied 76 ~ 33.33 MHz Max Min Max Min Max Min Max ‘nit 8 16.67 12.5 20 12.5 25 16.7 33.33 MHz 60 125 50 80 40 80 30 60 ns 24 95 20 54 15 59 14 — 5 — 5 — 4 — q,s ..,’..,., ..:’,}*.. *,,i+i.,, 3$’ ‘F.:. , ,“ ;,,, Rs ~!?,~. a?>,, ,\$* 66 17, 18, and 19) 16.67 MHz 20 MHz 25 MHz 33.33 MHz Unit Min Max Min Max Min Max Min Max 15 — 10 — 5 — 5 — ns (Read) 15 — 10 — 5 — 5 — ns (Write) 50 — 50 — 35 — 26 — ns 5 — 5 — ns Invalid 10 — 10 — Invalid 10 — 10 — 5 — 5 — ns o — o — o — o — ns to ~ Asserted to ~ Asserted (Read) o — o — o — o — ns q~ f,k. @ Asserted to ~ Asserted (Write) 30 — 25 — 20 — 15 — ns 89 ~%g~ Nega@&i~@yAddress ~ 1.5 V to 1.5 V ~~@@$refer ~1$ ,* $>\.*::>.” ? :.‘,, .,,. ,.?*\\> ,.,/