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M68000UMAD/AD
Communications and Advanced
Consumer Technologies Group
M68000
Addendum to
Freescale Semiconductor, Inc...
M68000
User Manual
August 7, 1997
This addendum to the M68000UM/AD User’s Manual, Revision 8, provides corrections to the original text as
well as additional information. This document and other information on this product is maintained on the World
Wide Web at http://www.motorola.com/68000.
OVERVIEW
This manual includes hardware details and programming information for the MC68HC000, the MC68HC001,
the MC68EC000, and the MC68SEC000. For ease of reading, the name M68000 MPUs will be used when
referring to all processors. Refer to M68000PM/AD, M68000 Programmer's Reference Manual, for detailed
information on the MC68000 instruction set.
The four microprocessors are very similar to each other and all contain the following features:
•
Sixteen 32-Bit Data and Address Registers
•
16-Mbyte Direct Addressing Range
•
Program Counter
•
6 Instruction Types
•
Operations on Five Main Data Types
•
Memory-Mapped Input/Output (I/O)
•
14 Addressing Modes
The following processors contain additional features:
•
MC68HC001/MC68EC000/MC68SEC000
—
•
Statically selectable 8- or 16-bit data bus
MC68HC000/MC68EC000/MC68HC001/MC68SEC000
—
Low power
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
1997 Motorola, Inc. All Rights Reserved.
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The primary features of the MC68SEC000 embedded processor include the following:
• Direct Replacement for the MC68EC000
—
—
—
Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP packages
Vast selection of existing third-party development tools for the MC68EC000 support the
MC68SEC000
Software written for the MC68EC000 will run unchanged on the MC68SEC000
• Power Management
—
—
—
—
Freescale Semiconductor, Inc...
•
Low-power HCMOS technology
Static design allows for stopping the processor clock
3.3V or 5V operation
Typical 0.5µA current consumption at 3.3V in sleep mode
Software Strength
—
—
Fully upward object-code compatible with other M68000 Family products
M68000 architecture allows effective assembly code with a C compiler
• Upgrade
—
—
Fully upward code-compatible with higher performance 680x0 and 68300 Family members
ColdFire® code-compatible with minor modifications
1. MC68HC000
The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates less power (by
an order of magnitude) than the NMOS MC68000.
The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The
MC68HC000 has a 16-bit data bus implementation of the MC68000 and is upward code-compatible with the
MC68010 and the MC68020 32-bit implementation of the architecture.
1.1 MC68HC001
The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/32-bit microprocessor with
the addition of statically selectable 8- or 16-bit data bus operation. The MC68HC001 is object-code compatible
with the MC68HC000. You can migrate code written for the MC68HC001 without modification to any member
of the M68000 Family.
1.2 MC68EC000
The MC68EC000 is an economical high-performance embedded controller designed to suit the needs of the
cost-sensitive embedded-controller market. The HCMOS MC68EC000 has an internal 32-bit architecture that
is supported by a statically selectable 8- or 16-bit data bus. This architecture provides a fast and efficient
processing device that can satisfy the requirements of sophisticated applications based on high-level
languages.
The MC68EC000 is fully object-code compatible with the MC68000. You can migrate code written for the
MC68EC000 without modification to any member of the M68000 Family.
The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with
8-bit microprocessors. The MC68EC000 benefits from the rich M68000 instruction set and its related high code
density with low memory bandwidth requirements.
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1.3 MC68SEC000
The MC68SEC000 is a cost-effective static embedded processor engineered for low-power applications. In
addition to providing the substantial cost and performance benefits of the MC68EC000, the low-power mode
of the MC68SEC000 provides significant advantages in power consumption and power management. The
typical current consumption of the MC68SEC000 is only 0.5µA in static standby mode and 15.0mA in normal
3.3V operation. The MC68SEC000 operates in either 3.3V or 5.0V systems. The remarkably low power
consumption, small footprint packages, and static implementation are combined in the MC68SEC000 for lowpower applications such as portable measuring equipment, electronic games, and battery-operated hand-held
consumer products.
Freescale Semiconductor, Inc...
The HCMOS MC68SEC000’s static architecture is a direct replacement for the MC68EC000, which offers the
lowest cost entry point to 32-bit processing. The internal 32-bit architecture provides fast and efficient
processing that satisfies the requirements of sophisticated applications based on high-level languages.
All of the existing third-party developer tools widely available for the MC68EC000 will directly support the
MC68SEC000. You can find detailed descriptions of these tools in the High Performance Embedded Systems
Source Catalog.
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2.0 SIGNAL DESCRIPTION
Change Figure 3-3 on Page 3-2.
VCC
A23-A0
ADDRESS BUS
GND
CLK
D15-D0
DATA BUS
AS
FC0
FC1
FC2
Freescale Semiconductor, Inc...
PROCESSOR
STATUS
R/W
UDS
LDS
ASYNCHRONOUS
BUS CONTROL
DTACK
MC68SEC000
BR
BG
BERR
RESET
SYSTEM
CONTROL
BUS ARBITRATION
CONTROL
IPL0
IPL1
HALT
IPL2
MODE
AVEC
INTERRUPT
CONTROL
Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)
2.1 Data Bus (D15-D0)
In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15D8 are undefined.” with “Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can
statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and
MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined.”
2.2 Bus Arbitration Control
In Section 3.4 on page 3-5, the sentence “In the 48-pin version of the MC68008 and MC68EC000, no pin is
available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration
scheme.” should read “In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant
acknowledge signal. These microprocessors use a two-wire bus arbitration scheme.”
2.3 System Control
The Mode subsection heading of Section 3.6 on page 3-7 should read ‘‘Mode (MODE) (MC68HC001/
68EC000/68SEC000).’’
2.4 MC68SEC000 Low-Power Mode
Add the following to Sections 4 and 5, Bus Operation.
The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section
describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the
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power consumption to its quiescent value1 while maintaining the internal state of the processor. The
low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided
by Motorola.
To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A
recommended method for entering the low-power mode is to use the TRAP instruction, which causes the
processor to begin exception processing, thus entering the supervisor mode. External circuitry should
accomplish the following steps during the trap routine:
Freescale Semiconductor, Inc...
1. Externally detect a write to the low-power address. You select this address which can be any address
in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be
detected by polling A23–A0, R/W, and FC2–FC0. When the low-power address is detected, R/W is
a logic low, and the function codes have a five (101) on their output, the processor is writing to the
low-power address in supervisor mode and user-designed circuitry should assert the
ADDRESS_MATCH signal shown in Figure 2 and Figure 3.
D
ADDRESS_MATCH
D
Q
CK
AS
D
Q
CK
CK
AS
Q
Q
Q
Q
CPU_CLK
CL
CL
RESTART
RESET
SYSTEM_CLK
Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus
D
ADDRESS_MATCH
AS
D
Q
CK
AS
CK
RESTART
RESET
AS
Q
CK
Q
Q
CL
D
Q
CL
D
Q
CK
Q
Q
CL
CPU_CLK
SYSTEM_CLK
Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus
2. Execute the STOP instruction. The external circuitry shown in Figure 2 and Figure 3 will count the
number of bus cycles starting with the write to the low-power address and will stop the processor
clock on the first falling edge of the system clock after the bus cycle that reads the immediate data
of the STOP instruction. Figure 3 has one more flip-flop than Figure 2 because the MC68SEC000 in
1.
5
The preliminary specification for the MC68SEC000’s current drain while in the low-power mode is Idd < 2µA for 3.3V operation and
Idd < 5µA for 5.0V operation.
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8-bit mode requires two bus cycles to fetch the immediate data of the STOP instruction. After the
processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit.
This can be done, but be careful that runt clocks and spurious glitches are not presented to the
MC68SEC000. A timing diagram is shown in Figure 4.
CLK
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
CPU_CLK
AS
Freescale Semiconductor, Inc...
RW
DTACK
Write to
Low-Power
Address
Fetch Immediate
Data of STOP
Instruction
Stop
Figure 4. MC68SEC000 Clock Stop Timing for 16-Bit Data Bus
Note: While the MC68SEC000 is in the low-power mode, all inputs must be driven to VDD or VSS, or have a
pull-up or pull-down resistor.
3. This step is optional depending on whether your applications require the MC68SEC000 signals with
three-state capability to be placed into a high-impedance state. To place the MC68SEC000 into a
three-state condition, the proper method for arbitrating the bus (as described in 5.2 Bus Arbitration
in the M68000 User’s Manual, Rev 8) should be completed during the fetch of the status register data
for the STOP instruction. A timing diagram with the bus arbitration sequence is shown in Figure 5.
CLK
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
CPU_CLK
AS
RW
DTACK
BR
BG
Write to
Low-Power
Address
Fetch Immediate
Data of STOP
Instruction
Stop
Figure 5. MC68SEC000 Clock Stop Timing with Bus Arbitration for 16-Bit Data Bus
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After the previous steps are completed, the MC68SEC000 will remain in the low-power mode until it
recognizes the appropriate interrupt . External logic will also have to poll IPLB2–IPLB0 to detect the proper
interrupt. When the correct interrupt level is received, the following steps will bring the processor out of the
low-power mode:
1. Restart the system clock if it was stopped.
2. Wait for the system clock to become stable.
3. Assert the RESTART signal. This will cause the processor’s clock to start on the next falling edge of
the system clock. Figure 6 shows the timing for bringing the processor out of the low-power mode.
Both the RESTART and RESET signals are subject to the asynchronous setup time as specified in
the Electrical Characteristics section of this addendum.
WARNING
Freescale Semiconductor, Inc...
The system clock must be stable before the RESTART signal is asserted
to prevent glitches in the clock. An unstable clock can cause unpredictable
results in the MC68SEC000.
CLK
CPU_CLK
RESTART
Figure 6. MC68SEC000 Clock Start Timing
4. If the MC68SEC000 was placed in a three-state condition, the BR signal must be negated before the
processor can begin executing instructions.
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An example trap routine is as follows:
TRAP_x
MOVE.B #0,$low_power_address
STOP #$2000
RTE
/* Write that causes ADDRESS_MATCH to assert */
/* STOP instruction with desired interrupt mask */
/* Return from the exception */
The first instruction (MOVE.B #0,$low_power_address) writes a byte to the low-power address that will
cause the external circuitry to begin the sequence that will stop the processor’s clock. The second
instruction (STOP #$2000) loads the SR with the immediate data. This lets you set the interrupt that will
cause the processor to come out of the low-power mode. The final instruction (RTE) tells the processor to
return from the exception and resume normal processing.
3.0 MC68SEC000 ELECTRICAL SPECIFICATIONS
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Add to the following table to Section 10.1.
3.1 MC68SEC000 MAXIMUM RATINGS
RATING
SYMBOL
VCC
VALUE
–0.3 to 6.5
Input Voltage
Vin
–0.5 to 6.5
V
Maximum Operating
Temperature Range
Commercial Extended "C" Grade
TA
TL to TH
0 to 70
–40 to 85
–55 to 150
°C
Supply Voltage
Storage Temperature
Tstg
UNIT
V
°C
3.2 CMOS CONSIDERATIONS
The following change should be made to Section 10.4, CMOS Considerations.
“Although the MC68HC000 and MC68EC000 is implemented with input protection diodes, care should be
exercised to ensure that the maximum input voltage specification is not exceeded.” should read “Although
the MC68HC000, MC68EC000, and MC68SEC000 are implemented with input protection diodes, be
careful not to exceed the maximum input voltage specification.”
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4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 on page 10-6 with Figure 7.
DRIVE
TO 2.4 V
2.0 V
2.0 V
CLK
0.8 V
0.8 V
A
DRIVE TO
0.5 V
OUTPUTS(1) CLK
B
2.0 V
VALID
OUTPUT n 0.8 V
2.0 V
0.8 V
VALID
OUTPUT
A
n+1
Freescale Semiconductor, Inc...
B
2.0 V
VALID
OUTPUT n
0.8 V
OUTPUTS(2) CLK
C
DRIVE TO
2.4 V
2.0 V
INPUTS(3) CLK
DRIVE TO
0.5 V
0.8 V
2.0 V
0.8 V
VALID
OUTPUT n+1
D
2.0 V
VALID
INPUT
0.8 V
C
2.0 V
INPUTS(4) CLK
0.8 V
D
VALID
INPUT
2.0 V
0.8 V
DRIVE
TO 2.4 V
DRIVE
TO 0.5 V
2.0 V
ALL SIGNALS(5)
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
Figure 7. Drive Levels and Test Points for AC Specifications - applies to all parts
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5.0 MC68SEC000 DC ELECTRICAL SPECIFICATIONS
Add the following table to Section 10.13 on page 10-23.
(VCC = 5.0 Vdc ±5%, 3.3 Vdc ±10%,; GND = 0 Vdc; TA = TL to TH)
3.3 V
Freescale Semiconductor, Inc...
CHARACTERISTIC
5.0 V
Input High Voltage
SYMBOL
VIH
MIN
2.0
MAX
VCC
MIN
2.0
MAX
VCC
UNIT
V
Input Low Voltage
VIL
GND
0.8
0.8
V
Input Leakage Current BERR, BR, DTACK, CLK, I PL2-IPL0, AVEC
MODE, HALT, RESET
Three-State (Off State) Input Current
Iin
—
—
—
2.5
20
2.5
uA
ITSI
2.5
20
2.5
GND –
0.5
—
Output High Voltage
VOH
2.4
—
VCC–0.75
—
Output Low Voltage
(IOL = 1.6 mA) HALT
(IOL = 3.2 mA) A23–A0, BG, FC2–FC0
(IOL = 5.0 mA) RESET
(IOL = 5.3 mA) AS, D15–D0, LDS, R/W, UDS
Current Dissipation*
f = 0 Hz
VOL
uA
V
V
ID
—
—
—
—
—
0.5
0.5
0.5
0.5
0.7
—
—
—
—
—
0.5
0.5
0.5
0.5
1.0
mA
f=10MHz
f=16 MHz
f= 20 MHz
Capacitance (Vin = 0 V, TA = 25 °C, Frequency = 1 MHz)**
Cin
—
—
—
—
10
15
20
20.0
—
—
—
—
15
25
30
20.0
mA
mA
mA
pF
Load Capacitance
CL
—
70
130
—
70
130
pF
HALT
All Others
*During normal operation, instantaneous Vcc current requirements may be as high as 1.5A.
Currents listed are with no loading.
**Capacitance is periodically sampled rather than 100% tested.
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6.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — CLOCK
TIMING (See Figure 2)
Add the following table and Figure 8 to Section 10.9 on page 10-9.
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NUM.
1
2,3
CHARACTERISTIC
Frequency of Operation
Cycle time
Clock Pulse Width
SYMBOL
f
tcyc
tCL
tCH
MIN
0
100
45
45
4,5
Clock Rise and Fall Times
tCr
tCf
—
—
10MHz
MAX
10.0
—
—
—
16MHz
10
10
20MHz
min
0
60
27
27
max
16.7
—
—
—
min
0
50
21
21
max
20.0
—
—
—
UNIT
MHz
ns
ns
—
—
5
5
—
—
4
4
ns
Applies to 3.3V and 5V.
1
2
3
2.0 V
0.8 V
4
5
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a
high voltage of 2.0 V, unless otherwise noted. The voltage swing through this
range should start outside and pass through the range such that the rise or
fall will be linear between 0.8 V and 2.0 V.
Figure 8. MC68SEC000 Clock Input Timing Diagram
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7.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — READ AND
WRITE CYCLES
Add the following table and Figures 9 and 10 to Section 10.16.
Applies to 3.3V and 5V.
(GND = 0 V; TA = TL to TH; see Figures 3 and 4)
NUM
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6
6A
7
CHARACTERISTIC
Clock Low to Address Valid
Clock High to FC Valid
Clock High to Address, Data Bus High Impedance (Maximum)
(Write)
Clock High to Address, FC Invalid (Minimum)
Clock High to AS, LDS, UDS Asserted
8
91
Address Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted
(Write)
11A2 FC Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted (Write)
121 Clock Low to AS, LDS, UDS Negated
112
16MHz
MIN
MAX
—
30
0
30
—
50
20MHz
MIN
MAX
—
25
0
25
—
42
UNIT
ns
ns
ns
0
3
—
35
0
3
—
30
0
3
—
25
ns
ns
20
—
15
—
10
—
ns
45
—
45
—
40
—
ns
3
35
3
30
3
25
ns
2
AS, LDS, UDS Negated to Address, FC Invalid
15
—
15
—
10
—
ns
2
AS (and LDS, UDS Read) Width Asserted
195
—
120
—
100
—
ns
95
—
60
—
50
—
ns
105
—
60
—
50
—
ns
13
14
14A2 LDS, UDS Width Asserted (Write)
152 AS, LDS, UDS Width Negated
16
172
Clock High to Control Bus High Impedance
AS, LDS, UDS Negated to R/W Invalid
—
15
55
—
—
15
50
—
—
10
42
—
ns
ns
181
Clock High to R/W High (Read)
0
35
0
30
0
25
ns
201
Clock High to R/W Low (Write)
0
35
0
30
0
25
ns
2,6
AS Asserted to R/W Low (Write)
—
10
—
10
—
10
ns
2
Address Valid to R/W Low (Write)
0
—
0
—
0
—
ns
21A
FC Valid to R/W Low (Write)
50
—
30
—
25
—
ns
222
23
R/W Low to DS Asserted (Write)
50
—
30
—
25
—
ns
252
Clock Low to Data-Out Valid (Write)
AS, LDS, UDS Negated to Data-Out Invalid (Write)
—
30
35
—
—
15
30
—
—
10
25
—
ns
ns
262
Data-Out Valid to LDS, UDS Asserted (Write)
30
—
15
—
10
—
ns
275
Data-In Valid to Clock Low (Setup Time on Read)
5
—
5
—
5
—
ns
282
28A
AS, LDS, UDS Negated to DTACK Negated (Asynchronous Hold)
0
110
0
110
0
95
ns
Clock High to DTACK Negated
0
110
0
110
0
95
ns
20A
21
2
12
10MHz
MIN
MAX
—
35
0
35
—
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AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
NUM
CHARACTERISTIC
Freescale Semiconductor, Inc...
29
29A
30
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
AS, LDS, UDS Negated to Data-In High Impedance (Read)
AS, LDS, UDS Negated to BERR Negated
2,5
DTACK
Asserted to Data-In Valid (Setup Time on Read)
31
32 HALT and RESET Input Transition Time
33 Clock High to BG Asserted
34 Clock High to BG Negated
35 BR Asserted to BG Asserted
367 BR Negated to BG Negated
38
10MHz
MIN
MAX
0
—
—
150
0
—
—
65
16MHz
MIN
MAX
0
—
—
90
0
—
—
50
20MHz
MIN
MAX
0
—
—
75
0
—
—
42
0
—
—
1.5
1.5
150
35
35
3.5
3.5
0
—
—
1.5
1.5
150
30
30
3.5
3.5
0
—
—
1.5
1.5
150
25
25
3.5
3.5
ns
ns
ns
Clks
Clks
UNIT
ns
ns
ns
ns
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
BG Width Negated
AS, LDS, UDS Negated to AVEC Negated
Asynchronous Input Setup Time
—
55
—
50
—
42
ns
1.5
0
5
—
55
—
1.5
0
5
—
50
—
1.5
0
5
—
42
—
Clks
ns
ns
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
564
Data-In Hold from Clock High
Data-Out Hold from Clock High (Write)
R/W Asserted to Data Bus Impedance Change (Write)
HALT, RESET Pulse Width
0
0
20
10
—
—
—
—
0
0
10
10
—
—
—
—
0
0
0
10
—
—
—
—
ns
ns
ns
Clks
587
BR Negated to AS, LDS, UDS, R/W Driven
1.5
—
1.5
—
1.5
—
Clks
1
—
1
—
1
—
Clks
39
44
475
482,3
52
53
55
7
58A
BR Negated to FC Driven
Applies to 3.3V and 5V.
NOTES: 1.
13
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
Actual value depends on clock period.
3.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
5.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6.
When AS and R/W are equally loaded (±20%), subtract 5 ns from the values given in these columns.
7.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
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S0
S1
S2
S3
S4
S5
S6
S7
CLK
6A
FC2–FC0
8
6
A23–A0
Freescale Semiconductor, Inc...
7
12
15
AS
14
11
13
11A
LDS / UDS
17
9
18
R/W
28
47
DTACK
27
48
29
31
DATA IN
47
30
BERR / BR
(NOTE 2)
47
47
32
HALT / RESET
32
56
47
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the
next falling edge of the clock.
2. BR need fall at this time only to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 V and 2.0 V.
Figure 9. MC68SEC000 Read Cycle Timing Diagram
14
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S0
S1
S2
S3
S4
S5
S6
S7
CLK
6A
FC2–FC0
8
6
A23–A0
Freescale Semiconductor, Inc...
7
12
15
AS
14
9
13
11
9
11A
LDS / UDS
20A
17
14A
20
18
21
22
R/W
21A
28
47
55
DTACK
26
53
23
7
48
25
DATA OUT
47
30
BERR / BR
(NOTE 2)
47
47
32
HALT / RESET
32
56
47
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between 0.8 V and 2.0 V.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A).
Figure 10. MC68SEC000 Write Cycle Timing Diagram
MOTOROLA
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Freescale Semiconductor, Inc.
8.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — BUS
ARBITRATION
Add the following table and Figure 11 to Section 10.17.
Freescale Semiconductor, Inc...
(GND = 0 Vdc; TA = TL to TH; refer to Figure 13)
NUM
CHARACTERISTICp
7
16
33
34
35
36
38
581
Clock High to Address, Data Bus High Impedance (Maximum)
Clock High to Control Bus High Impedance
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted
BR Negated to BG Negated
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
BG Width Negated
Asynchronous Input Setup Time
BR Negated to AS, LDS, UDS, R/W Driven
58A1
BR Negated to FC Driven
39
47
10MHz
MIN
MAX
—
55
—
55
0
35
0
35
1.5
3.5
1.5
3.5
—
55
16MHz
MIN
MAX
—
50
—
50
0
30
0
30
1.5
3.5
1.5
3.5
—
50
20MHz
MIN
MAX
—
42
—
42
0
25
0
25
1.5
3.5
1.5
3.5
—
42
1.5
5
1.5
—
—
—
1.5
5
1.5
—
—
—
1.5
5
1.5
—
—
—
Clks
ns
Clks
1
—
1
—
1
—
Clks
UNIT
ns
ns
ns
ns
Clks
Clks
ns
Applies to 3.3V and 5V.
1. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
16
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STROBES
AND R/W
36
BR
35
34
39
BG
33
38
Freescale Semiconductor, Inc...
CLK
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA
guarantees their recognition at the next falling edge of the clock.
Figure 11. Bus Arbitration Timing
CLK
47
33
BR
34
35
36
BG
39
38
58
AS
LDS/UDS
DS
R/W
58A
FC2–FC0
A23
A19–A0
D15D7–D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
Figure 12. MC68SEC000 Bus Arbitration Timing Diagram
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Freescale Semiconductor, Inc.
CLK
47
33
BR
34
35
BG
Freescale Semiconductor, Inc...
38
AS
DS
VMA
R/W
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.
Figure 13. Bus Arbitration Timing—Idle Bus Case
18
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CLK
47
33
BR
34
35
BG
Freescale Semiconductor, Inc...
16
AS
DS
VMA
R/W
FC2-FC0
7
A23-A0
D15-D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
This diagram also applies to the 68EC000.
Figure 14. Bus Arbitration Timing - Active Bus Case
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Freescale Semiconductor, Inc.
CLK
47
33
BR
35
39
39
36
BG
Freescale Semiconductor, Inc...
38
58
AS
DS
57A
VMA
R/W
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
This diagram also applies to the 68EC000.
Figure 15. Bus Arbitration - Multiple Bus Request
20
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9.0 MECHANICAL DATA
9.1 PIN ASSIGNMENTS
Add Figure 12 to Section 11.1.
Freescale Semiconductor, Inc...
64
R/W
D11
D10
D9
D8
D7
D6
D5
GND
D4
D3
D2
D1
D0
AS
UDS
LDS
The following defines the pin assignment and the package dimensions of the 64 lead QFP (FU package)
and 64 lead TQFP (PB package) for the MC68SEC000. Note that it is pin-to-pin compatible with the
MC68EC000.
49
48
1
D12
DTACK
D13
BG
D14
BR
D15
VCC
CLK
A23
GND
A21
A22
MODE
VCC
A20
MC68SEC000FU/PB
HALT
RESET
A19
AVEC
A18
BERR
A17
IPL2
A16
IPL1
A15
IPL0
A14
A11
A13
A12
A9
A10
A8
A7
A6
A5
A4
GND
A3
A2
A1
A0
33
32
FC0
16
17
FC1
FC2
Figure 16. 64-Lead Quad Flat Pack and 64-Lead Thin Quad Flat Pack
MOTOROLA
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Freescale Semiconductor, Inc.
10.0 PACKAGE DIMENSIONS - FU SUFFIX
This diagram replaces the one on Page 11-16
64 Lead Quad Flat Pack Case 840B-01
R
Freescale Semiconductor, Inc...
G
A
H
M
B
S
L
D
K
C
DIM
A
B
C
D
G
H
K
L
M
R
S
22
MILLIMETERS
MIN
16.95
13.90
16.95
13.90
0.30
INCHES
MAX
17.45
14.10
17.45
14.10
0.45
MIN
0.667
0.547
0.667
0.547
0.012
0.80 BSC
2.15
0.13
2.00
MAX
0.687
0.555
0.687
0.555
0.018
0.031 BSC
2.45
0.23
2.40
0.085
0.005
0.79
12.00 REF
12.00 REF
0.096
0.009
0.094
0.472 REF
0.472 REF
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Freescale Semiconductor, Inc.
11.0 PACKAGE DIMENSIONS - PB SUFFIX
Add the following to Section 11.2.
64 Lead Thin Quad Flat Pack Case 840F-02
G
H
M
Freescale Semiconductor, Inc...
A1 B1
A
B
D1
C1
L
K
D
C
DIM
A
A1
B
B1
C
C1
D
D1
G
H
K
L
M
MOTOROLA
MILLIMETERS
MAX
12.00 BSC
6.00 BSC
10.00 BSC
5.00 BSC
12.00 BSC
6.00 BSC
10.00 BSC
5.00 BSC
0.17
0.27
0.50 BSC
--1.60
0.09
0.20
1.35
1.45
MIN
INCHES
MIN
MAX
0.472 BSC
0.236 BSC
0.394 BSC
0.197 BSC
0.472 BSC
0.236 BSC
0.394 BSC
0.197 BSC
0.007
0.011
0.020 BSC
--0.004
0.053
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0.063
0.008
0.057
23
Freescale Semiconductor, Inc.
12.0 PACKAGE/FREQUENCY AVAILABILITY
Replaces Section 11.1
The following tables identify the packages and operating frequencies available for the MC68HC000,
MC68HC001, MC68EC000, and the MC68SEC000.
MC68SEC000
PACKAGE
Quad Flat Pack (FU)
10 MHz
16 MHz
20MHz
10 MHz
16 MHz
20MHz
Thin Quad Flat Pack (PB)
Freescale Semiconductor, Inc...
FREQUENCY
MC68HC000
PACKAGE
Plastic DIP
Plastic Quad Pack (PLCC)
Plastic Quad (Gull Wing)**
Pin Grid Array, Solder Lead Finish**
Pin Grid Array, Gold Lead Finish**
Plastic Quad Pack (PLCC)
MC68HC001**
PACKAGE
Plastic Quad Pack (PLCC)
Plastic Quad (Gull Wing)
Pin Grid Array, Gold Lead Finish
MC68EC000
PACKAGE
Plastic Quad Pack (PLCC)
Plastic Quad Flat Pack
VOLTAGE
3.3 V
✓
✓
✓
✓
✓
✓
FREQUENCY
8,10,12,16,20 MHz
8,10,12,16,20 MHz
8,10,12,16,20 MHz
8,10,12,16,20 MHz
8,10,12,16,20 MHz
FREQUENCY
8,10,12,16 MHz
8,10,12,16 MHz
8,10,12,16 MHz
8,10,12,16 MHz
FREQUENCY
8 MHz
10 MHz
12 MHz
16 MHz
20 MHz
5V
✓
✓
✓
✓
✓
✓
VOLTAGE
5V
3
3
3
3
3
VOLTAGE
5V
✓
✓
✓
✓
VOLTAGE
5V
✓
✓
✓
✓
✓
NOTE : ** not recommended for new designs
24
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ORDERING INFORMATION
Add the following to Section 11.
The following tables contains the ordering information for the MC68SEC000.
MC68SEC000 Ordering Information
PACKAGE
BODY SIZE
LEAD SPACING
QFP
14.0 mm X 14.0mm
0.8mm
TQFP
10.0mm x 10.0mm
0.5mm
SPEED (IN MH Z)
Freescale Semiconductor, Inc...
10/16/20 MHz
VOLTAGE
SUFFIX
3.3V or 5.0V
FU
CFU
PB
CPB
TEMPERATURE
RANGE
0C to +70C
-40C to +85C
0C to +70C
-40C to +85C
MC68HC000 Ordering Information
PACKAGE
BODY SIZE
LEAD SPACING
SPEED (IN MHZ)
VOLTAGE
SUFFIX
DIP
PLCC
81.91mm X 20.57mm
2.54mm
8, 10, 12, 16
8, 10, 12, 16, 20
8, 10, 12, 16
5.0V
P
FN
CFN
25.57mm X 25.27mm
1.27mm
TEMPERATURE
RANGE
0C to +70C
0C to +70C
-40C to +85C
MC68EC000 Ordering Information
PACKAGE
BODY SIZE
LEAD SPACING
SPEED (IN MHZ)
VOLTAGE
SUFFIX
PLCC
PQFP
25.57mm X 25.27mm
14.1mm X 14.1mm
1.27mm
0.8mm
8, 10,12, 16, 20
8, 10,12, 16, 20
5.0V
FN
FU
TEMPERATURE
RANGE
0C to +70C
DOCUMENTATION
Add to Section 11.
The documents listed in the following table contain detailed information that pertain to the MC68SEC000
processor. You can obtain these documents from the Literature Distribution Centers listed on the last page
of this document.
MC68SEC000 Documentation
MC68SEC000 DOCUMENTATION
M68000 Family
Programmer’s Reference Manual
M68000 User’s Manual
High Performance Embedded Systems
Source Catalog‘‘
MC68EC000 Product Brief
MC68SEC000 Product Brief
MOTOROLA
DOCUMENT NUMBER
M68000PM/AD
M68000UM/AD
BR729/D
MC68EC000/D
MC68SEC000/D
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate,
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