Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68F375
REFERENCE MANUAL
Revised 25 June 2003
Copyright 2003 MOTOROLA; All Rights Reserved
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68F375
REFERENCE MANUAL
Revised 25 June 2003
Copyright 2003 MOTOROLA; All Rights Reserved
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Paragraph
Number
TABLE OF CONTENTS
Page
Number
PREFACE
Section 1
OVERVIEW DESCRIPTION
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 MC68F375 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.3 Module Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.1 Central Processing Unit Module – CPU32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
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1.3.2 Single Chip Integration Module – SCIM2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.3 Queued Analog to Digital Converter Module – QADC64 . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.4 Analog Multiplexer – AMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.5 Queued Serial Multi-Channel Communications Module – QSMCM . . . . . . . . . . . . . . . . . 1-4
1.3.6 TouCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.7 Enhanced Time Processing Unit – TPU3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.8 DPTRAM TPU Emulation RAM Module – DPTRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.9 1T Flash Electrically Erasable Read Only Memory – CMFI . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.10 Static RAM – SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.11 Mask Programmable Read Only Memory – ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.12 Configurable Timer Module 9 – CTM9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 MC68F375 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6 MC68F375 Pin Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.7 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.7.1 Address Bus Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Section 2
SIGNAL DESCRIPTIONS
2.1 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1 Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Section 3
CENTRAL PROCESSOR UNIT
3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 CPU32 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2 Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.3 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.4.1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.4.2 Alternate Function Code Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
iii
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
3.2.5 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.3 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.6 Processing States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.7 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.8 Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.8.1 M68000 Family Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.8.2 Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.8.2.1 Low-Power Stop (LPSTOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
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3.8.2.2 Table Lookup and Interpolate (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.8.2.3 Loop Mode Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.9 Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.9.1 Exception Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.9.2 Types of Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.9.3 Exception Processing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.10 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.10.1 M68000 Family Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.10.2 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.10.3 Enabling BDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.10.4 BDM Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.10.4.1 External BKPT Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.10.4.2 BGND Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.10.4.3 Double Bus Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.10.4.4 Peripheral Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.10.5 Entering BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.10.6 BDM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.10.7 Background Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.10.7.1 Fault Address Register (FAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.10.7.2 Return Program Counter (RPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.10.7.3 Current Instruction Program Counter (PCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.10.8 Returning from BDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.10.9 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.10.10 Recommended BDM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.10.11 Deterministic Opcode Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.10.12 On-Chip Breakpoint Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Section 4
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1 SCIM Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.2 Module Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
iv
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
4.2.3 Interrupt Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.4 Noise Reduction in Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.5 Show Internal Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.6 FREEZE Assertion Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3.1 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.2 Clock Synthesizer Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.3 Slow Reference Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.3.4 Fast Reference Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.3.5 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
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4.3.6 Clock Synthesizer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.3.6.1 Frequency control Bits (X,W,Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.6.2 E Clock Divide Rate (EDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.6.3 Loss of Clock Oscillator Disable (LOSCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.6.4 Limp Mode (SLIMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.6.5 Synthesizer Lock (SLOCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.6.6 Reset Enable (RSTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.6.7 Low Power Stop Mode SCIM2 Clock (STSCIM) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.6.8 Low Power Stop Mode External Clock (STEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.7 Clock Circuits Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.7.1 Synthesizer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.7.2 Phase Comparator and Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.3.7.3 Lock Detect Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.7.4 Clock Control Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.7.5 Loss Of Clock Detect Circuit (LOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.8 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.8.1 POR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.8.2 External Clock Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.8.3 PLL Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.8.4 RSTEN Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.8.5 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4.3.8.6 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.3.8.7 Loss of Reference Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.4 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4.4.1 System Protection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
4.4.2 Reset Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
4.4.3 Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
4.4.4 Halt Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
4.4.5 Spurious Interrupt Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4.4.6 Software Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4.4.6.1 Software Watchdog Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.4.7 Periodic Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4.4.8 Interrupt Priority and Vectoring for the Periodic Interrupt Timer. . . . . . . . . . . . . . . . . . . 4-29
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
v
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
4.4.9 Low Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
4.4.9.1 Periodic Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
4.4.9.2 Periodic Interrupt Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4.5 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4.5.1 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.5.1.1 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.5.1.2 Address Strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.5.1.3 Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4.5.1.4 Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
4.5.1.5 Read/Write Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Freescale Semiconductor, Inc...
4.5.1.6 Size Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
4.5.1.7 Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
4.5.1.8 Data Size Acknowledge Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
4.5.1.9 Bus Error Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
4.5.1.10 Halt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
4.5.1.11 Autovector Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4.5.2 Dynamic Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4.5.3 Operand Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4.5.4 Misaligned Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4.5.5 Operand Transfer Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4.6 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
4.6.1 Synchronization to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
4.6.2 Regular Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
4.6.2.1 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
4.6.2.2 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
4.6.3 Fast Termination Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
4.6.4 CPU Space Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42
4.6.4.1 Breakpoint Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
4.6.4.2 LPSTOP Broadcast Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
4.6.5 Bus Exception Control Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
4.6.5.1 Bus Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4.6.5.2 Double Bus Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
4.6.5.3 Retry Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
4.6.5.4 Halt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
4.6.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
4.6.6.1 Show Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
4.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
4.7.1 SCIM2E Reset Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
4.7.1.1 SCIM2E Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
4.7.2 Reset Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
4.7.3 Reset Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
4.7.4 Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
4.7.5 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
vi
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
4.7.6 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
4.7.7 Pin State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
4.7.7.1 Reset States of SCIM2E Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58
4.7.7.2 Reset States of Pins Assigned to Other MCU Modules . . . . . . . . . . . . . . . . . . . . . 4-59
4.7.8 Operating Configuration Out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
4.7.8.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
4.7.8.2 Data Bus Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62
4.7.8.3 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64
4.7.8.4 Fully (16-bit) Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66
4.7.8.5 Breakpoint Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68
Freescale Semiconductor, Inc...
4.7.8.6 Emulation Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69
4.7.9 Use of the Three-State Control Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69
4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
4.8.1 Interrupt Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
4.8.2 Interrupt Priority and Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
4.8.3 Interrupt Acknowledge and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71
4.8.4 Interrupt Processing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
4.9 Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
4.9.1 Chip-Select Pin Assignment Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
4.9.1.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
4.9.2 Chip-Select Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
4.9.3 Chip-Select Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
4.9.4 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
4.9.4.1 Using Chip-Select Signals for Interrupt Acknowledge Cycle Termination . . . . . . . 4-84
4.9.4.2 Chip-Select Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
4.10 General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
4.10.1 Ports A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
4.10.2 Port A and B Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
4.10.3 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
4.10.3.1 Port E Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
4.10.3.2 Port E Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
4.10.3.3 Port E Pin Assignment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
4.10.4 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-90
4.10.4.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-91
4.10.4.2 Port F Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
4.10.4.3 Port F Pin Assignment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
4.10.4.4 Port F Edge-Detect Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.10.4.5 Port F Edge-Detect Interrupt Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.10.4.6 Port F Edge-Detect Interrupt Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.10.5 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.10.5.1 Port G and H Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
4.10.5.2 Port G and H Data Direction Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
4.10.6 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
vii
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
Section 5
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 QADC64 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3.1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.1.1 Port A Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.1.2 Port A Digital Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.2.1 Port B Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Freescale Semiconductor, Inc...
5.3.2.2 Port B Digital Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.3 External Trigger Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.4 Multiplexed Address Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.5 Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.7 Dedicated Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.8 External Digital Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.9 Digital Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.4 QADC64 Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5.1 Low-Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.5.2 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.5.3 Supervisor/Unrestricted Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.6 General-Purpose I/O Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.6.1 Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.6.2 Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.7 External Multiplexing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.8 Analog Input Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.9.1 Conversion Cycle Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.9.1.1 Amplifier Bypass Mode Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.9.2 Front-End Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.9.3 Digital-to-Analog Converter Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.9.4 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.9.5 Successive Approximation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.10 Digital Control Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.10.1 Queue Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.10.2 Queue Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.10.3.1 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.10.3.2 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.10.3.3 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.10.3.4 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
viii
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
5.10.4 QADC64 Clock (QCLK) Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.10.5 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.11.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.11.1.1 Polled and Interrupt-Driven Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.11.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.11.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.11.4 Interrupt Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.11.5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.12 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
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5.12.1 QADC64 Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5.12.2 QADC64 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5.12.3 Port A/B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5.12.4 Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.12.5 QADC64 Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.12.6 QADC64 Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5.12.7 QADC64 Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
5.12.8 QADC64 Status Register 0 (QASR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
5.12.9 QADC64 Status Register 1 (QASR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.12.10 Conversion Command Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.12.11 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
5.13 Analog Multiplexer Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.13.1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.13.1.1 External Pins (Connected to Pads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.13.1.2 Internal Pins (Connected to QADC64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.13.2 Mixed AMUX/External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5.13.3 Pin Connection and Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
Section 6
QUEUED SERIAL MULTI-CHANNEL MODULE
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.5 QSMCM Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.5.1 Low-Power Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.5.2 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.5.3 Access Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.5.4 QSMCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.5.5 QSMCM Configuration Register (QSMCMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.5.6 QSMCM Test Register (QTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.5.7 QSMCM Interrupt Level Registers (QILR, QIVR, QSPI_IL) . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.6 QSMCM Pin Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Page
Number
Paragraph
Number
6.6.1 Port QS Data Register (PORTQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.6.2 PORTQS Pin Assignment Register (PQSPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.6.3 PORTQS Data Direction Register (DDRQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.7 Queued Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.7.1 QSPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.7.1.1 QSPI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.7.1.2 QSPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.7.1.3 QSPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.7.1.4 QSPI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.7.1.5 QSPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
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6.7.2 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.7.2.1 Receive RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.7.2.2 Transmit RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.7.2.3 Command RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.7.3 QSPI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.7.4 QSPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.7.4.1 Enabling, Disabling, and Halting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.7.4.2 QSPI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.7.4.3 QSPI Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.7.5 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
6.7.5.1 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.7.5.2 Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.7.5.3 Delay Before Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.7.5.4 Delay After Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
6.7.5.5 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
6.7.5.6 Peripheral Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
6.7.5.7 Master Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.7.6 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.7.6.1 Description of Slave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
6.7.7 Slave Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
6.7.8 Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
6.8 Serial Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
6.8.1 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
6.8.2 SCI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
6.8.3 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
6.8.4 SCI Status Register (SCxSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
6.8.5 SCI Data Register (SCxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
6.8.6 SCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6.8.7 SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6.8.7.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6.8.7.2 Serial Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
6.8.7.3 Baud Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
6.8.7.4 Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
6.8.7.5 Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
6.8.7.6 Receiver Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
6.8.7.7 Idle-Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
6.8.7.8 Receiver Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56
6.8.7.9 Internal Loop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.9 SCI Queue Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.9.1 Queue Operation of SCI1 for Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.9.2 Queued SCI1 Status and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.9.2.1 QSCI1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.9.2.2 QSCI1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58
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6.9.3 QSCI1 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59
6.9.4 QSCI1 Additional Transmit Operation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60
6.9.5 QSCI1 Transmit Flow Chart Implementing the Queue . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
6.9.6 Example QSCI1 Transmit for 17 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64
6.9.7 Example SCI Transmit for 25 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65
6.9.8 QSCI1 Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
6.9.9 QSCI1 Additional Receive Operation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
6.9.10 QSCI1 Receive Flow Chart Implementing The Queue . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
6.9.11 QSCI1 Receive Queue Software Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
6.9.12 Example QSCI1 Receive Operation of 17 Data Frames . . . . . . . . . . . . . . . . . . . . . . . 6-71
Section 7
CAN 2.0B CONTROLLER MODULE
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.4 TouCAN Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.4.1 TX/RX Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.4.1.1 Common Fields for Extended and Standard Format Frames. . . . . . . . . . . . . . . . . . 7-4
7.4.1.2 Fields for Extended Format Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.4.1.3 Fields for Standard Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.4.1.4 Serial Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.4.1.5 Message Buffer Activation/Deactivation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4.1.6 Message Buffer Lock/Release/Busy Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4.2 Receive Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4.3 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.4.3.1 Configuring the TouCAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.4.4 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.4.5 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5 TouCAN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5.1 TouCAN Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5.2 TouCAN Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5.3 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
xi
Freescale Semiconductor, Inc.
Page
Number
Paragraph
Number
7.5.3.1 Transmit Message Buffer Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.5.3.2 Reception of Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.5.4 Receive Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.5.4.1 Receive Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.5.4.2 Locking and Releasing Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
7.5.5 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.6 Overload Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.6 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.6.1 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.6.2 Low-Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
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7.6.3 Auto-Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.8 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.8.1 TouCAN Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.8.2 TouCAN Interrupt Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
7.8.3 Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.8.4 Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
7.8.5 Prescaler Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.8.6 Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
7.8.7 Free Running Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
7.8.8 Receive Global Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
7.8.9 Receive Buffer 14 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
7.8.10 Receive Buffer 15 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
7.8.11 Error and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
7.8.12 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
7.8.13 Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
7.8.14 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Section 8
TIME PROCESSOR UNIT 3
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 TPU3 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.1 Time Bases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.2 Timer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.3 Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.4 Microengine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.2.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2.6 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3 TPU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3.1 Event Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3.2 Channel Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3.3 Interchannel Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.4 Programmable Channel Service Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
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REFERENCE MANUAL
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For More Information On This Product,
Go to: www.freescale.com
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Number
Paragraph
Number
8.3.5 Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.6 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3.7 TPU3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.3.8 Prescaler Control for TCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.3.9 Prescaler Control for TCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.4.1 TPU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.4.2 TPU3 Test Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.4.3 Development Support Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.4.4 Development Support Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
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8.4.5 TPU3 Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.4.6 Channel Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.4.7 Channel Function Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.4.8 Host Sequence Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.4.9 Host Service Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.4.10 Channel Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.4.11 Channel Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4.12 Link Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4.13 Service Grant Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4.14 Decoded Channel Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4.15 TPU3 Module Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.4.16 TPU Module Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.4.17 TPU3 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.4.18 TPU3 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.5 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Section 9
DUAL-PORT TPU RAM (DPTRAM)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.3 DPTRAM Configuration and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.4.1 DPTRAM Module Configuration Register (DPTMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.4.2 DPTRAM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.4.3 Ram Base Address Register (DPTBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.4.4 MISR High (MISRH) and MISR Low (MISRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.4.5 MISC Counter (MISCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.2 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.5.4 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.5.5 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Page
Number
Paragraph
Number
9.5.6 TPU3 Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.6 Multiple Input Signature Calculator (MISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Section 10
CDR MoneT FLASH FOR THE IMB3 (CMFI)
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.2 Features of the CMFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.1.3 Glossary of terms used in the CMFI EEPROM Specification . . . . . . . . . . . . . . . . . . . . 10-4
10.2 CMFI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.2.1 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
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10.3 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4 CMFI EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.4.1 CMFI EEPROM Module Control Block Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.2 Reserved Register Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3 CMFI EEPROM Configuration Register (CMFIMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.4 CMFI EEPROM Test Register (CMFITST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.4.5 CMFI Base Address Registers (CMFIBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.4.6 High Voltage Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4.7 CMFIBS CMFI Bootstrap Words [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.4.8 Pulse Width Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.4.9 A Technique to Determine SCLKR, CLKPE, and CLKPM . . . . . . . . . . . . . . . . . . . . . 10-21
10.5 CMFI EEPROM Array Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.5.1 Read Burst Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.5.2 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.6.1 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.6.2 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.6.3 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.6.4 Register Read and Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.6.5 Array Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.6.6 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.6.6.1 Program Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10.6.6.2 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.6.6.3 Programming Shadow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.6.6.4 Over Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.6.7 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.6.7.1 Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.6.7.2 Erase Margin Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.6.7.3 Erasing Shadow Information Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.6.8 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10.6.8.1 Low Power Stop Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10.6.8.2 STOP Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Page
Number
Paragraph
Number
10.6.9 Background Debug Mode or Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
Section 11
STATIC RANDOM ACCESS MEMORY (SRAM)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.1 SRAM Control Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2.2 SRAM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.2.2.1 SRAM Array Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 SRAM Module Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3.1 Module Configuration Register (RAMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
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11.3.2 Array Base Address Registers (RAMBAH, RAMBAL) . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.4.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.1.1 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.2 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.2.1 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.3 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.4 STOP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.4.5 Overlay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Section 12
MASK ROM MODULE
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Mask Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.3 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.1 ROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.1.1 ROM Module Control Block Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.2 ROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.3.2.1 ROM Array Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4 ROM Module Control and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4.1 Module Configuration Register (ROMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4.2 ROM Base Address Register (ROMBAH, ROMBAL) . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.4.3 ROM Signature High (SIGHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.4.4 ROM Signature Low (SIGLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.5 Bootstrap Information Words (ROMBS0–ROMBS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.1 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.6.2 Bootstrap Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.6.3 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.6.4 Read/Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.6.5 Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.6.6 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.6.7 FREEZE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Page
Number
Paragraph
Number
Section 13
CONFIGURABLE TIMER MODULE (CTM9)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.1 CTM9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1.2 CTM9 Pins and Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2 Free Running Counter Submodule (FCSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.2.1 The FCSM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.2.2 FCSM Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.2.3 FCSM External Event Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.2.4 The FCSM Time Base Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
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13.2.5 FCSM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.2.6 Freeze Action on the FCSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.2.7 FCSM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.2.7.1 FCSMSIC — FCSM Status/Interrupt/Control Register . . . . . . . . . . . . . . . . . . . . . 13-7
13.2.7.2 FCSMCNT — FCSM Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.3 Modulus Counter Submodule (MCSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.3.1 The MCSM Modulus Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.3.2 The MCSM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.3.2.1 Loading the MCSM Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.3.2.2 Using the MCSM as a Free-Running Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.3.3 MCSM Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.3.4 MCSM External Event Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.3.5 The MCSM Time Base Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.3.6 MCSM interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.3.7 Freeze Action on the MCSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.3.8 MCSM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.3.9 MCSMSIC — MCSM Status/Interrupt/Control Register . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.3.10 MCSMCNT — MCSM Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.3.11 MCSMML — MCSM Modulus Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4 Single-Action Submodule (SASM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4.1 SASM Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.1.1 Clearing and Using the FLAG Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.1.2 Input Capture (IC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.4.1.3 Output Compare (OC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.4.1.4 Output Compare and Toggle (OCT) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.4.1.5 Output Port (OP) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.4.2 SASM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.3 Freeze Action on the SASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.4 SASM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.4.1 SICA — SASM Status/Interrupt Control Register A . . . . . . . . . . . . . . . . . . . . . . 13-20
13.4.4.2 SDATA — SASM Data Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.4.4.3 SICB — SASM Status/Interrupt Control Register B . . . . . . . . . . . . . . . . . . . . . . 13-22
13.4.4.4 SDATB — SASM Data Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Number
Paragraph
Number
13.5 Double-Action Submodule (DASM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
13.5.1 32-Bit Coherent Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.5.2 DASM Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.5.2.1 Disable (DIS) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
13.5.2.2 Input Pulse Width Measurement (IPWM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
13.5.2.3 Input Period Measurement (IPM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27
13.5.2.4 Input Capture (IC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.5.2.5 Output Compare (OCB and OCAB) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
13.5.2.6 Output Pulse Width Modulation (OPWM) Mode. . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.5.3 DASM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
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13.5.4 Freeze Action on the DASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.5.5 DASM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35
13.5.5.1 DASMSIC — DASM Status/Interrupt Control Register. . . . . . . . . . . . . . . . . . . . 13-35
13.5.5.2 DASMA — DASM Data Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37
13.5.5.3 DASMB — DASM Data Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38
13.6 Pulse Width Modulation Submodule (PWMSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38
13.6.1 Output Flip-Flop and Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39
13.7 Time Base Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40
13.7.1 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40
13.7.2 The PWMSM Counter (PWMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40
13.7.3 PWMSM Period Registers and Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40
13.7.4 PWMSM Pulse Width Registers and Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41
13.7.5 0% and 100% ‘Pulses’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41
13.7.6 PWMSM Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42
13.7.7 PWMSM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42
13.7.8 Freeze Action on the PWMSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42
13.7.9 PWM frequency, Pulse Width and Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42
13.7.10 PWM Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43
13.7.11 PWM Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-44
13.7.12 PWM Period and Pulse Width Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-44
13.7.13 PWMSM Register Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-44
13.7.13.1 PWMSIC — Status, Interrupt and Control Register . . . . . . . . . . . . . . . . . . . . . 13-45
13.7.13.2 PWMA — PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-48
13.7.13.3 PWMB — PWM Pulse Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-49
13.7.13.4 PWMC — PWM Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-49
13.8 Bus Interface Unit Submodule (BIUSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50
13.8.1 Freeze Action on the BIUSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50
13.8.2 LPSTOP Action on the BIUSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50
13.8.3 STOP and WAIT Action on the BIUSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50
13.8.4 BIUSM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50
13.8.4.1 BIUMCR — BIUSM Module Configuration Register. . . . . . . . . . . . . . . . . . . . . . 13-51
13.8.4.2 BIUTBR — BIUSM Time Base Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52
13.9 Counter Prescaler Submodule (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Page
Number
Paragraph
Number
13.9.1 Freeze Action on the CPSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-53
13.9.2 CPSM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-53
13.9.2.1 CPCR — CPSM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-54
13.9.3 Clock Sources for the Counter Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-54
13.10 CTM9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-55
13.11 CTM9 Function Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-55
13.11.1 CTM9 Single Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-55
13.11.2 CTM9 Input Double Edge Pulse Width Measurement . . . . . . . . . . . . . . . . . . . . . . . 13-56
13.11.3 CTM9 Input Double Edge Period Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-57
13.11.4 CTM9 Single Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-58
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13.11.5 CTM9 Double Edge Single Output Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . 13-59
13.11.6 CTM9 Output Pulse Width Modulation With DASM . . . . . . . . . . . . . . . . . . . . . . . . . 13-60
13.11.7 CTM9 Input Pulse Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-61
Appendix A
INTERNAL MEMORY MAP
Appendix B
REGISTER GENERAL INDEX
Appendix C
REGISTER DIAGRAM INDEX
Appendix D
TPU ROM FUNCTIONS
D.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.2 Programmable Time Accumulator (PTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
D.3 Queued Output Match TPU Function (QOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5
D.4 Table Stepper Motor (TSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
D.5 Frequency Measurement (FQM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
D.6 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12
D.7 New Input Capture/Transition Counter (NITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15
D.8 Multiphase Motor Commutation (COMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17
D.9 Hall Effect Decode (HALLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
D.10 Multichannel Pulse-Width Modulation (MCPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-21
D.11 Fast Quadrature Decode TPU Function (FQD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-28
D.12 Period/Pulse-Width Accumulator (PPWA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-31
D.13 Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-33
D.14 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35
D.15 Discrete Input/Output (DIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-37
D.16 Synchronized Pulse-Width Modulation (SPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-39
D.17 Serial Input/Output Port (SIOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-42
D.17.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-43
D.17.1.1 CHAN_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
D.17.1.2 BIT_D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
D.17.1.3 HALF_PERIOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
D.17.1.4 BIT_COUNT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
D.17.1.5 XFER_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
D.17.1.6 SIOP_DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
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REFERENCE MANUAL
TABLE OF CONTENTS
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Page
Number
Paragraph
Number
D.17.2 Host CPU Initialization of the SIOP Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3 SIOP Function Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3.1 XFER_SIZE Greater than 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3.2 Data Positioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.17.3.3 Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-45
D-45
D-46
D-46
D-46
Freescale Semiconductor, Inc...
Appendix E
ELECTRICAL CHARACTERISTICS
E.1
E.2
E.3
E.4
E.5
E.6
E.7
E.8
E.9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
QSPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-20
TPU3 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-23
QADC64 and AMUX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-24
CTM9 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-29
E.9.1 5 V, 16.78 MHz Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-29
E.9.2 5 V, 25.0 MHz Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-29
E.10 TouCAN Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-32
E.11 CMFI FLASH Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-33
E.11.1 EPEB0 Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-34
E.11.2 FLASH Program/Erase Voltage Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-34
E.12 ROM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-36
INDEX
Online publishing by JABIS, http://www.jabis.com
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
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Number
MC68F375
REFERENCE MANUAL
TABLE OF CONTENTS
Rev. 25 June 03
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MOTOROLA
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Freescale Semiconductor, Inc...
Figure
Number
LIST OF FIGURES
Page
Number
1-1
1-2
MC68F375 Block Diagram ............................................................................. 1-7
MC68F375 Address Map .............................................................................. 1-10
2-1
2-2
MC68F375 Pad Map ...................................................................................... 2-8
MC68F375 Ball Map ....................................................................................... 2-9
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
CPU32 Block Diagram .................................................................................... 3-2
User Programming Model ............................................................................... 3-3
Supervisor Programming Model Supplement ................................................. 3-4
Data Organization in Data Registers .............................................................. 3-5
Address Organization in Address Registers ................................................... 3-6
Memory Operand Addressing ......................................................................... 3-8
Loop Mode Instruction Sequence ................................................................. 3-16
Common In-Circuit Emulator Diagram .......................................................... 3-20
Bus State Analyzer Configuration ................................................................. 3-20
Debug Serial I/O Block Diagram ................................................................... 3-25
BDM Serial Data Word ................................................................................. 3-26
BDM Connector Pinout ................................................................................. 3-26
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
SCIM2E Block Diagram .................................................................................. 4-2
Slow Reference Mode .................................................................................... 4-9
Fast Reference Mode ................................................................................... 4-12
External Clock Mode .................................................................................... 4-14
Crystal Oscillator and External Capacitor Configuration .............................. 4-17
LPSTOP Flowchart ....................................................................................... 4-22
System Protection ........................................................................................ 4-24
Periodic Interrupt Timer and Software Watchdog Timer .............................. 4-28
MCU Basic System ....................................................................................... 4-33
Operand Byte Order ..................................................................................... 4-37
Word Read Cycle Flowchart ......................................................................... 4-40
Write Cycle Flowchart ................................................................................... 4-41
CPU Space Address Encoding ..................................................................... 4-43
Breakpoint Operation Flowchart ................................................................... 4-45
LPSTOP Interrupt Mask Encoding on DATA[15:0] ....................................... 4-46
Bus Arbitration Flowchart for Single Request ............................................... 4-51
SCIM2 Reset Control Flow ........................................................................... 4-54
Power-On Reset ........................................................................................... 4-58
Preferred Circuit for Data Bus Mode Select Conditioning ............................ 4-63
Alternate Circuit for Data Bus Mode Select Conditioning ............................. 4-64
Basic MCU System ....................................................................................... 4-74
Chip-Select Circuit Block Diagram ............................................................... 4-75
CPU Space Encoding for Interrupt Acknowledge ......................................... 4-85
Port F Block Diagram ................................................................................... 4-91
MC68F375
REFERENCE MANUAL
LIST OF FIGURES
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Number
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
QADC64 Block Diagram ................................................................................. 5-1
QADC64 Input and Output Signals ................................................................. 5-3
Example of Full External Multiplexing ........................................................... 5-10
QADC64 Module Block Diagram .................................................................. 5-12
Conversion Timing ........................................................................................ 5-13
Bypass Mode Conversion Timing ................................................................. 5-13
QADC64 Queue Operation with Pause ........................................................ 5-16
QADC64 Clock Subsystem Functions .......................................................... 5-26
QADC64 Clock Programmability Examples ................................................. 5-28
QADC64 Interrupt Flow Diagram .................................................................. 5-30
QADC64 Interrupt Vector Format ................................................................. 5-33
QADC64 Conversion Queue Operation ....................................................... 5-46
AMUX/QADC64 Configured for Mixed Multiplexing ..................................... 5-55
Analog Multiplexer Submodule Charging Current Illustration ....................... 5-57
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
QSMCM Block Diagram ................................................................................. 6-2
QSPI Block Diagram ..................................................................................... 6-14
QSPI RAM .................................................................................................... 6-22
Flowchart of QSPI Initialization Operation .................................................... 6-27
Flowchart of QSPI Master Operation (Part 1) ............................................... 6-28
Flowchart of QSPI Master Operation (Part 2) ............................................... 6-29
Flowchart of QSPI Master Operation (Part 3) ............................................... 6-30
Flowchart of QSPI Slave Operation (Part 1) ................................................. 6-31
Flowchart of QSPI Slave Operation (Part 2) ................................................. 6-32
SCI Transmitter Block Diagram .................................................................... 6-42
SCI Receiver Block Diagram ........................................................................ 6-43
Queue Transmitter Block Enhancements ..................................................... 6-60
Queue Transmit Flow ................................................................................... 6-62
Queue Transmit Software Flow .................................................................... 6-63
Queue Transmit Example for 17 Data Bytes ................................................ 6-64
Queue Transmit Example for 25 Data Frames ............................................. 6-65
Queue Receiver Block Enhancements ......................................................... 6-66
Queue Receive Flow .................................................................................... 6-69
Queue Receive Software Flow ..................................................................... 6-70
Queue Receive Example for 17 Data Bytes ................................................. 6-71
7-1
7-2
7-3
7-4
7-5
7-6
TouCAN Block Diagram ................................................................................. 7-1
Typical CAN Network ..................................................................................... 7-3
Extended ID Message Buffer Structure .......................................................... 7-4
Standard ID Message Buffer Structure ........................................................... 7-4
TouCAN Interrupt Vector Generation ........................................................... 7-19
TouCAN Message Buffer Memory Map ........................................................ 7-23
8-1
8-2
8-3
TPU3 Block Diagram ...................................................................................... 8-1
TCR1 Prescaler Control ................................................................................. 8-7
TCR2 Prescaler Control ................................................................................. 8-8
MC68F375
REFERENCE MANUAL
LIST OF FIGURES
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Page
Number
Freescale Semiconductor, Inc...
Figure
Number
9-1
DPTRAM Configuration .................................................................................. 9-2
10-1
10-3
10-2
10-4
10-5
10-6
10-7
Block Diagram for a CMFI EEPROM in the 256-Kbyte Configuration. ......... 10-2
Shadow Information .................................................................................... 10-12
10-12
Pulse Status Timing .................................................................................... 10-19
Master Reset Configuration Timing ............................................................ 10-24
Program State Diagram .............................................................................. 10-28
Erase State Diagram .................................................................................. 10-33
11-1
SRAM Module Configuration ........................................................................ 11-2
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
Configurable Timer Module, CTM9 Block Diagram ...................................... 13-2
FCSM Block Diagram ................................................................................... 13-5
MCSM Block Diagram .................................................................................. 13-9
SASM Block Diagram ................................................................................. 13-15
SASM Block Diagram (Channel A) ............................................................. 13-16
DASM Block Diagram ................................................................................. 13-24
Input Pulse Width Measurement Example ................................................. 13-27
Input Period Measurement Example .......................................................... 13-28
DASM Input Capture Example ................................................................... 13-29
Single Shot Output Pulse Example ............................................................ 13-31
Single Shot Output Transition Example ...................................................... 13-31
DASM Output Pulse Width Modulation Example ........................................ 13-33
Pulse Width Modulation Submodule Block Diagram .................................. 13-39
CPSM Block Diagram ................................................................................. 13-53
CTM9 Example — Single Edge Input Capture ........................................... 13-56
CTM9 Example — Double Capture Pulse Width Measurement ................. 13-57
CTM9 Example — Double Capture Period Measurement .......................... 13-58
CTM9 Example — Single Edge Output Compare ...................................... 13-59
CTM9 Example — Double Edge Output Compare ..................................... 13-60
CTM9 Example — Pulse Width Modulation Output .................................... 13-61
D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-11
D-12
D-13
TPU3 Memory Map ........................................................................................D-1
PTA Parameters .............................................................................................D-4
QOM Parameters ...........................................................................................D-6
TSM Parameters — Master Mode ..................................................................D-8
TSM Parameters — Slave Mode ....................................................................D-9
FQM Parameters ..........................................................................................D-11
UART Transmitter Parameters .....................................................................D-13
UART Receiver Parameters .........................................................................D-14
NITC Parameters .........................................................................................D-16
COMM Parameters, Part 1 of 2 ....................................................................D-18
COMM Parameters, Part 2 of 2 ....................................................................D-19
HALLD Parameters ......................................................................................D-20
MCPWM Parameters — Master Mode .........................................................D-22
MC68F375
REFERENCE MANUAL
LIST OF FIGURES
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D-14
D-15
D-16
D-17
D-18
D-19
D-20
D-21
D-22
D-23
D-24
D-25
D-26
D-27
D-28
D-29
MCPWM Parameters — Slave Edge-Aligned Mode ....................................D-23
MCPWM Parameters — Slave Ch A Non-Inverted Center-Aligned Mode ...D-24
MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode ...D-25
MCPWM Parameters — Slave Ch A Inverted Center-Aligned Mode ...........D-26
MCPWM Parameters — Slave Ch B Inverted Center-Aligned Mode ...........D-27
FQD Parameters — Primary Channel ..........................................................D-29
FQD Parameters — Secondary Channel .....................................................D-30
PPWA Parameters .......................................................................................D-32
OC Parameters ............................................................................................D-34
PWM Parameters .........................................................................................D-36
DIO Parameters ...........................................................................................D-38
SPWM Parameters, Part 1 of 2 ....................................................................D-40
SPWM Parameters, Part 2 of 2 ....................................................................D-41
Two Possible SIOP Configurations ..............................................................D-42
SIOP Parameters .........................................................................................D-43
SIOP Function Data Transition Example ......................................................D-47
E-1
E-2
E-3
E-4
E-5
E-6
E-7
E-8
E-9
E-10
E-11
E-12
E-13
E-14
E-15
E-16
E-17
E-18
E-19
E-20
E-21
E-22
E-23
CLKOUT Output Timing Diagram ................................................................... E-9
External Clock Input Timing Diagram ............................................................. E-9
ECLK Output Timing Diagram ........................................................................ E-9
Read Cycle Timing Diagram ........................................................................ E-10
Write Cycle Timing Diagram ......................................................................... E-11
Fast Termination Read Cycle Timing Diagram ............................................ E-12
Fast Termination Write Cycle Timing Diagram ............................................. E-13
Bus Arbitration Timing Diagram — Active Bus Case ................................... E-14
Bus Arbitration Timing Diagram — Idle Bus Case .......................................E-15
Show Cycle Timing Diagram ........................................................................ E-15
Chip-Select Timing Diagram ........................................................................ E-16
Reset and Mode Select Timing Diagram ...................................................... E-16
Background Debugging Mode Timing — Serial Communication ................. E-17
Background Debugging Mode Timing — Freeze Assertion ......................... E-17
ECLK Timing Diagram .................................................................................. E-19
QSPI Timing — Master, CPHA = 0 .............................................................. E-21
QSPI Timing — Master, CPHA = 1 .............................................................. E-21
QSPI Timing — Slave, CPHA = 0 ................................................................ E-22
QSPI Timing — Slave, CPHA = 1 ................................................................ E-22
TPU Timing Diagram .................................................................................... E-23
EPEB0 Pin Timing ........................................................................................ E-34
VPP and VDD Power Sequencing ................................................................. E-35
A Recommended External VPP Pin Conditioning Circuit ..............................E-36
MC68F375
REFERENCE MANUAL
LIST OF FIGURES
Rev. 25 June 03
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Table
Number
LIST OF TABLES
Page
Number
Freescale Semiconductor, Inc...
1-1 MC68F375 Pin Usage .......................................................................................... 1-8
2-1
2-2
2-3
2-4
2-5
Pin Characteristics................................................................................................. 2-1
Power Connections................................................................................................ 2-3
Output Driver Types............................................................................................... 2-4
Signal Characteristics ............................................................................................ 2-4
Signal Functions .................................................................................................... 2-6
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Unimplemented MC68020 Instructions................................................................ 3-10
Instruction Set Summary ..................................................................................... 3-11
Exception Vector Assignments ............................................................................ 3-17
BDM Source Summary ........................................................................................ 3-21
Polling the BDM Entry Source ............................................................................. 3-22
Background Mode Command Summary.............................................................. 3-23
CPU Generated Message Encoding.................................................................... 3-26
4-1 SCIMMCR Bit Descriptions.................................................................................... 4-3
4-2 SCIMMCR Noise Control Bits................................................................................ 4-4
4-3 Show Cycle Enable Bits......................................................................................... 4-5
4-4 Effects of FREEZE Assertion................................................................................. 4-5
4-5 System Clock Sources........................................................................................... 4-6
4-6 CLKOUT Frequency: Slow Reference; 32.768 KHz Reference .......................... 4-10
4-7 CLKOUT In Fast Reference Mode with 4.0 MHz Reference ............................... 4-13
4-8 Port Reset Condition............................................................................................ 4-20
4-9 SYPCR Bit Descriptions ...................................................................................... 4-24
4-10 Bus Monitor Period ............................................................................................ 4-25
4-11 SWP Reset States ............................................................................................. 4-26
4-12 Software Watchdog Divide Ratio ....................................................................... 4-27
4-13 PTP Reset States .............................................................................................. 4-29
4-14 Periodic Interrupt Priority ................................................................................... 4-30
4-15 PICR Bit Descriptions ........................................................................................ 4-31
4-16 PITR Bit Descriptions......................................................................................... 4-31
4-17 Size Signal Encoding......................................................................................... 4-34
4-18 Address Space Encoding .................................................................................. 4-35
4-19 Effect of DSACK Signals ................................................................................... 4-36
4-20 Operand Alignment............................................................................................ 4-38
4-21 DSACK, BERR, and HALT Assertion Results ................................................... 4-47
4-22 Reset Source Summary..................................................................................... 4-55
4-23 RSR Bit Descriptions ......................................................................................... 4-56
4-24 SCIM2E Pin States During Reset ...................................................................... 4-59
4-25 Pins Associated with Basic Configuration Options ............................................ 4-60
4-26 Mode Configuration During Reset ..................................................................... 4-61
4-27 Fully (16-bit) Expanded Mode Reset Configuration........................................... 4-66
MC68F375
REFERENCE MANUAL
LIST OF TABLES
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Table
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4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
Reset Pin Function of CS[10:6] ......................................................................... 4-67
Reset Configuration for MC68F375 Memory Modules ...................................... 4-67
Partially (8-bit) Expanded Mode Reset Configuration........................................ 4-68
CSPAR0 Pin Assignments................................................................................. 4-76
CSPAR1 Pin Assignments................................................................................. 4-77
Reset Pin Function of CS[10:6] ......................................................................... 4-77
Pin Assignment Field Encoding ......................................................................... 4-77
Block Size Encoding .......................................................................................... 4-79
CSBARBT/CSBAR Bit Descriptions .................................................................. 4-80
CSOR Bit Descriptions ...................................................................................... 4-81
DSACK Field Encoding...................................................................................... 4-82
Interrupt Priority Level Field Encoding............................................................... 4-83
Chip-Select Base and Option Register
Reset Values ................................................................................................. 4-86
CSBOOT Base and Option Register
Reset Values ................................................................................................. 4-87
General-Purpose I/O Ports ................................................................................ 4-87
Port E Pin Assignments ..................................................................................... 4-90
Port F Pin Assignments ..................................................................................... 4-92
PFPAR Pin Functions ........................................................................................ 4-92
5-1 Multiplexed Analog Input Channels ....................................................................... 5-5
5-2 Analog Input Channels ........................................................................................ 5-11
5-3 Queue 1 Priority Assertion................................................................................... 5-15
5-4 QADC64 Clock Programmability ......................................................................... 5-28
5-5 QADC64 Status Flags and Interrupt Sources...................................................... 5-31
5-6 QADC64 Address Map ........................................................................................ 5-34
5-7 QADC64MCR Bit Settings .................................................................................. 5-35
5-8 QADC64INT Bit Settings .................................................................................... 5-36
5-9 PORTQA, PORTQB Bit Settings ........................................................................ 5-37
5-10 DDRQA Bit Settings.......................................................................................... 5-37
5-11 QACR0 Bit Settings .......................................................................................... 5-38
5-12 QACR1 Bit Settings .......................................................................................... 5-39
5-13 Queue 1 Operating Modes ................................................................................ 5-39
5-14 QACR2 Bit Settings .......................................................................................... 5-41
5-15 Queue 2 Operating Modes ................................................................................ 5-42
5-16 QASR0 Bit Settings .......................................................................................... 5-43
5-17 Queue Status..................................................................................................... 5-44
5-18 QASR1 Bit Settings .......................................................................................... 5-45
5-19 CCW Bit Settings .............................................................................................. 5-49
5-20 Non-Multiplexed Channel Assignments and Pin Designations.......................... 5-50
5-21 Multiplexed Channel Assignments and Pin Designations.................................. 5-50
5-22 AMUX I/O Functionality ..................................................................................... 5-53
6-1 QSMCM Register Map........................................................................................... 6-3
6-2 QSMCM Global Registers ..................................................................................... 6-5
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6-3 QSMCMMCR Bit Settings...................................................................................... 6-7
6-4 QILR Bit Settings ................................................................................................... 6-8
6-5 QIVR Bit Settings................................................................................................... 6-8
6-6 QSPI_IL Bit Settings .............................................................................................. 6-8
6-7 QSMCM Pin Control Registers .............................................................................. 6-9
6-8 Effect of DDRQS on QSPI Pin Function .............................................................. 6-10
6-9 QSMCM Pin Functions ........................................................................................ 6-11
6-10 PQSPAR Bit Settings......................................................................................... 6-12
6-11 DDRQS Bit Settings........................................................................................... 6-13
6-12 QSPI Register Map............................................................................................ 6-16
6-13 SPCR0 Bit Settings........................................................................................... 6-17
6-14 Bits Per Transfer................................................................................................ 6-17
6-15 SPCR1 Bit Settings........................................................................................... 6-18
6-16 SPCR2 Bit Settings........................................................................................... 6-19
6-17 SPCR3 Bit Settings........................................................................................... 6-20
6-18 SPSR Bit Settings............................................................................................. 6-21
6-19 Command RAM Bit Settings ............................................................................. 6-23
6-20 QSPI Pin Functions ........................................................................................... 6-24
6-21 Example SCK Frequencies
with a 40-MHz System Clock ........................................................................ 6-35
6-22 SCI Registers..................................................................................................... 6-44
6-23 SCCxR0 Bit Settings......................................................................................... 6-45
6-24 SCCxR1 Bit Settings......................................................................................... 6-46
6-25 SCxSR Bit Settings........................................................................................... 6-48
6-26 SCxSR Bit Settings........................................................................................... 6-50
6-27 SCI Pin Functions .............................................................................................. 6-50
6-28 Serial Frame Formats ........................................................................................ 6-51
6-29 Examples of SCIx Baud Rates .......................................................................... 6-52
6-30 Effect of Parity Checking on Data Size.............................................................. 6-52
6-31 QSCI1CR Bit Settings....................................................................................... 6-57
6-32 QSCI1SR Bit Settings....................................................................................... 6-59
7-1 Common Extended/Standard Format Frames....................................................... 7-5
7-2 Message Buffer Codes for Receive Buffers........................................................... 7-5
7-3 Message Buffer Codes for Transmit Buffers.......................................................... 7-5
7-4 Extended Format Frames ...................................................................................... 7-6
7-5 Standard Format Frames....................................................................................... 7-6
7-6 Receive Mask Register Bit Values......................................................................... 7-8
7-7 Mask Examples for Normal/Extended Messages .................................................. 7-8
7-8 Example System Clock, CAN Bit Rate and S-Clock Frequencies ......................... 7-9
7-9 Interrupt Sources and Vector Addresses............................................................. 7-20
7-10 TouCAN Register Map....................................................................................... 7-22
7-11 TCNMCR Bit Settings ....................................................................................... 7-24
7-12 CANICR Bit Settings......................................................................................... 7-26
7-13 CANCTRL0 Bit Settings.................................................................................... 7-26
7-14 RX MODE[1:0] Configuration............................................................................. 7-27
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7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
Transmit Pin Configuration ................................................................................ 7-27
CANCTRL1 Bit Settings..................................................................................... 7-28
PRESDIV Bit Settings....................................................................................... 7-29
CANCTRL2 Bit Settings.................................................................................... 7-29
TIMER Bit Settings ........................................................................................... 7-30
RXGMSKHI, RXGMSKLO Bit Settings ............................................................. 7-30
ESTAT Bit Settings ........................................................................................... 7-31
Transmit Bit Error Status ................................................................................... 7-32
Fault Confinement State Encoding .................................................................... 7-33
IMASK Bit Settings ........................................................................................... 7-33
IFLAG Bit Settings ............................................................................................ 7-33
RXECTR, TXECTR Bit Settings ....................................................................... 7-34
8-1 Enhanced TCR1 Prescaler Divide Values ............................................................ 8-6
8-2 TCR1 Prescaler Values ......................................................................................... 8-6
8-3 TCR2 Counter Clock Source ................................................................................. 8-7
8-4 TCR2 Prescaler Control......................................................................................... 8-8
8-5 TPU3 Register Map ............................................................................................... 8-9
8-6 TPUMCR Bit Settings ......................................................................................... 8-11
8-7 DSCR Bit Settings .............................................................................................. 8-12
8-8 DSSR Bit Settings............................................................................................... 8-13
8-9 TICR Bit Settings ................................................................................................ 8-14
8-10 CIER Bit Settings .............................................................................................. 8-14
8-11 CFSRx Bit Settings ........................................................................................... 8-15
8-12 HSQRx Bit Settings .......................................................................................... 8-16
8-13 HSSRx Bit Settings........................................................................................... 8-17
8-14 CPRx Bit Settings ............................................................................................. 8-17
8-15 Channel Priorities .............................................................................................. 8-17
8-16 CISR Bit Settings .............................................................................................. 8-18
8-17 TPUMCR2 Bit Settings ..................................................................................... 8-19
8-18 Entry Table Bank Location................................................................................. 8-19
8-19 System Clock Frequency/Minimum
Guaranteed Detected Pulse .......................................................................... 8-20
8-20 TPUMCR3 Bit Settings ..................................................................................... 8-20
8-21 Parameter RAM Address Map........................................................................... 8-21
9-1 DPTRAM Register Map ......................................................................................... 9-3
9-2 DPTMCR Bit Settings ........................................................................................... 9-4
9-3 DPTBAR Bit Settings ............................................................................................ 9-5
10-1
10-2
10-3
10-4
10-5
10-6
CMFI EEPROM Module External Signals.......................................................... 10-6
CMFI EEPROM Memory Map with 32-Bit Word ................................................ 10-7
CMFI Control Register Addressing .................................................................... 10-9
CMFIMCR Bit Settings.................................................................................... 10-10
CMFITST Bit Settings ...................................................................................... 10-13
CMF Programming Algorithm (v6 and Later)................................................... 10-13
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10-7 CMF Erase Algorithm (v6) ............................................................................... 10-14
10-8 CMFIBAR (CMFIBAH, CMFIBAL) Bit Settings ................................................ 10-15
10-9 CMFICTL1 Bit Settings .................................................................................... 10-16
10-10 CMFICTL2 Bit Settings.................................................................................. 10-17
10-11 System Clock Range ..................................................................................... 10-20
10-12 Clock Period Exponent and Pulse Width Range ........................................... 10-21
10-13 Program Interlock State Descriptions ............................................................ 10-28
10-14 Results of Programming Margin Read........................................................... 10-30
10-15 Register Shadow Information ........................................................................ 10-31
10-16 Erase Interlock State Descriptions................................................................. 10-33
11-1
11-2
11-3
11-4
RAMMCR Bit Settings ....................................................................................... 11-4
RASP Encoding ................................................................................................. 11-4
RAMBAH, RAMBAL Bit Settings ...................................................................... 11-5
SRAM Array Read/Write Minimum Access Times............................................. 11-6
12-1
12-2
12-3
12-4
12-5
12-6
ROM Module Register Map ............................................................................... 12-3
ROMMCR Bit Settings ....................................................................................... 12-4
BAR (ROMBAH, ROMBAL) Bit Settings............................................................ 12-6
SIGHI Bit Settings.............................................................................................. 12-6
SIGLO Bit Settings............................................................................................. 12-7
Minimum ROM Module Access Times............................................................. 12-11
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
CTM9 Configuration Description........................................................................ 13-3
FCSM Register Map .......................................................................................... 13-7
FMSMSIC Bit Settings ....................................................................................... 13-8
MCSM Register Map ....................................................................................... 13-12
MCSMSIC Bit Settings..................................................................................... 13-13
SASM Register Map ........................................................................................ 13-20
SICA Bit Settings ............................................................................................. 13-21
DASM Modes of Operation.............................................................................. 13-25
DASM PWM Example Output
Frequencies/Resolutions at fSYS = 16 MHz ............................................... 13-34
13-10 DASM Register Map...................................................................................... 13-35
13-11 DASMSIC Bit Settings ................................................................................... 13-36
13-12 PWM Pulse and Frequency Ranges (in Hz)
Using /2 Option (16.78 MHz)....................................................................... 13-43
13-13 PWM Pulse and FrequencyRanges (in Hz)
Using /3 Option (16.78 MHz)....................................................................... 13-43
13-14 PWMSM Register Map .................................................................................. 13-45
13-15 PWMSIC Bit Settings..................................................................................... 13-46
13-16 PWMSM Output Pin Polarity Selection.......................................................... 13-48
13-17 PWMSM Clock Rate Selection ...................................................................... 13-48
13-18 BIUSM Register Map ..................................................................................... 13-51
13-19 BIUMCR Bit Settings ..................................................................................... 13-51
13-20 CPSM Register Map...................................................................................... 13-53
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13-21 CPCR Bit Settings ......................................................................................... 13-54
13-22 Prescaler Division Ratio Select...................................................................... 13-54
A-1 TouCAN (CAN 2.0B Controller)............................................................................. A-2
A-2 CTM9 (Configurable Timer Module)...................................................................... A-4
A-3 QADC64 (Queued Analog-to-Digital Converter) ................................................... A-7
A-4 CMFI (CDR MoneT FLASH FOR THE IMB3) ....................................................... A-8
A-5 ROM Module ......................................................................................................... A-8
A-6 Overlay SRAM Modules (Static Random Access Memory).................................. A-9
A-7 DPTRAM (Dual-Port TPU RAM) ........................................................................... A-9
A-8 SCIM2E (Single-Chip Integration Module) ..........................................................A-10
A-9 SRAM Module (Static Random Access Memory)................................................A-12
A-10 QSMCM (Queued Serial Multi-Channel Module) .............................................. A-12
A-11 TPU3 (Time Processor Unit) ............................................................................. A-14
D-1
D-2
D-3
D-4
D-5
Bank 0 Functions ..................................................................................................D-2
Bank 1 Functions ..................................................................................................D-2
QOM Bit Encoding ................................................................................................D-5
SIOP Function Valid CHAN_Control Options......................................................D-44
SIOP State Timing ..............................................................................................D-46
E-1 Absolute Maximum Ratings................................................................................... E-1
E-2 Thermal Characteristics ........................................................................................E-2
E-3 DC Characteristics ................................................................................................E-2
E-4 Clock Control Timing............................................................................................. E-5
E-5 AC Timing.............................................................................................................. E-6
E-6 Background Debugging Mode Timing ................................................................. E-17
E-7 ECLK Bus Timing ................................................................................................ E-18
E-8 QSPI Timing ........................................................................................................E-20
E-9 Time Processor Unit (TPU3) Timing ...................................................................E-23
E-10 QADC64 Maximum Ratings .............................................................................. E-24
E-11 QADC64 DC Electrical Characteristics (Operating) .......................................... E-25
E-12 QADC64 AC Electrical Characteristics (Operating) .......................................... E-26
E-13 QADC64 Conversion Characteristics (Operating)............................................. E-27
E-14 AMUX_HV Absolute Maximum Ratings ............................................................ E-28
E-15 AMUX_HV DC Electrical Characteristics (Operating) .......................................E-28
E-16 AMUX_HV Conversion Characteristics (Operating).......................................... E-29
E-17 CTM9 5 V, 16.78 MHz Operating Conditions .................................................... E-29
E-18 CTM9 5 V, 25 MHz Operating Conditions .........................................................E-29
E-19 FCSM Timing Characteristics............................................................................E-30
E-20 MCSM Timing Characteristics........................................................................... E-30
E-21 SASM Timing Characteristics............................................................................E-31
E-22 DASM Timing Characteristics ........................................................................... E-31
E-23 PWMSM Timing Characteristics........................................................................ E-32
E-24 TouCAN AC Characteristics.............................................................................. E-32
E-25 CMFI Program and Erase Characteristics.........................................................E-33
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E-26 CMFI AC and DC Power Supply Characteristics .............................................. E-33
E-27 CMFI FLASH EEPROM Module Life................................................................. E-34
E-28 IMB3 ROM AC/DC Characteristics.................................................................... E-36
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Freescale Semiconductor, Inc...
PREFACE
This manual describes the capabilities, operation, and functions of the MC68F375
microcontroller unit. Documentation for the Modular Microcontroller Family follows
the modular construction of the devices in the product line. Each device has a comprehensive user’s manual which provides sufficient information for normal operation of the device. The user’s manual is supplemented by module reference
manuals that provide detailed information about module operation and applications. Refer to Motorola publication Advanced Microcontroller Unit (AMCU) Literature (BR1116/D) for a complete listing of documentation to supplement this
manual.
The following describes changes made to the manual since the revision 1 release
(15 October 2000):
Table i. Revision History
Revision
Date
Description
0
N/A
Initial document.
1
15 October 2000 First revision.
2
25 June 2003
Page Referrent
Description
2-2,
2-3
Table 2-1, Added Note #6 - All PortF pins have weak pull-up to pin mnemonic:
NOTES
FASTREF/PF[0], IRQ[7]/PF[7], IRQ[6]/PF[6], IRQ[5:1]/PF[5:1].
E-1
Table E-1
Max Vin changed to 6.5V
E-2
Table E-3
Changed VDDH to 5.0 +/- 5%
E-3
Table E-3
Note #12, Design information only, not tested:
• Removed on RUN, TPU3 emulation mode
• Added to LPSTOP, 4.19MHz crystal, VCO off (STSIM =0)
• Added to ISB for Transient condition
E-4
NOTES:
• Added PE[2] to Port E
Group 5 • Added PF[4:1] to Port F
E-4
NOTES
Added Note #11 - HALT and RESET are open drain and do not apply
for VOH5 spec
E-5
Table E-4
NOTES
Note #9, Design information only, not tested, added to
- 1 fref (Slow reference mode), -3 PLL Lock Time, -5 Limp Mode
Clock Frequency, -6 CLKOUT Jitter
E-6
Table E-5
tcyc changed to 30ns
E-25 Table E-11 Note #9 - Design information only, not tested, added to
- 3 Vss Differential Voltage, -4 VDD Differential Voltage, -8 MidAnalog Supply Voltage, -12 Input Hysteresis, -15 Reference Supply
Current, -16 Load Capacitance, PQA
E-28 Table E-15 Note #7, Design information only, not tested, added to
- 3 Vss Differential Voltage, -8 Disruptive Input Injection Current
Reference Supply Current
E-33 Table E-26 Note #1, Design information only, not tested, added to
- IDDF (Disabled), IPP (Read, VPP and Program, VPP)
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The following conventions are used throughout the manual.
Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
To set a bit means to establish logic level one on the bit.
To clear a bit means to establish logic level zero on the bit.
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0xXXXX denotes hexadecimal numbers, 0bXXXX denotes binary.
A signal that is asserted is in its active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal
changes from logic level zero to logic level one.
A signal that is negated is in its inactive logic state. An active low signal changes
from logic level zero to logic level one when negated, and an active high signal
changes from logic level one to logic level zero.
A specific bit or signal within a range is referred to by mnemonic and number.
For example, ADDR15 is bit 15 of the address bus. A range of bits or signals is
referred to by mnemonic and the numbers that define the range. For example, DATA[7:0] form the low byte of the data bus.
LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out.
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SECTION 1
OVERVIEW DESCRIPTION
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1.1 Introduction
The MC68F375 is a member of the MC68300/68HC16 family of modular microcontrollers. This family includes a series of modules from which numerous microcontrollers
(MCU’s) are derived. These modules are connected on-chip via the intermodule bus
(IMB). This section includes a list of pins that are available to each module on the chip,
see Table 1-1.
1.2 MC68F375 Feature List
The major features of the MC68F375 are listed below. A block diagram of the device
is shown in Figure 1-1.
• Modular architecture.
• 32-bit 68000 family CPU with upward object code compatibility (CPU32):
— Virtual memory implementation.
— Loop mode for instruction execution.
— Improved exception handling for controller applications.
— Table lookup and interpolate instruction.
• Single chip integration module (SCIM2E):
— External bus support.
— Parallel ports option on address and data bus in single chip modes and partially expanded modes.
— Nine programmable chip select outputs.
— Two special emulation-specific chip select outputs.
— System protection logic.
— System clock based on slow (~32 KHz) or Fast (~4 MHz) crystal reference or
external clock operation (2X).
— Periodic interrupt timer, watchdog timer, clock monitor and bus monitor.
• 10-bit queued analog-to-digital converter with AMUX (QADC64):
— Up to 16 channels on the QADC64 (25 total including the 16 AMUX Channels).
— 4 automatic channel selection and conversion modes.
— 2 channel scan queues of variable length.
— 64 result registers and 3 result alignment formats.
— Programmable input sample time.
— Analog multiplexer capable of multiplexing 16 analog channels.
• Queued serial multi-channel communication module with three serial I/O subsystems (QSMCM):
— 2 enhanced SCI (UART): modulus baud rate generator, parity. One SCI has
16 level Rx and Tx queues.
— Queued SPI: 160-byte RAM, up to 32 automatic transfers, continuous cycling,
8-to-16 bits per transfer, LSB/MSB first.
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— Dual function I/O port pins.
• Time processing unit (TPU3):
— 16 channels – each is associated with a pin.
— Each channel can perform any time function.
— Each time function may be assigned to more than one channel.
— Each channel has an event register comprised of: 16-bit capture register, 16bit compare/match register, 16-bit greater-than-or-equal-to comparator.
— Each channel can be programmed to perform match or capture operations
with one or both of the two 16-bit free running timer count registers (TCR1 and
TCR2).
— TCR1 is clocked from the internal TPU3 system clock.
— TCR2 may be clocked or gated from the external T2CLK pin.
— All time primitives are microcoded.
— 4 Kbytes of microstore program ROM space.
— All channels have eight 16-bit parameter registers.
— A hardware scheduler with three priority levels is included.
— Resolution is one system clock period.
— Modulus prescaler (DIV 2, 4, 6...... 62, 64)
• 6-Kbyte TPU emulation RAM (DPTRAM).
— Can be used as system RAM or TPU microcode storage.
• 256K Byte 1T Flash EEPROM (CMFI).
— 5 V program/erase.
— Block 0 protected by an external pin.
• SRAM
— External VSTBY pin for separate standby supply.
— 8-Kbyte static RAM (SRAM):
— 4 x 512-byte static RAM (SRAM):
— 512-byte modules can overlay any 512-byte portion (on 512-byte boundaries)
of the CMFI module.
• Late programmable read only memory – ROM:
— 8-Kbyte array, accessible as bytes or words.
— User selectable default base address.
— User selectable bootstrap ROM function.
• CAN2.0B controller module (TouCAN):
— Full implementation of CAN protocol specification – Version 2.0B.
— Standard/extended data and remote frames (up to 109/127 bits long).
— Programmable bit rate up to 1 Mbit/sec, derived from system clock.
— 16 Rx/Tx message buffers of 0-8 bytes data length, of which 2 buffers are configurable to work as Rx buffers with specific programmable masks.
— Programmable global Rx masks.
— Programmable transmit-first scheme: lowest ID or lowest buffer number.
— Low power “SLEEP” mode, with programmable “WAKE UP” on bus activity.
— Automatic time-stamping of received and transmitted messages.
• Configurable timer module 9 (CTM9):
— 1 bus interface unit submodule (BIUSM).
— 1 counter prescaler submodule (CPSM).
— 1 free-running counter submodule (FCSM).
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— 2 modulus counter submodules (MCSM).
— 4 single action submodules (SASM).
— 4 double action submodules (DASM).
— 4 dedicated PWM submodules (PWMSM)
• Package: flip chip and 217-ball 23 x 23 mm PBGA.
• Operating temperature: -40° C through 125° C
• Operating frequency: 33.00 MHz system clock at VDDL = 3.3 V / VDDH = 5.0 V.
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1.3 Module Descriptions
A short description of each module of the MC68F375 appears in the following sections.
For more details on each module, please refer to the specific module section as
indicated.
1.3.1 Central Processing Unit Module – CPU32
The CPU32 is upward-compatible with the M68000 family which excels at processing
calculation-intensive algorithms and supporting high level languages. All of the
MC68010 and most of the MC68020 enhancements such as virtual memory support,
loop mode execution, and 32-bit mathematical operations are supported. New instructions such as table lookup and interpolate and low-power stop support the specific
requirements of controller applications. Refer to SECTION 3 CENTRAL PROCESSOR UNIT.
1.3.2 Single Chip Integration Module – SCIM2E
The MC68F375 contains the single chip integration module 2 (SCIM2E). The SCIM2E
consists of several submodules: the external bus interface, the system protection submodule, the test submodule, the clock synthesizer, and the chip select submodule.
Refer to SECTION 4 SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E).
The MC68F375 SCIM2E includes improvements to the regular SCIM. This enhanced
SCIM includes improvements to the clock synthesizer. These changes are defined in
detail in 4.3.2 Clock Synthesizer Submodule. Please refer to the SCIM Reference
Manual (SCIMRM/AD) for more details on the characteristics of this module.
1.3.3 Queued Analog to Digital Converter Module – QADC64
The queued analog-to-digital converter 64 (QADC64) provides the microcontroller
unit (MCU) with two conversion sequence control mechanisms (queues); a 16
channel expandable multiplexer; a 10-bit A/D converter; and digital port logic. Refer to SECTION 5 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64.
• The queue RAM stores the sequence of channels to convert, conversion parameters, and stores conversion results.
• The queue control logic provides the trigger/run modes, interrupt control, queue
status, etc.
• The 10-bit A/D converter selects and convert the desired channel, using a successive approximation technique. The absolute accuracy (total unadjusted error)
compared to an ideal transfer curve is +/-2 counts.
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• The port logic provides up to 8 input-only and 8 bidirectional digital interface pins.
Pins which are used as analog channels should be masked out of the digital data.
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1.3.4 Analog Multiplexer – AMUX
The analog multiplexer (AMUX) submodule expands the channel capacity of the
QADC64 analog-to-digital converter inputs by a maximum of 32 analog channels. 16
analog channels are bonded out on the MC68F375. The AMUX does not have an
intermodule bus (IMB3) interface; control is through the QADC64. Refer to 5.13 Analog Multiplexer Submodule.
1.3.5 Queued Serial Multi-Channel Communications Module – QSMCM
The queued serial multi-channel module (QSMCM) provides the microcontroller unit
(MCU) with three serial communication interfaces divided into three submodules: the
queued serial peripheral interface (QSPI) and two serial communications interfaces
(SCI). These submodules communicate with the CPU via a common slave bus interface unit (SBIU). Refer to SECTION 5 QUEUED ANALOG-TO-DIGITAL
CONVERTER MODULE-64.
The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals and other MCUs. It is enhanced from the original QSM to include a total of 160
bytes of queue RAM to accommodate more receive, transmit, and control information.
The duplicate, independent, SCIs are full-duplex universal asynchronous receiver
transmitter (UART) serial interface. The original QSM SCI is enhanced by the addition
of an SCI, a common external baud clock source, receive and transmit buffers on one
SCI.
1.3.6 TouCAN Module
The TouCAN module is a communication controller implementing the CAN protocol. It
contains all the logic needed to implement the CAN2.0B protocol, supporting both
standard ID format and extended ID. The protocol is a CSMA/CD type, with collision
detection without loss, used mainly for vehicle systems communication and industrial
applications. The module contains 16 message buffers used for transmit and receive,
and masks used to qualify the received message ID before comparing it to the receive
buffers. Refer to SECTION 7 CAN 2.0B CONTROLLER MODULE.
1.3.7 Enhanced Time Processing Unit – TPU3
The TPU3 is an intelligent, semi-autonomous co-processor designed for timing control. Operating simultaneously with the CPU, the TPU processes microinstructions,
schedules and processes real-time hardware events, performs input and output, and
accesses shared data without CPU intervention. Consequently, for each timer event
the CPU setup and service time are minimized or eliminated.
The TPU3 can be viewed as a special-purpose microcomputer that performs a programmable series of two operations, match and capture. Each occurrence of either operation is called an event. A programmed series of events is called a function. TPU3
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functions replace software functions that would require host CPU interrupt service. Refer to SECTION 8 TIME PROCESSOR UNIT 3.
1.3.8 DPTRAM TPU Emulation RAM Module – DPTRAM
The RAM module with TPU microcode storage support (DPTRAM) consists of a control register block and a 6-Kbyte array of static RAM which can be used as a microcode
storage for TPU3 or general purpose memory. Microcode initialization is done by the
host CPU through standard IMB modes of access. Refer to SECTION 9 DUAL-PORT
TPU RAM (DPTRAM).
Freescale Semiconductor, Inc...
The DPTRAM interface includes an IMB3 bus Interface and two1 TPU3 interfaces.
When the RAM is being used in microcode mode, the array may only be accessed by
the TPU3 via a separate local bus, and not via the intermodule bus.
1.3.9 1T Flash Electrically Erasable Read Only Memory – CMFI
The MC68F375 contains an electrically erasable, programmable 256-Kbyte FLASH
memory (CMFI). The primary function of the CMFI module is to serve as electrically
programmable and erasable non-volatile memory (NVM) to store program instructions
and/or data. It is a non-volatile solid state silicon memory device consisting of an array
of isolated elements, a means for selectively adding and removing charge to the elements electrically and a means of selectively sensing the stored charge in the
elements. When power is removed from the device, the stored charge of the isolated
elements will be retained. Refer to SECTION 10 CDR MoneT FLASH FOR THE IMB3
(CMFI).
1.3.10 Static RAM – SRAM
There are two types of SRAM in the MC68F375:
• 8K Static RAM – SRAM. This module is a fast access (2 clocks) general purpose
static RAM (SRAM) for the MCU and is accessed via the IMB.
• 2K (4 x 512 Byte) Patch Static RAM – SRAM. These modules are fast access (2
clocks) general purpose static RAMs (SRAM) for the MCU with a patch option
which provides a method to overlay the internal CMFI memory for emulation.
Refer to SECTION 11 STATIC RANDOM ACCESS MEMORY (SRAM).
1.3.11 Mask Programmable Read Only Memory – ROM
The Mask ROM module is designed to be used with the inter-module bus (IMB3) and
consequently any CPU capable of operating on the IMB. A size of 8192 (8K) bytes was
selected to reside on the MC68F375 MCU. The ROM is a “late programmable” type
which means that programming of the array and control register options occurs later
in the processing flow, allowing reduction in cycle time between software code
changes from the user to available devices.
During master reset the ROM will monitor one DATA line (DATA14) to determine if it
should respond as a memory mapped ROM, or be disabled. If the state of DATA14 is
1.
Note: the MC68F375 contains only a single TPU3. The second TPU3 interface is inactive.
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1, the STOP bit in the ROMMCR register will be cleared to 0 and the array will respond
normally to the bootstrap address range and the ROM array base address. If DATA14
is 0, the STOP bit will be set and the bootstrap address range and the ROM array will
be disabled until the STOP bit is cleared either by an IMB write or until the next master
reset which occurs with DATA14 = 1. When STOP is set, the array will not respond to
the bootstrap address range or the ROM Array base address in ROMBAH and ROMBAL, allowing an external device to respond to the ROM Array’s address space, and/
or provide bootstrap information. This allows the ROM to be disabled from outside of
the device if necessary. Refer to SECTION 12 MASK ROM MODULE.
1.3.12 Configurable Timer Module 9 – CTM9
The configurable timer module (CTM) is a family of timer modules for the Motorola
Modular Microcontroller Family (MMF). The timer architecture is modular—before the
chip is manufactured the user can specify the number of time-bases (counter submodules) and channels (action submodules, or timer I/O pins) that are included. Refer to
SECTION 13 CONFIGURABLE TIMER MODULE (CTM9). The major blocks in the
CTM9 are:
• Bus interface unit submodule (BIUSM)
• Single action submodule (SASM)
• Double action submodule (DASM)
• Pulse width modulation submodule (PWMSM)
• Counter prescaler submodule (CPSM)
• Free-running counter submodule (FCSM)
• Modulus counter submodule (MCSM)
1.4 Referenced Documents
• CPU32 Central Processor Unit Reference Manual (CPU32RM/AD).
• SCIM Reference Manual (SCIMRM/AD).
• QSM Reference Manual (QSMRM/AD or QSM section of MC68332UM/AD).
• CTM Reference Manual (CTMRM/D).
• TPU Reference Manual (TPURM/AD).
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T2CLK
TP[15:0]
VDDDPTRAM
CS3–CS10
BGACK
BR
BG
FC0/CS3/PC0
FC1/PC1
FC2/CS5/PC2
ADDR19/CS6/PC3
ADDR20/CS7/PC4
ADDR21/CS8/PC5
ADDR22/CS9/PC6
ADDR23/CS10/ECLK
Control
Port TP
BR/CS0
BG/CSM
BGACK/CSE
FLASH
EEPROM
256K Bytes
DPTRAM
6 Kbytes
TPU3
SCIM2E
EBI
Control
CTM9
1
FCSM
ADDR[18:11]/PA[7:0]
ADDR[10:3]/PB[7:0]
D[15:0]
Intermodule Bus (IMB3)
Port E
4
PWMSM
Control
4
DASM
Control
DSACK0
DSACK1
AVEC
PE3
DS
AS
SIZ0
SIZ1
4
SASM
Port G/H
ADDR[2:0]
2
MCSM
Analog MUX
ANX[15:0]
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
RMC/PE3
DS/PE4
AS/PE5
SIZ0/PE6
SIZ1/PE7
DATA[15:8]/PG[7:0]
DATA[7:0]/PH[7:0]
TouCAN
ECK*
FASTREF
CPU32
Port F
SRAM
8 Kbytes
Control
IRQ[7:1]
FASTREF/PF0
IRQ1/PF1
IRQ2/PF2
IRQ3/PF3
IRQ4/PF4
IRQ5/PF5
IRQ6/PF6
IRQ7/PF7
CLKOUT
XTAL
EXTAL
XFC
VDDSYN/MODCLK
VSSSYN
Clock
Control
TSC
FREEZE/QUOT
Control
TSC
QUOT
FREEZE
VSTBY
CNTX
CNRX
DSCLK
DSO
DSI
IPIPE
IFETCH
BKPT
Test
VDDH, VDDL
VSS
RXD[1,2]
TXD[1,2]
PCS0/SS
PCS1
PCS2
PCS3
SCK
MISO
MOSI
Overlay SRAM 2K Bytes (4x512)
QSMCM
R/W
RESET
HALT
BERR
Port QS
Freescale Semiconductor, Inc...
QADC64
w/ AMUX
ROM 8 Kbytes
FC0
FC1
FC2
Port C
QAB Port
QAA Port
Port CT
CSBOOT
Chip
Selects
Port A/B
VPP
EPEB0
VRL
VRH
VDDA
VSSA
PQB[7:0]
PQA[7:0]
CPWM[8:5]
CTD[10:9]/[4:3]
CTS[20B:14A]
CTM2C
1.5 MC68F375 Functional Block Diagram
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
* Not Pinned Out
Figure 1-1 MC68F375 Block Diagram
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1.6 MC68F375 Pin Usage
Table 1-1 shows the MC68F375 pin usage. For more information on an individual pin,
refer to the corresponding module documentation.
Table 1-1 MC68F375 Pin Usage
Freescale Semiconductor, Inc...
Functions
Total Pins
Port Pins
CPU32
BDM
Total
3
3
SCIM2E
Port A, Port B
Port G, Port H
Port F
Port C
Port E
Bus Control, A[2:0], CSBOOT, TSC, RESET
CLKOUT, PLL
Total
16
16
8
7
8
13
4
72
16
16
8
7
8
QADC64/AMUX
Channels
Analog Mux
Total
16
16
32
16
4
7
4
7
11
11
16
1
17
16
QSMCM
SCI1, SCI2
SPI
ECK
Total
55
16
TPU3
Channels
Clock
Total
16
TouCAN
Receive
Transmit
1
1
2
PWMSM
SASM
DASM
Clock
4
8
4
1
17
Total
CTM9
Total
4
8
4
16
CMFI
EPEB0
Total
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Table 1-1 MC68F375 Pin Usage (Continued)
Functions
Total Pins
Power (VDDH, VDDL, VSS)
I/O Pad Power (VDDH)
Logic Power (VDDL)
Ground (VSS)
SRAM (VSTBY)
DPTRAM (VDDDPTRAM)
CMFI (VPP)
SCIM2E Clock (VDDSYN/VSSSYN)
QADC64 Power (VDDA/VSSA)
QADC64 Reference (VRH/VRL)
Total
14
3
16
1
1
1
2
2
2
42
Total
Freescale Semiconductor, Inc...
Port Pins
199
114
1.7 Address Map
Each MC68300/MC68HC16 derivative MCU has a 4-Kbyte block in the memory map
that is assigned to internal module registers. The MSB of the block address is userprogrammable via the MM (MODMAP) bit in the SCIMMCR register, see 1.7.1
Address Bus Decoding. Within this 4-Kbyte block are sub-blocks that are assigned
to the individual modules, as shown in the MC68F375 address map in Figure 1-2.
These sub-blocks vary in size, depending on the register requirements for each module. Positioning of registers within the module sub-blocks is dependent on the
individual modules and is specified in the respective module specifications. The RAM,
ROM, and CMFI array spaces are not shown with an assigned address because the
arrays are not enabled after reset. The arrays are enabled and the base address is set
by writing to the control blocks of each array.
Each module that is assigned a sub-block is responsible for responding to any
accesses within its assigned address range. Modules do not respond to any register
address within the module address space which is not implemented and not reserved.
These addresses are mapped outside the MC68F375. An access to a register at an
address which is reserved returns zeros, as do accesses to reserved bits within
registers.
If the SUPV bit in the module configuration register (MCR) within a module is set, any
user mode accesses to the module are mapped externally.
1.7.1 Address Bus Decoding
The internal MODMAP line is compared to internal address line A[23] while A[22:0] are
decoded by each module. If a module control block address is decoded, the access
will be internal. The value of A[22] down to the module block size is defined in Figure
1-2 for each module. These bits are fixed for this particular derivative device and are
specified by Motorola. The value of MODMAP is specified by the MM control bit in the
SCIM2E module configuration register (SCIMMCR), see 4.2.2 Module Mapping.
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0xYF F000
Unused
0xYF F080
TouCAN
384 Bytes
0xYF F200
FLASH ARRAY
256 K Bytes
CTM9
256 Bytes
0xYF F300
Unused
Freescale Semiconductor, Inc...
0xYF F400
QADC64
1024 Bytes
ROM ARRAY
8 K Bytes
0xYF F800
256K CMFI CTL, 32 Bytes
0xYF F820
0xYF F840
0xYF F848
0xYF F850
0xYF F858
SRAM ARRAY
512 Bytes
ROM CTL, 32 Bytes
OVERLAY SRAM1 CTL, 8 Bytes
SRAM ARRAY
512 Bytes
OVERLAY SRAM2 CTL, 8 Bytes
OVERLAY SRAM3 CTL, 8 Bytes
SRAM ARRAY
512 Bytes
OVERLAY SRAM4 CTL, 8 Bytes
0xYF F860
Unused
0xYF F880
6 K DPTRAM CTL, 32 Bytes
0xYF FA00
SCIM2E
128 Bytes
0xYF FA80
Unused
0xYF FB00
SRAM ARRAY
512 Bytes
DPTRAM ARRAY
6 K Bytes
8 K SRAM CTL, 8 Bytes
0xYF FB08
Unused
0xYF FC00
SRAM ARRAY
8 K Bytes
QSMCM
512 Bytes
0xYF FE00
TPU3
512 Bytes
0xYF FFFF
Y = M111, where M is the logic state of the module mapping (MM) bit
in the SCIM2E configuration register (SCIMMCR).
Figure 1-2 MC68F375 Address Map
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SECTION 2
SIGNAL DESCRIPTIONS
2.1 Pin Characteristics
Table 2-1 shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high impedance state, but the method of doing this differs
depending upon pin function. Refer to Table 2-3 for a description of output drivers. An
entry in the discrete I/O column of the MC68F375 pin characteristics table indicates
that a pin has an alternate I/O function. The port designation is given when it applies.
Refer to the MC68F375 block diagram for information about port organization.
Table 2-1 Pin Characteristics
Input Type
Pin Mnemonic
Module
Output
Driver
Sync
Hyst Sync
Hyst/Other
Port
Designation
ADDR[23]/
CS[10]/ECLK
SCIM2E
A
no
yes
no
—
ADDR[22:19]/
CS[9:6]/PC[6:3]
SCIM2E
A
no
yes
no
PC[6:3]
ADDR[18:11]/PA[7:0]
SCIM2E
A
no
yes
no
PA[7:0]
ADDR[10:3]/PB[7:0]
SCIM2E
A
no
yes
no
PB[7:0]
ADDR[2:0]
SCIM2E
A
no
yes
no
—
1
AN[59:57]/PQA[7:5]
QADC64
Aqa
no
yes
no
PQA[7:5]
AN[56:55]/ETRIG[2:1]/
PQA[4:3]
QADC64
Aqa
no
yes2
no
PQA[4:3]
AN[54:52]/MA[2:0]/
PQA[2:0]
QADC64
Aqa
no
yes3
no
PQA[2:0]
AN[51:48]/PQB[7:4]
QADC64
—
no
yes
no
PQB[7:4]
AN[3:0]/AN[z,y,x,w]/
PQB[3:0]
QADC64
—
no
yes1
no
PQB[3:0]
ANX[15:0]
QADC64
—
no
yes1
no
—
AS/PE[5]
SCIM2E
B
no
yes
no
PE[5]
AVEC/PE[2]
SCIM2E
B
yes
no
no
PE[2]
BERR
SCIM2E
B
yes
no
no
—
BG/CSM
SCIM2E
B
no
no
no
—
BGACK/CSE
SCIM2E
B
yes
no
no
—
BKPT/DSCLK
CPU
—
no
yes
no
—
BR/CS[0]
SCIM2E
B
yes
no
no
—
CLKOUT
SCIM2E
A
no
no
no
—
CNRX
TOUCAN
—
no
yes
no
—
CNTX
TOUCAN
Bo
no
yes
no
—
CSBOOT
SCIM2E
B
no
no
no
—
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Table 2-1 Pin Characteristics (Continued)
Input Type
Pin Mnemonic
Module
Output
Driver
Sync
Hyst Sync
Hyst/Other
Port
Designation
CPWM[8:5]
CTM9
A
no
yes
no
—
CTD[10:9]
CTM9
A
no
yes
no
—
CTM2C
CTM9
A
no
yes
no
—
CTS[20B-14A]
CTM9
A
no
yes
no
—
1
DATA[15:8]/PG[7:0]
SCIM2E
DB
no
yes
no
PG[7:0]
DATA[7:0]/PH[7:0]
SCIM2E
DB
no
yes
no
PH[7:0]
DS/PE[4]
SCIM2E
B
no
yes
no
PE[4]
DSACK[1:0]/PE[1:0]
SCIM2E
B
yes
no
no
PE[1:0]
ETRIG[2:1]/PQA[4:3]
QADC64
Aqa
no
yes1
no
PQA[4:3]
EXTAL4,5
PLLWXY
—
no
no
Special
—
FASTREF/PF[0]6
SCIM2E
Bp
no
yes1
no
PF[0]
FC[2]/CS[5]/PC[2]
FC[1]/PC[1]
FC[0]/CS[3]/PC[0]
SCIM2E
A
yes
no
no
PC[2:0]
FREEZE
/QOUT
SCIM2E
A
no
no
no
—
HALT
SCIM2E
Bop
yes
no
no
—
IFETCH/DSI
CPU
A
no
yes
no
—
IPIPE/DSO
CPU
A
no
no
no
—
IRQ[7]/PF[7]6
SCIM2E
Bp
no
yes
no
PF[7]
IRQ[6]/PF[6]6
SCIM2E
B
no
yes
no
PF[6]
IRQ[5:1]/PF[5:1]6
SCIM2E
B
no
yes
no
PF[5:1]
MA[2:0]/PQA[2:0]
QADC64
Aqa
no
yes1
no
PQA[2:0]
no
PQS[0]
MISO/PQS[0]
QSMCM
Bo
no
yes1
MOSI/PQS[1]
QSMCM
Bo
no
yes1
no
PQS[1]
PCS[0]/SS/PQS[3]
QSMCM
Bo
no
yes1
no
PQS[3]
no
PQS[6:4]
—
PCS[3:1]/PQS[6:4]
QSMCM
Bo
no
yes1
R/W
SCIM2E
A
yes
yes
no
RESET
SCIM2E
Bo
no
yes
no
—
RMC(BLOCK)/PE[3]
SCIM2E
B
no
yes
no
PE[3]
RXD[1,2]/PQS[8,10]
QSMCM
—
no
no
yes
PQS[8,10]
SCK/PQS[2]
QSMCM
Bo
no
yes1
no
PQS[2]
SIZ[1:0]/PE[7:6]
SCIM2E
B
no
yes
no
PE[7:6]
T2CLK
TPU3
A
no
yes
no
—
TP[15:0]
TPU3
A
no
yes
no
—
TSC
SCIM2E
—
no
yes
no
—
no
PQS[7,9]
no
—
TXD[1,2]/PQS[7,9]
QSMCM
Bo
no
yes1
VDDSYN
/MODCLK
SCIM2E
—
no
yes1
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Table 2-1 Pin Characteristics (Continued)
Input Type
Pin Mnemonic
Module
Output
Driver
Sync
Hyst Sync
Hyst/Other
Port
Designation
EPEB03
CMFI
—
yes
—
—
—
XFC4
PLLWXY
—
no
no
Special
—
XTAL4,3
PLLWXY
—
no
no
Special
—
Freescale Semiconductor, Inc...
NOTES:
1. DATA[15:0]
2. DATA[15:0]
3. DATA[15:0]
4. EXTAL, XFC and XTAL are clock reference connections.
5. These pins are 3 V level only.
6. All Port F pins have weak pull-up.
Table 2-2 Power Connections
Pin
Voltage
Description
1
VSTBY
3.3 V
Standby RAM power
VDDDPTRAM
3.3 V
DPTRAM power (connect to VDDL)
VDDSYN
VSSSYN
3.3 V2
0V
Clock synthesizer power
VDDA
VSSA
5V
0V
QADC64 converter power
VRH
VRL
5V
0V
QADC64 reference voltage
VSS
VDDH
0V
5V
Pad output driver power (Source and Drain)
VSS
VDDL
0V
3.3 V
VPP
3.3 V/5 V
Module power (Source and Drain)
CMFI program/erase voltage
NOTES:
1. Throughout this manual 3 V = 3.3 volts ±0.3 volts.
5 V = 5 volts ±10%, except VPP 5 V = 5 volts ±5%.
2. VDDSYN/MODCLK = 3.3 V for VDDSYN function.
VDDSYN/MODCLK = 0 V for MODCLK function.
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Table 2-3 Output Driver Types
Type
I/O
A
O
Output that is always driven. No external pull-up required.
Description
Aqa
O
Type A output open drain on a QADC64 pin
B
O
Three-state output that includes circuitry to assert output before high impedance is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level
while in the high-impedance state.
Bo
O
Type B output that can be operated in an open-drain mode.
Bop
O
Type B output that can be operated in an open-drain mode with weak pull-up.
O
Type B output with weak pull-up.
O
Data bus driver with weak pull-up which pulls data bus high during reset.
Freescale Semiconductor, Inc...
Bp
DB
Table 2-4 Signal Characteristics
Signal Name
MCU Module
Signal Type
Active State
ADDR[23:0]
SCIM2E
Bus
—
AN[59:48]/[3:0]
QADC64
Input
—
AN[z, y, x, w]
QADC64
Input
—
ANX[15:0]
Analog MUX
Input
—
AS
SCIM2E
Output
0
AVEC
SCIM2E
Input
0
BERR
SCIM2E
Input
0
BG
SCIM2E
Output
0
BGACK
SCIM2E
Input
0
BKPT
CPU32
Input
0
BR
SCIM2E
Input
0
CLKOUT
SCIM2E
Output
—
CNRX
TOUCAN
Input
---
CNTX
TOUCAN
Output
---
CS[10:5], CS[3], CS[0]
SCIM2E
Output
0
CSBOOT
SCIM2E
Output
0
CSE
SCIM2E
Output
0
CSM
SCIM2E
Output
0
CPWM[8:5]
CTM9
Output
1/0
CTD[10:9]
CTM9
Input/Output
—
CTM2C
CTM9
Input
1/0
CTS[20B - 14A]
CTM9
Input/Output
—
DATA[15:0]
SCIM2E
Bus
—
DS
SCIM2E
Output
0
DSACK[1:0]
SCIM2E
Input
0
DSCLK
CPU32
Input
Serial Clock
DSI
CPU32
Input
Serial Data
DSO
CPU32
Output
Serial Data
ECLK
SCIM2E
Output
—
MC68F375
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MOTOROLA
2-4
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 2-4 Signal Characteristics (Continued)
Signal Name
MCU Module
Signal Type
Active State
ETRIG[2:1]
QADC64
Input
1/0
EXTAL1
SCIM2E
Input
—
FASTREF
SCIM2E
Input/Output
1
FC[2]/CS[5]/PC[2]
FC[1]/PC[1]
FC[0]/CS[3]/PC[0]
SCIM2E
Output
1/0
FREEZE
SCIM2E
Output
1
HALT
SCIM2E
Input/Output
0
IPIPE
CPU32
Output
0
IFETCH
CPU32
Output
0
IRQ[7:1]
SCIM2E
Input
0
MA[2:0]
QADC64
Output
1
MISO
QSMCM
Input/Output
—
MOSI
QSMCM
Input/Output
—
PCS[3:0]
QSMCM
Input/Output
—
PQA[7:0]
QADC64
Input/Output
—
PQB[7:0]
QADC64
Input
—
QUOT
SCIM2E
Output
—
R/W
SCIM2E
Output
1/0
RESET
SCIM2E
Input/Output
0
RMC
SCIM2E
Output
0
RXD1, RXD2
QSMCM
Input
—
SCK
QSMCM
Input/Output
—
SIZ[1:0]
SCIM2E
Output
1
SS
QSMCM
Input
0
T2CLK
TPU3
Input
—
TP[15:0]
TPU3
Input/Output
—
TSC
SCIM2E
Input
0/1
TXD1, TXD2
QSMCM
Output
—
VDDSYN/MODCLK
SCIM2E
Input
—
EPEB01
CMFI
Input
—
XFC
SCIM2E
Input
—
XTAL1
SCIM2E
Output
—
NOTES:
1. These pins are 3 V level only.
MC68F375
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SIGNAL DESCRIPTIONS
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MOTOROLA
2-5
Freescale Semiconductor, Inc.
Table 2-5 Signal Functions
Signal Name
Address Bus
QADC64 Analog Input
AN[59:48]/[3:0]
QADC64 Analog Input
AN[z, y, x, w]
Analog MUX Inputs
Address Strobe
ANX[15:0]
AS
Function
24-bit address bus used by CPU32
Sixteen channel A/D converter analog input pins
Four input channels utilized when operating in multiplexed mode
Analog signal inputs multiplexed to the analog converters
Indicates that a valid address is on the address bus
Autovector
AVEC
Requests an automatic vector during interrupt acknowledge
Bus Error
BERR
Indicates that a bus error has occurred
Bus Grant
Bus Grant Acknowledge
Breakpoint
Freescale Semiconductor, Inc...
Mnemonic
ADDR[23:0]
Bus Request
System Clock Out
BG
Indicates that the MCU has relinquished the bus
BGACK
Indicates that an external device has assumed bus mastership
BKPT
Signals a hardware breakpoint to the CPU
BR
Indicates that an external device requires bus mastership
CLKOUT
Internal system clock
TOUCAN Receive Data
CNRX
CAN 2.0B Serial Data Input
TOUCAN Transmit Data
CNTX
CAN 2.0B Serial Data Output
Chip Selects
Boot Chip Select
CS[10:5], CS[3],
CS[0]
CSBOOT
Select external devices at programmed addresses
Chip select for external boot start-up ROM
Emulator Chip Select
CSE
Chip select for external port emulator
Module Chip Select
CSM
Chip select for external ROM emulator
CTM PWM
CPWM[8:5]
PWM channels which can also be used as general-purpose output
pins
CTM9 Double Action
Channel
CTD[10:9]
Bidirectional CTM9 double action timer channels
CTM9 Modulus Clock
CTM2C
CTM9 Single Action Channels
Data Bus
Data Strobe
Data and Size
Acknowledge
Development Serial In, Out,
Clock
QADC64 External Trigger
Crystal Oscillator
VCO Reference Mode Select
Function Codes
Freeze
CTM9 modulus counter clock input
CTS[20B - 14A]
DATA[15:0]
Bidirectional CTM9 single action timer channels
16-bit data bus
Read cycle — indicates that an external device should place valid
data on the data bus. Write cycle — indicates that valid data is on
the data bus.
DS
DSACK[1:0]
Provides asynchronous data transfers and dynamic bus sizing
DSI, DSO, DSCLK Serial I/O and clock for background debug mode
ETRIG[2:1]
When a scan queue is in external trigger mode, the corresponding
ETRIG pin is configured as a digital input and the software programmed I/O direction in the DDR is ignored.
EXTAL, XTAL
Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
FASTREF
Selects between FAST or SLOW reference modes
FC[2:0]
Identify processor state and current address space
FREEZE
Indicates that the CPU has acknowledged a breakpoint
Halt
HALT
Suspend external bus activity
Instruction Pipeline
IPIPE
Indicates instruction pipeline activity
MC68F375
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Freescale Semiconductor, Inc.
Table 2-5 Signal Functions (Continued)
Freescale Semiconductor, Inc...
Signal Name
Mnemonic
Function
Instruction Pipeline
IFETCH
Indicates instruction pipeline activity
Interrupt Request Level
IRQ[7:1]
Provides an interrupt priority level to the CPU
QADC64 Multiplexed Address
MA[2:0]
When external multiplexing is used, these pins provide the addresses to the external multiplexer
Master-In Slave-Out
MISO
Serial input to QSPI in master mode;
serial output from QSPI in slave mode
Master-Out Slave-In
MOSI
Serial output from QSPI in master mode;
serial input to QSPI in slave mode
Peripheral Chip Select
PCS[3:0]
QSPI Peripheral Chip Select
QADC64 Port A
PQA[7:0]
QADC64 port A analog inputs and I/O port PQA[7:0]
QADC64 Port B
PQB[7:0]
QADC64 port B analog inputs and input-only port PQB[7:0]
Quotient Out
Read/Write
Reset
Read-Modify-Write Cycle
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
TPU3 Clock
QUOT
RESET
System reset
RMC
Indicates an indivisible read-modify-write instruction
RXD1, RXD2
Serial input to the SCI
SCK
Clock output from QSPI in master mode; clock input from QSPI in
slave mode
SIZ[1:0]
Indicates the number of bytes remaining to be transferred during a
bus cycle
SS
Causes serial transmission when QSPI is in slave mode; chip-select in master mode
T2CLK
TP[15:0]
Three-State Control
TSC
Clock Mode Select
Indicates the direction of data transfer on the bus
R/W
TPU3 I/O Channels
SCI Transmit Data
Provides the quotient bit of the polynomial divider (test mode only)
TPU3 clock input
Bidirectional TPU3 channels
Places all output drivers in a high impedance state
TXD1, TXD2
Serial output from the SCI
VDDSYN/MODCLK Selects the source of the internal system clock
CMFI Block 0 Program/
Erase Enable
EPEB0
External Filter Capacitor
XFC
When asserted, allows CMFI block 0 to be programmed or erased.
Connection for external phase-locked loop filter capacitor
2.2 Pinout
The production MC68F375 will be bumped flip-chip and PBGA.
2.2.1 Pinout Diagram
The pad numbers for each pad/signal on the die are shown in Figure 2-1. Note that
the numbers and names correspond to the pad names and order on the die. The pin/
bump numbers on the PBGA and Bumped die may be different. The chip layout plan
is also shown in Figure 2-1.
MC68F375
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MOTOROLA
2-7
6K
DPTRAM
QSMCM
CTM9
TPU3
w/ AMUX
8K ROM
QADC64
256K
SRAM
SCIM2E CS
CPU32
SCIM2E
8K
PLLWXY
512 SRAM
512 SRAM
TOUCAN
512 SRAM
512 SRAM
CMFI FLASH EEPROM
SYSCINT1E
ANX15
ANX14
ANX13
ANX12
ANX11
ANX10
ANX9
ANX8
ANX7
ANX6
ANX5
ANX4
ANX3
ANX2
ANX1
ANX0
VRL
VRH
VSSA
VDDA
VPP
EPEB0
VSTBY
VSS
VDDH
ADDR18/PA7
ADDR17/PA6
ADDR16/PA5
ADDR15/PA4
ADDR14/PA3
ADDR13/PA2
ADDR12/PA1
ADDR11/PA0
ADDR10/PB7
ADDR9/PB6
VSS
VDDL
VSS
VDDH
ADDR8/PB5
ADDR7/PB4
ADDR6/PB3
ADDR5/PB2
ADDR4/PB1
ADDR3/PB0
ADDR2
ADDR1
ADDR0
VSS
VDDH
CNRX
CTD9
CTD10
CTS14A
CTS14B
CTS16A
CTS16B
VDDH
VSS
CTS18A
CTS18B
CTS20A
CTS20B
RXD1
TXD1
VDDF
VSS
RXD2
MOSI
MISO
TXD2
VDDH
VSS
PCS0/SS
SCK
PCS1
PCS2
PCS3
ADDR23/CS10/ECLK
ADDR22/CS9/PC6
ADDR21/CS8/PC5
ADDR20/CS7/PC4
ADDR19/CS6/PC3
VDDH
VSS
FC2/CS5/PC2
FC1/PC1
FC0/CS3/PC0
CSBOOT
BGACK/CSE
BG/CSM
BR/CS0
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
PE3/RMC
DS/PE4
VDDH
VSS
AS/PE5
SIZ0/PE6
CNTX
DATA15/PG7
DATA14/PG6
DATA13/PG5
DATA12/PG4
DATA11/PG3
DATA10/PG2
DATA9/PG1
DATA8/PG0
VSS
VDDH
DATA7/PH7
DATA6/PH6
DATA5/PH5
DATA4/PH4
DATA3/PH3
DATA2/PH2
DATA1/PH1
DATA0/PH0
VSS
VDDL
EXTAL
XTAL
VSSSYN
XFC
VDDSYN/MODCLK
VSS
VDDH
IPIPE/DSO
IFETCH/DSI
CLKOUT
FREEZE/QUOT
BKPT/DSCLK
TSC
RESET
HALT
BERR
IRQ7/PF7
IRQ6/PF6
VSS
VDDH
IRQ5/PF5
IRQ4/PF4
IRQ3/PF3
IRQ2/PF2
IRQ1/PF1
FASTREF/PF0
R/W
SIZ1/PE7
Freescale Semiconductor, Inc...
PQB7
PQB6
PQB5
PQB4
PQB3
PQB2
PQB1
PQB0
PQA7
PQA6
PQA5
PQA4
PQA3
PQA2
PQA1
PQA0
VDDH
VSS
VDDDPTRAM
VDDL
VSS
TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
VDDH
VSS
TP10
TP11
TP12
TP13
TP14
TP15
T2CLK
CTM2C
CTD3
CTD4
VDDH
VSS
CPWM5
CPWM6
CPWM7
CPWM8
Freescale Semiconductor, Inc.
Figure 2-1 MC68F375 Pad Map
MC68F375
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SIGNAL DESCRIPTIONS
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03This Product,
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MOTOROLA
2-8
REFERENCE MANUAL
MC68F375
VPP
ADDR17
/PA6
ADDR13
/PA2
ADDR9
/PB6
ADDR6
/PB3
ADDR4
/PB1
ANX2
VRH
EPEB0
ADDR16
/PA5
ADDR12
/PA1
ADDR8
/PB5
ADDR5
/PB2
ADDR3
/PB0
ADDR1
CNRX
VSS
H
J
K
L
M
N
P
R
SIGNAL DESCRIPTIONS
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T
U
CNTX
VSS
ADDR0
VRL
ANX3
ANX7
G
ANX10
ANX12
ANX6
ANX11
D
ANX14
F
ANX13
C
VSS
ANX9
ANX15
B
2
PQB7
E
VSS
A
1
4
5
DATA11
/PG3
DATA12
/PG4
DATA15
/PG7
DATA14
/PG6
DATA8
/PG0
DATA7
/PH7
DATA9
/PG1
DATA13
/PG5
VDDH
PQA5
PQA4
PQA6
PQA7
DATA10
/PG2
VDDL
ADDR10
/PB7
ADDR15
/PA4
VDDH
VSS
VDDA
ANX0
ANX4
VDDH
PQB0
PQB1
PQB2
PBQ3
VDDH
ADDR2
ADDR7
/PB4
ADDR11
/PA0
ADDR14
/PA3
ADDR18
/PA7
VSTBY
VSSA
ANX1
ANX5
ANX8
VDDH
PQB6
PQB4
PQB5
3
DATA4
/PH4
DATA3
/PH3
DATA5
/PH5
DATA6
/PH6
PQA0
PQA1
PQA2
PQA3
6
VSS
VSS
VSS
VDDL
TP0
TP1
9
VSS
VSS
VSS
TP4
TP3
TP5
TP6
10
VSS
VSS
VSS
TP8
TP7
TP9
TP10
11
TP12
TP11
TP13
TP14
EXTAL
N/C
DATA1
/PH1
DATA2
/PH2
XTAL
N/C
DATA0
/PH0
VDDL
N/C
VSSSYN
VSS
VSS
VDDSYN
/MODCLK
XFC
VSS
VDDH
IFETCH
/DSI
IPIPE/DSO
FREEZE
/QUOT
CLKOUT
Note: This pinout is a top down view.
VDDH
VSS
VSS
8
TP2
7
VDD
DPTRAM
12
HALT
RESET
TSC
BKPT
/DSCLK
N/C
TP15
T2CLK
CTM2C
Freescale Semiconductor, Inc...
13
IRQ5/PF5
IRQ6/PF6
IRQ7/PF7
BERR
N/C
CTD3
CTD4
CPWM5
14
ADDR22
/CS9/PC6
ADDR23
/CS10
/ECLK
IRQ3/PF3
IRQ4/PF4
IRQ2/PF2
VDDH
DSACK1
/PE1
FC0/CS3
/PC0
IRQ1/PF1
FASTREF
/PF0
VDDH
DS/PE4
DSACK0
/PE0
FC1 /PC1
N/C
PCS3
N/C
VSS
N/C
TXD2
VSS
VSS
N/C
VDDH
CTD10
CTD9
15
VDDH
RXD2
VDDF
VSS
VDDH
CPWM6
CPWM8
CPWM7
16
RW
VSS
SIZ0/PE6
VSS
SIZ1/PE7
AS/PE5
PE3/RMC AVEC/PE2
BG/CSM
CSBOOT
BGACK
/CSE
BR/CS0
ADDR19
/CS6/PC3
ADDR21
/CS8/PC5
PCS1
PCS0/SS
MISO
RXD1
CTS20A
CTS18A
CTS16B
CTS14B
VSS
17
FC2 /CS5
/PC2
ADDR20
/CS7/PC4
PCS2
SCK
MOSI
TXD1
CTS20B
CTS18B
CTS16A
VSS
CST14A
Freescale Semiconductor, Inc.
Note:
N/C = NO CONNECTION — these balls have no electrical connection inside the package.
Figure 2-2 MC68F375 Ball Map
MOTOROLA
2-9
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC68F375
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MOTOROLA
2-10
Freescale Semiconductor, Inc.
SECTION 3
CENTRAL PROCESSOR UNIT
Freescale Semiconductor, Inc...
The CPU32, the instruction processing module of the M68300 family, is based on the
industry-standard MC68000 processor. It has many features of the MC68010 and
MC68020, as well as unique features suited for high-performance controller applications. This section is an overview of the CPU32. For detailed information concerning
CPU operation, refer to the CPU32 Reference Manual (CPU32RM/AD).
3.1 General
Ease of programming is an important consideration in using a microcontroller. The
CPU32 instruction format reflects a philosophy emphasizing register-memory interaction. There are eight multifunction data registers and seven general-purpose
addressing registers.
All data resources are available to all operations requiring those resources. The data
registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand
lengths for all operations. Word and long-word operations support address manipulation. Although the program counter (PC) and stack pointers (SP) are special-purpose
registers, they are also available for most data addressing activities. Ease of program
checking and diagnosis is further enhanced by trace and trap capabilities at the
instruction level.
A block diagram of the CPU32 is shown in Figure 3-1. The major blocks operate in a
highly independent fashion that maximizes concurrency of operation while managing
the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and
control unit provide overall chip control, managing the internal buses, registers, and
functions of the execution unit.
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3-1
Freescale Semiconductor, Inc.
DECODE
BUFFER
STAGE
C
STAGE
B
STAGE
A
INSTRUCTION PIPELINE
Freescale Semiconductor, Inc...
CONTROL STORE
PROGRAM
COUNTER
SECTION
DATA
SECTION
CONTROL LOGIC
EXECUTION UNIT
MICROSEQUENCER AND CONTROL
WRITE PENDING
BUFFER
PREFETCH
CONTROLLER
MICROBUS
CONTROLLER
ADDRESS
BUS
BUS CONTROL
SIGNALS
DATA
BUS
1127A
Figure 3-1 CPU32 Block Diagram
3.2 CPU32 Registers
The CPU32 programming model consists of two groups of registers that correspond
to the user and supervisor privilege levels. User programs can use only the registers
of the user model. The supervisor programming model, which supplements the user
programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of the
MC68010 and later processors.
The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit
program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status
register, two alternate function code registers, and a 32-bit vector base register. Refer
to Figure 3-2 and Figure 3-3.
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3-2
Freescale Semiconductor, Inc.
31
16 15
8 7
0
D0
D1
D2
D3
DATA REGISTERS
D4
D5
D6
D7
Freescale Semiconductor, Inc...
31
16 15
8 7
0
A0
A1
A2
A3
ADDRESS REGISTERS
A4
A5
A6
31
16 15
8 7
0
A7’ (USP) USER STACK POINTER
31
0
PC
7
PROGRAM COUNTER
0
CCR CONDITION CODE REGISTER
CPU32 USER PROG MODEL
Figure 3-2 User Programming Model
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3-3
Freescale Semiconductor, Inc.
31
1615
0
A7 (SSP) SUPERVISOR STACK POINTER
15
87
0
(CCR)
31
SR
STATUS REGISTER
0
2
VBR
VECTOR BASE REGISTER
SFC
ALTERNATE FUNCTION
DFC
CODE REGISTERS
0
Freescale Semiconductor, Inc...
CPU32 SUPV PROG MODEL
Figure 3-3 Supervisor Programming Model Supplement
3.2.1 Data Registers
The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits and
addresses of 16 or 32 bits. The following data types are supported:
• Bits
• Packed Binary-Coded Decimal Digits
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
Each of data registers D7–D0 is 32 bits wide. Byte operands occupy the low-order 8
bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits.
When a data register is used as either a source or destination operand, only the appropriate low-order byte or word (in byte or word operations, respectively) is used or
changed; the remaining high-order portion is unaffected. The least significant bit (LSB)
of a long-word integer is addressed as bit zero, and the most significant bit (MSB) is
addressed as bit 31. Figure 3-4 shows the organization of various types of data in the
data registers.
Quad-word data consists of two long words and represents the product of 32-bit multiply or the dividend of 32-bit divide operations (signed and unsigned). Quad-words
may be organized in any two data registers without restrictions on order or pairing.
There are no explicit instructions for the management of this data type, although the
MOVEM instruction can be used to move a quad-word into or out of the registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form. CPU32
BCD instructions use a format in which a byte contains two digits. The four LSB contain the least significant digit, and the four MSB contain the most significant digit. The
ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single
byte.
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3-4
Freescale Semiconductor, Inc.
31
1
30
MSB
0
LSB
BYTE
31
24 23
1615
87
0
HIGH-ORDER BYTE MIDDLE HIGH BYTE MIDDLE LOW BYTE LOW-ORDER BYTE
WORD
31
1615
Freescale Semiconductor, Inc...
HIGH-ORDER WORD
0
LOW-ORDER WORD
LONG WORD
31
0
LONG WORD
QUAD-WORD
63
62
32
MSB
HIGH-ORDER LONG WORD
1
31
LOW-ORDER LONG WORD
0
LSB
CPU32 DATA ORG
Figure 3-4 Data Organization in Data Registers
3.2.2 Address Registers
Each address register and stack pointer is 32 bits wide and holds a 32-bit address.
Address registers cannot be used for byte-sized operands. Therefore, when an
address register is used as a source operand, either the low-order word or the entire
long-word operand is used, depending upon the operation size. When an address register is used as the destination, the entire register is affected, regardless of the operation size. If the source operand is a word size, the operand is sign-extended to 32 bits.
Address registers are used primarily for addresses and to support address computation. The instruction set includes instructions that add to, subtract from, compare, and
move the contents of address registers. Figure 3-5 shows the organization of
addresses in address registers.
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31
1615
SIGN EXTENDED
0
16-BIT ADDRESS OPERAND
31
0
FULL 32-BIT ADDRESS OPERAND
CPU32 ADDR ORG
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Figure 3-5 Address Organization in Address Registers
3.2.3 Program Counter
The PC contains the address of the next instruction to be executed by the CPU32.
During instruction execution and exception processing, the processor automatically
increments the contents of the PC or places a new value in the PC as appropriate.
3.2.4 Control Registers
The control registers described in this section contain control information for supervisor functions and vary in size. With the exception of the condition code register (the
user portion of the status register), the control registers are accessed only by instructions at the supervisor privilege level.
3.2.4.1 Status Register
The status register (SR) stores the processor status. It contains the condition codes
that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative (N), zero
(Z), overflow (V), and carry (C). The user (low-order) byte containing the condition
codes is the only portion of the SR information available at the user privilege level; it
is referenced as the condition code register (CCR) in user programs.
At the supervisor privilege level, software can access the full status register. The upper
byte of this register includes the interrupt priority (IP) mask (three bits), two bits for
placing the processor in one of two tracing modes or disabling tracing, and the supervisor/user bit for placing the processor at the desired privilege level.
Undefined bits in the status register are reserved by Motorola for future definition. The
undefined bits are read as zeros and should be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations, but for all CCR operations,
the upper byte is read as all zeros and is ignored when written, regardless of privilege
level.
Refer to APPENDIX A INTERNAL MEMORY MAP for bit/field definitions and a diagram of the status register.
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3.2.4.2 Alternate Function Code Registers
Alternate function code registers (SFC and DFC) contain 3-bit function codes. Function codes can be considered extensions of the 24-bit linear address that optionally
provide as many as eight 16-Mbyte address spaces. The processor automatically generates function codes to select address spaces for data and programs at the user and
supervisor privilege levels and to select a CPU address space used for processor
functions (such as breakpoint and interrupt acknowledge cycles).
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Registers SFC and DFC are used by the MOVES instruction to specify explicitly the
function codes of the memory address. The MOVEC instruction is used to transfer values to and from the alternate function code registers. This is a long-word transfer; the
upper 29 bits are read as zeros and are ignored when written.
3.2.5 Vector Base Register (VBR)
The VBR contains the base address of the 1024-byte exception vector table, consisting of 256 exception vectors. Exception vectors contain the memory addresses of
routines that begin execution at the completion of exception processing. More
information on the VBR and exception processing can be found in 3.9 Exception
Processing.
3.3 Memory Organization
Memory is organized on a byte-addressable basis in which lower addresses correspond to higher order bytes. For example, the address N of a long-word data item
corresponds to the address of the most significant byte of the highest order word. The
address of the most significant byte of the low-order word is N + 2, and the address of
the least significant byte of the long word is N + 3. The CPU32 requires long-word and
word data and all instructions to be aligned on word boundaries. Refer to Figure 3-6.
If this does not happen, an exception will occur when the CPU32 accesses the
misaligned instruction or data. Data misalignment is not supported.
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BIT DATA
1 BYTE = 8 BITS
7
6
5
4
3
2
1
0
1 BYTE = 8 BITS
15
8 7
MSB
BYTE 0
0
LSB
BYTE 1
BYTE 2
BYTE 3
WORD = 16 BITS
15
0
WORD
0
WORD 0
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MSB
LSB
WORD 1
WORD 2
LONG WORD = 32 BITS
0
15
MSB
HIGH ORDER
LONG WORD 0
LOW ORDER
LSB
LONG WORD 1
LONG WORD 2
ADDRESS 1
ADDRESS = 32 BITS
15
0
MSB
HIGH ORDER
ADDRESS 0
LOW ORDER
LSB
ADDRESS 1
ADDRESS 2
MSB = Most Significant Bit
LSB = Least Significant Bit
DECIMAL DATA
15
MSD
12 11
BCD DIGITS = 1 BYTE
8 7
BCD 0
BCD 1
BCD 4
BCD 5
LSD
4 3
0
BCD 2
BCD 3
BCD 6
BCD 7
MSD = Most Significant Digit
LSD = Least Significant Digit
1125A
Figure 3-6 Memory Operand Addressing
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3.4 Virtual Memory
The full addressing range of the CPU32 on the MC68F375 is 16 Mbytes in each of
eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16 Mbytes of memory available
to each user program by using virtual memory techniques.
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A system that supports virtual memory has a limited amount of high-speed physical
memory that can be accessed directly by the processor and maintains an image of a
much larger virtual memory on a secondary storage device. When the processor
attempts to access a location in the virtual memory map that is not resident in physical
memory, a page fault occurs. The access to that location is temporarily suspended
while the necessary data is fetched from secondary storage and placed in physical
memory. The suspended access is then restarted or continued.
The CPU32 uses instruction restart, which requires that only a small portion of the
internal machine state be saved. After correcting the fault, the machine state is
restored, and the instruction is fetched and started again. This process is completely
transparent to the application program.
3.5 Addressing Modes
Addressing in the CPU32 is register-oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory. There is no
need for extra instructions to store register contents in memory.
There are seven basic addressing modes:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Absolute
• Immediate
The register indirect addressing modes include postincrement, predecrement, and offset capability. The program counter indirect mode also has index and offset
capabilities. In addition to these addressing modes, many instructions implicitly specify
the use of the status register, stack pointer, and/or program counter.
3.6 Processing States
The processor is always in one of four processing states: normal, exception, halted, or
background. The normal processing state is associated with instruction execution; the
bus is used to fetch instructions and operands and to store results.
The exception processing state is associated with interrupts, trap instructions, tracing,
and other exception conditions. The exception may be internally generated explicitly
by an instruction or by an unusual condition arising during the execution of an instruc-
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tion. Exception processing can be forced externally by an interrupt, a bus error, or a
reset.
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The background processing state is initiated by breakpoints, execution of special
instructions, or a double bus fault. Background processing is enabled by pulling BKPT
low during RESET. Background processing allows interactive debugging of the system via a simple serial interface.
3.7 Privilege Levels
The processor operates at one of two levels of privilege: user or supervisor. Not all
instructions are permitted to execute at the user level. All instructions are available at
the supervisor level. Effective use of privilege level can protect system resources from
uncontrolled access. The state of the S bit in the status register determines the privilege level and whether the user stack pointer (USP) or supervisor stack pointer (SSP)
is used for stack operations.
3.8 Instructions
The CPU32 instruction set is summarized in Table 3-2. The instruction set of the
CPU32 is very similar to that of the MC68020. Two new instructions have been added
to facilitate controller applications: low-power stop (LPSTOP) and table lookup and
interpolate (TBLS, TBLSN, TBLU, TBLUN).
Table 3-1 shows the MC68020 instructions that are not implemented on the CPU32.
Table 3-1 Unimplemented MC68020 Instructions
Instruction
Description
BFxx
Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST)
CALLM, RTM
CAS, CAS2
cpxxx
PACK, UNPK
Memory
Call Module, Return Module
Compare and Swap (Read-Modify-Write Instructions)
Coprocessor Instructions (cpBcc, cpDBcc, cpGEN)
Pack, Unpack BCD Instructions
Memory Indirect Addressing Modes
The CPU32 traps on unimplemented instructions or illegal effective addressing
modes, allowing user-supplied code to emulate unimplemented capabilities or to
define special purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core
enhancements.
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Table 3-2 Instruction Set Summary
Instruction
Operand
Syntax
Operand
Size
ABCD
Dn, Dn
− (An), − (An)
8
8
ADD
Dn,
, Dn
8, 16, 32
8, 16, 32
Source + Destination ⇒ Destination
ADDA
, An
16, 32
Source + Destination ⇒ Destination
ADDI
#,
8, 16, 32
Immediate data + Destination ⇒ Destination
ADDQ
# ,
8, 16, 32
Immediate data + Destination ⇒ Destination
ADDX
Dn, Dn
− (An), − (An)
8, 16, 32
8, 16, 32
Source + Destination + X ⇒ Destination
AND
, Dn
Dn,
8, 16, 32
8, 16, 32
Source • Destination ⇒ Destination
ANDI
# ,
8, 16, 32
Data • Destination ⇒ Destination
ANDI to CCR
# ,
CCR
8
Source • CCR ⇒ CCR
ANDI to SR11
# , SR
16
Source • SR ⇒ SR
ASL
Dn, Dn
# , Dn
8, 16, 32
8, 16, 32
16
ASR
Dn, Dn
# , Dn
8, 16, 32
8, 16, 32
16
Bcc
label
8, 16, 32
BCHG
Dn,
# ,
8, 32
8, 32
BCLR
Dn,
# ,
8, 32
8, 32
( 〈 bit number〉 of destination ) ⇒ Z;
0 ⇒ bit of destination
BGND
none
none
If background mode enabled, then enter background mode, else format/vector ⇒ − (SSP);
PC ⇒ − (SSP); SR ⇒ − (SSP); (vector) ⇒ PC
BKPT
#
none
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal instruction
BRA
label
8, 16, 32
BSET
Dn,
# ,
8, 32
8, 32
BSR
label
8, 16, 32
BTST
Dn,
# ,
8, 32
8, 32
( 〈 bit number〉 of destination ) ⇒ Z
CHK
, Dn
16, 32
If Dn < 0 or Dn > (ea), then CHK exception
CHK2
, Rn
8, 16, 32
If Rn < lower bound or Rn > upper bound, then
CHK exception
CLR
8, 16, 32
0 ⇒ Destination
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Description
Source10 + Destination10 + X ⇒ Destination
X/C
0
X/C
If condition true, then PC + d ⇒ PC
( 〈 bit number〉 of destination ) ⇒ Z ⇒ bit of destination
PC + d ⇒ PC
( 〈 bit number〉 of destination ) ⇒ Z;
1 ⇒ bit of destination
SP − 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC
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Table 3-2 Instruction Set Summary (Continued)
Instruction
Operand
Syntax
Operand
Size
Description
CMP
, Dn
8, 16, 32
(Destination − Source), CCR shows results
CMPA
, An
16, 32
(Destination − Source), CCR shows results
CMPI
# ,
8, 16, 32
(Destination − Data), CCR shows results
CMPM
(An) +, (An) +
8, 16, 32
(Destination − Source), CCR shows results
CMP2
, Rn
8, 16, 32
16
Lower bound ≤ Rn ≤ Upper bound, CCR shows result
If condition false, then Dn − 1 ⇒ PC;
if Dn ≠ (− 1), then PC + d ⇒ PC
DBcc
Dn, label
DIVS/DIVU
, Dn
32/16 ⇒ 16 : Destination / Source ⇒ Destination
16
(signed or unsigned)
DIVSL/DIVUL
, Dr : Dq
, Dq
, Dr : Dq
64/32 ⇒ 32 :
32
Destination / Source ⇒ Destination
32/32 ⇒ 32
(signed or unsigned)
32/32 ⇒ 32 :
32
EOR
Dn,
8, 16, 32
Source ⊕ Destination ⇒ Destination
EORI
# ,
8, 16, 32
Data ⊕ Destination ⇒ Destination
EORI to CCR
# ,
CCR
8
Source ⊕ CCR ⇒ CCR
EORI to SR1
# , SR
16
Source ⊕ SR ⇒ SR
EXG
Rn, Rn
32
Rn ⇒ Rn
EXT
Dn
Dn
8 ⇒ 16
16 ⇒ 32
Sign extended Destination ⇒ Destination
EXTB
Dn
8 ⇒ 32
Sign extended Destination ⇒ Destination
ILLEGAL
none
none
SSP − 2 ⇒ SSP; vector offset ⇒ (SSP);
SSP − 4 ⇒ SSP; PC ⇒ (SSP);
SSP − 2 ⇒ SSP; SR ⇒ (SSP);
Illegal instruction vector address ⇒ PC
JMP
none
Destination ⇒ PC
JSR
none
SP − 4 ⇒ SP; PC ⇒ (SP); destination ⇒ PC
LEA
, An
32
LINK
⇒ An
SP − 4 ⇒ SP, An ⇒ (SP); SP ⇒ An, SP + d ⇒ SP
An, # d
16, 32
#
16
LSL
Dn, Dn
# , Dn
8, 16, 32
8, 16, 32
16
LSR
Dn, Dn
#, Dn
8, 16, 32
8, 16, 32
16
MOVE
,
8, 16, 32
MOVEA
, An
16, 32 ⇒ 32
MOVEA1
USP, An
An, USP
32
32
USP ⇒ An
An ⇒ USP
MOVE from
CCR
CCR,
16
CCR ⇒ Destination
MOVE to CCR
, CCR
16
Source ⇒ CCR
LPSTOP
1
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Data ⇒ SR; interrupt mask ⇒ EBI; STOP
X/C
0
0
X/C
Source ⇒ Destination
Source ⇒ Destination
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Table 3-2 Instruction Set Summary (Continued)
Instruction
Operand
Syntax
Operand
Size
MOVE from
SR1
SR,
16
SR ⇒ Destination
MOVE to SR1
, SR
16
Source ⇒ SR
MOVE USP1
USP, An
An, USP
32
32
USP ⇒ An
An ⇒ USP
MOVEC1
Rc, Rn
Rn, Rc
32
32
Rc ⇒ Rn
Rn ⇒ Rc
MOVEM
list,
, list
16, 32
16, 32 ⇒ 32
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16, 32
(An + d) ⇒ Dn [31 : 24]; (An + d + 2) ⇒ Dn [23 : 16];
(An + d + 4) ⇒ Dn [15 : 8]; (An + d + 6) ⇒ Dn [7 : 0]
(d16, An), Dn
MOVEQ
#, Dn
MOVES1
Rn,
, Rn
MULS/MULU
Listed registers ⇒ Destination
Source ⇒ Listed registers
Dn [31 : 24] ⇒ (An + d); Dn [23 : 16] ⇒ (An + d + 2);
Dn [15 : 8] ⇒ (An + d + 4); Dn [7 : 0] ⇒ (An + d + 6)
Dn, (d16, An)
MOVEP
Description
8 ⇒ 32
8, 16, 32
Immediate data ⇒ Destination
Rn ⇒ Destination using DFC
Source using SFC ⇒ Rn
, Dn
16 ∗ 16 ⇒ 32
Source ∗ Destination ⇒ Destination
, Dl
32 ∗ 32 ⇒ 32
(signed or unsigned)
, Dh : Dl 32 ∗ 32 ⇒ 64
NBCD
8
8
NEG
8, 16, 32
0 − Destination ⇒ Destination
NEGX
8, 16, 32
0 − Destination − X ⇒ Destination
0 − Destination10 − X ⇒ Destination
PC + 2 ⇒ PC
NOP
none
none
NOT
8, 16, 32
Destination ⇒ Destination
OR
, Dn
Dn,
8, 16, 32
8, 16, 32
Source + Destination ⇒ Destination
ORI
#,
8, 16, 32
Data + Destination ⇒ Destination
ORI to CCR
#,
CCR
16
Source + CCR ⇒ SR
ORI to SR1
#, SR
16
Source ; SR ⇒ SR
PEA
32
SP − 4 ⇒ SP; ⇒ SP
none
none
ROL
Dn, Dn
#, Dn
8, 16, 32
8, 16, 32
16
ROR
Dn, Dn
#, Dn
8, 16, 32
8, 16, 32
16
ROXL
Dn, Dn
#, Dn
8, 16, 32
8, 16, 32
16
ROXR
Dn, Dn
#, Dn
8, 16, 32
8, 16, 32
16
RTD
#d
16
RESET
1
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Assert RESET line
C
C
C
X
X
C
(SP) ⇒ PC; SP + 4 + d ⇒ SP
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Table 3-2 Instruction Set Summary (Continued)
Instruction
Operand
Syntax
Operand
Size
RTE1
none
none
(SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP;
Restore stack according to format
RTR
none
none
(SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP
RTS
none
none
(SP) ⇒ PC; SP + 4 ⇒ SP
SBCD
Dn, Dn
− (An), − (An)
8
8
Destination10 − Source10 − X ⇒ Destination
Scc
8
If condition true, then destination bits are set to one;
else, destination bits are cleared to zero
STOP1
#
16
Data ⇒ SR; STOP
SUB
, Dn
Dn,
8, 16, 32
Destination − Source ⇒ Destination
SUBA
, An
16, 32
Destination − Source ⇒ Destination
SUBI
#,
8, 16, 32
Destination − Data ⇒ Destination
SUBQ
#,
8, 16, 32
Destination − Data ⇒ Destination
SUBX
Dn, Dn
− (An), − (An)
8, 16, 32
8, 16, 32
Destination − Source − X ⇒ Destination
SWAP
Dn
16
TAS
8
TBLS/TBLU
, Dn
Dym : Dyn,
Dn
8, 16, 32
Dyn − Dym ⇒ Temp
(Temp ∗ Dn [7 : 0]) ⇒ Temp
(Dym ∗ 256) + Temp ⇒ Dn
TBLSN/TBLUN
, Dn
Dym : Dyn,
Dn
8, 16, 32
Dyn − Dym ⇒ Temp
(Temp ∗ Dn [7 : 0]) / 256 ⇒ Temp
Dym + Temp ⇒ Dn
TRAP
#
none
SSP − 2 ⇒ SSP; format/vector offset ⇒ (SSP);
SSP − 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);
vector address ⇒ PC
TRAPcc
none
#
none
16, 32
If cc true, then TRAP exception
If V set, then overflow TRAP exception
TRAPV
none
none
TST
8, 16, 32
UNLK
An
32
Description
MSW
LSW
Destination Tested Condition Codes bit 7 of
Destination
Source − 0, to set condition codes
An ⇒ SP; (SP) ⇒ An, SP + 4 ⇒ SP
NOTES:
1. Privileged instruction.
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3.8.1 M68000 Family Compatibility
It is the philosophy of the M68000 family that all user-mode programs can execute
unchanged on future derivatives of the M68000 family. Supervisor-mode programs
and exception handlers should require only minimal alteration.
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The CPU32 can be thought of as an intermediate member of the M68000 Family.
Object code from an MC68000 or MC68010 may be executed on the CPU32. Many of
the instruction and addressing mode extensions of the MC68020 are also supported.
Refer to the CPU32 Reference Manual (CPU32RM/AD) for a detailed comparison of
the CPU32 and MC68020 instruction set.
3.8.2 Special Control Instructions
Low-power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have
been added to the MC68000 instruction set for use in controller applications.
3.8.2.1 Low-Power Stop (LPSTOP)
In applications where power consumption is a consideration, the CPU32 forces the
device into a low-power standby mode when immediate processing is not required.
The low-power stop mode is entered by executing the LPSTOP instruction. The processor remains in this mode until an unmasked interrupt or reset occurs.
3.8.2.2 Table Lookup and Interpolate (TBL)
To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. Storage of many data points can require
an inordinate amount of memory. The table lookup instruction requires that only a
sample of data points be stored, reducing memory requirements. The TBL instruction
recovers intermediate values using linear interpolation. Results can be rounded with a
round-to-nearest algorithm.
3.8.2.3 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode
is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction. Figure 3-7 shows the
required form of an instruction loop for the processor to enter loop mode.
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ONE WORD INSTRUCTION
DBCC
DBCC DISPLACEMENT
0xFFFC = – 4
1126A
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Figure 3-7 Loop Mode Instruction Sequence
The loop mode is entered when the DBcc instruction is executed, and the loop displacement is –4. Once in loop mode, the processor performs only the data cycles
associated with the instruction and suppresses all instruction fetches. The termination
condition and count are checked after each execution of the data operations of the
looped instruction. The CPU32 automatically exits the loop mode on interrupts or other
exceptions. All single word instructions that do not cause a change of flow can be
looped.
3.9 Exception Processing
An exception is a special condition that preempts normal processing. Exception processing is the transition from normal mode program execution to execution of a routine
that deals with an exception.
3.9.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The vector
base register (VBR) contains the base address of a 1024-byte exception vector table
which consists of 256 exception vectors. Sixty-four vectors are defined by the
processor and 192 vectors are reserved for user definition as interrupt vectors. Except
for the reset vector each vector in the table is one long word in length. The reset vector
is two long words in length. Refer to Table 3-3 for information on vector assignment.
CAUTION
Because there is no protection on the 64 processor-defined vectors,
external devices can access vectors reserved for internal purposes.
This practice is strongly discouraged.
All exception vectors, except the reset vector and stack pointer, are located in supervisor data space. The reset vector and stack pointer are located in supervisor program
space. Only the initial reset vector and stack pointer are fixed in the processor memory
map. When initialization is complete, there are no fixed assignments. Since the VBR
stores the vector table base address, the table can be located anywhere in memory.
It can also be dynamically relocated for each task executed by an operating system.
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Table 3-3 Exception Vector Assignments
Vector Offset
Vector
Number
Dec
Hex
Space
0
0
000
SP
Reset: initial stack pointer
1
4
004
SP
Reset: initial program counter
Assignment
2
8
008
SD
Bus error
3
12
00C
SD
Address error
4
16
010
SD
Illegal instruction
5
20
014
SD
Zero division
6
24
018
SD
CHK, CHK2 instructions
7
28
01C
SD
TRAPcc, TRAPV instructions
8
32
020
SD
Privilege violation
9
36
024
SD
Trace
10
40
028
SD
Line 1010 emulator
11
44
02C
SD
Line 1111 emulator
12
48
030
SD
Hardware breakpoint
13
52
034
SD
(Reserved, coprocessor protocol violation)
14
56
038
SD
Format error and uninitialized interrupt
15
60
03C
SD
Format error and uninitialized interrupt
16–23
64
92
040
05C
SD
(Unassigned, reserved)
24
96
060
SD
Spurious interrupt
25
100
064
SD
Level 1 interrupt autovector
26
104
068
SD
Level 2 interrupt autovector
27
108
06C
SD
Level 3 interrupt autovector
28
112
070
SD
Level 4 interrupt autovector
29
116
074
SD
Level 5 interrupt autovector
30
120
078
SD
Level 6 interrupt autovector
31
124
07C
SD
Level 7 interrupt autovector
32–47
128
188
080
0BC
SD
Trap instruction vectors (0–15)
48–58
192
232
0C0
0E8
SD
(Reserved, coprocessor)
59–63
236
252
0EC
0FC
SD
(Unassigned, reserved)
64–255
256
1020
100
3FC
SD
User defined vectors (192)
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are
obtained from an external device; others are supplied by the processor. The processor
multiplies the vector number by four to calculate vector offset, then adds the offset to
the contents of the VBR. The sum is the memory address of the vector.
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3.9.2 Types of Exceptions
An exception can be caused by internal or external events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal execution. Illegal instructions, instruction fetches from odd
addresses, word or long-word operand accesses from odd addresses, and privilege
violations also cause internal exceptions.
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Sources of external exception include interrupts, breakpoints, bus errors, and reset
requests. Interrupts are peripheral device requests for processor action. Breakpoints
are used to support development equipment. Bus error and reset are used for access
control and processor restart.
3.9.3 Exception Processing Sequence
For all exceptions other than a reset exception, exception processing occurs in the following sequence. Refer to 4.7 Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the status
register. After the copy is made, the processor state bits in the status register are
changed — the S bit is set, establishing supervisor access level, and bits T1 and T0
are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority
mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from
CPU space 0xF (the bus cycle is an interrupt acknowledge). For all other exceptions,
internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and
placed on the supervisor stack. All stack frames contain copies of the status register
and the program counter for use by RTE. The type of exception and the context in
which the exception occurs determine what other information is stored in the stack
frame.
Finally, the processor prepares to resume normal execution of instructions. The
exception vector offset is determined by multiplying the vector number by four, and the
offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the program counter. If no other
exception is pending, the processor will resume normal execution at the new address
in the PC.
3.10 Development Support
The following features have been implemented on the CPU32 to enhance the instrumentation and development environment:
• M68000 Family Development Support
• Background Debug Mode
• Deterministic Opcode Tracking
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• Hardware Breakpoints
3.10.1 M68000 Family Development Support
All M68000 Family members include features to facilitate applications development.
These features include the following:
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Trace on Instruction Execution — M68000 Family processors include an instructionby-instruction tracing facility as an aid to program development. The MC68020,
MC68030, MC68040, and CPU32 also allow tracing only of those instructions causing
a change in program flow. In the trace mode, a trace exception is generated after an
instruction is executed, allowing a debugger program to monitor the execution of a program under test.
Breakpoint Instruction — An emulator may insert software breakpoints into the target
code to indicate when a breakpoint has occurred. On the MC68010, MC68020,
MC68030, and CPU32, this function is provided via illegal instructions, 0x4848–
0x484F, to serve as breakpoint instructions.
Unimplemented Instruction Emulation — During instruction execution, when an
attempt is made to execute an illegal instruction, an illegal instruction exception
occurs. Unimplemented instructions (F-line, A-line, . . .) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software.
3.10.2 Background Debug Mode
Microcomputer systems generally provide a debugger, implemented in software, for
system analysis at the lowest level. The background debug mode (BDM) on the
CPU32 is unique in that the debugger has been implemented in CPU microcode.
BDM incorporates a full set of debugging options: registers can be viewed or altered,
memory can be read or written to, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common
setup (refer to Figure 3-8), emulator hardware replaces the target system processor.
A complex, expensive pod-and-cable interface provides a communication path
between the target system and the emulator.
By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for
incircuit emulation. The processor remains in the target system (refer to Figure 3-9)
and the interface is simplified. The BSA monitors target processor operation and the
on-chip debugger controls the operating environment. Emulation is much “closer” to
target hardware, and many interfacing problems (for example, limitations on high-frequency operation, AC and DC parametric mismatches, and restrictions on cable
length) are minimized.
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TARGET
SYSTEM
IN-CIRCUIT
EMULATOR
TARGET
MCU
1128A
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Figure 3-8 Common In-Circuit Emulator Diagram
TARGET
SYSTEM
BUS STATE
ANALYZER
TARGET
MCU
1129A
Figure 3-9 Bus State Analyzer Configuration
3.10.3 Enabling BDM
Accidentally entering BDM in a non-development environment can lock up the CPU32
when the serial command interface is not available. For this reason, BDM is enabled
during reset via the breakpoint (BKPT) signal.
BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET.
BDM remains enabled until the next system reset. A high BKPT signal on the trailing
edge of RESET disables BDM. BKPT is latched again on each rising transition of
RESET. BKPT is synchronized internally, and must be held low for at least two clock
cycles prior to negation of RESET.
BDM enable logic must be designed with special care. If hold time on BKPT (after the
trailing edge of RESET) extends into the first bus cycle following reset, the bus cycle
could inadvertently be tagged with a breakpoint. Refer to the SCIM Reference Manual
(SCIMRM/AD) for timing information.
3.10.4 BDM Sources
Once BDM is enabled, any of several sources can cause the transition from normal
mode to BDM. These sources include external breakpoint hardware, the BGND
instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not
enabled when an exception condition occurs, the exception is processed normally.
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Table 3-4 summarizes the processing of each source for both enabled and disabled
cases. As shown in Table 3-4, the BKPT instruction never causes a transition into
BDM.
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Table 3-4 BDM Source Summary
Source
BDM Enabled
BDM Disabled
BKPT
Background
Breakpoint Exception
Double Bus Fault
Background
Halted
BGND Instruction
Background
Illegal Instruction
BKPT Instruction
Opcode Substitution/
Illegal Instruction
Opcode Substitution/
Illegal Instruction
3.10.4.1 External BKPT Signal
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM
is disabled, a breakpoint exception (vector 0x0C) is acknowledged. The BKPT input
has the same timing relationship to the data strobe trailing edge as does read cycle
data. There is no breakpoint acknowledge bus cycle when BDM is entered.
3.10.4.2 BGND Instruction
An illegal instruction, 0x4AFA, is reserved for use by development tools. The CPU32
defines 0x4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is
disabled, an illegal instruction trap is acknowledged.
3.10.4.3 Double Bus Fault
The CPU32 normally treats a double bus fault, (an exception that occurs while stacking for another exception) as a catastrophic system error and halts. When this
condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected. In BDM, the fault can be temporarily
bypassed, so that the origin of the fault can be isolated and eliminated.
3.10.4.4 Peripheral Breakpoints
CPU32 peripheral breakpoints are implemented in the same way as external breakpoints — peripherals request breakpoints by asserting the BKPT signal. Consult the
appropriate peripheral user’s manual for additional details on the generation of
peripheral breakpoints.
3.10.5 Entering BDM
When the processor detects a breakpoint or a double bus fault, or decodes a BGND
instruction, it suspends instruction execution and asserts the FREEZE output. This is
the first indication that the processor has entered BDM. Once FREEZE has been
asserted, the CPU enables the serial communication hardware and awaits a
command.
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The CPU writes a unique value indicating the source of BDM transition into temporary
register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP
and determine the source (refer to Table 3-5) by issuing a read system register command (RSREG). ATEMP is used in most debugger commands for temporary storage.
It is imperative that the RSREG command be the first command issued after transition
into BDM.
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Table 3-5 Polling the BDM Entry Source
Source
ATEMP[31:16]
ATEMP[15:0]
Double Bus Fault
SSW1
0xFFFF
BGND Instruction
0x0000
0x0001
Hardware Breakpoint
0x0000
0x0000
NOTES:
1. Special status word (SSW) is described in detail in the CPU32 Reference
Manual (CPU32RM/AD).
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence
is distinguished by a value of 0xFFFFFFFF in the current instruction PC. At no other
time will the processor write an odd value into this register.
3.10.6 BDM Commands
BDM commands consist of one 16-bit operation word and can include one or more 16bit extension words. Each incoming word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the
command is complete. Result operands are loaded into the output shift register to be
shifted out as the next command is read. This process is repeated for each command
until the CPU returns to normal operating mode. Table 3-6 is a summary of background mode commands.
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Table 3-6 Background Mode Command Summary
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Command
Mnemonic
Description
Read D/A Register
RDREG/RAREG
Read the selected address or data register and return the
results via the serial interface.
Write D/A Register
WDREG/WAREG
The data operand is written to the specified address or data
register.
Read System Register
RSREG
The specified system control register is read. All registers that
can be read in supervisor mode can be read in background
mode.
Write System Register
WSREG
The operand data is written into the specified system control
register.
Read Memory Location
READ
Read the sized data at the memory location specified by the
long-word address. The source function code register (SFC)
determines the address space accessed.
Write Memory Location
WRITE
Write the operand data to the memory location specified by the
long-word address. The destination function code (DFC) register determines the address space accessed.
DUMP
Used in conjunction with the READ command to dump large
blocks of memory. An initial READ is executed to set up the
starting address of the block and retrieve the first result. Subsequent operands are retrieved with the DUMP command.
Fill Memory Block
FILL
Used in conjunction with the WRITE command to fill large
blocks of memory. An initial WRITE is executed to set up the
starting address of the block and supply the first operand. Subsequent operands are written with the FILL command.
Resume Execution
GO
The pipe is flushed and re-filled before resuming instruction
execution at the current PC.
Patch User Code
CALL
Current program counter is stacked at the location of the current stack pointer. Instruction execution begins at user patch
code.
Reset Peripherals
RST
Asserts RESET for 512 clock cycles. The CPU is not reset by
this command. Synonymous with the CPU RESET instruction.
No Operation
NOP
NOP performs no operation and may be used as a null command.
Dump Memory Block
3.10.7 Background Mode Registers
BDM processing uses three special purpose registers to keep track of program context
during development. A description of each follows.
3.10.7.1 Fault Address Register (FAR)
The FAR contains the address of the faulting bus cycle immediately following a bus or
address error. This address remains available until overwritten by a subsequent bus
cycle. Following a double bus fault, the FAR contains the address of the last bus cycle.
The address of the first fault (if there was one) is not visible to the user.
3.10.7.2 Return Program Counter (RPC)
The RPC points to the location where fetching will commence after transition from
background mode to normal mode. This register should be accessed to change the
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flow of a program under development. Changing the RPC to an odd value will cause
an address error when normal mode prefetching begins.
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3.10.7.3 Current Instruction Program Counter (PCC)
The PCC holds a pointer to the first word of the last instruction executed prior to transition into background mode. Due to instruction pipelining, the instruction pointed to
may not be the instruction which caused the transition. An example is a breakpoint on
a released write. The bus cycle may overlap as many as two subsequent instructions
before stalling the instruction sequencer. A breakpoint asserted during this cycle will
not be acknowledged until the end of the instruction executing at completion of the bus
cycle. PCC will contain 0x00000001 if BDM is entered via a double bus fault immediately out of reset.
3.10.8 Returning from BDM
BDM is terminated when a resume execution (GO) or call user code (CALL) command
is received. Both GO and CALL flush the instruction pipeline and refetch instructions
from the location pointed to by the RPC.
The return PC and the memory space referred to by the status register SUPV bit reflect
any changes made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals
revert to IPIPE/IFETCH functionality.
3.10.9 Serial Interface
Communication with the CPU32 during BDM occurs via a dedicated serial interface,
which shares pins with other development features. Figure 3-10 is a block diagram of
the interface. The BKPT signal becomes the serial clock (DSCLK); serial input data
(DSI) is received on IFETCH, and serial output data (DSO) is transmitted on IPIPE.
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INSTRUCTION
REGISTER BUS
CPU
DEVELOPMENT SYSTEM
DATA
16
16
0
RCV DATA LATCH
COMMAND LATCH
DSI
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
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DSO
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
16
STATUS
RESULT LATCH
EXECUTION
UNIT
16
SYNCHRONIZE
MICROSEQUENCER
STATUS
M
CONTROL
LOGIC
DATA
DSCLK
CONTROL
LOGIC
SERIAL
CLOCK
32 DEBUG I/O BLOCK
Figure 3-10 Debug Serial I/O Block Diagram
The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral interface (SPI) protocol. The development system serves as the master of the
serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from
the CPU32 system clock, development system serial logic is unhindered by the operating frequency of the target processor. Operable frequency range of the serial clock
is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode — data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on
the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data
is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide, including 16 data bits and a status/control bit (refer
to Figure 3-11). Bit 16 indicates the status of CPU-generated messages. Table 3-7
shows the CPU-generated message types.
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16
0
15
DATA FIELD
S/C
⇑
STATUS CONTROL BIT
BDM SERIAL DATA WORD
Figure 3-11 BDM Serial Data Word
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Table 3-7 CPU Generated Message Encoding
Bit 16
Data
Message Type
0
XXXX
Valid data transfer
0
FFFF
Command complete; Status OK
1
0000
Not ready with response; Come again
1
0001
BERR terminated bus cycle; Data invalid
1
FFFF
Illegal command
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Motorola reserves the right to
use this bit for future enhancements.
3.10.10 Recommended BDM Connection
In order to provide for use of development tools when an MCU is installed in a system,
Motorola recommends that appropriate signal lines be routed to a male Berg connector or double-row header installed on the circuit board with the MCU. Refer to Figure
3-12.
DS 1
2
BERR
GND 3
4
BKPT/DSCLK
GND 5
6
FREEZE
RESET 7
8
IFETCH/DSI
VDD 9
10
IPIPE/DSO
32 BERG
Figure 3-12 BDM Connector Pinout
3.10.11 Deterministic Opcode Tracking
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch
(IFETCH) output identifies the bus cycles in which the operand is loaded into the
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instruction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these
two signals allows a bus state analyzer to synchronize itself to the instruction stream
and monitor its activity.
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3.10.12 On-Chip Breakpoint Hardware
An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap
on any memory access. Off-chip address comparators preclude breakpoints unless
show cycles are enabled. Breakpoints on instruction prefetches that are ultimately
flushed from the instruction pipeline are not acknowledged; operand breakpoints are
always acknowledged. Acknowledged breakpoints initiate exception processing at the
address in exception vector number 12, or alternately enter background mode.
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SECTION 4
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
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4.1 Overview
MC68F375 contains the single chip integration module 2 (SCIM2E). The SCIM2E consists of several submodules:
• The system configuration block controls MCU configuration and operating mode.
• The system clock generates clock signals used by the SCIM2E, other IMB modules, and external devices. Circuitry is included to detect loss of the phase-locked
loop (PLL) reference frequency and to control clock operation in low power stop
mode.
• The system protection block provides bus and software watchdog monitors. It
also incorporates a periodic interrupt generator that supports execution of timecritical control routines.
• The external bus interface (EBI) handles the transfer of information between the
CPU32 and external address space. Ports A, B, E, F, G, and H comprise the EBI
and may be used for discrete I/O subject to the MCU’s operating mode.
• The chip-select block provides nine general-purpose chip-select signals and two
emulation support chip-select signals. Each general-purpose chip select has associated base address and option registers that control the programmable characteristics of the chip select. Chip-select pins can also be used as generalpurpose output port C.
The MC68F375 SCIM2E includes improvements to the regular SCIM. This enhanced
SCIM includes improvements to the clock synthesizer. These changes are defined in
detail in 4.3.2 Clock Synthesizer Submodule. Please refer to the SCIM Reference
Manual (SCIMRM/AD) for more details on the characteristics of this module.
The SCIM2E has three basic operating modes:
• 16-bit expanded mode
• 8-bit expanded mode
• Single-chip mode
Operating mode is determined by the logic states of specific MCU pins during reset.
Refer to 4.7.8 Operating Configuration Out of Reset for more detailed information
on MCU operating modes.
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SYSTEM CONFIGURATION
XTAL
CLKOUT
EXTAL
MODCLK
FASTREF
CLOCK SYNTHESIZER
SYSTEM PROTECTION
CHIP SELECTS
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CHIP SELECTS
EXTERNAL BUS
EXTERNAL BUS INTERFACE
RESET
TSC
FREEZE/QUOT
FACTORY TEST
S(C)IM BLOCK
Figure 4-1 SCIM2E Block Diagram
4.2 System Configuration
The MCU can operate as a stand-alone device in single-chip mode or it can operate
with the support of external memory and/or peripheral devices in the 16-bit or 8-bit
expanded modes. System configuration is determined by asserting MCU pins during
reset and by setting bits in the SCIM2E module configuration register (SCIMMCR).
4.2.1 SCIM Module Configuration Register
SCIMMCR — SCIM Module Configuration Register
MSB
15
EXOFF
14
13
12
FRZSW FRZBM CPUD1
11
10
02
SLOWE
0
0
9
8
SHEN
0xYF FA00
7
6
5
4
SUPV
MM
ABD1
RWD1
1
1
*
*
3
2
1
LSB
0
1
1
IARB
RESET:
0
1
1
*
0
0
1
1
NOTES:
1. Reset state is mode-dependent. Refer to the following bit descriptions.
2. Ensure that initialization software does not change this value (it should always read zero).
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Table 4-1 SCIMMCR Bit Descriptions
Bit(s)
Name
Description
External clock off.
15
EXOFF
14
FRZSW
13
FRZBM
0 = The CLKOUT pin is driven during normal operation.
1 = The CLKOUT pin is placed in a high-impedance state.
Freeze software enable. Enables or disables the software watchdog and periodic interrupt timer
during background debug mode when FREEZE is asserted.
0 = Enables the software watchdog and periodic interrupt timer when FREEZE is asserted.
1 = Disables the software watchdog and periodic interrupt timer when FREEZE is asserted.
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Freeze bus monitor enable.
12
CPUD
11
—
10
SLOWE
9:8
SHEN
7
SUPV
6
MM
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
CPU development support disable. CPUD is cleared to zero when the MCU is in an expanded
mode, and set to one in single-chip mode.
0 = Instruction pipeline signals available on pins IPIPE and IFETCH.
1 = Pins IPIPE and IFETCH placed in high-impedance state unless a breakpoint occurs.
Reserved
Slow mode enable. Control bit which forces pins on the chip to operate in fast mode regardless
of how they are set up from the controlling module. Slow mode is enabled by setting this bit.
0 = Pins setup by the controlling module to operate in slow mode will operate in fast mode.
1 = Pins will operate at the normal speed controlled by the module.
Show cycle enable. The SHEN field determines how the external bus is driven during internal
transfer operations. A show cycle allows internal transfers to be monitored externally. Table 43 indicates whether show cycle data is driven externally, and whether external bus arbitration
can occur. To prevent bus conflict, external devices must not be selected during show cycles.
Supervisor/user data space. The SUPV bit places the SCIM2E global registers in either supervisor or user data space.
0 = Registers access controlled by the SUPV bit accessible in either supervisor or user mode.
1 = Registers access controlled by the SUPV bit restricted to supervisor access only.
Module mapping
5
4
3:0
ABD
RWD
IARB
0 = Internal modules are addressed from 0x7FF000 – 0x7FFFFF.
1 = Internal modules are addressed from 0xFFF000 – 0xFFFFFF.
Address Bus Disable. ABD is cleared to zero when the MCU is in an expanded mode, and set
to one in single-chip mode. ABD can be written only once after reset.
0 = Pins ADDR[2:0] operate normally.
1 = Pins ADDR[2:0] are disabled.
Read/write disable. RWD is cleared to zero when the MCU is in an expanded mode, and set to
one in single-chip mode. RWD can be written only once after reset.
0 = R/W signal operates normally
1 = R/W signal placed in high-impedance state.
Each module that can generate interrupts, including the SCIM2E, has an IARB field. Each IARB
field can be assigned a value from 0x0 to 0xF. During an interrupt acknowledge cycle, IARB permits arbitration among simultaneous interrupts of the same priority level. The reset value of the
SCIM2 IARB field is 0xF, the highest priority. This prevents SCIM2 interrupts from being discarded during system initialization.
The SCIMMCR register controls the system configuration. SCIMMCR can be read or
written at any time, except for the module mapping (MM) bit, which can only be written
once after reset, and the reserved bit, which is read-only. Writes have no effect.
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4.2.2 Module Mapping
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping (MM) bit in SCIMMCR determines where the
control register block is located in the system memory map. When MM = 0, register
addresses range from 0x7FF000 to 0x7FFFFF; when MM = 1, register addresses
range from 0xFFF000 to 0xFFFFFF.
Freescale Semiconductor, Inc...
For CPU16 devices, the MM bit must be a logical in order for the internal registers to
be available. The MM bit is a write-once bit. Writing the M bit to a logic 0 will make the
internal registers unavailable until a system reset occurs.
4.2.3 Interrupt Arbitration
Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbitration between interrupt requests of the same priority is performed by serial
contention between IARB field bit values. Contention will take place whenever an interrupt request is acknowledged, even when there is only a single request pending. For
an interrupt to be serviced, the appropriate IARB field must have a non-zero value. If
an interrupt request from a module with an IARB field value of 0b0000 is recognized,
the CPU32 will start to process the interrupt. The CPU will attempt to run and IACK
cycle. Because the IARB values of the interrupting module is 0b0000, the module cannot cause the termination of the IACK cycle. In this case, the IACK cycle can only be
terminated by an external DSACK, a software watchdog timeout or a bus error. If the
IACK cycle is terminated by BERR, a spurious interrupt exception is taken.
Because the SCIM2E routes external interrupt requests to the CPU32, the SCIM2E
IARB field value is used for external interrupts. The reset value of IARB for the
SCIM2E is 0b1111. The reset IARB value for all other modules is 0b0000. This prevents SCIM2E interrupts from being discarded during initialization. Refer to 4.8
Interrupts for a discussion of interrupt arbitration.
4.2.4 Noise Reduction in Single-Chip Mode
Four bits in SCIMMCR control pins that can be disabled in single-chip mode to reduce
MCU noise emissions. The characteristics of these control bits are listed in Table 4-2.
Except for EXOFF, these bits disable their associated pins when the MCU is configured for single-chip mode (BERR = 0 during reset).
Table 4-2 SCIMMCR Noise Control Bits
Bit
Mnemonic
Position in
SCIMMCR
EXOFF
15
Disables CLKOUT when set to one.
CPUD
12
Disables IPIPE/DSO and IFETCH/DSI pins when set to one.
ABD
5
Disables ADDR[2:0] when set to one.
RWD
4
Disables R/W when set to one.
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0
Inverted state of
the BERR pin
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EXOFF disables the CLKOUT external clock output pin by placing the pin in a highimpedance state. CLKOUT is enabled at power-up unless explicitly disabled by writing
a zero to EXOFF.
CPUD disables the IPIPE/DSO and IFETCH/DSI instruction tracking pins by placing
them in a high-impedance state when the MCU is not in background debug mode
(BDM). When the MCU enters BDM and FREEZE is asserted, IPIPE/DSO and
IFETCH/DSI become active and serve as the BDM serial I/O lines.
Freescale Semiconductor, Inc...
ABD and RWD disable the ADDR[2:0] and R/W pins by placing them in a high-impedance state. These pins should be disabled because they cannot be used for discrete
I/O and have no use in single-chip mode.
4.2.5 Show Internal Cycles
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in SCIMMCR determines what the external data bus interface does during internal
transfer operations. Table 4-3 shows whether data is driven externally, and whether
external bus arbitration can occur. The external address bus is always driven. Refer to
4.6.6.1 Show Cycles for more information.
Table 4-3 Show Cycle Enable Bits
SHEN[1:0]
Effect
00
Show cycles disabled, external arbitration enabled
01
Show cycles enabled, external arbitration disabled
10
Show cycles enabled, external arbitration enabled
11
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
4.2.6 FREEZE Assertion Response
When the CPU32 enters background debug mode, the IMB FREEZE signal is
asserted. The FRZ[1:0] bits in SCIMMCR control the behavior of the software watchdog, periodic interrupt timer, and bus monitor in response to FREEZE assertion. By
default, these protection mechanisms are disabled in BDM; they can be selectively
enabled by the FRZ[1:0] bits as shown in Table 4-4.
Table 4-4 Effects of FREEZE Assertion
FRZ[1:0]
Disabled Elements
0
0
None
0
1
Bus monitor
1
0
Software watchdog and periodic interrupt timer
1
1
Both
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4.3 System Clock
The system clock in the SCIM2E provides timing signals for IMB modules and the
external bus interface. MC68F375 MCUs are fully static MCU designs; register and
memory contents are not affected by clock rate changes. System hardware and software support clock rate changes during operation.
Freescale Semiconductor, Inc...
CAUTION
The SCIM2E system clock is different from the SCIM. Do not refer to
SCIM documentation for SCIM2E clock information.
4.3.1 System Clock Sources
The system clock signal can be generated from one of three sources. An internal
phase-locked loop (PLL) can synthesize the clock from either a slow or fast reference.
The clock signal can also be input directly from an external 2X frequency source.
The slow reference is typically a 32.768 KHz crystal; the fast reference is typically a
4 MHz crystal. The slow and fast references may be provided by sources other than a
crystal. Keep these clock sources in mind while reading the rest of this section.
The system clock source is determined upon RESET assertion by the state of the
VDDSYN/MODCLK and FASTREF/PF0 pins. In addition to selecting the system clock
source, these pins govern the functionality of the W, X, and Y bits in the synthesizer
control register (SYNCR) and the equation that determines the MCU operating frequency. Table 4-5 summarizes system clock source information. For more
information, see 4.3.6 Clock Synthesizer Control Register.
Table 4-5 System Clock Sources
VDDSYN/
MODCLK
FASTREF/
PF0
Clock Mode
SYNCR W/X/Y Bit
Assignments and
Reset Values
0
X1
External Clock
W : has no effect
X=0b1 : Divider
Y[2:0] = 0b000 : Divider
1
0
Slow Reference
W = 0b0 : Multiplier
X = 0b0 : Divider
Y[5:0] = 0b11111 : Multiplier
Fast Reference
W[2:0] = 0b011 : Multiplier
X = 0b0 : Divider
Y[2:0] = 0b111 : Divider
1
1
MCU Operating
Frequency Equation
f sys
f
ref
--------2
= ------------------------------, for Y ≤ 7
Y
(2 – X)(2 )
fsys = 4f
ref
( Y + 1)(2
( 2W + X )
)
f (W + 1)
ref
fsys = ------------------------------, for Y ≤7
Y
(2 – X)(2 )
NOTES:
1. In external clock mode, the FASTREF/PF0 pin has no effect on clock operation.
The parameter “fREF” refers to the frequency of the clock source connected to the
EXTAL pin. The parameter “fSYS” refers to the operating frequency of the MCU and
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has a defined relationship to fREF that depends on the clock mode selected during
reset.
4.3.2 Clock Synthesizer Submodule
The MC68F375 contains an improved version of the clock synthesizer subsystem. The
new architecture accommodates both slow or fast crystal references, see 4.3.1 System Clock Sources. Range of operation and power consumption were taken into
consideration when this new architecture was defined. Compatibility with the previous
architecture has been retained when possible.
Freescale Semiconductor, Inc...
In general, the improvements fall into four basic categories as follows:
• Configurable PLL for optimization of divider chain based on mode of operation;
• Improved loss-of-clock circuitry based on an independent RC oscillator;
• Improved lock detect circuitry;
• Improved noise immunity by the addition of a VSSSYN pin.
There are three modes for generating the system clock for the MCU. The system clock
may be driven directly into the EXTAL pin (external clock mode), it may be generated
on-chip by a phase locked loop (PLL) frequency synthesizer using either a slow or fast
reference mode. For modes using the PLL, a lock detect circuit detects that the PLL is
on frequency and sets a register flag. The PLL mode is determined at reset and
behaves according to Table 4-5. The source of the system clock is determined at reset
by the state of the FASTREF/PF0 and VDDSYN/MODCK pins. To enable external clock
mode, the VDDSYN/MODCK pin must be tied directly to VSS at all times
The MC68F375’s clock architecture supports the three modes of operation by optionally reconfiguring the number and location of the W bit and Y bit divider stages. In slow
reference mode, one W bit and six Y bits are located in the PLL feedback path,
enabling frequency multiplication by a factor of up to 2048. The X bit is located in the
VCO clock output path to enable dividing the system clock frequency by two without
disturbing the VCO and thus requiring re-lock. In fast reference mode, three W bits are
located in the PLL feedback path, enabling frequency multiplication by a factor from 1
to 8. Three Y bits and the X bit are located in the VCO clock output path to provide the
ability to slow the system clock without disturbing the PLL. In external clock mode,
three Y bits and the X bit are located between the EXTAL input and the system clock,
to allow slowing the clock for reduced power consumption. Refer to Figure 4-4, Figure
4-3, and Figure 4-2 for block diagrams of the architecture in these modes. The reset
value of the W, X and Y bits are determined by the clock mode as shown in Table 4-6.
NOTE
The crystal oscillator and frequency synthesizer circuits are powered
from a separate power pin pair (VDDSYN and VSSSYN) to allow the
oscillator to continue to run when the rest of the chip is powered
down. This allows avoidance of crystal start-up time. Separate supplies also help improve noise immunity.
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The filter for both PLL modes consists of resistor R1 connected in series with capacitor
C1. This combination is connected between VDDSYN and XFC. A second capacitor,
C2, is also connected between VDDSYN and XFC.
Freescale Semiconductor, Inc...
The following sections describe the clock sub-module in detail. One rule applies to all
modes of operation — the actual VCO core frequency must stay at or below two times
the maximum allowable system clock frequency. When changing frequencies, ensure
that the values written to the W, X, and Y bits do not select VCO core frequencies
above that value. If a system clock frequency is to be changed with multiple writes to
SYNCR, the write sequences should select lower VCO core frequencies first, and the
higher VCO core frequencies last unless it is certain the write sequence will not result
in VCO core frequencies above the maximum allowable system clock frequency.
4.3.3 Slow Reference Mode
In slow reference mode, the system clock is generated by the PLL typically from a
32.768-KHz reference. The frequency of the system clock is controlled by programming the X, Y, and W bits according to Table 4-6.
The W bit is in the feedback path of the VCO. When clear, this bit multiplies the reference frequency by two, and when set, by eight. This bit is clear at reset.
The Y bit divider is a 6-bit modulo counter which can multiply the reference input frequency by up to 256, providing a large number of programmable system clock
frequencies. The Y bits are all set to one at reset, providing the highest frequency system clock for a given combination of X and W bits.
The X bit is in the output path of the VCO. It may be used to divide the system clock
by two when clear and pass it without dividing when set. At reset, this bit is cleared to 0.
In slow reference mode, the W and Y bits are both in the feedback path of the PLL.
Changing the value of these bits requires the PLL to relock (with some delay) at the
new frequency. Changing the X bit, however, will change the system clock frequency
without having to wait for the PLL to relock.
Note that for slow reference mode, the crystal is not constrained to be 32.768 KHz but
must be in the range of 25 KHz to 50 KHz to ensure that the on-chip crystal oscillator
will work.
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.
Extal
Pin
Amplifier
Xtal
Pin
Input
Reference Clock
Up
Phase
Comparator
Freescale Semiconductor, Inc...
Feedback
Frequency
Charge
Pump
Dn
Y[5:0] Bits
*4(Y+1)
W[0] Bit
VCO
*2(22w)
XFC
Pin
X Bit
/(2-X)
External
Filter
R1
Circuit
System Clock
C2
C1
VSSSYN Pin
Figure 4-2 Slow Reference Mode
Figure 4-2 depicts the architecture of the system clock generation circuitry when in
this mode. Table 4-6 gives the range of system clock frequencies which may be generated using a 32.768-KHz crystal in this mode. The frequency representing the reset
configuration is shaded. Configurations of the PLL in which the system clock or the
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VCO core frequency can exceed maximum frequency specification are not supported
and are left blank, as a reminder, in the table for frequencies above 25 MHz. Select
operating frequencies from the table which do not violate the maximum system clock
frequency specification.
.
Freescale Semiconductor, Inc...
Table 4-6 CLKOUT Frequency: Slow Reference; 32.768 KHz Reference
Y
(bits)
X=0,
W=01
X=1,
W=02
Y
(bits)
X=0,
W=01
X=1,
W=02
0=000000
131,072
262,144
524,288
1=000001
262,144
524,288
1,048,576
1,048,576
32=100000
4,325,376
8,650,752
2,097,152
33=100001
4,456,448
8,912,896
2=000010
393,216
786,432
3=000011
524,288
1,048,576
1,572,864
3,145,728
34=100010
4,587,520
9,175,040
2,097,152
4,194,304
35=100011
4,718,592
9,437,184
4=000100
655,360
5=000101
786,432
1,310,720
2,621,440
5,242,880
36=100100
4,849,664
9,699,328
1,572,864
3,145,728
6,291,456
37=100101
4,980,736
9,961,472
6=000110
7=000111
917,504
1,835,008
3,670,016
7,340,032
38=100110
5,111,808
10,223,616
1,048,576
2,097,152
4,194,304
8,388,608
39=100111
5,242,880
10,485,760
8=001000
9=001001
1,179,648
2,359,296
4,718,592
9,437,184
40=101000
5,373,952
10,747,904
1,310,720
2,621,440
5,242,880
10,485,760
41=101001
5,505,024
11,010,048
10=001010
1,441,792
2,883,584
5,767,168
11,534,336
42=101010
5,636,096
11,272,192
11=001011
1,572,864
3,145,728
6,291,456
12,582,912
43=101011
5,767,168
11,534,336
12=001100
1,703,936
3,407,872
6,815,744
13,631,488
44=101100
5,898,240
11,796,480
13=001101
1,835,008
3,670,016
7,340,032
14,680,064
45=101101
6,029,312
12,058,624
14=001110
1,966,080
3,932,160
7,864,320
15,728,640
46=101110
6,160,384
12,320,768
15=001111
2,097,152
4,194,304
8,388,608
16,777,216
47=101111
6,291,456
12,582,912
4,456,448
8,912,896
3
3
48=110000
6,422,528
12,845,056
4,718,592
9,437,1843
18,874,3683
49=110001
6,553,600
13,107,200
4,980,736
9,961,472
3
3
50=110010
6,684,672
13,369,344
5,242,880
10,485,7603
20,971,5203
51=110011
6,815,744
13,631,488
4
4
52=110100
6,946,816
13,893,632
16=010000
17=010001
18=010010
19=010011
2,228,224
2,359,296
2,490,368
2,621,440
X=0, W=11 X=1, W=12
17,825,792
19,922,944
20=010100
2,752,512
5,505,024
11,010,048
21=010101
2,883,584
5,767,168
11,534,3364 23,068,6724
53=110101
7,077,888
14,155,776
22=010110
3,014,656
6,029,312
12,058,6244 24,117,2484
54=110110
7,208,960
14,417,920
23=010111
3,145,728
6,291,456
12,582,9124 25,165,8244
55=110111
7,340,032
14,680,064
24=011000
3,276,800
6,553,600
56=111000
7,471,104
14,942,208
25=011001
3,407,872
6,815,744
57=111001
7,602,176
15,204,352
26=011010
3,538,944
7,077,888
58=111010
7,733,248
15,466,496
27=011011
3,670,016
7,340,032
59=111011
7,864,320
15,728,640
28=011100
3,801,088
7,602,176
60=111100
7,995,392
15,990,784
29=011101
3,932,160
7,864,320
61=111101
8,126,464
16,252,928
30=011110
4,063,232
8,126,464
62=111110
8,257,536
16,515,072
31=011111
4,194,304
8,388,608
63=111111
8,388,608
16,777,216
22,020,096
X=0,
W=11
X=1,
W=12
NOTES:
1. VCO core frequency = 4 times the value in the table.
2. VCO core frequency = 2 times the value in the table. VCO core must not exceed 2x fSYS.
3. These values are valid for 20- and 25-MHz devices only.
4. These values are valid for 25-MHz devices only.
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4.3.4 Fast Reference Mode
In fast reference mode, the system clock is generated by the PLL from a reference frequency much higher than that used in slow reference mode (e.g., four MHz). At reset,
the system clock frequency will be equal to twice the reference frequency. This is
accomplished by configuring the W bits to multiply by four, and setting the X bit to
divide by two for a net result of multiplying by two. The frequency may be multiplied
using the W bits or divided using the X and Y bits to generate the desired system clock
frequency. This mode improves stability over the slow reference mode and, like slow
reference mode, provides a 50% duty cycle system clock regardless of the reference
duty cycle.
The W bits are in the feedback path of the VCO. They can be programmed to multiply
the reference frequency by a factor from one to eight. These bits come out of reset as
0b11, so that the system clock frequency is four times the reference clock frequency.
After reset, the W bits can be changed to multiply the reference to the desired system
clock frequency. Changing of the W bits will result in PLL unlocking for the PLL lock
time specified.
The X bit on the VCO output is used to divide the VCO frequency by two or one. This
bit comes out of reset clear (divide by two) so that the system clock frequency is actually one half of what it is multiplied to by the W bits. This bit may be set to increase the
system frequency to twice that of the frequency when this bit is clear.
The Y bit divider is a six-stage divider chain in the clock output path, whose output tap
is controlled by the three Y register bits. It can divide the output of the VCO down by
powers of two to as much as 64, providing a large number of programmable frequencies in this mode.
NOTE
Setting Y to 7 in this mode has the same effect as setting it to 6; the
maximum divisor is 26. Dividing the PLL output clock with the Y bits
reduces the system clock frequency thereby conserving power.
Since the X and Y bits are not in the PLL feedback path, the PLL will
not have to relock to the new target frequency when they are
changed. The Y bits are cleared to all zeros at reset. Figure 4-3 is a
block diagram of the fast reference mode architecture.
Table 4-7 gives example values of the system clock frequency in fast reference mode
using a 4.0-MHz reference. The frequency representing the reset configuration is
shaded in this table. This frequency ends up being twice the reference frequency when
the X bit is cleared, or 8.0 MHz with a 4.0-MHz reference clock. The X bit can then be
set to select a system frequency of four times the reference frequency, or 16.0 MHz
with a 4.0-MHz reference clock with no PLL re-lock time requirements. Combinations
of programmed values for the W, X, and Y bits which would exceed maximum system
or VCO core frequencies are not supported and are left blank, as a reminder, in the
table for frequencies above 33 MHz.
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Extal
Pin
Amp
Xtal
Pin
Input
Reference Clock
Up
Freescale Semiconductor, Inc...
Feedback
Frequency
Charge
Pump
Phase
Comparator
Dn
W[2:0] Bits
VCO
*(W+1)
Y[2:0] Bits
/2Y
XFC
Pin
(Y≤6)
X Bit
/(2-X)
External
R1
Filter
C2
Circuit
System Clock
C1
VSSSYN Pin
Figure 4-3 Fast Reference Mode
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Freescale Semiconductor, Inc...
Table 4-7 CLKOUT In Fast Reference Mode with 4.0 MHz Reference
Y
X=0
W=000
W=001
W=010
W=011
0=000
2,000,000
4,000,000
6,000,000
8,000,000
10,000,000 12,000,000 14,000,000 16,000,000
1=001
1,000,000
2,000,000
3,000,000
4,000,000
5,000,000
6,000,000
7,000,000
8,000,000
2=010
500,000
1,000,000
1,500,000
2,000,000
2,500,000
3,000,000
3,500,000
4,000,000
3=011
250,000
500,000
750,000
1,000,000
1,250,000
1,500,000
1,750,000
2,000,000
4=100
125,000
250,000
375,000
500,000
625,000
750,000
875,000
1,000,000
5=101
62,500
125,000
187,500
250,000
312,500
375,000
437,500
500,000
6=110
31,250
62,500
93,750
125,000
156,250
187,500
218,750
250,000
7=111
31,250
62,500
93,750
125,000
156,250
187,500
218,750
250,000
Y
X=1
W=000
W=001
W=010
W=011
W=100
W=101
W=110
W=111
0=000
4,000,000
8,000,000
W=100
W=101
W=110
W=111
12,000,000 16,000,000 20,000,000 24,000,000 28,000,000 32,000,000
1=001
2,000,000
4,000,000
6,000,000
8,000,000
10,000,000 12,000,000 14,000,000 16,000,000
2=010
1,000,000
2,000,000
3,000,000
4,000,000
5,000,000
6,000,000
7,000,000
8,000,000
3=011
500,000
1,000,000
1,500,000
2,000,000
2,500,000
3,000,000
3,500,000
4,000,000
4=100
250,000
500,000
750,000
1,000,000
1,250,000
1,500,000
1,750,000
2,000,000
5=101
125,000
250,000
375,000
500,000
625,000
750,000
375,000
1,000,000
6=110
62,500
125,000
187,500
250,000
312,500
375,000
187,500
500,000
7=111
62,500
125,000
187,500
250,000
312,500
375,000
187,500
500,000
4.3.5 External Clock Mode
In external clock mode, the clock source, which should be 2x the desired system frequency, must be driven onto the EXTAL pin. This clock is used to generate the system
clock directly (the VCO is turned off). At reset, the system clock frequency is one-half
the external clock frequency. If this frequency is the the maximum specified system
clock frequency, it must not violate strict minimum duty cycle requirements. A block
diagram of external clock mode is show in Figure 4-4.
In this mode, the six-stage Y divider and the one-stage X divider are placed in the clock
output path such that the input clock may be divided down by as much as 128 to produce the system clock. When this is done, it is not necessary to meet the input duty
cycle restrictions. The Y bit divider is a six-stage divider chain whose output tap is controlled by the three Y register bits. The X bit divider is a single-stage divider which is
bypassed when X is set to 1. X is 1 and Y is 0 after reset, so that the system clock is
the same as the external clock.
NOTE
Setting Y to 7 has the same effect as setting it to 6; the maximum divisor is 26. The X and Y bit dividers are in the output clock path.
Therefore, changing the X or Y bits in this mode causes the frequency to change without a delay.
MC68F375
REFERENCE MANUAL
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Rev. 25 June
03This Product,
For More Information
On
Go to: www.freescale.com
MOTOROLA
4-13
Freescale Semiconductor, Inc.
When the MC68F375 is configured in external clock mode, the VCO will be turned off
to save power. Changing the unused W bits will have no effect.
Y[2:0] Bits
X Bit
/(2Y)
/2
EXTAL
System Clock
/2
/(2-X)
(Y