MC68HC705SR3CP

MC68HC05SR3 MC68HC705SR3 Technical Data M68HC05 Microcontrollers MC68HC05SR3D/H Rev. 2.1 08/2005 freescale.com 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM GENERAL DESCRIPTION 1 PIN DESCRIPTIONS 2 INPUT/OUTPUT PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 TIMER 6 ANALOG TO DIGITAL CONVERTER 7 CPU CORE AND INSTRUCTION SET 8 LOW POWER MODES 9 OPERATING MODES 10 ELECTRICAL SPECIFICATIONS 11 MECHANICAL SPECIFICATIONS 12 MC68HC705SR3 A TPG 1 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 1 GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS 12 MECHANICAL SPECIFICATIONS A MC68HC705SR3 TPG 2 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM MC68HC05SR3 MC68HC705SR3 High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units All Trade Marks recognized. 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The Customer should ensure that it has the most up to date version of the document by contacting its local Freescale office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.  Freescale LTD., 2005 TPG 3 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM Conventions Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ‘u’ is used to indicate an undefined state (on reset). TPG 4 05SR3.Book Page 7 Thursday, August 4, 2005 1:08 PM CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05SR3D/H) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category. Excellent ❏ ❏ ❏ ❏ ❏ Organization Readability Understandability Accuracy Illustrations Poor ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ Excellent ❏ ❏ ❏ ❏ ❏ Tables Table of contents Index Page size/binding Overall impression Poor ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ Comments: 2. What is your intended use for this document? If more than one option applies, please rank them (1, 2, 3). ❏ ❏ ❏ Selection of device for new application System design Training purposes 3. ❏ Please specify: How well does this manual enable you to perform the task(s) outlined in question 2? Completely – Cut along this line to remove – Other Not at all Comments: ❏ ❏ ❏ ❏ 4. How easy is it to find the information you are looking for? Easy Difficult Comments: ❏ ❏ ❏ ❏ 5. Is the level of technical detail in the following sections sufficient to allow you to understand how the device functions? Too little detail SECTION 1 GENERAL DESCRIPTION SECTION 2 PIN DESCRIPTIONS SECTION 3 INPUT/OUTPUT PORTS SECTION 4 MEMORY AND REGISTERS SECTION 5 RESETS AND INTERRUPTS SECTION 6 TIMER SECTION 7 ANALOG TO DIGITAL CONVERTER SECTION 8 CPU CORE AND INSTRUCTION SET SECTION 9 LOW POWER MODES SECTION 10 OPERATING MODES SECTION 11 ELECTRICAL SPECIFICATIONS SECTION 12 MECHANICAL SPECIFICATIONS APPENDIX A MC68HC705SR3 ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ Too much detail ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ ✂ Comments: 6. Have you found any errors? If so, please comment: 7. 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TPG – Finally, tuck this edge into opposite flap – 6 05SR3.Book Page i Thursday, August 4, 2005 1:08 PM TABLE OF CONTENTS Paragraph Number TITLE Page Number 1 GENERAL DESCRIPTION 1.1 1.2 Features.................................................................................................................1-1 Mask Options.........................................................................................................1-2 2 PIN DESCRIPTIONS 2.1 Functional Pin Descriptions ...................................................................................2-1 2.2 OSC1 and OSC2 Connections ..............................................................................2-2 2.2.1 Crystal Oscillator..............................................................................................2-3 2.2.2 External Clock..................................................................................................2-3 2.2.3 RC Oscillator Option ........................................................................................2-4 2.3 Pin Assignments ....................................................................................................2-5 3 INPUT/OUTPUT PORTS 3.1 3.1.1 3.1.2 3.2 3.3 3.4 3.5 3.6 3.6.1 Parallel Ports .........................................................................................................3-1 Port Data Registers..........................................................................................3-1 Port Data Direction Registers ..........................................................................3-2 Port A — Keyboard Interrupts (KBI) ......................................................................3-2 PD0:PD5 — ADC Inputs........................................................................................3-2 PD6 — IRQ2..........................................................................................................3-3 Programmable Current Drive .................................................................................3-3 Programmable Pull-Up Devices.............................................................................3-5 Port Option Register ........................................................................................3-5 TPG MC68HC05SR3 Freescale i 7 05SR3.Book Page ii Thursday, August 4, 2005 1:08 PM Paragraph Number TITLE Page Number 4 MEMORY AND REGISTERS 4.1 4.2 4.3 4.4 4.5 I/O Registers ......................................................................................................... 4-1 RAM ......................................................................................................................4-1 ROM ......................................................................................................................4-1 Memory Map ......................................................................................................... 4-2 I/O Registers Summary .........................................................................................4-3 5 RESETS AND INTERRUPTS 5.1 RESETS ................................................................................................................5-1 5.1.1 Power-On Reset (POR) ................................................................................... 5-1 5.1.2 RESET Pin.......................................................................................................5-1 5.1.3 Low Voltage Reset (LVR) .................................................................................5-2 5.2 INTERRUPTS........................................................................................................5-2 5.2.1 Non-maskable Software Interrupt (SWI) ..........................................................5-3 5.2.2 Maskable Hardware Interrupts.........................................................................5-5 5.2.2.1 External Interrupt (IRQ)..............................................................................5-5 5.2.2.2 External Interrupt 2 (IRQ2).........................................................................5-7 5.2.2.3 Timer Interrupt ........................................................................................... 5-7 5.2.2.4 Keyboard Interrupt (KBI) ............................................................................5-8 6 TIMER 6.1 6.2 6.3 6.4 Timer Overview .....................................................................................................6-1 Timer Control Register (TCR) ............................................................................... 6-3 Timer Data Register (TDR) ................................................................................... 6-4 Operation during Low Power Modes ..................................................................... 6-4 7 ANALOG TO DIGITAL CONVERTER 7.1 7.2 7.3 7.4 ADC Operation ...................................................................................................... 7-2 ADC Status and Control Register (ADSCR)..........................................................7-3 ADC Data Register (ADDR) .................................................................................. 7-4 ADC during Low Power Modes..............................................................................7-4 TPG Freescale ii MC68HC05SR3 8 05SR3.Book Page iii Thursday, August 4, 2005 1:08 PM Paragraph Number TITLE Page Number 8 CPU CORE AND INSTRUCTION SET 8.1 Registers ...............................................................................................................8-1 8.1.1 Accumulator (A) ...............................................................................................8-1 8.1.2 Index register (X)..............................................................................................8-2 8.1.3 Program counter (PC) ......................................................................................8-2 8.1.4 Stack pointer (SP) ............................................................................................8-2 8.1.5 Condition code register (CCR).........................................................................8-2 8.2 Instruction set ........................................................................................................8-3 8.2.1 Register/memory Instructions ..........................................................................8-4 8.2.2 Branch instructions ..........................................................................................8-4 8.2.3 Bit manipulation instructions ............................................................................8-4 8.2.4 Read/modify/write instructions .........................................................................8-4 8.2.5 Control instructions ..........................................................................................8-4 8.2.6 Tables...............................................................................................................8-4 8.3 Addressing modes .................................................................................................8-11 8.3.1 Inherent............................................................................................................8-11 8.3.2 Immediate ........................................................................................................8-11 8.3.3 Direct................................................................................................................8-11 8.3.4 Extended..........................................................................................................8-12 8.3.5 Indexed, no offset.............................................................................................8-12 8.3.6 Indexed, 8-bit offset..........................................................................................8-12 8.3.7 Indexed, 16-bit offset........................................................................................8-12 8.3.8 Relative ............................................................................................................8-13 8.3.9 Bit set/clear ......................................................................................................8-13 8.3.10 Bit test and branch ...........................................................................................8-13 9 LOW POWER MODES 9.1 9.2 9.3 9.4 STOP Mode ...........................................................................................................9-1 WAIT Mode............................................................................................................9-1 SLOW Mode ..........................................................................................................9-3 Data-Retention Mode ............................................................................................9-3 10 OPERATING MODES 10.1 10.2 10.3 User Mode ...........................................................................................................10-1 Self-Check Mode .................................................................................................10-1 Bootstrap Mode ...................................................................................................10-3 TPG MC68HC05SR3 Freescale iii 9 05SR3.Book Page iv Thursday, August 4, 2005 1:08 PM Paragraph Number TITLE Page Number 11 ELECTRICAL SPECIFICATIONS 11.1 11.2 11.3 11.4 11.5 Maximum Ratings................................................................................................ 11-1 Thermal Characteristics ...................................................................................... 11-1 DC Electrical Characteristics............................................................................... 11-2 ADC Electrical Characteristics ............................................................................ 11-4 Control Timing ..................................................................................................... 11-5 12 MECHANICAL SPECIFICATIONS 12.1 12.2 12.3 40-Pin DIP Package (Case 711-03) .................................................................... 12-2 42-Pin SDIP Package (Case 858-01) .................................................................. 12-2 44-pin QFP Package (Case 824A-01) ................................................................. 12-3 A MC68HC705SR3 A.1 A.2 A.3 A.4 A.4.1 A.4.2 A.4.3 A.5 A.6 Features ............................................................................................................... A-1 Modes of Operation .............................................................................................. A-2 User Mode ............................................................................................................ A-2 Bootstrap Mode .................................................................................................... A-2 EPROM Programming .................................................................................... A-3 Program Control Register (PCR) .................................................................... A-3 EPROM Programming Sequence ................................................................... A-3 Mask Option Register (MOR) ............................................................................... A-4 Pin Assignments................................................................................................... A-5 TPG Freescale iv MC68HC05SR3 10 05SR3.Book Page v Thursday, August 4, 2005 1:08 PM LIST OF FIGURES Figure Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 4-1 5-1 5-2 5-3 5-4 6-1 7-1 8-1 8-2 9-1 10-1 12-1 12-2 12-3 TITLE Page Number MC68HC05SR3/ MC68HC705SR3 Block Diagram................................................ 1-3 Oscillator Connections............................................................................................ 2-3 Typical Oscillator Frequency for Selected External Resistor .................................. 2-4 Typical Oscillator Frequency for Wire-Strap Connection ........................................ 2-4 Pin Assignment for 40-pin PDIP ............................................................................. 2-5 Pin Assignment for 42-pin SDIP ............................................................................. 2-6 Pin Assignment for 44-pin QFP .............................................................................. 2-6 Port I/O Circuitry ..................................................................................................... 3-2 Typical IOL vs VOL @VDD=5V.............................................................................. 3-3 Typical IOH vs VOH @VDD=5V............................................................................. 3-4 Typical IOL vs VOL @VDD=3V.............................................................................. 3-4 Typical IOL vs VOL @VDD=3V.............................................................................. 3-5 MC68HC05SR3/MC68HC705SR3 Memory Map................................................... 4-2 Interrupt Stacking Order ......................................................................................... 5-3 Hardware Interrupt Processing Flowchart .............................................................. 5-4 External Interrupt.................................................................................................... 5-6 Keyboard Interrupt Circuitry.................................................................................... 5-8 Timer Block Diagram .............................................................................................. 6-2 ADC Converter Block Diagram ............................................................................... 7-1 Programming model ............................................................................................... 8-1 Stacking order ........................................................................................................ 8-2 STOP and WAIT Mode Flowcharts......................................................................... 9-2 MC68HC05SR3 Self-Check Circuit ...................................................................... 10-2 40-pin DIP Package.............................................................................................. 12-2 42-pin SDIP Package ........................................................................................... 12-2 44-pin QFP Package ............................................................................................ 12-3 TPG MC68HC05SR3 Freescale v 11 05SR3.Book Page vi Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY TPG Freescale vi MC68HC05SR3 12 05SR3.Book Page vii Thursday, August 4, 2005 1:08 PM LIST OF TABLES Table Number 1-1 3-1 4-1 5-1 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 10-1 10-2 11-1 11-2 11-3 11-4 11-5 A-1 TITLE Page Number Power-On Reset Delay Mask Option ...................................................................... 1-2 I/O Pin Functions .................................................................................................... 3-1 MC68HC05SR3/MC68HC705SR3 I/O Registers ................................................... 4-3 Reset/Interrupt Vector Addresses .......................................................................... 5-3 ADC Channel Assignments .................................................................................... 7-4 MUL instruction ...................................................................................................... 8-5 Register/memory instructions................................................................................. 8-5 Branch instructions ................................................................................................. 8-6 Bit manipulation instructions................................................................................... 8-6 Read/modify/write instructions ............................................................................... 8-7 Control instructions................................................................................................. 8-7 Instruction set ......................................................................................................... 8-8 M68HC05 opcode map........................................................................................... 8-10 Mode Selection..................................................................................................... 10-1 Self-Check Report ................................................................................................ 10-3 DC Electrical Characteristics for 5V Operation..................................................... 11-2 DC Electrical Characteristics for 3V Operation..................................................... 11-3 ADC Electrical Characteristics for 5V and 3V Operation...................................... 11-4 Control Timing for 5V Operation ........................................................................... 11-5 Control Timing for 3V Operation ........................................................................... 11-6 MC68HC705SR3 Operating Mode Entry Conditions .............................................A-2 TPG MC68HC05SR3 Freescale vii 13 05SR3.Book Page viii Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY TPG Freescale viii MC68HC05SR3 14 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 1 1 GENERAL DESCRIPTION The MC68HC05SR3 HCMOS microcontroller is a member of the M68HC05 family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, I/O, Timer, and Analog-to-Digital Converter. The MC68HC05SR3 is pin compatible with the MC6805R3 and is provided as a low power upgrade path for MC6805R3 applications. The low power advantage of CMOS is combined with the addition of I/O and port modifications which help eliminate external components in cost sensitive applications. The MC68HC705SR3 is an EPROM version of the MC68HC05SR3; it is available in windowed and OTP packages. All references to the MC68HC05SR3 apply equally to the MC68HC705SR3, unless otherwise stated. References specific to the MC68HC705SR3 are italicized in the text and also, for quick reference, they are summarized in Appendix A. 1.1 Features • Fully static chip design featuring the industry standard 8-bit M68HC05 core • Pin compatible with the MC6805R3 • Power saving STOP, WAIT, and SLOW modes • 3840 bytes of user ROM with security feature in MC68HC05SR3 3840 bytes of EPROM with security bit in MC68HC705SR3 • 192 bytes of RAM (64 bytes for stack) • 32 bidirectional I/O lines • Keyboard interrupts • 8-bit count-down timer with programmable 7-bit prescaler • On-chip crystal oscillator, with built-in capacitor for RC option • Second software programmable external interrupt line (IRQ2) • Direct LED drive capability on all ports • Programmable 20KΩ pull-up resistors integrated into I/O ports TPG MC68HC05SR3 GENERAL DESCRIPTION Freescale 1-1 15 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM 1 • Internal 100KΩ pull-up resistors on IRQ and RESET pins • Four channel 8-bit Analog to Digital Converter • Low Voltage Reset • Available in 40-pin PDIP, 42-pin SDIP and 44-pin QFP packages 1.2 Mask Options The following mask options are available: • RC or Crystal Oscillator (see Section 2.2). The default is crystal option. • Power-On Reset delay — Table 1-1 shows available options. The default value is 4096 cycles. Table 1-1 Power-On Reset Delay Mask Option Power-On Reset Delay (cycles) 256 512 1024 2048 4096 8192 16384 32768 • Power-On Reset Slow mode. If enabled, the device goes into Slow mode directly upon power-on reset. The bus frequency is 16 times slower than the normal mode. Thus, the power-on reset delay will also be 16 times longer. The default setting is “Slow mode” disabled. TPG Freescale 1-2 GENERAL DESCRIPTION MC68HC05SR3 16 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM DDR A SELF-CHECK/BOOTSTRAP ROM - 240 BYTES PORT A KEYBOARD INTERRUPT 8 PORT B USER ROM/EPROM - 3840 BYTES 8 PORT C 1 8 PA0 - PA7 RAM - 192 BYTES M68HC05 CPU 0 DDR B 7 ACCUMULATOR 7 PB0 - PB7 0 INDEX REGISTER 12 5 0 0 0 0 0 1 1 0 STACK POINTER 0 DDR C 4 PROGRAM COUNTER RESET RESET LOW VOLTAGE RESET 7-BIT PRESCALER 8-Bit ADC POWER 8-BIT COUNTER VDD TIMER CONTROL VSS OSC1 OSC2 PC0 - PC7 7 0 1 1 1 H I N Z C CONDITION CODE REGISTER DDR D IRQ PORT D 15 PD7 PD6/IRQ2 PD5/VRH PD4/VRL PD3/AN3 PD2/AN2 PD1/AN1 PD0/AN0 OSC ÷2 TIMER Figure 1-1 MC68HC05SR3/MC68HC705SR3 Block Diagram TPG MC68HC05SR3 GENERAL DESCRIPTION Freescale 1-3 17 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 1 THIS PAGE LEFT BLANK INTENTIONALLY TPG Freescale 1-4 GENERAL DESCRIPTION MC68HC05SR3 18 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 2 2 PIN DESCRIPTIONS This section provides a description of the functional pins of the MC68HC05SR3 microcontroller. 2.1 Functional Pin Descriptions 40-pin PDIP PIN No. 42-pin SDIP PIN No. 44-pin QFP PIN No. VDD VSS VSS(INT) VSS(EXT) 4 1 — — 5 — 1 2 10, 33 32 6 7 Power is supplied to the MCU using these pins. VDD should be connected to the positive supply. VSS, VSS(INT), and VSS(EXT) should be connected to supply ground. VPP 7 8 13 This is the EPROM programming voltage input pin on the MC68HC705SR3. On the MC68HC05SR3 part, this pin should be connected to VDD or VSS. 9 IRQ is software programmable to provide two choices of interrupt triggering sensitivity. These options are: 1) negative-edge-sensitive triggering only, or 2) both negative-edge-sensitive and level-sensitive triggering. This pin has an integrated pull-up resistor to VDD but should be tied to VDD if not needed to improve noise immunity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin may affect the mode of operation as described in Section 10. PIN NAME IRQ 3 4 DESCRIPTION RESET 2 3 8 This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. It also has an internal pull-down device that pulls the RESET pin low during the power-on reset cycles and an integrated pull-up resistor to VDD. TIMER 8 9 14 The TIMER pin provides an optional gating input to the timer. Refer to Section 6 for additional information. 5, 6 6, 7 11, 12 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. See Section 2.2 for detail. OSC1, OSC2 TPG MC68HC05SR3 PIN DESCRIPTIONS Freescale 2-1 19 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM PIN NAME 2 PA0-PA7 PB0-PB7 PC0-PC7 40-pin PDIP PIN No. 33-40 25-32 9-16 42-pin SDIP PIN No. 34-41 26-33 10-17 44-pin QFP PIN No. DESCRIPTION 42-44, 1-5 These eight I/O lines comprise port A. The state of any pin is software programmable. All port A lines are configured as input during power-on or external reset. PA0-PA7 are also associated with the Keyboard Interrupt function. Each pin is equipped with a programmable integrated 20KΩ pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. See Section 3 for details on the I/O ports. 31, 35-41 These eight I/O lines comprise port B. The state of any pin is software programmable. All port B lines are configured as input during power-on or external reset. Each pin is equipped with a programmable integrated 20KΩ pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. PB5-PB7 can also be programmed to provide a lower current drive of 2mA. See Section 3 for details on the I/O ports. 15-22 These eight I/O lines comprise port C. The state of any pin is software programmable. All port C lines are configured as input during power-on or external reset. Each pin is equipped with a programmable integrated 20KΩ pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. See Section 3 for details on the I/O ports. PD0-PD7 24-21, 20-17 25-22, 21-18 30-23 AN0-AN3 IRQ2 VRH VRL 24-21 18 19 20 25-22 19 20 21 30-27 24 25 26 2.2 These eight I/O lines comprise port D. The state of any pin is software programmable. All port D lines are configured as input during power-on or external reset. Each pin is equipped with a programmable integrated 20KΩ pull-up resistor connected to VDD when configured as input. When programmed as output, each pin can provide a current drive of 10mA. PD0-PD3 become analog inputs AN0-AN3 when the ADON bit is set in the ADC Status and Control Register ($0E). PD4 and PD5 becomes VRL and VRH respectively for the ADC reference voltage inputs. PD6 is configured as IRQ2 by setting IRQ2E in the Miscellaneous Control Register ($0C). See Section 3 for details on the I/O ports. OSC1 and OSC2 Connections The OSC1 and OSC2 pins are the connections for the on-chip oscillator — the following configurations are available: 1) A crystal or ceramic resonator as shown in Figure 2-1(a). 2) An external clock signal as shown in Figure 2-1(b). 3) RC options as shown in Figure 2-1(c) and Figure 2-1(d). TPG Freescale 2-2 PIN DESCRIPTIONS MC68HC05SR3 20 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM The external oscillator clock frequency, fOSC, is divided by two to produce the internal operating frequency, fOP. MCU OSC1 2 MCU OSC2 OSC1 OSC2 10MΩ Unconnected External Clock 25p 25p (b) External clock source connection (a) Crystal or ceramic resonator connections VDD MCU OSC1 OSC2 MCU OSC1 OSC2 R Unconnected (d) RC option 2 - internal resistor 25% to 50% accurate (c) RC option 1 - external resistor 10% to 25% accurate Figure 2-1 Oscillator Connections 2.2.1 Crystal Oscillator The circuit in Figure 2-1(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An external start-up resistor of approximately 10MΩ is needed between OSC1 and OSC2 for the crystal type oscillator. 2.2.2 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 2-1(b). TPG MC68HC05SR3 PIN DESCRIPTIONS Freescale 2-3 21 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 2.2.3 This configuration is intended to be the lowest cost option in applications where oscillator accuracy is not important. An internal constant current source and a capacitor have been integrated on-chip, connected between the OSC2 pin and VSS. Thus by either connecting a resistor to VDD from OSC2 or by putting a wire strap between OSC1 and OSC2 self-oscillations at the frequency as shown in Figure 2-2 and Figure 2-3 can be induced. Oscillator Frequency (MHz) 4.0 3.5 3.0 2.5 2.0 1.5 30 40 50 60 70 80 90 100 110 Resistance (KΩ) Figure 2-2 Typical Oscillator Frequency for Selected External Resistor T=0°C 2.25 Oscillator Frequency (MHz) 2 RC Oscillator Option 2.00 T=25°C 1.75 T=50°C 1.50 1.25 1.00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) Figure 2-3 Typical Oscillator Frequency for Wire-Strap Connection TPG Freescale 2-4 PIN DESCRIPTIONS MC68HC05SR3 22 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM 2.3 Pin Assignments 2 VSS 1 40 PA7 RESET 2 39 PA6 IRQ 3 38 PA5 VDD 4 37 PA4 OSC1 5 36 PA3 OSC2 6 35 PA2 VPP 7 34 PA1 TIMER 8 33 PA0 PC0 9 32 PB7 PC1 10 31 PB6 PC2 11 30 PB5 PC3 12 29 PB4 PC4 13 28 PB3 PC5 14 27 PB2 PC6 15 26 PB1 PC7 16 25 PB0 PD7 17 24 PD0/AN0 PD6/IRQ2 18 23 PD1/AN1 PD5/VRH 19 22 PD2/AN2 PD4/VRL 20 21 PD3/AN3 Figure 2-4 Pin Assignment for 40-pin PDIP TPG MC68HC05SR3 PIN DESCRIPTIONS Freescale 2-5 23 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM 2 VSS(INT) VSS(EXT) RESET IRQ VDD OSC1 OSC2 VPP TIMER PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD7 PD6/IRQ2 PD5/VRH PD4/VRL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 44 43 42 41 40 39 38 37 36 35 34 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 NC Figure 2-5 Pin Assignment for 42-pin SDIP 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 VDD VSS PB0 PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/VRL PD5/VRH PD6/IRQ2 PD7 OSC2 VPP TIMER PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 12 13 14 15 16 17 18 19 20 21 22 PA3 PA4 PA5 PA6 PA7 VSS(INT) VSS(EXT) RESET IRQ VDD OSC1 Figure 2-6 Pin Assignment for 44-pin QFP TPG Freescale 2-6 PIN DESCRIPTIONS MC68HC05SR3 24 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 3 3 INPUT/OUTPUT PORTS The MC68HC05SR3 has 32 bidirectional I/O lines, arranged as four 8-bit I/O ports (Port A, B, C, and D). The individual bits in these ports are programmable as either inputs or outputs under software control by the Data Direction Registers (DDRs). All port pins each has an associated 20KΩ pull-up resistor, which can be connected/disconnected under software control. Also, each port pin is capable of sinking and driving a maximum current of 10mA (e.g. direct drive for LEDs). Port A can also be configured for keyboard interrupts. 3.1 Parallel Ports Port A, B, C, and D are 8-bit bidirectional ports. Each Port pin is controlled by the corresponding bits in a Data Direction Register and a Data Register as shown in Figure 3-1. The functions of the I/O pins are summarized in Table 3-1. Table 3-1 I/O Pin Functions 3.1.1 R/W DDR 0 0 The I/O pin is in input mode. Data is written into the output data latch. I/O Pin Function 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is in an output mode. The output data latch is read. Port Data Registers Each Port I/O pin has a corresponding bit in the Port Data Register. When a Port I/O pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. All Port I/O pins can drive a current of 10mA when programmed as outputs. When a Port pin is programmed as an input, any read of the Port Data Register will return the logic state of the corresponding I/O pin. The locations of the Data Registers for Port A, B, C, and D are at $00, $01, $02, and $03 respectively. The Port Data Registers are unaffected by reset. TPG MC68HC05SR3 INPUT/OUTPUT PORTS Freescale 3-1 25 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM DATA DIRECTION REGISTER BIT 3 INTERNAL MC68HC05 CONNECTIONS LATCHED OUTPUT DATA BIT OUTPUT I/O PIN INPUT REGISTER BIT INPUT I/O Figure 3-1 Port I/O Circuitry 3.1.2 Port Data Direction Registers Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, C, and D are located at $04, $05, $06 and, $07 respectively. The DDRs are cleared by reset. Note: 3.2 A “glitch” may occur on an I/O pin when selecting from an input to an output unless the data register is first preconditioned to the desired state before changing the corresponding DDR bit from a “0” to a “1”. Port A — Keyboard Interrupts (KBI) Port A is configured for use as keyboard interrupts when the KBIE bit is set in the Miscellaneous Control Register (MCR). Individual keyboard interrupt port pins are also maskable by setting corresponding bits in the Keyboard Interrupt Mask Register. See Section 5.2.2.4 for details on the keyboard interrupts. 3.3 PD0:PD5 — ADC Inputs When the ADON bit is set in the ADC Status and Control Register, PD0 to PD3 are configured as ADC inputs AN0 to AN3 respectively. PD4 and PD5 are configured as VRL and VRH respectively. See Section 7 for details on the Analog to Digital Converter. TPG Freescale 3-2 INPUT/OUTPUT PORTS MC68HC05SR3 26 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM 3.4 PD6 — IRQ2 The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt IRQ2 behaves similar to IRQ except it is edge-triggered only. 3 See Section 5.2.2.2 for details on the external interrupt IRQ2. 3.5 Programmable Current Drive All I/O ports, when programmed as outputs, can source or sink a current of 10mA for driving LEDs directly. By setting the PIL bit in the Port Option Register (at $0A), PB5-PB7 can be programmed to a low-current mode that source or sink only a current of 2mA when programmed as output. This allows a direct drive to low current LEDs. best case 13 12 11 typical 10 All ports 9 worst case IOL (mA) 8 7 6 5 PB5-PB7 in low current mode 4 best case 3 typical worst case 2 1 0 0 1 2 3 4 5 VOL (volts) Figure 3-2 Typical IOL vs VOL @VDD =5V Note: Although the ports each has high current drive capability, designs should limit the total port currents to not more than 100mA. TPG MC68HC05SR3 INPUT/OUTPUT PORTS Freescale 3-3 27 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 0 1 2 VOH (volts) 3 4 5 0 –1 3 –2 worst case –3 typical –4 best case PB5-PB7 in low current mode –5 IOH (mA) –6 –7 –8 –9 worst case All ports –10 –11 typical –12 –13 –14 best case –15 Figure 3-3 Typical IOH vs VOH @VDD =5V IOL (mA) All ports 5 best case 4 typical 3 worst case 2 best case typical 1 worst case PB5-PB7 in low current mode 0 0 1 VOL (volts) 2 3 Figure 3-4 Typical IOL vs VOL @VDD =3V TPG Freescale 3-4 INPUT/OUTPUT PORTS MC68HC05SR3 28 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM VOH (volts) 0 1 2 3 0 PB5-PB7 in low current mode worst case typical –1 3 best case IOH (mA) –2 –3 worst case –4 typical All ports –5 best case Figure 3-5 Typical IOL vs VOL @VDD =3V 3.6 Programmable Pull-Up Devices Ports B, C, and D have 20KΩ pull-up resistors, which can be connected or disconnected, by setting appropriate bits in the Port Option Register (at $0A). 3.6.1 Port Option Register Address bit 7 Port Option Register (POPR) $0A bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset PIL PDP PCP PBP PB1 PB0 0000 0000 PIL — PB5:PB7 current drive select 1 (set) – 0 (clear) – PB5-PB7 are configured to 2mA drive port. PB5-PB7 are configured to 10mA drive port. PDP — Port D Pull-up 1 (set) – 0 (clear) – The internal 20KΩ pull-up resistors are connected to the inputs of Port D. No pull-up resistor is connected to the inputs of Port D. TPG MC68HC05SR3 INPUT/OUTPUT PORTS Freescale 3-5 29 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM PCP — Port C Pull-up 1 (set) 3 – 0 (clear) – The internal 20KΩ pull-up resistors are connected to the inputs of Port C. No pull-up resistor is connected to the inputs of Port C. PBP — PB2:PB7 Pull-up 1 (set) – 0 (clear) – The internal 20KΩ pull-up resistors are connected to the inputs of PB2-PB7. No pull-up resistor is connected to the inputs of PB2-PB7. PB1 — PB1 pull-up 1 (set) – 0 (clear) – The internal 20KΩ pull-up resistor is connected to the input of PB1. No pull-up resistor is connected to the input of PB1. PB0 — PB0 pull-up 1 (set) – 0 (clear) – The internal 20KΩ pull-up resistor is connected to the input of PB0. No pull-up resistor is connected to the input of PB0. TPG Freescale 3-6 INPUT/OUTPUT PORTS MC68HC05SR3 30 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 4 MEMORY AND REGISTERS 4 The MC68HC05SR3/MC68HC705SR3 has 8K-bytes of addressable memory, consisting of I/O registers, user ROM/EPROM, user RAM, and self-check/bootstrap ROM. Figure 4-1 shows the memory map for MC68HC05SR3/MC68HC705SR3 device. 4.1 I/O Registers The I/O, status and control registers are located within the first 16 bytes of memory, from $0000 to $000F. These are shown in the memory map in Figure 4-1; and a summary of the register outline is shown in Table 4-1. Reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. 4.2 RAM The user RAM (including the stack) consists of 192 bytes. It is separated into two blocks at locations $0010 to $008F, and $00C0 to $00FF. The stack begins at address $00FF and proceeds down to $00C0. 4.3 ROM The user ROM consists of 3840 bytes of memory, from $1000 to $1EFF. Twelve bytes of user vectors are also available, from $1FF4 to $1FFF. On the MC68HC705SR3, this ROM is replaced by EPROM. Note: Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. TPG MC68HC05SR3 MEMORY AND REGISTERS Freescale 4-1 31 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM 4.4 Memory Map Figure 4-1 shows the memory map for MC68HC05SR3/MC68HC705SR3 device. $0000 4 0 I/O 16 Bytes $000F $0010 Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register Timer Data Register Timer Control Register Port Option Register Keyboard Interrupt Mask Register Miscellaneous Control Register EPROM Programming Control Register ADC Status and Control Register ADC Data Register Ports 8 Bytes User RAM 128 Bytes Timer Registers 2 Bytes Port Option Register KBI Register Misc. Register EPROM Register $008F $0090 Unused ADC Registers 2 Bytes $00BF $00C0 15 Stack 64 Bytes $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $00FF $0100 Unused $0FFF $1000 User ROM/EPROM 3840 Bytes $1EFF $1F00 Self-Check/Bootstrap 240 Bytes $1FEF $1FF0 $1FFF User Vectors 12 Bytes $1FF0 $1FF2 $1FF4 $1FF6 $1FF8 $1FFA $1FFC $1FFE Reserved Reserved KBI Timer IRQ2 IRQ SWI RESET Figure 4-1 MC68HC05SR3/MC68HC705SR3 Memory Map TPG Freescale 4-2 MEMORY AND REGISTERS MC68HC05SR3 32 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM 4.5 I/O Registers Summary Table 4-1 shows a summary of I/O registers for MC68HC05SR3/MC68HC705SR3 device. Table 4-1 MC68HC05SR3/MC68HC705SR3 I/O Registers Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Port A Data $00 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 unaffected Port B Data $01 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 unaffected Port C Data $02 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 unaffected Port D Data $03 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 unaffected Port A Data Direction $04 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0000 0000 Port B Data Direction $05 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0000 0000 Port C Data Direction $06 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0000 0000 Port D Data Direction $07 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0000 0000 Register Name Timer Data (TDR) $08 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 1111 1111 Timer Control (TCR) $09 TIF TIM TCEX TINE PRER PR2 PR1 PR0 0100 -000 --00 0000 Port Option (POPR) $0A PIL PDP PCP PBP PB1 PB0 KBI Mask (KBIM) $0B KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 0000 0000 Miscellaneous Control (MCR) $0C KBIE KBIC INTO INTE LVRE SM EPROM Programming Control $0D ADC Status and Control (ADSCR) $0E ADC Data (ADDR) $0F Mask Option (MOR) $0FFF COCO ADRC ADON AD7 AD6 4 IRQ2F IRQ2E 0001 0000 ELAT PGM ---- --00 CH2 CH1 CH0 000- -000 AD5 AD4 AD3 AD2 AD1 AD0 uuuu uuuu SMD SEC TMR2 TMR1 TMR0 RC unaffected TPG MC68HC05SR3 MEMORY AND REGISTERS Freescale 4-3 33 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 4 THIS PAGE LEFT BLANK INTENTIONALLY TPG Freescale 4-4 MEMORY AND REGISTERS MC68HC05SR3 34 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 5 RESETS AND INTERRUPTS This section describes the reset and interrupt functions on the MCU. 5.1 5 RESETS The MC68HC05SR3 can be reset in three ways: • by initial power-on reset function, (POR), • by an active low input to the RESET pin, (RESET), and • by a Low Voltage Reset, (LVR). All of these resets will cause the program to go to the starting address, specified by the contents of memory locations $1FFE and $1FFF, and cause the interrupt mask (I-bit) of the Condition Code Register (CCR) to be set. 5.1.1 Power-On Reset (POR) The power-on reset (POR) occurs on power-up to allow the clock oscillator to stabilize. The POR is strictly for power-up conditions, and should not be used to detect any drops in power supply voltage. There is an oscillator stabilization delay of tPORL internal processor bus clock cycles after the oscillator becomes active. The RESET pin will be pulled down internally during these cycles. If the RESET pin is low (by external circuit) at the end of the tPORL period, the processor remains in the reset condition until RESET goes high. 5.1.2 RESET Pin The RESET input pin is used to reset the MCU to provide an orderly software start-up procedure. When using the external reset, the RESET pin must stay low for a minimum of 1.5tCYC. The RESET pin is connected to a Schmitt Trigger circuit as part of its input to improve noise immunity. TPG MC68HC05SR3 RESETS AND INTERRUPTS Freescale 5-1 35 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM 5.1.3 Low Voltage Reset (LVR) When the LVR function is enabled, an internal reset is generated if the supply voltage, VDD, drops below VLVR. (See Section 11 for value of VLVR). This LVR function is enabled by setting the LVRE bit in the Miscellaneous Control Register. Address bit 7 Miscellaneous Control Register 5 $0C KBIE bit 6 bit 5 bit 4 bit 3 bit 2 KBIC INTO INTE LVRE SM bit 1 bit 0 State on reset IRQ2F IRQ2E 0001 0000 LVRE — Low Voltage Reset Enable 1 (set) – Low Voltage Reset function enabled. 0 (clear) – Low Voltage Reset function disabled. Note: The LVR function should not be enabled when operating VDD =3V. 5.2 INTERRUPTS The MC68HC05SR3 MCU can be interrupted by different sources – four maskable hardware interrupt and one non-maskable software interrupt: • Software Interrupt Instruction (SWI) • External signal on IRQ pin • External signal on IRQ2 pin • TImer Overflow • Keyboard If the interrupt mask bit (I-bit) in the Condition Code Register (CCR) is set, all maskable interrupts are disabled. Clearing the I-bit enables interrupts. Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Table 5-1 shows the relative priority of all the possible interrupt sources. Figure 5-2 shows the interrupt processing flow. TPG Freescale 5-2 RESETS AND INTERRUPTS MC68HC05SR3 36 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM $00C0 (BOTTOM OF STACK) $00C1 $00C2 UNSTACKING ORDER • • • • • • 5 1 4 2 ACCUMULATOR 3 3 INDEX REGISTER 2 4 PROGRAM COUNTER (HIGH BYTE) 1 5 PROGRAM COUNTER (LOW BYTE) CONDITION CODE REGISTER STACKING ORDER 5 • • • • • • $00FD $00FE $00FF (TOP OF STACK) Figure 5-1 Interrupt Stacking Order Table 5-1 Reset/Interrupt Vector Addresses Register Flag Name Interrupt CPU Interrupt Vector Address Priority — — Reset RESET $1FFE-$1FFF highest — — Software SWI $1FFC-$1FFD — — External Interrupt IRQ $1FFA-$1FFB — — External Interrupt 2 IRQ2 $1FF8-$1FF9 TCR TIF Timer Overflow TIF $1FF6-$1FF7 — — Keyboard KBI $1FF4-$1FF5 5.2.1 lowest Non-maskable Software Interrupt (SWI) The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. TPG MC68HC05SR3 RESETS AND INTERRUPTS Freescale 5-3 37 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM From RESET Y Is I-bit Set? N IRQ External Interrupt ? Y Clear External Interrupt Request Latch N 5 IRQ2 External Interrupt ? Y N Timer Interrupt? Y PC → (SP, SP–1) X → (SP–2) A → (SP–3) CC→ (SP–4) N Set I-bit in CCR Keyboard Interrupt? Y N Load Interrupt Vectors to Program Counter Fetch Next Instruction SWI Instruction? Y N RTI Instruction? Y Restore Registers from Stack CC, A, X, PC N Execute Instruction Figure 5-2 Hardware Interrupt Processing Flowchart TPG Freescale 5-4 RESETS AND INTERRUPTS MC68HC05SR3 38 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM 5.2.2 Maskable Hardware Interrupts If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the I-bit allows interrupt processing to occur. Note: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared. 5.2.2.1 External Interrupt (IRQ) The external interrupt IRQ is controlled by two bits in the Miscellaneous Control Register ($0C). Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 bit 5 bit 4 bit 3 bit 2 KBIC INTO INTE LVRE SM bit 1 bit 0 5 State on reset IRQ2F IRQ2E 0001 0000 INTE — INTerrupt Enable 1 (set) – 0 (clear) – External interrupt IRQ is enabled. External interrupt is disabled. The external IRQ is default enabled at power-on reset. INTO — INTerrupt Option 1 (set) – Negative-edge sensitive triggering for IRQ. 0 (clear) – Negative-level sensitive triggering for IRQ. When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. When the interrupt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the Condition Code Register is set. This masks further interrupts until the present one is serviced. The service routine address is specified by the contents in $1FFA-$1FFB. The interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are spaced far enough apart to be serviced. The minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The second configuration shows several interrupt lines wired-OR to perform the interrupt at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. TPG MC68HC05SR3 RESETS AND INTERRUPTS Freescale 5-5 39 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM INTO BIT VDD VDD 100K IRQ & Q D C + & Q & R EXTERNAL INTERRUPT REQUEST I-BIT (CCR) POWER-ON RESET 5 + EXTERNAL RESET EXTERNAL INTERRUPT BEING SERVICED (IRQ ONLY) (a) Interrupt Function Diagram EDGE SENSITIVE TRIGGER CONDITION IRQ tILIH tILIL The minimum pulse width tILIH is either 125ns (VDD=5V) or 250ns (VDD=3V). The period tILIL should not be less than the number of tcyc cycles it takes to execute the interrupt service routine plus 21 tCYC cycles. tILIH LEVEL SENSITIVE TRIGGER CONDITION Wired ORed Interrupt signals if after servicing an interrupt the external interrupt pin (IRQ) remains low, then the next interrupt is recognized. Normally used with pull-up resistors for wired-OR connection. IRQ (b) Interrupt Mode Diagram Figure 5-3 External Interrupt TPG Freescale 5-6 RESETS AND INTERRUPTS MC68HC05SR3 40 05SR3.Book Page 7 Thursday, August 4, 2005 1:08 PM 5.2.2.2 External Interrupt 2 (IRQ2) The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt IRQ2 behaves similar to IRQ except it is edge-triggered only. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 bit 5 bit 4 bit 3 bit 2 KBIC INTO INTE LVRE SM bit 1 bit 0 State on reset IRQ2F IRQ2E 0001 0000 IRQ2E — IRQ2 Enable – External interrupt IRQ2 is enabled. 0 (clear) – External interrupt IRQ2 is disabled. 1 (set) 5 IRQ2F — IRQ2 Flag clear This is a write-only bit and always read as “0”. 1 (set) – 0 (clear) – Writing a “1” clears the IRQ2 interrupt latch. Writing a “0” has no effect. When a negative-edge is sensed on IRQ2 pin, an external interrupt occurs. The actual processor interrupt is generated only if the I-bit in the CCR is also cleared. When the interrupt is recognized, the current state of the processor is pushed onto the stack and the I-bit in the CCR is set. This masks further interrupts until the present one is serviced. The latch for IRQ2 is cleared by reset or by writing a “1” to the IRQ2F bit in the MCR in the interrupt service routine. The interrupt service routine address is specified by the contents in $1FF8-$1FF9. 5.2.2.3 Timer Interrupt The timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. The interrupt enable and flag for the timer interrupt are located in the Timer Control Register. Address bit 7 Timer Control Register (TCR) $09 TIF bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset TIM TCEX TINE PREP PR2 PR1 PR0 0100 -100 TIM — Timer Interrupt Mask 1 (set) – Timer interrupt is disabled. 0 (clear) – Timer interrupt is enabled. TPG MC68HC05SR3 RESETS AND INTERRUPTS Freescale 5-7 41 05SR3.Book Page 8 Thursday, August 4, 2005 1:08 PM TIF — Timer Interrupt Flag 1 (set) – 0 (clear) – A timer interrupt (timer overflow) has occurred. A timer interrupt (timer overflow) has not occurred. The I-bit in the CCR must be cleared in order for the timer interrupt to be processed. The interrupt will vector to the interrupt service routine at the address specified by the contents in $1FF6-$0FF7. 5.2.2.4 5 Keyboard Interrupt (KBI) Keyboard interrupt function is associated with Port A pins. The keyboard interrupt function is enabled by setting the keyboard interrupt enable bit KBIE (bit 7 of MCR at $0C) and the individual enable bits KBE0-KBE7 (bits 0-7 of KBIM at $0B). When the KBEx bit is set, the corresponding Port A pin will be configured as an input pin, regardless of the DDR setting, and a 20KΩ pull-up resistor is connected to the pin, as shown in Figure 5-4. When a high to low transition is sensed on the pin, a keyboard interrupt will be generated. An interrupt to the CPU will be generated if the I-bit in the CCR is cleared. The keyboard interrupt flag should be cleared in the interrupt service routine (by writing a “1” to KBIC bit in the MCR at $0C) after the key is debounced. Debouncing will avoid spurious false triggering. The keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is specified by the contents in $1FF4-$1FF5. KBEx of KBIM VDD & Keyboard Interrupt request & & & 20KΩ KBIE bit of MCR ($0C bit 7) 1 input for each of PA0-PA7 (8 input NAND) & DDR0-DDR7 Pad Logic PAx Internal Data bit (0-7), Port A Figure 5-4 Keyboard Interrupt Circuitry TPG Freescale 5-8 RESETS AND INTERRUPTS MC68HC05SR3 42 05SR3.Book Page 9 Thursday, August 4, 2005 1:08 PM The KBIE bit in the Miscellaneous Control Register controls the master enable for the keyboard interrupts. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 bit 5 bit 4 bit 3 bit 2 KBIC INTO INTE LVRE SM bit 1 State on reset bit 0 IRQ2F IRQ2E 0001 0000 KBIE — KeyBoard Interrupt Enable 1 (set) – Keyboard interrupts master enabled. 0 (clear) – Keyboard interrupts master disabled. 5 KBIC — KeyBoard Interrupt Clear This is a write-only bit and always read as “0”. 1 (set) – 0 (clear) – Writing a “1” clears the keyboard interrupt latch. Writing a “0” has no effect. The Keyboard Interrupt Mask Register (KBIMR) masks individual keyboard interrupt pins and setting of the internal pull-up resistors on port A. Address bit 7 KBIMR $0B KBE7 State on reset bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 0000 0000 KBEx — PAx Keyboard Interrupt Enable 1 (set) – Keyboard interrupt enabled for PAx. A 20KΩ internal pull-up resistor is connected. High to low transition on PAx will cause a keyboard interrupt. 0 (clear) – Keyboard interrupt for PAx pin is masked. Any transitions on PAx will not set any flags. TPG MC68HC05SR3 RESETS AND INTERRUPTS Freescale 5-9 43 05SR3.Book Page 10 Thursday, August 4, 2005 1:08 PM 5 THIS PAGE LEFT BLANK INTENTIONALLY TPG Freescale 5-10 RESETS AND INTERRUPTS MC68HC05SR3 44 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 6 TIMER This section describes the operation of the 8-bit count-down timer in the MC68HC05SR3. 6.1 Timer Overview 6 The MC68HC05SR3 timer block diagram is shown in Figure 6-1. The timer contains a single 8-bit software programmable count-down counter with a 7-bit software selectable prescaler. The counter may be preset under software control and decrements towards zero. When the counter decrements to zero, the timer interrupt flag (TIF bit in Timer Control Register, TCR) is set. Once timer interrupt flag is set, an interrupt is generated to the CPU only if the TIM bit in the TCR and I-bit in the CCR are cleared. When a interrupt is recognized, after completion of the current instruction, the processor proceeds to store the appropriate registers on the stack and then fetches the timer interrupt vector from locations $1FF6 and $1FF7. The counter continues to count after it reaches zero, allowing the software to determine the number of internal or external clocks since the timer interrupt flag was set. The counter may be read at any time by the processor without disturbing the count. The contents of the counter become stable prior to the read portion of a cycle and do not change during the read. The timer interrupt flag remains set until cleared by the software. If a write occurs before the timer interrupt is served, the interrupt is lost. The timer interrupt flag may also be used as a scanned status bit in a non-interrupt mode of operation. The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit 0, 1, 2 (PR0, PR1, PR2) of TCR are programmed to choose the appropriate prescaler output which is used as the 8-bit counter clock input. The processor cannot write into or read from the prescaler; however, its contents can be cleared to all zeros by writing to the PRER bit in the TCR. This will allow for truncation-free counting. The input clock for the timer sub-system is selectable from internal, external, or a combination of internal and external sources. The TCEX and TINE bits in the Timer Control Register selects the timer input clock. TPG MC68HC05SR3 TIMER Freescale 6-1 45 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM Timer Data Register ($08) 8 8 8-bit count-down timer counter 7-bit prescaler counter 6 Internal Bus RST 8 Prescaler Select Logic (8 to 1 MUX) Overflow Detect Circuit Interrupt Circuit 8 TIF TIM TCEX TINE PRER PR2 PR1 PR0 Timer Control Register ($09) TIMER Clock Source Logic Internal Processor Clock TCEX TINE 0 0 Internal clock to timer Clock Source 0 1 “AND” of internal clock and TIMER pin to timer 1 0 Input clock to timer disabled 1 1 TIMER pin to timer Figure 6-1 Timer Block Diagram TPG Freescale 6-2 TIMER MC68HC05SR3 46 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM 6.2 Timer Control Register (TCR) The TCR enables the software to control the operation of the timer. Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $09 TIF TIM TCEX TINE PRER PRE2 PRE1 PRE0 0100 -100 TIF — Timer Interrupt Flag 1 (set) – 0 (clear) – The timer has reached a count of zero. The timer has not reached a count of zero. The timer interrupt flag is set when the 8-bit counter decrements to zero. This bit is cleared on reset, or by writing a “0” to the TIF bit. 6 TIM — Timer Interrupt Mask 1 (set) – 0 (clear) – Timer interrupt request to the CPU is masked (disabled). Timer interrupt request to the CPU is not masked (enabled). A reset sets this bit to one; it must then be cleared by software to enable the timer interrupt to the CPU. This timer interrupt mask only masks timer interrupt request to the CPU, and does not affect counting of the 8-bit counter or the setting of TIF. TCEX — Timer Clock EXternal TINE — Timer INput Enable These two bits selects the source of the timer clock. Reset or power-on clears these bits to zero. TCEX TINE 0 0 Clock Source Internal clock to timer 0 1 “AND” of internal clock and TIMER pin to timer 1 0 Input clock to timer disabled 1 1 TIMER pin to timer PRER — PREscaler Reset Writing a “1” to this write-only bit will reset the prescaler to zero, which is necessary for any new counts set by writing to the Timer Data Register.This bit always reads as zero, and is not affected by reset. TPG MC68HC05SR3 TIMER Freescale 6-3 47 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM PR2:PR0 These three bits enable the program to select the division ratio of the prescaler. On reset, these three bits are set to “100”, which corresponds to a division ratio of 16. PR2 PR1 PR0 Divide Ratio 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 6 6.3 Timer Data Register (TDR) The TDR is a read/write register which contains the current value of the 8-bit count-down timer counter when read. Reading this register does not disturb the counter operation. Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $08 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 1111 1111 6.4 Operation during Low Power Modes The timer ceases counting in STOP mode. When STOP mode is exited by an external interrupt (IRQ or IRQ2), the internal oscillator will resume its operation, followed by internal processor stabilization delay. The timer is then cleared to zero and resumes its operation. The TIF bit in the TCR will be set. To avoid generating a timer interrupt when exiting STOP mode, it is recommended to set the TIM bit prior entering STOP mode. After exiting STOP mode TIF bit can then be cleared. The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. TPG Freescale 6-4 TIMER MC68HC05SR3 48 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 7 ANALOG TO DIGITAL CONVERTER The analog to digital converter system consists of a single 8-bit successive approximation converter and an 8-channel analog multiplexer. Four of the channels are available for analog inputs, and the other four channels are dedicated to internal test functions. There is one 8-bit ADC Data Register ($0F) and one 8-bit ADC Status and Control register ($0E). The reference supply, VRL and VRH for the converter uses two input pins (shared with PD4 and PD5) instead of the power supply lines, because drops caused by loading in the power supply lines would degrade the accuracy of the analog to digital conversion. An internal RC oscillator is available if the bus speed is low enough to degrade the ADC accuracy. An ADON bit allows the ADC to be switched off to reduce power consumption, which is particularly useful in the Wait mode. VRL Successive approximation register and control Analog MUX (Channel assignment) VRH VRH VRL 8-bit capacitive DAC with sample and hold AN0 AN1 AN2 AN3 7 Result 8 ADC Status and Control Register ($0E) CH0 CH1 CH2 ADON ADRC COCO (VRH +VRL)/4 (VRH +VRL)/2 ADC Data Register ($0F) Figure 7-1 ADC Converter Block Diagram TPG MC68HC05SR3 ANALOG TO DIGITAL CONVERTER Freescale 7-1 49 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM 7.1 ADC Operation As shown in Figure 7-1, the ADC consists of an analog multiplexer, an 8-bit digital to analog capacitor array, a comparator and a successive approximation register (SAR). There are eight options that can be selected by the multiplexer; the AN0 to AN3 input pins, VRH, VRL, (VRH +VRL)/4, or (VRH +VRL)/2. Selection is done via the CHx bits in the ADC Status and Control Register. AN0 to AN3 are input points for ADC conversion operations; the others are reference points which can be used for test purposes. The converter uses VRH and VRL as reference voltages. An input voltage equal to or greater than VRH converts to $FF. An input voltage equal to or less than VRL, but greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input source should use VRH as the supply voltage and should be referenced to VRL for the ratiometric conversions. To maintain full accuracy of the ADC, the following should be noted: 1) VRH should be equal to or less than VCC; 2) VRL should be equal to or greater than VSS but less than maximum specifications; and 7 3) VRH–VRL should be equal to or greater than 4 Volts. The ADC reference inputs (VRH and VRL) are applied to a precision internal digital to analog converter. Control logic drives this D/A converter and the analog output is successively compared with the selected analog input sampled at the beginning of the conversion. The conversion is monotonic with no missing codes. The result of each successive comparison is stored in the successive approximation register (SAR) and, when the conversion is complete, the contents of the SAR are transferred to the read-only ADC Data Register ($0F), and the conversion complete flag, COCO, is set in the ADC Status and Control Register ($0E). Warning: Any write to the ADC Status and Control Register will abort the current conversion, reset the conversion complete flag (COCO) and a new conversion starts on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared, thus the ADC is disabled. TPG Freescale 7-2 ANALOG TO DIGITAL CONVERTER MC68HC05SR3 50 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM 7.2 ADC Status and Control Register (ADSCR) The ADSCR is a read/write register containing status and control bits for the ADC. Address bit 7 bit 6 bit 5 $0E COCO ADRC ADON bit 4 bit 3 bit 2 bit 1 bit 0 State on reset CH2 CH1 CH0 000- -000 COCO — COnversion COmplete 1 (set) – 0 (clear) – An ADC conversion has completed; ADC Data Register ($0F) contains valid conversion result. ADC conversion not completed. This read-only status bit is set when a conversion is completed, indicating that the ADC Data Register contains a valid result. This COCO bit is cleared either by a write to the ADSCR or a read of the ADC Data Register. Once the COCO bit is cleared, a new conversion automatically starts. If the COCO bit is not cleared, conversions are initiated every 32 cycles. In this continuous conversion mode the ADC Data Register is refreshed with new data, every 32 cycles, and the COCO bit remains set. 7 ADRC — ADC RC Oscillator Control 1 (set) – 0 (clear) – ADC uses RC oscillator as clock source. ADC uses internal processor clock as clock source. The RC oscillator option must be used if the internal processor is running below 1MHz. A stabilization time of typically 1ms is required when switching to the RC oscillator option. ADON — ADC On 1 (set) – 0 (clear) – ADC is switched ON. ADC is switched OFF. When the ADC is turned from OFF to ON, it requires a time tADON for the current sources to stabilize. During this time ADC conversion results may be inaccurate. Switching the ADC off disables the internal charge pump and RC oscillator (if selected by ADRC=1), and hence saving power. CH2:CH0 — Channel Select Bits These three bits selects one of eight ADC channels for the conversion. Channels 0 to 3 correspond to inputs AN0-AN3 on port pins PD0-PD3 respectively. Channels 4 and 5 are the ADC reference inputs VRH and VRL, on port pins PD4 and PD5 respectively. Channels 6 and 7 are used for internal reference points. Table 7-1 shows the signals selected by the channel select bits. TPG MC68HC05SR3 ANALOG TO DIGITAL CONVERTER Freescale 7-3 51 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM Table 7-1 ADC Channel Assignments CH2 CH1 CH0 Channel Selected Signal 0 0 0 0 AD0 on PD0 0 0 1 1 AD1 on PD1 0 1 0 2 AD2 on PD2 0 1 1 3 AD3 on PD3 1 0 0 4 VRH 1 0 1 5 VRL 1 1 0 6 (VRH–VRL) ÷ 4 1 1 1 7 (VRH–VRL) ÷ 2 Using a port D pin as both an analog and digital input simultaneously is prohibited. When the ADC is enabled (ADON=1) and one of channels 0 to 5 is selected, the corresponding Port D pin will appear as a logic zero when read from the Port Data Register. 7 7.3 ADC Data Register (ADDR) The ADDR stores the result of a valid ADC conversion when the COCO bits is set in ADSCR. Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset $0F AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 uuuu uuuu 7.4 ADC during Low Power Modes The ADC continues normal operation in WAIT mode. To reduce power consumption in WAIT mode, the ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the ADC is in use and the internal bus clock is above 1MHz, it is recommended that the ADRC bit be cleared. In STOP mode, the ADC stops operation. TPG Freescale 7-4 ANALOG TO DIGITAL CONVERTER MC68HC05SR3 52 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 8 CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05SR3. 8.1 Registers The MCU contains five registers, as shown in the programming model of Figure 8-1. The interrupt stacking order is shown in Figure 8-2. 7 0 7 0 8 Accumulator Index register 15 7 0 Program counter 15 7 0 0 0 0 0 0 0 0 0 1 1 7 0 1 1 1 H I N Z C Stack pointer Condition code register Carry / borrow Zero Negative Interrupt mask Half carry Figure 8-1 Programming model 8.1.1 Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-1 53 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM Unstack Condition code register Accumulator Index register Program counter high Program counter low Stack 0 Interrupt Increasing memory address Return 7 Decreasing memory address Figure 8-2 Stacking order 8.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. 8.1.3 Program counter (PC) The program counter is a 16-bit register, which contains the address of the next byte to be fetched. 8 8.1.4 Stack pointer (SP) The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. 8.1.5 Condition code register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. TPG Freescale 8-2 CPU CORE AND INSTRUCTION SET MC68HC05SR3 54 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM Interrupt (I) When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates. 8.2 Instruction set The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: – Register/memory – Read/modify/write – Branch – Bit manipulation – Control 8 The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 8-1. TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-3 55 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 8.2.1 Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 8-2 for a complete list of register/memory instructions. 8.2.2 Branch instructions These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 8-3. 8.2.3 8 Bit manipulation instructions The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 8-4. 8.2.4 Read/modify/write instructions These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 8-5 for a complete list of read/modify/write instructions. 8.2.5 Control instructions These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 8-6 for a complete list of control instructions. 8.2.6 Tables Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 8-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 8-8). TPG Freescale 8-4 CPU CORE AND INSTRUCTION SET MC68HC05SR3 56 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM Table 8-1 MUL instruction X:A ← X*A Operation Multiplies the eight bits in the index register by the eight Description bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. H : Cleared I : Not affected N : Not affected Z : Not affected C : Cleared Condition codes Source MUL Form Addressing mode Cycles Bytes Opcode Inherent 11 1 $42 Table 8-2 Register/memory instructions Addressing modes Indexed (no offset) Opcode # Bytes # Cycles Opcode # Bytes # Cycles Opcode # Bytes # Cycles Opcode # Bytes # Cycles Opcode # Bytes # Cycles Indexed (16-bit offset) # Cycles Indexed (8-bit offset) # Bytes Extended Opcode Direct Mnemonic Immediate LDA A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 D6 3 5 Load X from memory LDX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 Store A in memory STA B7 2 4 C7 3 5 F7 1 4 E7 2 5 D7 3 6 Store X in memory STX BF 2 4 CF 3 5 FF 1 4 EF 2 5 DF 3 6 Add memory to A ADD AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 Add memory and carry to A ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5 Subtract memory SUB A0 2 2 B0 2 3 C0 3 4 F0 1 3 E0 2 4 D0 3 5 Subtract memory from A with borrow SBC A2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 D2 3 5 5 Function Load A from memory AND memory with A AND A4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 D4 3 OR memory with A ORA AA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5 Exclusive OR memory with A EOR A8 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 D8 3 5 Arithmetic compare A with memory CMP A1 2 2 B1 2 3 C1 3 4 F1 1 3 E1 2 4 D1 3 5 Arithmetic compare X with memory CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5 Bit test memory with A (logical compare) BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 D5 3 5 Jump unconditional JMP BC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4 Jump to subroutine JSR BD 2 5 CD 3 6 FD 1 5 ED 2 6 DD 3 7 8 TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-5 57 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM Table 8-3 Branch instructions Relative addressing mode Function 8 Mnemonic Opcode # Bytes # Cycles Branch always BRA 20 2 3 Branch never BRN 21 2 3 Branch if higher BHI 22 2 3 Branch if lower or same BLS 23 2 3 Branch if carry clear BCC 24 2 3 (Branch if higher or same) (BHS) 24 2 3 Branch if carry set BCS 25 2 3 (Branch if lower) (BLO) 25 2 3 Branch if not equal BNE 26 2 3 Branch if equal BEQ 27 2 3 Branch if half carry clear BHCC 28 2 3 Branch if half carry set BHCS 29 2 3 Branch if plus BPL 2A 2 3 Branch if minus BMI 2B 2 3 Branch if interrupt mask bit is clear BMC 2C 2 3 Branch if interrupt mask bit is set BMS 2D 2 3 Branch if interrupt line is low BIL 2E 2 3 Branch if interrupt line is high BIH 2F 2 3 Branch to subroutine BSR AD 2 6 Table 8-4 Bit manipulation instructions Addressing modes Bit set/clear Bit test and branch Function Mnemonic Opcode # Bytes # Cycles Opcode # Bytes # Cycles Branch if bit n is set BRSET n (n=0–7) 2•n 3 5 Branch if bit n is clear BRCLR n (n=0–7) 01+2•n 3 5 Set bit n BSET n (n=0–7) 10+2•n 2 5 Clear bit n BCLR n (n=0–7) 11+2•n 2 5 TPG Freescale 8-6 CPU CORE AND INSTRUCTION SET MC68HC05SR3 58 05SR3.Book Page 7 Thursday, August 4, 2005 1:08 PM Table 8-5 Read/modify/write instructions Addressing modes Inherent (X) Indexed (8-bit offset) Indexed (no offset) Opcode # Bytes # Cycles Opcode # Bytes # Cycles Opcode # Bytes # Cycles Opcode # Bytes # Cycles Opcode # Bytes # Cycles Direct Mnemonic Inherent (A) Increment INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6 Decrement DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6 Clear CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6 Complement COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 Negate (two’s complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 Rotate left through carry ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 Rotate right through carry ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 Logical shift left LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 Test for negative or zero TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5 Multiply MUL 42 1 11 Function 8 Table 8-6 Control instructions Inherent addressing mode Function Mnemonic Opcode # Bytes # Cycles Transfer A to X TAX 97 1 2 Transfer X to A TXA 9F 1 2 Set carry bit SEC 99 1 2 Clear carry bit CLC 98 1 2 Set interrupt mask bit SEI 9B 1 2 Clear interrupt mask bit CLI 9A 1 2 Software interrupt SWI 83 1 10 Return from subroutine RTS 81 1 6 Return from interrupt RTI 80 1 9 Reset stack pointer RSP 9C 1 2 No-operation NOP 9D 1 2 Stop STOP 8E 1 2 Wait WAIT 8F 1 2 TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-7 59 05SR3.Book Page 8 Thursday, August 4, 2005 1:08 PM Table 8-7 Instruction set Addressing modes Mnemonic INH IMM DIR EXT REL IX IX1 Condition codes IX2 BSC BTB H I N Z C ADC ◊ • ◊ ◊ ◊ ADD ◊ • ◊ ◊ ◊ AND • • ◊ ◊ • ASL • • ◊ ◊ ◊ ASR • • ◊ ◊ ◊ BCC • • • • • BCLR • • • • • BCS • • • • • BEQ • • • • • BHCC • • • • • BHCS • • • • • BHI • • • • • BHS • • • • • BIH • • • • • BIL • • • • • BIT • • ◊ ◊ • BLO • • • • • BLS • • • • • BMC • • • • • BMI • • • • • BMS • • • • • BNE • • • • • BPL • • • • • BRA • • • • • BRN • • • • • BRCLR • • • • ◊ BRSET • • • • ◊ BSET • • • • • BSR • • • • • CLC • • • • 0 • 8 CLI • 0 • • CLR • • 0 1 • CMP • • ◊ ◊ ◊ Address mode abbreviations BSC Bit set/clear IMM Immediate BTB Bit test & branch IX Indexed (no offset) DIR Direct IX1 EXT Extended IX2 INH Inherent REL Condition code symbols ◊ Tested and set if true, cleared otherwise Interrupt mask • Not affected Negate (sign bit) ? Load CCR from stack Z Zero 0 Cleared C Carry/borrow 1 Set H Half carry (from bit 3) Indexed, 1 byte offset I Indexed, 2 byte offset N Relative Not implemented TPG Freescale 8-8 CPU CORE AND INSTRUCTION SET MC68HC05SR3 60 05SR3.Book Page 9 Thursday, August 4, 2005 1:08 PM Table 8-7 Instruction set (Continued) Addressing modes Mnemonic INH IMM DIR EXT REL IX IX1 Condition codes IX2 BSC BTB H I N Z COM • • ◊ ◊ C 1 CPX • • ◊ ◊ ◊ DEC • • ◊ ◊ • EOR • • ◊ ◊ • INC • • ◊ ◊ • JMP • • • • • JSR • • • • • LDA • • ◊ ◊ • LDX • • ◊ ◊ • LSL • • ◊ ◊ ◊ ◊ LSR • • 0 ◊ MUL 0 • • • 0 NEG • • ◊ ◊ ◊ • NOP • • • • ORA • • ◊ ◊ • ROL • • ◊ ◊ ◊ ROR • • ◊ ◊ ◊ RSP • • • • • RTI ? ? ? ? ? RTS • • • • • SBC • • ◊ ◊ ◊ SEC • • • • 1 SEI • 1 • • • STA • • ◊ ◊ • STOP • 0 • • • STX • • ◊ ◊ • SUB • • ◊ ◊ ◊ SWI • 1 • • • TAX • • • • • TST • • ◊ ◊ • TXA • • • • • WAIT • 0 • • • Address mode abbreviations BSC Bit set/clear IMM Immediate BTB Bit test & branch IX Indexed (no offset) DIR Direct IX1 EXT Extended IX2 INH Inherent REL 8 Condition code symbols ◊ Tested and set if true, cleared otherwise Interrupt mask • Not affected Negate (sign bit) ? Load CCR from stack Z Zero 0 Cleared C Carry/borrow 1 Set H Half carry (from bit 3) Indexed, 1 byte offset I Indexed, 2 byte offset N Relative Not implemented TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-9 61 Freescale 8-10 CPU CORE AND INSTRUCTION SET BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 3 3 3 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 5 BTB 2 3 3 3 3 3 3 3 3 3 3 3 BRCLR7 BRSET7 BRCLR6 BRSET6 BRCLR5 BRSET5 BRCLR4 BRSET4 BRCLR3 BRSET3 BRCLR2 3 BRSET2 BRCLR1 BRSET1 BRCLR0 3 BRSET0 5 BSC 2 BCLR7 BSC 2 5 BSET7 BSC 2 5 BCLR6 BSC 2 5 BSET6 BSC 2 5 BCLR5 BSC 2 5 BSET5 BSC 2 5 BCLR4 BSC 2 5 BSET4 BSC 2 5 BCLR3 BSC 2 5 BSET3 BSC 2 5 BCLR2 BSC 2 5 BSET2 BSC 2 5 BCLR1 BSC 2 5 BSET1 BSC 2 5 BCLR0 BSC 2 5 BSET0 5 REL 2 3 REL 2 3 REL 2 3 REL 3 REL 2 3 REL 2 3 REL 3 REL 3 BIH BIL BMS BMC BMI BPL REL 2 REL 3 REL 2 3 REL 2 3 REL 3 REL 2 3 REL 2 3 BHCS REL 2 3 BHCC BEQ BNE BCS BCC BLS BHI BRN BRA 3 BSC BTB DIR EXT INH IMM Bit set/clear Bit test and branch Direct Extended Inherent Immediate IX IX1 IX2 REL A X Abbreviations for address modes and registers 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 Low High Branch REL 2 0010 CLR TST INC DEC ROL LSL ASR ROR LSR COM NEG DIR 3 0011 1 CLRA TSTA INCA DECA ROLA LSLA ASRA RORA LSRA COMA MUL NEGA INH 1 3 INH 1 INH 1 3 3 INH 1 INH 1 3 INH 1 3 INH 1 3 INH 1 3 3 INH 1 INH 1 3 INH 3 11 INH 1 3 CLRX TSTX INCX DECX ROLX LSLX ASRX RORX LSRX COMX NEGX INH 2 3 INH 2 INH 2 3 3 INH 2 INH 2 3 INH 2 3 INH 2 3 INH 2 3 3 INH 2 INH 2 3 3 INH 2 3 CLR TST INC DEC ROL LSL ASR ROR LSR COM NEG Read/modify/write INH IX1 5 6 0101 0110 Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accumulator Index register DIR 1 5 DIR 1 DIR 1 4 5 DIR 1 DIR 1 5 DIR 1 5 DIR 1 5 DIR 1 5 5 DIR 1 DIR 1 5 5 DIR 1 5 INH 4 0100 IX1 1 6 IX1 1 IX1 1 5 6 IX1 1 IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6 6 IX1 1 IX1 1 6 6 IX1 1 6 CLR TST INC DEC ROL LSL ASR ROR LSR COM NEG IX 7 0111 5 1 WAIT STOP SWI RTS RTI 1 1 1 1 1 1 1 INH 1 INH 2 2 INH 10 INH INH 6 9 Not implemented IX 1 5 IX IX 4 5 IX IX 5 IX 5 IX 5 IX 5 5 IX IX 1 5 1 IX 1 5 TXA NOP RSP SEI CLI SEC CLC TAX Control INH INH 8 9 1000 1001 8 Bit manipulation BTB BSC 0 1 0000 0001 2 2 INH 2 2 INH 2 INH 2 INH 2 2 INH 2 2 INH 2 2 INH 2 2 INH 2 2 2 2 2 2 2 LDX BSR ADD ORA ADC EOR LDA BIT AND CPX SBC CMP SUB IMM A 1010 2 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB 3 Bytes 1 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB SUB F 1111 EXT 3 EXT 3 5 EXT 3 4 EXT 3 6 EXT 3 3 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 5 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 4 IX 3 0 0000 IX2 2 IX2 2 6 IX2 2 5 IX2 2 7 IX2 2 4 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 6 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 5 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB IX1 E 1110 Address mode STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB Register/memory EXT IX2 C D 1100 1101 Cycles DIR 3 DIR 3 4 DIR 3 3 DIR 3 5 DIR 3 2 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 Mnemonic Legend 2 IMM 2 REL 2 2 6 IMM 2 IMM 2 2 IMM 2 2 IMM 2 2 2 2 IMM 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 IMM 2 2 2 DIR B 1011 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB IX IX 4 IX 3 IX 5 IX 2 IX 3 IX 3 IX 3 IX 3 IX 4 IX 3 IX 3 IX 3 IX 3 IX 3 IX 3 3 Low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 High Opcode in binary Opcode in hexadecimal IX1 1 IX1 1 5 IX1 1 4 IX1 1 6 IX1 1 3 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 5 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 4 IX F 1111 05SR3.Book Page 10 Thursday, August 4, 2005 1:08 PM Table 8-8 M68HC05 opcode map MC68HC05SR3 TPG 62 05SR3.Book Page 11 Thursday, August 4, 2005 1:08 PM 8.3 Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term ‘effective address’ (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced by’ and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide. 8.3.1 Inherent In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long. 8.3.2 8 Immediate In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC ← PC+2 8.3.3 Direct In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC ← PC+2 Address bus high ← 0; Address bus low ← (PC+1) TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-11 63 05SR3.Book Page 12 Thursday, August 4, 2005 1:08 PM 8.3.4 Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Freescale assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC ← PC+3 Address bus high ← (PC+1); Address bus low ← (PC+2) 8.3.5 Indexed, no offset In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC ← PC+1 Address bus high ← 0; Address bus low ← X 8 8.3.6 Indexed, 8-bit offset In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC ← PC+2 Address bus high ← K; Address bus low ← X+(PC+1) where K = the carry from the addition of X and (PC+1) 8.3.7 Indexed, 16-bit offset In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC ← PC+3 Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2) where K = the carry from the addition of X and (PC+2) TPG Freescale 8-12 CPU CORE AND INSTRUCTION SET MC68HC05SR3 64 05SR3.Book Page 13 Thursday, August 4, 2005 1:08 PM 8.3.8 Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from –126 to +129 from the opcode address. The programmer need not calculate the offset when using the Freescale assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC ← EA if branch taken; otherwise EA = PC ← PC+2 8.3.9 Bit set/clear In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC ← PC+2 Address bus high ← 0; Address bus low ← (PC+1) 8.3.10 8 Bit test and branch The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from –125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC ← PC+2 Address bus high ← 0; Address bus low ← (PC+1) EA2 = PC+3+(PC+2); PC ← EA2 if branch taken; otherwise PC ← PC+3 TPG MC68HC05SR3 CPU CORE AND INSTRUCTION SET Freescale 8-13 65 05SR3.Book Page 14 Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY 8 TPG Freescale 8-14 CPU CORE AND INSTRUCTION SET MC68HC05SR3 66 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 9 LOW POWER MODES The MC68HC05SR3 has three low-power operating modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The flow of the STOP and WAIT modes is shown in Figure 9-1. The third low-power operating mode is the SLOW mode. 9.1 STOP Mode Execution of the STOP instruction places the MCU in its lowest power consumption mode. In the STOP mode the internal oscillator is turned off, halting all internal processing. When the CPU enters STOP mode the I-bit in the Condition Code Register is cleared automatically, so that any hardware interrupts (IRQ, IRQ2 and KBI) can “wake” the MCU. All other registers and memory contents remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the STOP mode only by a hardware interrupt or an externally generated reset. When exiting the STOP mode the internal oscillator will resume after a pre-defined number of internal processor clock cycles, due to oscillator stabilization. 9.2 9 WAIT Mode The WAIT instruction places the MCU in a low-power mode, but consumes more power than the STOP mode. In the WAIT mode the internal processor clock is halted, suspending all processor and internal bus activities. Other Internal clocks remain active, permitting interrupts to be generated from the Timer. The Timer may be used to generate a periodic exit from the WAIT mode or, in conjunction with the external Timer pin, on the occurrence of external events. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register, so that any hardware interrupt can “wake” the MCU. All other registers, memory, and input/output lines remain in their previous states. TPG MC68HC05SR3 LOW POWER MODES Freescale 9-1 67 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM STOP WAIT Stop External Oscillator, Stop Internal Timer Clock, and Reset Start-Up Delay External Oscillator Active, and Internal Timer Clock Active Stop Internal Processor Clock, Clear I-Bit in CCR Stop Internal Processor Clock, Clear I-Bit in CCR Y External RESET? External RESET? Y N N N External Hardware Interrupt? Y Reset External Oscillator, and Stabilization Delay Y External Hardware Interrupt? N 9 N End of Start-Up Delay? Y N Y Restart Internal Processor Clock Timer Interrupt? Y Keyboard Interrupt? N Fetch Reset Vector or Service Interrupt (a) Stack (b) Set I-Bit (c) Vector to Interrupt Routine Figure 9-1 STOP and WAIT Mode Flowcharts TPG Freescale 9-2 LOW POWER MODES MC68HC05SR3 68 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM 9.3 SLOW Mode The SLOW mode function is controlled by the SM bit in the Miscellaneous Control Register. When the SM bit is set, the internal bus clock is divided by 16, resulting to a frequency equal to the oscillator frequency divide by 32. This feature permits a slow down of all the internal operations and thus reduces power consumption — particularly useful while in WAIT mode. The SM bit is automatically cleared while going to STOP mode. Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 bit 5 bit 4 bit 3 bit 2 KBIC INTO INTE LVRE SM bit 1 bit 0 State on reset IRQ2F IRQ2E 0001 0000 SM — Slow Mode 1 (set) – 0 (clear) – 9.4 Slow mode enabled. Internal bus frequency fOP =fOSC ÷ 32. Slow mode disabled. Internal bus frequency fOP =fOSC ÷ 2. Data-Retention Mode If the Low Voltage Reset function is not enabled, the contents of RAM and CPU registers are retained at supply voltages as low as 2Vdc. This is called the data-retention mode where the data is held, but the device is not guaranteed to operate. The RESET pin must be held low during data-retention mode. The Low Voltage Reset Function is enabled/disabled by the LVRE bit in the Miscellaneous Control Register ($0C). Address bit 7 Miscellaneous Control Register $0C KBIE bit 6 bit 5 bit 4 bit 3 bit 2 KBIC INTO INTE LVRE SM bit 1 bit 0 9 State on reset IRQ2F IRQ2E 0001 0000 LVRE — Low Voltage Reset Enable 1 (set) – Low Voltage Reset function enabled. 0 (clear) – Low Voltage Reset function disabled. TPG MC68HC05SR3 LOW POWER MODES Freescale 9-3 69 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY 9 TPG Freescale 9-4 LOW POWER MODES MC68HC05SR3 70 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 10 OPERATING MODES The MC68HC05SR3/MC68HC705SR3 has two modes of operation: the User Mode and the Self-Check/Bootstrap Mode. Table 10-1 shows the conditions required for entering the two operating modes. Table 10-1 Mode Selection RESET 5V VPP PB1 VSS to VDD VSS to VDD MODE USER VTST VDD SELF-CHECK/BOOTSTRAP VTST =2×VDD 10.1 User Mode The normal operating mode of the MC68HC05SR3/MC68HC705SR3 is the User mode. This mode is entered on the rising edge of RESET when the VPP and PB1 pins are between VSS and VDD. 10.2 10 Self-Check Mode The Self-check mode is provided on the MC68HC05SR3 for the user to check device functions with an on-chip self-check program masked at location $1F00 to $1FEF under minimum hardware support. The self-check schematic is shown in Figure 10-1. Self-check mode is entered on the rising edge of RESET when the VPP pin is at VTST (2×VDD) and PB1 pin is at VDD. Once in the self-check mode, PB1 can then be used for other purposes. After entering the self-check mode, CPU branches to the self-check program and carries out the self-check. Self-check is a repetitive test, i.e. if all parts are checked to be good, the CPU will repeat the self-check again. Therefore, the LEDs attached to Port A will be flashing if the device is good; else the combination of LEDs’ on-off pattern can show what part of the device is suspected to be bad. Table 10-2 lists the LEDs’ on-off patterns and their corresponding indications. TPG MC68HC05SR3 OPERATING MODES Freescale 10-1 71 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM MC68HC05SR3 OUT Crystal OSC 4MHz OSC1 OSC2 PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/VRL PD5/VRH PD6/IRQ2 PD7 +5V 4K7 RESET RESET 1µF +5V + 10K +5V 330 D1 PB0 PB4 330 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 D2 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 IRQ TIMER PB1 PB5 10 330 330 D3 D4 VPP PB2 PB6 VPP +5V PB3 VDD + PB7 VSS 47µF 0.1µF Figure 10-1 MC68HC05SR3 Self-Check Circuit TPG Freescale 10-2 OPERATING MODES MC68HC05SR3 72 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM Table 10-2 Self-Check Report D4 D3 D2 D1 Flashing REMARKS O.K. (self-check is on-going) 1 1 1 1 1 1 1 0 Bad port A Bad port B 1 1 0 1 Bad port C 1 1 0 0 Bad port D 1 0 1 1 Bad RAM 1 0 1 0 Bad ROM 1 0 0 0 Bad SWI 0 1 1 1 Bad IRQ 1=LED on, 0=LED off 10.3 Bootstrap Mode The Bootstrap mode is provided in the EPROM part (MC68HC705SR3) as a mean of self-programming its EPROM with minimal circuitry. Bootstrap mode will be entered on the rising edge of RESET when the VPP pin is at VTST (2 × VDD) and PB1 pin is at VDD. Once in the bootstrap mode, PB1 can then be used for other purposes. After entering the bootstrap mode, CPU branches to the bootstrap program and carries out the EPROM programming routine. The user EPROM consists of 3840 bytes, from location $1000 to $1EFF. Refer to Appendix A for further details on MC68HC705SR3. 10 TPG MC68HC05SR3 OPERATING MODES Freescale 10-3 73 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY 10 TPG Freescale 10-4 OPERATING MODES MC68HC05SR3 74 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 11 ELECTRICAL SPECIFICATIONS This section contains the electrical specifications for MC68HC05SR3. 11.1 Maximum Ratings (Voltages referenced to VSS) SYMBOL VALUE Supply Voltage RATINGS VDD –0.3 to +7.0 V Input Voltage VIN VSS –0.3 to VDD +0.3 V VPP Pin VIN VSS –0.3 to 2xVDD +0.3 V Current Drain per pin excluding VDD and VSS ID 25 mA Operating Temperature Standard Extended TA TL to TH 0 to +70 –40 to +85 °C TSTG –65 to +150 °C Storage Temperature Range UNIT This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤(Vin or Vout)≤VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD). 11.2 11 Thermal Characteristics CHARACTERISTICS Thermal resistance DIP SOIC QFP SYMBOL VALUE UNIT θJA θJA θJA 60 60 60 °C/W °C/W °C/W TPG MC68HC05SR3 ELECTRICAL SPECIFICATIONS Freescale 11-1 75 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM 11.3 DC Electrical Characteristics Table 11-1 DC Electrical Characteristics for 5V Operation (VDD =5.0Vdc ±10%, VSS =0Vdc, temperature range=0 to 70°C) SYMBOL MINIMUM TYPICAL MAXIMUM UNIT Output voltage ILOAD = –10µA ILOAD = +10µA CHARACTERISTICS VOH VOL VDD–0.1 — — — — 0.1 V V Output high voltage (ILOAD=–0.8mA) All Ports VOH VDD–0.8 — — V Output low voltage (ILOAD=+1.6mA) All Ports VOL — 0.1 0.4 V Output high current (VOL=2.5V) All ports (VOL=3.0V) PB5-PB7 in low-current mode IOH IOH 10 2 — — — — mA mA Output low current (VOL=2.5V) All ports (VOL=3.0V) PB5-PB7 in low-current mode IOL IOL 10 2 — — — — mA mA IPORT — 100 — mA Input high voltage PA0-PA7, PB0, PB1, IRQ, RESET, OSC1 VIH 0.7×VDD — VDD V Input low voltage PA0-PA7, PB0, PB1, IRQ, RESET, OSC1 VIL VSS — 0.2×VDD V — — — — — 5.0 1.3 — — — 7.0 2.5 20 30 40 mA mA µA µA µA Total I/O port current Either source or sink 11 Supply current: Run Wait Stop 25°C 0°C to +70°C (Standard) –40°C to +85°C (Extended) IDD I/O ports high-Z leakage current PA0-PA7, PB0-PB7, PC0-PC7, PD0-PD7 IIL — — ±10 µA Input current RESET, IRQ, OSC1 IIN — — ±1 µA Capacitance Ports (as input or output) RESET, IRQ, OSC1, OSC2 COUT CIN — — — — 12 8 pF pF Low voltage reset threshold VLVR 2.8 3.5 4.2 V Pull-up resistor PA0-PA7, PB0-PB7, PC0-PC7, PD0-PD7 RESET, IRQ RPU 14 85 36 100 50 176 KΩ KΩ Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25°C only. (3) Wait IDD: Only timer system active. (4) Wait, Stop IDD: All ports configured as inputs, VIL=0.2Vdc, VIH=VDD–0.2Vdc. (5) Run (operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC =2.0MHz), all inputs 0.2Vdc from rail; no DC loads, less than 50pF on all outputs, CL=20pF on OSC2. (6) Stop IDD measured with OSC1=VSS. (7) Wait IDD is affected linearly by the OSC2 capacitance. TPG Freescale 11-2 ELECTRICAL SPECIFICATIONS MC68HC05SR3 76 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM Table 11-2 DC Electrical Characteristics for 3V Operation (VDD =3.0Vdc ±10%, VSS =0Vdc, temperature range=0 to 70°C) SYMBOL MINIMUM TYPICAL MAXIMUM UNIT Output voltage ILOAD = –10µA ILOAD = +10µA CHARACTERISTICS VOH VOL VDD–0.1 — — — — 0.1 V V Output high voltage (ILOAD=–0.8mA) All Ports VOH VDD–0.3 — — V Output low voltage (ILOAD=+1.6mA) All Ports VOL — 0.1 0.3 V Output high current (VOH=1.0V) All ports IOH 2.7 3.5 4.7 mA Output low current (VOL=2.0V) All ports IOL 3.0 4.0 5.2 Total I/O port current Either source or sink IPORT — 100 — mA Input high voltage PA0-PA7, PB0, PB1, IRQ, RESET, OSC1 VIH 0.7×VDD — VDD V Input low voltage PA0-PA7, PB0, PB1, IRQ, RESET, OSC1 VIL VSS — 0.2×VDD V Supply current: Run Wait Stop 25°C 0°C to +70°C (Standard) –40°C to +85°C (Extended) IDD — — — — — 2.4 0.75 — — — 3.5 1.5 20 30 40 mA mA µA µA µA I/O ports high-Z leakage current PA0-PA7, PB0-PB7, PC0-PC7, PD0-PD7 IIL — — ±10 µA Input current RESET, IRQ, OSC1 IIN — — ±1 µA COUT CIN — — — — 12 8 pF pF RPU 14 85 36 100 50 176 KΩ KΩ Capacitance Ports (as input or output) RESET, IRQ, OSC1, OSC2 Pull-up resistor PA0-PA7, PB0-PB7, PC0-PC7, PD0-PD7 RESET, IRQ mA 11 Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25°C only. (3) Wait IDD: Only timer system active. (4) Wait, Stop IDD: All ports configured as inputs, VIL=0.2Vdc, VIH=VDD–0.2Vdc. (5) Run (operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC =2.0MHz), all inputs 0.2Vdc from rail; no DC loads, less than 50pF on all outputs, CL=20pF on OSC2. (6) Stop IDD measured with OSC1=VSS. (7) Wait IDD is affected linearly by the OSC2 capacitance. TPG MC68HC05SR3 ELECTRICAL SPECIFICATIONS Freescale 11-3 77 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM 11.4 ADC Electrical Characteristics Table 11-3 ADC Electrical Characteristics for 5V and 3V Operation MINIMUM MAXIMUM UNIT Resolution CHARACTERISTICS Number of bits resolved by the ADC PARAMETER 8 8 bits Absolute accuracy Difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors.(1) — — ±1.5 (VDD =5V) ±2 (VDD =3.3V) LSB LSB Conversion range Analog input voltage range VRL VRH V Power-up time ADC power-up time delay, tADON — 500 µs VRH Maximum analog reference voltage VRL VDD+0.1 V VRL Minimum analog reference voltage VSS–0.1 VRH V Conversion time Total time to perform a single analog to digital conversion (a) External clock (OSC1, OSC2) (b) Internal RC oscillator — — 32 32 tCYC tCYC Monotonicity Conversion result never decreases with an increase in input voltage and has no missing codes Inherent (within total error) Zero-input reading Conversion result when VIN=VRL 00 — hex Full-scale reading Conversion result when VIN=VRH — FF hex Analog input acquisition sampling(2) (a) External clock (OSC1, OSC2) (b) Internal RC oscillator — — 12 12 tCYC µs Input capacitance Input capacitance on AN0-AN3 — 8 pF Input leakage Input leakage on ADC pins(3) AN0, AN1, AN2, AN3, VRL, VRH — ±400 nA Sample acquisition time Notes: (1) Error includes quantization. ADC accuracy may decrease proportionately as VDD is reduced below 3.0V. (2) Source impedances greater than 10KΩ adversely affect internal RC charging time during input sampling. (3) The external system error caused by input leakage current is approximately equal to the product of R source and input current. 11 TPG Freescale 11-4 ELECTRICAL SPECIFICATIONS MC68HC05SR3 78 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM 11.5 Control Timing Table 11-4 Control Timing for 5V Operation (VDD =5.0Vdc ±10%, VSS =0Vdc, temperature range=0 to 70°C) CHARACTERISTICS SYMBOL Frequency of operation RC oscillator Option Crystal option External clock option fOSC Internal operating frequency (fOSC/2) RC oscillator Crystal External clock fOP MINIMUM MAXIMUM UNIT 0.1 0.1 dc 4.0 4.0 4.0 MHz MHz MHz — — dc 2.0 2.0 2.0 MHz MHz MHz Processor cycle time (1/fOP) tCYC 500 — ns RC oscillator stabilization time tRCON — 1 ms Crystal oscillator start-up time (crystal oscillator) tOXOV — 100 ms Stop recovery start-up time (crystal oscillator) tILCH — 100 ms 1.5 — Timer resolution(2) tRL tCYC tRESL See note (2) — tCYC Interrupt pulse width low (edge-triggered) tILIH 125 — ns Interrupt pulse period tILIL See note (3) — tCYC RESET pulse width low PA0-PA7 interrupt pulse width high (edge-triggered) tIHIL 125 — ns PA0-PA7 interrupt pulse period tIHIH See note (3) — tCYC t 90 — ns ∆fOSC ∆fOSC – – ±25 ±15 % % OSC1 pulse width RC oscillator frequency combined stability(4) fOSC=2.0MHz, VDD=5.0Vdc±10%, tA=-40°C to +85°C fOSC=2.0MHz, VDD=5.0Vdc±10%, tA=0°C to +40°C Notes: (1) VDD=5.0Vdc±10%, VSS=0Vdc, tA=tL to tH (2) The TIMER input pin is the limiting factor in determining timer resolution. (3) The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC. 11 (4) Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C). TPG MC68HC05SR3 ELECTRICAL SPECIFICATIONS Freescale 11-5 79 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM Table 11-5 Control Timing for 3V Operation (VDD =3.0Vdc ±10%, VSS =0Vdc, temperature range=0 to 70°C) CHARACTERISTICS SYMBOL Frequency of operation RC oscillator Option Crystal option External clock option fOSC Internal operating frequency (fOSC/2) RC oscillator Crystal External clock fOP MINIMUM MAXIMUM UNIT 0.1 0.1 dc 2.0 2.0 2.0 MHz MHz MHz — — dc 1.0 1.0 1.0 MHz MHz MHz Processor cycle time (1/fOP) tCYC 1000 — ns RC oscillator stabilization time tRCON — 2 ms Crystal oscillator start-up time (crystal oscillator) tOXOV — 200 ms Stop recovery start-up time (crystal oscillator) tILCH — 200 ms 1.5 — Timer resolution(2) tRL tCYC tRESL See note (2) — tCYC Interrupt pulse width low (edge-triggered) tILIH 250 — ns Interrupt pulse period tILIL See note (3) — tCYC RESET pulse width low PA0-PA7 interrupt pulse width high (edge-triggered) tIHIL 250 — ns PA0-PA7 interrupt pulse period tIHIH See note (3) — tCYC t 180 — ns ∆fOSC ∆fOSC — — ±35 ±20 % % OSC1 pulse width RC oscillator frequency combined stability(4) fOSC=2.0MHz, VDD=3.0Vdc±10%, tA=–40°C to +85°C fOSC=2.0MHz, VDD=3.0Vdc±10%, tA=0°C to +40°C Notes: (1) VDD=3.0Vdc±10%, VSS=0Vdc, tA=tL to tH (2) The TIMER input pin is the limiting factor in determining timer resolution. (3) The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC. (4) Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C). 11 TPG Freescale 11-6 ELECTRICAL SPECIFICATIONS MC68HC05SR3 80 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM 12 MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 40-pin DIP, 42-pin SDIP and 44-pin QFP packages for the MC68HC05SR3. 12 TPG MC68HC05SR3 MECHANICAL SPECIFICATIONS MOTOROLA 12-1 81 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM 12.1 40-Pin DIP Package (Case 711-03) 40 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 21 B 1 20 A L C N J H G F K D M SEATING PLANE DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 Figure 12-1 40-pin DIP Package 12.2 42-Pin SDIP Package (Case 858-01) -A42 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). 22 -B1 21 L DIM A B C D F G H J K L M N H C -TSEATING PLANE 12 0.25 (0.010) N G F D 42 PL K M T A S M J 42 PL 0.25 (0.010) M T B INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 0.81 1.17 1.778 BSC 7.62 BSC 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 S Figure 12-2 42-pin SDIP Package TPG MOTOROLA 12-2 MECHANICAL SPECIFICATIONS MC68HC05SR3 82 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM 12.3 44-pin QFP Package (Case 824A-01) L 33 23 DETAIL A S S D D S V H A-B B -A,B,DB M L B 0.20 (0.008) -B- 0.20 (0.008) M C A-B 0.05 (0.002) A-B -A- S 22 34 DETAIL A 44 12 1 11 F -DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B BASE METAL S D S S D S J N D M DETAIL C 0.20 (0.008) M C A-B S D S SECTION B–B C E -H- 0.01 (0.004) -CSEATING PLANE H M G M T DATUM PLANE DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINED AT DATUM PLANE ĆHĆ. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE ĆCĆ. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE ĆHĆ. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.45 2.10 0.45 0.30 2.10 2.00 0.40 0.30 0.80 BSC 0.25 Ċ 0.23 0.13 0.95 0.65 8.00 REF 10° 5° 0.17 0.13 7° 0° 0.30 0.13 12.95 13.45 Ċ 0.13 Ċ 0° 12.95 13.45 Ċ 0.40 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC 0.010 Ċ 0.005 0.009 0.026 0.037 0.315 REF 10° 5° 0.005 0.007 7° 0° 0.005 0.012 0.510 0.530 Ċ 0.005 Ċ 0° 0.510 0.530 Ċ 0.016 0.063 REF 12 Figure 12-3 44-pin QFP Package TPG MC68HC05SR3 MECHANICAL SPECIFICATIONS MOTOROLA 12-3 83 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY 12 TPG MOTOROLA 12-4 MECHANICAL SPECIFICATIONS MC68HC05SR3 84 05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM A MC68HC705SR3 This appendix summarizes the differences between the MC68HC05SR3 and MC68HC705SR3. The same information can also be found in appropriate sections of the book. The MC68HC705SR3 is an EPROM version of the MC68HC05SR3. The 3840 bytes of user ROM in the MC68HC05SR3 are replaced by 3840 bytes of user EPROM. A.1 Features • Functionally equivalent to MC68HC05SR3 • 3840 bytes of user EPROM • EPROM bootstrap mode replaces Self-Check mode on the MC68HC05SR3 • Available in the following packages: OTP 40-pin PDIP, windowed EPROM 40-pin Ceramic DIP, OTP 42-pin SDIP, and 44-pin QFP A TPG MC68HC05SR3 MC68HC705SR3 Freescale A-1 85 05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM A.2 Modes of Operation The MC68HC705SR3 has two modes of operation – user mode and EPROM bootstrap mode. Table A-1 shows the conditions required to enter each mode on the rising edge of RESET. Table A-1 MC68HC705SR3 Operating Mode Entry Conditions RESET 5V VPP PB1 VSS to VDD VSS to VDD MODE USER VTST VDD BOOTSTRAP VTST =2×VDD A.3 User Mode The normal operating mode of the MC68HC705SR3 is the user mode. User mode will be entered on the rising edge of RESET when the VPP and PB1 pins are between VSS and VDD. Warning: In the MC68HC705SR3, all vectors are fetched from EPROM in user mode; therefore, the EPROM must be programmed (via the bootstrap mode) before the device is powered up in user mode. A.4 Bootstrap Mode The bootstrap mode is provided as a mean of self-programming MC68HC705SR3 EPROM with minimal circuitry, and can only run in the crystal oscillator mode. Bootstrap mode will be entered on the rising edge of RESET when the VPP pin is at VTST (2×VDD) and PB1 pin is at VDD. Once in the bootstrap mode, PB1 can then be used for other purposes. After entering the bootstrap mode, CPU branches to the bootstrap program and carries out the EPROM programming routine. The user EPROM consists of 3840 bytes, from location $1000 to $1EFF. This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootstrap function does not have to be done from an external EPROM, but it may be done from a host. A The user code must be a one-to-one correspondence with the internal EPROM addresses. TPG Freescale A-2 MC68HC705SR3 MC68HC05SR3 86 05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM A.4.1 EPROM Programming Programming boards are available from Freescale for programming the on-chip EPROM. Please contact your Freescale Representative. The Programming Control register (PCR) is provided for EPROM programming. The function of the EPROM depends on the device operating mode. A.4.2 Program Control Register (PCR) Address bit 7 bit 6 $0D bit 5 bit 4 bit 3 bit 2 RESERVED bit 1 bit 0 State on reset ELAT PGM ---- --00 ELAT - EPROM Latch Control 1 (set) – 0 (clear) – EPROM address and data bus configured for programming (writes to EPROM cause address data to be latched). EPROM is in programming mode and cannot be read if ELATA is 1. This bit should not be set unless a programming voltage is applied to the VPP pin. EPROM address and data bus configured for normal reads. PGM - EPROM Program Command 1 (set) – 0 (clear) – A.4.3 Programming power connected to the EPROM array. If ELAT ≠ 1 then PGM = 0. Programming power disconnected from the EPROM array. EPROM Programming Sequence Programming the EPROM of the MC68HC705SR3 is as follows: 1) Set the ELAT bit. 2) Write the data to be programmed to the address to be programmed. 3) Set the PGM bit. 4) Delay for 1ms. 5) Clear the PGM and the ELAT bits. The last action may be carried out in a single CPU write operation. It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but should be equal to VDD during normal operation. A Example shows address $1900 is programmed with $00. TPG MC68HC05SR3 MC68HC705SR3 Freescale A-3 87 05SR3.Book Page 4 Thursday, August 4, 2005 1:08 PM CLR LDX BSET LDA STA BSET JSR CLR PCR #$00 1,PCR #$00 $1900,X 0,PCR DELAY PCR A.5 ;reset PCR ;load index register with 00 ;set ELAT bit ;load data=00 in to A ;latch data and address ;program ;call delay subroutine for 1ms ;reset PCR Mask Option Register (MOR) The Mask Option Register (MOR) contains programmable EPROM bits to control mask options, and cannot be changed in User mode. The erased state are zeros. This register is latched upon reset going away. Address bit 7 Mask Option Register (MOR) bit 6 $0FFF bit 5 bit 4 bit 3 bit 1 bit 0 State on reset SMD SEC TMR2 TMR1 TMR0 RC unaffected bit 2 SMD — SLOW Mode at Power-on When programmed to “1”, this bit enables SLOW mode at power-up. Operating frequency, fOP =fOSC ÷2÷16=fOSC ÷32. SEC — EPROM Security When programmed to “1”, this bit disables some functions of the Bootstrap mode, preventing external reading of EPROM content. TMR2:TMR0 — Power-on Reset Delay The amount Power-On Reset delay is set by programming these three bits. The delay is selected as follows: A TMR2 TMR1 TMR0 Delay (Instruction Cycles) 0 0 0 256 0 0 1 512 0 1 0 1024 0 1 1 2048 1 0 0 4096 1 0 1 8192 1 1 0 16384 1 1 1 32768 TPG Freescale A-4 MC68HC705SR3 MC68HC05SR3 88 05SR3.Book Page 5 Thursday, August 4, 2005 1:08 PM RC — RC or Crystal Oscillator Option 1 (set) – 0 (clear) – A.6 Resistor option selected. Crystal option selected. Pin Assignments See Section 2.3 for pin assignments for the available packages. A TPG MC68HC05SR3 MC68HC705SR3 Freescale A-5 89 05SR3.Book Page 6 Thursday, August 4, 2005 1:08 PM THIS PAGE LEFT BLANK INTENTIONALLY A TPG Freescale A-6 MC68HC705SR3 MC68HC05SR3 90 05SR3.Book Page 7 Thursday, August 4, 2005 1:08 PM GENERAL DESCRIPTION 1 PIN DESCRIPTIONS 2 INPUT/OUTPUT PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 TIMER 6 ANALOG TO DIGITAL CONVERTER 7 CPU CORE AND INSTRUCTION SET 8 LOW POWER MODES 9 OPERATING MODES 10 ELECTRICAL SPECIFICATIONS 11 MECHANICAL SPECIFICATIONS 12 MC68HC705SR3 A TPG 91 05SR3.Book Page 8 Thursday, August 4, 2005 1:08 PM 1 GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS 12 MECHANICAL SPECIFICATIONS A MC68HC705SR3 TPG 92 How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. 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