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MC68HC11P2
MC68HC711P2
Technical Data
M68HC11
Microcontrollers
MC68HC11P2/D
Rev. 1, 4/2002
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MC68HC11P2
MC68HC711P2
Technical Data — Rev 1.0
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MC68HC11P2 — Rev 1.0
Technical Data
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Technical Data
MC68HC11P2 — Rev 1.0
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Technical Data — MC68HC11P2
List of Paragraphs
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 17
Section 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 21
Section 3. Operating Modes and On-Chip Memory . . . . 41
Section 4. Parallel Input/Output . . . . . . . . . . . . . . . . . . . . 73
Section 5. Serial Communications Interface (SCI) . . . . . 87
Section 6. Motorola Interconnect Bus (MI BUS). . . . . . 109
Section 7. Serial Peripheral Interface (SPI). . . . . . . . . . 125
Section 8. Timing System. . . . . . . . . . . . . . . . . . . . . . . . 137
Section 9. Analog-to-Digital Converter . . . . . . . . . . . . . 173
Section 10. Resets and Interrupts . . . . . . . . . . . . . . . . . 185
Section 11. CPU Core and Instruction Set . . . . . . . . . . 213
Section 12. Electrical Specifications. . . . . . . . . . . . . . . 231
Section 13. Mechanical Data . . . . . . . . . . . . . . . . . . . . . 247
Section 14. Ordering Information . . . . . . . . . . . . . . . . . 251
Section 15. Development Support. . . . . . . . . . . . . . . . . 253
MC68HC11P2 — Rev 1.0
Technical Data
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Technical Data
MC68HC11P2 — Rev 1.0
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Technical Data — MC68HC11P2
Table of Contents
List of Paragraphs
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Table of Contents
List of Figures
List of Tables
Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Section 2. Pin Descriptions
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5
Crystal driver and external clock input (XTAL, EXTAL) . . . . . .24
2.6
E clock output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.7
Phase-locked loop (XFC, VDDSYN). . . . . . . . . . . . . . . . . . . . . 26
2.8
Interrupt request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.9
Nonmaskable interrupt (XIRQ/VPPE). . . . . . . . . . . . . . . . . . . . 32
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2.11
VRH and VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.12
PG7/R/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.13
Port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Section 3. Operating Modes and On-Chip Memory
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4
On-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5
System initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6
EPROM, EEPROM and CONFIG register . . . . . . . . . . . . . . . . 64
Section 4. Parallel Input/Output
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.8
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.9
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4.10
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.11
Internal pull-up/pull-down resistors . . . . . . . . . . . . . . . . . . . . . . 83
4.12
System configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Section 5. Serial Communications Interface (SCI)
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3
Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.4
Transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.5
Receive operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.6
Wakeup feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.7
SCI error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
5.8
SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.9
Status flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.10
Additional SCI subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Section 6. Motorola Interconnect Bus (MI BUS)
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3
Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.4
The push field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.5
The pull field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.6
Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
6.7
Message validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.8
Interfacing to MI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.9
MI BUS clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10
SCI/MI BUS2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.11
SCI/MI BUS3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Section 7. Serial Peripheral Interface (SPI)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3
Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.4
SPI transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.5
SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.6
SPI system errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.7
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Section 8. Timing System
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.3
Timer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8.4
Input capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.5
Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8.6
Real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
8.7
Computer operating properly watchdog function . . . . . . . . . . 157
8.8
Pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
8.9
Pulse-width modulation (PWM) timer . . . . . . . . . . . . . . . . . . . 162
Section 9. Analog-to-Digital Converter
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
9.3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
9.4
A/D converter power-up and clock select . . . . . . . . . . . . . . . . 178
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9.7
Operation in STOP and WAIT modes. . . . . . . . . . . . . . . . . . . 184
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Section 10. Resets and Interrupts
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10.4
Effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
10.5
Reset and interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
10.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
10.7
Low power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Section 11. CPU Core and Instruction Set
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.3
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.4
Data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.5
Opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.6
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
11.7
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Section 12. Electrical Specifications
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.4
Thermal characteristics and power considerations. . . . . . . . . 233
12.5
Test methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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12.7
Control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Section 13. Mechanical Data
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
13.2
Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
13.3
Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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Section 14. Ordering Information
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Section 15. Development Support
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.3
EVS — Evaluation system . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Glossary
Revision History
15.4
Major Changes Between Revision 1.0 and Revision 0.0 . . . . 265
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List of Figures
Figure
Title
Page
MC68HC11P2/MC68HC711P2 block diagram . . . . . . . . . . . . . 19
84-pin PLCC/CERQUAD pinout . . . . . . . . . . . . . . . . . . . . . . . . 22
External reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PLL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RAM stand-by connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MC68HC11P2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
RAM and register overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SCI baud rate generator circuit diagram. . . . . . . . . . . . . . . . . . 88
SCI1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Interrupt source resolution within SCI. . . . . . . . . . . . . . . . . . . 103
MI BUS timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Biphase coding and error detection . . . . . . . . . . . . . . . . . . . . 113
MI BUS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A typical interface between the MC68HC11P2 and the MI BUS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7-1
SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7-2
SPI transfer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
8-1
Timer clock divider chains . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
8-2
Capture/compare block diagram. . . . . . . . . . . . . . . . . . . . . . . 141
8-3
Pulse accumulator block diagram. . . . . . . . . . . . . . . . . . . . . .159
8-4
PWM timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
8-5
PWM duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
9-1
A/D converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 174
9-2
Electrical model of an A/D input pin (in sample mode) . . . . . . 175
9-3
A/D conversion sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10-1 Processing flow out of reset (1 of 2) . . . . . . . . . . . . . . . . . . . . 206
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1-1
2-1
2-2
2-3
2-4
2-5
3-1
3-2
5-1
5-2
5-3
6-1
6-2
6-3
6-4
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10-4
10-5
10-6
11-1
11-2
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
13-1
13-2
13-3
Interrupt priority resolution (2 of 3) . . . . . . . . . . . . . . . . . . . . . 209
Interrupt priority resolution (3 of 3) . . . . . . . . . . . . . . . . . . . . . 210
Interrupt source resolution within the SCI subsystem. . . . . . . 211
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Stacking operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Test methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Timer inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
STOP recovery timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
WAIT recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Port read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Port write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
SPI master timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . 243
SPI master timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . 243
SPI slave timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 244
SPI slave timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 244
Expansion bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
84-pin PLCC/CERQUAD pinout . . . . . . . . . . . . . . . . . . . . . . . 248
84-pin PLCC mechanical dimensions. . . . . . . . . . . . . . . . . . . 249
84-pin CERQUAD mechanical dimensions . . . . . . . . . . . . . . 250
Technical Data
MC68HC11P2 — Rev 1.0
List of Figures
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List of Tables
Table
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2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
5-1
7-1
8-1
8-2
8-3
8-4
9-1
10-1
10-2
10-3
10-4
10-5
11-1
11-2
14-1
15-1
Title
Page
Port signal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Example bootloader baud rates . . . . . . . . . . . . . . . . . . . . . . . . 43
Register and control bit assignments . . . . . . . . . . . . . . . . . . . .47
Registers with limited write access . . . . . . . . . . . . . . . . . . . . . . 51
Hardware mode select summary . . . . . . . . . . . . . . . . . . . . . . . 53
RAM and register remapping . . . . . . . . . . . . . . . . . . . . . . . . . . 56
EEPROM remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
EEPROM block protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Erase mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Example SCI baud rate control values . . . . . . . . . . . . . . . . . . . 95
SPI clock rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Timer resolution and capacity. . . . . . . . . . . . . . . . . . . . . . . . . 139
RTI periodic rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Pulse accumulator timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Clock A and clock B prescalers . . . . . . . . . . . . . . . . . . . . . . . 167
A/D converter channel assignments . . . . . . . . . . . . . . . . . . . . 180
COP timer rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Reset cause, reset vector and operating mode . . . . . . . . . . . 192
Highest priority interrupt selection . . . . . . . . . . . . . . . . . . . . . 198
Interrupt and reset vector assignments . . . . . . . . . . . . . . . . . 199
Stacking order on entry to interrupts. . . . . . . . . . . . . . . . . . . . 201
Reset vector comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
M68HC11 development tools . . . . . . . . . . . . . . . . . . . . . . . . . 253
MC68HC11P2 — Rev 1.0
Technical Data
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List of Tables
Technical Data
MC68HC11P2 — Rev 1.0
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Technical Data — MC68HC11P2
Section 1. General Description
1.1 Contents
1.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 Introduction
The MC68HC11P2 8-bit microcomputer is a member of the M68HC11
family of HCMOS microcomputers. In addition to 32kbytes of ROM, the
MC68HC11P2 contains 1kbyte of RAM and 640 bytes of EEPROM. With
its advanced timer and communication features (including MI BUS(1))
the MC68HC11P2 is especially suitable for mobile communications and
automotive applications.
The MC68HC711P2 is an EPROM version of the MC68HC11P2, with
the User ROM replaced by a similar amount of EPROM. All references
to the MC68HC11P2 apply equally to the MC68HC711P2, unless
otherwise noted. References specific to the MC68HC711P2 are
italicised in the text.
1. The Motorola interconnect bus (MI BUS) is a serial communications protocol which supports
distributed real-time control efficiently and with a high degree of noise immunity. It allows data
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1.3 Features
•
Low power, high performance M68HC11 CPU core, with 4MHz
bus capability
•
Power saving PLL clock circuit, with automatic disable during
WAIT mode
•
32kbytes of User ROM (MC68HC11P2); 32kbytes User EPROM
(MC68HC711P2)
•
1kbyte of RAM
•
640 bytes of byte-erasable User EEPROM, with on-chip charge
pump
•
Up to 50 general purpose I/O lines, plus up to 12 input-only lines
•
Non-multiplexed address and data buses, permitting direct access
to the full 64k address map
•
16-bit timer with 3/4 input captures and 4/5 output compares;
pulse accumulator and COP watchdog timer
•
Three 8- or 9-bit SCI subsystems, two with MI BUS† capability
•
SPI subsystem, with software selectable MSB/LSB first option
•
8-channel, 8-bit analog-to-digital (A/D) converter
•
Four 8-bit PWM timer channels (may be concatenated to form
one, or two, 16-bit channels)
•
Available in 84-pin PLCC or 84-pin CERQUAD packages
Technical Data
MC68HC11P2 — Rev 1.0
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Pulse accumulator
Timer
Periodic interrupt
COP watchdog
SS
SCK
MOSI
MISO
SCI1+
TXD1
RXD1
PD1
PD0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VRH
VRL
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
8-channel
A/D
converter
1024 bytes RAM
VPPE/XIRQ
IRQ
RESET
LIR/MODA
VSTBY/MODB
XTAL
EXTAL
E
XFC
VDDSYN
M68HC11
CPU
SCI3+ (with MI BUS)
PLL
SCI2+ (with MI BUS)
5
VDD
VSS
PWM
5
TXD3
RXD3
TXD2
RXD2
PW4
PW3
PW2
PW1
PD5
PD4
PD3
PD2
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
R/W
Interrupts
&
mode
select
Oscillator
Port E
640 bytes EEPROM
Port D
SPI
Port G
(including 64 bytes for vectors)
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port H
ROM or EPROM
32768 x 8
OC1/PAI
OC1/OC2
OC1/OC3
OC1/OC4
IC4/OC1/OC5
IC1
IC2
IC3
Port A
General Description
Features
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Port B
Port F
Port C
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Non-multiplexed address and data buses
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
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General Description
Technical Data
MC68HC11P2 — Rev 1.0
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Technical Data — MC68HC11P2
Section 2. Pin Descriptions
2.1 Contents
2.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5
Crystal driver and external clock input (XTAL, EXTAL) . . . 24
2.6
E clock output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.7
Phase-locked loop (XFC, VDDSYN) . . . . . . . . . . . . . . . . . . . 26
2.8
Interrupt request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.9
Nonmaskable interrupt (XIRQ/VPPE) . . . . . . . . . . . . . . . . . . 32
2.10
MODA and MODB (MODA/LIR and MODB/VSTBY) . . . . . . . 33
2.11
VRH and VRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.12
PG7/R/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.13
Port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2 Introduction
The MC68HC11P2 is available in an 84-pin plastic-leaded chip carrier
(PLCC); the MC68HC711P2 is also available in an 84-pin windowed
cerquad package, to allow full use of the EPROM. Most pins on this MCU
serve two or more functions, as described in the following paragraphs.
Refer to Figure 2-1 which shows the pin assignments for both 84-pin
packages.
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74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PD2/MISO
PD1/TXD1
PD0/RXD1
MODA/LIR
RESET
XFC
VDDSYN
EXTAL
XTAL
E
VDDR
VSSX
PC7/D7
PC6/D6
PC5/D5
PC4/D4
PC3/D3
PC2/D2
PC1/D1
PC0/D0
IRQ
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
PW1/PH0
PW2/PH1
PW3/PH2
PW4/PH3
RXD2/PH4
TXD2/PH5
RXD3/PH6
TXD3/PH7
MODB/VSTBY
XIRQ
VDD
VDDL
VSSX
VSS
R/W/PG7
PG6
PG5
PG4
PG3
PG2
PG1
84
83
82
81
80
79
78
77
76
75
11
10
9
8
7
6
5
4
3
2
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
PB5/A13
PB6/A14
PB7/A15
VSS
VDD
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC1/OC5/IC4
PA4/OC1/OC4
PA5/OC1/OC3
PA6/OC1/OC2
PA7/OC1/PAI
PD5/SS
PD4/SCK
PD3/MOSI
Pin Descriptions
PG0
VDD AD
AD7/PE7
AD6/PE6
AD5/PE5
AD4/PE4
AD3/PE3
AD2/PE2
AD1/PE1
AD0/PE0
VRL
VRH
VSS AD
A7/PF7
A6/PF6
A5/PF5
A4/PF4
A3/PF3
A2/PF2
A1/PF1
A0/PF0
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Figure 2-1. 84-pin PLCC/CERQUAD pinout
2.3 VDD and VSS
Power is supplied to the microcontroller via these pins. VDD is the
positive supply and VSS is ground. The MCU operates from a single 5V
(nominal) power supply.
It is in the nature of CMOS designs that very fast signal transitions occur
on the MCU pins. These short rise and fall times place very high shortduration current demands on the power supply. To prevent noise
problems, special care must be taken to provide good power supply
bypassing at the MCU. Bypass capacitors should have good high-
Technical Data
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Pin Descriptions
RESET
Bypassing requirements vary, depending on how heavily the MCU pins
are loaded.
The MC68HC11P2 MCU has five VDD pins and five VSS pins. One pair
of these pins is reserved for supplying power to the analog-to-digital
converter (VDD AD, VSS AD); two pairs are used for the internal logic
(VDD, VSS); the remaining two pairs supply power for the port logic on
either half of the chip (VDDL, VSSX and VDDR, VSSX). This
arrangement minimizes the injection of noise into the digital circuitry on
the chip.
2.4 RESET
An active low bidirectional control signal, RESET, acts as an input to
initialize the MCU to a known start-up state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the
clock monitor or the COP watchdog circuit. The CPU distinguishes
between internal and external reset conditions by sensing whether the
reset pin rises to a logic one in less than six E clock cycles after a reset
has occurred. It is therefore not advisable to connect an external
resistor-capacitor (RC) power-up delay circuit to the reset pin of
M68HC11 devices because the circuit charge time constant can cause
the device to misinterpret the type of reset that occurred. Refer to
Resets and Interrupts for further information.
Figure 2-2 illustrates a typical reset circuit that includes an external
switch together with a low voltage inhibit circuit, to prevent power
transitions, or RAM or EEPROM corruption.
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Pin Descriptions
VDD
VDD
2
4.7 k¾
IN
RESET
VDD
Manual
reset
1
To M68HC11
RESET
MC34064
GND
3
4.7 k¾
4.7 k¾
1µF
2
IN
RESET
1
MC34164
GND
3
Figure 2-2. External reset circuitry
2.5 Crystal driver and external clock input (XTAL, EXTAL)
These two pins provide the interface for either a crystal or a CMOS
compatible clock to control the internal clock generator circuitry. The
frequency applied to these pins must be four times higher than the
desired E clock rate (unless the PLL circuit is used to provide the E
clock).
The XTAL pin is normally left unconnected when an external CMOS
compatible clock input is connected to the EXTAL pin. However, a 10 k¾
to 100 k¾ load resistor connected from XTAL to ground can be used to
reduce RFI noise emission. The XTAL output is normally intended to
drive only a crystal. The XTAL output can be buffered with a highimpedance buffer, or it can be used to drive the EXTAL input of another
M68HC11 family device.
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Pin Descriptions
Crystal driver and external clock input (XTAL, EXTAL)
In all cases, use caution when designing circuitry associated with the
oscillator pins. Load capacitances shown in the oscillator circuits include
all stray layout capacitances. See Figure 2-3.
25 pF
EXTAL
(a) Common crystal
connections
4•E
crystal
10 M¾
M68HC11
XTAL
25 pF
EXTAL
(b) External oscillator
connections
External oscillator
M68HC11
XTAL
NC or
10–100k¾ load
25 pF
220¾
EXTAL
EXTAL
10 M¾
M68HC11
XTAL
4•E
crystal
M68HC11
25 pF
NC or
10–100k¾
load
XTAL
(c) One crystal driving two MCUs
Note: capacitor values include all stray capacitance.
Figure 2-3. Oscillator connections
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Pin Descriptions
2.6 E clock output (E)
E is the output connection for the internally generated E clock. The signal
from E is used as a timing reference. The frequency of the E clock output
is one quarter that of the input frequency at the XTAL and EXTAL pins
(except when the PLL is used as the clock source). When E clock output
is low, an internal process is taking place; when it is high, data is being
accessed. All clocks, including the E clock, are halted when the MCU is
in STOP mode. The E clock output can be turned off in single chip
modes to reduce the effects of RFI.
2.7 Phase-locked loop (XFC, VDDSYN)
The XFC and VDDSYN pins are the inputs for the on-chip PLL (phaselocked loop) circuitry. On reset all the device clocks are derived from the
EXTAL input. The EXTAL clock is used as a reference for the PLL circuit,
which generates a clock that is a multiple of the EXTAL frequency. Once
the PLL has stabilized, alternate clocks may be selected.
VDDSYN is the power supply pin for the PLL. Connecting it high enables
the internal low frequency oscillator circuitry designed for the PLL. The
PLL has been designed particularly for use with 614.4 and 640kHz
crystals, though other values may be used. The maximum
recommended crystal frequency for PLL operation is 2MHz. Above this
frequency VDDSYN should be grounded to disable the PLL and enable
the high frequency oscillator circuit; in this state EXTAL is designed for
16MHz operation and XFC may be left unconnected.
The PLL consists of a variable bandwidth loop filter, a voltage controlled
oscillator (VCO), a feedback frequency divider and a digital phase
detector. VDDSYN is the supply voltage for the PLL and must be suitably
bypassed. The external capacitor on XFC should be located as close to
the chip as possible to minimize noise. A typical value for this capacitor
is 0.047µF, for a crystal frequency of 614.4kHz.(1)
1. In general, a larger capacitor will improve the PLL’s frequency stability, at the expense of in) at the desired frequency. For a 32kHz applicreasing the time required for it to settle (t
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Phase-locked loop (XFC, VDDSYN)
The PLL filter has two bandwidths that are automatically selected by the
PLL, if the AUTO bit in PLLCR is set. Whenever the PLL is first enabled,
the wide bandwidth mode is used. This enables the PLL frequency to
ramp up quickly. When the output frequency is near the desired value,
the filter is switched to the narrow bandwidth mode, to make the final
frequency more stable. Manual control is possible, by clearing AUTO in
PLLCR, and setting the appropriate value for BWC.
A block diagram of the PLL circuitry is given in Figure 2-4.
VDDSYN
EXTAL
XFC
tREF
Phase
detect
PCOMP
Loop filter
4XCLK
Bus clock
select
VCO
To clock
generation
circuitry
EXTAL
Low frequency
crystal oscillator
BCS
ST4XCK
tFB
Frequency divider
VCOOUT
Module clock
select
For SCI
and timer
EXTAL
SYNR
MCS
Figure 2-4. PLL circuit
2.7.1 Synchronization of PLL with subsystems
The timer and SCI subsystems operate off the EXTAL clock, but are
accessed by the CPU relative to the internal PH2 signal. Although the
EXTAL clock is used as the reference for the PLL, the PH2 clock and the
module clocks for the timer and the SCI are not synchronized. In order
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2.7.2 Changing the PLL frequency
To change the PLL frequency it is necessary to perform the following
sequence of events, in order to prevent possible bursts of high frequency
operation during the reconfiguration of the PLL:
1. Switch to the low frequency bus rate (BCS = 0)
2. Disable the PLL (PLLON = 0)
3. Change the value in SYNR
4. Enable the PLL (PLLON = 1)
5. Wait a time tPLLS for the PLL frequency to stabilize
6. Switch to the high frequency bus rate (BCS = 1)
2.7.3 PLL registers
Two registers are used to control the operation of the MC68HC11P2
phase-locked loop circuitry. These are the PLL control register and the
synthesizer program register, each of which is described below.
2.7.3.1 PLLCR — PLL control register
Address bit 7
PLL control (PLLCR)
bit 6
bit 5
bit 4
bit 3
State
on reset
bit 2
bit 1
bit 0
$002E PLLON BCS AUTO BWC VCOT MCS
LCK
WEN 1010 1000
This read/write register contains two bits that are used to enable and
disable the synthesizer and to switch from slow (EXTAL) to one of the
fast speeds. Two further bits are used to control the filter bandwidth. The
SCI and timer clock source and the slow clock for WAIT mode are also
controlled by this register.
PLLON — PLL on
1 = Switch PLL on.
0 = Switch PLL off.
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Pin Descriptions
Phase-locked loop (XFC, VDDSYN)
This bit activates the synthesizer circuit without connecting it to the
control circuit. This allows the circuit to stabilize before it drives the
CPU clocks. PLLON is set by reset, to allow the control loop to
stabilize during power up.
PLLON cannot be cleared whilst using VCOOUT to drive the internal
processor clock, i.e. when BCS is set.
BCS — Bus clock select
1 = VCOOUT output drives the clock circuit (4XCLK).
0 = EXTAL drives the clock circuit (4XCLK).
This bit determines which signal drives the clock circuit generating the
bus clocks. Once BCS has been altered it can take up to [1.5 EXTAL
+ 1.5 VCOOUT] cycles for the change in the clock to occur. Reset
clears this bit.
NOTE:
PLLON and BCS have built-in safeguards so that VCOOUT cannot be
selected as the clock source (BCS = 1) if the PLL is off (PLLON = 0).
Similarly, the PLL cannot be turned off (PLLON = 0) if it is on and in use
(BCS = 1). Turning the PLL on and selecting VCOOUT as the clock
source therefore requires two independent writes to PLLCR.
AUTO — Automatic bandwidth control
1 = Automatic bandwidth control selected.
0 = Manual bandwidth control selected.
AUTO selects between automatic bandwidth control circuits in the
phase detect block and manual bandwidth control. Reset sets this bit.
BWC — Bandwidth control
1 = High bandwidth control selected.
0 = Low bandwidth control selected.
Bandwidth control is under manual control only when AUTO is clear.
(When AUTO is set, BWC acts as a read-only status bit to indicate
which mode has been selected by the internal circuit.) A delay of tPLLS
is required between changes to BWC. The low bandwidth driver is
always enabled, so this bit determines whether the high bandwidth
driver is on or off. On PLL start-up in automatic mode (AUTO = 1), the
high bandwidth driver is enabled (BWC = 1) by internal circuitry until
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the PLL is near the specified frequency. The high bandwidth driver is
then disabled and BWC is cleared by internal circuitry. Reset clears
this bit.
Auto
BWC
0
0
1
0
1
X
High
bandwidth
Off
On
Auto
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VCOT — VCO test (Test mode only)
1 = Loop filter operates as specified by AUTO and BWC.
0 = Low bandwidth mode of the PLL filter is disabled.
This bit is used to isolate the loop filter from the VCO for testing
purposes. VCOT is always set when AUTO = 1 when running in
automatic mode. This bit is writable only in test mode. Reset sets this
bit.
MCS — Module clock select
1 = 4XCLK is the source for the SCI and timer divider chain.
0 = EXTAL is the source for the SCI and timer divider chain.
Reset clears this bit.
LCK — Synthesizer lock detect
1 = The PLL has stabilized.
0 = The PLL is not stable.
This bit is used as an indicator for software that it is all right to set
BCS.
WEN — WAIT enable
1 = Low-power WAIT mode selected (PLL set to ‘idle’ in WAIT
mode).
0 = Do not alter the 4XCLK during WAIT mode.
This bit determines whether the 4XCLK is disconnected from
VCOOUT during WAIT and connected to EXTAL. Reset clears this
bit.
When set, the CPU will respond to a WAIT instruction by first stacking
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Phase-locked loop (XFC, VDDSYN)
Any interrupt, any reset, or the assertion of RAF in any of the SCIs will
allow the PLL to resume operating at the frequency specified in the
SYNR. The user must set BCS after the PLL has had time to adjust
(tPLLS). If, for a specific SCI, the RE bit is clear, then RAF cannot
become set, hence the PLL will not resume normal operation.
2.7.3.2 SYNR — Synthesizer program register
Address bit 7
Synthesizer program (SYNR)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$002F SYNX1SYNX0 SYNY5SYNY4SYNY3SYNY2 SYNY1 SYNY0 0000 1011
The PLL frequency synthesizer multiplies the frequency of the crystal
oscillator. The multiplication factor is software programmable via a loop
divider, which consists of a six-bit modulo N counter, with a further two
bit scaling factor.
The multiplication factor is given by 2(Y + 1)2X, where 0 ð X ð 3 and 0 ð
Y ð 63.
NOTE:
Exceeding recommended operating frequencies can result in
indeterminate MCU operation.
SYNX[1:0]
These bits program the binary taps (divide by 1, 2, 4 and 8). Reset
clears these bits.
SYNY[5:0]
These bits program the six-bit modulo N (1 to 64) counter. Reset sets
these bits to %001011.
NOTE:
The resolution of the multiplication factors decreases by a factor of two,
as X increases:
X
0
1
2
3
Y
0 – 63
0 – 63
0 – 63
0 – 63
Possible multipliers
2, 4, 6, 8, …, 128
4, 8, 12, 16, …, 256
8, 16, 24, 32, …, 512
16, 32, 48, 64, …, 1024
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2.8 Interrupt request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge sensitive triggering or level
sensitive triggering is program selectable (OPTION register). IRQ is
always configured to level sensitive triggering at reset.
NOTE:
Connect an external pull-up resistor, typically 4.7 k¾, to VDD when IRQ
is used in a level sensitive wired-OR configuration. See also
Nonmaskable interrupt (XIRQ/VPPE).
2.9 Nonmaskable interrupt (XIRQ/VPPE)
The XIRQ input provides a means of requesting a non-maskable
interrupt after reset initialization. During reset, the X bit in the condition
code register (CCR) is set and any interrupt is masked until MCU
software enables it. Because the XIRQ input is level-sensitive, it can be
connected to a multiple-source wired-OR network with an external pullup resistor to VDD. XIRQ is often used as a power loss detect interrupt.
Whenever XIRQ or IRQ is used with multiple interrupt sources (IRQ
must be configured for level sensitive operation if there is more than one
source of IRQ interrupt), each source must drive the interrupt input with
an open-drain type of driver to avoid contention between outputs. There
should be a single pull-up resistor near the MCU interrupt input pin
(typically 4.7 k¾). There must also be an interlock mechanism at each
interrupt source so that the source holds the interrupt line low until the
MCU recognizes and acknowledges the interrupt request. If one or more
interrupt source is still pending after the MCU services a request, the
interrupt line will still be held low and the MCU will be interrupted again
as soon as the interrupt mask bit in the MCU is cleared (normally upon
return from an interrupt). Refer to Resets and Interrupts.
The VPPE pin is used to input the external EPROM programming
voltage, which must be present during EPROM programming.
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MODA and MODB (MODA/LIR and MODB/VSTBY)
2.10 MODA and MODB (MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes.
Refer to Operating Modes and On-Chip Memory.
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After the operating mode has been selected, the LIR pin provides an
open-drain output to indicate that execution of an instruction has begun.
The LIR pin is normally configured for wired-OR operation (only pulls
low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a short time to
prevent false triggering. A series of E clock cycles occurs during
execution of each instruction. The LIR signal goes low during the first E
clock cycle of each instruction (opcode fetch). This output is provided for
assistance in program debugging and its operation is controlled by the
LIRDV bit in the OPT2 register.
The VSTBY pin is used to input RAM stand-by power. The MCU is
powered from the VDD pin unless the difference between the level of
VSTBY and VDD is greater than one MOS threshold (about 0.7 volts).
When these voltages differ by more than 0.7 volts, the internal 1024-byte
RAM and part of the reset logic are powered from VSTBY rather than
VDD. This allows RAM contents to be retained without VDD power
applied to the MCU. Reset must be driven low before VDD is removed
and must remain low until VDD has been restored to a valid level.
VDD
4.7k¾
VDD
4.8 V NiCd
VOUT
To MODB/VSTBY
pin of M68HC11
MAX 690
(+)
VBATT
Figure 2-5. RAM stand-by connections
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2.11 VRH and VRL
These pins provide the reference voltages for the analog-to-digital
converter.
2.12 PG7/R/W
This pin provides two separate functions, depending on the operating
mode. In single chip and bootstrap modes, PG7/R/W acts as
input/output port G bit 7. Refer to Parallel Input/Output for further
information.
In expanded and test modes, PG7/R/W performs the read/write function.
PG7/R/W signals the direction of transfers on the external data bus. A
high on this pin indicates that a read cycle is in progress.
2.13 Port signals
In the 84-pin PLCC package, 62 pins are arranged into seven 8-bit ports:
A, B, C, E, F, G, and H, and one six-bit port (D). The lines of ports A, B,
C, D, F, G, and H are fully bidirectional; E is input only. Each of the
bidirectional ports serves a purpose other than I/O, depending on the
operating mode or peripheral function selected. Note that ports B, C, F,
and one bit of port G are available for I/O functions only in single chip
and bootstrap modes. Refer to Table 2-1 for details of the port signals’
functions in different operating modes.
NOTE:
When using the information about port functions, do not confuse pin
function with the electrical state of the pin at reset. All general-purpose
I/O pins configured as inputs at reset are in a high-impedance state. Port
data registers reflect the functional state of the port at reset. The pin
function is mode dependent.
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Port signals
Table 2-1. Port signal functions
Port/bit
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PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB[7:0]
PC[7:0]
PD0
PD1
PD2
PD3
PD4
PD5
PE[7:0]
PF[7:0]
PG[6:0]
PG7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
Single chip
and
bootstrap mode
Expanded multiplexed
and
special test mode
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5/IC4 and/or OC1
PA4/OC4 and/or OC1
PA5/OC3 and/or OC1
PA6/OC2 and/or OC1
PA7/PAI and/or OC1
PB[7:0]
A[15:8]
PC[7:0]
D[7:0]
PD0/RXD1
PD1/TXD1
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
Input only or analog inputs
PF[7:0]
A[7:0]
PG[6:0]
PG7/R/W
PH0/PW1
PH1/PW2
PH2/PW3
PH3/PW4
PH4/RXD2
PH5/TXD2
PH6/RXD3
PH7/TXD3
2.13.1 Port A
Port A is an 8-bit general-purpose I/O port with a data register (PORTA)
and a data direction register (DDRA). Port A pins share functions with
the 16-bit timer system (see Timing System for further information).
PORTA can be read at any time: inputs return the pin level; outputs
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outputs. Writes to PORTA do not change the pin state when the pins are
configured for timer output compares.
Out of reset, port A pins [7:0] are general-purpose high-impedance
inputs. When the functions associated with these pins are disabled, the
bits in DDRA govern the I/O state of the associated pin. For further
information, refer to Parallel Input/Output.
2.13.2 Port B
Port B is an 8-bit general-purpose I/O port with a data register (PORTB)
and a data direction register (DDRB). In single chip mode, port B pins are
general-purpose I/O pins (PB[7:0]). In expanded mode, port B pins act
as the high-order address lines (A[15:8]) of the address bus.
PORTB can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTB is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode. For further information, refer to
Parallel Input/Output.
Port B pins include on-chip pull-up devices which can be enabled or
disabled.
2.13.3 Port C
Port C is an 8-bit general-purpose I/O port with a data register (PORTC)
and a data direction register (DDRC). In single chip mode, port C pins
are general-purpose I/O pins (PC[7:0]). In the expanded mode, port C
pins are configured as data bus pins (D[7:0]).
PORTC can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTC is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode. Port C pins are generalpurpose inputs out of reset in single chip and bootstrap modes. In
expanded and test modes, these pins are data bus lines out of reset.
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Port signals
The CWOM control bit in the OPT2 register disables port C’s P-channel
output drivers. Because the N-channel driver is not affected by CWOM,
setting CWOM causes port C to become an open-drain-type output port
suitable for wired-OR operation. In wired-OR mode (PORTC bits at logic
level zero), the pins are actively driven low by the N-channel driver.
When a port C bit is at logic level one, the associated pin is in a high
impedance state as neither the N-channel nor the P-channel devices are
active. It is customary to have an external pull-up resistor on lines that
are driven by open-drain devices. Port C can only be configured for
wired-OR operation when the MCU is in single chip mode. For further
information, refer to Parallel Input/Output.
2.13.4 Port D
Port D, a 6-bit general-purpose I/O port, has a data register (PORTD)
and a data direction register (DDRD). The six port D lines (D[5:0]) can
be used for general-purpose I/O, for one of the serial communications
interfaces (SCI1, bits [0:1]) and for the serial peripheral interface (SPI,
bits [2:5]) subsystem.
PORTD can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTD is written, the data is stored in
internal latches and are driven only if port D is configured for generalpurpose output.
For further information, refer to Parallel Input/Output, Serial
Communications Interface (SCI) and Serial Peripheral Interface
(SPI).
2.13.5 Port E
Port E, PE/AD[7:0], is an input-only port that can also be used as the
analog inputs for the analog-to-digital converter.
For further information, refer to Parallel Input/Output and Analog-toDigital Converter.
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2.13.6 Port F
Port F is an 8-bit general-purpose I/O port with a data register (PORTF)
and a data direction register (DDRF). In single chip mode, port F pins are
general-purpose I/O pins (PF[7:0]). In expanded mode, port F pins act
as the low-order address lines (A[7:0]) of the address bus.
PORTF can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTF is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode.
Port F pins include on-chip pull-up devices that can be enabled or
disabled.
For further information, refer to Parallel Input/Output.
2.13.7 Port G
In normal modes, Port G is an 8-bit general-purpose I/O port with a data
register (PORTG) and a data direction register (DDRG). Port G bit 7 is
the R/W line in expanded mode; the remaining bits are always general
purpose I/O.
PORTG can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTG is written, the data is stored in
internal latches.The pins are driven only if they are configured as outputs
in single chip or bootstrap mode. For further information, refer to Parallel
Input/Output.
Port G pins include on-chip pull-up devices that can be enabled or
disabled.
2.13.8 Port H
Port H is an 8-bit general-purpose I/O port with a data register (PORTH)
and a data direction register (DDRH). Port H pins support either
input/output, SCI2 (bits [7:6]), SCI3 (bits [5:4]), or pulse-width
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Port signals
PORTH can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTH is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode.
Port H pins include on-chip pull-up or pull-down devices that can be
enabled or disabled via the Port pull-up assignment register (PPAR).
Port H [7:4] have pull-up resistors; port H [3:0] have pull-down resistors.
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For further information, refer to Parallel Input/Output, Serial
Communications Interface (SCI), Motorola Interconnect Bus
(MI BUS) and Timing System.
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Technical Data — MC68HC11P2
Section 3. Operating Modes and On-Chip Memory
3.1 Contents
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.4
On-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5
System initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6
EPROM, EEPROM and CONFIG register . . . . . . . . . . . . . . . 64
3.2 Introduction
This section contains information about the modes that define
MC68HC11P2 operating conditions, and about the on-chip memory that
allows the MCU to be configured for various applications.
3.3 Operating modes
The values of the mode select inputs MODB and MODA during reset
determine the operating mode. Single chip and expanded modes are the
normal modes. In single chip mode only on-board memory is available.
Expanded mode, however, allows access to external memory. Each of
these two normal modes is paired with a special mode. Bootstrap, a
variation of the single chip mode, is a special mode that executes a
bootloader program in an internal bootstrap ROM. Test is a special
mode that allows privileged access to internal resources.
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3.3.1 Single chip operating mode
In single chip operating mode, the MC68HC11P2 microcontroller has no
external address or data bus. Ports B, C, F, and the R/W pin are
available for general-purpose parallel I/O.
3.3.2 Expanded operating mode
In expanded operating mode, the MCU can access a 64kbyte physical
address space. The address space includes the same on-chip memory
addresses used for single chip mode, in addition to external memory and
peripheral devices.
The expansion bus is made up of ports B, C, and F, and the R/W signal.
In expanded mode, high order address bits are output on the port B pins,
low order address bits on the port F pins, and the data bus on port C. The
R/W/PG7 pin signals the direction of data transfer on the port C bus.
3.3.3 Special test mode
Special test, a variation of the expanded mode, is primarily used during
Motorola’s internal production testing; however, it is accessible for
programming the CONFIG register, programming calibration data into
EEPROM, and supporting emulation and debugging during
development.
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Operating modes
3.3.4 Special bootstrap mode
When the MCU is reset in special bootstrap mode, a small on-chip ROM
is enabled at address $BE40–$BFFF. The ROM contains a reset vector
and a bootloader program. The MCU fetches the reset vector, then
executes the bootloader.
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For normal use of the bootloader program, send a synchronization byte
$FF to the SCI receiver at either E clock ÷256, or E clock ÷1664 (7812
or 1200 baud respectively, for an E clock of 2MHz). Then download up
to 1024 bytes of program data (which is put into RAM starting at $0080).
These characters are echoed through the transmitter. The bootloader
program ends the download after a timeout of four character times or
1024 bytes. When loading is complete, the program jumps to location
$0080 and begins executing the code. Use of an external pull-up resistor
is required when using the SCI transmitter pin (TXD) because port D pins
are configured for wired-OR operation by the bootloader. In bootstrap
mode, the interrupt vectors point to RAM. This allows the use of
interrupts through a jump table.
Further baud rate options are available on the MC68HC11P2 by using a
different value for the synchronization byte, as shown in Table 3-1. Refer
also to Motorola application note AN1060, M68HC11 Bootstrap Mode
(the bootloader mode is similar to that used on the MC68HC11K4).
Table 3-1. Example bootloader baud rates
Sync.
byte
Timeout
delay
$FF
$FF
$F0
$FD
$FD
4 char.
4
4.9
17.3
13
2.00MHz
7812
1200
9600
5208
3906
Baud rates for an E clock of:
2.10MHz
3.00MHz
3.15MHz
8192
11718
12288
1260
1800
1890
10080
14400
15120
5461
7812
8192
4096
5859
6144
MC68HC11P2 — Rev 1.0
4.00MHz
15624
2400
19200
10416
7812
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Operating Modes and On-Chip Memory
3.4 On-chip memory
The MC68HC11P2 MCU includes 1024 bytes of on-chip RAM, 32kbytes
of ROM/EPROM and 640 bytes of EEPROM. The bootloader ROM
occupies a 512 byte block of the memory map. The CONFIG register is
implemented as a separate EEPROM byte.
Start
address
$0000
$0080
$0480
Register
block
$x000 Each of these blocks
$x07F can be mapped to any
$x080 4k page boundary,
RAM
1024 bytes $x47F using the INIT register.
$0D80
$1000
EEPROM $xD80
640 bytes $xFFF
This block may be remapped
to any 4k page, using INIT2.
BootROM
$BE40
Special Bootstrap mode only.
Vectors
$BFFF
Special modes only.
$8000
$8000
$BE40
32kbytes ROM
(MC68HC11P2) or
32kbytes EPROM
(MC68HC711P2).
NVM
32kbytes
Can be mapped to either
$0000–$7FFF or
$8000–$FFFF,
using the CONFIG register.
$C000
$FFBF
$FFC0
–$FFFF
Vectors
Single
chip
Expanded
Special
Bootstrap
$FFFF
Normal mode vectors.
Special
Test
Figure 3-1. MC68HC11P2 memory map
3.4.1 Mapping allocations
Memory locations for on-chip resources are the same for both expanded
and single chip modes. The 128-byte register block originates at $0000
after reset and can be placed at any other 4k boundary ($x000) after
reset by writing an appropriate value to the INIT register. Refer to Figure
3-1, which shows the memory map.
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On-chip memory
registers are both mapped to the same 4k boundary, RAM starts at
$x080 and 128 bytes are remapped at $x400–$x47F. Otherwise, RAM
starts at $x000.
Remapping is accomplished by writing appropriate values into the two
nibbles of the INIT register.
The 640-byte EEPROM is initially located at $0D80 after reset when
EEPROM is enabled in the memory map by the CONFIG register.
EEPROM can be placed at any other 4k boundary ($xD80) by writing to
the INIT2 register.
If ROM is available, the ROMAD and ROMON bits in the CONFIG
register control the position and presence of ROM in the memory map.
In special test mode, the ROMON bit is cleared so the ROM is removed
from the memory map. In single chip mode, the ROMAD bit is set to one
after reset, which enables the ROM at $8000–$FFFF. In expanded
mode, the ROM may be enabled from $0000–7FFF (ROMAD = 0) to
allow an external memory to contain the interrupt vectors and
initialization code.
In special bootstrap mode, a bootloader ROM is enabled at locations
$BE40–$BFFF. The vectors for special bootstrap mode are contained in
the bootloader program. The boot ROM occupies a 512 byte block of the
memory map, though not all locations are used.
3.4.1.1 RAM
The MC68HC11P2 has 1024 bytes of fully static RAM that are used for
storing instructions, variables and temporary data during program
execution. RAM can be placed at any 4k boundary in the 64kbyte
address space by writing an appropriate value to the INIT register.
By default, RAM is initially located at $0080 in the memory map. Direct
addressing mode can access the first 128 locations of RAM using a onebyte address operand. Direct mode accesses save program memory
space and execution time. Registers can be moved to other boundaries
to allow 256 bytes of RAM to be located in direct addressing space.
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The on-chip RAM is a fully static memory. RAM contents can be
preserved during periods of processor inactivity by either of two
methods, both of which reduce power consumption:
1. During the software-based STOP mode, MCU clocks are stopped,
but the MCU continues to draw power from VDD. Power supply
current is directly related to operating frequency in CMOS
integrated circuits and there is very little leakage when the clocks
are stopped. These two factors reduce power consumption while
the MCU is in STOP mode.
2. To reduce power consumption to a minimum, VDD can be turned
off, and the MODB/VSTBY pin can be used to supply RAM power
from either a battery back-up or a second power supply. Although
this method requires external hardware, it is very effective. Refer
to Pin Descriptions for information about how to connect the
stand-by RAM power supply and to Resets and Interrupts for a
description of low power operation.
3.4.1.2 ROM and EPROM
The MC68HC11P2 MCU has 32kbytes of ROM/EPROM. The
ROM/EPROM array is enabled when the ROMON bit in the CONFIG
register is set to one (erased). The ROMAD bit in CONFIG places the
ROM/EPROM at either $8000–$FFFF out of reset (ROMAD = 1) or at
$0000–$7FFF (ROMAD = 0) in expanded mode.
3.4.1.3 Bootloader ROM
The bootloader ROM is enabled at address $BE40–$BFFF during
special bootstrap mode. The reset vector is fetched from this ROM and
the MCU executes the bootloader firmware. In normal modes, the
bootloader ROM is disabled.
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On-chip memory
3.4.2 Registers
In Table 3-2, a summary of registers and control bits, the registers are
shown in ascending order within the 128-byte register block. The
addresses shown are for default block mapping ($0000–$007F),
however, the INIT register remaps the block to any 4k page
($x000–$x07F).
Table 3-2. Register and control bit assignments (Sheet 1 of 4)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data (PORTA)
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
undefined
Data direction A (DDRA)
$0001
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0 0000 0000
Data direction B (DDRB)
$0002
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0 0000 0000
Data direction F (DDRF)
$0003
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0 0000 0000
Port B data (PORTB)
$0004
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
undefined
Port F data (PORTF)
$0005
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
undefined
Port C data (PORTC)
$0006
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
undefined
Data direction C (DDRC)
$0007
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
Port D data (PORTD)
$0008
0
0
PD5
PD4
PD3
PD2
PD1
Data direction D (DDRD)
$0009
0
0
DDD5
DDD4
DDD3
DDD2
DDD1
Port E data (PORTE)
$000A
PE7
PE6
PE5
PE4
PE3
PE2
PE1
$000B
FOC1
FOC2
FOC3
FOC4
FOC5
Timer compare force (CFORC)
DDC0 0000 0000
PD0
undefined
DDD0 0000 0000
PE0
undefined
0
0
0
0000 0000
Output compare 1 mask (OC1M)
$000C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
0
0
0
0000 0000
Output compare 1 data (OC1D)
$000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
0
0
0
0000 0000
(10)
(9)
(bit 8) 0000 0000
Timer count (TCNT) high
$000E
(bit 15)
(14)
(13)
(12)
(11)
Timer count (TCNT) low
$000F
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Timer input capture 1 (TIC1) high
$0010
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
undefined
Timer input capture 1 (TIC1) low
$0011
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Timer input capture 2 (TIC2) high
$0012
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
undefined
Timer input capture 2 (TIC2) low
$0013
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Timer input capture 3 (TIC3) high
$0014
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
undefined
Timer input capture 3 (TIC3) low
$0015
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Timer output compare 1 (TOC1) high $0016
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
1111 1111
$0017
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Timer output compare 2 (TOC2) high $0018
Timer output compare 1 (TOC1) low
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
1111 1111
Timer output compare 2 (TOC2) low
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
$0019
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Table 3-2. Register and control bit assignments (Sheet 2 of 4)
Register name
Address
Timer output compare 4 (TOC4) high $001C
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
1111 1111
Timer output compare 4 (TOC4) low
$001D
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Capture 4/compare 5 (TI4/O5) high
$001E
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
1111 1111
Capture 4/compare 5 (TI4/O5) low
$001F
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Timer control 1 (TCTL1)
$0020
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0000 0000
Timer control 2 (TCTL2)
$0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000
Timer interrupt mask 1 (TMSK1)
$0022
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0000 0000
Timer interrupt flag 1 (TFLG1)
$0023
OC1F
OC2F
OC3F
OC4F I4/O5F
IC1F
IC2F
IC3F
0000 0000
Timer interrupt mask 2 (TMSK2)
$0024
TOI
RTII
PAOVI
PAII
0
0
PR1
PR0
0000 0000
RTIF PAOVF
PAIF
0
0
0
0
0000 0000
0
I4/O5
RTR1
(3)
(2)
(1)
Timer interrupt flag 2 (TFLG2)
$0025
TOF
Pulse accumulator control (PACTL)
$0026
0
Pulse accumulator count (PACNT)
$0027
(bit 7)
(6)
SPI control (SPCR)
$0028
SPIE
SPE
PAEN PAMOD PEDGE
(5)
(4)
DWOM MSTR CPOL CPHA
SPR1
RTR0 0000 0000
(bit 0)
undefined
SPR0 0000 01uu
SPI status (SPSR)
$0029
SPIF
WCOL
0
MODF
0
0
0
0
0000 0000
SPI data (SPDR)
$002A
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
EPROM programming (EPROG) ‡
$002B
MBE
0
0
0
Port pull-up assignment (PPAR)
$002C
0
0
0
0
reserved
$002D
BCS
AUTO
BWC
PLL control (PLLCR)
$002E PLLON
ELAT EXCOL EXROW
EPGM 0000 0000
HPPUE GPPUE FPPUE BPPUE 0000 1111
VCOT
MCS
LCK
WEN
1010 1000
Synthesizer program (SYNR)
$002F
A/D control & status (ADCTL)
$0030
SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0 0000 1011
CCF
0
SCAN
MULT
CD
CC
CB
CA
u0uu uuuu
A/D result 1 (ADR1)
$0031
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
A/D result 2 (ADR2)
$0032
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
A/D result 3 (ADR3)
$0033
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
A/D result 4 (ADR4)
$0034
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Block protect (BPROT)
$0035
BULKP
0
reserved
$0036
EE3
EE2
BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
EEPROM mapping (INIT2)
$0037
System config. options 2 (OPT2)
$0038
LIRDV CWOM STRCH IRVNE LSBF
SPR2
0
0
000x 0000
System config. options 1 (OPTION)
$0039
ADPU
CSEL
IRQE
DLY
CME
FCME
CR1
CR0
0001 0000
COP timer arm/reset (COPRST)
$003A
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
EEPROM programming (PPROG)
$003B
ODD
EVEN
Highest priority interrupt (HPRIO)
$003C RBOOT SMOD
RAM & I/O mapping (INIT)
$003D
EE1
0
MDA
EE0
BYTE
M3DL1 M3DL0 M2DL1 M2DL0 0000 0000
ROW ERASE EELAT EEPGM 0000 0000
PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
RAM3 RAM2 RAM1 RAM0 REG3
REG2
Technical Data
REG1
REG0 0000 0000
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Table 3-2. Register and control bit assignments (Sheet 3 of 4)
Register name
Address
reserved
$0040
reserved
$0041
reserved
$0042
reserved
$0043
reserved
$0044
reserved
$0045
reserved
$0046
reserved
$0047
reserved
$0048
bit 7
bit 6
reserved
$0049
reserved
$004A
reserved
$004B
reserved
$004C
reserved
$004D
reserved
$004E
reserved
$004F
SCI/MI 2/3 baud high (S2BDH)
$0050
SCI/MI 2/3 baud low (S2BDL)
$0051
SCI/MI 2 control 1 (S2CR1)
$0052
SCI/MI 2 control 2 (S2CR2)
$0053
TIE2
TCIE2
SCI/MI 2 status 1 (S2SR1)
$0054
TDRE2
TC2
B2TST B2SPL
S2B7
S2B6
bit 5
bit 0
S2B12 S2B11 S2B10
S2B9
S2B8 0000 0000
S2B4
S2B3
S2B2
S2B1
S2B0 0000 0100
M2
WAKE2
ILT2
PE2
ILIE2
TE2
RE2
RDRF2 IDLE2
OR2
NF2
FE2
S2B5
LOPS2 WOMS2 MIE2
RIE2
bit 3
bit 2
SCI/MI 2 status 2 (S2SR2)
$0055
0
0
0
0
0
0
0
$0056
R8B
T8B
0
0
0
0
0
SCI/MI 2 data low (S2DRL)
$0057
reserved
$0058
0000 0000
PF2
1100 0000
RAF2 0000 0000
0
undefined
R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undefined
$0059
SCI/MI 3 control 1 (S3CR1)
$005A LOPS3 WOMS3 MIE3
SCI/MI 3 control 2 (S3CR2)
$005B
SCI/MI 3 status 1 (S3SR1)
$005C TDRE3
TIE3
TCIE3
TC3
M3
WAKE3
ILT3
ILIE3
TE3
RE3
RDRF3 IDLE3
OR3
NF3
FE3
RIE3
PE3
SCI/MI 3 status 2 (S3SR2)
$005D
0
0
0
0
0
0
0
$005E
R8C
T8C
0
0
0
0
0
SCI/MI 3 data low (S3DRL)
$005F
$0061
Pulse width scale (PWSCAL)
$0062
0000 0000
PF3
1100 0000
RAF3 0000 0000
0
undefined
R7T7C R6T6C R5T5C R4T4C R3T3C R2T2C R1T1C R0T0C undefined
$0060 CON34 CON12 PCKA2 PCKA1
Pulse width polarity select (PWPOL)
PT3
RWU3 SBK3 0000 0000
SCI/MI 3 data high (S3DRH)
Pulse width clock select (PWCLK)
PT2
RWU2 SBK2 0000 0000
SCI/MI 2 data high (S2DRH)
reserved
State
on reset
bit 1
0
bit 4
0
PCKB3 PCKB2 PCKB1 0000 0000
PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
(bit 7)
(6)
(5)
(4)
(3)
MC68HC11P2 — Rev 1.0
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(1)
(bit 0) 0000 0000
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Table 3-2. Register and control bit assignments (Sheet 4 of 4)
bit 0
State
on reset
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Pulse width count 2 (PWCNT2)
$0065
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 3 (PWCNT3)
$0066
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 4 (PWCNT4)
$0067
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width period 1 (PWPER1)
$0068
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width period 2 (PWPER2)
$0069
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width period 3 (PWPER3)
$006A
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width period 4 (PWPER4)
$006B
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width duty 1 (PWDTY1)
$006C
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width duty 2 (PWDTY2)
$006D
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width duty 3 (PWDTY3)
$006E
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
Pulse width duty 4 (PWDTY4)
$006F
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
1111 1111
SCI 1 baud rate high (SCBDH)
$0070
BTST
BSPL
0
SCI 1 baud rate low (SCBDL)
$0071
SBR7
SBR6
SBR5
SBR12 SBR11 SBR10 SBR9
SBR8 0000 0000
SBR4
SBR3
SBR0 0000 0100
SBR2
SBR1
SCI 1 control 1 (SCCR1)
$0072 LOOPS WOMS
0
M
WAKE
ILT
PE
PT
0000 0000
SCI 1 control 2 (SCCR2)
$0073
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0000 0000
SCI 1 status 1 (SCSR1)
$0074
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1100 0000
SCI 1 status 2 (SCSR2)
$0075
0
0
0
0
0
0
0
RAF
0000 0000
SCI 1 data high (SCDRH)
$0076
R8
T8
0
0
0
0
0
0
undefined
SCI 1 data low (SCDRL)
$0077
R7T7
R6T6
R5T5
R4T4
R3T3
R2T2
R1T1
R0T0
undefined
reserved
$0078
reserved
$0079
reserved
$007A
reserved
$007B
Port H data (PORTH)
$007C
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
undefined
Data direction H (DDRH)
$007D
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
Port G data (PORTG)
$007E
PG7
PG6
PG5
PG4
PG3
PG2
PG1
Data direction G (DDRG)
$007F
DDH0 0000 0000
PG0
undefined
DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000
KEY
‡
Applies only to EPROM devices
x State on reset depends on mode selected
u State of bit on reset is undefined
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System initialization
3.5 System initialization
Registers and bits that control initialization and the basic operation of the
MCU are protected against writes except under special circumstances.
The following table lists registers that can be written only once after
reset, or that must be written within the first 64 cycles after reset.
Table 3-3. Registers with limited write access
Register
address
Register
name
Must be written in
first 64 cycles
Write
once only
$x024
Timer interrupt mask register 2 (TMSK2)
(1)
—
$x035
Block protect register (BPROT)
(2)
—
$x037
EEPROM mapping register (INIT2)
No
Yes
$x038
System configuration options register 2 (OPT2)
No
(3)
$x039
System configuration options register (OPTION)
(4)
—
$x03D
RAM and I/O map register (INIT)
Yes
—
1. Bits 1 and 0 can be written once and only in first 64 cycles; when SMOD = 1, however, these bits can be written at any
time. All other bits can be written at any time.
2. Bits can be written to zero once and only in first 64 cycles or in special modes. Bits can be set to one at any time.
3. Bit 4 (IRVNE) can be written only once.
4. Bits 5, 4, 2, 1, and 0 can be written once and only in first 64 cycles; when SMOD = 1, however, bits 5, 4, 2, 1, and 0 can
be written at any time. All other bits can be written at any time.
3.5.1 Mode selection
The four mode variations are selected by the logic states of the mode A
(MODA) and mode B (MODB) pins during reset. The MODA and MODB
logic levels determine the logic state of special mode (SMOD) and the
mode A (MDA) control bits in the highest priority I-bit interrupt and
miscellaneous (HPRIO) register.
After reset is released, the mode select pins no longer influence the
MCU operating mode. In single chip operating mode, MODA pin is
connected to a logic zero. In expanded mode, MODA is normally
connected to VDD through a pull-up resistor of 4.7 k¾. The MODA pin
also functions as the load instruction register (LIR) pin when the MCU is
not in reset. The open-drain active low LIR output pin drives low during
the first E cycle of each instruction. The MODB pin also functions as the
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stand-by power input (VSTBY), which allows the RAM contents to be
maintained in the absence of VDD.
Refer to Table 3-4, which is a summary of mode pin operation, the mode
control bits and the four operating modes.
A normal mode is selected when MODB is logic one during reset. One
of three reset vectors is fetched from address $FFFA–$FFFF, and
program execution begins from the address indicated by this vector. If
MODB is logic zero during reset, the special mode reset vector is fetched
from addresses $BFFA–$BFFF and software has access to special test
features. Refer to Resets and Interrupts.
3.5.1.1 HPRIO — Highest priority I-bit interrupt & misc. register
Address bit 7
Highest priority interrupt (HPRIO) $003C
NOTE:
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
RBOO
SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
T
RBOOT, SMOD and MDA bits depend on the power-up initialization
mode and can only be written in special modes when SMOD = 1. Refer
to Table 3-4.
RBOOT — Read bootstrap ROM
1 = Bootloader ROM enabled, at $BE40–$BFFF.
0 = Bootloader ROM disabled and not in map.
SMOD — Special mode select
1 = Special mode variation in effect.
0 = Normal mode variation in effect.
Once cleared, cannot be set again.
MDA — Mode select A
1 = Normal expanded or special test mode. (Expanded buses
active.)
0 = Normal single chip or special bootstrap mode. (Ports active.)
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System initialization
Table 3-4. Hardware mode select summary
Inputs
MODB
1
1
0
0
Control bits in HPRIO
(latched at reset)
RBOOT SMOD
MDA
Single chip
0
0
0
Expanded
0
0
1
Special bootstrap
1
1
0
Special test
0
1
1
Mode
MODA
0
1
0
1
PSEL[4:0] — Priority select bits (refer to Resets and Interrupts)
3.5.2 Initialization
Because bits in the following registers control the basic configuration of
the MCU, an accidental change of their values could cause serious
system problems. The protection mechanism, overridden in special
operating modes, requires a write to the protected bits only within the
first 64 bus cycles after any reset, or only once after each reset. See
Table 3-3.
3.5.2.1 CONFIG — System configuration register
Address bit 7
Configuration control (CONFIG) $003F
ROMA
D
bit 6
bit 5
1
1
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PARE NOSE NOCO ROMO
EEON x11x 1xxx
N
C
P
N
CONFIG controls the presence and/or location of ROM and EEPROM in
the memory map and enables the COP watchdog system. A security
feature that protects data in EEPROM and RAM is available on mask
programmed MCUs, controlled by the NOSEC bit. Refer to RAM and
EEPROM security.
CONFIG is made up of EEPROM cells and static working latches. The
operation of the MCU is controlled directly by these latches and not the
EEPROM byte. When programming the CONFIG register, the EEPROM
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These bits can be read at any time. The value read is the one latched
into the register from the EEPROM cells during the last reset sequence.
A new value programmed into this register is not readable until after a
subsequent reset sequence. Unused bits always read as ones.
If SMOD = 1, CONFIG bits can be written at any time. If SMOD = 0,
CONFIG bits can only be written using the EEPROM programming
sequence, and are neither readable nor active until latched via the next
reset.
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ROMAD — ROM mapping control
1 = ROM addressed from $8000 to $FFFF.
0 = ROM addressed from $0000 to $7FFF (expanded mode only).
In single chip mode, reset sets this bit.
Bits [6,5] — Not implemented; always read one
PAREN — Pull-up assignment register enable (see Parallel
Input/Output)
1 = PPAR register enabled; pull-ups can be enabled using PPAR.
0 = PPAR register disabled; all pull-ups disabled.
NOSEC — EEPROM security disabled (see RAM and EEPROM
security)
1 = Disable security.
0 = Enable security.
NOCOP — COP system disable (see Resets and Interrupts)
1 = COP system disabled.
0 = COP system enabled (forces reset on timeout).
ROMON — ROM enable
1 = ROM included in the memory map.
0 = ROM excluded from the memory map.
In single chip mode, reset sets this bit. In special test mode, reset
clears ROMON.
EEON — EEPROM enable
1 = EEPROM included in the memory map.
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3.5.2.2 INIT — RAM and I/O mapping register
Address bit 7
RAM & I/O mapping (INIT)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000
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The internal registers used to control the operation of the MCU can be
relocated on 4k boundaries within the memory space with the use of
INIT. This 8-bit special-purpose register can change the default locations
of the RAM and control registers within the MCU memory map. It can be
written to only once within the first 64 E clock cycles after a reset. It then
becomes a read-only register.
RAM[3:0] — RAM map position
These four bits, which specify the upper hexadecimal digit of the RAM
address, control the position of the RAM in the memory map. The RAM
can be positioned at the beginning of any 4k page in the memory map.
Refer to Table 3-5.
REG[3:0] — 128-byte register block position
These four bits specify the upper hexadecimal digit of the address for the
128-byte block of internal registers. The register block is positioned at
the beginning of any 4k page in the memory map. Refer to Table 3-5.
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Table 3-5. RAM and register remapping
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RAM[3:0]
Location
0000
$0000–$03FF
0001
$1000–$13FF
0010
$2000–$23FF
0011
$3000–$33FF
0100
$4000–$43FF
0101
$5000–$53FF
0110
$6000–$63FF
0111
$7000–$73FF
1000
$8000–$83FF
1001
$9000–$93FF
1010
$A000–$A3FF
1011
$B000–$B3FF
1100
$C000–$C3FF
1101
$D000–$D3FF
1110
$E000–$E3FF
1111
$F000–$F3FF
NOTE:
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
$0000–$007F
$1000–$107F
$2000–$207F
$3000–$307F
$4000–$407F
$5000–$507F
$6000–$607F
$7000–$707F
$8000–$807F
$9000–$907F
$A000–$A07F
$B000–$B07F
$C000–$C07F
$D000–$D07F
$E000–$E07F
$F000–$F07F
When the memory map has the 128-byte register block mapped at the
same location as RAM, the registers have priority and the RAM is
relocated to the memory space immediately following the register block.
This mapping feature keeps all the RAM available for use. Refer to
Figure 3-2, which illustrates the overlap.
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System initialization
$x000
$x07F
$x080
$x000
$x07F
$x080
RAM A
Register block
RAM B
RAM B
$x3FF
$x3FF
$x400
$x47F
Register and RAM mapped
to different 4k boundaries.
RAM A
Register and RAM mapped
to the same 4k boundary.
Figure 3-2. RAM and register overlap
3.5.2.3 INIT2 — EEPROM mapping and MI BUS delay register
Address bit 7
EEPROM mapping (INIT2)
$0037
EE3
bit 3
bit 2
bit 1
bit 0
State
on reset
bit 6
bit 5
bit 4
EE2
EE1
EE0 M3DL1 M3DL0 M2DL1 M2DL0 0000 0000
This register determines the location of EEPROM in the memory map.
INIT2 may be read at any time but bits 7–4 may be written only once after
reset in normal modes (bits 3–0 may be written at any time).
EE[3:0] — EEPROM map position
EEPROM is located at $xD80–$xFFF, where x is the hexadecimal
digit represented by EE[3:0]. Refer to Table 3-6.
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Table 3-6. EEPROM remapping
EE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
$0D80–$0FFF
$1D80–$1FFF
$2D80–$2FFF
$3D80–$3FFF
$4D80–$4FFF
$5D80–$5FFF
$6D80–$6FFF
$7D80–$7FFF
$8D80–$8FFF
$9D80–$9FFF
$AD80–$AFFF
$BD80–$BFFF
$CD80–$CFFF
$DD80–$DFFF
$ED80–$EFFF
$FD80–$FFFF
M3DL1, M3DL0, M2DL1, M2DL0 — MI BUS delay select (refer to
Motorola Interconnect Bus (MI BUS))
3.5.2.4 OPTION — System configuration options register 1
Address bit 7
System config. options 1
(OPTION)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
$0039 ADPU CSEL IRQE
DLY
CME FCME CR1
bit 0
State
on reset
CR0 0001 0000
The 8-bit special-purpose OPTION register sets internal system
configuration options during initialization. The time protected control bits,
IRQE, DLY, FCME and CR[1:0] can be written only once in the first 64
cycles after a reset and then they become read-only bits. This minimizes
the possibility of any accidental changes to the system configuration.
They may be written at any time in special modes.
ADPU — A/D power-up (refer to Analog-to-Digital Converter)
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System initialization
After enabling the A/D power, at least 100µs should be allowed for
system stabilization.
CSEL — Clock select (refer to Analog-to-Digital Converter)
1 = A/D and EEPROM use internal RC clock source (about
1.5MHz).
0 = A/D and EEPROM use system E clock (must be at least 1MHz).
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Selects alternate clock source for on-chip EEPROM and A/D charge
pumps. The on-chip RC clock should be used when the E clock
frequency falls below 1MHz.
IRQE — Configure IRQ for falling edge sensitive operation
1 = Falling edge sensitive operation.
0 = Low level sensitive operation.
DLY — Enable oscillator start-up delay
1 = A delay of approximately 4064 E clock cycles is imposed as the
MCU is started up from the STOP mode.
0 = The oscillator start-up delay coming out of STOP is bypassed
and the MCU resumes processing within about four bus
cycles. A stable external oscillator is required if this option is
selected.
CME — Clock monitor enable (refer to Resets and Interrupts)
1 = Clock monitor enabled.
0 = Clock monitor disabled.
In order to use both STOP and clock monitor, the CME bit should be
set before executing STOP, then set again after recovering from
STOP.
FCME — Force clock monitor enable (refer to Resets and Interrupts)
1 = Clock monitor enabled; cannot be disabled until next reset.
0 = Clock monitor follows the state of the CME bit.
When FCME is set, slow or stopped clocks will cause a clock failure
reset sequence. To utilize STOP mode, FCME should always be
cleared.
CR[1:0] — COP timer rate select bits (refer to Resets and Interrupts)
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3.5.2.5 OPT2 — System configuration options register 2
Address bit 7
bit 6
System config. options 2 (OPT2) $0038 LIRDV CWOM
bit 5
bit 4
bit 3
bit 2
STRC
IRVNE LSBF SPR2
H
bit 1
bit 0
State
on reset
0
0
000x 0000
LIRDV — LIR driven
1 = Enable LIR drive high pulse.
0 = LIR only driven low (requires pull-up on pin).
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In single chip and bootstrap modes, this bit has no meaning or effect.
The LIR pin is normally configured for wired-OR operation (only pulls
low). In order to detect consecutive instructions in a high-speed
application, this signal can be made to drive high for a quarter of a
cycle to prevent false triggering.
CWOM — Port C wired-OR mode
1 = Port C outputs are open-drain.
0 = Port C operates normally.
STRCH — Stretch external accesses
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
When this bit is set, off-chip accesses of addresses $0000–$7FFF
($8000–$FFFF, if ROMAD is clear) are extended by one E clock cycle
to allow access to slow peripherals. The E clock stretches externally,
but the internal clocks are not affected, so that timers and serial
systems are not corrupted. In single chip and boot modes this bit has
no effect.
IRVNE — Internal read visibility/not E
IRVNE can be written once in any user mode. In expanded modes,
IRVNE determines whether IRV is on or off. In special test mode,
IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
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System initialization
In single chip modes this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
Refer to the following table for a summary of the operation
immediately following reset.
Mode
Single chip
Expanded
Boot
Special test
IRVNE
after reset
0
0
0
1
E clock
after reset
On
On
On
On
IRV
IRVNE
IRVNE
after reset affects only can be written
Off
E
Once
Off
IRV
Once
Off
E
Once
On
IRV
Unlimited
LSBF — LSB-first enable (refer to Serial Peripheral Interface (SPI))
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
SPR2 — SPI clock rate select (refer to Serial Peripheral Interface
(SPI))
This bit adds a divide-by-four to the SPI clock chain.
Bits 1, 0 — not implemented; always read zero.
3.5.2.6 BPROT — Block protect register
Address bit 7
Block protect (BPROT)
$0035 BULKP
bit 6
bit 5
0
BPRT4
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PTCO
BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
N
BPROT prevents accidental writes to EEPROM and the CONFIG
register. The bits in this register can be written to zero only once during
the first 64 E clock cycles after reset in the normal modes; they can be
set at any time. Once the bits are cleared, the EEPROM array and the
CONFIG register can be programmed or erased. Setting the bits in the
BPROT register to logic one protects the EEPROM and CONFIG
Table 3-7
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BULKP — Bulk erase of EEPROM protect
1 = EEPROM cannot be bulk or row erased.
0 = EEPROM can be bulk erased normally.
Bit 6 — not implemented; always reads zero.
BPRT4 — Block protect bit for top 128 bytes of EEPROM (see below)
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PTCON — Protect for CONFIG register
1 = CONFIG register cannot be programmed or erased.
0 = CONFIG register can be programmed or erased normally.
Note that, in special modes, CONFIG may be written regardless of the
state of PTCON.
BPRT[4:0] — Block protect bits for EEPROM
1 = Protection is enabled for associated block; it cannot be
programmed or erased.
0 = Protection disabled for associated block.
Each of these five bits protects a block of EEPROM against writing or
erasure, as follows:
Table 3-7. EEPROM block protect
Bit name
BPRT0
BPRT1
BPRT2
BPRT3
BPRT4
Block protected
$xD80–$xD9F
$xDA0–$xDDF
$xDE0–$xE5F
$xE60–$xF7F
$xF80–$xFFF
Technical Data
Block size
32 bytes
64 bytes
128 bytes
288 bytes
128 bytes
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System initialization
3.5.2.7 TMSK2 — Timer interrupt mask register 2
Address bit 7
Timer interrupt mask 2 (TMSK2) $0024
TOI
bit 6
bit 5
bit 4
RTII PAOVI PAII
State
on reset
bit 3
bit 2
bit 1
bit 0
0
0
PR1
PR0 0000 0000
PR[1:0] are time-protected control bits and can be changed only once
and then only within the first 64 bus cycles after reset in normal modes.
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NOTE:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOI — Timer overflow interrupt enable
1 = Interrupt requested when TOF is set.
0 = TOF interrupts disabled.
RTII — Real-time interrupt enable
1 = Interrupt requested when RTIF set.
0 = RTIF interrupts disabled.
PAOVI — Pulse accumulator overflow interrupt enable (Refer to Timing
System)
1 = Interrupt requested when PAOVF set.
0 = PAOVF interrupts disabled.
PAII — Pulse accumulator interrupt enable (Refer to Timing System)
1 = Interrupt requested when PAIF set.
0 = PAIF interrupts disabled.
PR[1:0] — Timer prescaler select
These two bits select the prescale rate for the main 16-bit free-running
timer system. These bits can be written only once during the first 64
E clock cycles after reset in normal modes, or at any time in special
modes. Refer to the following table:
PR[1:0]
00
01
10
Prescale
factor
1
4
8
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3.6 EPROM, EEPROM and CONFIG register
3.6.1 EPROM
Using the on-chip EPROM programming feature requires an external
power supply (VPPE). Normal programming is accomplished using the
EPROG register. Program EPROM at room temperature only and place
an opaque label over the quartz window after programming.
The erased state of each EPROM byte is $FF.
3.6.1.1 EPROG — EPROM programming control register
Address bit 7
EPROM programming (EPROG) $002B
MBE
bit 6
bit 5
0
ELAT
bit 4
bit 3
EXCO EXRO
L
W
bit 2
bit 1
0
0
bit 0
State
on reset
EPGM 0000 0000
MBE — Multiple byte program enable
1 = Program four bytes with the same data.
0 = Normal programming.
When programming four bytes simultaneously, address bits 7 and 4
are ignored, hence a write to, for example, $99 will actually program
$09, $19, $89 and $99 (i.e. %x00x 1001). This bit may be read or
written only in special modes; it will always read zero in normal
modes.
Bits 6, 2, 1 — Not implemented; always read zero.
ELAT — EPROM latch control
1 = EPROM address and data buses configured for programming.
EPROM cannot be read.
0 = EPROM address and data buses configured for normal
operation.
When set, this bit causes the address and data for writes to the
EPROM to be latched. ELAT may be read and written at any time.
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EPROM, EEPROM and CONFIG register
EXCOL — Select extra columns
1 = User array disabled; extra column selected.
0 = User array selected.
The extra column may be accessed at bit 7; addresses use bits 11–5,
bits 4–0 must be ones. The EXCOL bit always reads zero in normal
modes and may be read or written only in special modes.
EXROW — Select extra rows
1 = User array disabled; extra rows selected.
0 = User array selected.
There are four extra rows (two in each block). Addresses use bits 6–0,
bits 11–7 must be zeros. (The high nibble determines which 16k block
is accessed.) The EXROW bit always reads zero in normal modes
and may be read or written only in special modes.
EPGM — EPROM program command
1 = Programming voltage (VPPE) switched to the EPROM array.
0 = Programming voltage (VPPE) disconnected from the EPROM
array.
This bit can be read at any time, but may only be written if ELAT is set.
NOTE:
If ELAT = 0 (normal operation) then EPGM = 0 (programming voltage
disconnected).
3.6.1.2 EPROM programming
The EPROM may be programmed and verified in software, via the MCU,
using the following procedure. The ROMON bit in the CONFIG register
should be set. On entry, A contains the data to be programmed and X
contains the EPROM address.
EPROG
LDAB
STAB
STAA
LDAB
STAB
JSR
CLR
#$20
$102B
$0, X
#$21
$102B
DLYEP
$102B
Set ELAT bit (PGM=0) to enable EPROM latches.
Store data to EPROM address
Set EPGM bit, with ELAT=1, to enable prog. voltage
Delay 2–4 ms
Turn off programming voltage and set to READ mode
With this method, the EPROM is programmed by software while in the
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utility can be used. To use the resident utility, bootload a three-byte
program consisting of a single jump instruction to $BF00. $BF00 is the
starting address of a resident EPROM programming utility. The utility
program sets the X and Y index registers to default values, then receives
programming data from an external host and puts it in EPROM. The
value in IX determines programming delay time. The value in IY is a
pointer to the first address in EPROM to be programmed (default =
$D000). When the utility program is ready to receive programming data,
it sends the host an $FF character; then it waits. When the host sees the
$FF character, the EPROM programming data is sent, starting with
location $D000. After the last byte to be programmed is sent and the
corresponding verification data is returned, the programming operation
is terminated by resetting the MCU.
3.6.2 EEPROM
The 640-byte on-board EEPROM is initially located from $0D80 to
$0FFF after reset in all modes. It can be mapped to any other 4k
boundary by writing to the INIT2 register. The EEPROM is enabled by
the EEON bit in the CONFIG register. Programming and erasing is
controlled by the PPROG register.
Unlike information stored in ROM, data in the 640 bytes of EEPROM can
be erased and reprogrammed under software control. Because
programming and erasing operations use an on-chip charge pump
driven by VDD, a separate external power supply is not required.
An internal charge pump supplies the programming voltage. Use of the
block protect register (BPROT) prevents inadvertent writes to (or erases
of) blocks of EEPROM (see BPROT — Block protect register). The
CSEL bit in the OPTION register selects an on-chip oscillator clock for
programming and erasing while operating at frequencies below 2MHz.
Refer to Resets and Interrupts.
In special modes there two extra rows and columns of EEPROM, which
are used for factory testing. Endurance and data retention specifications
do not apply to these cells.
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EPROM, EEPROM and CONFIG register
3.6.2.1 PPROG — EEPROM programming control register
Address bit 7
EEPROM programming
(PPROG)
NOTE:
$003B
bit 6
bit 5
ODD EVEN
0
bit 4
bit 3
BYTE ROW
bit 2
bit 1
bit 0
State
on reset
ERAS
EEPG
EELAT
0000 0000
E
M
Writes to EEPROM addresses are inhibited while EEPGM is one. A write
to a different EEPROM location is prevented while a program or erase
operation is in progress.
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ODD — Program odd rows in half of EEPROM (Test)
EVEN — Program even rows in half of EEPROM (Test)
If both ODD and EVEN are set to one then all odd and even rows in
half of the EEPROM will be programmed with the same data, within
one programming cycle.
Bit 5 — Not implemented; always reads zero.
BYTE — EEPROM byte erase mode
1 = Erase only one byte of EEPROM.
0 = Row or bulk erase mode used.
ROW — EEPROM row/bulk erase mode (only valid when BYTE = 0)
1 = Erase only one 16 byte row of EEPROM.
0 = Erase all 640 bytes of EEPROM.
Table 3-8. Erase mode selection
Byte
0
0
1
1
Row
0
1
0
1
Action
Bulk erase (all 640 bytes)
Row erase (16 bytes)
Byte erase
Byte erase
ERASE — Erase/normal control for EEPROM
1 = Erase mode.
0 = Normal read or program mode.
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EELAT — EEPROM latch control
1 = EEPROM address and data bus set up for programming or
erasing.
0 = EEPROM address and data bus set up for normal reads.
When the EELAT bit is cleared, the EEPROM can be read as if it were
a ROM. The block protect register has no effect during reads.
EEPGM — EEPROM program command
1 = Program or erase voltage switched on to EEPROM array.
0 = Program or erase voltage switched off to EEPROM array.
During EEPROM programming, the ROW and BYTE bits of PPROG
are not used. If the frequency of the E clock is 1MHz or less, set the
CSEL bit in the OPTION register. Remember that zeros must be
erased by a separate erase operation before programming. The
following example of how to program an EEPROM byte assumes that
the appropriate bits in BPROT have been cleared.
PROG
LDAB
STAB
STAA
LDAB
STAB
JSR
CLR
#$02
$103B
$0D80
#$03
$103B
DLY10
$103B
EELAT=1
Set EELAT bit
Store data to EEPROM address
EELAT=EEPGM=1
Turn on programming voltage
Delay 10 ms
Turn off high voltage and set to READ mode
3.6.2.2 EEPROM bulk erase
To erase the EEPROM, ensure that the proper bits of the BPROT
register are cleared, then complete the following steps using the PPROG
register:
1. Write to PPROG with the ERASE, EELAT and appropriate BYTE
and ROW bits set.
2. Write to the appropriate EEPROM address with any data. Row
erase only requires a write to any location in the row. Bulk erase
is accomplished by writing to any location in the array.
3. Write to PPROG with ERASE, EELAT, EEPGM and the
appropriate BYTE and ROW bits set.
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EPROM, EEPROM and CONFIG register
6. Clear the PPROG register to reconfigure the EEPROM address
and data buses for normal operation.
The following is an example of how to bulk erase the 512-byte EEPROM.
The CONFIG register is not affected in this example.
BULKE
LDAB
STAB
STAA
LDAB
STAB
JSR
CLR
#$02
$103B
$0D80
#$03
$103B
DLY10
$103B
EELAT=1
Set EELAT bit
Store data to any EEPROM address
EELAT=EEPGM=1
Turn on programming voltage
Delay 10 ms
Turn off high voltage and set to READ mode
3.6.2.3 EEPROM row erase
The following example shows how to perform a fast erase of large
sections of EEPROM:
ROWE
LDAB
STAB
STAB
LDAB
STAB
JSR
CLR
#$0E
$103B
0,X
#$0F
$103B
DLY10
$103B
ROW=ERASE=EELAT=1
Set to ROW erase mode
Write any data to any address in ROW
ROW=ERASE=EELAT=EEPGM=1
Turn on high voltage
Delay 10 ms
Turn off high voltage and set to READ mode
3.6.2.4 EEPROM byte erase
The following is an example of how to erase a single byte of EEPROM:
BYTEE
LDAB
STAB
STAB
LDAB
STAB
JSR
CLR
#$16
$103B
0,X
#$17
$103B
DLY10
$103B
BYTE=ERASE=EELAT=1
Set to BYTE erase mode
Write any data to address to be erased
BYTE=ERASE=EELAT=EEPGM=1
Turn on high voltage
Delay 10 ms
Turn off high voltage and set to READ mode
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3.6.3 CONFIG register programming
Because the CONFIG register is implemented with EEPROM cells, use
EEPROM procedures to erase and program this register. The procedure
for programming is the same as for programming a byte in the EEPROM
array, except that the CONFIG register address is used. CONFIG can be
programmed or erased (including byte erase) while the MCU is
operating in any mode, provided that PTCON in BPROT is clear. To
change the value in the CONFIG register, complete the following
procedure. Do not initiate a reset until the procedure is complete.
1. Erase the CONFIG register.
2. Program the new value to the CONFIG address.
3. Initiate reset.
CONFIG — System configuration register
Address bit 7
Configuration control (CONFIG) $003F
ROMA
D
bit 6
bit 5
1
1
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PARE NOSE NOCO ROMO
EEON x11x 1xxx
N
C
P
N
For a description of the bits contained in the CONFIG register refer to
CONFIG — System configuration register.
CONFIG is made up of EEPROM cells and static working latches. The
operation of the MCU is controlled directly by these latches and not the
EEPROM byte. When programming the CONFIG register, the EEPROM
byte is accessed. When the CONFIG register is read, the static latches
are accessed.
These bits can be read at any time. The value read is the one latched
into the register from the EEPROM cells during the last reset sequence.
A new value programmed into this register is not readable until after a
subsequent reset sequence. Unused bits always read as ones.
If SMOD = 1, CONFIG bits can be written at any time. If SMOD = 0,
CONFIG bits can only be written using the EEPROM programming
sequence, and are neither readable nor active until latched via the next
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EPROM, EEPROM and CONFIG register
3.6.4 RAM and EEPROM security
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The optional security feature protects the contents of EEPROM and
RAM from unauthorized access. A program, or a key portion of a
program, can be protected against duplication. To accomplish this, the
protection mechanism restricts operation of protected devices to single
chip modes, and thus prevents the memory locations from being
monitored externally (single chip modes do not allow visibility of the
internal address and data buses). Resident programs, however, have
unlimited access to the internal EEPROM and RAM and can read, write,
or transfer the contents of these memories. The NOSEC bit in the
CONFIG register disables this feature on devices that incorporate it.
Contact a Motorola representative for information on the availability of
this feature.
If the security feature is present and enabled and bootstrap mode is
selected, then the following sequence is performed by the bootstrap
program:
1. Output $FF on the SCI.
2. Turn block protect off. Clear BPROT register.
3. IF EEPROM is enabled, erase it all.
4. Verify that the EEPROM is erased; if not, begin sequence again.
5. Write $FF to every RAM byte.
6. Erase the CONFIG register.
If all the above operations are successful, the bootloading process
continues as if the device has not been secured.
CONFIG — System configuration register
Address bit 7
Configuration control (CONFIG)
$003F
ROMA
D
bit 6
bit 5
bit 4
1
1
PAREN
bit 3
bit 2
bit 1
bit 0
State
on reset
NOSE NOCO ROMO
EEON x11x 1xxx
C
P
N
For a description of the other bits contained in the CONFIG register refer
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NOSEC — EEPROM security disabled
1 = Disable security.
0 = Enable security.
MC68HC11P2 devices are normally manufactured with NOSEC set to
one and the security option is unavailable. On special request, a mask
option is selected during fabrication that enables the security mode. On
these parts, the secure mode is invoked by programming the NOSEC bit
to zero.
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Technical Data — MC68HC11P2
Section 4. Parallel Input/Output
4.1 Contents
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
4.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
4.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
4.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.8
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
4.9
Port G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
4.10
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
4.11
Internal pull-up/pull-down resistors . . . . . . . . . . . . . . . . . . . 83
4.12
System configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.2 Introduction
The MC68HC11P2 has up to 54 input/output lines and 8 input-only lines,
depending on the operating mode. To enhance the I/O functions, the
data bus of this microcontroller is nonmultiplexed. The following table is
a summary of the configuration and features of each port.
MC68HC11P2 — Rev 1.0
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Table 4-1. Port configuration
Port
A
B
C
D
E
F
G
H
NOTE:
Input
pins
—
—
—
—
8
—
—
—
Output
pins
—
—
—
—
—
—
—
—
Bidirectional
pins
8
8
8
6
—
8
8
8
Alternate functions
Timer
High order address
Data bus
SPI and SCI1
A/D converter
Low order address
R/W on PG7
PWM and SCI2/3 (with MI BUS)
Do not confuse pin function with the electrical state of that pin at reset.
All general-purpose I/O pins that are configured as inputs at reset are in
a high-impedance state and the contents of the port data registers are
undefined; in port descriptions, a ‘u’ indicates this condition. The pin
function is mode dependent.
4.3 Port A
Port A is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port A pins are shared with
timer functions, as shown in the following table.
Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Alternate function
IC3
IC2
IC1
OC5 and/or OC1, or IC4
OC4 and/or OC1
OC3 and/or OC1
OC2 and/or OC1
PAI and/or OC1
See Timing System
for more information.
On reset the pins are configured as general purpose high-impedance
inputs.
Technical Data
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Port B
4.3.1 PORTA — Port A data register
Address bit 7
Port A data (PORTA)
$0000
PA7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PA6
PA5
PA4
PA3
PA2
PA1
PA0 undefined
This is a read/write register and is not affected by reset. The bits may be
read and written at any time, but, when a pin is allocated to its alternate
function, a write to the corresponding register bit has no affect on the pin
state.
4.3.2 DDRA — Data direction register for port A
Address bit 7
Data direction A (DDRA)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000
DDA[7:0] — Data direction for port A
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.4 Port B
Port B is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port B pins are used as the
nonmultiplexed high order address pins, as shown in the following
table.
Pin
PB0
PB1
PB2
PB3
PB4
PB5
PB6
Alternate
function
A8
A9
A10
A11
A12
A13
A14
In expanded or test
mode, the pins
become the high
order address and
port B is not
included in the
memory map.
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The state of the pins on reset is mode dependent. In single chip or
bootstrap mode, port B pins are high-impedance inputs with selectable
internal pull-up resistors (see Internal pull-up/pull-down resistors). In
expanded or test mode, port B pins are high order address outputs and
PORTB/DDRB are not in the memory map.
4.4.1 PORTB — Port B data register
Address bit 7
Port B data (PORTB)
$0004
PB7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PB6
PB5
PB4
PB3
PB2
PB1
PB0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.4.2 DDRB — Data direction register for port B
Address bit 7
Data direction B (DDRB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0002 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0000 0000
DDB[7:0] — Data direction for port B
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
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Port C
4.5 Port C
Port C is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port C pins are used as the
nonmultiplexed data bus pins, as shown in the following table.
Alternate
function
D0
D1
D2
D3
D4
D5
D6
D7
Pin
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
In expanded or test
mode, the pins
become the data bus
and port C is not
included in the
memory map.
The state of the pins on reset is mode dependent. In single chip or
bootstrap mode, port C pins are high-impedance inputs. In expanded or
test modes, port C pins are the data bus I/O and PORTC/DDRC are not
in the memory map.
4.5.1 PORTC — Port C data register
Address bit 7
Port C data (PORTC)
$0006
PC7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PC6
PC5
PC4
PC3
PC2
PC1
PC0 undefined
The bits may be read and written at any time and are not affected by
reset.
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4.5.2 DDRC — Data direction register for port C
Address bit 7
Data direction C (DDRC)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000
DDC[7:0] — Data direction for port C
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.6 Port D
Port D is a 6-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port D pins are shared with
SCI and SPI functions, as shown in the following table.
PD0
PD1
Alternate
function
RXD1
TXD1
PD2
PD3
PD4
PD5
MISO
MOSI
SCK
SS
Pin
See Serial
Communications Interface
(SCI) for more information.
See Serial Peripheral
Interface (SPI) for more
information.
On reset the pins are configured as general purpose high-impedance
inputs.
4.6.1 PORTD — Port D data register
Address bit 7
Port D data (PORTD)
$0008
0
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
PD5
PD4
PD3
PD2
PD1
PD0 undefined
This is a read/write register and is not affected by reset. The bits may be
read and written at any time, but, when a pin is allocated to its alternate
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Port E
4.6.2 DDRD — Data direction register for port D
Address bit 7
Data direction D (DDRD)
$0009
0
bit 6
0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 0000 0000
Bits [7:6] — Reserved; always read zero
DDD[5:0] — Data direction for port D
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.7 Port E
Port E is an 8-bit input-only port. In addition to their input capability, port
E pins are shared with A/D functions, as shown in the following table.
Pin
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Alternate
function
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
See Analog-to-Digital
Converter for more
information.
On reset the pins are configured as general purpose high-impedance
inputs.
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4.7.1 PORTE — Port E data register
Address bit 7
Port E data (PORTE)
$000A
PE7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PE6
PE5
PE4
PE3
PE2
PE1
PE0 undefined
This is a read-only register and is not affected by reset. The bits may be
read at any time.
NOTE:
As port E shares pins with the A/D converter, a read of the this register
may affect any conversion currently in progress, if it coincides with the
sample portion of the conversion cycle. Hence, normally port E should
not be read during the sample portion of any conversion.
4.8 Port F
Port F is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port F pins are used as the
non-multiplexed low order address pins, as shown in the following
table.
Pin
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
Alternate
function
A0
A1
A2
A3
A4
A5
A6
A7
In expanded or test
mode, the pins become
the low order address
and port F is not included
in the memory map.
The state of the pins on reset is mode dependent. In single chip or
bootstrap mode, port F pins are high-impedance inputs with selectable
internal pull-up resistors (see Internal pull-up/pull-down resistors). In
expanded or test modes, port F pins are low order address outputs and
PORTF/DDRF are not in the memory map.
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Port G
4.8.1 PORTF — Port F data register
Address bit 7
Port F data (PORTF)
$0005
PF7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PF6
PF5
PF4
PF3
PF2
PF1
PF0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.8.2 DDRF — Data direction register for port F
Address bit 7
Data direction F (DDRF)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0003 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 0000 0000
DDF[7:0] — Data direction for port F
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.9 Port G
Port G is an 8-bit bidirectional port, with both data and data direction
registers. In addition to its I/O capability, port G pin 7 (PG7) is used as
the R/W pin in expanded and test modes.
The state of PG7 on reset is mode dependent. In single chip or bootstrap
mode, PG7 is a high-impedance input. In expanded or test modes, PG7
is the R/W output. The remaining pins (PG[6:0]) are high-impedance
inputs, with software selectable internal pull-up resistors (see Internal
pull-up/pull-down resistors).
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4.9.1 PORTG — Port G data register
Address bit 7
Port G data (PORTG)
$007E
PG7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PG6
PG5
PG4
PG3
PG2
PG1
PG0 undefined
The bits may be read and written at any time and are not affected by
reset.
4.9.2 DDRG — Data direction register for port G
Address bit 7
Data direction G (DDRG)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$007F DDG7 DDG6 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000
DDG[7:0] — Data direction for port G
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.10 Port H
Port H is an 8-bit bidirectional port, with both data and data direction
registers. In addition to their I/O capability, port H pins are shared with
SCI/MI BUS and PWM functions, as shown in the following table.
Pin
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
Alternate
function
PW1
PW2
PW3
PW4
RXD2
TXD2
RXD3
TXD3
See Timing System
for more information.
See Serial Communications
Interface (SCI) and Motorola
Interconnect Bus (MI BUS)
for more information.
On reset the pins are configured as general purpose high-impedance
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Internal pull-up/pull-down resistors
ups on pins 7–4 and pull-downs on pins 3–0 (see Internal pull-up/pulldown resistors).
4.10.1 PORTH — Port H data register
Address bit 7
Port H data (PORTH)
$007C
PH7
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PH6
PH5
PH4
PH3
PH2
PH1
PH0 undefined
This is a read/write register and is not affected by reset. The bits may be
read and written at any time, but, when a pin is allocated to its alternate
function, a write to the corresponding register bit has no affect on the pin
state.
4.10.2 DDRH — Data direction register for port H
Address bit 7
Data direction H (DDRH)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$007D DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 0000 0000
DDH[7:0] — Data direction for port H
1 = The corresponding pin is configured as an output.
0 = The corresponding pin is configured as an input.
4.11 Internal pull-up/pull-down resistors
Three of the ports (B, F and G) have internal, software selectable pull-up
resistors. Port H has both pull-up and pull-down resistors, as described
below.
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4.11.1 PPAR — Port pull-up assignment register
Address bit 7
Port pull-up assignment (PPAR) $002C
0
bit 6
bit 5
bit 4
0
0
0
bit 3
bit 2
bit 1
bit 0
State
on reset
HPPUEGPPUEFPPUEBPPUE 0000 1111
Bits [7:4] — Not implemented; always read zero
xPPUE — Port x pin pull-up enable
These bits control the on-chip pull-up devices connected to all the
pins on I/O ports B, F, G and H. They are collectively enabled or
disabled via the PAREN bit in the CONFIG register (see below).
1 = Port x pin on-chip pull-up devices enabled.
0 = Port x pin on-chip pull-up devices disabled.
NOTE:
Port H [7:4] have pull-up resistors; port H [3:0] have pull-down resistors.
All eight internal resistors are enabled if HPPUE is set.
NOTE:
FPPUE and BPPUE have no effect in expanded mode since ports F and
B are dedicated address bus outputs.
4.12 System configuration
One bit in each of the following registers is directly concerned with the
configuration of the I/O ports. For full details on the other bits in the
registers, refer to the appropriate section.
4.12.1 OPT2 — System configuration options register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
System config. options 2 (OPT2) $0038 LIRDV CWOMSTRCH IRVNE LSBF SPR2
bit 1
bit 0
State
on reset
0
0
000x 0000
LIRDV — LIR driven (refer to Operating Modes and On-Chip Memory)
1 = Enable LIR drive high pulse.
0 = LIR only driven low – requires pull-up on pin.
Technical Data
MC68HC11P2 — Rev 1.0
Parallel Input/Output
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Parallel Input/Output
System configuration
CWOM — Port C wired-OR mode
1 = Port C outputs are open-drain.
0 = Port C operates normally.
STRCH — Stretch external accesses (refer to Operating Modes and
On-Chip Memory)
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
IRVNE — Internal read visibility/not E (refer to Operating Modes and
On-Chip Memory)
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
LSBF — LSB first enable (refer to Serial Peripheral Interface (SPI))
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
SPR2 — SPI clock rate select (refer to Serial Peripheral Interface
(SPI))
Bits 1, 0 — not implemented; always read zero.
4.12.2 CONFIG — System configuration register
Address bit 7
Configuration control (CONFIG) $003F ROMAD
bit 6
bit 5
1
1
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PARENNOSECNOCOPROMON EEON x11x 1xxx
ROMAD — ROM mapping control (refer to Operating Modes and OnChip Memory)
1 = ROM addressed from $8000 to $FFFF.
0 = ROM addressed from $0000 to $7FFF (expanded mode only).
MC68HC11P2 — Rev 1.0
Technical Data
Parallel Input/Output
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Parallel Input/Output
PAREN — Pull-up assignment register enable
1 = PPAR register enabled; pull-ups can be enabled using PPAR.
0 = PPAR register disabled; all pull-ups disabled.
NOSEC — EEPROM security disabled (refer to Operating Modes and
On-Chip Memory)
1 = Disable security.
0 = Enable security.
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NOCOP — COP system disable (refer to Resets and Interrupts)
1 = COP system disabled.
0 = COP system enabled (forces reset on timeout).
ROMON — ROM enable (refer to Operating Modes and On-Chip
Memory)
1 = ROM present in the memory map.
0 = ROM disabled from the memory map.
EEON — EEPROM enable (refer to Operating Modes and On-Chip
Memory)
1 = EEPROM is present in the memory map.
0 = EEPROM is disabled from the memory map.
Technical Data
MC68HC11P2 — Rev 1.0
Parallel Input/Output
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Technical Data — MC68HC11P2
Section 5. Serial Communications Interface (SCI)
5.1 Contents
5.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3
Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.4
Transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.5
Receive operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.6
Wakeup feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.7
SCI error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.8
SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.9
Status flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.10
Additional SCI subsystems . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2 Introduction
The serial communications interface (SCI) is a universal asynchronous
receiver transmitter (UART). It has a non-return to zero (NRZ) format
(one start, eight or nine data, and one stop bit) that is compatible with
standard RS-232 systems.
The MC68HC11P2 contains three serial communications interfaces, all
having similar operation. For ease of reference, a full description of SCI1
(PD0/RXD1, PD1/TXD1) is given first, followed by summaries for SCI2
and SCI3, detailing their differences.
MC68HC11P2 — Rev 1.0
Technical Data
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
The SCI shares I/O with two of port D’s pins:
Pin
PD0
PD1
Alternate
function
RXD1
TXD1
The SCI transmit and receive functions are enabled by TE and RE
respectively, in SCCR2.
The SCI features enabled on this MCU include: 13-bit modulus
prescaler; idle line detect; receiver-active flag; transmitter and receiver
hardware parity. A block diagram of the enhanced baud rate generator
is shown in Figure 5-1. See Table 5-1 for example baud rate control
values.
ST4XCK
Transmitter
baud rate
clock
Internal
phase 2 clock
13-bit counter
÷ 16
Reset
13-bit compare
EQ
÷2
Sync
Receiver
baud rate
clock
SCBDH/L: SCI baud control
Figure 5-1. SCI baud rate generator circuit diagram
5.3 Data format
The serial data format requires the following conditions:
•
An idle-line condition before transmission or reception of a
message.
•
A start bit, logic zero, transmitted or received, that indicates the
start of each character.
•
Data that is transmitted and received least significant bit (LSB)
first.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Transmit operation
•
A stop bit, logic one, used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits, and a
stop bit.)
•
A break (defined as the transmission or reception of a logic zero
for some multiple number of frames).
Selection of the word length is controlled by the M bit of SCCR1.
5.4 Transmit operation
The SCI transmitter includes a parallel data register (SCDRH/SCDRL)
and a serial shift register. The contents of the shift register can only be
written through the serial data registers. This double buffered operation
allows a character to be shifted out serially while another character is
waiting in the serial data registers to be transferred into the shift register.
The output of the shift register is applied to TXD as long as transmission
is in progress or the transmit enable (TE) bit of serial communication
control register 2 (SCCR2) is set. The block diagram, Figure 5-2, shows
the transmit serial shift register and the buffer logic at the top of the
figure.
5.5 Receive operation
During receive operations, the transmit sequence is reversed. The serial
shift register receives data and transfers it to the parallel receive data
registers (SCDRH/SCDRL) as a complete word. This double buffered
operation allows a character to be shifted in serially while another
character is still in the serial data registers. An advanced data recovery
scheme distinguishes valid data from noise in the serial data stream.
The data input is selectively sampled to detect receive data, and majority
sampling logic determines the value and integrity of each bit.
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Technical Data
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
T8
LOOPS
10/11-bit TX shift register
WOMS
H 8 7
†
TXD1
0 L
M
WAKE
ST4XCK
clock
LOOPS
ILT
M
PE
PE
PT
PT
Transmitter
control
TE
Flag control
Rate generator
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SBK
TIE
WAKE
ILIE
PE
TE
PT
RE
RE
RWU
Receiver
RWU
SBK
SCBDL
SCCR2
TCIE
RIE
WOMS
SCBDH
SCCR1
Transmit buffer
control
M
LOOPS
WOMS
ILT
10/11-bit RX shift register
8 7
0
STOP
Receive buffer
PF
RAF
SCSR2
FE
NF
OR
IDLE
TC
SCSR1
RDRF
RXD1
START
R8
TDRE
Data
recovery
OR
RIE
&
IDLE
ILIE
&
RDRF
RIE
&
+
SCI interrupt request
TC
TCIE
TDRE
TIE
&
Note: † = always reads as zero
&
Internal data bus
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Wakeup feature
5.6 Wakeup feature
The wakeup feature reduces SCI service overhead in multiple receiver
systems. Software for each receiver evaluates the first character or
frame of each message. All receivers are placed in wakeup mode by
writing a one to the RWU bit in the SCCR2 register. When RWU is set,
the receiver-related status flags (RDRF, IDLE, OR, NF, FE, and PF) are
inhibited (cannot be set). Although RWU can be cleared by a software
write to SCCR2, to do so would be unusual. Normally RWU is set by
software and is cleared automatically with hardware. Whenever a new
message begins, logic alerts the dormant receivers to wake up and
evaluate the initial character of the new message.
Two methods of wakeup are available: idle-line wakeup and address
mark wakeup. During idle-line wakeup, a dormant receiver activates as
soon as the RXD line becomes idle. In the address mark wakeup, logic
one in the most significant bit (MSB) of a character activates all sleeping
receivers. To use either receiver wakeup method, establish a software
addressing scheme to allow the transmitting devices to direct messages
to individual receivers or to groups of receivers. This addressing scheme
can take any form as long as all transmitting and receiving devices are
programmed to understand the same scheme.
5.6.1 Idle-line wakeup
Clearing the WAKE bit in SCCR1 register enables idle-line wakeup
mode. In idle-line wakeup mode, all receivers are active (RWU bit in
SCCR2 = 0) when each message begins. The first frames of each
message are addressing frames. Each receiver in the system evaluates
the addressing frames of a message to determine if the message is
intended for that receiver. When a receiver finds that the message is not
intended for it, it sets the RWU bit. Once set, the RWU control bit
disables all but the necessary receivers for the remainder of the
message, thus reducing software overhead for the remainder of that
message. As soon as an idle line is detected by receiver logic, hardware
automatically clears the RWU bit so that the first frames of the next
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Serial Communications Interface (SCI)
receiver wakeup requires a minimum of one idle frame time between
messages, and no idle time between frames within a message.
5.6.2 Address-mark wakeup
Setting the WAKE bit in SCCR1 register enables address-mark wakeup
mode. The address-mark wakeup method uses the MSB of each frame
to differentiate between address information (MSB = 1) and actual
message data (MSB = 0). All frames consist of seven information bits
(eight bits if M bit in SCCR1 = 1) and an MSB which, when set to one,
indicates an address frame. The first frames of each message are
addressing frames. Receiver logic evaluates these marked frames to
determine the receivers for which that message is intended. When a
receiver finds that the message is not intended for it, it sets the RWU bit.
Once set, the RWU control bit disables all but the necessary receivers
for the remainder of the message, thus reducing software overhead for
the remainder of that message. When the next message begins, its first
frame will have the MSB set which will automatically clear the RWU bit
and indicate that this is an addressing frame. This frame is always the
first frame received after wakeup because the RWU bit is cleared before
the stop bit for the first frame is received. This method of wakeup allows
messages to include idle times, however, there is a loss in efficiency due
to the extra bit time required for the address bit in each frame.
5.7 SCI error detection
Four error conditions can occur during SCI operation. These error
conditions are: serial data register overrun, received bit noise, framing,
and parity error. Four bits (OR, NF, FE, and PF) in serial
communications status register 1 (SCSR1) indicate if one of these error
conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be
transferred from the receive shift register to the serial data registers
(SCDRH/SCDRL) and the registers are already full (RDRF bit is set).
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Serial Communications Interface (SCI)
SCI registers
The OR is cleared when the SCSR is read (with OR set), followed by a
read of the SCI data registers.
The noise flag (NF) bit is set if there is noise on any of the received bits,
including the start and stop bits. The NF bit is not set until the RDRF flag
is set. The NF bit is cleared when the SCSR is read (with FE equal to
one) followed by a read of the SCI data registers.
When no stop bit is detected in the received data character, the framing
error (FE) bit is set. FE is set at the same time as the RDRF. If the byte
received causes both framing and overrun errors, the processor only
recognizes the overrun error. The framing error flag inhibits further
transfer of data into the SCI data registers until it is cleared. The FE bit
is cleared when the SCSR is read (with FE equal to one) followed by a
read of the SCI data registers.
The parity error flag (PF) is set if received data has incorrect parity. The
flag is cleared by a read of SCSR1 with PE set, followed by a read of
SCDR.
5.8 SCI registers
There are eight addressable registers in the SCI. SCBDH, SCBDL,
SCCR1, and SCCR2 are control registers. The contents of these
registers control functions and indicate conditions within the SCI. The
status registers SCSR1 and SCSR2 contain bits that indicate certain
conditions within the SCI. SCDRH and SCDRL are SCI data registers.
These double buffered registers are used for the transmission and
reception of data, and are used to form the 9-bit data word for the SCI.
If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be
accessed. Note that if 9-bit data format is used, the upper register should
be written first to ensure that it is transferred to the transmitter shift
register with the lower register.
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Serial Communications Interface (SCI)
5.8.1 SCBDH, SCBDL — SCI baud rate control registers
Address bit 7
bit 6
bit 5
0
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SCI 1 baud rate high (SCBDH)
$0070 BTST BSPL
SBR12 SBR11 SBR10 SBR9 SBR8 0000 0000
SCI 1 baud rate low (SCBDL)
$0071 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0000 0100
The contents of this register determine the baud rate of the SCI.
BTST — Baud register test (Test mode only)
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BSPL — Baud rate counter split (Test mode only)
Bit 5 — Not implemented; always reads zero
SBR[12:0] — SCI baud rate selects
Use the following formula to calculate SCI baud rate. Refer to the
table of baud rate control values for example rates:
ST4XCK
SCI baud rate = ----------------------------16 × ( 2BR )
where the baud rate control value (BR) is the contents of SCBDH/L
(BR = 1, 2, 3,... 8191).
BR = 0 disables the baud rate generator. For example, to obtain a
baud rate of 1200 with a 12MHz crystal, the baud register (SCBDH/L)
should contain $0138 (see Table 5-1).
NOTE:
ST4XCK may be the output of the PLL circuit or it may be the EXTAL
input of the MCU. Selection is made by the MCS bit in the PLLCR (see
Crystal driver and external clock input (XTAL, EXTAL)).
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
SCI registers
Table 5-1. Example SCI baud rate control values
Target
baud
rate
110
150
300
600
1200
2400
4800
9600
19200
38400
Crystal frequency (EXTAL)
8 MHz
12 MHz
16 MHz
Dec
Hex
Dec
Hex
Dec
Hex
value
value
value
value
value
value
2272
$08E0
3409
$0D51
4545
$11C1
1666
$0682
2500
$09C4
3333
$0D05
833
$0341
1250
$04E2
1666
$0682
416
$01A0
625
$0271
833
$0341
208
$00D0
312
$0138
416
$01A0
104
$0068
156
$009C
208
$00D0
52
$0034
78
$004E
104
$0068
26
$001A
39
$0027
52
$0034
13
$000D
20
$0014
26
$001A
13
$000D
5.8.2 SCCR1 — SCI control register 1
Address bit 7
SCI 1 control 1 (SCCR1)
$0072
bit 6
LOOP
WOMS
S
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0
M
WAKE
ILT
PE
PT
0000 0000
The SCCR1 register provides the control bits that determine word length
and select the method used for the wakeup feature.
LOOPS — SCI loop mode enable
1 = SCI transmit and receive are disconnected from TXD and RXD
pins, and transmitter output is fed back into the receiver input.
0 = SCI transmit and receive operate normally.
Both the transmitter and receiver must be enabled to use the LOOP
mode. When the LOOP mode is enabled, the TXD pin is driven high
(idle line state) if the transmitter is enabled.
WOMS — Wired-OR mode for SCI pins (PD1, PD0)
1 = TXD and RXD are open drains if operating as outputs.
0 = TXD and RXD operate normally.
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Serial Communications Interface (SCI)
M — Mode (select character format)
1 = Start bit, 9 data bits, 1 stop bit.
0 = Start bit, 8 data bits, 1 stop bit.
WAKE — Wakeup by address mark/idle
1 = Wakeup by address mark (most significant data bit set).
0 = Wakeup by IDLE line recognition.
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ILT — Idle line type
1 = Long (SCI counts ones only after stop bit).
0 = Short (SCI counts consecutive ones after start bit).
This bit determines which of two types of idle line detection method is
used by the SCI receiver. In short mode the stop bit and any bits that
were ones before the stop bit will be considered as part of that string
of ones, possibly resulting in erroneous or premature detection of an
idle line condition. In long mode the SCI system does not begin
counting ones until a stop bit is received.
PE — Parity enable
1 = Parity enabled.
0 = Parity disabled.
PT — Parity type
1 = Parity odd (an odd number of ones causes parity bit to be zero,
an even number of ones causes parity bit to be one).
0 = Parity even (an even number of ones causes parity bit to be
zero, an odd number of ones causes parity bit to be one).
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Serial Communications Interface (SCI)
SCI registers
5.8.3 SCCR2 — SCI control register 2
Address bit 7
SCI 1 control 2 (SCCR2)
$0073
TIE
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TCIE
RIE
ILIE
TE
RE
RWU
SBK 0000 0000
The SCCR2 register provides the control bits that enable or disable
individual SCI functions.
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TIE — Transmit interrupt enable
1 = SCI interrupt requested when TDRE status flag is set.
0 = TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
1 = SCI interrupt requested when TC status flag is set.
0 = TC interrupts disabled.
RIE — Receiver interrupt enable
1 = SCI interrupt requested when RDRF flag or the OR status flag
is set.
0 = RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 = SCI interrupt requested when IDLE status flag is set.
0 = IDLE interrupts disabled.
TE — Transmitter enable
1 = Transmitter enabled.
0 = Transmitter disabled.
RE — Receiver enable
1 = Receiver enabled.
0 = Receiver disabled.
RWU — Receiver wakeup control
1 = Wakeup enabled and receiver interrupts inhibited.
0 = Normal SCI receiver.
SBK — Send break
1 = Break codes generated as long as SBK is set.
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Serial Communications Interface (SCI)
5.8.4 SCSR1 — SCI status register 1
Address bit 7
SCI 1 status 1 (SCSR1)
$0074 TDRE
bit 6
TC
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
RDRF IDLE
OR
NF
FE
PF
1100 0000
bit 5
The bits in SCSR1 indicate certain conditions in the SCI hardware and
are automatically cleared by special acknowledge sequences.
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TDRE — Transmit data register empty flag
1 = SCDR empty.
0 = SCDR busy.
This flag is set when SCDR is empty. Clear the TDRE flag by reading
SCSR1 with TDRE set and then writing to SCDR.
TC — Transmit complete flag
1 = Transmitter idle.
0 = Transmitter busy.
This flag is set when the transmitter is idle (no data, preamble, or
break transmission in progress). Clear the TC flag by reading SCSR1
with TC set and then writing to SCDR.
RDRF — Receive data register full flag
1 = SCDR full.
0 = SCDR empty.
Once cleared, IDLE is not set again until the RXD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SCDR. Clear the RDRF flag by reading SCSR1 with
RDRF set and then reading SCDR.
IDLE — Idle line detected flag
1 = RXD line is idle.
0 = RXD line is active.
This flag is set if the RXD line is idle. Once cleared, IDLE is not set
again until the RXD line has been active and becomes idle again. The
IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1
with IDLE set and then reading SCDR.
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Serial Communications Interface (SCI)
SCI registers
OR — Overrun error flag
1 = Overrun detected.
0 = No overrun.
OR is set if a new character is received before a previously received
character is read from SCDR. Clear the OR flag by reading SCSR1
with OR set and then reading SCDR.
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NF — Noise error flag
1 = Noise detected.
0 = Unanimous decision.
NF is set if the majority sample logic detects anything other than a
unanimous decision. Clear NF by reading SCSR1 with NF set and
then reading SCDR.
FE — Framing error
1 = Zero detected.
0 = Stop bit detected.
FE is set when a zero is detected where a stop bit was expected.
Clear the FE flag by reading SCSR1 with FE set and then reading
SCDR.
PF — Parity error flag
1 = Incorrect parity detected.
0 = Parity correct.
PF is set if received data has incorrect parity. Clear PF by reading
SCSR1 with PE set and then reading SCDR.
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Serial Communications Interface (SCI)
5.8.5 SCSR2 — SCI status register 2
Address bit 7
SCI 1 status 2 (SCSR2)
$0075
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0
0
0
0
0
0
0
bit 0
State
on reset
RAF 0000 0000
In the SCSR2 only bit 0 is used, to indicate receiver active. The other
seven bits always read zero.
Bits [7:1] — Not implemented; always read zero
RAF — Receiver active flag (read only)
1 = A character is being received.
0 = A character is not being received.
5.8.6 SCDRH, SCDRL — SCI data high/low registers
Address bit 7
SCI 1 data high (SCDRH)
$0076
SCI 1 data low (SCDRL)
$0077
R8
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
T8
0
0
0
0
0
0
undefined
R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 undefined
SCDRH/SCDRL is a parallel register that performs two functions. It is the
receive data register when it is read, and the transmit data register when
it is written. Reads access the receive data buffer and writes access the
transmit data buffer. Data received or transmitted is double buffered.
R8 — Receiver bit 8
Ninth serial data bit received when SCI is configured for a nine data
bit operation
T8 — Transmitter bit 8
Ninth serial data bit transmitted when SCI is configured for a nine data
bit operation
Bits [5:0] — Not implemented; always read zero
R/T[7:0] — Receiver/transmitter data bits [7:0]
SCI data is double buffered in both directions.
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Serial Communications Interface (SCI)
Status flags and interrupts
5.9 Status flags and interrupts
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The SCI transmitter has two status flags. These status flags can be read
by software (polled) to tell when certain conditions exist. Alternatively, a
local interrupt enable bit can be set to enable each of these status
conditions to generate interrupt requests. Status flags are automatically
set by hardware logic conditions, but must be cleared by software. This
provides an interlock mechanism that enables logic to know when
software has noticed the status indication. The software clearing
sequence for these flags is automatic — functions that are normally
performed in response to the status flags also satisfy the conditions of
the clearing sequence.
TDRE and TC flags are normally set when the transmitter is first enabled
(TE set to one). The TDRE flag indicates there is room in the transmit
queue to store another data character in the transmit data register. The
TIE bit is the local interrupt mask for TDRE. When TIE is zero, TDRE
must be polled. When TIE and TDRE are one, an interrupt is requested.
The TC flag indicates the transmitter has completed the queue. The
TCIE bit is the local interrupt mask for TC. When TCIE is zero, TC must
be polled; when TCIE is one and TC is one, an interrupt is requested.
Writing a zero to TE requests that the transmitter stop when it can. The
transmitter completes any transmission in progress before shutting
down. Only an MCU reset can cause the transmitter to stop and shut
down immediately. If TE is cleared when the transmitter is already idle,
the pin reverts to its general-purpose I/O function (synchronized to the
bit-rate clock). If anything is being transmitted when TE is cleared, that
character is completed before the pin reverts to general-purpose I/O, but
any other characters waiting in the transmit queue are lost. The TC and
TDRE flags are set at the completion of this last character, even though
TE has been disabled.
MC68HC11P2 — Rev 1.0
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Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
5.9.1 Receiver flags
The SCI receiver has seven status flags, three of which can generate
interrupt requests. The status flags are set by the SCI logic in response
to specific conditions in the receiver. These flags can be read (polled) at
any time by software. Refer to Figure 5-3, which shows SCI interrupt
arbitration.
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When an overrun takes place, the new character is lost, and the
character that was in its way in the parallel receive data register (RDR)
is undisturbed. RDRF is set when a character has been received and
transferred into the parallel RDR. The OR flag is set instead of RDRF if
overrun occurs. A new character is ready to be transferred into the RDR
before a previous character is read from the RDR.
The NF, FE and PF flags provide additional information about the
character in the RDR, but do not generate interrupt requests.
The receiver active flag (RAF) indicates that the receiver is busy.
The last receiver status flag and interrupt source come from the IDLE
flag. The RXD line is idle if it has constantly been at logic one for a full
character time. The IDLE flag is set only after the RXD line has been
busy and becomes idle. This prevents repeated interrupts for the time
RXD remains idle.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Status flags and interrupts
Note: The bit names shown are for SCI1. The
diagram applies equally to SCI2 and SCI3,
when the appropriate bit names are
substituted.
Begin
Yes
RDRF = 1?
No
Yes
OR = 1?
No
RIE = 1?
Yes
No
Yes
TDRE = 1?
No
TIE = 1?
Yes
No
TCIE = 1?
Yes
No
Yes
No
TC = 1?
RE = 1?
TE = 1?
Yes
No
Yes
No
Yes
IDLE = 1?
No
ILIE = 1?
No
Yes
RE = 1?
Yes
No
No valid SCI
interrupt request
Valid SCI
interrupt request
Figure 5-3. Interrupt source resolution within SCI
MC68HC11P2 — Rev 1.0
Technical Data
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Serial Communications Interface (SCI)
5.10 Additional SCI subsystems
In addition to the subsystem described in the above paragraphs (SCI1),
the MC68HC11P2 has two other, similar, SCI modules (SCI2, SCI3).
These two systems are identical to that described, with the following
exceptions:
SCI2 and SCI3 share I/O with four port H pins:
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Pin
PH4
PH5
PH6
PH7
Alternate
function
RXD2
TXD2
RXD3
TXD3
The SCI2 transmit and receive functions are enabled by TE2 and RE2
respectively, in S2CR2; similarly, the SCI3 transmit and receive
functions are enabled by TE3 and RE3 respectively, in S3CR2.
SCI1 functions and data are handled by a register block at
$0070–$0077. The corresponding registers for SCI2 and SCI3 are at
addresses $0050–$0057 and $005A–$005F respectively, as shown in
the following sections.
SCI2 and SCI3 share the same baud rate register (at $0050/51).
In addition to their SCI functions, these two subsystems are also used
for MI BUS, controlled by bit 5 of their respective SCCR1 registers. Refer
to Motorola Interconnect Bus (MI BUS) for full details of MI BUS
operation.
5.10.1 SCI2
SCI2 shares I/O with two of port H’s pins: receive pin RXD2/PH6 and
transmit pin TXD2/PD7. The SCI receive and transmit functions are
enabled by RE and TE respectively, in S2CR2.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Additional SCI subsystems
5.10.1.1 S2BDH, S2BDL — SCI2/3 baud rate control registers
Address bit 7
bit 6
SCI/MI 2/3 baud high (S2BDH)
$0050 B2TST B2SPL
SCI/MI 2/3 baud low (S2BDL)
$0051
bit 5
0
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
S2B12 S2B11 S2B10 S2B9 S2B8 0000 0000
S2B7 S2B6 S2B5 S2B4 S2B3 S2B2 S2B1 S2B0 0000 0100
The contents of this register determine the baud rate for both SCI2 and
SCI3. For details of the bits and the corresponding baud rates see
SCBDH, SCBDL — SCI baud rate control registers. This register also
controls the MI BUS clock rate (see Motorola Interconnect Bus
(MI BUS)).
5.10.1.2 S2CR1 — SCI2 control register 1
Address bit 7
SCI/MI 2 control 1 (S2CR1)
$0052 LOPS2
bit 6
bit 5
bit 4
WOMS
MIE2
2
M2
bit 3
State
on reset
bit 2
bit 1
bit 0
WAKE
ILT2
2
PE2
PT2 0000 0000
The S2CR1 register provides the control bits that determine word length
and select the method used for the wakeup feature. Bit 5 has an MI BUS
control function detailed below (for details of the other bits see SCCR1
— SCI control register 1).
MIE2 — Motorola interface bus enable 2
1 = MI BUS is enabled for this subsystem.
0 = The SCI functions normally.
When MIE2 is set, the SCI2 registers, bits and pins assume the
functionality required for MI BUS.
5.10.1.3 S2CR2 — SCI2 control register 2
Address bit 7
SCI/MI 2 control 2 (S2CR2)
$0053
bit 6
bit 1
bit 0
State
on reset
bit 5
bit 4
bit 3
bit 2
TIE2 TCIE2 RIE2
ILIE2
TE2
RE2 RWU2 SBK2 0000 0000
The S2CR2 register provides the control bits that enable or disable
individual SCI functions. For details of the bits, see SCCR2 — SCI
MC68HC11P2 — Rev 1.0
Technical Data
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Serial Communications Interface (SCI)
5.10.1.4 S2SR1 — SCI2 status register 1
Address bit 7
SCI/MI 2 status 1 (S2SR1)
bit 6
bit 5
bit 4
State
on reset
bit 3
bit 2
bit 1
bit 0
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2
NF2
FE2
PF2 1100 0000
The bits in S2SR1 indicate certain conditions in the SCI hardware and
are automatically cleared by special acknowledge sequences. For
details of the bits, see SCSR1 — SCI status register 1.
5.10.1.5 S2SR2 — SCI2 status register 2
Address bit 7
SCI/MI 2 status 2 (S2SR2)
$0055
0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0
0
0
0
0
0
bit 0
State
on reset
RAF2 0000 0000
In the S2SR2 only bit 0 is used, to indicate receiver active (see SCSR2
— SCI status register 2). The other seven bits always read zero.
5.10.1.6 S2DRH, S2DRL — SCI2 data high/low registers
Address bit 7
R8B
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
T8B
0
0
0
0
0
0
undefined
SCI/MI 2 data high (S2DRH)
$0056
SCI/MI 2 data low (S2DRL)
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undefined
S2DRH/S2DRL is a parallel register that performs two functions. It is the
receive data register when it is read, and the transmit data register when
it is written. Reads access the receive data buffer and writes access the
transmit data buffer. Data received or transmitted is double buffered.
See SCDRH, SCDRL — SCI data high/low registers for more details.
5.10.2 SCI3
SCI3 shares I/O with two of port H’s pins: receive pin RXD3/PH4 and
transmit pin TXD3/PD5. The SCI receive and transmit functions are
enabled by RE and TE respectively, in S3CR2.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Additional SCI subsystems
5.10.2.1 S3CR1 — SCI3 control register 1
Address bit 7
SCI/MI 3 control 1 (S3CR1)
bit 6
bit 5
bit 4
$005A LOPS3 WOMS3 MIE3
M3
bit 3
State
on reset
bit 2
bit 1
bit 0
WAKE3 ILT3
PE3
PT3 0000 0000
The S3CR1 register provides the control bits that determine word length
and select the method used for the wakeup feature. Bit 5 has an MI BUS
control function detailed below (for details of the other bits see SCCR1
— SCI control register 1).
MIE3 — Motorola Interface Bus Enable 3
1 = MI BUS is enabled for this subsystem.
0 = The SCI functions normally.
When MIE3 is set, the SCI3 registers, bits and pins assume the
functionality required for MI BUS.
5.10.2.2 S3CR2 — SCI3 control register 2
Address bit 7
SCI/MI 3 control 2 (S3CR2)
$005B
bit 6
bit 1
bit 0
State
on reset
bit 5
bit 4
bit 3
bit 2
TIE3 TCIE3 RIE3
ILIE3
TE3
RE3 RWU3 SBK3 0000 0000
The S3CR2 register provides the control bits that enable or disable
individual SCI functions. For details of the bits, see SCCR2 — SCI
control register 2.
5.10.2.3 S3SR1 — SCI3 status register 1
Address bit 7
SCI/MI 3 status 1 (S3SR1)
bit 6
bit 5
bit 4
State
on reset
bit 3
bit 2
bit 1
bit 0
$005C TDRE3 TC3 RDRF3 IDLE3 OR3
NF3
FE3
PF3 1100 0000
The bits in S3SR1 indicate certain conditions in the SCI hardware and
are automatically cleared by special acknowledge sequences. For
details of the bits, see SCSR1 — SCI status register 1.
MC68HC11P2 — Rev 1.0
Technical Data
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
5.10.2.4 S3SR2 — SCI3 status register 2
Address bit 7
SCI/MI 3 status 2 (S3SR2)
$005D
0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0
0
0
0
0
0
bit 0
State
on reset
RAF3 0000 0000
In S3SR2 only bit 0 is used, to indicate receiver active (see SCSR2 —
SCI status register 2 for details). The other seven bits always read zero.
5.10.2.5 S3DRH, S3DRL — SCI3 data high/low registers
Address bit 7
R8C
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
T8C
0
0
0
0
0
0
undefined
SCI/MI 3 data high (S3DRH)
$005E
SCI/MI 3 data low (S3DRL)
$005F R7T7C R6T6C R5T5C R4T4C R3T3C R2T2C R1T1C R0T0C undefined
S3DRH/S3DRL is a parallel register that performs two functions. It is the
receive data register when it is read, and the transmit data register when
it is written. Reads access the receive data buffer and writes access the
transmit data buffer. Data received or transmitted is double buffered.
See SCDRH, SCDRL — SCI data high/low registers for more details.
Technical Data
MC68HC11P2 — Rev 1.0
Serial Communications Interface (SCI)
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Technical Data — MC68HC11P2
Section 6. Motorola Interconnect Bus (MI BUS)
6.1 Contents
6.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3
Push-pull sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.4
The push field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
6.5
The pull field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.6
Biphase coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.7
Message validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.8
Interfacing to MI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.9
MI BUS clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.10
SCI/MI BUS2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.11
SCI/MI BUS3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2 Introduction
The Motorola Interconnect Bus (MI BUS) is a serial communications
protocol which supports distributed real-time control efficiently and with
a high degree of noise immunity, at a typical bit rate for the data transfer
of 20kHz. The MI BUS is suitable for medium speed networks requiring
very low cost multiplex wiring; only one wire is required to connect to
slave devices.(1)
1. Related information on Motorola’s MI BUS is contained in the following Motorola publications:
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
The MC68HC11P2 contains two similar MI BUS modules. For ease of
reference, a full description of MI BUS2 is given, followed by a summary
of MI BUS3, detailing its differences.
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The MI BUS uses a push-pull sequence to transfer data. The master
device, which, in this case, is the MC68HC11P2, sends a push field to
the slave devices connected to the bus. The push field contains data
plus an address that is recognized by one of the slaves. The slave
addressed returns data which the master pulls from the MI BUS over the
same wire. Specific details of the message format are covered later in
this section. The MCU (master) can take the bus at any time, with a start
bit that violates the rules of Manchester biphase encoding. Up to eight
slave devices may be addressed by the MI BUS. Other features of
MI BUS include message validation, error detection, and default value
setting.
On the MC68HC11P2 the MI BUS module shares the same pins on port
H as the SCI2 and SCI3 modules. Data is transmitted (or ‘pushed’) via
the TXD pin, and received (‘pulled’) via the RXD pin. While data is being
pushed RXD will be disconnected from the receiver circuitry. The
message frame is handled automatically in hardware. The MCU register
interface is similar to that for the SCI.
Pin
PH4
PH5
PH6
PH7
Alternate
function
RXD2
TXD2
RXD3
TXD3
MI BUS2 functions are enabled by MIE2 in S2CR1; MI BUS3 functions
by MIE3 in S3CR1.
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Push-pull sequence
6.3 Push-pull sequence
Communication between the MCU and the slave device always utilizes
the same frame organization. First, the MCU sends serial data to the
selected device. This data field is called the ‘push field’. At the end of the
push field, the selected device automatically sends back to the MCU the
data held during the push sequence. The MCU reads the serial data sent
by the selected device. This data is called the ‘pull field’ and contains
status information followed by the end-of-frame information from the
selected device.
Time slots
Push (biphase coded)
Push-pull function
Pull (NRZ coded)
TXD pin (true data)
1 0
0 1
MI BUS wire
0 1 2 3 4 5 6 7
Start
Push
Start sync D0 D1 D2 D3 D4
A0
Data
A1
Pull
A2 sync
Address
Push field
(driven by MCU)
NRZ
Data
End of frame
Pull field
(driven by slave)
New frame
Bit fields
Stop
S3
S2
S1
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Message frame
Figure 6-1. MI BUS timing
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
6.4 The push field
The push field consists of a start bit, a push synchronization bit, a push
data field and a push address field. The start consists of three time slots
having the dominant logical state ‘0’. The start marks the beginning of
the message frame by violation of the rule of the Manchester code. The
push synchronization bit consists of a biphase coded ‘0’. Biphase coding
will be discussed later. The push data field consists of five bits of biphase
coded data. The push address consists of three bits of biphase coded
data. Data and address are written to the lower byte of the SCI data
register (S2DRL). The push data occupies the lower five bits and the
push address occupies the upper three bits of the register.
6.5 The pull field
The pull field consists of a pull synchronization bit, a pull data field and
an end of frame. The pull synchronization bit is a biphase coded ‘1’ and
is initiated by the MCU during the time slot after the last address bit of
the push field. The pull data field consists of an NRZ coded transmission,
each bit taking one time slot. Once shifted in, the pull data is stored in
the lower byte of the SCI data register (S2DRL). The end-of-frame field
is a square wave signal having a typical frequency of 20kHz ± 1%
tolerance (i.e. the bit rate of the push field) when the data sent to the
selected device is valid.
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
Biphase coding
6.6 Biphase coding
Manchester biphase L coding is used for the push field bits. Each bit
requires two time slots to encode the logic value of the bit. This encoding
allows the detection of a single error at the time slot level. Bits are
encoded as follows:
1 = In the first time slot, the logic level is set to zero, followed by a
logic level one in the second time slot;
0 = In the first time slot, the logic level is set to one, followed by a
logic level zero in the second time slot.
‘0’
‘1’
Biphase coded signal
0
1
2
3
4
5
a
6
7
0
1
b
2
3
4
5
a
6
7
t
b
Biphase detection
a’
a
b’
b
a’
a
b’
b
Noise detection
Figure 6-2. Biphase coding and error detection
6.7 Message validation
The communication between the MCU and the selected device is valid
when the MCU reads a pull data field having correct codes (excluding
the codes ‘111’ and ‘000’) followed by a square wave signal, having a
frequency of 20kHz, contained in the end-of-frame information.
An MI BUS error is detected when the pull field contains the code ‘111’
followed by the end-of-frame permanently tied to logical state ‘1’. This
means that the communication between the MCU and the selected
device was not accomplished.
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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6.7.1 Controller detected errors
There are three different MI BUS error types which are detected by the
selected slave device and are not mutually exclusive. The MCU cannot
determine which error occurred.
Noise error Slave devices take two samples in each time slot of
the biphase encoded push field. An error occurs when the two
samples for each time slot are not the same logical level.
Biphase error Slave devices receiving the push field detect the
biphase code. An error occurs when the two time slots of the
biphase code do not yield a logical exclusive-OR function.
Field error A field error is detected when the fixed-form of the
push field is violated.
6.7.2 MCU detected errors
There is a fourth error that can be detected by the MCU. This error
causes the noise flag (NF) to be asserted in the S2SR1 (or S3SR1)
register during the push field sequence.
Bit error A bit error can be detected by the MCU during the push
field. The MI BUS serial system monitors the bus via on-chip
hardware at the RXD pin at the same time as sending data. A bit
error is detected at that bit time when the value monitored is
different from the bit value sent.
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Message validation
T8
LOPS2
10/11-bit TX shift register
WOMS2
H 8 7
MIE2
M2
TXD2
0 L
WAKE2
ST4XCK
clock
ILT2
PE2
MIE2
PT2
PT2
Transmitter
control
TE2
TIE2
Flag control
Rate generator
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SBK2
TCIE2
ILIE2
TE2
MIE2
RE2
S2BDL
S2CR2
RIE2
RE2
WOMS
S2BDH
S2CR1
Transmit buffer
Receiver
RWU2
control
SBK2
WOMS
10/11-bit RX shift register
8 7
R8
†
RAF2
S2SR2
†
NF2
OR2
†
TC2
RDRF2
RXD2
START
Receive buffer
S2SR1
TDRE2
Data
recovery
0
STOP
OR2
RIE2
&
IDLE2
ILIE2
&
RDRF2
RIE2
&
+
SCI interrupt request
TC2
TCIE2
TDRE2
TIE2
&
&
Note: † = always reads as zero
= not used in MI BUS mode
Internal data bus
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
6.8 Interfacing to MI BUS
Physically the MI BUS consists of only a single wire. In the example
shown in Figure 6-4, only a single transistor and a few passive
components are required to connect up the MC68HC11P2 for full
MI BUS operation.
VDD
+12V
4.7k¾
1.2k¾
18V
MI BUS
VDD
T1
TX
3.9k¾
VDD
10k¾
MCU
22k¾
10k¾
RX
VSS
Figure 6-4. A typical interface between the MC68HC11P2 and the MI BUS
The transistor serves both to drive the MI BUS during the push field and
to protect the MCU TX pin from voltage transients generated in the
wiring. Without the transistor, EMI could damage the TX pin. Similarly,
the input pin (RX) is protected from EMI by clamping it to the MCU supply
rails with two diodes. When a load dump occurs, the zener diode (18V)
is switched on and hence turns the transistor on; this generates the logic
‘0’ state on the MI BUS. After eight time slots (200ms) of continuous ‘0’
state, all devices on the MI BUS will have their outputs disabled.
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
MI BUS clock rate
The MI BUS line can take two states, recessive or dominant. The
recessive state (‘1’) is represented by 5V, through a pull-up resistor of
10k¾. The dominant state (‘0’) is represented by a maximum 0.3V
(VCESAT of the transistor, T1).
The bus load depends on the number of devices on the bus. Each device
has a pull-up resistor of 10k¾. An external termination resistor is used
to stabilize the load resistance of the bus at 600¾.
6.9 MI BUS clock rate
The MI BUS clock rate is set via the SCI baud registers. To use the
MI BUS the ST4XCK clock frequency that drives the SCI clock generator
must be selected to match the minimum resolution of the MI BUS logic.
This is expressed by the following formula:
ST4XCK = 16 • 2n • (2 • Push_field_bit_rate) = 16 • 2n • 40kHz =
n • 1280kHz
where ‘n’ is an integer and 20kHz is the minimum Push field bit rate for
the MI BUS. Values for ST4XCK could be 1280kHz, 2560kHz, …, n •
1280kHz. The value ‘n’ is the modulus for the MI BUS baud register (see
S2BDH, S2BDL — MI BUS clock rate control registers). The
ST4XCK may be the output of the PLL circuit or it may be the EXTAL
input of the MCU. This selection is made by setting the MCS bit which is
described in PLLCR — PLL control register.
6.10 SCI/MI BUS2 registers
MI BUS operation is controlled by the same group of registers as is used
for the SCI. However the function of some of the bits is modified when in
MI BUS mode. A description of the registers, as applicable to the
MI BUS function, is given here.
NOTE:
Bits that have no meaning in MI BUS mode are shown shaded to avoid
confusion.
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
6.10.1 INIT2 — EEPROM mapping and MI BUS delay register
Address bit 7
EEPROM mapping (INIT2)
$0037
EE3
bit 3
bit 2
bit 1
bit 0
State
on reset
bit 6
bit 5
bit 4
EE2
EE1
EE0 M3DL1 M3DL0 M2DL1 M2DL0 0000 0000
This register sets the MI BUS delay time. INIT2 may be read at any time
but bits 7–4 may be written only once after reset in normal modes (bits
3–0 may be written at any time).
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EE[3:0] — EEPROM map position
EEPROM is located at $xD80–$xFFF, where x is the hexadecimal
digit represented by EE[3:0]. Refer to INIT2 — EEPROM mapping
and MI BUS delay register.
M3DL1:M3DL0, M2DL1:M2DL0 — MI BUS delay select
These bits are used to set up the delay for the start of the NRZ receive
for MI BUS operation as shown (for a 20kHz bit rate) in the following
table. Each MI BUS module is controlled by one pair of bits.
MxDL1
MxDL0
Delay factor
Delay time(1)
0
0
1
0
1
1
1
0
1
2
3
4
1.5625µs(2)
3.1250µs
4.6875µs
6.2500µs
1. 20kHz bit rate requires 25µs (40kHz) time slots.
2. 25µs ÷ 16
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
SCI/MI BUS2 registers
6.10.2 S2BDH, S2BDL — MI BUS clock rate control registers
Address bit 7
bit 6
bit 5
SCI/MI 2/3 baud high (S2BDH)
$0050 B2TST B2SPL
SCI/MI 2/3 baud low (S2BDL)
$0051
0
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
S2B12 S2B11 S2B10 S2B9 S2B8 0000 0000
S2B7 S2B6 S2B5 S2B4 S2B3 S2B2 S2B1 S2B0 0000 0100
The contents of this register determine the clock rate for both MI BUS 2
and MI BUS 3.
S2B[12:0] — SCI baud rate/ MI BUS clock rate selects
Use the following formula to calculate MI BUS 2/3 clock rate. Refer to
the table of baud rate control values (Table 5-1) for example rates:
ST4XCK
MI BUS clock rate = ----------------------------16 × ( 2BR )
where the baud rate control value (BR) is the contents of S2BDH/L
(BR = 1, 2, 3,... 8191).
BR = 0 disables the clock rate generator.
6.10.3 S2CR1 — MI BUS2 control register 1
Address bit 7
SCI/MI 2 control 1 (S2CR1)
bit 6
bit 5
bit 4
$0052 LOPS2WOMS2 MIE2
M2
bit 3
State
on reset
bit 2
bit 1
bit 0
WAKE2 ILT2
PE2
PT2 0000 0000
WOMS2 — Wired-OR mode for MI BUS2 pins (PH4, PH5)
1 = TXD2 and RXD2 are open drains if operating as outputs.
0 = TXD2 and RXD2 operate normally.
MIE2 — Motorola interface bus enable 2
1 = MI BUS is enabled for this subsystem.
0 = The SCI functions normally.
When MIE2 is set, the SCI2 registers, bits and pins assume the
functionality required for MI BUS.
PT2 — MI BUS TX polarity
1 = MI BUS transmit pin will send inverted data.
0 = MI BUS transmit pin functions normally.
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
6.10.4 S2CR2 — MI BUS2 control register 2
Address bit 7
SCI/MI 2 control 2 (S2CR2)
$0053
bit 6
bit 1
bit 0
State
on reset
bit 5
bit 4
bit 3
bit 2
TIE2 TCIE2 RIE2
ILIE2
TE2
RE2 RWU2 SBK2 0000 0000
RIE2 — Receiver interrupt enable 2
1 = MI BUS interrupt requested when RDRF2 flag is set.
0 = RDRF2 and OR2 interrupts disabled.
TE2 — Transmitter enable 2
1 = Transmitter enabled and port pin dedicated to the MI BUS.
0 = Transmitter disabled.
RE2 — Receiver enable 2
1 = Port pin dedicated to the MI BUS; the receiver is enabled by a
pull sync and is inhibited during a push field.
0 = Receiver disabled.
SBK2 — Send break 2
1 = MI transmit line is set low for 20 time slots.
0 = No action.
When an MI BUS wire is held low for eight or more time slots an
internal circuit on any slave device connected to the bus may reset or
preset the device with default values.
6.10.5 S2SR1 — MI BUS2 status register 1
Address bit 7
SCI/MI 2 status 1 (S2SR1)
bit 6
bit 5
bit 4
State
on reset
bit 3
bit 2
bit 1
bit 0
$0054 TDRE2 TC2 RDRF2 IDLE2 OR2
NF2
FE2
PF2 1100 0000
The bits in S2SR1 indicate certain conditions in the MI BUS hardware
and are automatically cleared by special acknowledge sequences. The
receive related flag bits in S2SR1 (RDRF2, OR2 and NF2) are cleared
by a read of this register followed by a read of the transmit/receive data
register. However, only those bits that were set when S2SR1 was read
will be cleared by the subsequent read of the transmit/receive data
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
SCI/MI BUS2 registers
RDRF2 — Receive data register full flag 2
1 = Contents of the receiver serial shift register have been
transferred to the receiver data register.
0 = Contents of the receiver serial shift register have not been
transferred to the receiver data register.
This bit is set when the contents of the receiver serial shift register
have been transferred to the receiver data register.
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The EOF (end-of-frame) during an MI BUS pull-field is a continuous
square wave, which will result in multiple RDRFs. This may be dealt
with in any of the following ways:
– By clearing the RIE2 mask, ignoring unneeded RDRF2s,
initiating a push field, waiting for TDRE2(1) and then clearing
the RDRF2;
– By clearing the RE2 bit when a pull field is complete, followed
by setting the RE2 bit after the TDRE2† flag associated with
the next push field is asserted;
– By disabling the MI BUS.
OR2 — Bit error 2
1 = A bit error has been detected.
0 = No bit error has been detected.
This bit is set when a push field bit value on the MI BUS does not
match the bit value that was sent. This is known as an MI BUS bit
error. OR2 does not generate an interrupt request in MI BUS mode.
NF2 — Noise error flag 2
1 = Noise detected.
0 = No noise detected.
This bit is set when noise is detected on the receive line during an
MI BUS pull field.
1. Note that TDREx and TCx will both behave in the same way as during normal SCI transmis-
MC68HC11P2 — Rev 1.0
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
6.10.6 S2SR2 — MI BUS2 status register 2
Address bit 7
SCI/MI 2 status 2 (S2SR2)
$0055
0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0
0
0
0
0
0
bit 2
bit 1
bit 0
State
on reset
RAF2 0000 0000
RAF — Receiver active flag (read only)
1 = A character is being received.
0 = A character is not being received.
6.10.7 S2DRL — MI BUS2 data register
Address bit 7
SCI/MI 2 data low (S2DRL)
bit 6
bit 5
bit 4
bit 3
bit 0
State
on reset
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undefined
0
1
0
1
S1
S2
S3
1
Pull field
A2
A1
A0
D4
D3
D2
D1
D0
Push field
This register forms the 8-bit data/address word for the MI push field and
contains the 3-bit data word received as the MI pull field.
R/T[7:0] — Receiver/transmitter data bits [7:0]
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI BUS receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI BUS. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
WRITE: Writes access the eight bits of the write-only MI BUS transmit
data register. MI BUS devices require a 5-bit data pattern followed by
a 3-bit address pattern to be sent during the push field. The data
pattern is mapped to the lowest five bits of the data register and the
address to the highest three bits, as shown in the above table. Thus
MI-data[4:0] is written to S2DRL[4:0] and MI-address[2:0] is written to
S2DRL[7:5].
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
SCI/MI BUS3 registers
6.11 SCI/MI BUS3 registers
The MI BUS2 and MI BUS3 modules share the MI BUS delay register
(INIT2) at $0037 and the MI BUS2 clock rate register (S2BDH/L) at
$0050–51. The two modules are functionally identical to one another
and the registers for MI BUS3 are given here for reference purposes
only. All explanations of bit function can be found in the relevant section
of the MI BUS2 register descriptions.
6.11.1 S3CR1 — MI BUS3 control register 1
Address bit 7
SCI/MI 3 control 1 (S3CR1)
bit 6
bit 5
bit 4
$005A LOPS3WOMS3 MIE3
M3
bit 3
State
on reset
bit 2
bit 1
bit 0
WAKE3 ILT3
PE3
PT3 0000 0000
bit 1
bit 0
6.11.2 S3CR2 — MI BUS3 control register 2
Address bit 7
SCI/MI 3 control 2 (S3CR2)
State
on reset
bit 5
bit 4
bit 3
bit 2
TIE3 TCIE3 RIE3
ILIE3
TE3
RE3 RWU3 SBK3 0000 0000
bit 4
bit 3
bit 2
bit 1
bit 0
$005C TDRE3 TC3 RDRF3 IDLE3 OR3
NF3
FE3
PF3 1100 0000
bit 0
$005B
bit 6
6.11.3 S3SR1 — MI BUS3 status register 1
Address bit 7
SCI/MI 3 status 1 (S3SR1)
bit 6
bit 5
State
on reset
6.11.4 S3SR2 — MI BUS3 status register 2
Address bit 7
SCI/MI 3 status 2 (S3SR2)
$005D
0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0
0
0
0
0
0
MC68HC11P2 — Rev 1.0
State
on reset
RAF3 0000 0000
Technical Data
Motorola Interconnect Bus (MI BUS)
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Motorola Interconnect Bus (MI BUS)
6.11.5 S3DRL — MI BUS3 data register
Address bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$005F R7T7C R6T6C R5T5C R4T4C R3T3C R2T2C R1T1C R0T0C undefined
0
1
0
1
S1
S2
S3
1
Pull field
A2
A1
A0
D4
D3
D2
D1
D0
Push field
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SCI/MI 3 data low (S3DRL)
bit 6
Technical Data
MC68HC11P2 — Rev 1.0
Motorola Interconnect Bus (MI BUS)
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Technical Data — MC68HC11P2
Section 7. Serial Peripheral Interface (SPI)
7.1 Contents
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
7.4
SPI transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.5
SPI signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.6
SPI system errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.7
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2 Introduction
The serial peripheral interface (SPI), an independent serial
communications subsystem, allows the MCU to communicate
synchronously with peripheral devices, such as transistor-transistor
logic (TTL) shift registers, liquid crystal (LCD) display drivers, analog-todigital converter subsystems, and other microprocessors. The SPI is
also capable of inter-processor communication in a multiple master
system. The SPI system can be configured as either a master or a slave
device, with data rates as high as one half of the E clock rate when
configured as a master and as fast as the E clock rate when configured
as a slave.
The SPI shares I/O with four of port D’s pins and is enabled by SPE in
the SPCR:
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
Pin
PD2
PD3
PD4
PD5
Alternate
function
MISO
MOSI
SCK
SS
7.3 Functional description
The central element in the SPI system is the block containing the shift
register and the read data buffer (see Figure 7-1). The system is single
buffered in the transmit direction and double buffered in the receive
direction. This means that new data for transmission cannot be written
to the shifter until the previous transfer is complete; however, received
data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read
out of the read data buffer before the next serial character is ready to be
transferred, no overrun condition occurs. A single MCU register address
is used for reading data from the read data buffer and for writing data to
the shifter.
The SPI status block represents the SPI status functions (transfer
complete, write collision, and mode fault) performed by the serial
peripheral status register (SPSR). The SPI control block represents
those functions that control the SPI system through the serial peripheral
control register (SPCR).
7.4 SPI transfer formats
During an SPI transfer, data is simultaneously transmitted and received.
A serial clock line synchronizes shifting and sampling of the information
on the two serial data lines. A slave select line allows individual selection
of a slave SPI device; slave devices that are not selected do not interfere
with SPI bus activities. On a master SPI device, the select line can
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
SPI transfer formats
optionally be used to indicate a multiple master bus contention. Refer to
Figure 7-2.
MISO
PD2
S
M
M
MCU
system clock
MOSI
PD3
S
8-bit shift register
Read data buffer
Divider
Shift control logic
Pin
control
logic
÷8 ÷16 ÷32 ÷64 ÷128
Clock
SPI clock (master)
Select
S
Clock
logic
SCK
PD4
M
OPT2 – Options register 2
MSTR
DWOM
MSTR
SPR2
SS
PD5
SPE
÷4
LSBF
÷2
LSBF
SPE
SPI control
SPSR – SPI status register
SPR0
SPR1
CPHA
CPOL
MSTR
DWOM
SPE
SPIE
MODF
WCOL
SPIE
SPIF
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SPCR – SPI control register
SPDR – SPI data register
SPI interrupt
request
Internal bus
Figure 7-1. SPI block diagram
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
SCK cycle #
(for reference)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
Sample input
Data out (CPHA=0)
MSB
6
5
4
3
2
1
LSB
Sample input
Data out (CPHA=1)
MSB
6
5
4
3
2
1
LSB
SS (to slave)
Note: this figure shows the LSBF=0 (default) case. If LSBF=1, data is transferred in the reverse order (LSB first).
Figure 7-2. SPI transfer format
7.4.1 Clock phase and polarity controls
Software can select one of four combinations of serial clock phase and
polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or active low clock, and has no significant effect on the transfer format.
The clock phase (CPHA) control bit selects one of two different transfer
formats. The clock phase and polarity should be identical for the master
SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transfers to allow a master
device to communicate with peripheral slaves having different
requirements.
When CPHA equals zero, the SS line must be deasserted and
reasserted between each successive serial byte. Also, if the slave writes
data to the SPI data register (SPDR) while SS is low, a write collision
error results.
When CPHA equals one, the SS line can remain low between
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
SPI signals
7.5 SPI signals
The following paragraphs contain descriptions of the four SPI signals:
master in slave out (MISO), master out slave in (MOSI), serial clock
(SCK), and slave select (SS).
Any SPI output line must have its corresponding data direction bit in
DDRD register set. If the DDR bit is clear, that line is disconnected from
the SPI logic and becomes a general-purpose input. All SPI input lines
are forced to act as inputs regardless of the state of the corresponding
DDR bits in DDRD register.
7.5.1 Master in slave out
MISO is one of two unidirectional serial data signals. It is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
7.5.2 Master out slave in
The MOSI line is the second of the two unidirectional serial data signals.
It is an output from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
7.5.3 Serial clock
SCK, an input to a slave device, is generated by the master device and
synchronizes data movement in and out of the device through the MOSI
and MISO lines. Master and slave devices are capable of exchanging a
byte of information during a sequence of eight clock cycles.
There are four possible timing relationships that can be chosen by using
control bits CPOL and CPHA in the serial peripheral control register
(SPCR). Both master and slave devices must operate with the same
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Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
master device, select the clock rate. In a slave device, SPR[1:0] have no
effect on the operation of the SPI.
7.5.4 Slave select
The slave select SS input of a slave device must be externally asserted
before a master device can exchange data with the slave device. SS
must be low before data transactions begin and must stay low for the
duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault
error flag (MODF) is set in the serial peripheral status register (SPSR).
To disable the mode fault circuit, write a one in bit 5 of the port D data
direction register. This sets the SS pin to act as a general-purpose
output, rather than a dedicated input to the slave select circuit, thus
inhibiting the mode fault flag. The other three lines are dedicated to the
SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS.
CPHA settings should be identical for master and slave. When CPHA =
0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS
must go high between successive characters in an SPI message. When
CPHA = 1, SS can be left low between successive SPI characters. In
cases where there is only one SPI slave MCU, its SS line can be tied to
VSS as long as only CPHA = 1 clock mode is used.
7.6 SPI system errors
Two kinds of system errors can be detected by the SPI system. The first
type of error arises in a multiple-master system when more than one SPI
device simultaneously tries to be a master. This error is called a mode
fault. The second type of error, write collision, indicates that an attempt
was made to write data to the SPDR while a transfer was in progress.
When the SPI system is configured as a master and the SS input line
goes to active low, a mode fault error has occurred — usually because
Technical Data
MC68HC11P2 — Rev 1.0
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
SPI system errors
master, there is a chance of contention between two pin drivers. For
push-pull CMOS drivers, this contention can cause permanent damage.
The mode fault detection circuitry attempts to protect the device by
disabling the drivers. The MSTR control bit in the SPCR and all four
DDRD control bits associated with the SPI are cleared and an interrupt
is generated (subject to masking by the SPIE control bit and the I bit in
the CCR).
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Other precautions may need to be taken to prevent driver damage. If two
devices are made masters at the same time, the mode fault detector
does not help protect either one unless one of them selects the other as
slave. The amount of damage possible depends on the length of time
both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in
progress. Because the SPDR is not double buffered in the transmit
direction, writes to SPDR cause data to be written directly into the SPI
shift register. Because this write corrupts any transfer in progress, a
write collision error is generated. The transfer continues undisturbed,
and the write data that caused the error is not written to the shifter.
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. A master knows when a transfer
is in progress, so there is no reason for a master to generate a writecollision error, although the SPI logic can detect write collisions in both
master and slave devices.
The SPI configuration determines the characteristics of a transfer in
progress. For a master, a transfer begins when data is written to SPDR
and ends when SPIF is set. For a slave with CPHA equal to zero, a
transfer starts when SS goes low and ends when SS returns high. In this
case, SPIF is set at the middle of the eighth SCK cycle when data is
transferred from the shifter to the parallel data register, but the transfer
is still in progress until SS goes high. For a slave with CPHA equal to
one, transfer begins when the SCK line goes to its active level, which is
the edge at the beginning of the first SCK cycle. The transfer ends when
SPIF is set, for a slave in which CPHA=1.
MC68HC11P2 — Rev 1.0
Technical Data
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
7.7 SPI registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control,
status, and data storage functions. Refer to the following information for
a description of how these registers are organized.
7.7.1 SPCR — Serial peripheral control register
Address bit 7
SPI control (SPCR)
$0028
SPIE
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPIE — Serial peripheral interrupt enable
1 = A hardware interrupt sequence is requested each time SPIF or
MODF is set.
0 = SPI interrupts are inhibited.
Set the SPIE bit to a one to request a hardware interrupt sequence
each time the SPIF or MODF status flag is set. SPI interrupts are
inhibited if this bit is clear or if the I bit in the condition code register is
one.
SPE — Serial peripheral system enable
1 = Port D [5:2] is dedicated to the SPI.
0 = Port D has its default I/O functions.
When the SPE bit is set, the port D pins 2, 3, 4, and 5 are dedicated
to the SPI functions and lose their general purpose I/O functions.
When the SPI system is enabled and expects any of PD[4:2] to be
inputs then those pins will be inputs regardless of the state of the
associated DDRD bits. If any of PD[4:2] are expected to be outputs
then those pins will be outputs only if the associated DDRD bits are
set. However, if the SPI is in the master mode, DDD5 determines
whether PD5 is an error detect input (DDD5 = 0) or a general-purpose
output (DDD5 = 1).
DWOM — Port D wired-OR mode
1 = Port D [5:2] buffers configured for open-drain outputs.
0 = Port D [5:2] buffers configured for normal CMOS outputs.
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Serial Peripheral Interface (SPI)
SPI registers
MSTR — Master mode select
1 = Master mode
0 = Slave mode
CPOL — Clock polarity
1 = SCK is active low.
0 = SCK is active high.
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When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device has a steady state low
value. When CPOL is set, SCK idles high. Refer to Figure 7-2 and
Clock phase and polarity controls.
CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPHA bit
selects one of two different clocking protocols. Refer to Figure 7-2
and Clock phase and polarity controls.
SPR1 and SPR0 — SPI clock rate selects
These two bits select the SPI clock rate, as shown in Table 7-1. Note
that SPR2 is located in the OPT2 register and its state on reset is
zero.
Table 7-1. SPI clock rates
SPR[2:0]
E clock
divide ratio
000
001
010
011
100
101
110
111
2
4
16
32
8
16
64
128
SPI clock frequency (≡ baud rate) for:
E = 2MHz
E = 3MHz
E = 4MHz
1.0 MHz
1.5 MHz
2.0 MHz
500 kHz
750kHz
1.0 MHz
125 kHz
187.5 kHz
250 kHz
62.5 kHz
93.7 kHz
125 kHz
250 kHz
375 kHz
500 kHz
125 kHz
187.5 kHz
250 kHz
31.3 kHz
46.9 kHz
62.5 kHz
15.6 kHz
23.4 kHz
31.3 kHz
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Serial Peripheral Interface (SPI)
7.7.2 SPSR — Serial peripheral status register
Address bit 7
SPI status (SPSR)
$0029
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0
MODF
0
0
0
0
0000 0000
SPIF WCOL
SPIF — SPI interrupt complete flag
1 = Data transfer to external device has been completed.
0 = No valid completion of data transfer.
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SPIF is set upon completion of data transfer between the processor
and the external device. If SPIF goes high, and if SPIE is set, a serial
peripheral interrupt is generated. To clear the SPIF bit, read the SPSR
with SPIF set, then access the SPDR. Unless SPSR is read (with
SPIF set) first, attempts to write SPDR are inhibited.
WCOL — Write collision
1 = Write collision.
0 = No write collision.
Clearing the WCOL bit is accomplished by reading the SPSR (with
WCOL set) followed by an access of SPDR. Refer to Slave select
and SPI system errors.
MODF — Mode fault
1 = Mode fault.
0 = No mode fault.
To clear the MODF bit, read the SPSR (with MODF set), then write to
the SPCR. Refer to Slave select and SPI system errors.
Bits [5, 3:0] — Not implemented; always read zero.
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Serial Peripheral Interface (SPI)
SPI registers
7.7.3 SPDR — SPI data register
Address bit 7
SPI data (SPDR)
$002A (bit 7)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
The SPDR is used when transmitting or receiving data on the serial bus.
Only a write to this register initiates transmission or reception of a byte,
and this only occurs in the master device. At the completion of
transferring a byte of data, the SPIF status bit is set in both the master
and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun
and the loss of the byte that caused the overrun, the first SPIF must be
cleared by the time a second transfer of data from the shift register to the
read buffer is initiated.
SPI is double buffered in and single buffered out.
7.7.4 OPT2 — System configuration options register 2
Address bit 7
bit 6
System config. options 2 (OPT2) $0038 LIRDV CWOM
bit 5
bit 4
bit 3
bit 2
STRC
IRVNE LSBF SPR2
H
bit 1
bit 0
State
on reset
0
0
000x 0000
LIRDV — LIR driven (refer to Operating Modes and On-Chip Memory)
1 = Enable LIR drive high pulse.
0 = LIR only driven low – requires pull-up on pin.
CWOM — Port C wired-OR mode (refer to Parallel Input/Output)
1 = Port C outputs are open-drain.
0 = Port C operates normally.
STRCH — Stretch external accesses (refer to Operating Modes and
On-Chip Memory)
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
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IRVNE — Internal read visibility/not E (refer to Operating Modes and
On-Chip Memory)
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
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LSBF — LSB first enable
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
If this bit is set, data, which is usually transferred MSB first, is
transferred LSB first. LSBF does not affect the position of the MSB
and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 — SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain.
With the two bits in the SPCR, this bit specifies the SPI clock rate.
Refer to Table 7-1.
Bits 1, 0 — not implemented; always read zero.
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Technical Data — MC68HC11P2
Section 8. Timing System
8.1 Contents
8.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
8.3
Timer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8.4
Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.5
Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8.6
Real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
8.7
Computer operating properly watchdog function . . . . . . . 157
8.8
Pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
8.9
Pulse-width modulation (PWM) timer . . . . . . . . . . . . . . . . . 162
8.2 Introduction
The M68HC11 timing system is composed of five clock divider chains.
The main clock divider chain includes a 16-bit free-running counter,
which is driven by a programmable prescaler. The main timer’s
programmable prescaler provides one of the four clocking rates to drive
the 16-bit counter. Two prescaler control bits select the prescale rate.
The prescaler output divides the system clock by 1, 4, 8, or 16. Taps
from this main clocking chain drive circuitry generate the slower clocks
used by the pulse accumulator, the real-time interrupt (RTI), and the
computer operating properly (COP) watchdog subsystems, which are
also described in this section. Refer to Figure 8-1.
All main timer system activities are referenced to this free-running
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maximum count, the counter rolls over to $0000, sets an overflow flag
and continues to increment. As long as the MCU is running in a normal
operating mode, there is no way to reset, change or interrupt the
counting. The capture/compare subsystem features three input capture
channels, four output compare channels and one channel that can be
selected to perform either input capture or output compare. Each of the
three input capture functions has its own 16-bit input capture register
(time capture latch) and each of the output compare functions has its
own 16-bit compare register. All timer functions, including the timer
overflow and RTI, have their own interrupt controls and separate
interrupt vectors.
The pulse accumulator contains an 8-bit counter and edge select logic.
The pulse accumulator can operate in either event counting mode or
gated time accumulation mode. During event counting mode, the pulse
accumulator’s 8-bit counter increments when a specified edge is
detected on an input signal. During gated time accumulation mode, an
internal clock source increments the 8-bit counter while an input signal
has a predetermined logic level.
The real-time interrupt (RTI) is a programmable periodic interrupt circuit
that permits pacing the execution of software routines by selecting one
of four interrupt rates.
The COP watchdog clock input (E/215) is tapped off from the freerunning counter chain. The COP automatically times out unless it is
serviced within a specific time by a program reset sequence. If the COP
is allowed to time out, a reset is generated, which drives the RESET pin
low to reset the MCU and the external system. Refer to Table 8-1 for
crystal related frequencies and periods.
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Timing System
Timer structure
Table 8-1. Timer resolution and capacity
Control bits
PR[1:0]
4.0MHz
1.0MHz
1000ns
8.0MHz
2.0MHz
500ns
Clock
12.0MHz
3.0MHz
333ns
16.0MHz
4.0MHz
250ns
00
1.0µs
500ns
333ns
250ns
65.536ms 32.768ms 21.845ms 16.384ms
01
4.0µs
2.0µs
1.333µs
1.0µs
262.14ms 131.07ms 87.381ms 65.536ms
10
8.0µs
4.0µs
2.667µs
2.0µs
524.29ms 262.14ms 174.76ms 131.07ms
11
16.0µs
1049 ms
8.0µs
5.333µs
4.0µs
524.29ms 349.53ms 262.14ms
4E
E
1/E
1/E
216/E
4/E
218/E
8/E
219/E
16/E
220/E
XTAL
E clock
Period
– resolution
– overflow
– resolution
– overflow
– resolution
– overflow
– resolution
– overflow
8.3 Timer structure
The timer functions share I/O with all eight pins of port A:
Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Alternate function
IC3
IC2
IC1
OC5 and/or OC1, or IC4
OC4 and/or OC1
OC3 and/or OC1
OC2 and/or OC1
PAI and/or OC1
Figure 8-2 shows the capture/compare system block diagram. The port
A pin control block includes logic for timer functions and for generalpurpose I/O. For pins PA3, PA2, PA1 and PA0, this block contains both
the edge-detection logic and the control logic that enables the selection
of which edge triggers an input capture. The digital level on PA[3:0] can
be read at any time (read PORTA register), even if the pin is being used
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Timing System
used for an output compare function, it cannot be written directly as if it
were a general-purpose output. Each of the output compare functions
(OC[5:2]) is related to one of the port A output pins. Output compare 1
(OC1) has extra control logic, allowing it optional control of any
combination of the PA[7:3] pins. The PA7 pin can be used as a generalpurpose I/O pin, as an input to the pulse accumulator or as an OC1
output pin.
Baud
÷2
Oscillator and
clock generator
÷4
SCI receiver clock
÷ 1, 2, 3, 4, 5,…, 8191
÷ 16
÷2
SCI transmitter clock
E clock
Internal bus clock (PH2)
Prescaler
÷ 2, 4, 8,16, 32, 64, 128
SPI
SPR[2:0]
E/26
Pulse accumulator
Prescaler
÷ 1, 2, 4, 8
RTR[1:0]
13
E/2
Real time interrupt
÷4
E/215
Prescaler
÷ 1, 4, 8, 16
PR[1:0]
Prescaler
÷ 1, 4, 16, 64
CR[1:0]
TOF
TCNT
Set
Q
Set
Q
FF1
Reset
IC/OC
FF2
Q
+
Clear COP timer
System reset
Technical Data
Reset
Q
Force COP reset
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Timing System
Timer structure
Prescaler
÷ 1, 4, 8, 16
PR[1:0]
MCU
E clock
TCNT (hi) TCNT (lo)
TOI
16-bit
free running counter
TOF
&
Taps for RTI, COP and PA
CFORC
16-bit timer bus
Force O/P
compare
16-bit comparator EQ
9
Note †
To pulse accumulator
OC1I
&
8
OC1F
+
TOC1 (hi) TOC1 (lo)
Bit 7
FOC1
PA7/
OC1/
PAI
OC2I
&
16-bit comparator
EQ
7
OC2F
+
TOC2 (hi) TOC2 (lo)
Bit 6
PA6/
OC2/
OC1
Bit 5
PA5/
OC3/
OC1
Bit 4
PA4/
OC4/
OC1
Bit 3
PA3/
OC5/
OC1/
IC4
Bit 2
PA2/
IC1
Bit 1
PA1/
IC2
Bit 0
PA0/
IC3
FOC2
OC3I
&
16-bit
comparator EQ
6
OC3F
+
TOC3 (hi) TOC3 (lo)
FOC3
OC4I
&
16-bit comparator
EQ
5
OC4F
+
TOC4 (hi) TOC4 (lo)
FOC4
I4/O5I
&
16-bit
TI4/O5 (hi) TI4/O5 (lo)
16-bit latch
I4/O5F
+
FOC5
CLK
IC4
IC1I
I4/O5
&
16-bit latch
TIC1 (hi)
4
OC5
comparator EQ
CLK
3
IC1F
TIC1 (lo)
IC2I
&
16-bit latch
TIC2 (hi)
CLK
2
IC2F
TIC2 (lo)
IC3I
&
16-bit latch
TIC3 (hi)
CLK
TIC3 (lo)
1
IC3F
TFLG1
TMSK1
Port A
status
flags
interrupt
enables
pin
control‡
Pins/
functions
† Interrupt requests 1–9 (these are further qualified by the I-bit in the CCR)
‡ Port A pin actions are controlled by OC1M, OC1D, PACTL, TCTL1 and TCTL2 registers
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8.4 Input capture
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The input capture function records the time an external event occurs by
latching the value of the free-running counter when a selected edge is
detected at the associated timer input pin. Software can store latched
values and use them to compute the periodicity and duration of events.
For example, by storing the times of successive edges of an incoming
signal, software can determine the period and pulse width of a signal. To
measure period, two successive edges of the same polarity are
captured. To measure pulse width, two alternate polarity edges are
captured.
In most cases, input capture edges are asynchronous with respect to the
internal timer counter, which is clocked relative to an internal clock
(PH2). These asynchronous capture requests are synchronized with
PH2 so that latching occurs on the opposite half cycle of PH2 from when
the timer counter is being incremented. This synchronization process
introduces a delay from when the edge occurs to when the counter value
is detected. Because these delays cancel out when the time between
two edges is being measured, the delay can be ignored. When an input
capture is being used with an output compare, there is a similar delay
between the actual compare point and when the output pin changes
state.
The control and status bits that implement the input capture functions
are contained in the PACTL, TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDA3 bit of the
DDRA register. Note that this bit is cleared out of reset. To enable PA3
as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with
bit I4/O5 being cleared. If the DDA3 bit is set (configuring PA3 as an
output), and IC4 is enabled, then writes to PA3 cause edges on the pin
to result in input captures. Writing to TI4/O5 has no effect when the
TI4/O5 register is acting as IC4.
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Input capture
8.4.1 TCTL2 — Timer control register 2
Address bit 7
Timer control 2 (TCTL2)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0021 EDG4BEDG4AEDG1BEDG1AEDG2BEDG2AEDG3BEDG3A 0000 0000
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Use the control bits of this register to program input capture functions to
detect a particular edge polarity on the corresponding timer input pin.
Each of the input capture functions can be independently configured to
detect rising edges only, falling edges only, any edge (rising or falling),
or to disable the input capture function. The input capture functions
operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count cycle.
EDGxB and EDGxA — Input capture edge control
EDGxB
0
0
1
1
EDGxA
0
1
0
1
Configuration
ICx disabled
ICx captures on rising edges only
ICx captures on falling edges only
ICx captures on any edge
There are four pairs of these bits. Each pair is cleared by reset and
must be encoded to configure the corresponding input capture edge
detector circuit. IC4 functions only if the I4/O5 bit in the PACTL
register is set.
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8.4.2 TIC1–TIC3 — Timer input capture registers
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer input capture 1 (TIC1) high $0010 (bit 15) (14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
not
affected
Timer input capture 1 (TIC1) low $0011
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
Timer input capture 2 (TIC2) high $0012 (bit 15) (14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
not
affected
Timer input capture 2 (TIC2) low $0013 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
Timer input capture 3 (TIC3) high $0014 (bit 15) (14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
not
affected
Timer input capture 3 (TIC3) low $0015 (bit 7)
(5)
(4)
(3)
(2)
(1)
(bit 0)
not
affected
Address bit 7
(bit 7)
(6)
When an edge has been detected and synchronized, the 16-bit freerunning counter value is transferred into the input capture register pair
as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2
clock so that the count value is stable whenever a capture occurs. Input
capture values can be read from a pair of 8-bit read-only registers. A
read of the high-order byte of an input capture register pair inhibits a new
capture transfer for one bus cycle. If a double-byte read instruction, such
as LDD, is used to read the captured value, coherency is assured. When
a new input capture occurs immediately after a high-order byte read,
transfer is delayed for an additional cycle but the value is not lost.
The TICx registers are not affected by reset.
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Output compare
8.4.3 TI4/O5 — Timer input capture 4/output compare 5 register
Address bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
Capture 4/compare 5 (TI4/O5)
high
$001E (bit 15) (14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Capture 4/compare 5 (TI4/O5)
low
$001F (bit 7)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
(6)
bit 0
State
on reset
bit 6
Use TI4/O5 as either an input capture register or an output compare
register, depending on the function chosen for the PA3 pin. To enable it
as an input capture pin, set the I4/O5 bit in the pulse accumulator control
register (PACTL) to logic level one. To use it as an output compare
register, set the I4/O5 bit to a logic level zero. Refer to PACTL — Pulse
accumulator control register.
The TI4/O5 register pair resets to ones ($FFFF).
8.5 Output compare
Use the output compare (OC) function to program an action to occur at
a specific time — when the 16-bit counter reaches a specified value. For
each of the five output compare functions, there is a separate 16-bit
compare register and a dedicated 16-bit comparator. The value in the
compare register is compared to the value of the free-running counter on
every bus cycle. When the compare register matches the counter value,
an output compare status flag is set. The flag can be used to initiate the
automatic actions for that output compare function.
To produce a pulse of a specific duration, write a value to the output
compare register that represents the time the leading edge of the pulse
is to occur. The output compare circuit is configured to set the
appropriate output either high or low, depending on the polarity of the
pulse being produced. After a match occurs, the output compare register
is reprogrammed to change the output pin back to its inactive level at the
next match. A value representing the width of the pulse is added to the
original value, and then written to the output compare register. Because
the pin state changes occur at specific values of the free-running
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the free-running counter, independent of software latency. To generate
an output signal of a specific frequency and duty cycle, repeat this pulsegenerating procedure.
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There are four 16-bit read/write output compare registers: TOC1, TOC2,
TOC3, and TOC4, and the TI4/O5 register, which functions under
software control as either IC4 or OC5. Each of the OC registers is set to
$FFFF on reset. A value written to an OC register is compared to the
free-running counter value during each E clock cycle. If a match is found,
the particular output compare flag is set in timer interrupt flag register 1
(TFLG1). If that particular interrupt is enabled in the timer interrupt mask
register 1 (TMSK1), an interrupt is generated. In addition to an interrupt,
a specified action can be initiated at one or more timer output pins. For
OC[5:2], the pin action is controlled by pairs of bits (OMx and OLx) in the
TCTL1 register. The output action is taken on each successful compare,
regardless of whether or not the OCxF flag in the TFLG1 register was
previously cleared.
OC1 is different from the other output compares in that a successful OC1
compare can affect any or all five of the OC pins. The OC1 output action
taken when a match is found is controlled by two 8-bit registers with
three bits unimplemented: the output compare 1 mask register, OC1M,
and the output compare 1 data register, OC1D. OC1M specifies which
port A outputs are to be used, and OC1D specifies what data is placed
on these port pins.
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Timing System
Output compare
8.5.1 TOC1–TOC4 — Timer output compare registers
Address bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
Timer output compare 1 (TOC1)
$0016 (bit 15) (14)
high
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 1 (TOC1)
$0017 (bit 7)
low
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer output compare 2 (TOC2)
$0018 (bit 15) (14)
high
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 2 (TOC2)
$0019 (bit 7)
low
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer output compare 3 (TOC3)
$001A (bit 15) (14)
high
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 3 (TOC3)
$001B (bit 7)
low
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer output compare 4 (TOC4)
$001C (bit 15) (14)
high
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 4 (TOC4)
$001D (bit 7)
low
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
(6)
bit 0
State
on reset
bit 6
All output compare registers are 16-bit read-write. Each is initialized to
$FFFF at reset. If an output compare register is not used for an output
compare function, it can be used as a storage location. A write to the
high-order byte of an output compare register pair inhibits the output
compare function for one bus cycle. This inhibition prevents
inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses
can be used.
For output compare functions, write a comparison value to output
compare registers TOC1–TOC4 and TI4/O5. When TCNT value
matches the comparison value, specified pin actions occur.
All TOCx register pairs reset to ones ($FFFF).
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8.5.2 CFORC — Timer compare force register
Address bit 7
Timer compare force (CFORC)
bit 6
bit 5
bit 4
bit 3
$000B FOC1 FOC2 FOC3 FOC4 FOC5
bit 2
bit 1
bit 0
State
on reset
0
0
0
0000 0000
The CFORC register allows forced early compares. FOC[1:5]
correspond to the five output compares. These bits are set for each
output compare that is to be forced. The action taken as a result of a
forced compare is the same as if there were a match between the OCx
register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their
programmed pin actions to occur at the next timer count transition after
the write to CFORC.
The CFORC bits should not be used on an output compare function that
is programmed to toggle its output on a successful compare because a
normal compare that occurs immediately before or after the force can
result in an undesirable operation.
FOC[1:5] — Force output compares
1 = A forced output compare action will occur on the specified pin.
0 = No action.
Bits [2:0] — Not implemented; always read zero
8.5.3 OC1M — Output compare 1 mask register
Address bit 7
Output compare 1 mask (OC1M) $000C
bit 6
bit 5
bit 4
bit 3
OC1M OC1M OC1M OC1M OC1M
7
6
5
4
3
bit 2
bit 1
bit 0
State
on reset
0
0
0
0000 0000
Use OC1M with OC1 to specify the bits of port A that are affected by a
successful OC1 compare. The bits of the OC1M register correspond to
PA7–PA3.
OC1M[7:3] — Output compare masks for OC1
1 = OC1 is configured to control the corresponding pin of port A.
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Output compare
8.5.4 OC1D — Output compare 1 data register
Address bit 7
Output compare 1 data (OC1D)
bit 6
bit 5
bit 4
bit 3
$000D OC1D7OC1D6OC1D5OC1D4OC1D3
bit 2
bit 1
bit 0
State
on reset
0
0
0
0000 0000
Use this register with OC1 to specify the data that is to be written to the
affected pin of port A after a successful OC1 compare. When a
successful OC1 compare occurs, a data bit in OC1D is written to the
corresponding pin of port A for each bit that is set in OC1M.
OC1D[7:3] — Output compare data for OC1
If OC1Mx is set, data in OC1Dx is output to port A pin x on successful
OC1 compares.
Bits [2:0] — Not implemented; always read zero
8.5.5 TCNT — Timer counter register
Address bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
Timer count (TCNT) high
$000E (bit 15) (14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 0000 0000
Timer count (TCNT) low
$000F (bit 7)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
(6)
bit 0
State
on reset
bit 6
The 16-bit read-only TCNT register contains the prescaled value of the
16-bit timer. A full counter read addresses the more significant byte
(MSB) first. A read of this address causes the less significant byte (LSB)
to be latched into a buffer for the next CPU cycle so that a double-byte
read returns the full 16-bit state of the counter at the time of the MSB
read cycle.
TCNT resets to $0000.
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8.5.6 TCTL1 — Timer control register 1
Address bit 7
Timer control 1 (TCTL1)
$0020
OM2
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OL2
OM3
OL3
OM4
OL4
OM5
OL5 0000 0000
The bits of this register specify the action taken as a result of a
successful OCx compare.
OM[2:5] — Output mode
OL[2:5] — Output level
OMx
0
0
1
1
OLx
0
1
0
1
Action taken on successful compare
Timer disconnected from OCx pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
These control bit pairs are encoded to specify the action taken after a
successful OCx compare. OC5 functions only if the I4/O5 bit in the
PACTL register is clear.
8.5.7 TMSK1 — Timer interrupt mask register 1
Address bit 7
Timer interrupt mask 1 (TMSK1) $0022
OC1I
bit 6
bit 5
bit 4
bit 3
OC2I
OC3I
OC4I I4/O5I
State
on reset
bit 2
bit 1
bit 0
IC1I
IC2I
IC3I 0000 0000
Use this 8-bit register to enable or inhibit the timer input capture and
output compare interrupts.
NOTE:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
OC1I–OC4I — Output compare x interrupt enable
1 = OCx interrupt is enabled.
0 = OCx interrupt is disabled.
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware
interrupt sequence is requested.
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Output compare
I4/O5I — Input capture 4/output compare 5 interrupt enable
1 = IC4/OC5 interrupt is enabled.
0 = IC4/OC5 interrupt is disabled.
When I4/O5 in PACTL is set, I4/O5I is the input capture 4 interrupt
enable bit.
When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt
enable bit.
IC1I–IC3I — Input capture x interrupt enable
1 = ICx interrupt is enabled.
0 = ICx interrupt is disabled.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware
interrupt sequence is requested.
8.5.8 TFLG1 — Timer interrupt flag register 1
Address bit 7
Timer interrupt flag 1 (TFLG1)
bit 6
bit 5
bit 4
bit 3
State
on reset
bit 2
bit 1
bit 0
$0023 OC1F OC2F OC3F OC4F I4/O5F IC1F
IC2F
IC3F 0000 0000
Bits in this register indicate when timer system events have occurred.
Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer
subsystem to operate in either a polled or interrupt driven system. Clear
flags by writing a one to the corresponding bit position(s).
NOTE:
Bits in TFLG1 correspond bit for bit with flag bits in TMSK1. Ones in
TMSK1 enable the corresponding interrupt sources.
OC1F–OC4F — Output compare x flag
1 = Counter has reached the preset output compare x value.
0 = Counter has not reached the preset output compare x value.
These flags are set each time the counter matches the corresponding
output compare x values.
I4/O5F — Input capture 4/output compare 5 flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in
PACTL
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IC1F–IC3F — Input capture x flag
1 = Selected edge has been detected on corresponding port pin.
0 = Selected edge has not been detected on corresponding port
pin.
These flags are set each time a selected active edge is detected on
the ICx input line
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8.5.9 TMSK2 — Timer interrupt mask register 2
Timer interrupt mask 2 (TMSK2)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0024
TOI
RTII
PAOVI
PAII
0
0
PR1
PR0
0000 0000
Use this 8-bit register to enable or inhibit timer overflow and real-time
interrupts. The timer prescaler control bits are included in this register.
NOTE:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOI — Timer overflow interrupt enable
1 = Timer overflow interrupt requested when TOF is set.
0 = TOF interrupts disabled.
RTII — Real-time interrupt enable (refer to Real-time interrupt)
PAOVI — Pulse accumulator overflow interrupt enable (refer to
Pulse accumulator status and interrupt bits)
PAII — Pulse accumulator input edge interrupt enable (refer to
Pulse accumulator status and interrupt bits)
PR[1:0] — Timer prescaler select
PR[1:0]
00
01
10
11
Prescaler
1
4
8
16
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Output compare
These bits are used to select the prescaler divide-by ratio. In normal
modes, PR[1:0] can only be written once, and the write must be within
64 cycles after reset. See Table 8-1 for specific timing values.
8.5.10 TFLG2 — Timer interrupt flag register 2
Address bit 7
Timer interrupt flag 2 (TFLG2)
$0025
TOF
bit 6
bit 5
bit 4
RTIF PAOVF PAIF
bit 3
bit 2
bit 1
bit 0
State
on reset
0
0
0
0
0000 0000
Bits in this register indicate when certain timer system events have
occurred. Coupled with the four high-order bits of TMSK2, the bits of
TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Clear flags by writing a one to the corresponding
bit position(s).
NOTE:
Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOF — Timer overflow interrupt flag
1 = TCNT has overflowed from $FFFF to $0000.
0 = No timer overflow has occurred.
RTIF — Real time (periodic) interrupt flag (refer to Real-time interrupt)
PAOVF — Pulse accumulator overflow interrupt flag (refer to Pulse
accumulator)
PAIF — Pulse accumulator input edge interrupt flag (refer to Pulse
accumulator.)
Bits [3:0] — Not implemented; always read zero
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8.6 Real-time interrupt
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The real-time interrupt (RTI) feature, used to generate hardware
interrupts at a fixed periodic rate, is controlled and configured by two bits
(RTR1 and RTR0) in the pulse accumulator control (PACTL) register.
The RTII bit in the TMSK2 register enables the interrupt capability. The
four different rates available are a product of the MCU oscillator
frequency and the value of bits RTR[1:0]. Refer to Table 8-2, which
shows the periodic real-time interrupt rates.
Table 8-2. RTI periodic rates
RTR[1:0]
E = 3MHz
E = 2MHz
E = 1MHz
E = xMHz
00
01
10
11
2.731ms
5.461ms
10.923ms
21.845ms
4.096ms
8.192ms
16.384ms
32.768ms
8.192ms
16.384ms
32.768ms
65.536ms
213/E
214/E
215/E
216/E
The clock source for the RTI function is a free-running clock that cannot
be stopped or interrupted except by reset. This clock causes the time
between successive RTI timeouts to be a constant that is independent
of the software latency associated with flag clearing and service. For this
reason, an RTI period starts from the previous timeout, not from when
RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set,
an interrupt request is generated. After reset, one entire RTI period
elapses before the RTIF flag is set for the first time. Refer to the TMSK2,
TFLG2, and PACTL registers.
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Real-time interrupt
8.6.1 TMSK2 — Timer interrupt mask register 2
Address bit 7
Timer interrupt mask 2 (TMSK2) $0024
TOI
bit 6
bit 5
bit 4
RTII PAOVI PAII
State
on reset
bit 3
bit 2
bit 1
bit 0
0
0
PR1
PR0 0000 0000
This register contains the real-time interrupt enable bit.
NOTE:
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
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TOI — Timer overflow interrupt enable (refer to TMSK2 — Timer
interrupt mask register 2)
RTII — Real-time interrupt enable
1 = Real time interrupt requested when RTIF is set.
0 = Real time interrupts disabled.
PAOVI — Pulse accumulator overflow interrupt enable (refer to Pulse
accumulator)
PAII — Pulse accumulator input edge (refer to Pulse accumulator)
PR[1:0] — Timer prescaler select (refer to TMSK2 — Timer interrupt
mask register 2)
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8.6.2 TFLG2 — Timer interrupt flag register 2
Address bit 7
Timer interrupt flag 2 (TFLG2)
$0025
TOF
bit 6
bit 5
bit 4
RTIF PAOVF PAIF
bit 3
bit 2
bit 1
bit 0
State
on reset
0
0
0
0
0000 0000
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Bits of this register indicate the occurrence of timer system events.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow
the timer subsystem to operate in either a polled or interrupt driven
system. Clear flags by writing a one to the corresponding bit position(s).
NOTE:
Bits in TFLG2 correspond bit for bit with flag bits in TMSK2. Ones in
TMSK2 enable the corresponding interrupt sources.
TOF — Timer overflow interrupt flag
1 = The timer has overflowed, from $FFFF to $0000.
0 = No timer overflow has occurred.
RTIF — Real-time interrupt flag
1 = RTI period has elapsed.
0 = RTI flag has been cleared.
The RTIF status bit is automatically set to one at the end of every RTI
period.
PAOVF — Pulse accumulator overflow interrupt flag (refer to Pulse
accumulator)
PAIF — Pulse accumulator input edge interrupt flag (refer to Pulse
accumulator)
Bits [3:0] — Not implemented; always read zero
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Computer operating properly watchdog function
8.6.3 PACTL — Pulse accumulator control register
Address bit 7
Pulse accumulator control
(PACTL)
$0026
0
bit 6
bit 5
bit 4
PAEN PAMODPEDGE
bit 3
0
bit 2
bit 1
bit 0
State
on reset
I4/O5 RTR1 RTR0 0000 0000
Bits RTR[1:0] of this register select the rate for the RTI system. The
remaining bits control the pulse accumulator and IC4/OC5 functions.
Bits 7, 3 — Not implemented; always read zero
PAEN — Pulse accumulator system enable (refer to Pulse
accumulator)
PAMOD — Pulse accumulator mode (refer to Pulse accumulator)
PEDGE — Pulse accumulator edge control (refer to Pulse
accumulator)
I4/O5 — Input capture 4/output compare (refer to Pulse
accumulator)
RTR[1:0] — RTI interrupt rate select
These two bits determine the rate at which the RTI system requests
interrupts. The RTI system is driven by an E/213 clock rate that is
compensated so it is independent of the timer prescaler. These two
control bits select an additional division factor. Refer to Table 8-2.
8.7 Computer operating properly watchdog function
The clocking chain for the COP function, tapped off from the main timer
divider chain, is only superficially related to the main timer system. The
CR[1:0] bits in the OPTION register and the NOCOP bit in the CONFIG
register determine the status of the COP function. One additional
register, COPRST, is used to arm and clear the COP watchdog reset
system. Refer to Resets and Interrupts for a more detailed discussion
of the COP function.
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8.8 Pulse accumulator
The MC68HC11P2 has an 8-bit counter that can be configured to
operate either as a simple event counter, or for gated time accumulation,
depending on the state of the PAMOD bit in the PACTL register. Refer
to the pulse accumulator block diagram, Figure 8-3.
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In the event counting mode, the 8-bit counter is clocked to increasing
values by an external pin. The maximum clocking rate for the external
event counting mode is the E clock divided by two. In gated time
accumulation mode, a free-running E clock ÷ 64 signal drives the 8-bit
counter, but only while the external PAI pin is activated. Refer to Table
8-3. The pulse accumulator counter can be read or written at any time.
Table 8-3. Pulse accumulator timing
Crystal
frequency
4.0 MHz
8.0 MHz
12.0 MHz
16.0 MHz
E clock
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
Cycle
time
1000 ns
500 ns
333 ns
250 ns
64/E
64 µs
32 µs
21.33 µs
16.0 µs
Technical Data
PACNT
overflow
16.384 ms
8.192 ms
5.461 ms
4.096 ms
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Pulse accumulator
TOF
RTIF
TFLG2
PAOVF
&
PAIF
0
TOI
0
E/64 clock
(from main timer)
TMSK2
Disable flag setting
0
PAOVI
PAII
1
Interrupt
requests
RTII
0
&
2
0
0
PR1
PR0
&
Overflow
2:1
MUX
PA7/
OC1/
PAI
Clock
Input buffer
and edge detector
PACNT
Enable
RTR0
I4/O5
RTR1
0
PEDGE
PAMOD
From
OC1
PAEN
Output buffer
0
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PACTL
From
DDRA7
Internal data bus
Figure 8-3. Pulse accumulator block diagram
Pulse accumulator control bits are also located within two timer
registers, TMSK2 and TFLG2, as described in the following paragraphs.
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8.8.1 PACTL — Pulse accumulator control register
Address bit 7
Pulse accumulator control
(PACTL)
$0026
0
bit 6
bit 5
bit 4
PAEN PAMODPEDGE
bit 3
0
bit 2
bit 1
bit 0
State
on reset
I4/O5 RTR1 RTR0 0000 0000
Four of this register’s bits control an 8-bit pulse accumulator system.
Another bit enables either the OC5 function or the IC4 function, while two
other bits select the rate for the real-time interrupt system.
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Bits [7, 3] — Not implemented; always read zero
PAEN — Pulse accumulator system enable
1 = Pulse accumulator enabled.
0 = Pulse accumulator disabled.
PAMOD — Pulse accumulator mode
1 = Gated time accumulation mode.
0 = Event counter mode.
PEDGE — Pulse accumulator edge control
This bit has different meanings depending on the state of the PAMOD
bit, as shown:
PAMOD PEDGE
Action of clock
0
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A zero on PAI inhibits counting.
1
1
A one on PAI inhibits counting.
I4/O5 — Input capture 4/output compare 5
1 = Input capture 4 function is enabled (no OC5).
0 = Output compare 5 function is enabled (no IC4).
RTR[1:0] — RTI interrupt rate selects (refer to Real-time interrupt)
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Pulse accumulator
8.8.2 PACNT — Pulse accumulator count register
Address bit 7
Pulse accumulator count
(PACNT)
$0027 (bit 7)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
(6)
(5)
(4)
(3)
(2)
(1)
bit 0
State
on reset
(bit 0) undefined
This 8-bit read/write register contains the count of external input events
at the PAI input, or the accumulated count. In gated time accumulation
mode, PACNT is readable even if PAI is not active. The counter is not
affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading
occur during opposite half cycles.
8.8.3 Pulse accumulator status and interrupt bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF
are located within timer registers TMSK2 and TFLG2.
8.8.3.1 TMSK2 — Timer interrupt mask 2 register
Address bit 7
Timer interrupt mask 2 (TMSK2) $0024
TOI
bit 6
bit 5
bit 4
RTII PAOVI PAII
State
on reset
bit 3
bit 2
bit 1
bit 0
0
0
PR1
PR0 0000 0000
bit 3
bit 2
bit 1
bit 0
State
on reset
0
0
0
0
0000 0000
8.8.3.2 TFLG2 — Timer interrupt flag 2 register
Address bit 7
Timer interrupt flag 2 (TFLG2)
$0025
TOF
bit 6
bit 5
bit 4
RTIF PAOVF PAIF
PAOVI and PAOVF — Pulse accumulator interrupt enable and overflow
flag
The PAOVF status bit is set each time the pulse accumulator count
rolls over from $FF to $00. To clear this status bit, write a one in the
corresponding data bit position (bit 5) of the TFLG2 register. The
PAOVI control bit allows configuring the pulse accumulator overflow
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are inhibited, and the system operates in a polled mode, which
requires that PAOVF be polled by user software to determine when
an overflow has occurred. When the PAOVI control bit is set, a
hardware interrupt request is generated each time PAOVF is set.
Before leaving the interrupt service routine, software must clear
PAOVF by writing to the TFLG2 register.
PAII and PAIF — Pulse accumulator input edge interrupt enable and flag
The PAIF status bit is automatically set each time a selected edge is
detected at the PA7/PAI/OC1 pin. To clear this status bit, write to the
TFLG2 register with a one in the corresponding data bit position (bit
4). The PAII control bit allows configuring the pulse accumulator input
edge detect for polled or interrupt-driven operation but does not affect
setting or clearing the PAIF bit. When PAII is zero, pulse accumulator
input interrupts are inhibited, and the system operates in a polled
mode. In this mode, the PAIF bit must be polled by user software to
determine when an edge has occurred. When the PAII control bit is
set, a hardware interrupt request is generated each time PAIF is set.
Before leaving the interrupt service routine, software must clear PAIF
by writing to the TFLG register.
8.9 Pulse-width modulation (PWM) timer
The PWM timer subsystem provides up to four 8-bit pulse-width
modulated waveforms on the port H pins. Channel pairs can be
concatenated to create 16-bit PWM outputs. Three clock sources (A, B,
and S) and a flexible clock select scheme give the PWM a wide range of
frequencies.
Pin
PH0
PH1
PH2
PH3
Alternate
function
PW1
PW2
PW3
PW4
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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Freescale Semiconductor, Inc.
Timing System
Pulse-width modulation (PWM) timer
for the PWM clock sources and enables the 16-bit PWM functions. The
PWPOL register determines each channel’s polarity and selects the
clock source for each channel. The PWSCAL register derives a userscaled clock based on the A clock source, and the PWEN register
enables the PWM channels.
Each channel also has a separate 8-bit counter, period register, and duty
cycle register. The period and duty cycle registers are double buffered
so that if they are changed while the channel is enabled, the change
does not take effect until the counter rolls over or the channel is disabled.
A new period or duty cycle can be forced into effect immediately by
writing to the period or duty cycle register and then writing to the counter.
With PWMs configured for 8-bit mode and E equal to 4MHz, PWM
signals can be produced from 40 kHz (1% duty cycle resolution) to less
than 10 cycles per second (approximately 0.4% duty cycle resolution).
By configuring the PWMs for 16-bit mode with E equal to 4MHz, PWM
periods greater than one minute are possible.
In 16-bit mode, duty cycle resolution of up to 15 parts per million can be
achieved (at a PWM frequency of 60Hz). In the same system, a PWM
frequency of 1kHz corresponds to a duty cycle resolution of 0.025%.
8.9.1 PWM timer block diagram
Figure 8-4 shows the block diagram of the PWM timer subsystem.
Three different clock sources are selectable and provide inputs to the
control registers. Each of the four channels has a counter, a period
register, and a duty register. The waveform output is the result of a
match between the period register (PWPERx) and the value in the
counter (PWCNTx). The duty register (PWDTYx) changes the state of
the output during the period to determine the duty cycle.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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Timing System
CON34
CNT4
CNT3
PWEN4
PCKB1 PCKB2 PCKB3
Clock B
Clock
select
Prescale select
÷1, 2, 4, 8, 16, 32, 64, 128
reset
PCLK4
÷2
PCLK1
CNT2
CNT1
8-bit counter
Clock S
PCLK3
EQ
8
Divider
PWEN3
Prescale select
÷1, 2, 4, 8
PCKA1
4
PCKA2
8-bit comparator
PWSCAL
MCU
E clock
PCLK2
Clock
select
Clock A
CON12
PWEN1
PWEN2
PWCNT1
PPOL1
PWCNT2
reset
reset
8-bit comparator
PWDTY1
EQ
8-bit comparator
PWPER1
EQ
8-bit comparator
PWDTY2
EQ
8-bit comparator
PWPER2
EQ
S Q
PWCNT3
reset
Bit 0
PH0/
PW1
MUX
Bit 1
PH1/
PW2
PPOL2
PPOL3
Port H
pin
control
MUX
Bit 2
PH2/
PW3
MUX
Bit 3
PH3/
PW4
R Q
S Q
R Q
CON12
reset
MUX
16-bit
PWM
control
carry
PWCNT4
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
8-bit comparator
PWDTY3
EQ
8-bit comparator
PWPER3
EQ
8-bit comparator
PWDTY4
EQ
8-bit comparator
PWPER4
EQ
S Q
R Q
16-bit
PWM
control
S Q
R Q
PPOL4
carry
CON34
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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Timing System
Pulse-width modulation (PWM) timer
8.9.2 PWCLK — PWM clock prescaler and 16-bit select register
Address bit 7
bit 6
bit 5
bit 4
Pulse width clock select (PWCLK) $0060 CON34CON12PCKA2PCKA1
bit 3
0
bit 2
bit 1
bit 0
State
on reset
PCKB3PCKB2PCKB1 0000 0000
This register contains bits for selecting the 16-bit PWM options and for
selecting the prescaler values for the clocks.
Freescale Semiconductor, Inc...
8.9.2.1 16-bit PWM function
The PWCLK register contains two control bits, each of which is used to
concatenate a pair of PWM channels into one 16-bit channel. Channels
3 and 4 are concatenated with the CON34 bit, and channels 1 and 2 are
concatenated with the CON12 bit.
When the 16-bit concatenated mode is selected, the clock source is
determined by the low order channel. Channel 2 is the low order channel
when channels 1 and 2 are concatenated. Channel 4 is the low order
channel when channels 3 and 4 are concatenated. The pins associated
with channels 1 and 3 can be used for general-purpose I/O when 16-bit
PWM mode is selected.
Channel 1 registers are the high order byte of the double-byte channel
when channels 1 and 2 are concatenated. Channel 3 registers are the
high order byte of the double-byte channel when channels 3 and 4 are
concatenated. Reads of the high order byte cause the low order byte to
be latched for one cycle to guarantee that double byte reads are
accurate. Writes to the low byte of the counter cause reset of the entire
counter. Writes to the upper bytes of the counter have no effect.
CON34 — Concatenate channels 3 and 4
1 = Channels 3 and 4 are concatenated into one 16-bit PWM
channel.
0 = Channels 3 and 4 are separate 8-bit PWMs.
When concatenated, channel 3 is the high-order byte and the channel
4 pin (PH3) is the output.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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Timing System
CON12 — Concatenate Channels 1 and 2
1 = Channels 1 and 2 are concatenated into one 16-bit PWM
channel.
0 = Channels 1 and 2 are separate 8-bit PWMs.
When concatenated, channel 1 is the high-order byte and the channel
2 pin (PH1) is the output.
8.9.2.2 Clock prescaler selection
Freescale Semiconductor, Inc...
The three available clocks are clock A, clock B, and clock S (scaled).
Clock A can be software selected to be E, E/2, E/4, or E/8. Clock B can
be software selected to be E, E/2, E/4,..., E/128. The scaled clock (clock
S) uses clock A as an input and divides it with a reloadable counter. The
rates available are software selectable to be clock A/2, down to clock A
/512.
The clock source portion of the block diagram shows the three clock
sources and how the scaled clock is created. Clock A is an input to an 8bit counter which is then compared to a user programmable scale value.
When they match, this circuit has an output that is divided by two and the
counter is reset.
Each PWM timer channel can be driven by one of two clocks. Refer to
Figure 8-4.
PCKA[2:1] — Prescaler for clock A
Determines the frequency of clock A. Refer to Table 8-4.
Bit 3 — Not implemented; always reads zero
PCKB[3:1] — Prescaler for clock B
Determines the frequency of clock B. Refer to Table 8-4.
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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Timing System
Pulse-width modulation (PWM) timer
Table 8-4. Clock A and clock B prescalers
PCKA[2:1]
00
01
10
11
Clock A
E
E/2
E/4
E/8
PCKB[3:1]
000
001
010
011
100
101
110
111
Clock B
E
E/2
E/4
E/8
E/16
E/32
E/64
E/128
8.9.3 PWPOL — PWM timer polarity & clock source select register
Address bit 7
Pulse width polarity select
(PWPOL)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000
PCLK[4:3] — Pulse width channel 4/3 clock select
1 = Clock S is source.
0 = Clock B is source.
PCLK[2:1] — Pulse width channel 2/1 clock select
1 = Clock S is source.
0 = Clock A is source.
PPOL[4:1] — Pulse width channel x polarity
1 = PWM channel x output is high at the beginning of the clock
cycle and goes low when duty count is reached.
0 = PWM channel x output is low at the beginning of the clock cycle
and goes high when duty count is reached.
Each channel has a polarity bit that allows a cycle to start with either
a high or a low level. This is shown on the block diagram, Figure 8-4,
as a selection of either the Q output or the Q output of the PWM output
flip flop. When one of the bits in the PWPOL register is set, the
associated PWM channel output is high at the beginning of the clock
cycle, then goes low when the duty count is reached.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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Timing System
8.9.4 PWSCAL — PWM timer prescaler register
Address bit 7
Pulse width scale (PWSCAL)
$0062 (bit 7)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
(6)
(5)
(4)
(3)
(2)
(1)
bit 0
State
on reset
(bit 0) 0000 0000
Scaled clock S is generated by dividing clock A by the value in PWSCAL,
then dividing the result by two. If PWSCAL = $00, clock A is divided by
256, then divided by two to generate clock S.
8.9.5 PWEN — PWM timer enable register
Address bit 7
Pulse width enable (PWEN)
bit 6
$0063 TPWSL DISCP
bit 5
bit 4
0
0
bit 3
bit 2
bit 1
bit 0
State
on reset
PWEN4PWEN3PWEN2PWEN10000 0000
Each timer has an enable bit to start its waveform output. Writing any of
these PWENx bits to one causes the associated port line to become an
output regardless of the state of the associated DDR bit. This does not
change the state of the DDR bit and when PWENx returns to zero the
DDR bit again controls I/O state. On the front end of the PWM timer the
clock is connected to the PWM circuit by the PWENx enable bit being
high. There is a synchronizing circuit to guarantee that the clock will only
be enabled or disabled at an edge.
PWEN contains 4 PWM enable bits — one for each channel. When an
enable bit is set to one, the pulse modulated signal becomes available
at the associated port pin.
TPWSL — PWM scaled clock test bit (Test mode only)
1 = Clock S output to PWSCAL register (Test only).
0 = Normal operation.
When TPWSL is one, clock S from the PWM timer is output to
PWSCAL register. Normal writing to the PWSCAL register still
functions.
DISCP — Disable compare scaled E clock (Test mode only)
1 = Match of period does not reset associated count register (Test
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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Timing System
Pulse-width modulation (PWM) timer
Bits [5:4] — Not implemented; always read zero
PWEN[4:1] — Pulse width channels 4–1
1 = Channel enabled on the associated port pin.
0 = Channel disabled.
8.9.6 PWCNT1–4 — PWM timer counter registers 1 to 4
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Pulse width count 1 (PWCNT1)
$0064 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 2 (PWCNT2)
$0065 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 3 (PWCNT3)
$0066 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Pulse width count 4 (PWCNT4)
$0067 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Each channel has its own counter which can be read at any time without
affecting the count or the operation of the PWM channel. Writing to a
counter causes it to be reset to $00; this is generally done before the
counter is enabled. A counter may also be written to whilst it is enabled;
this may cause a truncated PWM period.
8.9.7 PWPER1–4 — PWM timer period registers 1 to 4
Address bit 7
bit 0
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Pulse width period 1 (PWPER1) $0068 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width period 2 (PWPER2) $0069 (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width period 3 (PWPER3) $006A (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width period 4 (PWPER4) $006B (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
There is one period register for each channel. The value in this register
determines the period of the associated PWM timer channel. PWPERx
is connected internally to a buffer which compares directly with the
counter register. The period value in PWPERx is loaded into the buffer
when the counter is cleared by the termination of the previous period or
by a write to the counter. This register can be written at any time, and the
written value will take effect from the start of the next PWM timer cycle.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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Timing System
8.9.8 PWDTY1–4 — PWM timer duty cycle registers 1 to 4
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Pulse width duty 1 (PWDTY1)
$006C (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 2 (PWDTY2)
$006D (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 3 (PWDTY3)
$006E (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Pulse width duty 4 (PWDTY4)
$006F (bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Freescale Semiconductor, Inc...
There is one duty register for each channel. The value in this register
determines the duty cycle of the associated PWM timer channel.
PWDTYx is compared to the counter contents and if they are equal, a
match occurs and the output goes to the state defined by the associated
polarity bit. If the register is written while the channel is enabled, then the
new value is held in a buffer until the counter rolls over or the channel is
disabled. Reads of this register return the most recent value written.
NOTE:
If PWDTYx Š PWPERx then there will be no change of state due to the
duty cycle value. In addition, if the duty register is set to $00, then the
output will always be in the state which would normally be result from the
duty change of state (see also Boundary cases).
PWMx
PWDTYx
PWPERx
Figure 8-5. PWM duty cycle
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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Timing System
Pulse-width modulation (PWM) timer
8.9.9 Boundary cases
Freescale Semiconductor, Inc...
The following boundary conditions apply to the values stored in the
PWDTYx and PWPERx registers and the PPOLx bits:
•
If PWDTYx = $00, PWPERx > $00 and PPOLx = 0 then the output
is always high.
•
If PWDTYx = $00, PWPERx > $00 and PPOLx = 1 then the output
is always low.
•
If PWDTYx Š PWPERx and PPOLx = 0 then the output is always
low.
•
If PWDTYx Š PWPERx and PPOLx = 1 then the output is always
high.
•
If PWPERx = $00 and PPOLx = 0 then the output is always low.
•
If PWPERx = $00 and PPOLx = 1 then the output is always high.
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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Timing System
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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Technical Data — MC68HC11P2
Section 9. Analog-to-Digital Converter
9.1 Contents
9.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
9.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
9.4
A/D converter power-up and clock select . . . . . . . . . . . . . 178
9.5
Channel assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
9.6
Control, status and results registers . . . . . . . . . . . . . . . . . 181
9.7
Operation in STOP and WAIT modes . . . . . . . . . . . . . . . . . 184
9.2 Introduction
The analog-to-digital (A/D) system, a successive approximation
converter, uses an all-capacitive charge redistribution technique to
convert analog signals to digital values.
The A/D converter shares input pins with port E:
Pin
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Alternate
function
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
MC68HC11P2 — Rev 1.0
Technical Data
Analog-to-Digital Converter
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Analog-to-Digital Converter
9.3 Overview
The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The
VDD AD and VSS AD pins are used to input supply voltage to the A/D
converter. This allows the supply voltage to be bypassed independently.
The converter does not require external sample and hold circuits
because of the type of charge redistribution technique used. A/D
converter timing can be synchronized to the system E clock, or to an
internal resistor capacitor (RC) oscillator. The A/D converter system
consists of four functional blocks: multiplexer, analog converter, digital
control and result storage. Refer to Figure 9-1.
PE0/
AD0
VRH
VRL
8-bit capacitive DAC
with sample and hold
PE1/
AD1
Successive approximation
register and control
PE2/
AD2
PE3/
AD3
PE4/
AD4
Result
Internal
data bus
Analog
MUX
CCF
PE5/
AD5
0
SCAN
MULT
PE6/
AD6
CD
CC
CB
PE7/
AD7
CA
ADCTL – A/D control
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Result register interface
ADR1 - A/D result 1
ADR2 - A/D result 2
ADR3 - A/D result 3
Technical Data
ADR4 - A/D result 4
MC68HC11P2 — Rev 1.0
Analog-to-Digital Converter
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Analog-to-Digital Converter
Overview
9.3.1 Multiplexer
The multiplexer selects one of 16 inputs for conversion. Input selection
is controlled by the value of bits CD – CA in the ADCTL register. The
eight port E pins are fixed-direction analog inputs to the multiplexer, and
additional internal analog signal lines are routed to it.
Freescale Semiconductor, Inc...
Port E pins can also be used as digital inputs. Digital reads of port E pins
are not recommended during the sample portion of an A/D conversion
cycle, when the gate signal to the N-channel input gate is on. Because
no P-channel devices are directly connected to either input pins or
reference voltage pins, voltages above VDD do not cause a latchup
problem, although current should be limited according to maximum
ratings. Refer to Figure 9-2, which is a functional diagram of an input
pin.
Input
protection
device
Analog
input
Diffusion and
poly coupler
ð4k¾
Note 1
zero
Branch if higher
Branch if higher or same
Bit(s) test A with memory
C=1?
Z=1?
N⊕V=0?
Z + (N ⊕ V) = 0 ?
C+Z=0?
C=0?
A•M
BITB (opr)
Bit(s) test B with memory
B•M
BLE (rel)
BLO (rel)
BLS (rel)
BLT (rel)
BMI (rel)
BNE (rel)
Branch if ð zero
Branch if lower
Branch if lower or same
Branch if < zero
Branch if minus
Branch if ¦ zero
Z + (N ⊕ V) = 1 ?
C=1?
C+Z=1?
N⊕V=1?
N=1?
Z=0?
A
A
A
A
A
B
B
B
B
B
EXT
IND, X
IND, Y
INH
INH
REL
DIR
IND, X
IND, Y
REL
REL
REL
REL
REL
REL
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
REL
REL
REL
REL
REL
REL
77
67
18 67
47
57
24
15
1D
18 1D
25
27
2C
2E
22
24
85
95
B5
A5
18 A5
C5
D5
F5
E5
18 E5
2F
25
23
2D
2B
26
hh ll
ff
ff
—
—
rr
dd mm
ff mm
ff mm
rr
rr
rr
rr
rr
rr
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
rr
rr
rr
rr
rr
Technical Data
6
6
7
2
2
3
6
7
8
3
3
3
3
3
3
2
3
4
4
5
2
3
4
4
5
3
3
3
3
3
3
— — — — ∅ ∅ ∅ ∅
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
∅
—
∅
∅
∅
—
∅
∅
∅
—
0
∅
∅
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
—
—
—
—
—
—
∅
—
—
—
—
—
—
0
—
—
—
—
—
—
—
— — — — ∅ ∅ 0 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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CPU Core and Instruction Set
Instruction set
Table 11-2. Instruction set (Sheet 3 of 8)
Mnemonic
Operation
Description
BRCLR(opr)
(msk)
(rel)
BRN (rel)
BRSET(opr)
(msk)
(rel)
BSET (opr)
(msk)
Branch if bit(s) clear
M • mm = 0 ?
Branch never
Branch if bit(s) set
1=0?
M • mm = 0 ?
Set bit(s)
M + mm ⇒ M
BSR (rel)
BVC (rel)
BVS (rel)
CBA
CLC
CLI
CLR (opr)
Branch to subroutine
Branch if overflow clear
Branch if overflow set
Compare A with B
Clear carry bit
Clear interrupt mask
Clear memory byte
see Figure 11-2
V=0?
V=1?
A–B
0⇒C
0⇒I
0⇒M
CLRA
CLRB
CLV
CMPA (opr)
Clear accumulator A
Clear accumulator B
Clear overflow flag
Compare A with memory
0⇒A
0⇒B
0⇒V
A–M
CMPB (opr)
Compare B with memory
B–M
COM (opr)
Ones complement memory byte
$FF – M ⇒ M
COMA
COMB
CPD (opr)
Ones complement A
Ones complement B
Compare D with memory (16-bit)
$FF – A ⇒ A
$FF – B ⇒ B
D – (M:M+1)
Addressing
mode
A
B
A
A
A
A
A
B
B
B
B
B
A
B
DIR
IND, X
IND, Y
REL
DIR
IND, X
IND, Y
DIR
IND, X
IND, Y
REL
REL
REL
INH
INH
INH
DIR
IND, X
IND, Y
INH
INH
INH
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
EXT
IND, X
IND, Y
INH
INH
IMM
DIR
EXT
IND, X
IND, Y
Opcode
13
1F
18 1F
21
12
1E
18 1E
14
1C
18 1C
8D
28
29
11
0C
0E
7F
6F
18 6F
4F
5F
0A
81
91
B1
A1
18 A1
C1
D1
F1
E1
18 E1
73
63
18 63
43
53
1A 83
1A 93
1A B3
1A A3
CDA3
Instruction
Operand Cycles
dd mm rr
6
ff mm rr
7
ff mm rr
8
rr
3
dd mm rr
6
ff mm rr
7
ff mm rr
8
dd mm
6
ff mm
7
ff mm
8
rr
6
rr
3
rr
3
—
2
—
2
—
2
hh ll
6
ff
6
ff
7
—
2
—
2
—
2
ii
2
dd
3
hh ll
4
ff
4
ff
5
ii
2
dd
3
hh ll
4
ff
4
ff
5
hh ll
6
ff
6
ff
7
—
2
—
2
jj kk
5
dd
6
hh ll
7
ff
7
ff
7
MC68HC11P2 — Rev 1.0
Condition codes
S X H I N Z V C
— — — — — — — —
— — — — — — — —
— — — — — — — —
— — — — ∅ ∅ 0 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
∅
—
—
0
—
—
—
∅
—
—
1
—
—
—
∅
—
—
0
—
—
—
∅
0
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
—
∅
1
1
—
∅
0
0
0
∅
0
0
—
∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ 0 1
— — — — ∅ ∅ 0 1
— — — — ∅ ∅ 0 1
— — — — ∅ ∅ ∅ ∅
Technical Data
CPU Core and Instruction Set
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Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Table 11-2. Instruction set (Sheet 4 of 8)
Mnemonic
Operation
Description
CPX (opr)
Compare IX with memory (16bit)
IX – (M:M+1)
CPY (opr)
Compare IY with memory (16bit)
IY – (M:M+1)
DAA
DEC (opr)
Decimal adjust A
Decrement memory byte
adjust sum to BCD
M–1⇒M
DECA
DECB
DES
DEX
DEY
EORA (opr)
Decrement accumulator A
Decrement accumulator B
Decrement stack pointer
Decrement index register X
Decrement index register Y
Exclusive OR A with memory
A–1⇒A
B–1⇒B
SP – 1 ⇒ SP
IX – 1 ⇒ IX
IY – 1 ⇒ IY
A⊕M⇒A
EORB (opr)
Exclusive OR B with memory
B⊕M⇒A
FDIV
IDIV
INC (opr)
Fractional divide, 16 by 16
Integer divide, 16 by 16
Increment memory byte
D / IX ⇒ IX; r ⇒ D
D / IX ⇒ IX; r ⇒ D
M+1⇒M
INCA
INCB
INS
INX
INY
JMP (opr)
Increment accumulator A
Increment accumulator B
Increment stack pointer
Increment index register X
Increment index register Y
Jump
A+1⇒A
B+1⇒B
SP + 1 ⇒ SP
IX + 1 ⇒ IX
IY + 1 ⇒ IY
see Figure 11-2
JSR (opr)
Jump to subroutine
see Figure 11-2
Addressing
mode
A
B
A
A
A
A
A
B
B
B
B
B
A
B
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
INH
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
INH
INH
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
EXT
IND, X
IND, Y
DIR
Opcode
8C
9C
BC
AC
CDAC
18 8C
18 9C
18 BC
1A AC
18 AC
19
7A
6A
18 6A
4A
5A
34
09
18 09
88
98
B8
A8
18 A8
C8
D8
F8
E8
18 E8
03
02
7C
6C
18 6C
4C
5C
31
08
18 08
7E
6E
18 6E
9D
Instruction
Operand Cycles
jj kk
4
dd
5
hh ll
6
ff
6
ff
7
jj kk
5
dd
6
hh ll
7
ff
7
ff
7
—
2
hh ll
6
ff
6
ff
7
—
2
—
2
—
3
—
3
—
4
ii
2
dd
3
hh ll
4
ff
4
ff
5
ii
2
dd
3
hh ll
4
ff
4
ff
5
—
41
—
41
hh ll
6
ff
6
ff
7
—
2
—
2
—
3
—
3
—
4
hh ll
3
ff
3
ff
4
dd
5
Technical Data
Condition codes
S X H I N Z V C
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ? ∅
— — — — ∅ ∅ ∅ —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
∅
—
—
—
∅
∅
∅
—
∅
∅
∅
∅
∅
—
—
—
0
—
—
—
—
—
—
— — — — ∅ ∅ 0 —
— — — — — ∅ ∅ ∅
— — — — — ∅ 0 ∅
— — — — ∅ ∅ ∅ —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
∅
—
—
—
—
∅
∅
—
∅
∅
—
∅
∅
—
—
—
—
—
—
—
—
—
—
— — — — — — — —
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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CPU Core and Instruction Set
Instruction set
Table 11-2. Instruction set (Sheet 5 of 8)
Addressing
mode
Mnemonic
Operation
Description
LDAA (opr)
Load accumulator A
M⇒A
LDAB (opr)
Load accumulator B
M⇒B
LDD (opr)
Load double accumulator D
M ⇒ A; M+1 ⇒ B
LDS (opr)
Load stack pointer
M:M+1 ⇒ SP
LDX (opr)
Load index register X
M:M+1 ⇒ IX
LDY (opr)
Load index register Y
M:M+1 ⇒ IY
LSL (opr)
Logical shift left
LSLA
LSLB
LSLD
Logical shift left A
Logical shift left B
Logical shift left D
0
LSR (opr)
b0
0
C
b15
0
LSRA
LSRB
LSRD
Logical shift right A
Logical shift right B
Logical shift right D
C
b0
0
C
b15
74
64
18 64
44
54
04
Instruction
Operand Cycles
ii
2
dd
3
hh ll
4
ff
4
ff
5
ii
2
dd
3
hh ll
4
ff
4
ff
5
jj kk
3
dd
4
hh ll
5
ff
5
ff
6
jj kk
3
dd
4
hh ll
5
ff
5
ff
6
jj kk
3
dd
4
hh ll
5
ff
5
ff
6
jj kk
4
dd
5
hh ll
6
ff
6
ff
6
hh ll
6
ff
6
ff
7
—
2
—
2
—
3
Condition codes
S X H I N Z V C
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
b0
Logical shift right
b7
EXT
IND, X
IND, Y
A INH
B INH
INH
A
A
A
A
A
B
B
B
B
B
C
b7
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
EXT
IND, X
IND, Y
A INH
B INH
INH
Opcode
86
96
B6
A6
18 A6
C6
D6
F6
E6
18 E6
CC
DC
FC
EC
18 EC
8E
9E
BE
AE
18 AE
CE
DE
FE
EE
CDEE
18 CE
18 DE
18 FE
1A EE
18 EE
78
68
18 68
48
58
05
hh ll
ff
ff
—
—
—
6
6
7
2
2
3
— — — — 0 ∅ ∅ ∅
— — — — 0 ∅ ∅ ∅
— — — — 0 ∅ ∅ ∅
— — — — 0 ∅ ∅ ∅
b0
MC68HC11P2 — Rev 1.0
Technical Data
CPU Core and Instruction Set
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CPU Core and Instruction Set
Table 11-2. Instruction set (Sheet 6 of 8)
Mnemonic
Operation
Description
NEG (opr)
Twos complement memory byte
0–M⇒M
NEGA
NEGB
NOP
ORAA
Twos complement A
Twos complement B
No operation
OR accumulator A (inclusive)
0–A⇒A
0–B⇒B
no operation
A+M⇒A
ORAB
OR accumulator B (inclusive)
PSHA
PSHB
PSHX
PSHY
PULA
PULB
PULX
PULY
ROL (opr)
Push A onto stack
Push B onto stack
Push IX onto stack (low first)
Push IY onto stack (low first)
Pull A from stack
Pull B from stack
Pull IX from stack (high first)
Pull IY from stack (high first)
Rotate left
Addressing
mode
A
B
A
A
A
A
A
B+M⇒B
B
B
B
B
B
A ⇒ Stack; SP = SP–1 A
B ⇒ Stack; SP = SP–1 B
IX ⇒ Stack; SP = SP–2
IY ⇒ Stack; SP = SP–2
SP = SP+1; Stack ⇒ A A
SP = SP+1; Stack ⇒ B B
SP = SP+2; Stack ⇒ IX
SP = SP+2; Stack ⇒ IY
C
b7
ROLA
ROLB
ROR (opr)
b0
Rotate left A
Rotate left B
Rotate right
A
B
C
b7
RORA
RORB
RTI
RTS
SBA
SBCA (opr)
Rotate right A
Rotate right B
Return from interrupt
Return from subroutine
Subtract B from A
Subtract with carry from A
b0
A
B
see Figure 11-2
see Figure 11-2
A–B⇒A
A–M–C⇒A
A
A
A
A
A
EXT
IND, X
IND, Y
INH
INH
INH
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
INH
INH
INH
EXT
IND, X
IND, Y
INH
INH
EXT
IND, X
IND, Y
INH
INH
INH
INH
INH
IMM
DIR
EXT
IND, X
IND, Y
Opcode
70
60
18 60
40
50
01
8A
9A
BA
AA
18 AA
CA
DA
FA
EA
18 EA
36
37
3C
18 3C
32
33
38
18 38
79
69
18 69
49
59
76
66
18 66
46
56
3B
39
10
82
92
B2
A2
18 A2
Instruction
Operand Cycles
hh ll
6
ff
6
ff
7
—
2
—
2
—
2
ii
2
dd
3
hh ll
4
ff
4
ff
5
ii
2
dd
3
hh ll
4
ff
4
ff
5
—
3
—
3
—
4
—
5
—
4
—
4
—
5
—
6
hh ll
6
ff
6
ff
7
—
2
—
2
hh ll
6
ff
6
ff
7
—
2
—
2
—
12
—
5
—
2
ii
2
dd
3
hh ll
4
ff
4
ff
5
Technical Data
Condition codes
S X H I N Z V C
— — — — ∅ ∅ ∅ ∅
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
∅
—
∅
∅
∅
—
∅
∅
∅
—
0
∅
∅
—
—
— — — — ∅ ∅ 0 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
—
—
—
—
—
—
—
—
∅
—
—
—
—
—
—
—
—
∅
—
—
—
—
—
—
—
—
∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
—
—
∅
—
—
—
—
—
↓
—
—
—
—
—
∅
—
—
—
—
—
∅
—
—
—
∅
∅
∅
—
∅
∅
∅
∅
∅
—
∅
∅
∅
∅
∅
—
∅
∅
∅
∅
∅
—
∅
∅
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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CPU Core and Instruction Set
Instruction set
Table 11-2. Instruction set (Sheet 7 of 8)
Mnemonic
Operation
Description
SBCB (opr)
Subtract with carry from B
B–M–C⇒B
SEC
SEI
SEV
STAA (opr)
Set carry
Set interrupt mask
Set overflow flag
Store accumulator A
1⇒C
1⇒I
1⇒V
A⇒M
STAB (opr)
Store accumulator B
B⇒M
STD (opr)
Store accumulator D
A ⇒ M; B ⇒ M+1
STOP
STS (opr)
Stop internal clocks
Store stack pointer
—
SP ⇒ M:M+1
STX (opr)
Store index register X
IX ⇒ M:M+1
STY (opr)
Store index register Y
IY ⇒ M:M+1
SUBA (opr)
Subtract memory from A
A–M⇒A
SUBB (opr)
Subtract memory from B
B–M⇒B
SUBD (opr)
Subtract memory from D
D – M:M+1 ⇒ D
Addressing
mode
B
B
B
B
B
A
A
A
A
B
B
B
B
A
A
A
A
A
B
B
B
B
B
IMM
DIR
EXT
IND, X
IND, Y
INH
INH
INH
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
INH
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
EXT
IND, X
IND, Y
IMM
DIR
Opcode
C2
D2
F2
E2
18 E2
0D
0F
0B
97
B7
A7
18 A7
D7
F7
E7
18 E7
DD
FD
ED
18 ED
CF
9F
BF
AF
18 AF
DF
FF
EF
CDEF
18 DF
18 FF
1A EF
18 EF
80
90
B0
A0
18 A0
C0
D0
F0
E0
18 E0
83
93
Instruction
Operand Cycles
ii
2
dd
3
hh ll
4
ff
4
ff
5
—
2
—
2
—
2
dd
3
hh ll
4
ff
4
ff
5
dd
3
hh ll
4
ff
4
ff
5
dd
4
hh ll
5
ff
5
ff
6
—
2
dd
4
hh ll
5
ff
5
ff
6
dd
4
hh ll
5
ff
5
ff
6
dd
5
hh ll
6
ff
6
ff
6
ii
2
dd
3
hh ll
4
ff
4
ff
5
ii
2
dd
3
hh ll
4
ff
4
ff
5
jj kk
4
dd
5
MC68HC11P2 — Rev 1.0
Condition codes
S X H I N Z V C
— — — — ∅ ∅ ∅ ∅
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
∅
—
—
—
∅
—
—
1
0
1
—
—
—
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — — — — —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ 0 —
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
— — — — ∅ ∅ ∅ ∅
Technical Data
CPU Core and Instruction Set
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Freescale Semiconductor, Inc.
CPU Core and Instruction Set
Table 11-2. Instruction set (Sheet 8 of 8)
Mnemonic
Operation
Description
SWI
TAB
TAP
TBA
TEST
TPA
TST (opr)
Software interrupt
Transfer A to B
Transfer A to CC register
Transfer B to A
Test (only in test modes)
Transfer CC register to A
Test for zero or minus
see Figure 11-2
A⇒B
A ⇒ CCR
B⇒A
address bus increments
CCR ⇒ A
M–0
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
Test A for zero or minus
Test B for zero or minus
Transfer stack pointer to X
Transfer stack pointer to Y
Transfer X to stack pointer
Transfer Y to stack pointer
Wait for interrupt
Exchange D with X
Exchange D with Y
A–0
B–0
SP + 1 ⇒ IX
SP + 1 ⇒ IY
IX – 1 ⇒ SP
IY – 1 ⇒ SP
stack registers & WAIT
IX ⇒ D; D ⇒ IX
IY ⇒ D; D ⇒ IY
Operators
⇒ Is transferred to
• Boolean AND
+ Arithmetic addition, except where used as an
inclusive-OR symbol in Boolean formulae
⊕ Exclusive-OR
* Multiply
: Concatenation
– Arithmetic subtraction, or negation symbol
(Twos complement)
Cycles
† Infinite, or until reset occurs
‡ 12 cycles are used, beginning with the opcode
fetch. A wait state is entered, which remains
in effect for an integer number of MPU E clock
cycles (n) until an interrupt is recognized.
Finally, two additional cycles are used to fetch
the appropriate interrupt vector. (14 + n, total).
Addressing
mode
INH
INH
INH
INH
INH
INH
EXT
IND, X
IND, Y
A INH
B INH
INH
INH
INH
INH
INH
INH
INH
Opcode
3F
16
06
17
00
07
7D
6D
18 6D
4D
5D
30
18 30
35
18 35
3E
8F
18 8F
Instruction
Operand Cycles
—
14
—
2
—
2
—
2
—
†
—
2
hh ll
6
ff
6
ff
7
—
2
—
2
—
3
—
4
—
3
—
4
—
‡
—
3
—
4
S
—
—
∅
—
—
—
—
Condition codes
X H I N Z V
— — 1 — — —
— — — ∅ ∅ 0
↓ ∅ ∅ ∅ ∅ ∅
— — — ∅ ∅ 0
— — — — — —
— — — — — —
— — — ∅ ∅ 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∅
∅
—
—
—
—
—
—
—
∅
∅
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
C
—
—
∅
—
—
—
0
0
0
—
—
—
—
—
—
—
Operands
dd 8-bit direct address ($0000–$00FF); the high byte is assumed
to be zero
ff
8-bit positive offset ($00 to $FF (0 to 256)) is added to the
contents of the index register
hh High order byte of 16-bit extended address
ii
One byte of immediate data
jj
High order byte of 16-bit immediate data
kk Low order byte of 16-bit immediate data
ll
Low order byte of 16-bit extended address
mm 8-bit mask (set bits to be affected)
rr Signed relative offset ($80 to $7F (–128 to +127));
offset is relative to the address following the offset byte
Condition Codes
— Bit not changed
0
Bit always cleared
1
Bit always set
∅ Bit set or cleared, depending on the operation
↓ Bit can be cleared, but cannot become set
?
Not defined
Technical Data
MC68HC11P2 — Rev 1.0
CPU Core and Instruction Set
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Technical Data — MC68HC11P2
Section 12. Electrical Specifications
12.1 Contents
12.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
12.4
Thermal characteristics and power considerations . . . . .233
12.5
Test methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.6
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 235
12.7
Control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
12.2 Introduction
This section contains the electrical specifications and associated timing
information for the standard supply voltage (VDD = 5V ± 10%)
MC68HC11P2 variants.
MC68HC11P2 — Rev 1.0
Technical Data
Electrical Specifications
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Electrical Specifications
12.3 Maximum ratings
Rating
Symbol
VDD
Value
Unit
– 0.3 to +7.0
V
Input voltage (1)
Vin
– 0.3 to +7.0
V
Operating temperature range
– MC68HC11P2, MC68HC711P2
TA
TL to TH
–40 to +85
°C
Storage temperature range
Tstg
– 55 to +150
°C
Current drain per pin (2)
– not VDD, VSS, VDD AD, VSS AD,
VRH or VRL
ID
25
mA
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Supply voltage
(1)
1. All voltages are with respect to VSS.
2. Maximum current drain per pin is for one pin at a time, observing maximum
power dissipation limits.
NOTE:
This device contains circuitry designed to protect against damage due to
high electrostatic voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid the application of any voltages
higher than those given in the maximum ratings table to this high
impedance circuit. For maximum reliability all unused inputs should be
tied to either VSS or VDD.
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Electrical Specifications
Thermal characteristics and power considerations
12.4 Thermal characteristics and power considerations
The average chip junction temperature, TJ, in degrees Celsius can be
obtained from the following equation:
T J = T A + ( PD • θ JA )
[1]
where:
TA = Ambient temperature (°C)
Freescale Semiconductor, Inc...
θJA = Package thermal resistance, junction-to-ambient (°C/W)
PD = Total power dissipation = PINT + PI/O (W)
PINT = Internal chip power = IDD • VDD (W)
PI/O = Power dissipation on input and output pins (User determined)
An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = --------------------T J + 273
[2]
Solving equations [1] and [2] for K gives:
K = P D • ( T A + 273 ) + θJA • P D2
[3]
where K is a constant for a particular part. K can be determined by
measuring PD (at equilibrium) for a known TA. Using this value of K, the
values of PD and TJ can be obtained for any value of TA, by solving the
above equations. The package thermal characteristics are shown
below:
Characteristics
Thermal resistance
– 84-pin PLCC package
– 84-pin CERQUAD package (EPROM)
– 88-pin QFP package
Symbol
θJA
MC68HC11P2 — Rev 1.0
Value
Unit
°C/W
50
50
TBD
Technical Data
Electrical Specifications
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Electrical Specifications
12.5 Test methods
VDD
R2
Test
Point
R1
R2
C
3.26k¾
2.38k¾
90pF
PD[4:1]
3.26k¾
2.38k¾
200pF
Freescale Semiconductor, Inc...
Pins
PA[7:0], PB[7:0], PC[7:0],
PD5, PD0, E, R/W, AS
C
R1
(a) Equivalent test loads
Clocks,
strobes
~VDD
0.4V
0.4V
~VSS
VDD – 0.8V
nominal
nominal
70% of VDD
Inputs
20% of VDD
nominal timing
~VDD
VDD – 0.8V
0.4V
Outputs
~VSS
(b) DC testing
Clocks,
strobes
~VDD
20% of VDD
~VSS
20% of VDD
70% of VDD
spec.
Inputs
20% of VDD
spec.
70% of VDD
VDD – 0.8V (2)
0.4V (2)
spec. timing
~VDD
70% of VDD
20% of VDD
Outputs
~VSS
(c) AC testing
Notes:
(1) Full test loads are applied during all DC electrical tests and AC timing measurements.
(2) During AC timing measurements, inputs are driven to 0.4V and VDD – 0.8V;
timing measurements are taken at the 20% and 70% of V DD points.
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Electrical Specifications
DC electrical characteristics
12.6 DC electrical characteristics
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted)
Characteristic
Symbol
Min.
Max.
voltage(1)
Output
(ILOAD = ± 10 µA):
All outputs except XTAL
All outputs except XTAL, RESET & MODA
Output high voltage(1) (ILOAD = –0.8mA, VDD =4.5V):
All outputs except XTAL, RESET & MODA
Output low voltage (ILOAD = +1.6mA):
All outputs except XTAL
Input high voltage:
All inputs except RESET
RESET
Input low voltage – all inputs
I/O ports tristate leakage (VIN = VIH or VIL):
Ports A, B, C, D, F, G, H, MODA/LIR, RESET
Input leakage(2) (VIN = VDD or VSS):
IRQ, XIRQ (ROM parts)
MODB/VSTBY, XIRQ (EPROM parts)
Input current with pull-up resistors (VIN = VIL):
Ports B, F, G, H
RAM stand-by voltage (power down)
RAM stand-by current (power down)
Input capacitance:
Port E, IRQ, XIRQ, EXTAL
Ports A, B, C, D, F, G, H, MODA/LIR, RESET
Output load capacitance:
All outputs except PD[4:1], XTAL, MODA/LIR
PD[4:1]
Unit
VOL
VOH
—
VDD – 0.1
0.1
—
V
V
VOH
VDD – 0.8
—
V
VOL
—
0.4
V
VIL
0.7VDD
0.8VDD
VSS – 0.3
VDD + 0.3
VDD + 0.3
0.2VDD
V
IOZ
—
±10
µA
—
—
±1
±10
IIPR
100
500
µA
VSB
ISB
CIN
2.0
—
VDD
V
µA
pF
—
—
8
12
—
—
90
200
VIH
V
IIN
µA
10
CL
pF
1. VOH specification for RESET and MODA is not applicable as they are open-drain pins.
VOH specification is not applicable to ports C and D in wired-OR mode.
2. Refer to A/D specification for the leakage current value for port E.
MC68HC11P2 — Rev 1.0
Technical Data
Electrical Specifications
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Electrical Specifications
Characteristic
Symbol
(1)
Maximum total supply current (including PLL) :
RUN: Single chip mode
RUN: Expanded mode
WAIT: Single chip mode(2)
WAIT: Expanded mode(2)
STOP: Single chip mode
Power dissipation: Single chip mode
Power dissipation: Expanded mode
2MHz
3MHz
4MHz
Unit
27
35
10
12
50
32
42
15
17
50
40
50
20
22
50
mA
mA
mA
mA
µA
149
193
176
231
220
275
mW
IDD
PD
1. All current measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs.
EXTAL is driven with a square wave, with tCYC = 500/333/250ns for 2/3/4MHz devices.
VIL 0.2V; VIH ≥ VDD – 0.2V; no DC loads
WAIT: all peripheral functions shut down
STOP: all clocks stopped
2. If the PLL low-power WAIT mode is selected (WEN = 1) then, with an external clock of 614kHz, the supply current will not
exceed 1mA in single chip mode, or 2mA in expanded mode.
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Electrical Specifications
Control timing
12.7 Control timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Characteristic (1)
Symbol
2.0MHz
Min.
Max.
3.0MHz
Min. Max.
4.0MHz
Unit
Min.
Max.
Frequency of operation
fOP
0
2.0
0
3.0
0
4.0
MHz
E clock period
tCYC
500
—
333
—
250
—
ns
Crystal frequency
fXTAL
—
8.0
—
12.0
—
16.0
MHz
External oscillator frequency
4fOP
0
8.0
0
12.0
0
16.0
MHz
Processor control set-up time (tPCSU = tCYC/4 + 50ns)
tPCSU
175
—
133
—
112
—
ns
PWRSTL(3)
PWRSTL(4)
8
1
2
—
—
—
8
1
2
—
—
—
8
1
2
—
—
—
10
tCYC +20
—
ns
—
10
tCYC +20
—
—
10
tCYC +20
—
PWIRQ
—
ns
PWTIM
tCYC +20
—
tCYC +20
—
tCYC +20
—
ns
WAIT recovery start-up time
tWRS
—
4
—
4
—
4
tCYC
Clock monitor reset
fCMON
10
200
10
200
10
200
kHz
PLL crystal frequency
fXTAL
—
2.0
—
2.0
—
2.0
MHz
PLL stabilization time
tPLLS
—
TBD
—
TBD
—
TBD
ms
Reset input pulse width (2)
Mode programming set-up time
tMPS
Mode programming hold time
tMPH
Interrupt pulse width (IRQ edge sensitive mode)
Timer pulse width
(Input capture and pulse accumulator inputs)
tCYC
tCYC
1. All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin and samples the pin level two cycles later to determine the source of the interrupt. (See Resets and Interrupts.)
3. To guarantee an external reset vector.
4. This is the minimum input time; it can be pre-empted by an internal reset.
PA[3:0](1)
PWTIM
PA[3:0]
(2)
PA7(1), (3)
PA7(2), (3)
Notes
(1) Rising edge sensitive input.
(2) Falling edge sensitive input.
(3) Maximum pulse accumulator clocking rate is E clock frequency divided by two (E/2).
MC68HC11P2 — Rev 1.0
Technical Data
Electrical Specifications
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Electrical Specifications
VDD
EXTAL
4064 tCYC
E
tPCSU
PWRSTL
RESET
tMPS
tMPH
MODA,
MODB
FFFE FFFE FFFE FFFE FFFF
Address
New
PC
FFFE FFFE FFFE FFFE FFFE FFFF
New
PC
Figure 12-3. Reset timing
E clock
tPCSU
IRQ(1)
IRQ(2), XIRQ
or internal
interrupt
Address(3)
Data(4)
PWIRQ
OA
OP
OA+1
SP
––
PCL
SP–1 SP–2 SP–3
PCH
IYL
IYH
SP–4 SP–5 SP–6 SP–7 SP–8 SP–8
IXL
IXH
B
A
CCR
––
VA
VA+1
New
PC
VH
VL
OP
R/W
Notes:
(1) Edge sensitive IRQ pin (IRQE = 1).
(2) Level sensitive IRQ pin (IRQE = 0).
(3) Where OA = Opcode address and VA = Vector address.
(4) Where OP = Opcode, VH = Vector (MSB) and VL = Vector (LSB).
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Electrical Specifications
Control timing
Internal
clocks
IRQ(1)
PWIRQ
IRQ(2)
or XIRQ
tSTOPDELAY(3)
E clock
Address(4)
SA(6)
SA+1
SA+1
Opcode
Resume program with instruction which follows the STOP instruction
Address(5)
SA(6)
SA+1
SA+1
SA+2 SP…
SP–7 SP–8 SP–8
FFF2
FFF3
New
PC
Notes:
(1) Edge sensitive IRQ pin (IRQE = 1).
(2) Level sensitive IRQ pin (IRQE = 0).
(3) tSTOPDELAY = 4064 tCYC (DLY = 1) or 4 tCYC (DLY = 0).
(4) XIRQ with X-bit in CCR = 1.
(5) IRQ (or XIRQ, with X-bit = 0; in this case vector fetch will be $FFF4/5).
(6) SA = STOP address.
Figure 12-5. STOP recovery timing
E clock
tPCSU
IRQ, XIRQ,
or internal
interrupts
tWRS
Address
WA(1) WA+1
SP
SP–1
SP–2…SP–8
SP–8 SP–8…SP–8
SP–8 SP–8 SP–8
VA(2)
VA+1
New
PC
Stack registers
R/W
Notes:
RESET also causes recovery from WAIT.
(1) WA = WAIT address.
(2) VA = Vector address.
MC68HC11P2 — Rev 1.0
Technical Data
Electrical Specifications
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Electrical Specifications
12.7.1 Peripheral port timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
fOP
2.0MHz
Min.
Max.
0
2.0
3.0MHz
Min.
Max.
0
3.0
4.0MHz
Min.
Max.
0
4.0
tCYC
500
—
333
—
250
—
ns
tPDSU
100
—
100
—
100
—
ns
tPDH
50
—
50
—
50
—
ns
—
—
200
225
—
—
200
183
—
—
200
162
Characteristic (1)
Symbol
Frequency of operation (E clock frequency)
E clock period
Peripheral data set-up time, all ports
Peripheral data hold time, all ports
(2)
(2)
Unit
MHz
tPWD
Delay time, peripheral data write
MCU write to port A, B, G or H
MCU write to port C, D or F
ns
1. All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits clear in OPT2 and SPCR registers, respectively).
MCU read of port
E clock
tPDSU
tPDH
Ports
A, C, D, F
tPDSU
tPDH
Ports
B, E, G, H
Figure 12-7. Port read timing diagram
MCU write to port
E clock
tPWD
Ports
C, D, F
Previous port data
New data valid
tPWD
Ports
A, B, G, H
Previous port data
New data valid
Figure 12-8. Port write timing diagram
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Electrical Specifications
Control timing
12.7.2 Analog-to-digital converter characteristics
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, 750kHz ″ E ″ 4MHz, unless otherwise noted)
Characteristic
Parameter
Resolution
Number of bits resolved by ADC
Maximum deviation from the ideal ADC
Non-linearity
transfer characteristics
Difference from the output of an ideal ADC for
Zero error
zero input voltage
Full-scale
Difference from the output of an ideal ADC for
error
full-scale input voltage
Total
Maximum sum of non-linearity, zero and fullunadjusted
scale errors
error
Quantization
Uncertainty due to converter resolution
error
Difference between the actual input voltage
Absolute
and the full-scale weighted equivalent of the
accuracy
binary output code, including all error sources
Conversion
Analog input voltage range
range
VRH
Analog reference voltage (high) (2)
(2)
2MHz(1) 3MHz(1) 4MHz(1)
Unit
Max.
Max.
Max.
—
—
—
bits
Min.
Absolute
—
8
—
—
±0.5
±1
±1
LSB
—
—
±0.5
±1
±1
LSB
—
—
±0.5
±1
±1
LSB
—
—
±0.5
±1.5
±1.5
LSB
—
—
±0.5
±0.5
±0.5
LSB
—
—
±1
±2
±2
LSB
VRL
—
VRH
VRH
VRH
V
VRL
—
VDD+0.1 VDD+0.1 VDD+0.1
V
VSS–0.1
—
VRH
VRH
VRH
V
∅VR
Minimum difference between VRH and VRL
(2)
3
—
—
—
—
V
Conversion
time
Total time to perform a single A/D conversion:
E clock
Internal RC oscillator
—
—
32
—
Monotonicity
Conversion result never decreases with an
increase in input voltage and has no missing codes
VRL
Zero input
reading
Full-scale
reading
Sample
acquisition
time
Analog reference voltage (low)
—
—
tCYC
—
tCYC+32 tCYC+32 tCYC+32 µs
Guaranteed
Conversion result when VIN = VRL
$00
—
—
—
—
Hex
Conversion result when VIN = VRH
—
—
$FF
$FF
$FF
Hex
Analogue input acquisition sampling time:
E clock
Internal RC oscillator
—
—
12
—
—
12
—
12
—
12
tCYC
µs
—
20 (typ)
—
—
—
pF
—
—
—
—
400
1.0
400
1.0
400
1.0
nA
µA
Sample/hold
Input capacitance (PE[0:7]) during sample
capacitance
Input leakage on A/D pins:
Input
PE[0:7]
leakage
VRL, VRH
MC68HC11P2 — Rev 1.0
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Electrical Specifications
12.7.3 Serial peripheral interface timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Characteristic (1)
Num
Symbol
2.0MHz
Min. Max.
3.0MHz
Min. Max.
4.0MHz
Min. Max.
Unit
Operating frequencyMaster
Slave
fOP(M)
fOP(S)
0
0
0.5
2.0
0
0
0.5
3.0
0
0
0.5
4.0
fOP
MHz
1
Cycle timeMaster
Slave
tCYC(M)
tCYC(S)
2.0
500
—
—
2.0
333
—
—
2.0
250
—
—
tCYC
ns
2
Enable lead time (2) Master
Slave
tLEAD(M)
tLEAD(S)
—
250
—
—
—
240
—
—
—
200
—
—
ns
3
Enable lag time (2) Master
Slave
tLAG(M)
tLAG(S)
—
250
—
—
—
240
—
—
—
200
—
—
ns
4
Clock (SCK) high timeMaster
Slave
340
190
—
—
227
127
—
—
130
85
—
—
ns
tW(SCKL)M 340
tW(SCKL)S 190
—
—
227
127
—
—
130
85
—
—
ns
tW(SCKH)
M
tW(SCKH)S
5
Clock (SCK) low timeMaster
Slave
6
Input data set-up timeMaster
Slave
tSU(M)
tSU(S)
100
100
—
—
100
100
—
—
100
100
—
—
ns
7
Input data hold timeMaster
Slave
tH(M)
tH(S)
100
100
—
—
100
100
—
—
100
100
—
—
ns
8
Access time (from high-z to data active)
Slave
tA
0
120
0
120
0
120
ns
9
Disable time (hold time to high-z state)Slave
tDIS
—
240
—
167
—
125
ns
10
Data valid (after enable edge) (3)
tV(S)
—
240
—
167
—
125
ns
11
Output data hold time (after enable edge)
tHO
0
—
0
—
0
—
ns
12
Rise time (3)
SPI outputs (SCK, MOSI and MISO)
SPI inputs (SCK, MOSI, MISO and SS)
tRM
tRS
—
—
100
2.0
—
—
100
2.0
—
—
100
2.0
ns
µs
13
Fall time (3)
SPI outputs (SCK, MOSI and MISO)
SPI inputs (SCK, MOSI, MISO and SS)
tFM
tFS
—
—
100
2.0
—
—
100
2.0
—
—
100
2.0
ns
µs
1. All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
2. Signal production depends on software.
3. Assumes 200pF load on all SPI pins.
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
Control timing
SS
(input)
SS is held high on master
1
SCK (CPOL=0)
(output)
SCK (CPOL=1)
(output)
12
13
13
12
5
(see note)
4
5
(see note)
4
6
MISO
(input)
7
MSB in
Bit 6……1
10 (ref.)
11
MOSI
(output)
Master MSB out
LSB in
10
11 (ref.)
Bit 6……1
Master LSB out
13
12
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
Figure 12-9. SPI master timing (CPHA = 0)
SS
(input)
SS is held high on master
1
13
12
5
SCK (CPOL=0)
(output)
(see note)
4
12
13
5
SCK (CPOL=1)
(output)
(see note)
4
6
MISO
(input)
MSB in
10 (ref.)
Bit 6……1
11
MOSI
(output)
Master MSB out
7
LSB in
10
Bit 6……1
13
11 (ref.)
Master LSB out
12
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
Figure 12-10. SPI master timing (CPHA = 1)
MC68HC11P2 — Rev 1.0
Technical Data
Electrical Specifications
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Electrical Specifications
SS
(input)
1
13
12
12
13
3
5
SCK (CPOL=0)
(input)
4
2
5
SCK (CPOL=1)
(input)
4
6
MOSI
(input)
7
MSB in
Bit 6……1
8
MISO
(output)
10
Slave MSB out
LSB in
11
9
Bit 6……1
Slave LSB out
(see note)
Note: Not defined, but normally the MSB of character just received.
Figure 12-11. SPI slave timing (CPHA = 0)
SS
(input)
1
12
12
13
3
5
SCK (CPOL=0)
(input)
4
2
5
SCK (CPOL=1)
(input)
4
6
MOSI
(input)
7
MSB in
8
MISO
(output)
13
Bit 6……1
10
(see note)
LSB in
11
Slave MSB out
Bit 6……1
9
Slave LSB out
Note: Not defined, but normally the LSB of character last transmitted.
Figure 12-12. SPI slave timing (CPHA = 1)
Technical Data
MC68HC11P2 — Rev 1.0
Electrical Specifications
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Electrical Specifications
Control timing
12.7.4 Nonmultiplexed expansion bus timing
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Num
1
2
3
4A
4B
9
11
12
fOP
2.0MHz
Min. Max.
0
2.0
3.0MHz
Min. Max.
0
3.0
4.0MHz
Min. Max.
0
4.0
tCYC
500
—
333
—
250
—
ns
PWEL
230
—
147
—
105
—
ns
PWEH
225
—
142
—
100
—
ns
tr
tf
—
—
20
20
—
—
20
18
—
—
20
15
ns
tAH
53
—
32
—
21
—
ns
tAD
—
103
—
82
—
71
ns
tAV
127
—
65
—
34
—
ns
tDSR
30
—
30
—
20
—
ns
tDHR
0
—
0
—
0
—
ns
tDDW
—
40
—
40
—
40
ns
tDHW
63
—
42
—
31
—
ns
Characteristic (1)
Symbol
Frequency of operation (E clock frequency)
E clock period
Pulse width, E low
(2), (3)
Pulse width, E high
(2), (3)
E clockrise time
fall time
Address hold time (3)
Address delay time
(3)
17
Address valid to E rise time
Read data set-up time
18
Read data hold time
19
Write data delay time
(3)
(3)
Unit
MHz
21
Write data hold time
29
MPU address access time (3)
tACCA
347
—
203
—
144
—
ns
39
Write data set-up time (3)
Address valid to data tristate time
tDSW
185
—
102
—
60
—
ns
tAVDZ
—
10
—
10
—
10
ns
57
1. All timing is given with respect to 20% and 70% of VDD, unless otherwise noted.
2. Input clock duty cycles other than 50% will affect the bus performance.
3. For fOP 2MHz the following formulae may be used to calculate parameter values:
PWEL = tCYC/2 – 20ns PWEH = tCYC/2 – 25ns
tAH = tCYC/8 – 10ns tAD = tCYC/8 + 40ns
tAV = PWEL – tAD tDHW = tCYC/8
tACCA = tCYC – tf – tDSR – tADtDSW = PWEH – tDDW
tECSA = PWEH – tECSD – tDSRtACSD = tCYC/4 + 40ns
tACSA = tCYC – tf – tDSR – tACSD
MC68HC11P2 — Rev 1.0
Technical Data
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Electrical Specifications
1
3
4B
2
E clock
4A
11
12
9
R/W,
Address
29
17
18
Data
(read)
19
57
39
21
Data
(write)
Figure 12-13. Expansion bus timing
12.7.5 EEPROM characteristics
Characteristic
–40 to +85°C
Temperature range
–40 to +105°C –40 to +125°C
Unit
Programming time (1)
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