MC7457RX1000NC

Freescale Semiconductor Data Sheet: Technical Data MPC7457EC Rev. 8, 04/2013 MPC7457 RISC Microprocessor This hardware specification is primarily concerned with the MPC7457; however, unless otherwise noted, all information here also applies to the MPC7447. The MPC7457 and MPC7447 are implementations of the PowerPC™ microprocessor family of reduced instruction set computer (RISC) microprocessors. This hardware specification describes pertinent electrical and physical characteristics of the MPC7457. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family User’s Manual. To locate any published updates for this hardware specification, refer to the website listed on the back page of this document. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2006 Freescale Semiconductor, Inc. All rights reserved. Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 . . . . . . . . . . . . 9 4. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. Electrical and Thermal Characteristics . . . . . . . . . . . 11 6. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 44 9. System Design Information . . . . . . . . . . . . . . . . . . . 50 11. Document Revision History . . . . . . . . . . . . . . . . . . . 68 10. Part Numbering and Marking . . . . . . . . . . . . . . . . . . 65 Overview 1 Overview The MPC7457 is the fourth implementation of the fourth generation (G4) microprocessors from Freescale. The MPC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7457 consists of a processor core, a 512-Kbyte L2, and an internal L3 tag and controller that support a glueless backside L3 cache through a dedicated high-bandwidth interface. The MPC7447 is identical to the MPC7457 except that it does not support the L3 cache interface. Figure 1 shows a block diagram of the MPC7457. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. The L3 interface supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as cache; the remaining 2 Mbytes must be private memory. Note that the MPC7457 is a footprint-compatible, drop-in replacement in a MPC7455 application if the core power supply is 1.3 V. 2 Features This section summarizes features of the MPC7457 implementation of the PowerPC architecture. Major features of the MPC7457 are as follows: • High-performance, superscalar microprocessor — As many as four instructions can be fetched from the instruction cache at a time. — As many as three instructions can be dispatched to the issue queues at a time. — As many as 12 instructions can be in the instruction queue (IQ). — As many as 16 instructions can be at some stage of execution simultaneously. — Single-cycle execution for most instructions — One instruction per clock cycle throughput for most instructions — Seven-stage pipeline control • Eleven independent execution units and three register files — Branch processing unit (BPU) features static and dynamic branch prediction – 128-entry (32-set, four-way set associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. – 2048-entry branch history (BHT) with 2 bits per entry for 4 levels of prediction—not-taken, strongly not-taken, taken, and strongly taken – Up to three outstanding speculative branches MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 2 Freescale Semiconductor Features – Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. – Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 3 4 Completes up to three instructions per clock 96-Bit (3 Instructions) Vector Integer Unit 2 128-Bit Dispatch Unit +++ x÷ 32-Bit Integer Integer Integer Unit 122 Unit Unit (3) Integer Unit 2 Notes: 1. The L3 cache interface is not implemented on the MPC7447. 2. The Castout Queue and Push Queue share resources such for a combined total of 10 entries. The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push. L2 Store Queue (L2SQ) Snoop Push/ L1 Castouts Interventions (4) Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status 19-Bit Address Bus Accumulator 128-Entry ITLB Load/Store Unit Completed Stores L1 Push Finished Stores External SRAM (1, 2, or 4 Mbytes) 64-Bit Data (8-Bit Parity) L3CR FPR File Tags 64-Bit FPSCR + x÷ FloatingPoint Unit Reservation Stations (2) 36-Bit Address Bus 64-Bit Data Bus Bus Accumulator Bus Store Queue Castout Queue (9)/ Push Queue (10) 2 System Bus Interface 64-Bit 32-Kbyte I Cache 32-Kbyte D Cache Tags 128-Bit (4 Instructions) 16 Rename Buffers PA Load Queue (11) Load Miss L1 Castout + (EA Calculation) Vector Touch Engine EA 128-Entry DTLB DBAT Array SRs (Original) Data MMU IBAT Array SRs (Shadow) Instruction MMU Reservation Stations (2-Entry) L3 Cache Controller 1 32-Bit Line Block 0/1 Tags Status 32-Bit 16 Rename Buffers GPR File Vector Touch Queue FPR Issue (2-Entry/1-Issue) Instruction Queue (12-Word) Reservation Reservation Reservation Station Station Station 512-Kbyte Unified L2 Cache Controller 128-Bit Vector FPU L2 Prefetch (3) L1 Service Queues Vector Integer Unit 1 Instruction Fetch (2) Cacheable Store Request(1) L1 Load Miss (5) L1 Load Queue (LLQ) L1 Store Queue (LSQ) Memory Subsystem Vector Permute Unit 16 Rename Buffers VR File Reservation Stations (2) LR BHT (2048-Entry) VR Issue (4-Entry/2-Issue) CTR BTIC (128-Entry) Fetcher GPR Issue (6-Entry/3-Issue) Instruction Unit Branch Processing Unit Reservation Reservation Reservation Reservation Station Station Station Station Completion Queue (16-Entry) Completion Unit • Time Base Counter/Decrementer • Clock Multiplier • JTAG/COP Interface • Thermal/Power Management • Performance Monitor Additional Features Features Figure 1. MPC7457 Block Diagram MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor Features • — Four integer units (IUs) that share 32 GPRs for integer operands – Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions – IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions — Five-stage FPU and a 32-entry FPR file – Fully IEEE 754-1985 compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Hardware support for denormalized numbers – Thirty-two 64-bit FPRs for single- or double-precision operands — Four vector units and 32-entry vector register file (VRs) – Vector permute unit (VPU) – Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add instructions (for example, vaddsbs, vaddshs, and vaddsws) – Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm) – Vector floating-point unit (VFPU) — Three-stage load/store unit (LSU) – Supports integer, floating-point, and vector instruction load/store traffic – Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations – Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle throughput – Four-cycle FPR load latency (single, double) with one-cycle throughput – No additional delay for misaligned access within double-word boundary – Dedicated adder calculates effective addresses (EAs) – Supports store gathering – Performs alignment, normalization, and precision conversion for floating-point data – Executes cache control and TLB instructions – Performs alignment, zero padding, and sign extension for integer data – Supports hits under misses (multiple outstanding misses) – Supports both big- and little-endian modes, including misaligned little-endian accesses Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: — Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2 — A maximum of three instructions can be dispatched to the issue queues per clock cycle MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 5 Features • • • • • — Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue) Rename buffers — 16 GPR rename buffers — 16 FPR rename buffers — 16 VR rename buffers Dispatch unit — Decode/dispatch stage fully decodes each instruction Completion unit — The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending. — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch — Retires as many as three instructions per clock cycle Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set associative instruction and data caches — Pseudo least recently used (PLRU) replacement algorithm — 32-byte (eight-word) L1 cache block — Physically indexed/physical tags — Cache write-back or write-through operation programmable on a per-page or per-block basis — Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle — Caches can be disabled in software. — Caches can be locked in software. — MESI data cache coherency maintained in hardware — Separate copy of data cache tags for efficient snooping — L1 cache supports parity generation and checking — No snooping of instruction cache except for icbi instruction — Data cache supports AltiVec LRU and transient instructions — Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding. Level 2 (L2) cache interface — On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache — Fully pipelined to provide 32 bytes per clock cycle to the L1 caches — A total nine-cycle load latency for an L1 data cache miss that hits in L2 MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 6 Freescale Semiconductor Features • • • — PLRU replacement algorithm — Cache write-back or write-through operation programmable on a per-page or per-block basis — 64-byte, two-sectored line size — L2 cache supports parity and generation checking on both tags and data Level 3 (L3) cache interface (not implemented on MPC7447) — Provides critical double-word forwarding to the requesting unit — Internal L3 cache controller and tags — External data SRAMs — Support for 1-, 2-, and 4-Mbyte (MB) total SRAM space — Support for 1- or 2-MB of cache space — Cache write-back or write-through operation programmable on a per-page or per-block basis — 64-byte (1-MB) or 128-byte (2-MB) sectored line size — Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-, or 4-MB of private memory — Supports MSUG2 dual data rate (DDR) synchronous burst SRAMs, PB2 pipelined synchronous burst SRAMs, and pipelined (register-register) late write synchronous burst SRAMs — Supports parity on cache and tags — Configurable core-to-L3 frequency divisors — 64-bit external L3 data bus sustains 64 bits per L3 clock cycle Separate memory management units (MMUs) for instructions and data — 52-bit virtual address; 32- or 36-bit physical address — Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBATs (eight each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs) – Both TLBs are 128-entry, two-way set associative, and use LRU replacement algorithm – TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed in hardware or by system software) Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs — L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache — As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and L2/L3 bus — As many as 16 out-of-order transactions can be present on the MPX bus MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 7 Features • • • • • • — Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). — Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache — Separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the L1 data cache and L2 cache Multiprocessing support features include the following: — Hardware-enforced, MESI cache coherency protocols for data cache — Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations Power and thermal management — 1.3-V processor core — The following three power-saving modes are available to the system: – Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and back to nap using a QREQ/QACK processor-system handshake protocol. – Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. – Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed on exiting the deep sleep state. — Thermal management facility provides software-controllable thermal management. Thermal management is performed through the use of three supervisor-level registers and an MPC7457-specific thermal management exception. — Instruction cache throttling provides control of instruction fetching to limit power consumption Performance monitor can be used to help debug system designs and improve software efficiency In-system testability and debugging features through JTAG boundary-scan capability Testability — LSSD scan design — IEEE 1149.1 JTAG interface — Array built-in self test (ABIST)—factory test only Reliability and serviceability — Parity checking on system bus and L3 cache bus — Parity checking on the L2 and L3 cache tag arrays MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 8 Freescale Semiconductor Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 3 Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 Table 1 compares the key features of the MPC7457 with the key features of the earlier MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7457 is extended (compared to the MPC7400), while maintaining the same level of performance as measured by the number of instructions executed per cycle (IPC). Table 1. Microarchitecture Comparison Microarchitectural Specs MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/ MPC7441 Basic Pipeline Functions Logic inversions per cycle 18 18 18 Pipeline stages up to execute 5 5 5 Total pipeline stages (minimum) 7 7 7 3 + Branch 3 + Branch 3 + Branch Pipeline maximum instruction throughput Pipeline Resources Instruction buffer size 12 12 12 Completion buffer size 16 16 16 16, 16, 16 16, 16, 16 16, 16, 16 3 3 3 2 (any 2 of 4 units) 2 (any 2 of 4 units) 2 (any 2 of 4 units) 1 1 1 Renames (integer, float, vector) Maximum Execution Throughput SFX Vector Scalar floating-point Out-of-Order Window Size in Execution Queues 1 entry × 3 queues 1 entry × 3 queues 1 entry × 3 queues In order, 4 queues In order, 4 queues In order, 4 queues In order In order In order BTIC, BHT, link stack BTIC, BHT, link stack BTIC, BHT, link stack 128-entry, 4-way 128-entry, 4-way 128-entry, 4-way 2K-entry 2K-entry 2K-entry Link stack depth 8 8 8 Unresolved branches supported 3 3 3 Branch taken penalty (BTIC hit) 1 1 1 SFX integer units Vector units Scalar floating-point unit Branch Processing Resources Prediction structures BTIC size, associativity BHT size MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 9 Comparison with the MPC7455, MPC7445, MPC7450, MPC7451, and MPC7441 Table 1. Microarchitecture Comparison (continued) Microarchitectural Specs Minimum misprediction penalty MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/ MPC7441 6 6 6 Execution Unit Timings (Latency-Throughput) Aligned load (integer, float, vector) 3-1, 4-1, 3-1 3-1, 4-1, 3-1 3-1, 4-1, 3-1 Misaligned load (integer, float, vector) 4-2, 5-2, 4-2 4-2, 5-2, 4-2 4-2, 5-2, 4-2 9 data/13 instruction 9 data/13 instruction 9 data/13 instruction SFX (aDd Sub, Shift, Rot, Cmp, logicals) 1-1 1-1 1-1 Integer multiply (32 × 8, 32 × 16, 32 × 32) 3-1, 3-1, 4-2 3-1, 3-1, 4-2 3-1, 3-1, 4-2 Scalar float 5-1 5-1 5-1 VSFX (vector simple) 1-1 1-1 1-1 VCFX (vector complex) 4-1 4-1 4-1 VFPU (vector float) 4-1 4-1 4-1 VPER (vector permute) 2-1 2-1 2-1 128-entry, 2-way 128-entry, 2-way 128-entry, 2-way Hardware + software Hardware + software Hardware + software 8/8 8/8 4/4 32K/32K 32K/32K 32K/32K 8-way 8-way 8-way Locking granularity Way Way Way Parity on I cache Word Word Word Parity on D cache Byte Byte Byte 5/1 5/1 5/1 4 streams 4 streams 4 streams L2 L2 L2 512-Kbyte/8-way 256-Kbyte/8-way 256-Kbyte/8-way 256 bits 256 bits 256 bits 2 2 2 Byte Byte Byte L1 miss, L2 hit latency MMUs TLBs (instruction and data) Tablewalk mechanism Instruction BATs/data BATs L1 I Cache/D Cache Features Size Associativity Number of D cache misses (load/store) Data stream touch engines On-Chip Cache Features Cache level Size/associativity Access width Number of 32-byte sectors/line Parity Off-Chip Cache Support 1 MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 10 Freescale Semiconductor General Parameters Table 1. Microarchitecture Comparison (continued) Microarchitectural Specs MPC7457/MPC7447 MPC7455/MPC7445 MPC7450/MPC7451/ MPC7441 L3 L3 L3 1 MB, 2MB, 4 MB 2 1 MB, 2 MB 1 MB, 2 MB 1 MB, 2 MB 1 MB, 2 MB 1 MB, 2 MB 8-way 8-way 8-way 2, 4 2, 4 2, 4 MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 MSUG2 DDR, LW, PB2 64 64 64 1 MB, 2 MB, 4 MB 1 MB, 2 MB 1 MB, 2 MB Byte Byte Byte Cache level Total SRAM space supported On-chip tag logical size (cache space) Associativity Number of 32-byte sectors/line Off-Chip data SRAM support Data path width Direct mapped SRAM sizes Parity Notes: 1. Not implemented on MPC7447, MPC7445, or MPC7441. 2. The MPC7457 supports up to 4 MB of SRAM, of which a maximum of 2 MB can be configured as cache memory; the remaining 2 MB may be unused or configured as private memory. 4 General Parameters The following list provides a summary of the general parameters of the MPC7457: Technology 0.13 μm CMOS, nine-layer metal Die size 9.1 mm × 10.8 mm Transistor count 58 million Logic design Fully-static Packages MPC7447: Surface mount 360 ceramic ball grid array (CBGA) MPC7457: Surface mount 483 ceramic ball grid array (CBGA) Core power supply 1.3 V ±50 mV DC nominal I/O power supply 1.8 V ±5% DC, or 2.5 V ±5% DC, or 1.5 V ±5% DC (L3 interface only, not implemented on MPC7447) 5 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7457. 5.1 DC Electrical Characteristics The tables in this section describe the MPC7457 DC electrical characteristics.Table 2 provides the absolute maximum ratings. MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 11 Electrical and Thermal Characteristics Table 2. Absolute Maximum Ratings 1 Characteristic Symbol Maximum Value Unit Notes Core supply voltage VDD –0.3 to 1.60 V 2 PLL supply voltage AVDD –0.3 to 1.60 V 2 BVSEL = 0 OVDD –0.3 to 1.95 V 3, 4 BVSEL = HRESET or OVDD OVDD –0.3 to 2.7 V 3, 5 L3VSEL = ¬HRESET GVDD –0.3 to 1.65 V 3, 6 L3VSEL = 0 GVDD –0.3 to 1.95 V 3, 7 L3VSEL = HRESET or GVDD GVDD –0.3 to 2.7 V 3, 8 Processor bus Vin –0.3 to OVDD + 0.3 V 9, 10 L3 bus Vin –0.3 to GVDD + 0.3 V 9, 10 JTAG signals Vin –0.3 to OVDD + 0.3 V Tstg –55 to 150 °C Processor bus supply voltage L3 bus supply voltage Input voltage Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. BVSEL must be set to 0, such that the bus is in 1.8-V mode. 5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode. 6. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5-V mode. 7. L3VSEL must be set to 0, such that the bus is in 1.8-V mode. 8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5-V mode. 9. Caution: Vin must not exceed OVDD or GVDD by more than 0.3 V at any time including during power-on reset. 10.Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. Figure 2 shows the undershoot and overshoot voltage on the MPC7457. MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 12 Freescale Semiconductor Electrical and Thermal Characteristics OVDD/GVDD + 20% OVDD/GVDD + 5% OVDD/GVDD VIH VIL GND GND – 0.3 V GND – 0.7 V Not to exceed 10% of tSYSCLK Figure 2. Overshoot/Undershoot Voltage The MPC7457 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7457 core voltage must always be provided at nominal 1.3 V (see Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD or GVDD power pins. Table 3. Input Threshold Voltage Setting BVSEL Signal Processor Bus Input Threshold is Relative to: L3VSEL Signal 1 L3 Bus Input Threshold is Relative to: Notes 0 1.8 V 0 1.8 V 2, 3 ¬HRESET Not Available ¬HRESET 1.5 V 2, 4 HRESET 2.5 V HRESET 2.5 V 2 1 2.5 V 1 2.5 V 2 Notes: 1. Not implemented on MPC7447. 2. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2. 3. If used, pull-down resistors should be less than 250 Ω. 4. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET. MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor 13 Electrical and Thermal Characteristics Table 4 provides the recommended operating conditions for the MPC7457. Table 4. Recommended Operating Conditions 1 Recommended Value Characteristic Symbol Unit Min Core supply voltage VDD 1.3 V ± 50 mV V PLL supply voltage AVDD 1.3 V ± 50 mV V BVSEL = 0 OVDD 1.8 V ± 5% V BVSEL = HRESET or OVDD OVDD 2.5 V ± 5% V L3VSEL = 0 GVDD 1.8 V ± 5% V L3VSEL = HRESET or GVDD GVDD 2.5 V ± 5% V L3VSEL = ¬HRESET GVDD 1.5 V ± 5% V Processor bus supply voltage L3 bus supply voltage Input voltage Processor bus Vin GND OVDD V L3 bus Vin GND GVDD V JTAG signals Vin GND OVDD V Tj 0 105 °C Die-junction temperature Notes Max 2 3 Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. 3. ¬HRESET is the inverse of HRESET. Table 5 provides the package thermal characteristics for the MPC7457. Table 5. Package Thermal Characteristics 1 Value Characteristic Symbol MPC7447 MPC7457 Unit Notes Junction-to-ambient thermal resistance, natural convection RθJA 22 20 °C/W 2, 3 Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board RθJMA 14 14 °C/W 2, 4 Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board RθJMA 16 15 °C/W 2, 4 Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board RθJMA 11 11 °C/W 2, 4 Junction-to-board thermal resistance RθJB 6 6 °C/W 5 Junction-to-case thermal resistance RθJC