MC88915FN70R2

   SEMICONDUCTOR TECHNICAL DATA         The MC88915 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 7). Five “Q” outputs (QO–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2. The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1 and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20 MHz). In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see detailed description on page 11). A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go low if phase–lock is lost or when the PLL_EN pin is low. Under certain conditions the lock output may remain low, even though the part is phase–locked. Therefore the LOCK output signal should not be used to drive any active circuitry; it should be used for passive monitoring or evaluation purposes only. Features • Five Outputs (QO–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input • The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part–to–part skew) • Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available • Input frequency range from 5MHz – 2X_Q FMAX spec • Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available • All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL–level compatible • Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes RST VCC Q5 GND Q4 VCC 2X_Q 4 3 2 1 28 27 26 FEEDBACK 5 25 Q/2 REF_SEL 6 24 GND SYNC[0] 7 23 Q3 VCC(AN) 8 22 VCC RC1 9 21 Q2 GND(AN) 10 20 GND SYNC[1] 11 19 LOCK 12 13 FREQ_SEL Q0 16 17 18 VCC Q1 GND PLL_EN FN SUFFIX PLASTIC PLCC CASE 776–02 ORDERING INFORMATION MC88915FN55 PLCC MC88915FN70 PLCC 1/97 1 GND 15 28–Lead Pinout (Top View) Yield Surface Modeling and YSM are trademarks of Motorola, Inc.  Motorola, Inc. 1997 14 REV 4 MC88915 LOCK FEEDBACK SYNC (0) 0 SYNC (1) 1 M U X PHASE/FREQ. CHARGE PUMP/LOOP FILTER DETECTOR VOLTAGE CONTROLLED OSCILLATOR EXTERNAL REC NETWORK (RC1 Pin) REF_SEL 2x_Q 1 0 PLL_EN MUX D (÷1) CP 1 DIVIDE BY TWO Q (÷2) Q0 Q R M U X 0 D Q Q1 Q Q2 Q Q3 Q Q4 Q Q5 Q Q/2 CP R FREQ_SEL RST D CP PIN SUMMARY Pin Name Num I/O SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK RC1 Q(0–4) Q5 2x_Q Q/2 LOCK RST PLL_EN VCC,GND 1 1 1 1 1 1 5 1 1 1 1 1 1 11 Input Input Input Input Input Input Output Output Output Output Output Input Input R Function Reference clock input Reference clock input Chooses reference between sync[0] & Sync[1] Selects Q output frequency Feedback input to phase detector Input for external RC network Clock output (locked to sync) Inverse of clock output 2 x clock output (Q) frequency (synchronous) Clock output(Q) frequency ÷ 2 (synchronous) Indicates phase lock has been achieved (high when locked) Asynchronous reset (active low) Disables phase–lock for low freq. testing Power and ground pins (note pins 8, 10 are “quiet” supply pins for internal logic only) D CP R D CP R D CP R D CP R MC88915 Block Diagram MOTOROLA 2 TIMING SOLUTIONS BR1333 — Rev 6 MC88915 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND; TA =0° C to + 70° C, VCC = 5.0V ± 5%) Symbol Parameter Test Conditions VCC V Guaranteed Limit Unit VIH Minimum High–Level Input Voltage Vout = 0.1 V or VCC – 0.1 V 4.75 5.25 2.0 2.0 V VIL Maximum Low–Level Input Voltage Vout = 0.1 V or VCC – 0.1 V 4.75 5.25 0.8 0.8 V VOH Minimum High–Level Output Voltage Vin = VIH or VIL IOH = –36 mA 1 4.75 5.25 4.01 4.51 V VOL Maximum Low–Level Output Voltage Vin = VIH or VIL IOL = 36 mA 1 4.75 5.25 0.44 0.44 V Maximum Input Leakage Current VI = VCC or GND 5.25 ±1.0 µA ICCT Maximum ICC/Input VI = VCC – 2.1 V 5.25 1.5 2 mA IOLD Minimum Dynamic Output Current 3 VOLD = 1.0V Max 5.25 88 mA VOHD = 3.85 V Max 5.25 –88 mA VI = VCC or GND 5.25 1.0 mA Iin IOHD ICC Maximum Quiescent Supply Current (per Package) 1. IOL and IOH are 12mA and –12mA respectively for the LOCK output. 2. The PLL_EN input pin is not guaranteed to meet this specification. 3. Maximum test duration is 2.0ms, one output loaded at a time. CAPACITANCE AND POWER SPECIFICATIONS Symbol Parameter Typical Values Unit Conditions 4.5 pF VCC = 5.0 V CIN Input Capacitance CPD Power Dissipation Capacitance 40 pF VCC = 5.0 V PD1 Power Dissipation @ 33MHz with 50Ω Thevenin Termination 15 mW/Output 120 mW/Device mW VCC = 5.0 V T = 25°C PD2 Power Dissipation @ 33MHz with 50Ω Parallel Termination to GND 37.5 mW/Output 300 mW/Device mW VCC = 5.0 V T = 25° C SYNC INPUT TIMING REQUIREMENTS Symbol tRISE, tFALL tCYCLE Duty Cycle Parameter Min Maximum Rise and Fall times, (SYNC Inputs: From 0.8V – 2.0V) – FN55 FN70 36 28.5 Input Clock Period (SYNC Inputs) Max Unit 3.0 ns 2001 ns 50% ±25% Input Duty Cycle (SYNC Inputs) 1. Information in Fig. 5 and in the “General AC Specification Notes”, Note #3 describes this specification and its actual limits depending on the application. FREQUENCY SPECIFICATIONS (TA =0° C to + 70° C, VCC = 5.0V ±5%, CL = 50pF) Guaranteed Minimum Symbol fmax 1 Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0–Q4,Q5 Output) MC88915FN55 MC88915FN70 Unit 55 70 MHz 27.5 35 MHz 1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded at 50 pF. TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MC88915 AC ELECTRICAL CHARACTERISTICS (TA =0° C to +70° C, VCC = 5.0V ±5%, CL = 50pF) Symbol Min Max Unit Rise and Fall Times, all Outputs Into a 50 pF, 500 Ω Load (Between 0.2VCC and 0.8VCC) 1.0 2.5 ns tRISE, tFALL 3 (2X_Q Output) Rise and Fall Time, 2X_Q Output Into a 20 pF Load With Termination specified in note 2 (Between 0.8 V and 2.0 V) 0.5 1.6 ns tPulse Width 3 Output Pulse Width (Q0, Q1, Q3, Q4, Q5, Q/2 @VCC/2) 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5 tRISE, tFALL (Outputs) Parameter (Q0,Q1,Q3,Q4, Q5,Q/2) tCYCLE = 1/Freq. at which the “Q” Outputs are running ns tPulse Width 3 (Q2 only) Output Pulse Width (Q2 Output @ VCC/2) 0.5tCYCLE – 0.6 0.5tCYCLE + 0.6 tPulse Width 3 (2X_Q Output) Output Pulse Width (2X_Q Output @ 1.5 V) (See AC Note 2) 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5 ns tPulse Width 3 (2X_Q Output) Output Pulse Width (2X_Q Output @ VCC/2) 0.5tCYCLE – 1.0 0.5tCYCLE + 1.0 ns tPD 3 (470kΩ From RC1 to An.VCC) (Sync–Feedback) SYNC input to feedback delay –1.05 (meas. @ SYNC0 or 1 and FEEDBACK input pins) (470kΩ From RC1 to An.GND) (See General AC Specification note 4 and Fig. 2 for explanation) tSKEWr 1,3 (Rising) tSKEWf 1,3 (Falling) tSKEWall 1,3 tLOCK tPHL (Reset – Q) –0.50 ns +1.25 +3.25 Output–to–Output Skew Between Outputs Q0 – Q4, Q/2 (Rising Edges Only) – 500 ps Output–to–Output Skew Between Outputs Q0 – Q4 (Falling Edges Only) – 750 ps Output–to–Output Skew Between Outputs 2X_Q, Q/2, Q0 – Q4 Rising, Q5 Falling – 750 ps Time Required to acquire 2 Phase–Lock from time SYNC Input Signal is Received. 1 10 ms 1.5 13.5 ns Propagation Delay, RST to Any Output (High–Low) 1. Under equally loaded conditions, CL ≤50pF (±2pF), and at a fixed temperature and voltage. 2. With VCC fully powered–on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min is with C1 = 0.01µF. 3. These specifications are not tested, they are guaranteed by statistical characterization. See General AC Specification note 1. RESET TIMING REQUIREMENTS 1 Symbol Parameter Minimum Unit tREC, RST to SYNC Reset Recovery Time rising RST edge to falling SYNC edge 9.0 ns tW, RST LOW Minimum Pulse Width, RST input LOW 5.0 ns 1. These reset specs are valid only when PLL_EN is LOW and the part is in Test mode (not in phase–lock) MOTOROLA 4 TIMING SOLUTIONS BR1333 — Rev 6 MC88915 General AC Specification Notes statistical characterization. In this way all units passing the ATE test will meet or exceed the non–tested specifications limits. 1. Several specifications can only be measured when the MC88915 is in phase–locked operation. It is not possible to have the part in phase–lock on ATE (automated test equipment). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88915 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. Response Surface Modeling (RSM) techniques were used to relate IC performance to the CMOS transistor properties over operation voltage and temperature. IC Performance to each specification and fab variation were used in conjunction with Yield Surface Modeling (YSM ) methodology to set performance limits of ATE testable specifications within those which are to be guaranteed by Rs 88915 2X_Q Output 2. These two specs (tRlSE/FALL and tPULSE Width 2X_Q output) guarantee that the MC88915 meets the 25 MHz 68040 P–Clock input specification (at 50 MHz). For these two specs to be guaranteed by Motorola, the termination scheme shown below in Figure 1 must be used. 3. The wiring Diagrams and written explanations in Figure 5 demonstrate the input and output frequency relationships for three possible feedback configurations. The allowable SYNC input range for each case is also indicated. There are two allowable SYNC frequency ranges, depending whether FREQ_SEL is high or low. Although not shown, it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the “Q” outputs. Table 1 below summarizes the allowable SYNC frequency range for each possible configuration. ZO (CLOCK TRACE) 68040 P–Clock Input Rp Rs = Zo – 7 Ω Rp = 1.5 Zo Figure 1. MC68040 P–Clock Input Termination Scheme FREQ_SEL Level Feedback Output Allowable SYNC Input Frequency Range (MHZ) Corresponding VCO Frequency Range Phase Relationships of the “Q” Outputs to Rising SYNC Edge 0° HIGH Q/2 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAX Spec) HIGH Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 0° HIGH Q5 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 180° HIGH 2X_Q 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 0° LOW Q/2 2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec) 0° LOW Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAX Spec) 0° LOW Q5 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAXSpec) 180° LOW 2X_Q 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAXSpec) 0° Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations. 4. A 1 MΩ resistor tied to either Analog VCC or Analog GND as shown in Figure 2 is required to ensure no jitter is present on the MC88915 outputs. This technique causes a phase offset between the SYNC input and the output connected to the FEEDBACK input, measured at the input pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by measuring the phase relationship for the 14 TIMING SOLUTIONS BR1333 — Rev 6 lots described in note 1 while the part was in phase–locked operation. The actual measurements were made with a 10 MHz SYNC input (1.0 ns edge rate from 0.8 V – 2.0 V) with the Q/2 output fed back. The phase measurements were made at 1.5 V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100 Ω to ground. 5 MOTOROLA MC88915 EXTERNAL LOOP FILTER ANALOG VCC 470KΩ REFERENCE RESISTOR 330Ω RC1 330Ω 0.1µF R2 470KΩ REFERENCE RESISTOR C1 0.1µF ANALOG GND RC1 R2 C1 ANALOG GND With the 470KΩ resistor tied in this fashion, the tPD specification measured at the input pins is: With the 470KΩ resistor tied in this fashion, the tPD specification measured at the input pins is: tPD = 2.25ns ± 1.0ns tPD = –0.775ns ± 0.275ns 3.0V SYNC INPUT 2.25ns OFFSET SYNC INPUT 3.0V –0.775ns OFFSET 5.0V 5.0V FEEDBACK OUTPUT FEEDBACK OUTPUT Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is Present When a 470KΩ Resistor is Tied to VCC or Ground 5. The tSKEWr specification guarantees that the rising edges of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall within a 500ps window within one part. However, if the relative position of each output within this window is not specified, the 500 ps window must be added to each side of the tPD specification limits to calculate the total part–to–part skew. For this reason the absolute distribution of these outputs are provided in table 2. When taking the skew data, Q0 was used as a reference, so all measurements are relative to this output. The information in Table 2 is derived from measurements taken from the 14 process lots described in Note 1, over the temperature and voltage range. Output – (ps) + (ps) Q0 0 0 Q1 –72 40 Q2 –44 276 Q3 –40 255 Q4 –274 –34 Q/2 –16 250 2X_Q –633 –35 Table 2. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q, Within the 500ps tSKEWr Spec Window MOTOROLA 6 TIMING SOLUTIONS BR1333 — Rev 6 MC88915 6. Calculation of Total Output–to–Skew between multiple parts (Part–to–Part skew) – 0.32ns] = –1.37ns is the lower tPD limit, and [–0.5ns + 0.32ns] = –0.18ns is the upper limit. Therefore the worst case skew of output Q2 between any number of parts is |(–1.37) – (–0.18)| = 1.19ns. Q2 has the worst case skew distribution of any output, so 1.2ns is the absolute worst case output–to–output skew between multiple parts. By combining the tPD specification and the information in Note 5, the worst case output–to–output skew between multiple 88915’s connected in parallel can be calculated. This calculation assumes that all parts have a common SYNC input clock with equal delay of that input signal to each part. This skew value is valid at the 88915 output pins only (equally loaded), it does not include PCB trace delays due to varying loads. 7. Note 4 explains that the tPD specification was measured and is guaranteed for the configuration of the Q/2 output connected to the FEEDBACK pin and the SYNC input running at 10MHz. The fixed offset (tPD) as described above has some dependence on the input frequency and at what frequency the VCO is running. The graphs of Figure 3 demonstrate this dependence. With a 1MΩ resistor tied to analog VCC as shown in note 4, the tPD spec. limits between SYNC and the Q/2 output (connected to the FEEDBACK pin) are –1.05ns and –0.5ns. To calculate the skew of any given output between two or more parts, the absolute value of the distribution of that output given in table 2 must be subtracted and added to the lower and upper tPD spec limits respectively. For output Q2, [276 – (–44)] = 320ps is the absolute value of the distribution. Therefore [–1.05ns The data presented in Figure 3 is from devices representing process extremes, and the measurements were also taken at the voltage extremes (VCC = 5.25V and 4.75V). Therefore the data in Figure 3 is a realistic representation of the variation of tPD. –0.5 –0.50 –0.75 –1.0 tPD SYNC to FEEDBACK (ns) –1.5 tPD SYNC to –1.00 FEEDBACK (ns) –1.25 –2.0 –1.50 2.5 tPD SYNC to FEEDBACK (ns) 5.0 7.5 10.0 12.5 15.0 SYNC INPUT FREQUENCY (MHz) 17.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 SYNC INPUT FREQUENCY (MHz) Figure 3a. Figure 3b. tPD versus Frequency Variation for Q/2 Output Fed Back, Including Process and Voltage Variation @ 25°C (With 1MΩ Resistor Tied to Analog VCC) tPD versus Frequency Variation for Q4 Output Fed Back, Including Process and Voltage Variation @ 25°C (With 1MΩ Resistor Tied to Analog VCC) 3.5 3.5 3.0 3.0 2.5 2.0 tPD SYNC to 2.5 FEEDBACK (ns) 2.0 1.5 1.5 1.0 1.0 0.5 0.5 2.5 5.0 7.5 10.0 12.5 15.0 SYNC INPUT FREQUENCY (MHz) 17.5 0 5 10 15 20 SYNC INPUT FREQUENCY (MHz) 25 Figure 3c. Figure 3d. tPD versus Frequency Variation for Q/2 Output Fed Back, Including Process and Voltage Variation @ 25°C (With 1MΩ Resistor Tied to Analog GND) tPD versus Frequency Variation for Q4 Output Fed Back, Including Process and Voltage Variation @ 25°C (With 1MΩ Resistor Tied to Analog GND) TIMING SOLUTIONS BR1333 — Rev 6 7 MOTOROLA MC88915 SYNC INPUT (SYNC[1] or SYNC[0]) tCYCLE SYNC INPUT t PD FEEDBACK INPUT Q/2 OUTPUT tSKEWf tSKEWALL tSKEWr tSKEWf tSKEWR Q0 – Q4 OUTPUTS tCYCLE “Q” OUTPUTS Q5 OUTPUT 2X_Q OUTPUT Figure 4. Output / Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook–up configuration of Figure 5a on page 9) Timing Notes: • The MC88915 aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. • All skew specs are measured between the VCC/2 crossing point of the appropriate output edges.All skews are specified as ‘windows’, not as a ± deviation around a center point. • If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency. MOTOROLA 8 TIMING SOLUTIONS BR1333 — Rev 6 MC88915 50 MHz SIGNAL 12.5 MHz FEEDBACK SIGNAL HIGH LOW 12.5 MHz INPUT CRYSTAL OSCILLATOR EXTERNAL LOOP FILTER RST Q5 FEEDBACK REF_SEL Q4 SYNC[0] MC88915 ANALOG VCC Q3 RC1 ANALOG GND Q2 FQ_SEL Q0 1:2 Input to “Q” Output Frequency Relationship 2X_Q Q/2 25MHz “Q” CLOCK OUTPUTS Q1 PLL_EN Allowable Input Frequency Range: 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) 2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW) HIGH HIGH In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The “Q” outputs (Q0–Q4, Q5) will always run at 2X the Q/2 frequency, and the 2X_Q output will run at 4X the Q/2 frequency. Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back 50 MHz SIGNAL 25 MHz FEEDBACK SIGNAL HIGH LOW CRYSTAL OSCILLATOR 25 MHZ INPUT EXTERNAL LOOP FILTER RST Q5 FEEDBACK REF_SEL Q4 2X_Q Q/2 SYNC[0] MC88915 ANALOG VCC Q3 RC1 ANALOG GND Q2 FQ_SEL Q0 1:1 Input to “Q” Output Frequency Relationship 12.5 MHz SIGNAL In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up 25MHz the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the “Q” outputs) will “Q” CLOCK equal the SYNC frequency. The Q/2 output will alOUTPUTS ways run at 1/2 the “Q” frequency, and the 2X_Q output will run at 2X the “Q” frequency. Q1 PLL_EN Allowable Input Frequency Range: 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW) HIGH HIGH Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back 50 MHz FEEDBACK SIGNAL HIGH RST LOW CRYSTAL OSCILLATOR 50 MHz INPUT EXTERNAL LOOP FILTER Q4 Q5 FEEDBACK REF_SEL MC88915 SYNC[0] ANALOG VCC RC1 ANALOG GND FQ_SEL HIGH Q0 2X_Q Q/2 2:1 Input to “Q” Output Frequency Relationship 12.5 MHz SIGNAL Q3 25MHz “Q” CLOCK OUTPUTS Q2 Q1 PLL_EN In this application, the 2X_Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2X_Q and SYNC, thus the 2X_Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2X_Q frequency, and the “Q” outputs will run at 1/2 the 2X_Q frequency. Allowable Input Frequency Range: HIGH 20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW) Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back TIMING SOLUTIONS BR1333 — Rev 6 9 MOTOROLA MC88915 BOARD VCC 47Ω 10µF LOW FREQ BYPASS 0.1µF HIGH FREQ BYPASS 470KΩ 8 ANALOG VCC 9 RC1 10 ANALOG GND 330Ω 0.1µF (LOOP FILTER CAP) ANALOG LOOP FILTER/VCO SECTION OF THE MC88915 28–PIN PLCC PACKAGE (NOT DRAWN TO SCALE) 47Ω BOARD GND A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88915 IN A NORMAL DIGITAL ENVIRONMENT. Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915 Notes Concerning Loop Filter and Board Layout Issues 1. Figure 6 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter–free operation: is to give the 88915 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c.There are no special requirements set forth for the loop filter resistors (470K and 330Ω). The loop filter capacitor (0.1µF) can be a ceramic chip capacitior, the same as a standard bypass capacitor. 1a.All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1d.The 470K reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead–band. If the VCO (2X_Q output) is running above 40MHz, the 470K resistor provides the correct amount of current injection into the charge pump (2–3µA). If the VCO is running below 40MHz, a 1MΩ reference resistor should be used (instead of 470K). 1b.The 47Ω resistors, the 10µF low frequency bypass capacitor, and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915’s sensitivity to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100pS phase deviation on the 88915 outputs. A 250mV step deviation on VCC using the recommended filter values should cause no more than a 250pS phase deviation; if a 25µF bypass capacitor is used (instead of 10µF) a 250mV VCC step should cause no more than a 100pS phase deviation. 2. In addition to the bypass capacitors used in the analog filter of Figure 6, there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88915 outputs, in addition to reducing potential for noise in the ‘analog’ section of the chip. These bypass capacitors should also be tied as close to the 88915 package as possible. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88915’s digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 6 MOTOROLA 10 TIMING SOLUTIONS BR1333 — Rev 6 MC88915 CMMU CMMU CPU CMMU CMMU CMMU CMMU CMMU CPU CMMU CMMU CMMU MC88915 CPU CARD PLL CLOCK @f 2f SYSTEM CLOCK SOURCE CPU CARD MC88915 PLL DISTRIBUTE CLOCK @ f 2f CLOCK @ 2f AT POINT OF USE PLL MEMORY CONTROL 2f MEMORY CARDS CLOCK @ 2f AT POINT OF USE Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915 for Frequency Multiplication and Low Board–to–Board Skew MC88915 System Level Testing Functionality When the PLL_EN pin is low, the VCO is disabled and the 88915 is in low frequency “test mode”. In test mode (with FREQ_SEL high), the 2X_Q output is inverted from the selected SYNC input, and the “Q” outputs are divide–by–2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide–by–4. With FREQ_SEL low the 2X_Q output is divide–by–2 of the SYNC, the “Q” outputs divide–by–4, and the Q/2 output divide–by–8. These relationships can be seen on the block diagram. A recommended test configuration would be to use SYNC0 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. When these inputs are low, the 88915 is in test mode and the SYNC0 input is selected. This functionality is needed since most board–level testers run at 1 MHz or below, and the 88915 cannot lock onto that low of an input frequency. In the test mode described above, any frequency test signal can be used. TIMING SOLUTIONS BR1333 — Rev 6 11 MOTOROLA MC88915 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B T L–M M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA 0.007 (0.180) 12 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– TIMING SOLUTIONS BR1333 — Rev 6 MC88915 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 TIMING SOLUTIONS BR1333 — Rev 6 ◊ 13 MC88915/D MOTOROLA