MC88915TFN160

 SEMICONDUCTOR TECHNICAL DATA # #    "  !! 55, 70, 100, 133 and 160MHz Versions Order Number: MC88915T/D Rev 5, 08/2001            The MC88915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. For a 3.3V version, see the MC88LV915T data sheet. The PLL allows the high current, low skew outputs to lock onto a single LOW SKEW CMOS clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915T to multiply a PLL CLOCK DRIVER low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 7). Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2. The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1 and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version). In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see detailed description on page 11). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse. A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a SYNC signal and full 5V VCC. Features • Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input • The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t PD specification, which defines the part–to–part skew) • Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available • Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version) • Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available • All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL–level compatible. ±88mA IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge • Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3–state) for board test purposes • Lock Indicator (LOCK) accuracy indicates a phase–locked state Yield Surface Modeling and YSM are trademarks of Motorola, Inc.  Motorola, Inc. 2001  Pinout: 28–Lead PLCC (Top View) % ()* ,   ' $ ' , .3'     !   ' (3)"   $ )/$12   ' ,$  , (   ' $$   $ )/$12   "%!   ('3)" $  '     , ' $ &""3$ FN SUFFIX PLASTIC PLCC CASE 776–02 PIN SUMMARY 2 !59 -81 @8  )/$12 )/$12 (3)" ('3)" ! ( ' ' J3' ' "%! % ()* &""3$ ,$               @BGF @BGF @BGF @BGF @BGF @BGF %GFBGF %GFBGF %GFBGF %GFBGF %GFBGF @BGF @BGF @9/?5:9 (898D8@68 6>A6= A6= 8E ,% @F8D@4> D8CG8@6K >AI 887546= ( @8FIAD= >A6= AGFBGF >A6=87 FA EK@6 @H8DE8 A9 6>A6= AGFBGF J 6>A6= AGFBGF ' 9D8CG8@6K EK@6;DA@AGE >A6= AGFBGF' 9D8CG8@6K ÷ EK@6;DA@AGE @7A6= ;4E 588@ 46;8 EK@6;DA@AGE D8E8F 46FAI 8E B;4E8>A6= 9AD >AI 9D8C F8EFA6= @BGF Rp Rp = 1.5 Zo Figure 1. MC68040 P–Clock Input Termination Scheme Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations. HIGH Q/2 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAX Spec) Phase Relationships of the “Q” Outputs to Rising SYNC Edge 0° HIGH Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 0° HIGH Q5 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 180° HIGH 2X_Q 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 0° LOW Q/2 2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec) 0° LOW Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAX Spec) 0° LOW Q5 5 to (2X_Q FMAX Spec)/4 20 to (2X_Q FMAXSpec) 180° LOW 2X_Q 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAXSpec) 0° FREQ_SEL Level Feedback Output Allowable SYNC Input Frequency Range (MHZ) 4. A 1MΩ resistor tied to either Analog VCC or Analog GND as shown in Figure 2 is required to ensure no jitter is present on the MC88915T outputs. This technique causes a phase offset between the SYNC input and the output connected to the FEEDBACK input, measured at the input pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by 12 Corresponding VCO Frequency Range measuring the phase relationship for the 14 lots described in note 1 while the part was in phase–locked operation. The actual measurements were made with a 10MHz SYNC input (1.0ns edge rate from 0.8V – 2.0V) with the Q/2 output fed back. The phase measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. MOTOROLA $"% , #Ω (($ () )*%( Ω ( .*($" "%%&  "*( Ω  µ ( #Ω (($ () )*%(   µ $"% $ ( (  $"% $ - 4>N %+*&+*) I4KE DG@ 4F  F;8 M' 9D8CG8@6K 4@7 F;8 .3' AGFBGF I> DG@ 4F . F;8 M' 9D8CG8@6K 77:B-.71 9;@? =1 4>I4KE DG@ 4F   F;8 .3' 9D8N M' $"% , CG8@6K 4@7 F;8 M' AGFBGFE I> DG@ 4F  F;8 .*($" "%! .3' 9D8CG8@6K "%%& ' ( %+*&+*)  "*( $"% $ 77:B-.71 9;@? =1