MC908JL3ECPE

MC68HC908JK1 MC68HRC908JK1 MC68HC908JK3 JC68HRC908JK3 MC68HC908JL3 MC68HRC908JL3 Technical Data M68HC08 Microcontrollers Rev. 1.1 MC68HC908JL3/H August 1, 2005 freescale.com Technical Data — MC68H(R)C908JL3 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 37 Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . 39 Section 5. Configuration Register (CONFIG) . . . . . . . . . 47 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 51 Section 7. System Integration Module (SIM) . . . . . . . . . 71 Section 8. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . 95 Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . 101 Section 10. Timer Interface Module (TIM) . . . . . . . . . . . 115 Section 11. Analog-to-Digital Converter (ADC) . . . . . . 137 Section 12. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . . 159 Section 14. Keyboard Interrupt Module (KBI). . . . . . . . 165 Section 15. Computer Operating Properly (COP) . . . . 173 Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 179 Section 17. Break Module (BREAK) . . . . . . . . . . . . . . . 183 Section 18. Electrical Specifications. . . . . . . . . . . . . . . 191 Section 19. Mechanical Specifications . . . . . . . . . . . . . 203 Section 20. Ordering Information . . . . . . . . . . . . . . . . . 207 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data List of Sections 3 List of Sections Technical Data 4 MC68H(R)C908JL3 — Rev. 1.1 List of Sections Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Section 2. Memory 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Section 3. Random-Access Memory (RAM) 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Section 4. FLASH Memory (FLASH) 4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Table of Contents 5 Table of Contents 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.8 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 46 Section 5. Configuration Register (CONFIG) 5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Section 6. Central Processor Unit (CPU) 6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8 Instruction Set Summary 6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Technical Data 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MC68H(R)C908JL3 — Rev. 1.1 Table of Contents Freescale Semiconductor Table of Contents Section 7. System Integration Module (SIM) 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 75 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 75 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 77 7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 79 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.4.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 80 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 80 7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . . 81 7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 87 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Table of Contents 7 Table of Contents 7.8.1 7.8.2 7.8.3 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .91 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . 92 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . 94 Section 8. Oscillator (OSC) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.3 X-tal Oscillator (MC68HC908xxx). . . . . . . . . . . . . . . . . . . . . . . 96 8.4 RC Oscillator (MC68HRC908xxx) . . . . . . . . . . . . . . . . . . . . . . 97 8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 98 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . . 98 8.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 98 8.5.4 X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . .98 8.5.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . 99 8.5.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . .99 8.5.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 100 Section 9. Monitor ROM (MON) 9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 9.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Technical Data 8 MC68H(R)C908JL3 — Rev. 1.1 Table of Contents Freescale Semiconductor Table of Contents 9.4.6 9.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Section 10. Timer Interface Module (TIM) 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 120 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .120 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 121 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 122 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 123 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . 127 10.10.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . 129 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 130 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 131 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . 135 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Table of Contents 9 Table of Contents Section 11. Analog-to-Digital Converter (ADC) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .142 11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 145 Section 12. I/O Ports 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.4 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.4.1 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 150 12.4.2 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . 151 12.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 153 Technical Data 10 MC68H(R)C908JL3 — Rev. 1.1 Table of Contents Freescale Semiconductor Table of Contents 12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 156 12.6.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 157 Section 13. External Interrupt (IRQ) 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 163 13.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 163 Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 169 14.4.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 170 14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 171 Section 15. Computer Operating Properly (COP) 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Table of Contents 11 Table of Contents 15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 176 15.5 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 178 Section 16. Low Voltage Inhibit (LVI) 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 16.5 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . 180 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Section 17. Break Module (BREAK) 17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Technical Data 12 MC68H(R)C908JL3 — Rev. 1.1 Table of Contents Freescale Semiconductor Table of Contents 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 186 17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .186 17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 186 17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 186 17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . . 187 17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 190 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 Section 18. Electrical Specifications 18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.6 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 194 18.7 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 18.8 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.9 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 197 18.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Table of Contents 13 Table of Contents Section 19. Mechanical Specifications 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.3 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.4 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.5 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.6 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Section 20. Ordering Information 20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Technical Data 14 MC68H(R)C908JL3 — Rev. 1.1 Table of Contents Freescale Semiconductor Technical Data — MC68H(R)C908JL3 List of Figures Figure Title 1-1 1-2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2-1 2-2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .30 4-1 4-2 4-3 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 40 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 45 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 46 5-1 5-2 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . . 48 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . . 49 6-1 6-2 6-3 6-4 6-5 6-6 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 56 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .74 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Page Technical Data List of Figures 15 List of Figures Figure Title Page 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 84 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . . 86 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . . 86 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . . 87 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . . 89 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . . 89 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . . 91 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . 94 8-1 8-2 X-tal Oscillator External Connections . . . . . . . . . . . . . . . . . . . . 96 RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . .97 9-1 9-2 9-3 9-4 9-5 9-6 9-7 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 106 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .113 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .118 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 122 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 127 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 130 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 131 TIM Channel Status and Control Registers (TSC0:TSC1) . . . 132 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 136 11-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11-3 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 142 Technical Data 16 MC68H(R)C908JL3 — Rev. 1.1 List of Figures Freescale Semiconductor List of Figures Figure Title Page 11-4 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11-5 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . . 145 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .148 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 150 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . 152 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 153 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 156 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . 157 13-1 13-2 13-3 13-4 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 161 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .161 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 163 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . 164 14-1 14-2 14-3 14-4 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . 166 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 169 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 170 15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . 176 15-3 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 177 16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .180 16-2 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . 180 16-3 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . 181 17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 185 17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 185 17-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 187 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data List of Figures 17 List of Figures Figure Title 17-4 17-5 17-6 17-7 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 188 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 188 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 188 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . 190 18-1 18-2 18-3 18-4 18-5 RC vs. Frequency (5V @25°C) . . . . . . . . . . . . . . . . . . . . . . .196 RC vs. Frequency (3V @25°C) . . . . . . . . . . . . . . . . . . . . . . .199 Typical Operating IDD, with All Modules Turned On (25 °C) . 200 Typical Wait Mode IDD, with ADC Turned On (25 °C) . . . . . . 200 Typical Stop Mode IDD, with all Modules Disabled (25 °C) . . 200 19-1 19-2 19-3 19-4 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .205 Technical Data 18 Page MC68H(R)C908JL3 — Rev. 1.1 List of Figures Freescale Semiconductor Technical Data — MC68H(R)C908JL3 List of Tables Table Title Page 1-1 1-2 Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6-1 6-2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7-1 7-2 7-3 7-4 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 Monitor Mode Entry Requirements and Options. . . . . . . . . . . 104 Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . . 107 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 107 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 110 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 110 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 111 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 111 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 112 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 112 10-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 134 11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data List of Tables 19 List of Tables Table Title Page 12-1 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12-2 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12-3 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DC Electrical Characteristics (5V) . . . . . . . . . . . . . . . . . . . . . 194 Control Timing (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Oscillator Component Specifications (5V) . . . . . . . . . . . . . . . 196 DC Electrical Characteristics (3V) . . . . . . . . . . . . . . . . . . . . . 197 Control Timing (3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Oscillator Component Specifications (3V) . . . . . . . . . . . . . . . 199 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Technical Data 20 MC68H(R)C908JL3 — Rev. 1.1 List of Tables Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.2 Introduction The MC68H(R)C908JL3 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. Table 1-1. Summary of Device Variations Device FLASH Memory Size Pin Count MC68H(R)C908JL3 4096 bytes 28 pins MC68H(R)C908JK3 4096 bytes 20 pins MC68H(R)C908JK1 1536 bytes 20 pins All references to the MC68H(R)C908JL3 in this data book apply equally to the MC68H(R)C908JK3 and MC68H(R)C908JK1, unless otherwise stated. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data General Description 21 General Description 1.3 Features Features of the MC68H(R)C908JL3 include the following: • High-performance M68HC08 architecture • Fully upward-compatible object code with M6805, M146805, and M68HC05 Families • Low-power design; fully static with stop and wait modes • 5V and 3V operating voltages • 8MHz internal bus operation • RC-oscillator circuit or crystal-oscillator options • In-system FLASH programming • FLASH security1 • User FLASH memory – 4096 bytes for MC68H(R)C908JL3/JK3 – 1536 bytes for MC68H(R)C908JK1 • 128 bytes of on-chip random-access memory (RAM) • 2-channel, 16-bit timer interface module (TIM) • 12-channel, 8-bit analog-to-digital converter (ADC) • 23 general purpose I/O ports for MC68H(R)C908JL3: – 7 keyboard interrupt with internal pull-up – 10 LED drivers – 2 × 25mA open-drain I/O with pull-up – 2 ICAP/OCAP/PWM • 15 general purpose I/O ports for MC68H(R)C908JK3/JK1: – 1 keyboard interrupt with internal pull-up (with RC oscillator option selected) – 4 LED drivers – 2 × 25mA open-drain I/O with pull-up – 2 ICAP/OCAP/PWM 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 22 MC68H(R)C908JL3 — Rev. 1.1 General Description Freescale Semiconductor General Description • System protection features: – Optional computer operating properly (COP) reset – Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation. – Illegal opcode detection with reset – Illegal address detection with reset • Master reset pin with internal pull-up and power-on reset • IRQ1 with programmable pull-up and schmitt-trigger input • 28-pin PDIP and 28-pin SOIC packages for MC68H(R)C908JL3 • 20-pin PDIP and 20-pin SOIC packages for MC68H(R)C908JK3/JK1 Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.4 MCU Block Diagram Figure 1-1 shows the structure of the MC68H(R)C908JL3. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data General Description 23 DDRA PTA PTA/KBI[0:6] PTB[0:7] PTD PTB DDRD DDRB CPU CONTROL ALU X-TAL OSCILLATOR OR RC-OSCILLATOR VDD VSS OSC2/RCCLK/PTA6 OSC1 68HC08 CPU ACCUM CPU REGISTERS INDEX REG SYSTEM INTEGRATION MODULE RST MODE SELECT MODULE IRQ1 General Description STK PNTR 8-BIT ADC ADC[0:7]/ PTB[0:7] ADC[11:8]/ PTD[0:3] POWER SUPPLY AND VOLTAGE REGULATOR PROGRAM COUNTER COND CODE REG V 1 1 H I N Z C BREAK MODULE POWER-ON RESET MODULE TCH0/PTD4 16-BIT TIMER MODULE 128 BYTES RAM MC68H(R)C908JL3/JK3: 4096 BYTES MC68H(R)C908JK1: 1536 BYTES USER FLASH MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor RST, IRQ1: PIN HAS INTERNAL 30K PULL-UP PTD[6:7]: PINS HAVE 25mA OPEN-DRAIN OUTPUT & PROGRAMMABLE 5K PULL-UP PTA[0:5], PTD[2:3], PTD[6:7]: PIN HAS LED DRIVE PTA[0:6]: PINS HAVE PROGRAMMABLE KEYBOARD INTERRUPT AND PULL-UP PTA[0:5] and PTD[0:1]: NOT AVAILABLE ON 20-PIN DEVICES – MC68H(R)C908JK3/JK1 Figure 1-1. MCU Block Diagram COP MODULE MONITOR ROM 960 BYTES TCH1/PTD5 General Description Technical Data 24 PTD[0:7] General Description 1.5 Pin Assignments The MC68H(R)C908JL3 is available in 28-pin packages and the MC68H(R)C908JK3/JK1 in 20-pin packages. Figure 1-2 shows the pin assignment for the two packages. IRQ1 1 28 RST PTA0 2 27 PTA5 VSS 3 26 PTD4 OSC1 4 25 PTD5 OSC2/PTA6 5 24 PTD2 IRQ1 1 20 RST PTA1 6 23 PTA4 VSS 2 19 PTD4 VDD 7 22 PTD3 OSC1 3 18 PTD5 PTA2 8 21 PTB0 OSC2/PTA6 4 17 PTD2 PTA3 9 20 PTB1 VDD 5 16 PTD3 PTB7 10 19 PTD1 PTB7 6 15 PTB0 PTB6 11 18 PTB2 PTB6 7 14 PTB1 PTB5 12 17 PTB3 PTB5 8 13 PTB2 PTD7 13 16 PTD0 PTD7 9 12 PTB3 PTD6 14 15 PTB4 10 11 PTB4 28-PIN ASSIGNMENT MC68H(R)C908JL3 PTD6 20-PIN ASSIGNMENT MC68H(R)C908JK3/JK1 Pins not bonded out on 20-pin package: PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, PTD1. Figure 1-2. MCU Pin Assignments MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data General Description 25 General Description 1.6 Pin Functions Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL In 5V or 3V Out 0V VDD Power supply. VSS Power supply ground RST RESET input, active low. With Internal pull-up and schmitt trigger input. Input VDD IRQ1 External IRQ pin. With software programmable internal pull-up and schmitt trigger input. This pin is also used for mode entry selection. Input VDD to VDD+VHI OSC1 X-tal or RC oscillator input. In Analog Out Analog For RC oscillator option: Default is RCCLK output. Shared with PTA6/KBI6, with programmable pull-up. In/Out VDD 7-bit general purpose I/O port. In/Out VDD Shared with 7 keyboard interrupts KBI[0:6]. In VDD Each pin has programmable internal pull-up device. In VDD In/Out VDD In Analog 8-bit general purpose I/O port. In/Out VDD PTD[3:0] shared with 4 ADC inputs, ADC[8:11]. Input Analog PTD[4:5] shared with TIM channels, TCH0 and TCH1. In/Out VDD PTD[6:7] can be configured as 25mA open-drain output with pull-up. In/Out VDD For X-tal oscillator option: X-tal oscillator output, this is the inverting OSC1 signal. OSC2 PTA[0:6] 8-bit general purpose I/O port. PTB[0:7] Shared with 8 ADC inputs, ADC[0:7]. PTD[0:7] NOTE: On the 20-pin package, the following pins are not available: PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1. Technical Data 26 MC68H(R)C908JL3 — Rev. 1.1 General Description Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 2. Memory 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 4096 bytes of user FLASH for MC68H(R)C908JL3/JK3 1536 bytes of user FLASH for MC68H(R)C908JK1 • 128 bytes of RAM • 48 bytes of user-defined vectors • 960 bytes of Monitor ROM MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Memory 27 Memory $0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $007F RESERVED 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $EBFF UNIMPLEMENTED 60160 BYTES $EC00 ↓ $FBFF FLASH MEMORY MC68H(R)C908JL3/JK3 4096 BYTES $FC00 ↓ $FDFF MONITOR ROM 512 BYTES $FE00 BREAK STATUS REGISTER (BSR) $FE01 RESET STATUS REGISTER (RSR) $FE02 RESERVED (UBAR) $FE03 BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 FLASH BLOCK PROTECT REGISTER (FLBPR) $FE0A RESERVED $FE0B RESERVED $FE0C BREAK ADDRESS HIGH REGISTER (BRKH) $FE0D BREAK ADDRESS LOW REGISTER (BRKL) $FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0F RESERVED $FE10 ↓ $FFCF MONITOR ROM 448 BYTES $FFD0 ↓ $FFFF USER VECTORS 48 BYTES UNIMPLEMENTED 62720 BYTES $0100 ↓ $F5FF FLASH MEMORY MC68H(R)C908JK1 1536 BYTES $F600 ↓ $FBFF Figure 2-1. Memory Map Technical Data 28 MC68H(R)C908JL3 — Rev. 1.1 Memory Freescale Semiconductor Memory 2.3 I/O Section Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: • $FE00 (Break Status Register, BSR) • $FE01 (Reset Status Register, RSR) • $FE02 (Reserved, SUBAR) • $FE03 (Break Flag Control Register, BFCR) • $FE04 (Interrupt Status Register 1, INT1) • $FE05 (Interrupt Status Register 2, INT2) • $FE06 (Interrupt Status Register 3, INT3) • $FE07 (Reserved) • $FE08 (FLASH Control Register, FLCR) • $FE09 (FLASH Block Protect Register, FLBPR) • $FE0A (Reserved) • $FE0B (Reserved) • $FE0C (Break Address Register High, BRKH) • $FE0D (Break Address Register Low, BRKL) • $FE0E (Break Status and Control Register, BRKSCR) • $FE0F (Reserved) • $FFFF (COP Control Register, COPCTL) 2.4 Monitor ROM The 960 bytes at addresses $FC00–$FDFF and $FE10–$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Section 9. Monitor ROM (MON).) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Memory 29 Memory Addr. Register Name $0000 Read: Port A Data Register Write: (PTA) Reset: $0001 Bit 7 Read: Port B Data Register Write: (PTB) Reset: 0 6 5 4 3 2 1 Bit 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTD2 PTD1 PTD0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 Unaffected by reset Read: $0002 Unimplemented Write: $0003 Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A $0004 Write: (DDRA) Reset: PTD7 PTD6 PTD5 PTD4 PTD3 Unaffected by reset 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read: DDRB7 Data Direction Register B $0005 Write: (DDRB) Reset: 0 Read: Unimplemented Write: $0006 Read: DDRD7 Data Direction Register D $0007 Write: (DDRD) Reset: 0 Read: $0008 ↓ $0009 Unimplemented Write: $000A Read: Port D Control Register Write: (PDCR) Reset: = Unimplemented SLOWD7 SLOWD6 PTDPU7 0 R 0 0 PTDPU6 0 = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5) Technical Data 30 MC68H(R)C908JL3 — Rev. 1.1 Memory Freescale Semiconductor Memory Addr. $000B ↓ $000C $000D $000E ↓ $0019 $001A $001B $001C $001D $001E $001F Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Unimplemented Write: Read: Port A Input Pull-up PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Enable Register Write: (PTAPUE) Reset: 0 0 0 0 0 0 0 0 Read: Unimplemented Write: Read: Keyboard Status and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset: 0 0 0 0 KEYF 0 ACKK 0 IMASKK MODEK 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 0 0 0 0 IRQF1 0 IMASK1 MODE1 0 Read: Unimplemented Write: Read: IRQ Status and Control Register Write: (INTSCR) Reset: ACK1 0 Read: IRQPUD Configuration Register 2 Write: † (CONFIG2) Reset: 0 Read: COPRS Configuration Register 1 Write: (CONFIG1)† Reset: 0 0 0 0 0 0 0 0 R R LVIT1 LVIT0 R R R 0 0 0* 0* 0 0 0 R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 PS2 PS1 PS0 0 0 0 † One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only. $0020 Read: TIM Status and Control Register Write: (TSC) Reset: TOF 0 0 TOIE TSTOP 0 1 = Unimplemented 0 0 TRST 0 0 R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Memory 31 Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 $0021 Read: TIM Counter Register High Write: (TCNTH) Reset: 0 0 0 0 0 0 0 0 Read: TIM Counter Register Low Write: (TCNTL) Reset: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 $0022 $0023 $0024 Read: TIM Counter Modulo Register High Write: (TMODH) Reset: Read: TIM Counter Modulo Register Low Write: (TMODL) Reset: Read: TIM Channel 0 Status and $0025 Control Register Write: (TSC0) Reset: $0026 $0027 Read: TIM Channel 0 Register High Write: (TCH0H) Reset: Read: TIM Channel 0 Register Low Write: (TCH0L) Reset: Read: TIM Channel 1 Status and $0028 Control Register Write: (TSC1) Reset: $0029 $002A Read: TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset: CH0F 0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset CH1F 0 CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5) Technical Data 32 MC68H(R)C908JL3 — Rev. 1.1 Memory Freescale Semiconductor Memory Addr. $002B ↓ $003B $003C $003D Register Name Bit 7 $FE00 5 4 3 2 1 Bit 0 AIEN ADCO CH4 CH3 CH2 CH1 CH0 0 0 0 1 1 1 1 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Read: Unimplemented Write: Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset: Read: ADC Input Clock Register Write: $003E (ADICLK) Reset: $003F 6 COCO Indeterminate after reset 0 0 0 0 0 0 0 0 0 0 0 R R R R ADIV2 ADIV1 ADIV0 0 0 R R Read: Unimplemented Write: Read: Break Status Register Write: (BSR) Reset: SBSW See note R 0 Note: Writing a logic 0 clears SBSW. $FE01 Read: Reset Status Register Write: (RSR) POR: Read: $FE02 Reserved Write: $FE03 Read: Break Flag Control Register Write: (BFCR) Reset: Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 R R R R R R R R BCFE R R R R R R R 0 IF5 IF4 IF3 0 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 0 = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Memory 33 Memory Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: IF14 0 0 0 0 0 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Read: Interrupt Status Register 3 Write: $FE06 (INT3) Reset: 0 0 0 0 0 0 0 IF15 R R R R R R R R 0 0 0 0 0 0 0 0 R R R R R R R R 0 0 0 0 HVEN MASS ERASE PGM 0 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 0 0 0 0 0 0 0 0 R R R R R R R R Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read: $FE07 Reserved Write: $FE08 Read: FLASH Control Register Write: (FLCR) Reset: $FE09 Read: FLASH Block Protect Write: Register (FLBPR) Reset: Read: $FE0A ↓ $FE0B Reserved Write: $FE0C Read: Break Address High Register Write: (BRKH) Reset: $FE0D Read: Break Address low Register Write: (BRKL) Reset: Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: $FFFF Read: COP Control Register Write: (COPCTL) Reset: 0 Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5) Technical Data 34 MC68H(R)C908JL3 — Rev. 1.1 Memory Freescale Semiconductor Memory . Table 2-1. Vector Addresses Vector Priority Lowest Vector IF15 IF14 Address Vector $FFDE ADC Conversion Complete Vector (High) $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) $FFE1 Keyboard Vector (Low) IF13 to IF6 IF5 IF4 IF3 — $FFF2 TIM Overflow Vector (High) $FFF3 TIM Overflow Vector (Low) $FFF4 TIM Channel 1 Vector (High) $FFF5 TIM Channel 1 Vector (Low) $FFF6 TIM Channel 0 Vector (High) $FFF7 TIM Channel 0 Vector (Low) IF2 IF1 — Highest — — Not Used $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High) $FFFF Reset Vector (Low) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Not Used Technical Data Memory 35 Memory Technical Data 36 MC68H(R)C908JL3 — Rev. 1.1 Memory Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 Introduction This section describes the 128 bytes of RAM. 3.3 Functional Description Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Random-Access Memory (RAM) 37 Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 38 MC68H(R)C908JL3 — Rev. 1.1 Random-Access Memory (RAM) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 4. FLASH Memory (FLASH) 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.8 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.9 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.2 Introduction This section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68H(R)C908JL3/JK3: 4096 bytes user FLASH from $EC00 – $FBFF. MC68H(R)C908JK1: 1536 bytes user FLASH from $F600 – $FBFF. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data FLASH Memory (FLASH) 39 FLASH Memory (FLASH) 4.3 Functional Description The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: NOTE: • $EC00 – $FBFF; user memory, 4096 bytes: MC68H(R)C908JL3/JK3 • $F600 – $FBFF; user memory, 1536 bytes: MC68H(R)C908JK1 • $FFD0 – $FFFF; user interrupt vectors, 48 bytes. An erased bit reads as logic 1 and a programmed bit reads as logic 0. A security feature prevents viewing of the FLASH contents.1 4.4 FLASH Control Register The FLASH Control Register controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Figure 4-1. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM=1 or ERASE=1 and the proper sequence for program or erase is followed. 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 40 MC68H(R)C908JL3 — Rev. 1.1 FLASH Memory (FLASH) Freescale Semiconductor FLASH Memory (FLASH) 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or block erase operation when the ERASE bit is set. 1 = Mass Erase operation selected 0 = Block Erase operation selected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM — Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected 4.5 FLASH Block Erase Operation Use the following procedure to erase a block of FLASH memory. A block consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte User Interrupt Vectors area also forms a block. Any block within the 4K bytes User Memory area ($EC00–$FBFF) can be erased alone. The 48-byte User Interrupt Vector blocks can not be erased alone due to security concern. Mass erase is required to erase this block. 1. Set the ERASE bit and clear the MASS bit in the FLASH Control Register. 2. Write any data to any FLASH location within the address range of the block to be erased. 3. Wait for a time, tnvs (10µs). 4. Set the HVEN bit. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data FLASH Memory (FLASH) 41 FLASH Memory (FLASH) 5. Wait for a time tERASE (1ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh (5µs). 8. Clear the HVEN bit. 9. After time, trcv (1µs), the memory can be accessed in read mode again. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 4.6 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH Control Register. 2. Write any data to any FLASH location within the FLASH memory address range. 3. Wait for a time, tnvs (10µs). 4. Set the HVEN bit. 5. Wait for a time tERASE (4ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh1 (100µs). 8. Clear the HVEN bit. 9. After time, trcv (1µs), the memory can be accessed in read mode again. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Technical Data 42 MC68H(R)C908JL3 — Rev. 1.1 FLASH Memory (FLASH) Freescale Semiconductor FLASH Memory (FLASH) 4.7 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of FLASH memory: (Figure 4-2 shows a flowchart of the programming algorithm.) NOTE: In order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any FLASH location within the address range of the row to be programmed. 3. Wait for a time, tnvs (10µs). 4. Set the HVEN bit. 5. Wait for a time, tpgs (5µs). 6. Write data to the byte being programmed. 7. Wait for time, tPROG (30µs). 8. Repeat step 6 and 7 until all the bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (5µs). 11. Clear the HVEN bit. 12. After time, trcv (1µs), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data FLASH Memory (FLASH) 43 FLASH Memory (FLASH) NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 6 to step 10), must not exceed the maximum programming time, tPROG max. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 4.8 FLASH Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH Block Protect Register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. Technical Data 44 MC68H(R)C908JL3 — Rev. 1.1 FLASH Memory (FLASH) Freescale Semiconductor FLASH Memory (FLASH) 1 Set PGM bit Algorithm for programming a row (32 bytes) of FLASH memory 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, tnvs 4 Set HVEN bit 5 Wait for a time, tpgs 6 7 Write data to the FLASH address to be programmed Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG max. 9 Clear PGM bit 10 Wait for a time, tnvh 11 Clear HVEN bit 12 Wait for a time, trcv This row program algorithm assumes the row/s to be programmed are initially erased. End of Programming Figure 4-2. FLASH Programming Flowchart MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data FLASH Memory (FLASH) 45 FLASH Memory (FLASH) 4.9 FLASH Block Protect Register The FLASH Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory. Address: Read: Write: Reset: $FE09 Bit 7 6 5 4 3 2 1 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 0 0 0 0 0 0 0 Bit 0 0 0 Figure 4-3. FLASH Block Protect Register (FLBPR) BPR[7:1], bit-0 — FLASH Protection Register Bits [7:1] These eight bits in FLBPR (bit-0 is always 0) represent bits [12:5] of a 16-bit memory address. Bits [15:13] are logic 1s and bits [4:0] are logic 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH memory. Examples of protect start address: BPR[7:0] Start of Address of Protect Range $00–$60 The entire FLASH memory is protected. $62 (0110 0010) $EC40 (1110 1100 0100 0000) $64 (0110 0100) $EC80 (1110 1100 1000 0000) $68 (0110 1000) $ED00 (1110 1101 0000 0000) and so on... $DE (1101 1110) $FBC0 (1111 1011 1100 0000) $FE (1111 1110) $FFC0 (1111 1111 1100 0000) $FF The entire FLASH memory is not protected. Technical Data 46 MC68H(R)C908JL3 — Rev. 1.1 FLASH Memory (FLASH) Freescale Semiconductor FLASH Memory (FLASH) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data FLASH Memory (FLASH) 47 FLASH Memory (FLASH) Technical Data 48 MC68H(R)C908JL3 — Rev. 1.1 FLASH Memory (FLASH) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5.2 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options: • Stop mode recovery time (32 × 2OSCOUT cycles or 4096 × 2OSCOUT cycles) • STOP instruction • Computer operating properly module (COP) • COP reset period (COPRS), (213 –24) × 2OSCOUT or (218 –24) × 2OSCOUT • Enable LVI circuit • Select LVI trip voltage MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Configuration Register (CONFIG) 47 Configuration Register (CONFIG) 5.3 Functional Description The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU it is recommended that this register be written immediately after reset. The configuration register is located at $001E and $001F, and may be read at anytime. NOTE: The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-1 and Figure 5-2. Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD R R LVIT1 LVIT0 R R R Reset: 0 0 0 0 0 0 POR: 0 0 0 0 0 0 Read: Write: R Not affected Not affected 0 0 = Reserved Figure 5-1. Configuration Register 2 (CONFIG2) IRQPUD — IRQ1 Pin Pull-up control bit 1 = Internal Pull-up is disconnected 0 = Internal Pull-up is connected between IRQ1 pin and VDD LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in Section 16. Technical Data 48 MC68H(R)C908JL3 — Rev. 1.1 Configuration Register (CONFIG) Freescale Semiconductor Configuration Register (CONFIG) Address: $001F Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 R = Reserved Figure 5-2. Configuration Register 1 (CONFIG1) COPRS —þCOP reset period selection bit 1 = COP reset cycle = (213 – 24) × 2OSCOUT 0 = COP reset cycle = (218 – 24) × 2OSCOUT LVID —þLow Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 × OSCXCLK cycles instead of a 4096 × 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 × 2OSCOUT cycles 0 = Stop mode recovery after 4096 × 2OSCOUT cycles NOTE: Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. (See Section 15. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Configuration Register (CONFIG) 49 Configuration Register (CONFIG) Technical Data 50 MC68H(R)C908JL3 — Rev. 1.1 Configuration Register (CONFIG) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8 Instruction Set Summary 6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Central Processor Unit (CPU) 51 Central Processor Unit (CPU) 6.3 Features • Object code fully upward-compatible with M68HC05 Family • 16-bit stack pointer with stack manipulation instructions • 16-bit index register with x-register manipulation instructions • 8-MHz CPU internal bus frequency • 64-Kbyte program/data memory space • 16 addressing modes • Memory-to-memory data moves without using accumulator • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 6.4 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. Technical Data 52 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) 7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 0 15 STACK POINTER (SP) 0 15 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 6-2. Accumulator (A) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Central Processor Unit (CPU) 53 Central Processor Unit (CPU) 6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 6-3. Index Register (H:X) 6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Technical Data 54 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 6-4. Stack Pointer (SP) NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF Figure 6-5. Program Counter (PC) 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Central Processor Unit (CPU) 55 Central Processor Unit (CPU) 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 6-6. Condition Code Register (CCR) V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 Technical Data 56 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N — Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Central Processor Unit (CPU) 57 Central Processor Unit (CPU) C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 6.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 6.6.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Technical Data 58 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) 6.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 6.7 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. 6.8 Instruction Set Summary 6.9 Opcode Map See Table 6-2. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Central Processor Unit (CPU) 59 Central Processor Unit (CPU) V H I N Z C ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP A ← (A) + (M) + (C) Add with Carry ↕ ↕ IMM DIR EXT IX2 – ↕ ↕ ↕ IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff IMM DIR EXT IX2 – ↕ ↕ ↕ IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP Add without Carry AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) – – – – – – IMM AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right BCC rel Branch if Carry Bit Clear C C PC ← (PC) + 2 + rel ? (C) = 0 Mn ← 0 Technical Data 60 ff ee ff 2 3 4 4 3 2 4 5 A7 ii 2 AF ii 2 2 3 4 4 3 2 4 5 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 38 48 58 68 78 9E68 dd DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 37 47 57 67 77 9E67 dd ff 4 1 1 4 3 5 – – – – – – REL 24 rr 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) – – – – – – DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 ↕ b0 b0 2 3 4 4 3 2 4 5 IMM DIR EXT IX2 – IX1 IX SP1 SP2 0 – – ↕ ↕ 0 b7 b7 Clear Bit n in M ↕ ↕ A ← (A) & (M) Logical AND ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCLR n, opr A ← (A) + (M) ff ee ff Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary ↕ ff ee ff ff ff ff 4 1 1 4 3 5 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) Effect on CCR V H I N Z C Cycles Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 – – – – – – REL 27 rr 3 BGE opr Branch if Greater Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 – – – – – – REL 90 rr 3 BGT opr Branch if Greater Than (Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = – – – – – – REL 0 92 rr 3 BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3 BHS rel Branch if Higher or Same (Same as BCC) PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3 BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 – – – – – – REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL 2E rr 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 93 rr 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) BLO rel Branch if Lower (Same as BCS) BLS rel (A) & (M) 0 – – ↕ ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = – – – – – – REL 1 A5 B5 C5 D5 E5 F5 9EE5 9ED5 3 PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3 Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3 BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 – – – – – – REL 91 rr 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 – – – – – – REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 – – – – – – REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 – – – – – – REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel – – – – – – REL 20 rr 3 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Central Processor Unit (CPU) 61 Central Processor Unit (CPU) Table 6-1. Instruction Set Summary DIR (b0) DIR (b1) DIR (b2) DIR (b3) – – – – – ↕ DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 – – – – – – REL 21 rr 3 PC ← (PC) + 3 + rel ? (Mn) = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) – – – – – ↕ DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 Mn ← 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) – – – – – – DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 – – – – – – REL AD rr 4 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 Description V H I N Z C BRCLR n,opr,rel Branch if Bit n in M Clear BRN rel Branch Never BRSET n,opr,rel Branch if Bit n in M Set BSET n,opr BSR rel Set Bit n in M Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel PC ← (PC) + 3 + rel ? (Mn) = 0 PC ← (PC) + 2 PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel DIR PC ← (PC) + 3 + rel ? (A) – (M) = $00 IMM PC ← (PC) + 3 + rel ? (A) – (M) = $00 IMM PC ← (PC) + 3 + rel ? (X) – (M) = $00 – – – – – – IX1+ PC ← (PC) + 3 + rel ? (A) – (M) = $00 IX+ PC ← (PC) + 2 + rel ? (A) – (M) = $00 SP1 PC ← (PC) + 4 + rel ? (A) – (M) = $00 31 41 51 61 71 9E61 Cycles Operand Effect on CCR Opcode Operation Address Mode Source Form CLC Clear Carry Bit C←0 – – – – – 0 INH 98 1 CLI Clear Interrupt Mask I←0 – – 0 – – – INH 9A 2 M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 DIR INH INH 0 – – 0 1 – INH IX1 IX SP1 3F 4F 5F 8C 6F 7F 9E6F CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Technical Data 62 dd ff ff 3 1 1 1 3 2 4 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) V H I N Z C CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Compare A with M (A) – (M) COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A (H:X) – (M:M + 1) (X) – (M) (A)10 DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff DIR INH INH 1 IX1 IX SP1 33 43 53 63 73 9E63 dd 0 – – ↕ ↕ IMM DIR ↕ – – ↕ ↕ ↕ ↕ IMM DIR EXT IX2 – – ↕ ↕ ↕ IX1 IX SP1 SP2 U – – ↕ ↕ ↕ INH A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1 DIR PC ← (PC) + 3 + rel ? (result) ≠ 0 INH PC ← (PC) + 2 + rel ? (result) ≠ 0 – – – – – – INH PC ← (PC) + 2 + rel ? (result) ≠ 0 IX1 PC ← (PC) + 3 + rel ? (result) ≠ 0 IX PC ← (PC) + 2 + rel ? (result) ≠ 0 SP1 PC ← (PC) + 4 + rel ? (result) ≠ 0 M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1 A ← (H:A)/(X) H ← Remainder MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor ↕ IMM DIR EXT IX2 – – ↕ ↕ ↕ IX1 IX SP1 SP2 ↕ – – ↕ ↕ DIR INH INH – IX1 IX SP1 – – – – ↕ ↕ INH ff ee ff Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary 2 3 4 4 3 2 4 5 ff 4 1 1 4 3 5 65 75 ii ii+1 dd 3 4 A3 B3 C3 D3 E3 F3 9EE3 9ED3 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 ff ff ee ff 72 2 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr 3A 4A 5A 6A 7A 9E6A dd 52 ff ff 5 3 3 5 4 6 4 1 1 4 3 5 7 Technical Data Central Processor Unit (CPU) 63 Central Processor Unit (CPU) V H I N Z C EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Load A from M LDHX #opr LDHX opr Load H:X from M LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP DIR INH INH – IX1 IX SP1 3C 4C 5C 6C 7C 9E6C dd ff ee ff ff ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 PC ← Jump Address dd hh ll ee ff ff 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 2 3 4 4 3 2 4 5 A ← (M) 0 – – ↕ ↕ H:X ← (M:M + 1) X ← (M) C 0 b7 b0 Technical Data 64 – – ↕ ↕ ii dd hh ll ee ff ff BC CC DC EC FC Load X from M Logical Shift Left (Same as ASL) ↕ A8 B8 C8 D8 E8 F8 9EE8 9ED8 DIR EXT – – – – – – IX2 IX1 IX Jump Jump to Subroutine 0 – – ↕ ↕ M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1 Increment LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP A ← (A ⊕ M) Exclusive OR M with A IMM DIR EXT IX2 – IX1 IX SP1 SP2 Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary IMM DIR EXT IX2 – IX1 IX SP1 SP2 IMM DIR 45 55 0 – – ↕ ↕ – 0 – – ↕ ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 AE BE CE DE EE FE 9EEE 9EDE ii dd hh ll ee ff ff DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 38 48 58 68 78 9E68 dd ↕ ff ee ff ff ff 4 1 1 4 3 5 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) V H I N Z C LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right 0 C b7 MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr Move MUL Unsigned multiply ↕ b0 DIR INH INH – – 0 ↕ ↕ IX1 IX SP1 (M)Destination ← (M)Source 0 – – ↕ ↕ H:X ← (H:X) + 1 (IX+D, DIX+) X:A ← (X) × (A) DD DIX+ – IMD IX+D – 0 – – – 0 INH DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 34 44 54 64 74 9E64 4E 5E 6E 7E dd ff 4 1 1 4 3 5 dd dd dd ii dd dd 5 4 4 4 ff 42 30 40 50 60 70 9E60 Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary 5 dd 4 1 1 4 3 5 NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP Negate (Two’s Complement) NOP No Operation None – – – – – – INH 9D 1 NSA Nibble Swap A A ← (A[3:0]:A[7:4]) – – – – – – INH 62 3 M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) ↕ IMM DIR EXT IX2 – IX1 IX SP1 SP2 AA BA CA DA EA FA 9EEA 9EDA ff ff ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP Inclusive OR A and M PSHA Push A onto Stack Push (A); SP ← (SP) – 1 – – – – – – INH 87 2 PSHH Push H onto Stack Push (H); SP ← (SP) – 1 – – – – – – INH 8B 2 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 – – – – – – INH 89 2 PULA Pull A from Stack SP ← (SP + 1); Pull (A) – – – – – – INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) – – – – – – INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) – – – – – – INH 88 2 ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP Rotate Left through Carry A ← (A) | (M) 0 – – ↕ ↕ C ↕ b7 b0 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 39 49 59 69 79 9E69 ff ee ff dd ff ff 4 1 1 4 3 5 Technical Data Central Processor Unit (CPU) 65 Central Processor Unit (CPU) V H I N Z C DIR INH INH – – ↕ ↕ ↕ IX1 IX SP1 36 46 56 66 76 9E66 dd Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary 4 1 1 4 3 5 ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP Rotate Right through Carry RSP Reset Stack Pointer SP ← $FF – – – – – – INH 9C 1 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) ↕ ↕ ↕ ↕ ↕ ↕ INH 80 7 RTS Return from Subroutine SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL) – – – – – – INH 81 4 C b7 ↕ b0 IMM DIR EXT IX2 – – ↕ ↕ ↕ IX1 IX SP1 SP2 A2 B2 C2 D2 E2 F2 9EE2 9ED2 ff ff ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP Subtract with Carry SEC Set Carry Bit C←1 – – – – – 1 INH 99 1 SEI Set Interrupt Mask I←1 – – 1 – – – INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP Store A in M STHX opr Store H:X in M STOP Enable IRQ Pin; Stop Oscillator STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP Store X in M A ← (A) – (M) – (C) M ← (A) (M:M + 1) ← (H:X) I ← 0; Stop Oscillator M ← (X) Technical Data 66 ↕ DIR EXT IX2 – IX1 IX SP1 SP2 B7 C7 D7 E7 F7 9EE7 9ED7 – DIR 35 – – 0 – – – INH 8E 0 – – ↕ ↕ 0 – – ↕ ↕ 0 – – ↕ ↕ DIR EXT IX2 – IX1 IX SP1 SP2 BF CF DF EF FF 9EEF 9EDF ff ee ff ff ee ff 3 4 4 3 2 4 5 dd 4 dd hh ll ee ff ff 1 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Central Processor Unit (CPU) V H I N Z C SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Subtract A ← (A) – (M) ↕ IMM DIR EXT IX2 – – ↕ ↕ ↕ IX1 IX SP1 SP2 A0 B0 C0 D0 E0 F0 9EE0 9ED0 ii dd hh ll ee ff ff ff ee ff Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary 2 3 4 4 3 2 4 5 SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte TAP Transfer A to CCR CCR ← (A) ↕ ↕ ↕ ↕ ↕ ↕ INH 84 2 TAX Transfer A to X X ← (A) – – – – – – INH 97 1 TPA Transfer CCR to A A ← (CCR) – – – – – – INH 85 1 TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP Test for Negative or Zero TSX Transfer SP to H:X TXA Transfer X to A TXS Transfer H:X to SP (A) – $00 or (X) – $00 or (M) – $00 83 9 0 – – ↕ ↕ DIR INH INH – IX1 IX SP1 3D 4D 5D 6D 7D 9E6D dd ff ff 3 1 1 3 2 4 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH 9F 1 (SP) ← (H:X) – 1 – – – – – – INH 94 2 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor – – 1 – – – INH Technical Data Central Processor Unit (CPU) 67 Central Processor Unit (CPU) V H I N Z C A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & | ⊕ () –( ) # « ← ? : ↕ — Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected Technical Data 68 Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1. Instruction Set Summary MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Table 6-2. Opcode Map Bit Manipulation DIR DIR MSB Branch REL DIR INH 3 4 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL 5 6 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 IX 9E6 7 Control INH INH 8 9 Register/Memory IX2 SP2 IMM DIR EXT A B C D 9ED 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 SP1 IX E 9EE F LSB 0 1 2 3 4 Central Processor Unit (CPU) 0 Read-Modify-Write INH IX1 5 6 7 8 9 A B C E F Technical Data 69 INH Inherent REL Relative IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD Direct-Direct IMD Immediate-Direct IX+D Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions 5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment 7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR MSB 0 3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX High Byte of Opcode in Hexadecimal LSB Low Byte of Opcode in Hexadecimal 0 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode Central Processor Unit (CPU) D 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH Central Processor Unit (CPU) Technical Data 70 MC68H(R)C908JL3 — Rev. 1.1 Central Processor Unit (CPU) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 75 7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 75 7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 77 7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 79 7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 7.4.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 80 7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 80 7.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . . 81 7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 7.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . 86 7.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . 87 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 71 System Integration Module (SIM) 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.8.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . .91 7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . 92 7.8.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . 94 7.2 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and COP timeout • Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Technical Data 72 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK 2OSCOUT (FROM OSCILLATOR) OSCOUT (FROM OSCILLATOR) ÷2 VDD CLOCK CONTROL INTERNAL PULL-UP RESET PIN LOGIC CLOCK GENERATORS POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) USB RESET (FROM USB MODULE) RESET INTERRUPT SOURCES INTERRUPT CONTROL AND PRIORITY DECODE CPU INTERFACE Figure 7-1. SIM Block Diagram Table 7-1. Signal Name Conventions Signal Name Description 2OSCOUT Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit. OSCOUT The 2OSCOUT frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = 2OSCOUT ÷ 4) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 73 System Integration Module (SIM) Addr. Register Name Read: $FE00 Break Status Register Write: (BSR) Reset: Bit 7 6 5 4 3 2 1 R R R R R R 0 0 0 0 0 0 0 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 R R R R R R R R BCFE R R R R R R R 0 IF5 IF4 IF3 0 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 IF14 0 0 0 0 0 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF15 R R R R R R R R 0 0 0 0 0 0 0 0 SBSW NOTE Bit 0 R Note: Writing a logic 0 clears SBSW. Read: $FE01 Reset Status Register Write: (RSR) POR: Read: $FE02 Reserved Write: Reset: $FE03 Read: Break Flag Control Register Write: (BFCR) Reset: Read: $FE04 Interrupt Status Register 1 Write: (INT1) Reset: Read: $FE05 Interrupt Status Register 2 Write: (INT2) Reset: Read: $FE06 Interrupt Status Register 3 Write: (INT3) Reset: 0 = Unimplemented R = Reserved Figure 7-2. SIM I/O Register Summary Technical Data 74 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) 7.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 7-3. From OSCILLATOR 2OSCOUT From OSCILLATOR OSCOUT SIM COUNTER ÷2 BUS CLOCK GENERATORS SIM Figure 7-3. SIM Clock Signals 7.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four. 7.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the time-out. 7.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 2OSCOUT cycles. (See 7.7.2 Stop Mode.) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 75 System Integration Module (SIM) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. 7.4 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in Monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 7.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 7.8 SIM Registers.) 7.4.1 External Pin Reset The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum of 67 2OSCCLK cycles, assuming that the POR was not the source of the reset. See Table 7-2 for details. Figure 7-4 shows the relative timing. Table 7-2. PIN Bit Set Timing Reset Type Number of Cycles Required to Set PIN POR 4163 (4096 + 64 + 3) All others 67 (64 + 3) Technical Data 76 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) OSCOUT RST IAB VECT H VECT L PC Figure 7-4. External Reset Timing 7.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (Figure 7-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR. (See Figure 7-6 . Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096 2OSCOUT cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 7-5. IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES 2OSCOUT IAB VECTOR HIGH Figure 7-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR INTERNAL RESET LVI Figure 7-6. Sources of Internal Reset MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 77 System Integration Module (SIM) The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 7.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables the oscillator to drive 2OSCOUT. • Internal clocks to the CPU and modules are held inactive for 4096 2OSCOUT cycles to allow stabilization of the oscillator. • The RST pin is driven low during the oscillator stabilization time. • The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES 2OSCOUT OSCOUT RST $FFFE IAB $FFFF Figure 7-7. POR Recovery Technical Data 78 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) 7.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every (212 – 24) 2OSCOUT cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time-out. The COP module is disabled if the RST pin or the IRQ1 pin is held at VDD + VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ1 pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VDD + VHI on the RST pin disables the COP module. 7.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 7.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 79 System Integration Module (SIM) 7.4.2.5 LVI Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIP. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RSTB) is held low while the SIM counter counts out 4096 2OSCCLK cycles. Sixtyfour 2OSCOUT cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RSTB) pin for all internal reset sources. 7.5 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of 2OSCOUT. 7.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. 7.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32 2OSCOUT cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG). Technical Data 80 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) 7.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 7.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 7.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.) 7.6 Exception Control Normal, sequential program execution can be changed in three different ways: • Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts 7.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 7-8 flow charts the handling of system interrupts. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 81 System Integration Module (SIM) FROM RESET BREAK INTERRUPT? I BIT SET? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO TIMER INTERRUPT? YES NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. (As many interrupts as exist on chip) FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS. NO EXECUTE INSTRUCTION. Figure 7-8. Interrupt Processing Technical Data 82 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 7-9 shows interrupt entry timing. Figure 7-10 shows interrupt recovery timing. MODULE INTERRUPT I BIT IAB IDB DUMMY SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 7-9. Interrupt Entry MODULE INTERRUPT I BIT IAB SP – 4 IDB SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 7-10. Interrupt Recovery 7.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 83 System Integration Module (SIM) set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. CLI LDA #$FF INT1 BACKGROUND ROUTINE PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 7-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. Technical Data 84 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) 7.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 7.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 7-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 7-3. Interrupt Sources Flag Mask1 INT Register Flag Vector Address Reset — — — $FFFE–$FFFF SWI Instruction — — — $FFFC–$FFFD IRQ1 Pin IRQF1 IMASK1 IF1 $FFFA–$FFFB Timer Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7 Timer Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5 TOF TOIE IF5 $FFF2–$FFF3 Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1 ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF Source Priority Highest Timer Overflow Interrupt Lowest Note: 1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 85 System Integration Module (SIM) 7.6.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IF5 IF4 IF3 0 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 7-12. Interrupt Status Register 1 (INT1) IF1, IF3 to IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3 and 7 — Always read 0 7.6.2.2 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 0 0 0 0 0 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 7-13. Interrupt Status Register 2 (INT2) IF14 — Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 to 6 — Always read 0 Technical Data 86 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) 7.6.2.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 7-14. Interrupt Status Register 3 (INT3) IF15 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1 to 7 — Always read 0 7.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.6.4 Break Interrupts The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See Section 17. Break Module (BREAK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 87 System Integration Module (SIM) protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 7.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 7.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 7-15 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break Technical Data 88 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) status register (BSR). If the COP disable bit, COPD, in the mask option register is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode. IAB WAIT ADDR IDB WAIT ADDR + 1 PREVIOUS DATA SAME NEXT OPCODE SAME SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 7-15. Wait Mode Entry Timing Figure 7-16 and Figure 7-17 show the timing for WAIT recovery. IAB $6E0B IDB $A6 $A6 $6E0C $A6 $01 $00FF $0B $00FE $00FD $00FC $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 7-16. Wait Recovery from Interrupt or Break 32 Cycles $6E0B IAB IDB $A6 $A6 32 Cycles RSTVCTH RSTVCT L $A6 RST 2OSCOUT Figure 7-17. Wait Recovery from Internal Reset MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 89 System Integration Module (SIM) 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and 2OSCOUT) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 2OSCOUT cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register (BSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-18 shows stop mode entry timing. NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. CPUSTOP IAB IDB STOP ADDR STOP ADDR + 1 PREVIOUS DATA SAME NEXT OPCODE SAME SAME SAME R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 7-18. Stop Mode Entry Timing Technical Data 90 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) STOP RECOVERY PERIOD 2OSCOUT INT/BREAK IAB STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 7-19. Stop Mode Recovery from Interrupt or Break 7.8 SIM Registers The SIM has three memory mapped registers. Table 7-4 shows the mapping of these registers. Table 7-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 RSR User $FE03 BFCR User 7.8.1 Break Status Register (BSR) The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R Reset: 1 SBSW Note(1) Bit 0 R 0 R = Reserved 1. Writing a logic zero clears SBSW. Figure 7-20. Break Status Register (BSR) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 91 System Integration Module (SIM) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit clears it. ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited ; by break. TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too. DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH RTI ; Restore H register. 7.8.2 Reset Status Register (RSR) This register contains six flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Technical Data 92 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor System Integration Module (SIM) Address: Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 Write: POR: = Unimplemented Figure 7-21. Reset Status Register (RSR) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $00 after POR while IRQB = VDD 0 = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data System Integration Module (SIM) 93 System Integration Module (SIM) 7.8.3 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 7-22. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Technical Data 94 MC68H(R)C908JL3 — Rev. 1.1 System Integration Module (SIM) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 8. Oscillator (OSC) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.3 X-tal Oscillator (MC68HC908xxx). . . . . . . . . . . . . . . . . . . . . . . 96 8.4 RC Oscillator (MC68HRC908xxx) . . . . . . . . . . . . . . . . . . . . . . 97 8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 98 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . . 98 8.5.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 98 8.5.4 X-tal Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . .98 8.5.5 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . 99 8.5.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . .99 8.5.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8.7 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . 100 8.2 Introduction The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator modules are available: • MC68HC908xxx— built-in oscillator module (X-tal oscillator) that requires an external crystal or ceramic-resonator. This option also allows an external clock that can be driven directly into OSC1. • MC68HRC908xxx — built-in oscillator module (RC oscillator) that requires an external RC connection only. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Oscillator (OSC) 95 Oscillator (OSC) 8.3 X-tal Oscillator (MC68HC908xxx) The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, as shown in Figure 8-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: • Crystal, X1 • Fixed capacitor, C1 • Tuning capacitor, C2 (can also be a fixed capacitor) • Feedback resistor, RB • Series resistor, RS (optional) From SIM To SIM 2OSCOUT XTALCLK To SIM OSCOUT ÷2 SIMOSCEN MCU OSC1 OSC2 RS* RB X1 *RS can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. See Section 18. for component value requirements. C1 C2 Figure 8-1. X-tal Oscillator External Connections Technical Data 96 MC68H(R)C908JL3 — Rev. 1.1 Oscillator (OSC) Freescale Semiconductor Oscillator (OSC) The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. 8.4 RC Oscillator (MC68HRC908xxx) The RC oscillator circuit is designed for use with external R and C to provide a clock source with tolerance less than 10%. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: • CEXT • REXT To SIM From SIM 2OSCOUT SIMOSCEN Ext-RC Oscillator EN To SIM OSCOUT RCCLK ÷2 0 1 PTA6 I/O PTA6 MCU PTA6EN PTA6/RCCLK (OSC2) OSC1 VDD REXT CEXT See Section 18. for component value requirements. Figure 8-2. RC Oscillator External Connections MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Oscillator (OSC) 97 Oscillator (OSC) 8.5 I/O Signals The following paragraphs describe the oscillator I/O signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK) For the X-tal oscillator device, OSC2 pin is the output of the crystal oscillator inverting amplifier. For the RC oscillator device, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of the internal RC oscillator clock, RCCLK. Option OSC2 pin function X-tal oscillator Inverting OSC1 RC oscillator Controlled by PTAEN bit in PTAPUER ($0D) PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6 I/O 8.5.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the X-tal oscillator circuit or the RC-oscillator. 8.5.4 X-tal Oscillator Clock (XTALCLK) XTALCLK is the X-tal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 8-1 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start-up. Technical Data 98 MC68H(R)C908JL3 — Rev. 1.1 Oscillator (OSC) Freescale Semiconductor Oscillator (OSC) 8.5.5 RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. Figure 8-2 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry. 8.5.6 Oscillator Out 2 (2OSCOUT) 2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module and is used to determine the COP cycles. 8.5.7 Oscillator Out (OSCOUT) The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency. 8.6 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 8.6.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to the SIM module. 8.6.2 Stop Mode The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Oscillator (OSC) 99 Oscillator (OSC) 8.7 Oscillator During Break Mode The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state. Technical Data 100 MC68H(R)C908JL3 — Rev. 1.1 Oscillator (OSC) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 9. Monitor ROM (MON) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 9.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.4.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.2 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. This mode is also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be achieved without use of the higher test voltage, VDD + VHI, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 101 Monitor ROM (MON) 9.3 Features Features of the monitor ROM include the following: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer • Execution of code in RAM or FLASH • FLASH memory security feature1 • FLASH memory programming interface • 960 bytes monitor ROM code size • Monitor mode entry without high voltage, VDD + VHI, if reset vector is blank ($FFFE and $FFFF contain $FF) • Standard monitor mode entry if high voltage, VDD + VHI, is applied to IRQ1 9.4 Functional Description The monitor ROM receives and executes commands from a host computer. Figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute host-computer code in RAM while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR configuration and requires a pull-up resistor. 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 102 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Monitor ROM (MON) RST VDD RC CIRCUIT (FOR MC68HRC908xxx) VDD See Figure 18-1 for component values vs. frequency. 0.1 µF VDD + VHI 10k Ω HC908JL3 HC908JK3 HC908JK1 10k Ω SW2 C OSC1 IRQ1 OSC2 (SEE NOTE 4 AND 5) VDD D VDD VDD (SEE NOTE 2) 0.1 µF VSS 10 µF 10 µF MC145407 + + + 3 18 4 17 2 19 C (SEE NOTE 1) 20 OSC1 9.8304MHz 10 µF D C 10MΩ 1 20 pF OSC2 D + 10 µF VDD VDD 20 pF 10 kΩ X-TAL CIRCUIT DB-25 2 3 A 5 6 16 (SEE NOTE 3) SW1 PTB3 B 15 10 kΩ 7 VDD 1 MC74HC125 VDD 14 2 3 6 5 10 kΩ 4 PTB0 VDD 10 kΩ 7 PTB1 NOTES: 1. X-tal circuit replaced by RC circuit for MC68HRC908xxx 2. External oscillator must have a 50% duty cycle. 3. Affects high voltage entry to monitor mode only (SW2 at position C): SW1: Position A — Bus clock = OSC1 ÷ 4 SW1: Position B — Bus clock = OSC1 ÷ 2 4. SW2: Position C — High voltage entry to monitor mode. Input clock = OSC1; Bus clock depends on SW1. SW2: Position D — Bus clock source = X-TAL or RC oscillator. Bus clock = XTALCLK ÷ 4 or RCCLK ÷ 4. 5. See Table 18-4 for IRQ1 voltage level requirements. PTB2 10 kΩ Figure 9-1. Monitor Mode Circuit MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 103 Monitor ROM (MON) 9.4.1 Entering Monitor Mode Table 9-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If IRQ1 = VDD + VHI: – External clock on OSC1 is 4.9125MHz – PTB3 = low 2. If IRQ1 = VDD + VHI: – External clock on OSC1 is 9.8304MHz – PTB3 = high 3. If $FFFE & $FFFF is blank (contains $FF): – The oscillator clock is 9.8304MHz (X-tal or RC) – IRQ1 = VDD IRQ1 $FFFE and $FFFF PTB3 PTB2 PTB1 PTB0 Table 9-1. Monitor Mode Entry Requirements and Options Clock Source and Frequency VDD + VHI X 0 0 1 1 OSC1 at 4.9152MHz 2.4576MHz VDD + VHI X 1 0 1 1 OSC1 at 9.8304MHz 2.4576MHz VDD BLANK (contain $FF) 1 X-tal or RC oscillator at 9.8304MHz 2.4576MHz Low-voltage entry to monitor mode. 9600 baud communication on PTB0. COP disabled. VDD NOT BLANK X X-tal or RC oscillator at desired frequency XTALCLK ÷ 4 or RCCLK ÷ 4 Enters User mode. If $FFFE and $FFFF is blank, MCU will encounter an illegal address reset. X X X X X X Bus Frequency Comments Bypasses X-tal or RC oscillator; external clock driven directly into OSC1. 9600 baud communication on PTB0. COP disabled. Notes: 1. PTB3 = 0: Bypasses the divide-by-two prescaler to SIM when using VDD + VHI for monitor mode entry. The OSC1 clock must be 50% duty cycle for this condition. 2. XTALCLK is the X-tal oscillator output, for MC68HC908xxx. See Figure 8-1. 4. RCCLK is the RC oscillator output, for MC68HRC908xxx. See Figure 8-2. 5. See Table 18-4 for VDD + VHI voltage level requirements. Technical Data 104 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Monitor ROM (MON) If VDD +VHI is applied to IRQ1 and PTB3 is low upon monitor mode entry (Table 9-1 condition set 1), the bus frequency is a divide-by-two of the external clock input to OSC1. If PTB3 is high with VDD +VHI applied to IRQ1 upon monitor mode entry (Table 9-1 condition set 2), the bus frequency is a divide-by-four of the external clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VDD +VHI is applied to IRQ1. In this event, the OSCOUT frequency is equal to the 2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. Entering monitor mode with VDD + VHI on IRQ1, the COP is disabled as long as VDD + VHI is applied to either the IRQ1 or the RST. (See Section 7. System Integration Module (SIM) for more information on modes of operation.) If entering monitor mode without high voltage on IRQ1 and reset vector being blank ($FFFE and $FFFF) (Table 9-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions, including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the state of IRQ1 or the RST. Figure 9-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ1 = VDD. An oscillator frequency (XTALCLK or RCCCLK) of 9.8304MHz is required for a baud rate of 9600. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 105 Monitor ROM (MON) POR RESET IS VECTOR BLANK? NO NORMAL USER MODE YES MONITOR MODE EXECUTE MONITOR CODE POR TRIGGERED? NO YES Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 9.5 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. The break signal also provides a timing reference to allow the host to determine the necessary baud rate. In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. Technical Data 106 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Monitor ROM (MON) Table 9-2 is a summary of the vector differences between user mode and monitor mode. Table 9-2. Monitor Mode Vector Differences Functions COP Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD Modes Notes: 1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends control to the address on the stack pointer. 9.4.2 Baud Rate The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud rate if entry to monitor mode is by IRQ1 = VDD + VHI. When PTB3 is high, the divide by ratio is 1024. If the PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. Table 9-3. Monitor Baud Rate Selection Monitor Mode Entry By: IRQ1 = VDD + VHI Blank reset vector, IRQ1 = VDD Input Clock Frequency PTB3 Baud Rate 4.9152 MHz 0 9600 bps 9.8304 MHz 1 9600 bps 4.9152 MHz 1 4800 bps 9.8304 MHz X 9600 bps 4.9152 MHz X 4800 bps MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 107 Monitor ROM (MON) 9.4.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 9-3 and Figure 9-4.) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT BIT 7 NEXT START BIT Figure 9-3. Monitor Data Format $A5 START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BREAK START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT STOP BIT NEXT START BIT NEXT START BIT Figure 9-4. Sample Monitor Waveforms The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive baud rates must be identical. 9.4.4 Echoing As shown in Figure 9-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin for error checking. SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ECHO ADDR. LOW DATA RESULT Figure 9-5. Read Transaction Any result of a command appears after the echo of the last byte of the command. Technical Data 108 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Monitor ROM (MON) 9.4.5 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 9-6.) When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT 0 1 2 3 4 5 TWO-STOP-BIT DELAY BEFORE ZERO ECHO 6 7 0 1 2 3 4 5 6 7 Figure 9-6. Break Transaction 9.4.6 Commands The monitor ROM uses the following commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 109 Monitor ROM (MON) Table 9-4. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW ECHO DATA RESULT Table 9-5. WRITE (Write Memory) Command Description Write byte to memory Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA ECHO Technical Data 110 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Monitor ROM (MON) Table 9-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA RESULT ECHO Table 9-7. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode $19 Command Sequence SENT TO MONITOR IWRITE IWRITE DATA DATA ECHO NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 111 Monitor ROM (MON) Table 9-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH SP LOW RESULT ECHO Table 9-9. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO Technical Data 112 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Monitor ROM (MON) 9.5 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data. NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTB0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. (See Figure 9-7.) VDD 4096 + 32 OSCXCLK CYCLES RST COMMAND BYTE 8 BYTE 2 BYTE 1 24 BUS CYCLES FROM HOST PTB0 NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. 4 1 COMMAND ECHO 2 BREAK 1 BYTE 8 ECHO 1 BYTE 2 ECHO FROM MCU 4 BYTE 1 ECHO 1 Figure 9-7. Monitor Mode Entry Timing MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Monitor ROM (MON) 113 Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bytes. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Technical Data 114 MC68H(R)C908JL3 — Rev. 1.1 Monitor ROM (MON) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 10. Timer Interface Module (TIM) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 120 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .120 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 121 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 122 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 123 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . 127 10.10.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . 129 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . 130 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 131 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . 135 MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 115 Timer Interface Module (TIM) 10.2 Introduction This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 is a block diagram of the TIM. 10.3 Features Features of the TIM include the following: • Two input capture/output compare channels – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered pulse width modulation (PWM) signal generation • Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits • Modular architecture expandable to eight channels 10.4 Pin Name Conventions The TIM share two I/O pins with two port D I/O pins. The full name of the TIM I/O pins are listed in Table 10-1. The generic pin name appear in the text that follows. Table 10-1. Pin Name Conventions TIM Generic Pin Names: TCH0 TCH1 Full TIM Pin Names: PTD4/TCH0 PTD5/TCH1 Technical Data 116 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) 10.5 Functional Description Figure 10-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels. PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE 16-BIT COMPARATOR INTERRUPT LOGIC TMODH:TMODL TOV0 CHANNEL 0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L PORT LOGIC TCH0 CH0F 16-BIT LATCH MS0A CH0IE INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L PORT LOGIC TCH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC Figure 10-1. TIM Block Diagram MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 117 Timer Interface Module (TIM) Addr. $0020 $0021 $0022 Register Name TIM Status and Control Register (TSC) TIM Counter Register High (TCNTH) TIM Counter Register Low (TCNTL) Bit 7 $0023 TIM Counter Modulo Register Low (TMODL) $0024 $0025 TIM Channel 0 Status and Control Register (TSC0) TIM Channel 0 Register High (TCH0H) $0026 TIM Channel 0 Register Low (TCH0L) $0027 $0028 TIM Channel 1 Status and Control Register (TSC1) 5 TOIE TSTOP 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 Read: TOF Write: 0 Reset: 0 0 1 0 0 0 0 0 Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: 0 0 0 0 0 0 0 0 Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: 1 1 1 1 1 1 1 1 Read: CH0F Write: 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Reset: 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 TRST Write: Write: Reset: TIM Counter Modulo Register High (TMODH) 6 Read: Write: Reset: Read: Write: Read: Write: Reset: Read: Write: Indeterminate after reset Bit7 Bit6 Bit5 Reset: Bit4 Bit3 Indeterminate after reset Read: CH1F Write: 0 Reset: 0 CH1IE 0 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 Figure 10-2. TIM I/O Register Summary Technical Data 118 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) $0029 $002A TIM Channel 1 Register High (TCH1H) TIM Channel 1 Register Low (TCH1L) Read: Write: Bit15 Bit14 Bit13 Reset: Read: Write: Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 Indeterminate after reset Bit7 Bit6 Bit5 Reset: Bit4 Bit3 Indeterminate after reset = Unimplemented Figure 10-2. TIM I/O Register Summary 10.5.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source. 10.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 10.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 119 Timer Interface Module (TIM) 10.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • When changing to a larger output compare value, enable channel x TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 10.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM Technical Data 120 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 10-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic one. Program the TIM to set the pin if the state of the PWM pulse is logic zero. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 121 Timer Interface Module (TIM) OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 10-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 10.10.1 TIM Status and Control Register (TSC)). The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 10.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 10.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to Technical Data 122 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable channel x TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 10.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 123 Timer Interface Module (TIM) (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. 10.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 10-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. NOTE: Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 10-3.) In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Technical Data 124 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100% duty cycle output. (See 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).) 10.6 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value rolls over to $0000 after matching the value in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. • TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE=1. CHxF and CHxIE are in the TIM channel x status and control register. 10.7 Wait Mode The WAIT instruction puts the MCU in low-power-consumption standby mode. The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 125 Timer Interface Module (TIM) If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 10.8 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR).) To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero. After the break, doing the second step clears the status bit. 10.9 I/O Signals Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin. Technical Data 126 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) 10.10 I/O Registers The following I/O registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM control registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 and TSC1) • TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L) 10.10.1 TIM Status and Control Register (TSC) The TIM status and control register does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: $0020 Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 10-4. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter resets to $0000 after reaching the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic zero to TOF. If another TIM MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 127 Timer Interface Module (TIM) overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic one to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic zero. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 10-2 shows. Reset clears the PS[2:0] bits. Technical Data 128 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) Table 10-2. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal Bus Clock ÷ 1 0 0 1 Internal Bus Clock ÷ 2 0 1 0 Internal Bus Clock ÷ 4 0 1 1 Internal Bus Clock ÷ 8 1 0 0 Internal Bus Clock ÷ 16 1 0 1 Internal Bus Clock ÷ 32 1 1 0 Internal Bus Clock ÷ 64 1 1 1 Not available 10.10.2 TIM Counter Registers (TCNTH:TCNTL) The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 129 Timer Interface Module (TIM) Address: Read: $0021 TCNTH Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 $0022 TCNTL Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Write: Reset: Address: Read: Write: Reset: = Unimplemented Figure 10-5. TIM Counter Registers (TCNTH:TCNTL) 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Technical Data 130 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) Address: Read: Write: Reset: Address: Read: Write: Reset: $0023 TMODH Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 $0024 TMODL Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) Each of the TIM channel status and control registers does the following: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIM overflow • Selects 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 131 Timer Interface Module (TIM) Address: $0025 TSC0 Bit 7 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 5 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Read: CH0F Write: 0 Reset: 0 0 $0028 TSC1 Bit 7 6 Address: Read: CH1F Write: 0 Reset: 0 CH1IE 0 0 0 = Unimplemented Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE=1), clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic zero to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic zero to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic one to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled Technical Data 132 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 10-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. (See Table 10-3.) Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 10-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 133 Timer Interface Module (TIM) Table 10-3. Mode, Edge, and Level Selection MSxB MSxA ELSxB ELSxA X 0 0 0 Mode Output Preset NOTE: X 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 1 1 X 0 1 1 X 1 0 1 X 1 1 Configuration Pin under Port Control; Initial Output Level High Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only Input Capture Capture on Falling Edge Only Capture on Rising or Falling Edge Output Compare or PWM Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Buffered Output Clear Output on Compare Compare or Buffered Set Output on Compare PWM Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE: When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic zero, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 10-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. Technical Data 134 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Timer Interface Module (TIM) OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 10-8. CHxMAX Latency 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Timer Interface Module (TIM) 135 Timer Interface Module (TIM) Address: Read: Write: $0026 TCH0H Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: Address: Read: Write: Indeterminate after reset $0027 TCH0L Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset: Address: Read: Write: Indeterminate after reset $0029 TCH1H Bit 7 6 5 4 3 2 1 Bit 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Reset: Address: Read: Write: Reset: Indeterminate after reset $02A TCH1L Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Indeterminate after reset Figure 10-9. TIM Channel Registers (TCH0H/L:TCH1H/L) Technical Data 136 MC68H(R)C908JL3 — Rev. 1.1 Timer Interface Module (TIM) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 11. Analog-to-Digital Converter (ADC) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .142 11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.2 Introduction This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 12-channels analog-to-digital converter. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Analog-to-Digital Converter (ADC) 137 Analog-to-Digital Converter (ADC) 11.3 Features Features of the ADC module include: Addr. $003C $003D • 12 channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock Register Name Bit 7 Read: ADC Status and Control Register Write: (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset: Read: ADC Input Clock Register $003E Write: (ADICLK) Reset: 6 5 4 3 2 1 Bit 0 AIEN ADCO CH4 CH3 CH2 CH1 CH0 0 0 0 1 1 1 1 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 COCO Indeterminate after reset ADIV2 ADIV1 ADIV0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11-1. ADC I/O Register Summary 11.4 Functional Description Twelve ADC channels are available for sampling external sources at pins PTB0–PTB7 and PTD0–PTD3. An analog multiplexer allows the single ADC converter to select one of the 12 ADC channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 11-2 shows a block diagram of the ADC. Technical Data 138 MC68H(R)C908JL3 — Rev. 1.1 Analog-to-Digital Converter (ADC) Freescale Semiconductor Analog-to-Digital Converter (ADC) INTERNAL DATA BUS READ DDRB/DDRD DISABLE WRITE DDRB/DDRD DDRBx/DDRDx RESET WRITE PTB/PTD ADCx PTBx/PTDx READ PTB/PTD DISABLE ADC CHANNEL x ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC ADC VOLTAGE IN ADCVIN CHANNEL SELECT (1 OF 12 CHANNELS) CH[4:0] ADC CLOCK COCO CLOCK GENERATOR BUS CLOCK ADIV[2:0] ADICLK Figure 11-2. ADC Block Diagram 11.4.1 ADC Port I/O Pins PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC Status and Control register, $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Analog-to-Digital Converter (ADC) 139 Analog-to-Digital Converter (ADC) Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read. 11.4.2 Voltage Conversion When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS. NOTE: Input voltage should not exceed the analog supply voltages. 11.4.3 Conversion Time Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1MHz, then one conversion will take 16µs to complete. With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz. Conversion Time = 16 ADC Clock Cycles ADC Clock Frequency Number of Bus Cycles = Conversion Time × Bus Frequency 11.4.4 Continuous Conversion In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC data register with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADC Status & Control register, $003C) is set after each conversion and can be cleared by writing the ADC status and control register or reading of the ADC data register. Technical Data 140 MC68H(R)C908JL3 — Rev. 1.1 Analog-to-Digital Converter (ADC) Freescale Semiconductor Analog-to-Digital Converter (ADC) 11.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 11.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 11.6 Low-Power Modes The following subsections describe the ADC in low-power modes. 11.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the CH[4:0] bits in the ADC Status and Control register to logic 1’s before executing the WAIT instruction. 11.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode. 11.7 I/O Signals The ADC module has 12 channels that are shared with I/O port B and port D. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Analog-to-Digital Converter (ADC) 141 Analog-to-Digital Converter (ADC) 11.7.1 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module. 11.8 I/O Registers These I/O registers control and monitor ADC operation: • ADC Status and Control register (ADSCR) • ADC data register (ADR) • ADC clock register (ADICLK) 11.8.1 ADC Status and Control Register The following paragraphs describe the function of the ADC Status and Control register. Address: $003C Bit 7 Read: COCO Write: Reset: 0 6 5 4 3 2 1 Bit 0 AIEN ADCO CH4 CH3 CH2 CH1 CH0 0 0 1 1 1 1 1 = Unimplemented Figure 11-3. ADC Status and Control Register (ADSCR) COCO — Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read. Reset clears this bit. 1 = conversion completed (AIEN = 0) 0 = conversion not completed (AIEN = 0) When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be logic 0 when read. Technical Data 142 MC68H(R)C908JL3 — Rev. 1.1 Analog-to-Digital Converter (ADC) Freescale Semiconductor Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] — ADC Channel Select Bits ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of the ADC channels. The five channel select bits are detailed in the following table. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (See Table 11-1.) The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a logic 1. NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Analog-to-Digital Converter (ADC) 143 Analog-to-Digital Converter (ADC) Table 11-1. MUX Channel Select CH4 CH3 CH2 CH1 CH0 ADC Channel Input Select 0 0 0 0 0 ADC0 PTB0 0 0 0 0 1 ADC1 PTB1 0 0 0 1 0 ADC2 PTB2 0 0 0 1 1 ADC3 PTB3 0 0 1 0 0 ADC4 PTB4 0 0 1 0 1 ADC5 PTB5 0 0 1 1 0 ADC6 PTB6 0 0 1 1 1 ADC7 PTB7 0 1 0 0 0 ADC8 PTD3 0 1 0 0 1 ADC9 PTD2 0 1 0 1 0 ADC10 PTD1 0 1 0 1 1 ADC11 PTD0 0 1 1 0 0 : : : : : — Unused (see Note 1) 1 1 0 1 0 1 1 0 1 1 — Reserved 1 1 1 0 0 — Unused 1 1 1 0 1 VDDA (see Note 2) 1 1 1 1 0 VSSA (see Note 2) 1 1 1 1 1 ADC power off NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications. 11.8.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Technical Data 144 MC68H(R)C908JL3 — Rev. 1.1 Analog-to-Digital Converter (ADC) Freescale Semiconductor Analog-to-Digital Converter (ADC) Address: Read: $003D Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: Indeterminate after reset = Unimplemented Figure 11-4. ADC Data Register (ADR) 11.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC. Address: Read: Write: Reset: $003E Bit 7 6 5 ADIV2 ADIV1 ADIV0 0 0 0 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 11-5. ADC Input Clock Register (ADICLK) ADIV2:ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 11-2 shows the available clock configurations. The ADC clock should be set to approximately 1MHz. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Analog-to-Digital Converter (ADC) 145 Analog-to-Digital Converter (ADC) Table 11-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC Input Clock ÷ 1 0 0 1 ADC Input Clock ÷ 2 0 1 0 ADC Input Clock ÷ 4 0 1 1 ADC Input Clock ÷ 8 1 X X ADC Input Clock ÷ 16 X = don’t care Technical Data 146 MC68H(R)C908JL3 — Rev. 1.1 Analog-to-Digital Converter (ADC) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 12. I/O Ports 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.4 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.4.1 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . 150 12.4.2 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . 151 12.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . 153 12.5.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . 153 12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . 155 12.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . 156 12.6.3 Port D Control Register (PDCR). . . . . . . . . . . . . . . . . . . . . 157 12.2 Introduction Twenty three bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data I/O Ports 147 I/O Ports Addr. Register Name $0000 Read: Port A Data Register Write: (PTA) Reset: $0001 $0003 Bit 7 Read: Port B Data Register Write: (PTB) Reset: Read: Port D Data Register Write: (PTD) Reset: Read: Data Direction Register A $0004 Write: (DDRA) Reset: 0 PTB7 $000D 4 3 2 1 Bit 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTD2 PTD1 PTD0 PTB6 PTB5 PTB4 PTB3 Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 Unaffected by reset 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read: DDRD7 Data Direction Register D $0007 Write: (DDRD) Reset: 0 $000A 5 Unaffected by reset Read: DDRB7 Data Direction Register B $0005 Write: (DDRB) Reset: 0 Read: Port D Control Register Write: (PDCR) Reset: 6 SLOWD7 SLOWD6 PTDPU7 0 0 0 PTDPU6 0 Read: Port A Input Pull-up PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Enable Register Write: (PTAPUE) Reset: 0 0 0 0 0 0 0 0 Figure 12-1. I/O Port Register Summary 12.3 Port A Port A is an 7-bit special function port that shares all seven of its pins with the Keyboard Interrupt (KBI) Module, See Section 14. Each port A pin also has software configurable pull-up device if the corresponding port pin is configured as input port. PTA0 to PTA5 has direct LED drive capability. Technical Data 148 MC68H(R)C908JL3 — Rev. 1.1 I/O Ports Freescale Semiconductor I/O Ports 12.4 Port A Data Register (PTA) The port A data register (PTA) contains a data latch for each of the seven port A pins. Address: $0000 Bit 7 Read: Write: 0 6 5 4 3 2 1 Bit 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 LED (Sink) LED (Sink) LED (Sink) Reset: Additional Functions: Unaffected by Reset LED (Sink) LED (Sink) LED (Sink) 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Figure 12-2. Port A Data Register (PTA) PTA[6:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBI[6:0] — Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE6-KBIE0, in the keyboard interrupt control register (KBAIER) enable the port A pins as external interrupt pins, (see Section 14. Keyboard Interrupt Module (KBI)). MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data I/O Ports 149 I/O Ports 12.4.1 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output buffer. Address: $0004 Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 Figure 12-3. Data Direction Register A (DDRA) DDRA[6:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[6:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 12-4 shows the port A I/O logic. Technical Data 150 MC68H(R)C908JL3 — Rev. 1.1 I/O Ports Freescale Semiconductor I/O Ports READ DDRA ($0004) PTAPUEx INTERNAL DATA BUS WRITE DDRA ($0004) RESET WRITE PTA ($0000) DDRAx 30k PTAx PTAx READ PTA ($0000) To Keyboard Interrupt Circuit Figure 12-4. Port A I/O Circuit When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. 12.4.2 Port A Input Pull-up Enable Register (PTAPUE) The Port A Input Pull-up Enable Register (PTAPUE) contains a software configurable pull-up device for each if the seven port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx be configured as input. Each pull-up device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data I/O Ports 151 I/O Ports Address: Read: Write: $000D Bit 7 6 5 4 3 2 1 Bit 0 PTA6EN PTAPUE 6 PTAPUE 5 PTAPUE 4 PTAPUE 3 PTAPUE 2 PTAPUE 2 PTAPUE 0 0 0 0 0 0 0 0 0 Reset: Figure 12-5. Port A Input Pull-up Enable Register (PTAPUE) PTA6EN — Enable PTA6 on OSC2 This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has no effect for X-tal oscillator option. 1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions. 0 = OSC2 pin outputs the RC oscillator clock (RCCLK) PTAPUE[6:0] — Port A Input Pull-up Enable bits These read/write bits are software programmable to enable pull-up devices on port A pins 1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0 0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit. Table 12-1 summarizes the operation of the port B pins. Table 12-1. Port A Pin Functions 1. 2. 3. 4. Accesses to DDRB DDRA Bit PTA Bit 1 0 X(1) 0 0 X 1 PTAPUE Bit Read/Write Read Write Input, VDD(2) DDRA6-DDRA0 Pin PTA6-PTA0(3) X Input, Hi-Z(4) DDRA6-DDRA0 Pin PTA6-PTA0(3) X Output DDRA6-DDRA0 PTA6-PTA0 PTA6-PTA0 X = Don’t care. I/O pin pulled to VDD by internal pull-up. Writing affects data register, but does not affect input. Hi-Z = High Impedence Technical Data 152 Accesses to PTB I/O Pin Mode MC68H(R)C908JL3 — Rev. 1.1 I/O Ports Freescale Semiconductor I/O Ports 12.5 Port B Port B is an 8-bit special function port that shares all eight of its port pins with the Analog-to-Digital converter (ADC) module, See Section 11. 12.5.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins. Address: Read: Write: $0001 Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 ADC2 ADC2 ADC0 Reset: Alternative Function: Unaffected by reset ADC7 ADC6 ADC5 ADC4 ADC3 Figure 12-6. Port B Data Register (PTB) PTB[7:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. 12.5.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-7. Data Direction Register B (DDRB) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data I/O Ports 153 I/O Ports DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic. READ DDRB ($0005) INTERNAL DATA BUS WRITE DDRB ($0005) RESET WRITE PTB ($0001) DDRBx PTBx PTBx READ PTB ($0001) To Analog-To-Digital Converter Figure 12-8. Port B I/O Circuit When DDRBx is a logic 1, reading address $0001 reads the Hotbox data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-2summarizes the operation of the port B pins. Table 12-2. Port B Pin Functions Accesses to DDRB DDRB Bit PTB Bit Accesses to PTB I/O Pin Mode Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRB7-DDRB0 Pin PTB[7:0](3) 1 X Output DDRB7-DDRB0 Pin PTB[7:0] 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input. Technical Data 154 MC68H(R)C908JL3 — Rev. 1.1 I/O Ports Freescale Semiconductor I/O Ports 12.6 Port D Port D is an 8-bit special function port that shares two of its pins with Timer Interface Module, (see Section 10.) and shares four of its pins with Analog to Digital Conversion Module (see Section 11.). PTD6 and PTD7 each has high current drive (25mA sink) and programmable pullup. PTD2, PTD3, PTD6 and PTD7 each has LED driving capability. 12.6.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins. Address: Read: Write: $0003 Bit 7 6 5 4 3 2 1 Bit 0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 LED LED LED LED ADC8 ADC9 ADC10 ADC11 Reset: Additional Functions TCH1 TCH0 25mA sink 25mA sink (Slow Edge) (Slow Edge) 5k pull-up 5k pull-up Figure 12-9. Port D Data Register (PTD) PTD[7:0] — Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data I/O Ports 155 I/O Ports 12.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer. Address: Read: Write: Reset: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Figure 12-10. Data Direction Register D (DDRD) DDRD[7:0] — Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 12-11 shows the port D I/O logic. READ DDRD ($0007) PTDPU[6:7] INTERNAL DATA BUS WRITE DDRD ($0007) RESET WRITE PTD ($0003) DDRDx 5k PTDx PTDx READ PTD ($0003) PTD[0:3] To Analog-To-Digital Converter PTD[4:5] To Timer Figure 12-11. Port D I/O Circuit Technical Data 156 MC68H(R)C908JL3 — Rev. 1.1 I/O Ports Freescale Semiconductor I/O Ports When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port D pins. Table 12-3. Port D Pin Functions DDRD Bit PTD Bit Accesses to DDRA I/O Pin Mode Accesses to PTD Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRD[7:0] Pin PTD[7:0](3) 1 X Output DDRD[7:0] Pin PTD[7:0] 1. X = don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input. 12.6.3 Port D Control Register (PDCR) The Port D Control Register enables/disables the pull-up resistor and slow-edge high current capability of pins PTD6 and PTD7. Address: Read: $000A Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 0 0 0 0 Figure 12-12. Port D Control Register (PDCR) SLOWDx — Slow Edge Enable The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink) of port pins PTD6 and PTD7 respectively. DDRx bit is not affected by SLOWDx. 1 = Slow edge enabled; pin is open-drain output 0 = Slow edge disabled; pin is push-pull PTDPUx — Pull-up Enable The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and PTD7 respectively, regardless the status of DDRDx bit. 1 = Enable 5k pull-up 0 = Disable 5k pull-up MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data I/O Ports 157 I/O Ports Technical Data 158 MC68H(R)C908JL3 — Rev. 1.1 I/O Ports Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 13. External Interrupt (IRQ) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 13.4.1 IRQ1 Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 163 13.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 163 13.2 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 13.3 Features Features of the IRQ module include the following: • A dedicated external interrupt pin, IRQ1 • IRQ1 interrupt control bits • Hysteresis buffer • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Selectable internal pullup resistor MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data External Interrupt (IRQ) 159 External Interrupt (IRQ) 13.4 Functional Description A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 13-1 shows the structure of the IRQ module. Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. • Software clear — Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (ISCR). Writing a logic one to the ACK1 bit clears the IRQ1 latch. • Reset — A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or falling-edge and low-leveltriggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1 pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic one The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK1 bit in the ISCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK1 bit is clear. Technical Data 160 MC68H(R)C908JL3 — Rev. 1.1 External Interrupt (IRQ) Freescale Semiconductor External Interrupt (IRQ) NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests.(See 7.6 Exception Control.) INTERNAL ADDRESS BUS ACK1 RESET TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD IRQPUD VDD INTERNAL IRQF1 PULLUP DEVICE D CLR Q CK IRQ1 SYNCHRONIZER IRQ1 INTERRUPT REQUEST HIGH VOLTAGE DETECT TO MODE SELECT LOGIC IRQ1 FF IMASK1 MODE1 Figure 13-1. IRQ Module Block Diagram Addr. $001D Register Name Read: IRQ Status and Control Register Write: (INTSCR) Reset: Bit 7 6 5 4 3 2 0 0 0 0 IRQF1 0 ACK1 0 0 0 0 0 0 1 Bit 0 IMASK1 MODE1 0 0 = Unimplemented Figure 13-2. IRQ I/O Register Summary 13.4.1 IRQ1 Pin A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software clear, or reset clears the IRQ1 latch. If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive. With MODE1 set, both of the following actions must occur to clear IRQ1: MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data External Interrupt (IRQ) 161 External Interrupt (IRQ) • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ1 pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ1 pin. A falling edge that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. • Return of the IRQ1 pin to logic one — As long as the IRQ1 pin is at logic zero, IRQ1 remains active. The vector fetch or software clear and the return of the IRQ1 pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ1 pin is at logic zero. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low. If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ1 latch. The IRQF1 bit in the ISCR register can be used to check for pending interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ1 pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE: An internal pull-up resistor to VDD is connected to the IRQ1 pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E). Technical Data 162 MC68H(R)C908JL3 — Rev. 1.1 External Interrupt (IRQ) Freescale Semiconductor External Interrupt (IRQ) 13.5 IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 7. System Integration Module (SIM).) To allow software to clear the IRQ1 latch during a break interrupt, write a logic one to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero (its default state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect on the IRQ latch. 13.6 IRQ Status and Control Register (ISCR) The IRQ Status and Control Register (ISCR) controls and monitors operation of the IRQ module. The ISCR has the following functions: • Shows the state of the IRQ1 flag • Clears the IRQ1 latch • Masks IRQ1 and interrupt request • Controls triggering sensitivity of the IRQ1 interrupt pin Address: Read: $001D Bit 7 6 5 4 3 0 0 0 0 IRQF1 Write: Reset: 2 ACK1 0 0 0 0 0 0 1 Bit 0 IMASK1 MODE1 0 0 = Unimplemented Figure 13-3. IRQ Status and Control Register (INTSCR) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data External Interrupt (IRQ) 163 External Interrupt (IRQ) IRQF1 — IRQ1 Flag This read-only status bit is high when the IRQ1 interrupt is pending. 1 = IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writing a logic one to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic zero. Reset clears ACK1. IMASK1 — IRQ1 Interrupt Mask Bit Writing a logic one to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1. 1 = IRQ1 interrupt requests disabled 0 = IRQ1 interrupt requests enabled MODE1 — IRQ1 Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1. 1 = IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD R R LVIT1 LVIT0 R R R Reset: 0 0 0 0 0 0 POR: 0 0 0 0 0 0 Read: Write: R Not affected Not affected 0 0 = Reserved Figure 13-4. Configuration Register 2 (CONFIG2) IRQPUD — IRQ1 Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ1 pin and VDD Technical Data 164 MC68H(R)C908JL3 — Rev. 1.1 External Interrupt (IRQ) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 169 14.4.3 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 170 14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 171 14.2 Introduction The keyboard interrupt module (KBI) provides seven independently maskable external interrupts which are accessible via PTA0–PTA6 pins. 14.3 Features Features of the keyboard interrupt module include the following: • Seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask • Software configurable pull-up device if input pin is configured as input port bit • Programmable edge-only or edge- and level- interrupt sensitivity • Exit from low-power modes MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Keyboard Interrupt Module (KBI) 165 Keyboard Interrupt Module (KBI) Addr. $001A $001B Register Name Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Read: Keyboard Status and Control Register Write: (KBSCR) Reset: 0 Read: 0 Keyboard Interrupt Enable Write: Register (KBIER) Reset: 0 ACKK 1 Bit 0 IMASKK MODEK 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 = Unimplemented Figure 14-1. KBI I/O Register Summary 14.4 Functional Description INTERNAL BUS KBI0 ACKK VDD . KBIE0 TO PULLUP ENABLE D . CLR VECTOR FETCH DECODER KEYF RESET Q SYNCHRONIZER CK . KEYBOARD INTERRUPT FF KBI6 Keyboard Interrupt Request IMASKK MODEK KBIE6 TO PULLUP ENABLE Figure 14-2. Keyboard Interrupt Block Diagram Writing to the KBIE6–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pull-up device irrespective of PTAPUEx bits in the port A input pull-up enable register (see 12.4.2). A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. Technical Data 166 MC68H(R)C908JL3 — Rev. 1.1 Keyboard Interrupt Module (KBI) Freescale Semiconductor Keyboard Interrupt Module (KBI) A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. • If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. • Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Keyboard Interrupt Module (KBI) 167 Keyboard Interrupt Module (KBI) If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, disable the pullup device, use the data direction register to configure the pin as an input and then read the data register. NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 14.4.1 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and Technical Data 168 MC68H(R)C908JL3 — Rev. 1.1 Keyboard Interrupt Module (KBI) Freescale Semiconductor Keyboard Interrupt Module (KBI) level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 14.4.2 Keyboard Status and Control Register • Flags keyboard interrupt requests. • Acknowledges keyboard interrupt requests. • Masks keyboard interrupt requests. • Controls keyboard interrupt triggering sensitivity. Address: Read: $001A Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 14-3. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used These read-only bits always read as logic 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on portA. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Keyboard Interrupt Module (KBI) 169 Keyboard Interrupt Module (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-A. ACKK always reads as logic 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port-A. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port-A. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only 14.4.3 Keyboard Interrupt Enable Register The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 Figure 14-4. Keyboard Interrupt Enable Register (KBIER) KBIE6–KBIE0 — Port-A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin Technical Data 170 MC68H(R)C908JL3 — Rev. 1.1 Keyboard Interrupt Module (KBI) Freescale Semiconductor Keyboard Interrupt Module (KBI) 14.5 Wait Mode The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 14.6 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 14.7 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Keyboard Interrupt Module (KBI) 171 Keyboard Interrupt Module (KBI) Technical Data 172 MC68H(R)C908JL3 — Rev. 1.1 Keyboard Interrupt Module (KBI) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 15. Computer Operating Properly (COP) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.1 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 176 15.5 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 178 15.2 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Computer Operating Properly (COP) 173 Computer Operating Properly (COP) 15.3 Functional Description Figure 15-1 shows the structure of the COP module. SIM 2OSCOUT SIM RESET CIRCUIT RESET VECTOR FETCH RESET STATUS REGISTER COP TIMEOUT CLEAR ALL STAGES INTERNAL RESET SOURCES(1) CLEAR STAGES 5–12 12-BIT SIM COUNTER COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE CLEAR COP COUNTER COP RATE SEL (COPRS FROM CONFIG1) NOTE: 1. See SIM section for more details. Figure 15-1. COP Block Diagram The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 – 24 or 213 – 24 2OSCOUT cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 218 – 24 2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout period of 32.766 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter. Technical Data 174 MC68H(R)C908JL3 — Rev. 1.1 Computer Operating Properly (COP) Freescale Semiconductor Computer Operating Properly (COP) NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 × 2OSCOUT cycles and sets the COP bit in the reset status register (RSR). (See 7.8.2 Reset Status Register (RSR).). NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 15.4 I/O Signals The following paragraphs describe the signals shown in Figure 15-1. 15.4.1 2OSCOUT 2OSCOUT is the oscillator output signal. 2OSCOUT frequency is equal to the crystal frequency or the RC-oscillator frequency. 15.4.2 COPCTL Write Writing any value to the COP control register (COPCTL) (see 15.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector. 15.4.3 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × 2OSCOUT cycles after power-up. 15.4.4 Internal Reset An internal reset clears the SIM counter and the COP counter. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Computer Operating Properly (COP) 175 Computer Operating Properly (COP) 15.4.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. 15.4.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). (See Section 5. Configuration Register (CONFIG).) 15.4.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1. Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 R = Reserved Figure 15-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is (213 – 24) × 2OSCOUT cycles 0 = COP timeout period is (218 – 24) × 2OSCOUT cycles COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled Technical Data 176 MC68H(R)C908JL3 — Rev. 1.1 Computer Operating Properly (COP) Freescale Semiconductor Computer Operating Properly (COP) 15.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. Address: $FFFF Bit 7 6 5 4 3 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset 2 1 Bit 0 Figure 15-3. COP Control Register (COPCTL) 15.6 Interrupts The COP does not generate CPU interrupt requests. 15.7 Monitor Mode The COP is disabled in monitor mode when VDD + VHI is present on the IRQ1 pin or on the RST pin. 15.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 15.8.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Computer Operating Properly (COP) 177 Computer Operating Properly (COP) 15.8.2 Stop Mode Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. 15.9 COP Module During Break Mode The COP is disabled during a break interrupt when VDD + VHI is present on the RST pin. Technical Data 178 MC68H(R)C908JL3 — Rev. 1.1 Computer Operating Properly (COP) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 16. Low Voltage Inhibit (LVI) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 16.5 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . 180 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 16.2 Introduction This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage. 16.3 Features Features of the LVI module include the following: • Selectable LVI trip voltage • Selectable LVI circuit disable MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Low Voltage Inhibit (LVI) 179 Low Voltage Inhibit (LVI) 16.4 Functional Description Figure 16-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determines at which VDD level the LVI module should take actions. The LVI module generates one output signal: LVI Reset — an reset signal will be generated to reset the CPU when VDD drops to below the set trip point. VDD LVID VDD > LVITRIP = 0 LVI RESET VDD < LVITRIP = 1 LOW VDD DETECTOR LVT1 LVT0 Figure 16-1. LVI Module Block Diagram 16.5 LVI Control Register (CONFIG2/CONFIG1) Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD R R LVIT1 LVIT0 R R R Reset: 0 0 0 0 0 0 POR: 0 0 0 0 0 0 R = Reserved Read: Write: Not affected Not affected 0 0 Figure 16-2. Configuration Register 2 (CONFIG2) Technical Data 180 MC68H(R)C908JL3 — Rev. 1.1 Low Voltage Inhibit (LVI) Freescale Semiconductor Low Voltage Inhibit (LVI) Address: $001F Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 Reset: R = Reserved Figure 16-3. Configuration Register 1 (CONFIG1) LVID —þLow Voltage Inhibit Disable Bit 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled LVIT1, LVIT0 — LVI Trip Voltage Selection These two bits determine at which level of VDD the LVI module will come into action. LVIT1 and LVIT0 are cleared by a Power-On Reset only. LVIT1 LVIT0 Trip Voltage(1) Comments 0 0 VLVR3 (2.4V) For VDD =3V operation 0 1 VLVR3 (2.4V) For VDD =3V operation 1 0 VLVR5 (4.0V) For VDD =5V operation 1 1 Reserved 1. See Section 18. Electrical Specifications for full parameters. 16.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low-powerconsumption standby modes. 16.6.1 Wait Mode The LVI module, when enabled, will continue to operate in WAIT Mode. 16.6.2 Stop Mode The LVI module, when enabled, will continue to operate in STOP Mode. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Low Voltage Inhibit (LVI) 181 Low Voltage Inhibit (LVI) Technical Data 182 MC68H(R)C908JL3 — Rev. 1.1 Low Voltage Inhibit (LVI) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 17. Break Module (BREAK) 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 186 17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .186 17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 186 17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 186 17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . . 187 17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.5.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 190 17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 17.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 17.2 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Break Module (BREAK) 183 Break Module (BREAK) 17.3 Features Features of the break module include the following: • Accessible I/O registers during the break Interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 17.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: • A CPU-generated address (the address in the program counter) matches the contents of the break address registers. • Software writes a logic one to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 17-1 shows the structure of the break module. Technical Data 184 MC68H(R)C908JL3 — Rev. 1.1 Break Module (BREAK) Freescale Semiconductor Break Module (BREAK) IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 17-1. Break Module Block Diagram Addr. $FE00 $FE03 $FE0C $FE0D Register Name Read: Break Status Register Write: (BSR) Reset: Read: Break Flag Control Register Write: (BFCR) Reset: Read: Break Address High Register Write: (BRKH) Reset: Read: Break Address low Register Write: (BRKL) Reset: Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Note: Writing a logic 0 clears SBSW. Bit 7 6 5 4 3 2 R R R R R R 1 SBSW See note Bit 0 R 0 BCFE R R R R R R R Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented R 0 = Reserved Figure 17-2. Break I/O Register Summary MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Break Module (BREAK) 185 Break Module (BREAK) 17.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 7.8.3 Break Flag Control Register (BFCR) and see the Break Interrupts subsection for each module.) 17.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 17.4.3 TIM During Break Interrupts A break interrupt stops the timer counter. 17.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VDD + VHI is present on the RST pin. 17.5 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) Technical Data 186 MC68H(R)C908JL3 — Rev. 1.1 Break Module (BREAK) Freescale Semiconductor Break Module (BREAK) 17.5.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits. Address: Read: Write: Reset: $FE0E Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 17-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic zero to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic one to BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Break Module (BREAK) 187 Break Module (BREAK) 17.5.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: Read: Write: Reset: $FE0C Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Figure 17-4. Break Address Register High (BRKH) Address: Read: Write: Reset: $FE0D Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 17-5. Break Address Register Low (BRKL) 17.5.3 Break Status Register The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: $FE00 Bit 7 6 5 4 3 2 R R R R R R Reset: 1 SBSW Note(1) Bit 0 R 0 R = Reserved 1. Writing a logic zero clears SBSW. Figure 17-6. Break Status Register (BSR) Technical Data 188 MC68H(R)C908JL3 — Rev. 1.1 Break Module (BREAK) Freescale Semiconductor Break Module (BREAK) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit clears it. ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited ; by break. TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too. DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH RTI ; Restore H register. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Break Module (BREAK) 189 Break Module (BREAK) 17.5.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Reset: 0 R = Reserved Figure 17-7. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 17.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes. 17.6.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set (see 7.7 Low-Power Modes). Clear the SBSW bit by writing logic zero to it. 17.6.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 7.8 SIM Registers. Technical Data 190 MC68H(R)C908JL3 — Rev. 1.1 Break Module (BREAK) Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 18. Electrical Specifications 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.6 5V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 194 18.7 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 18.8 5V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.9 3V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . 197 18.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 18.11 3V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 18.2 Introduction This section contains electrical and timing specifications. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Electrical Specifications 191 Electrical Specifications 18.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to Sections 18.6 and 18.9 for guaranteed operating conditions. Table 18-1. Absolute Maximum Ratings(1) Characteristic Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VIN VSS –0.3 to VDD +0.3 V VDD +VHI VSS –0.3 to +8.5 V I ±25 mA Storage temperature TSTG –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA Mode entry voltage, IRQ1 pin Maximum current per pin excluding VDD and VSS NOTE: 1. Voltages referenced to VSS. NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.) Technical Data 192 MC68H(R)C908JL3 — Rev. 1.1 Electrical Specifications Freescale Semiconductor Electrical Specifications 18.4 Functional Operating Range Table 18-2. Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit TA – 40 to +125 – 40 to +85 °C VDD 5V ± 10% 3V ± 10% V 18.5 Thermal Characteristics Table 18-3. Thermal Characteristics Characteristic Symbol Value Unit 70 70 70 70 °C/W °C/W °C/W °C/W Thermal resistance 20-Pin PDIP 20-Pin SOIC 28-Pin PDIP 28-Pin SOIC θJA I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD × VDD) + PI/O = K/(TJ + 273 °C) W Constant(2) K Average junction temperature Maximum junction temperature PD x (TA + 273 °C) + PD2 × θJA W/°C TJ TA + (PD × θJA) °C TJM 100 °C NOTES: 1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Electrical Specifications 193 Electrical Specifications 18.6 5V DC Electrical Characteristics Table 18-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –2.0mA) PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 VOH VDD –0.8 — — V Output low voltage (ILOAD = 1.6mA) PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 VOL — — 0.4 V Output low voltage (ILOAD = 25mA) PTD6, PTD7 VOL — — 0.5 V LED drives (VOL = 3V) PTA0–PTA5, PTD2, PTD3, PTD6, PTD7 IOL 10 19 25 mA Input high voltage PTA0–PTA6, PTB0–PTB7, PTD0–PTD7, RST, IRQ1, OSC1 VIH 0.7 × VDD — VDD V Input low voltage PTA0–PTA6, PTB0–PTB7, PTD0–PTD7, RST, IRQ1, OSC1 VIL VSS — 0.3 × VDD V VDD supply current Run, fOP = 4MHz(3) Wait (MC68HRC908xxx)(4) Wait (MC68HC908xxx)(4) Stop(5) –40°C to 85°C IDD — — — — 7 1 5 1 10 1.5 5.5 5 mA mA mA µA Digital I/O ports Hi-Z leakage current IIL — — ± 10 µA Input current IIN — — ±1 µA Capacitance Ports (as input or output) COUT CIN — — — — 12 8 pF POR rearm voltage(6) VPOR 0 — 100 mV POR rise time ramp rate(7) RPOR 0.035 — — V/ms Monitor mode entry voltage VDD +VHI 1.5 × VDD — 8.5 V Pullup resistors(8) PTD6, PTD7 RST, IRQ1, PTA0–PTA6 RPU1 RPU2 1.8 16 3.3 26 4.8 36 kΩ kΩ LVI reset voltage VLVR5 3.6 4.0 4.4 V Technical Data 194 MC68H(R)C908JL3 — Rev. 1.1 Electrical Specifications Freescale Semiconductor Electrical Specifications Table 18-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit NOTES: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD. 5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V 18.7 5V Control Timing Table 18-5. Control Timing (5V) Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 8 MHz RST input pulse width low(3) tIRL 750 — ns NOTES: 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Electrical Specifications 195 Electrical Specifications 18.8 5V Oscillator Characteristics Table 18-6. Oscillator Component Specifications (5V) Characteristic Symbol Min Typ Max Unit fOSCXCLK — 10 32 MHz fRCCLK 2 10 12 MHz fOSCXCLK dc — 32 MHz Crystal load capacitance(2) CL — — — Crystal fixed capacitance(2) C1 — 2 × CL — Crystal tuning capacitance(2) C2 — 2 × CL — Feedback bias resistor RB — 10 MΩ — Series resistor(2), (3) RS — — — Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1) RC oscillator external R REXT RC oscillator external C CEXT See Figure 18-1 — 10 — pF NOTES: 1. No more than 10% duty cycle deviation from 50% 2. Consult crystal vendor data sheet 3. Not Required for high frequency crystals RC frequency, fRCCLK (MHz) 14 12 CEXT = 10 pF 10 MCU 5V @ 25°C OSC1 8 6 VDD 4 REXT CEXT 2 0 0 10 20 30 Resistor, REXT (kΩ) 40 50 Figure 18-1. RC vs. Frequency (5V @25°C) Technical Data 196 MC68H(R)C908JL3 — Rev. 1.1 Electrical Specifications Freescale Semiconductor Electrical Specifications 18.9 3V DC Electrical Characteristics Table 18-7. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –1.0mA) PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 VOH VDD – 0.4 — — V Output low voltage (ILOAD = 0.8mA) PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 VOL — — 0.4 V Output low voltage (ILOAD = 20mA) PTD6, PTD7 VOL — — 0.5 V LED drives (VOL = 1.8V) PTA0–PTA5, PTD2, PTD3, PTD6, PTD7 IOL 4 9 12 mA Input high voltage PTA0–PTA6, PTB0–PTB7, PTD0–PTD7, RST, IRQ1, OSC1 VIH 0.7 × VDD — VDD V Input low voltage PTA0–PTA6, PTB0–PTB7, PTD0–PTD7, RST, IRQ1, OSC1 VIL VSS — 0.3 × VDD V VDD supply current Run, fOP = 2MHz(3) Wait (MC68HRC908xxx)(4) Wait (MC68HC908xxx)(4) Stop(5) –40°C to 85°C IDD — — — — 5 1 4 1 8 1.3 4.5 5 mA mA mA µA Digital I/O ports Hi-Z leakage current IIL — — ± 10 µA Input current IIN — — ±1 µA Capacitance Ports (as input or output) COUT CIN — — — — 12 8 pF POR rearm voltage(6) VPOR 0 — 100 mV POR rise time ramp rate(7) RPOR 0.035 — — V/ms Monitor mode entry voltage VDD +VHI 1.5 × VDD — 8.5 V Pullup resistors(8) PTD6, PTD7 RST, IRQ1, PTA0–PTA6 RPU1 RPU2 1.8 16 3.3 26 4.8 36 kΩ kΩ LVI reset voltage VLVR3 2.0 2.4 2.69 V MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Electrical Specifications 197 Electrical Specifications Table 18-7. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit NOTES: 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD. 5. STOP IDD measured with OSC1 grounded, no port pins sourcing current. LVI is disabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0V 18.10 3V Control Timing Table 18-8. Control Timing (3V) Characteristic(1) Symbol Min Max Unit Internal operating frequency(2) fOP — 4 MHz RST input pulse width low(3) tIRL 1.5 — µs NOTES: 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset. Technical Data 198 MC68H(R)C908JL3 — Rev. 1.1 Electrical Specifications Freescale Semiconductor Electrical Specifications 18.11 3V Oscillator Characteristics Table 18-9. Oscillator Component Specifications (3V) Characteristic Symbol Min Typ Max Unit fOSCXCLK — 8 16 MHz fRCCLK 2 8 12 MHz fOSCXCLK dc — 16 MHz Crystal load capacitance(2) CL — — — Crystal fixed capacitance(2) C1 — 2 × CL — Crystal tuning capacitance(2) C2 — 2 × CL — Feedback bias resistor RB — 10 MΩ — Series resistor(2), (3) RS — — — Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1) RC oscillator external R REXT RC oscillator external C CEXT See Figure 18-2 — 10 — pF NOTES: 1. No more than 10% duty cycle deviation from 50% 2. Consult crystal vendor data sheet 3. Not Required for high frequency crystals RC frequency, fRCCLK (MHz) 14 12 CEXT = 10 pF 10 MCU 3V @ 25°C OSC1 8 6 VDD 4 REXT CEXT 2 0 0 10 20 30 Resistor, REXT (kΩ) 40 50 Figure 18-2. RC vs. Frequency (3V @25°C) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Electrical Specifications 199 Electrical Specifications 18.12 Typical Supply Currents 14 12 IDD (mA) 10 8 6 MC68HRC908xxx 4 5.5 V 3.3 V 2 0 0 1 2 3 4 5 6 fOP or fBUS (MHz) 7 8 9 Figure 18-3. Typical Operating IDD, with All Modules Turned On (25 °C) 2 1.75 IDD (mA) 1.50 1.25 1 MC68HRC908xxx 0.75 0.5 5.5 V 3.3 V 0.25 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 Figure 18-4. Typical Wait Mode IDD, with ADC Turned On (25 °C) 0.5 IDD (µA) 0.4 0.3 0.2 MC68HRC908xxx 5.5 V 3.3 V 0.1 0 0 1 2 3 4 5 fOP or fBUS (MHz) 6 7 8 9 Figure 18-5. Typical Stop Mode IDD, with all Modules Disabled (25 °C) Technical Data 200 MC68H(R)C908JL3 — Rev. 1.1 Electrical Specifications Freescale Semiconductor Electrical Specifications 18.13 ADC Characteristics Table 18-10. ADC Characteristics Characteristic Symbol Min Max Unit Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V Input voltages VADIN VSS VDD V Resolution BAD 8 8 Bits Absolute accuracy AAD ± 0.5 ± 1.5 LSB Includes quantization ADC internal clock fADIC 0.5 1.048 MHz tAIC = 1/fADIC, tested only at 1 MHz Conversion range RAD VSS VDD V Power-up time tADPU 16 Conversion time tADC 16 17 tAIC cycles Sample time(1) tADS 5 — tAIC cycles Zero input reading(2) ZADI 00 01 Hex VIN = VSS Full-scale reading(3) FADI FE FF Hex VIN = VDD Input capacitance CADI — (20) 8 pF Not tested — — ±1 µA Input leakage(3) Port B/port D Comments tAIC cycles NOTES: 1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Electrical Specifications 201 Electrical Specifications 18.14 Memory Characteristics Table 18-11. Memory Characteristics Characteristic Symbol Min Max Unit VRDR 1.3 — V — 1 — MHz FLASH read bus clock frequency fRead(1) 32k 8M Hz FLASH page erase time tErase(2) 1 — ms FLASH mass erase time tMErase(3) 4 — ms FLASH PGM/ERASE to HVEN set up time tnvs 10 — µs FLASH high-voltage hold time tnvh 5 — µs FLASH high-voltage hold time (mass erase) tnvhl 100 — µs FLASH program hold time tpgs 5 — µs FLASH program time tPROG 30 40 µs FLASH return to read time trcv(4) 1 — µs FLASH cumulative program hv period tHV(5) — 4 ms — 10k — cycles — 10k — cycles — 10 — years RAM data retention voltage FLASH program bus clock frequency FLASH row erase endurance(6) FLASH row program endurance(7) FLASH data retention time(8) NOTES: 1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH memory. 4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 32) ≤ tHV max. 6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase / program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. Technical Data 202 MC68H(R)C908JL3 — Rev. 1.1 Electrical Specifications Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 19. Mechanical Specifications 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.3 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.4 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.5 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.6 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.2 Introduction This section gives the dimensions for: • 20-pin plastic dual in-line package (case #738) • 20-pin small outline integrated circuit package (case #751D) • 28-pin plastic dual in-line package (case #710) • 28-pin small outline integrated circuit package (case #751F) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, please visit the Freescale website at http://freescale.com. Follow or Worldwide Web on-line instructions to retrieve the current mechanical specifications. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Mechanical Specifications 203 Mechanical Specifications 19.3 20-Pin PDIP –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– DIM A B C D E F G J K L M N K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M T B M M INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 Figure 19-1. 20-Pin PDIP (Case #738) 19.4 20-Pin SOIC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C –T– 18X G K SEATING PLANE DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M Figure 19-2. 20-Pin SOIC (Case #751D) Technical Data 204 MC68H(R)C908JL3 — Rev. 1.1 Mechanical Specifications Freescale Semiconductor Mechanical Specifications 19.5 28-Pin PDIP 28 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 15 B DIM A B C D F G H J K L M N 14 1 L C A N H G F M K D J SEATING PLANE MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0° 15° 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0° 15° 0.020 0.040 Figure 19-3. 28-Pin PDIP (Case #710) 19.6 28-Pin SOIC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A15 28 14X -B1 P 0.010 (0.25) M B M 14 28X D 0.010 (0.25) M T A S B M S R X 45 C 26X -T- G SEATING PLANE K F J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0° 8° 10.01 10.55 0.25 0.75 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0° 8° 0.395 0.415 0.010 0.029 Figure 19-4. 28-Pin SOIC (Case #751F) MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Mechanical Specifications 205 Mechanical Specifications Technical Data 206 MC68H(R)C908JL3 — Rev. 1.1 Mechanical Specifications Freescale Semiconductor Technical Data — MC68H(R)C908JL3 Section 20. Ordering Information 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 20.2 Introduction This section contains ordering numbers for the MC68H(R)C908JL3, MC68H(R)C908JK3, and MC68H(R)C908JK1. MC68H(R)C908JL3 — Rev. 1.1 Freescale Semiconductor Technical Data Ordering Information 207 Ordering Information 20.3 MC Order Numbers Table 20-1. MC Order Numbers MC order number MC68HC908JL3CP MC68HC908JL3CDW MC68HC908JL3MP MC68HC908JL3MDW MC68HRC908JL3CP MC68HRC908JL3CDW MC68HRC908JL3MP MC68HRC908JL3MDW MC68HC908JK3CP MC68HC908JK3CDW MC68HC908JK3MP MC68HC908JK3MDW Oscillator type FLASH memory Package 4096 Bytes 28-pin package Crystal oscillator RC oscillator Crystal oscillator 4096 Bytes MC68HRC908JK3CP MC68HRC908JK3CDW MC68HRC908JK3MP MC68HRC908JK3MDW MC68HC908JK1CP MC68HC908JK1CDW RC oscillator 20-pin package Crystal oscillator 1536 Bytes MC68HRC908JK1CP MC68HRC908JK1CDW RC oscillator Notes: C = –40 °C to +85 °C M = –40 °C to +125 °C (available for VDD = 5V only) P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) Technical Data 208 MC68H(R)C908JL3 — Rev. 1.1 Ordering Information Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. 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