MC908QT1ACDWER

Addendum to MC68HC908QY4A, rev. 3 This addendum introduces a change to this data sheet. Chapter 15 Development Support, Section 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. Changes to: Chapter 15 Development Support, Section 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. An improved security function denies monitor mode entry if five or more of the eight security bytes are $00 (zero bytes). MC68HC908QY4A Data Sheet, Addendum 5/2012 Freescale Semiconductor 1 This page intentionally blank. MC68HC908QY4A Data Sheet, Addendum 5/2012 2 Freescale Semiconductor MC68HC908QY4A MC68HC908QT4A MC68HC908QY2A MC68HC908QT2A MC68HC908QY1A MC68HC908QT1A Data Sheet M68HC08 Microcontrollers MC68HC908QY4A Rev. 3 03/2010 freescale.com MC68HC908QY4A MC68HC908QY2A MC68HC908QY1A MC68HC908QT4A MC68HC908QT2A MC68HC908QT1A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007–2010. All rights reserved. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 3 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level December, 2005 N/A August, 2006 April, 2007 March, 2010 1 2 3 Page Number(s) Description Initial release N/A Added 1.7 Unused Pin Termination. 20 Figure 4-1. Auto Wakeup Interrupt Request Generation Logic — Corrected clock source. 51 4.3 Functional Description — Clarified operation. 52 4.5.1 Wait Mode — Corrected operation details. 53 4.6.4 Configuration Register 2 — Corrected clock source. 55 4.6.5 Configuration Register 1 — Added SSREC bit description. 55 5.2 Functional Description — Corrected clock source. 58 12.1 Introduction — Replaced note. 103 13.7.2 Stop Mode — Corrected clock source. 121 16.12 Supply Current Characteristics — Updated maximum values for SIDD at both 5 V and 3 V. 165 A.2.3 Improved Auto Wakeup Module (AWU) — Corrected clock source. 194 Chapter 3 Analog-to-Digital Converter (ADC10) Module — Renamed ADCSC register to ADSCR to be consistent with development tools. 37 Figure 15-18. Monitor Mode Entry Timing — Changed CGMXCLK to BUSCLKX4 154 16.12 Supply Current Characteristics — Added note 6 below table 165 Chapter 17 Ordering Information and Mechanical Specifications — Updated chapter to include: Table 17-1. Consumer and Industrial Device Numbering System Table 17-2. Automotive Device Numbering System 17.3 Orderable Part Numbering System 17.3.1 Consumer and Industrial Orderable Part Numbering System 17.3.2 Automotive Orderable Part Number System 171 171 172 172 172 Clarify internal oscillator trim register information. 27, 30, 31, 34, 95, 101 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Chapter 11 Oscillator (OSC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 13 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Chapter 14 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 171 Appendix A 908QTA/QYxA Conversion Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 5 List of Chapters MC68HC908QYA/QTA Family Data Sheet, Rev. 3 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 17 18 19 20 20 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Memory Emulation Using FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 28 29 29 30 31 31 32 34 35 Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.1 Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.2 Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.3 Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3.4 Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 39 40 40 40 40 40 41 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 7 Table of Contents 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.4 Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.5 Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 ADC10 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 ADC10 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 ADC10 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 ADC10 Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 ADC10 Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.5 ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 ADC10 Result Low Register (ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 42 43 43 43 44 44 44 44 44 45 45 45 45 45 46 46 46 47 48 48 Chapter 4 Auto Wakeup Module (AWU) 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 51 52 52 53 53 53 53 53 54 54 55 55 Chapter 5 Configuration Register (CONFIG) 5.1 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 8 Freescale Semiconductor Chapter 6 Computer Operating Properly (COP) 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.6.1 6.6.2 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 62 62 62 62 62 62 63 63 63 63 63 63 63 63 Chapter 7 Central Processor Unit (CPU) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 65 66 66 67 67 68 69 69 69 69 69 70 75 Chapter 8 External Interrupt (IRQ) 8.1 8.2 8.3 8.3.1 8.3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 77 79 79 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 9 Table of Contents 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.7.1 8.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 80 80 80 80 80 80 81 Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1.1 MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1.2 MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 KBI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 KBI Input Pins (KBIx:KBI0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.1 Keyboard Status and Control Register (KBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.2 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.3 Keyboard Interrupt Polarity Register (KBIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 83 84 85 86 86 86 86 86 86 87 87 87 87 88 88 Chapter 10 Low-Voltage Inhibit (LVI) 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.5.1 10.5.2 10.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 89 89 90 90 90 90 91 91 91 91 91 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 10 Freescale Semiconductor Chapter 11 Oscillator (OSC) Module 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.1 Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.1.1 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.1.2 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.3 RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.4 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.5 Bus Clock Times 4 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.6 Bus Clock Times 2 (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.2.3 External to Internal Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.3 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.4 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.5 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.6 OSC During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7.1 Oscillator Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7.2 Oscillator Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.8.1 Oscillator Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chapter 12 Input/Output Ports (PORTS) 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.4 12.4.1 12.4.2 12.4.3 12.4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 103 103 104 104 105 106 106 106 107 108 108 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 11 Table of Contents Chapter 13 System Integration Module (SIM) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 109 110 111 111 111 111 111 112 113 113 113 114 114 114 114 114 114 115 115 115 118 118 119 119 119 120 120 120 120 120 121 122 122 123 Chapter 14 Timer Interface Module (TIM) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 125 125 125 126 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 12 Freescale Semiconductor 14.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.1 TIM Channel I/O Pins (TCH1:TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.2 TIM Clock Pin (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 127 128 128 129 129 130 131 131 131 131 131 132 132 132 132 132 134 134 135 137 Chapter 15 Development Support 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 139 139 141 141 141 141 142 142 143 143 143 144 144 144 148 148 149 150 150 150 150 154 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 13 Table of Contents Chapter 16 Electrical Specifications 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14 16.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical 3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 155 156 156 157 158 159 160 161 162 163 165 167 169 170 Chapter 17 Ordering Information and Mechanical Specifications 17.1 17.2 17.3 17.3.1 17.3.2 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Orderable Part Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Consumer and Industrial Orderable Part Numbering System . . . . . . . . . . . . . . . . . . . . . . Automotive Orderable Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 171 172 172 172 172 Appendix A 908QTA/QYxA Conversion Guidelines A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 Benefits of the Enhanced QYxA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1 New Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.2 Enhanced Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.2.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.3 Improved Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.3.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.4 New Power-on Reset Module (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.5 Keyboard Interface Module (KBI) Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.5.1 Registers Affected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.6 On-Chip Routine Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3 Conversion Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.4 Code Changes Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.5 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.6 Differences in Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 191 191 192 193 193 194 194 194 195 195 195 196 196 197 197 MC68HC908QYA/QTA Family Data Sheet, Rev. 3 14 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68HC908QY4A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1. Summary of Device Variations Device FLASH Memory Size ADC Pin Count MC68HC908QT1A MC68HC908QT2A 1536 bytes — 8 pins 1536 bytes 6 channel, 10 bit 8 pins MC68HC908QT4A 4096 bytes 6 channel, 10 bit 8 pins MC68HC908QY1A 1536 bytes — 16 pins MC68HC908QY2A 1536 bytes 6 channel, 10 bit 16 pins MC68HC908QY4A 4096 bytes 6 channel, 10 bit 16 pins 1.2 Features Features include: • High-performance M68HC08 CPU core • Fully upward-compatible object code with M68HC05 Family • 5-V and 3-V operating voltages (VDD) • 8-MHz internal bus operation at 5 V, 4-MHz at 3 V • Trimmable internal oscillator – Software selectable 1 MHz, 2 MHz, or 3.2 MHz internal bus operation – 8-bit trim capability – ±25% untrimmed – Trimmable to approximately 0.4%(1) • Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz and 8–32 MHz • Software configurable input clock from either internal or external source • Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source • On-chip in-application programmable FLASH memory – Internal program/erase voltage generation – Monitor ROM containing user callable program/erase routines – FLASH security(2) 1. See 16.11 Oscillator Characteristics for internal oscillator specifications 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 15 General Description • • • • • • • • • • • • • On-chip random-access memory (RAM) 2-channel, 16-bit timer interface (TIM) module 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) Up to 13 bidirectional input/output (I/O) lines and one input only: – Six shared with KBI – Six shared with ADC – Two shared with TIM – One input only shared with IRQ – High current sink/source capability on all port pins – Selectable pullups on all ports, selectable on an individual bit basis – Three-state ability on all port pins 6-bit keyboard interrupt with wakeup feature (KBI) – Programmable for rising/falling or high/low level detect Low-voltage inhibit (LVI) module features: – Software selectable trip point System protection features: – Computer operating properly (COP) watchdog – Low-voltage detection with reset – Illegal opcode detection with reset – Illegal address detection with reset External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin Master asynchronous reset pin with internal pullup (RST) shared with general-purpose input/output (I/O) pin Memory mapped I/O registers Power saving stop and wait modes MC68HC908QY4A, MC68HC908QY2A and MC68HC908QY1A are available in these packages: – 16-pin plastic dual in-line package (PDIP) – 16-pin small outline integrated circuit (SOIC) package – 16-pin thin shrink small outline packages (TSSOP) MC68HC908QT4A, MC68HC908QT2A and MC68HC908QT1A are available in these packages: – 8-pin PDIP – 8-pin SOIC – 8-pin dual flat no lead (DFN) package Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support MC68HC908QYA/QTA Family Data Sheet, Rev. 3 16 Freescale Semiconductor MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QY4A. PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE VDD POWER SUPPLY VSS RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current sink and source capability PTB[0:7]: Not available on 8-pin devices Figure 1-1. Block Diagram MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 17 General Description 1.4 Pin Assignments The MC68HC908QT4A, MC68H908QT2A, and MC68HC098QT1A are available in 8-pin packages. The MC68HC908QY4A, MC68HC908QY2A, and MC68HC908QY1A are available in 16-pin packages. Figure 1-2 shows the pin assignment for these packages. VDD 1 8 VSS PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 2 7 PTA0/TCH0/AD0/KBI0 6 PTA1/TCH1/KBI1 PTA4/OSC2/AD2/KBI4 3 6 PTA1/TCH1/AD1/KBI1 5 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 4 5 PTA2/IRQ/KBI2/TCLK VDD 1 8 VSS PTA5/OSC1/KBI5 2 7 PTA4/OSC2/KBI4 3 PTA3/RST/KBI3 4 8-PIN ASSIGNMENT MC68HC908QT1A PDIP/SOIC 8-PIN ASSIGNMENT MC68HC908QT2A AND MC68HC908QT4A PDIP/SOIC VDD 1 16 VSS PTB0 PTB7 2 15 PTB0/AD4 14 PTB1 PTB6 3 14 PTB1/AD5 13 PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 4 13 PTA0/TCH0/AD0/KBI0 PTA1/TCH1/KBI1 PTA4/OSC2/AD2/KBI4 5 12 PTA1/TCH1/AD1/KBI1 PTB2 PTB5 6 11 PTB2 PTB3 PTB4 7 10 PTB3 PTA3/RST/KBI3 8 9 VDD 1 16 VSS PTB7 2 15 PTB6 3 PTA5/OSC1/KBI5 4 PTA4/OSC2/KBI4 5 PTB5 6 12 11 PTB4 7 10 PTA3/RST/KBI3 8 9 PTA2/IRQ/KBI2/TCLK 16-PIN ASSIGNMENT MC68HC908QY2A AND MC68HC908QY4A PDIP/SOIC 16-PIN ASSIGNMENT MC68HC908QY1A PDIP/SOIC PTA0/TCH0/KBI0 PTB1 PTB0 VSS VDD PTB7 PTB6 PTA5/OSC1/KBI5 1 2 3 4 5 6 7 8 PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTB4 PTB5 PTA4/OSC2/KBI4 16 15 14 13 12 11 10 9 16-PIN ASSIGNMENT MC68HC908QY1A TSSOP PTA0/TCH0/KBI0 1 PTA2/IRQ/KBI2/TCLK PTA0/TCH0/AD0/KBI0 PTB1/AD5 PTB0/AD4 VSS VDD PTB7 PTB6 PTA5/OSC1/AD3/KBI5 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PTA1/TCH1/AD1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTB4 PTB5 PTA4/OSC2/AD2/KBI4 16-PIN ASSIGNMENT MC68HC908QY2A AND MC68HC908QY4A TSSOP 8 PTA1/TCH1/KBI1 PTA0/TCH0/AD0/KBI0 1 8 PTA1/TCH1/AD1/KBI1 VSS 2 7 PTA2/IRQ/KBI2/TCLK VSS 2 7 PTA2/IRQ/KBI2/TCLK VDD 3 6 PTA3/RST/KBI3 VDD 3 6 PTA3/RST/KBI3 PTA5/OSC1/KB15 4 5 PTA4/OSC2/KBI4 8-PIN ASSIGNMENT MC68HC908QT1A DFN PTA5//OSC1/AD3/KB15 4 5 PTA4/OSC2/AD2/KBI4 8-PIN ASSIGNMENT MC68HC908QT2A AND MC68HC908QT4A DFN Figure 1-2. MCU Pin Assignments MC68HC908QYA/QTA Family Data Sheet, Rev. 3 18 Freescale Semiconductor Pin Functions 1.5 Pin Functions Table 1-2 provides a description of the pin functions. Table 1-2. Pin Functions Pin Name Description Input/Output VDD Power supply Power VSS Power supply ground Power PTA0 PTA1 PTA2 PTA0 — General purpose I/O port Input/Output TCH0 — Timer Channel 0 I/O Input/Output AD0 — A/D channel 0 input Input KBI0 — Keyboard interrupt input 0 Input PTA1 — General purpose I/O port Input/Output TCH1 — Timer Channel 1 I/O Input/Output AD1 — A/D channel 1 input Input KBI1 — Keyboard interrupt input 1 Input PTA2 — General purpose input-only port Input IRQ — External interrupt with programmable pullup and Schmitt trigger input Input KBI2 — Keyboard interrupt input 2 Input TCLK — Timer clock input Input PTA3 — General purpose I/O port PTA3 PTA4 PTA5 PTB0(1) PTB1(1) PTB2PTB7(1) RST — Reset input, active low with internal pullup and Schmitt trigger Input/Output Input KBI3 — Keyboard interrupt input 3 Input PTA4 — General purpose I/O port Input/Output OSC2 —XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) Output Output AD2 — A/D channel 2 input Input KBI4 — Keyboard interrupt input 4 Input PTA5 — General purpose I/O port Input/Output OSC1 — XTAL, RC, or external oscillator input Input AD3 — A/D channel 3 input Input KBI5 — Keyboard interrupt input 5 Input PTB0 — General-purpose I/O port Input/Output AD4 — A/D channel 4 input PTB1 — General-purpose I/O port Input Input/Output AD5 — A/D channel 5 input Input 6 General-purpose I/O port Input/Output 1. The PTB pins are not available on the 8-pin packages. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 19 General Description 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function Priority in Shared Pins Pin Name Highest-to-Lowest Priority Sequence PTA0(1) AD0 → TCH0 → KBI0 → PTA0 PTA1(1) AD1 → TCH1 → KBI1 → PTA1 PTA2 IRQ → TCLK → KBI2 → PTA2 PTA3 RST → KBI3 → PTA3 PTA4(1) OSC2 → AD2 → KBI4 → PTA4 PTA5(1) OSC1 → AD3 → KBI5 → PTA5 PTB0(1) AD4 → PTB0 PTB1(1) AD5 → PTB1 1. When a pin is to be used as an ADC pin, the I/O port function should be left as an input and all other shared modules should be disabled. The ADC does not override additional modules using the pin. 1.7 Unused Pin Termination Input pins and I/O port pins that are not used in the application must be terminated. This prevents excess current caused by floating inputs, and enhances immunity during noise or transient events. Termination methods include: 1. Configuring unused pins as outputs and driving high or low; 2. Configuring unused pins as inputs and enabling internal pull-ups; 3. Configuring unused pins as inputs and using external pull-up or pull-down resistors. Never connect unused pins directly to VDD or VSS. Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method 1 or 2 above are appropriate. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 20 Freescale Semiconductor Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1, register locations are marked with the word Reserved or with the letter R. 2.4 Direct Page Registers Figure 2-2 shows the memory mapped registers of the MC68HC908QYA/QTA Family. Registers with addresses between $0000 and $00FF are considered direct page registers and all instructions including those with direct page addressing modes can access them. Registers between $0100 and $FFFF require non-direct page addressing modes. See Chapter 7 Central Processor Unit (CPU) for more information on addressing modes. MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 21 Memory $0000 ↓ $003F IDIRECT PAGE REGISTERS 64 BYTES $0040 ↓ $007F UNIMPLEMENTED 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $27FF UNIMPLEMENTED 9984 BYTES $2800 ↓ $2A1F AUXILIARY ROM 544 BYTES $2A20 ↓ $2F7D UNIMPLEMENTED 1374 BYTES $2F7E ↓ $2FFF AUXILIARY ROM 130 BYTES $3000 ↓ $EDFF UNIMPLEMENTED 48640 BYTES $EE00 ↓ $FDFF FLASH MEMORY 4096 BYTES RESERVED 2560 BYTES $EE00 ↓ $F7FF $FE00 ↓ $FE1F MISCELLANEOUS REGISTERS 32 BYTES FLASH MEMORY 1536 BYTES $F800 ↓ $FDFF $FE20 ↓ $FF7D MONITOR ROM 350 BYTES $FF7E ↓ $FFAF UNIMPLEMENTED 50BYTES $FFB0 ↓ $FFBD FLASH 14 BYTES $FFBE ↓ $FFC1 MISCELLANEOUS REGISTERS 4 BYTES $FFC2 ↓ $FFCF FLASH 14 BYTES $FFD0 ↓ $FFFF USER VECTORS 48 BYTES MC68HC908QY4A, MC68HC908QT4A Memory Map MC68HC908QT1A, MC68HC908QT2A, MC68HC908QY1A, and MC68HC908QY2A Memory Map Figure 2-1. Memory Map MC68HC908QYA/QTA Family Data Sheet, Rev. 3 22 Freescale Semiconductor Direct Page Registers Addr. Register Name Bit 7 Read: $0000 $0001 $0002 ↓ $0003 $0004 $0005 $0006 ↓ $000A $000B $000C $000D ↓ $0019 $001A $001B $001C Port A Data Register (PTA) Write: See page 104. Reset: Port B Data Register Read: (PTB) Write: See page 106. Reset: R 6 AWUL 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 Bit 0 PTA1 PTA0 PTB1 PTB0 DDRA1 DDRA0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 Unaffected by reset Reserved Data Direction Register A Read: (DDRA) Write: See page 104. Reset: Data Direction Register B Read: (DDRB) Write: See page 107. Reset: 0 R R DDRA5 DDRA4 DDRA3 0 0 0 0 0 0 0 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 0 0 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0 0 0 0 0 0 0 0 0 0 0 KEYF 0 IMASKK MODEK Reserved Port A Input Pullup Enable Read: OSC2EN Register (PTAPUE) Write: See page 105. Reset: 0 Port B Input Pullup Enable Read: PTBPUE7 Register (PTBPUE) Write: See page 108. Reset: 0 0 Reserved Keyboard Status and Read: Control Register (KBSCR) Write: See page 87. Reset: 0 Keyboard Interrupt Read: Enable Register (KBIER) Write: See page 88. Reset: 0 Read: 0 0 Keyboard Interrupt Polarity Register (KBIPR) Write: See page 88. Reset: ACKK 0 0 0 0 0 0 0 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 0 0 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 0 0 0 0 0 0 R = Reserved = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 23 Memory Addr. Register Name Read: $001D $001E IRQ Status and Control Register (INTSCR) Write: See page 81. Reset: Configuration Register 2 Read: (CONFIG2)(1) Write: See page 57. Reset: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 ACK 1 Bit 0 IMASK MODE 0 0 0 0 0 0 0 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN 0 0 0 0 0 0 0 0(2) 1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only. $001F Configuration Register 1 Read: (CONFIG1)(1) Write: See page 58. Reset: COPRS LVISTOP LVIRSTD LVIPWRD LVITRIP SSREC STOP COPD 0 0 0 0 0(2) 0 0 0 PS2 PS1 PS0 1. One-time writable register after each reset. 2. LVITRIP reset to 0 by a power-on reset (POR) only. $0020 $0021 $0022 TIM Status and Control Read: Register (TSC) Write: See page 132. Reset: TOF $0024 $0025 $0026 0 0 1 0 0 0 0 0 TIM Counter Register High Read: (TCNTH) Write: See page 134. Reset: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 TIM Counter Register Low Read: (TCNTL) Write: See page 134. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 TIM Counter Modulo Register High (TMODH) Write: See page 134. Reset: TIM Counter Modulo Read: Register Low (TMODL) Write: See page 134. Reset: TIM Channel 0 Status and Read: Control Register (TSC0) Write: See page 135. Reset: TIM Channel 0 Read: Register High (TCH0H) Write: See page 137. Reset: Read: $0027 0 TSTOP Read: $0023 0 TOIE TIM Channel 0 Register Low (TCH0L) Write: See page 137. Reset: 0 CH0F 0 TRST Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 24 Freescale Semiconductor Direct Page Registers Addr. Register Name Bit 7 Read: $0028 $0029 $002A $002B ↓ $0035 $0036 $0037 $0038 $0039 ↓ $003B $003C TIM Channel 1 Status and Control Register (TSC1) Write: See page 135. Reset: TIM Channel 1 Read: Register High (TCH1H) Write: See page 137. Reset: TIM Channel 1 Read: Register Low (TCH1L) Write: See page 137. Reset: $003E $003F 0 6 5 0 CH1IE 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 2 Bit 1 Bit 0 Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset Reserved Oscillator Status and Read: OSCOPT1 OSCOPT0 Control Register (OSCSC) Write: See page 100. Reset: 0 0 ECGST ICFS1 ICFS0 ECFS1 ECFS0 ECGON 1 0 0 0 0 0 Reserved Oscillator Trim Register (OSCTRIM) See page 101. Read: Write: Reset: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 1 0 0 0 0 0 0 0 COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 AD9 AD8 R R R R R R R R 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R R R R R R R R 0 0 0 0 0 0 0 0 ADLPC ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP ACLKEN 0 0 0 0 0 0 0 0 R = Reserved Reserved ADC10 Status and Control Read: Register (ADSCR) Write: See page 46. Reset: Read: $003D CH1F ADC10 Data Register High (ADRH) Write: See page 48. Reset: ADC10 Data Register Low Read: (ADRL) Write: See page 48. Reset: ADC10 Clock Register Read: (ADCLK) Write: See page 48. Reset: = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 25 Memory Addr. Register Name Bit 7 Read: $FE00 $FE01 $FE02 $FE03 Break Status Register (BSR) Write: See page 143. Reset: $FE05 $FE06 $FE07 $FE08 $FE0A $FE0B R R 3 R 2 1 SBSW R 0 Bit 0 R 0 PIN COP ILOP ILAD MODRST LVI 0 POR: 1 0 0 0 0 0 0 0 Break Auxiliary Read: Register (BRKAR) Write: See page 143. Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCFE R R R R R R R Interrupt Status Register 1 (INT1) Write: See page 119. Reset: IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 2 Read: (INT2) Write: See page 119. Reset: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 3 Read: (INT3) Write: See page 119. Reset: IF22 IF21 IF20 IF19 IF18 IF17 IF16 IF15 R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 HVEN MASS ERASE PGM 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R = Reserved Break Flag Control Read: Register (BFCR) Write: See page 143. Reset: BDCOP 0 Reserved FLASH Control Register Read: (FLCR) Write: See page 29. Reset: Read: $FE09 R 4 Write: Read: $FE04 5 POR SIM Reset Status Register (SRSR) See page 122. Read: R 6 Break Address High Register (BRKH) Write: See page 142. Reset: Break Address low Read: Register (BRKL) Write: See page 142. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 143. Reset: = Unimplemented U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 26 Freescale Semiconductor Direct Page Registers Addr. Register Name Read: $FE0C $FE0D ↓ $FE0F $FFBE $FFBF $FFC0 $FFC1 $FFFF LVI Status Register (LVISR) Write: See page 91. Reset: Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 TRIM2 TRIM1 TRIM0 TRIM2 TRIM1 TRIM0 Reserved FLASH Block Protect Read: Register (FLBPR) Write: See page 34. Reset: Unaffected by reset Reserved Internal Oscillator Trim Read: (Factory Programmed Write: VDD = 3.0 V) Reset: Internal Oscillator Trim Read: (Factory Programmed Write: VDD = 5.0 V) Reset: COP Control Register Read: (COPCTL) Write: See page 63. Reset: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 Unaffected by reset LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5) MC68HC908QYA/QTA Family Data Sheet, Rev. 3 Freescale Semiconductor 27 Memory Table 2-1. Vector Addresses Vector Priority Vector Address Lowest IF22IF16 $FFD0,1$FFDC,D Not used IF15 $FFDE,F ADC conversion complete vector IF14 $FFE0,1 Keyboard vector IF13 — Not used IF12 — Not used IF11 — Not used IF10 — Not used IF9 — Not used IF8 — Not used IF7 — Not used IF6 — Not used IF5 $FFF2,3 TIM overflow vector IF4 $FFF4,5 TIM channel 1 vector IF3 $FFF6,7 TIM channel 0 vector IF2 — IF1 $FFFA,B IRQ vector — $FFFC,D SWI vector — $FFFE,F Reset vector Highest Vector Not used 2.5 Random-Access Memory (RAM) This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait or stop mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HC08 resets the stack pointer to $00FF. In the devices that have RAM above $00FF, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM). LDHX TXS #RamLast+1 ;point one past RAM ;SP