Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9328MXL
Rev. 8, 12/2006
MC9328MXL
Package Information
Plastic Package
Case 1304B-01
(MAPBGA–225)
MC9328MXL
Ordering Information
See Table 1 on page 3
1
Introduction
The i.MX Family of applications processors provides a
leap in performance with an ARM9™ microprocessor
core and highly integrated system functions. The i.MX
family specifically addresses the requirements of the
personal, portable product market by providing
intelligent integrated peripherals, an advanced processor
core, and power management capabilities.
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signals and Connections . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . 17
Functional Description and Application
Information . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Pin-Out and Package Information . . . . . . . . 84
6 Product Documentation . . . . . . . . . . . . . . . . 88
Contact Information . . . . . . . . . . . . . . . Last Page
The MC9328MXL (i.MXL) processor features the
advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules,
which include a USB device, an LCD controller, and an
MMC/SD host controller, support a suite of peripherals
to enhance portable products seeking to provide a rich
multimedia experience. It is packaged in either a
256-contact Mold Array Process-Ball Grid Array
(MAPBGA) or 225-contact MAPBGA package.
Figure 1 shows the functional block diagram of the
i.MXL processor.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved.
Introduction
System Control
JTAG/ICE
Bootstrap
Standard
System I/O
CGM
(PLLx2)
Power
Control
GPIO
Connectivity
MC9328MXL
PWM
MMC/SD
Timer 1 & 2
CPU Complex
Memory Stick®
Host Controller
RTC
ARM9TDMI™
Watchdog
SPI 1 and
SPI 2
UART 1
UART 2
I Cache
AIPI 1
Multimedia
D Cache
VMMU
Multimedia
Accelerator
Interrupt
Controller
Video Port
SSI/I2S
I2C
USB Device
AIPI 2
DMAC
(11 Chnl)
Bus
Control
EIM &
SDRAMC
Human Interface
LCD Controller
Figure 1. i.MXL Functional Block Diagram
1.1
Features
To support a wide variety of applications, the processor offers a robust array of features, including the following:
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ARM920T™ Microprocessor Core
AHB to IP Bus Interfaces (AIPIs)
External Interface Module (EIM)
SDRAM Controller (SDRAMC)
DPLL Clock and Power Control Module
Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
Serial Peripheral Interface (SPI)
Two General-Purpose 32-bit Counters/Timers
Watchdog Timer
Real-Time Clock/Sampling Timer (RTC)
LCD Controller (LCDC)
Pulse-Width Modulation (PWM) Module
Universal Serial Bus (USB) Device
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
Memory Stick® Host Controller (MSHC)
Direct Memory Access Controller (DMAC)
Synchronous Serial Interface and an Inter-IC Sound (SSI/I2S) Module
Inter-IC (I2C) Bus Module
MC9328MXL Technical Data, Rev. 8
2
Freescale Semiconductor
Introduction
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1.2
Video Port
General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Multimedia Accelerator (MMA)
Power Management Features
Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O
256-pin MAPBGA Package
225-contact MAPBGA Package
Target Applications
The i.MXL processor is targeted for advanced information appliances, smart phones, Web browsers,
digital MP3 audio players, handheld computers, and messaging applications.
1.3
Ordering Information
Table 1 provides ordering information.
Table 1. i.MXL Ordering Information
Package Type
Frequency
Temperature
Solderball Type
256-lead MAPBGA
200 MHz
0OC to 70OC
Pb-free
MC9328MXLVM20(R2)
-30 C to 70 C
Pb-free
MC9328MXLDVM20(R2)
0OC to 70OC
Pb-free
MC9328MXLVM15(R2)
-30 C to 70 C
Pb-free
MC9328MXLDVM15(R2)
-40OC to 85OC
Pb-free
MC9328MXLCVM15(R2)
0 C to 70 C
Pb-free
MC9328MXLVP20(R2)
-30OC to 70OC
Pb-free
MC9328MXLDVP20(R2)
0°C to 70°C
Pb-free
MC9328MXLVP15(R2)
-30OC to 70OC
Pb-free
MC9328MXLDVP15(R2)
Pb-free
MC9328MXLCVP15(R2)
O
150 MHz
O
225-lead MAPBGA
200 MHz
150 MHz
O
O
O
O
O
O
-40 C to 85 C
1.4
Order Number
Conventions
This document uses the following conventions:
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•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
A signal is an electronic construct whose state conveys or changes in state convey information.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
3
Signals and Connections
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2
A pin is an external physical connection. The same pin can be used to connect a number of signals.
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
Signals and Connections
Table 2 identifies and describes the i.MXL processor signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. i.MXL Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
Address bus signals
D[31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16].
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8].
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
OE
Memory Output Enable—Active low output enables external data bus.
CS [5:0]
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input
signal by external DRAM.
DTACK
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 clock counts have elapsed.
MC9328MXL Technical Data, Rev. 8
4
Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MXL processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals
are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
SDIBA [3:0]
SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on
SDRAM cycles.
DQM [3:0]
SDRAM data enable
CSD0
SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable
by programming the system control register.
CSD1
SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by
programming the system control register. By default, CSD1 is selected, so it can be used as boot
chip-select by properly configuring BOOT [3:0] input pins.
RAS
SDRAM Row Address Select signal
CAS
SDRAM Column Address Select signal
SDWE
SDRAM Write Enable signal
SDCKE0
SDRAM Clock Enable 0
SDCKE1
SDRAM Clock Enable 1
SDCLK
SDRAM Clock
RESET_SF
Not Used
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut
down.
XTAL16M
Crystal output
EXTAL32K
32 kHz crystal input
XTAL32K
32 kHz crystal output
CLKO
Clock Out signal selected from internal clock signals.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
5
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
DMA
DMA_REQ
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
Line pulse or H sync
LSCLK
Shift clock
ACD/OE
Alternate crystal direction/output enable.
CONTRAST
This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR
Program horizontal scan direction (Sharp panel dedicated signal).
PS
Control signal output for source driver (Sharp panel dedicated signal).
MC9328MXL Technical Data, Rev. 8
6
Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
CLS
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1 and SPI 2
SPI1_MOSI
Master Out/Slave In
SPI1_MISO
Slave In/Master Out
SPI1_SS
Slave Select (Selectable polarity)
SPI1_SCLK
Serial Clock
SPI1_SPI_RDY
Serial Data Ready
SPI2_TXD
SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
SPI2_RXD
SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
SPI2_SS
SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative
signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the
MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
SPI2_SCLK
SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative
signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the
MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT
Timer 2 Output
USB Device
USBD_VMO
USB Minus Output
USBD_VPO
USB Plus Output
USBD_VM
USB Minus Input
USBD_VP
USB Plus Input
USBD_SUSPND
USB Suspend Output
USBD_RCV
USB Receive Data
USBD_ROE
USB OE
USBD_AFE
USB Analog Front End Enable
Secure Digital Interface
SD_CMD
SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-up
enable register, a 4.7K–69K external pull up resistor must be added.
SD_CLK
MMC Output Clock
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
7
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
SD_DAT [3:0]
Function/Notes
Data—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable
register, a 50K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS
Memory Stick Bus State (Output)—Serial bus control signal
MS_SDIO
Memory Stick Serial Data (Input/Output)
MS_SCLKO
Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider
MS_SCLKI
Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is only for test
purposes, not for use in application mode.
MS_PI0
General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
MS_PI1
General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD
Receive Data
UART1_TXD
Transmit Data
UART1_RTS
Request to Send
UART1_CTS
Clear to Send
UART2_RXD
Receive Data
UART2_TXD
Transmit Data
UART2_RTS
Request to Send
UART2_CTS
Clear to Send
UART2_DSR
Data Set Ready
UART2_RI
Ring Indicator
UART2_DCD
Data Carrier Detect
UART2_DTR
Data Terminal Ready
Serial Audio Port – SSI (configurable to I2S protocol)
SSI_TXDAT
Transmit Data
SSI_RXDAT
Receive Data
SSI_TXCLK
Transmit Serial Clock
SSI_RXCLK
Receive Serial Clock
SSI_TXFS
Transmit Frame Sync
SSI_RXFS
Receive Frame Sync
I2C
I2C_SCL
I2C Clock
I2C_SDA
I2C Data
MC9328MXL Technical Data, Rev. 8
8
Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
PWM
PWMO
PWM Output
Test Function
TRISTATE
Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input
with a 1 k ohm resistor to ground. (TRI-STATE® is a registered trademark of National Semiconductor.)
Digital Supply Pins
NVDD
Digital Supply for the I/O pins
NVSS
Digital Ground for the I/O pins
Supply Pins – Analog Modules
AVDD
Supply for analog blocks
Internal Power Supply
QVDD
Power supply pins for silicon internal circuitry
QVSS
Ground pins for silicon internal circuitry
2.1
I/O Pads Power Supply and Signal Multiplexing Scheme
This section describes detailed information about both the power supply for each I/O pin and its function
multiplexing scheme. The user can reference information provided in Table 6 on page 18 to configure the
power supply scheme for each device in the system (memory and external peripherals). The function
multiplexing information also shown in Table 6 allows the user to select the function of each pin by
configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions.
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme
Primary
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
Signal
Dir
NVDD1
D2
B1
A24
O
NVDD1
C1
C2
D31
I/O
NVDD1
D1
C1
A23
O
NVDD1
E3
D2
D30
I/O
NVDD1
E2
D1
A22
O
NVDD1
E4
D3
D29
I/O
NVDD1
E1
E2
A21
O
NVDD1
F3
E3
D28
I/O
Alternate
PullUp
GPIO
AIN
BIN
AOUT
Default
Signal
Dir
Mux
Pull
-Up
ETMTRAC
ESYNC
O
PA0
69K
ETMTRAC
ECLK
O
PA31
69K
A23
ETMPIPE
STAT2
O
PA30
69K
A22
ETMPIPE
STAT1
O
PA29
69K
A21
SPI2_
SCLK
A24
69K
69K
69K
69K
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
9
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
Signal
Dir
NVDD1
F1
E1
A20
O
NVDD1
F4
F2
D27
I/O
NVDD1
F2
F4
A19
O
NVDD1
G3
E4
D26
I/O
NVDD1
G2
F1
A18
O
NVDD1
G4
F3
D25
I/O
NVDD1
G1
G2
A17
O
NVDD1
H4
G3
D24
I/O
NVDD1
H2
F5
A16
O
NVDD1
H3
G4
D23
I/O
NVDD1
H1
G1
A15
O
NVDD1
H5
H2
D22
I/O
NVDD1
J1
H3
A14
O
NVDD1
J3
G5
D21
I/O
NVDD1
K1
H1
A13
O
NVDD1
J4
H4
D20
I/O
NVDD1
J2
J1
A12
O
NVDD1
K4
J4
D19
I/O
NVDD1
K2
J2
A11
O
NVDD1
L4
J3
D18
I/O
NVDD1
L1
K1
A10
O
NVDD1
L3
K4
D17
I/O
NVDD1
L2
K3
A9
O
NVDD1
M1
K2
D16
I/O
NVDD1
N1
L1
A8
O
NVDD1
M2
L4
D15
I/O
NVDD1
N2
L2
A7
O
NVDD1
P1
L5
D14
I/O
NVDD1
R1
M4
A6
O
NVDD1
M3
L3
D13
I/O
NVDD1
P2
M1
A5
O
NVDD1
N3
M2
D12
I/O
NVDD1
P3
N1
A4
O
NVDD1
R2
M3
D11
I/O
Alternate
PullUp
GPIO
AIN
BIN
AOUT
Default
Signal
Dir
Mux
Pull
-Up
ETMPIPE
STAT0
O
PA28
69K
A20
ETMTRAC
EPKT3
O
PA27
69K
A19
ETMTRAC
EPKT2
O
PA26
69K
A18
ETMTRAC
EPKT1
O
PA25
69K
A17
ETMTRAC
EPKT0
O
PA24
69K
A16
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
MC9328MXL Technical Data, Rev. 8
10
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
Signal
Dir
NVDD1
N4
P3
EB0
O
NVDD1
M4
N3
D10
I/O
NVDD1
P4
P1
A3
O
NVDD1
R3
N2
EB1
O
NVDD1
N5
P2
D9
I/O
NVDD1
R4
R1
EB2
O
NVDD1
P5
T2
A2
O
NVDD1
M5
R2
EB3
O
NVDD1
N6
R5
D8
I/O
NVDD1
R5
T3
OE
O
NVDD1
P6
R3
A1
O
Alternate
PullUp
Signal
Dir
GPIO
AIN
BIN
AOUT
Default
Mux
Pull
-Up
PA23
69K
PA23
69K
69K
69K
NVDD1
L7
T4
CS5
O
NVDD1
R6
N4
D7
I/O
NVDD1
M7
R4
CS4
O
PA22
69K
PA22
NVDD1
R7
N5
A0
O
PA21
69K
A0
NVDD1
N7
P4
CS3
O
NVDD1
P7
P5
D6
I/O
NVDD1
K3
T5
CS2
O
NVDD1
R8
M5
SDCLK
O
NVDD1
M8
T6
CS1
O
NVDD1
N8
T7
CS0
O
NVDD1
P8
R6
D5
I/O
NVDD1
L9
P6
ECB
I
NVDD1
R9
N6
D4
I/O
NVDD1
R10
R7
LBA
O
NVDD1
R11
P8
D3
I/O
NVDD1
M9
R8
BCLK
NVDD1
L8
P7
D2
NVDD1
N9
N7
PA17
NVDD1
K10
N8
D1
NVDD1
M10
M7
RW
NVDD1
P10
T8
MA11
O
NVDD1
P9
M8
MA10
O
NVDD1
N10
R9
D0
I/O
NVDD1
R12
P9
DQM3
O
I/O
I/O
69K
CSD1
CSD1
CSD0
CSD0
69K
69K
ETMTRAC
EPKT7
PA20
69K
ECB
ETMTRAC
EPKT6
PA19
69K
LBA
ETMTRAC
EPKT5
PA18
69K
BCLK
ETMTRAC
EPKT4
PA17
69K
69K
69K
69K
SPI2_
SS
DTACK
PA17
69K
69K
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
11
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
Signal
Dir
NVDD1
N11
T9
DQM2
O
NVDD1
P11
N9
DQM1
O
NVDD1
N12
R10
DQM0
O
NVDD1
P12
M9
RAS
O
NVDD1
R13
L8
CAS
O
NVDD1
R14
T10
SDWE
O
NVDD1
N13
R11
SDCKE0
O
NVDD1
P13
P10
SDCKE1
O
NVDD1
P15
N10
RESET_S
F
O
NVDD1
P14
T11
CLKO
O
AVDD1
R15
T12
AVDD1
Static
QVDD2
M13
R15
QVDD2
Static
AVDD1
N15
P13
TRST
I
AVDD1
N14
T13
TRISTATE
I
Alternate
PullUp
Signal
Dir
GPIO
Mux
Pull
-Up
AIN
BIN
AOUT
Default
69K
1
AVDD1
M15
T14
EXTAL16
M
I
AVDD1
L14
T15
XTAL16M
O
AVDD1
L15
R16
EXTAL32
K
I
AVDD1
K15
P16
XTAL32K
O
AVDD1
M14
M10
RESET_I
I
69K
N2
AVDD1
K14
N11
RESET_O
UT
O
AVDD1
L12
R12
POR2
I
AVDD1
K13
M11
BIG_ENDI
I
AN3
AVDD1
M12
P11
BOOT33
I
AVDD1
K11
N12
BOOT23
I
AVDD1
J14
R13
BOOT13
I
AVDD1
J15
P12
BOOT03
I
NVDD2
J13
R14
TDO4
O
NVDD2
H15
N15
TMS
I
69K
NVDD2
J12
L9
TCK
I
69K
NVDD2
K12
N16
TDI
I
69K
NVDD2
J11
P14
I2C_SCL
O
PA16
69K
PA16
NVDD2
H14
P15
I2C_SDA
I/O
PA15
69K
PA15
MC9328MXL Technical Data, Rev. 8
12
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
NVDD2
H13
NVDD2
Primary
Alternate
GPIO
AIN
BIN
AOUT
Default
Mux
Pull
-Up
I
PA14
69K
PA14
CSI_HSY
NC
I
PA13
69K
PA13
M14
CSI_VSY
NC
I
PA12
69K
PA12
G13
N14
CSI_D7
I
PA11
69K
PA11
NVDD2
J10
M15
CSI_D6
I
PA10
69K
PA10
NVDD2
G15
M16
CSI_D5
I
PA9
69K
PA9
NVDD2
F15
M12
CSI_D4
I
PA8
69K
PA8
NVDD2
G12
L16
CSI_D3
I
PA7
69K
PA7
NVDD2
F14
L15
CSI_D2
I
PA6
69K
PA6
NVDD2
H11
L14
CSI_D1
I
PA5
69K
PA5
NVDD2
E14
L13
CSI_D0
I
PA4
69K
PA4
NVDD2
E15
L12
CSI_MCL
K
O
PA3
69K
PA3
NVDD2
G11
L11
PWMO
O
PA2
69K
PA2
NVDD2
E13
L10
TIN
I
PA1
69K
NVDD2
D14
K15
TMR2OUT
O
PD31
69K
NVDD2
F13
K16
LD15
O
PD30
69K
PD30
NVDD2
F12
K14
LD14
O
PD29
69K
PD29
NVDD2
D15
K13
LD13
O
PD28
69K
PD28
NVDD2
C14
K12
LD12
O
PD27
69K
PD27
NVDD2
D13
J14
LD11
O
PD26
69K
PD26
NVDD2
E12
K11
LD10
O
PD25
69K
PD25
NVDD2
C13
H15
LD9
O
PD24
69K
PD24
NVDD2
C12
J13
LD8
O
PD23
69K
PD23
NVDD2
B15
J12
LD7
O
PD22
69K
PD22
NVDD2
B14
J11
LD6
O
PD21
69K
PD21
NVDD2
A15
H14
LD5
O
PD20
69K
PD20
NVDD2
A14
H13
LD4
O
PD19
69K
PD19
NVDD2
B13
H16
LD3
O
PD18
69K
PD18
NVDD2
A13
H12
LD2
O
PD17
69K
PD17
NVDD2
D12
G16
LD1
O
PD16
69K
PD16
NVDD2
B12
H11
LD0
O
PD15
69K
PD15
NVDD2
C11
G15
FLM/VSY
NC
O
PD14
69K
PD14
Signal
Dir
N13
CSI_PIXC
LK
G14
M13
NVDD2
H12
NVDD2
PullUp
Signal
Dir
SPI2_
RXD_0
SPI2_
TXD
PA1
PD31
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
13
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
NVDD2
D11
G14
Primary
Alternate
GPIO
AIN
BIN
AOUT
Default
Mux
Pull
-Up
O
PD13
69K
PD13
Signal
Dir
LP/HSYN
C
PullUp
Signal
Dir
NVDD2
E11
G13
ACD/OE
O
PD12
69K
PD12
NVDD2
C10
G12
CONTRA
ST
O
PD11
69K
PD11
NVDD2
B11
F16
SPL_SPR
O
UART2_D
SR
O
PD10
69K
NVDD2
A12
H10
PS
O
UART2_RI
O
PD9
69K
NVDD2
F10
G11
CLS
O
UART2_D
CD
O
PD8
69K
SPI2_
SS
PD8
NVDD2
A11
F12
REV
O
UART2_D
TR
I
PD7
69K
SPI2_
SCLK
PD7
NVDD2
B10
F15
LSCLK
O
PD6
69K
PD6
NVDD3
D10
G9
SPI1_MO
SI
I/O
PC17
69K
PC17
NVDD3
E10
F9
SPI1_MIS
O
I/O
PC16
69K
PC16
NVDD3
B9
E9
SPI1_SS
I/O
PC15
69K
PC15
NVDD3
A10
B9
SPI1_SCL
K
I/O
PC14
69K
PC14
NVDD3
A9
D9
SPI1_SPI
_RDY
I/O
PC13
69K
NVDD3
E8
A9
UART1_R
XD
I
PC12
69K
PC12
NVDD3
B8
C9
UART1_T
XD
O
PC11
69K
PC11
NVDD3
C9
A8
UART1_R
TS
I
PC10
69K
PC10
NVDD3
E9
G8
UART1_C
TS
O
PC9
69K
PC9
NVDD3
A8
B8
SSI_TXCL
K
I/O
PC8
69K
PC8
NVDD3
C8
F8
SSI_TXFS
I/O
PC7
69K
PC7
NVDD3
F9
E8
SSI_TXDA
T
O
PC6
69K
PC6
NVDD3
B7
D8
SSI_RXD
AT
I
PC5
69K
PC5
NVDD3
F8
B7
SSI_RXCL
K
I
PC4
69K
PC4
NVDD3
A7
C8
SSI_RXFS
I
PC3
69K
PC3
NVDD4
C7
C7
UART2_R
XD
I
PB31
69K
PB31
SPI2_
TXD
PD10
SPI2_
RXD_1
DMA_REQ
PD9
PC13
MC9328MXL Technical Data, Rev. 8
14
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
NVDD4
D8
NVDD4
Primary
Alternate
GPIO
AIN
BIN
AOUT
Default
Mux
Pull
-Up
O
PB30
69K
PB30
UART2_R
TS
I
PB29
69K
PB29
C6
UART2_C
TS
O
PB28
69K
PB28
B6
D7
USBD_VM
O
O
PB27
69K
PB27
NVDD4
C6
D6
USBD_VP
O
O
PB26
69K
PB26
NVDD4
A6
E6
USBD_VM
I
PB25
69K
PB25
NVDD4
D6
B6
USBD_VP
I
PB24
69K
PB24
NVDD4
A5
D5
USBD_SU
SPND
O
PB23
69K
PB23
NVDD4
B5
C5
USBD_RC
V
I/O
PB22
69K
PB22
NVDD4
A4
B5
USBD_RO
E
O
PB21
69K
PB21
NVDD4
B4
A5
USBD_AF
E
O
PB20
69K
PB20
NVDD4
A3
G7
PB19
I/O
69K
PB19
NVDD4
C4
F6
PB18
I/O
69K
PB18
NVDD4
D4
G6
PB17
O
69K
PB17
NVDD4
B3
B4
PB16
I
69K
PB16
Signal
Dir
F7
UART2_T
XD
E7
E7
NVDD4
F7
NVDD4
PullUp
Signal
Dir
NVDD4
A2
C4
PB15
I
69K
PB15
NVDD4
C3
D4
PB14
I
69K
PB14
NVDD4
A1
B3
SD_CMD
I/O
MS_BS
PB13
69K
PB13
NVDD4
B2
A3
SD_CLK
O
MS_SCLK
O
PB12
69K
PB12
NVDD4
B1
A2
SD_DAT3
I/O
MS_SDIO
PB11
69K
(pull
down)
PB11
NVDD4
C5
E5
SD_DAT2
I/O
MS_SCLK
I
PB10
69K
PB10
NVDD4
D3
B2
SD_DAT1
I/O
MS_PI1
PB9
69K
PB9
NVDD4
C2
C3
SD_DAT0
I/O
MS_PI0
PB8
69K
PB8
NVDD1
NVDD1
QVDD1
D5
K8
NVDD1
Static
G6
A1
NVSS
Static
E5
H5
NVDD1
Static
H6
T1
NVSS
Static
J8
H9
QVDD1
Static
E6
H8
QVSS
Static
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
15
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
I/O Supply
Voltage
225
BGA
Ball
256
BGA
Ball
Signal
Dir
NVDD1
F5
J5
NVDD
Static
J6
K6
NVSS
Static
G5
K5
NVDD1
Static
K6
M6
NVSS
Static
J5
H6
NVDD1
Static
H7
J7
NVSS
Static
NVDD1
K5
L6
NVDD1
Static
J7
J7
NVSS
Static
NVDD1
L5
L6
NVDD1
Static
G8
K7
NVSS
Static
L5
J8
NVDD1
Static
NVDD1
NVDD1
NVDD1
NVDD2
QVDD3
NVDD2
QVDD4
NVDD3
H8
L7
NVSS
Static
K7
T16
QVSS
Static
H10
K10
NVDD2
Static
G9
J10
NVSS
Static
F11
J15
QVDD3
Static
G10
J16
QVSS
Static
C15
K9
NVDD2
Static
H9
J9
NVSS
Static
D7
A13
QVDD4
Static
L13
B13
QVSS
Static
D9
A10
NVDD3
Static
J9
A7
NVSS
Static
K9
A4
NVSS
Static
NVDD4
G7
A6
NVDD4
Static
NVDD1
F6
NVDD1
Static
NVDD1
L6
NVDD1
Static
NVDD1
M6
NVDD1
Static
NVDD1
K8
NVDD1
Static
L10
NVSS
Static
L11
NVSS
Static
M11
NVSS
Static
Alternate
PullUp
Signal
Dir
GPIO
Mux
Pull
-Up
AIN
BIN
AOUT
Default
1
Pull down this input with 1KΩ resistor to GND.
External circuit required to drive this input.
3 Tie this input high (to AVDD) or pull down with 1KΩ resistor to GND.
4 Pull up this output with a resistor to NVDD2.
2
MC9328MXL Technical Data, Rev. 8
16
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
This section contains the electrical specifications and timing diagrams for the i.MXL processor.
3.1
Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the
device may occur. Functional operation should be restricted to the limits listed in Recommended Operating
Range Table 5 on page 18 or the DC Characteristics table.
Table 4. Maximum Ratings
Symbol
Rating
Minimum
Maximum
Unit
NVDD
DC I/O Supply Voltage
-0.3
3.3
V
QVDD
DC Internal (core = 150 MHz) Supply Voltage
-0.3
1.9
V
QVDD
DC Internal (core = 200 MHz) Supply Voltage
-0.3
2.0
V
AVDD
DC Analog Supply Voltage
-0.3
3.3
V
DC Bluetooth Supply Voltage
-0.3
3.3
V
BTRFVDD
VESD_HBM
ESD immunity with HBM (human body model)
–
2000
V
VESD_MM
ESD immunity with MM (machine model)
–
100
V
Latch-up immunity
–
200
mA
ILatchup
Test
Storage temperature
-55
150
°C
Pmax
Power Consumption
8001
13002
mW
A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM®
core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
2 A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the
ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS
application at 200MHz, and where the whole image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V,
therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with
each toggle GPIO consuming 4mA.
1
3.2
Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXL
processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are
used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of
VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply
voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
17
Electrical Characteristics
Table 5. Recommended Operating Range
Symbol
Rating
Minimum
Maximum
Unit
0
70
°C
TA
Operating temperature range
MC9328MXLVM20/MC9328MXLVM15
MC9328MXLVP20/MC9328MXLVP15
TA
Operating temperature range
MC9328MXLDVM20/MC9328MXLDVM15
MC9328MXLDVP20/MC9328MXLDVP15
-30
70
°C
TA
Operating temperature range
MC9328MXLCVM15/
MC9328MXLCVP15
-40
85
°C
NVDD
I/O supply voltage (if using MSHC, CSI, SPI, LCD, and USBd which are
only 3 V interfaces)
2.70
3.30
V
NVDD
I/O supply voltage (if not using the peripherals listed above)
1.70
3.30
V
QVDD
Internal supply voltage (Core = 150 MHz)
1.70
1.90
V
QVDD
Internal supply voltage (Core = 200 MHz)
1.80
2.00
V
AVDD
Analog supply voltage
1.70
3.30
V
3.3
Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the “Power-Up Sequence” section of
application note AN2537 on the i.MX applications processor website.
3.4
DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the i.MXL processor.
Table 6. Maximum and Minimum DC Characteristics
Number or
Symbol
Min
Typical
Max
Unit
Full running operating current at 1.8V for QVDD, 3.3V for
NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4
decoding playback from external memory card to both
external SSI audio decoder and driving TFT display panel,
and OS with MMU enabled memory system is running on
external SDRAM).
–
QVDD at
1.8V = 120mA;
NVDD+AVDD at
3.0V = 30mA
–
mA
Sidd1
Standby current
(Core = 150 MHz, QVDD = 1.8V, temp = 25°C)
–
25
–
μA
Sidd2
Standby current
(Core = 150 MHz, QVDD = 1.8V, temp = 55°C)
–
45
–
μA
Sidd3
Standby current
(Core = 150 MHz, QVDD = 2.0V, temp = 25°C)
–
35
–
μA
Sidd4
Standby current
(Core = 150 MHz, QVDD = 2.0V, temp = 55°C)
–
60
–
μA
Iop
Parameter
MC9328MXL Technical Data, Rev. 8
18
Freescale Semiconductor
Electrical Characteristics
Table 6. Maximum and Minimum DC Characteristics (Continued)
Number or
Symbol
Parameter
Min
Typical
Max
Unit
VIH
Input high voltage
0.7VDD
–
Vdd+0.2
V
VIL
Input low voltage
–
–
0.4
V
VOH
Output high voltage (IOH = 2.0 mA)
0.7VDD
–
Vdd
V
VOL
Output low voltage (IOL = -2.5 mA)
–
–
0.4
V
IIL
Input low leakage current
(VIN = GND, no pull-up or pull-down)
–
–
±1
μA
IIH
Input high leakage current
(VIN = VDD, no pull-up or pull-down)
–
–
±1
μA
IOH
Output high current
(VOH = 0.8VDD, VDD = 1.8V)
4.0
–
–
mA
IOL
Output low current
(VOL = 0.4V, VDD = 1.8V)
-4.0
–
–
mA
IOZ
Output leakage current
(Vout = VDD, output is high impedance)
–
–
±5
μA
Ci
Input capacitance
–
–
5
pF
Co
Output capacitance
–
–
5
pF
3.5
AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an
operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All
timing is measured at 30 pF loading.
Table 7. Tristate Signal Timing
Pin
TRISTATE
Parameter
Minimum
Maximum
Unit
–
20.8
ns
Time from TRISTATE activate until I/O becomes Hi-Z
Table 8. 32k/16M Oscillator Signal Timing
Parameter
EXTAL32k input jitter (peak to peak)
EXTAL32k startup time
EXTAL16M input jitter (peak to peak) 1
EXTAL16M startup time 1
1
Minimum
RMS
Maximum
Unit
–
5
20
ns
800
–
–
ms
–
TBD
TBD
–
TBD
–
–
–
The 16 MHz oscillator is not recommended for use in new designs.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
19
Functional Description and Application Information
4
Functional Description and Application Information
This section provides the electrical information including and timing diagrams for the individual modules
of the i.MXL.
4.1
Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
• 32-bit data field
• 7-bit address field
• A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
in Figure 2.
2a
1
2b
3a
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
Valid Data
Valid Data
4a
4b
Figure 2. Trace Port Timing Diagram
Table 9. Trace Port Timing Diagram Parameter Table
1.8 ± 0.1 V
Ref No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
0
85
0
100
MHz
2a
Clock high time
1.3
–
2
–
ns
2b
Clock low time
3
–
2
–
ns
3a
Clock rise time
–
4
–
3
ns
3b
Clock fall time
–
3
–
3
ns
MC9328MXL Technical Data, Rev. 8
20
Freescale Semiconductor
Functional Description and Application Information
Table 9. Trace Port Timing Diagram Parameter Table (Continued)
1.8 ± 0.1 V
Ref No.
4.2
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
4a
Output hold time
2.28
–
2
–
ns
4b
Output setup time
3.42
–
3
–
ns
DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
5
–
100
MHz
5
–
30
MHz
DPLL input clock freq range
Vcc = 1.8V
Pre-divider output clock
freq range
Vcc = 1.8V
DPLL output clock freq range
Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor (MF)
Includes both integer and fractional parts
5
–
15
–
MF integer part
–
5
–
15
–
MF numerator
Should be less than the denominator
0
–
1022
–
MF denominator
–
1
–
1023
–
Pre-multiplier lock-in time
–
–
–
312.5
μsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
250
280
(56 μs)
300
Tref
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
220
250
(50 μs)
270
Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
300
350
(70 μs)
400
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
270
320
(64 μs)
370
Tref
Freq jitter (p-p)
–
–
0.005
(0.01%)
0.01
2•Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
1.5
ns
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
–
–
4
mW
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
21
Functional Description and Application Information
4.3
Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
90% AVDD
1
10% AVDD
POR
2
RESET_POR
Exact 300ms
3
7 cycles @ CLK32
RESET_DRAM
4
HRESET
14 cycles @ CLK32
RESET_OUT
CLK32
HCLK
Figure 3. Timing Relationship with POR
5
RESET_IN
14 cycles @ CLK32
HRESET
RESET_OUT
4
6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
MC9328MXL Technical Data, Rev. 8
22
Freescale Semiconductor
Functional Description and Application Information
Table 11. Reset Module Timing Parameter Table
1.8 ± 0.1 V
Ref
No.
1
3.0 ± 0.3 V
Parameter
Unit
Min
Max
Min
Max
note1
–
note1
–
–
300
300
300
300
ms
1
Width of input POWER_ON_RESET
2
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
3
7K to 32K-cycle stretcher for SDRAM reset
7
7
7
7
Cycles of
CLK32
4
14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
14
14
14
14
Cycles of
CLK32
5
Width of external hard-reset RESET_IN
4
–
4
–
Cycles of
CLK32
6
4K to 32K-cycle qualifier
4
4
4
4
Cycles of
CLK32
POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal
tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals
for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals.
Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in
calculating timing for the start-up process.
4.4
External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the i.MXL processor,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 12 defines the parameters of signals.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
23
Functional Description and Application Information
(HCLK) Bus Clock
1a
1b
2a
2b
3a
3b
Address
Chip-select
Read (Write)
4a
OE (rising edge)
4b
4c
OE (falling edge)
4d
5a
EB (rising edge)
5b
5c
EB (falling edge)
5d
6a
LBA (negated falling edge)
6b
6a
LBA (negated rising edge)
6c
7a
BCLK (burst clock) - rising edge
7b
7c
7d
BCLK (burst clock) - falling edge
8b
Read Data
9a
8a
9b
Write Data (negated falling)
9a
9c
Write Data (negated rising)
10a
DTACK_B
10a
Figure 5. EIM Bus Timing Diagram
Table 12. EIM Bus Timing Parameter Table
1.8 ± 0.1 V
Ref No.
3.0 ± 0.3 V
Parameter
Unit
Min
Typical
Max
Min
Typical
Max
1a
Clock fall to address valid
2.48
3.31
9.11
2.4
3.2
8.8
ns
1b
Clock fall to address invalid
1.55
2.48
5.69
1.5
2.4
5.5
ns
2a
Clock fall to chip-select valid
2.69
3.31
7.87
2.6
3.2
7.6
ns
2b
Clock fall to chip-select invalid
1.55
2.48
6.31
1.5
2.4
6.1
ns
3a
Clock fall to Read (Write) Valid
1.35
2.79
6.52
1.3
2.7
6.3
ns
3b
Clock fall to Read (Write) Invalid
1.86
2.59
6.11
1.8
2.5
5.9
ns
MC9328MXL Technical Data, Rev. 8
24
Freescale Semiconductor
Functional Description and Application Information
Table 12. EIM Bus Timing Parameter Table (Continued)
1.8 ± 0.1 V
Ref No.
4a
Unit
Clock1 rise to Output Enable Valid
1
Min
Typical
Max
Min
Typical
Max
2.32
2.62
6.85
2.3
2.6
6.8
ns
4b
Clock rise to Output Enable Invalid
2.11
2.52
6.55
2.1
2.5
6.5
ns
4c
Clock1 fall to Output Enable Valid
2.38
2.69
7.04
2.3
2.6
6.8
ns
1
4d
Clock fall to Output Enable Invalid
2.17
2.59
6.73
2.1
2.5
6.5
ns
5a
Clock1 rise to Enable Bytes Valid
1.91
2.52
5.54
1.9
2.5
5.5
ns
1
5b
Clock rise to Enable Bytes Invalid
1.81
2.42
5.24
1.8
2.4
5.2
ns
5c
Clock1 fall to Enable Bytes Valid
1.97
2.59
5.69
1.9
2.5
5.5
ns
5d
Clock1
1.76
2.48
5.38
1.7
2.4
5.2
ns
6a
Clock1 fall to Load Burst Address Valid
2.07
2.79
6.73
2.0
2.7
6.5
ns
6b
Clock1
1.97
2.79
6.83
1.9
2.7
6.6
ns
6c
Clock1 rise to Load Burst Address Invalid
1.91
2.62
6.45
1.9
2.6
6.4
ns
7a
Clock1
1.61
2.62
5.64
1.6
2.6
5.6
ns
7b
Clock1rise to Burst Clock fall
1.61
2.62
5.84
1.6
2.6
5.8
ns
7c
Clock1
1.55
2.48
5.59
1.5
2.4
5.4
ns
7d
Clock1 fall to Burst Clock fall
1.55
2.59
5.80
1.5
2.5
5.6
ns
8a
Read Data setup time
5.54
–
–
5.5
–
–
ns
8b
Read Data hold time
0
–
–
0
–
–
ns
9a
Clock1
1.81
2.72
6.85
1.8
2.7
6.8
ns
9b
Clock1 fall to Write Data Invalid
1.45
2.48
5.69
1.4
2.4
5.5
ns
9c
Clock1
1.63
–
–
1.62
–
–
ns
2.52
–
–
2.5
–
–
ns
10a
1
3.0 ± 0.3 V
Parameter
fall to Enable Bytes Invalid
fall to Load Burst Address Invalid
rise to Burst Clock rise
fall to Burst Clock rise
rise to Write Data Valid
rise to Write Data Invalid
DTACK setup time
Clock refers to the system clock signal, HCLK, generated from the System DPLL
4.4.1
DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group
supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2
DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
25
Functional Description and Application Information
4.4.2.1
WAIT Read Cycle without DMA
3
Address
2
8
CS5
1
9
programmable
min 0ns
EB
5
OE
4
WAIT
7
DATABUS
10
XL
6
11
Figure 6. WAIT Read Cycle without DMA
Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
See note 2
–
ns
3T
–
ns
1
OE and EB assertion time
2
CS5 pulse width
3
OE negated to address inactive
56.81
57.28
ns
4
Wait asserted after OE asserted
–
1020T
ns
5
Wait asserted to OE negated
2T+1.57
3T+7.33
ns
6
Data hold timing after OE negated
T-1.49
–
ns
7
Data ready after wait asserted
0
T
ns
8
OE negated to CS negated
1.5T-0.68
1.5T-0.06
ns
9
OE negated after EB negated
0.06
0.18
ns
10
Become low after CS5 asserted
0
1019T
ns
11
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Technical Data, Rev. 8
26
Freescale Semiconductor
Functional Description and Application Information
4.4.2.2
WAIT Read Cycle DMA Enabled
4
Address
2
9
CS5
1
EB
10
programmable
min 0ns
3
6
OE
RW (logic high)
5
WAIT
7
11
L
8
DATABUS
12
Figure 7. DTACK WAIT Read Cycle DMA Enabled
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
See note 2
–
ns
3T
–
ns
1.5T-0.68
1.5T-0.06
ns
1
OE and EB assertion time
2
CS pulse width
3
OE negated before CS5 is negated
4
Address inactived before CS negated
–
0.05
ns
5
Wait asserted after CS5 asserted
–
1020T
ns
6
Wait asserted to OE negated
2T+1.57
3T+7.33
ns
7
Data hold timing after OE negated
T-1.49
–
ns
8
Data ready after wait is asserted
–
T
ns
9
CS deactive to next CS active
T
–
ns
10
OE negate after EB negate
0.06
0.18
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
27
Functional Description and Application Information
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
3.0 ± 0.3 V
Number
12
Characteristic
Unit
Minimum
Maximum
1T
1020T
Wait pulse width
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.3
WAIT Write Cycle without DMA
5
Address
1
3
programmable
min 0ns
CS5
2
10
programmable
min 0ns
EB
4
7
RW
OE (logic high)
6
WAIT
DATABUS
from i.MXL
11
9
8
12
Figure 8. WAIT Write Cycle without DMA
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5
RW negated to Address inactive
64.22
–
ns
6
Wait asserted after CS5 asserted
–
1020T
ns
MC9328MXL Technical Data, Rev. 8
28
Freescale Semiconductor
Functional Description and Application Information
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
3.0 ± 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated after CS5 is negated
0.5T
0.5T+0.5
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.4
WAIT Write Cycle DMA Enabled
5
Address
1
CS5
3
programmable
min 0ns
10
2
EB
11
programmable
min 0ns
7
4
RW
6
OE (logic high)
12
WAIT
9
13
8
DATABUS
Figure 9. WAIT Write Cycle DMA Enabled
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
29
Functional Description and Application Information
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 ± 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5
Address inactived after CS negated
–
0.09
ns
6
Wait asserted after CS5 asserted
–
1020T
ns
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
CS deactive to next CS active
T
–
ns
11
EB negate after CS negate
0.5T
0.5T+0.5
12
Wait becomes low after CS5 asserted
0
1019T
ns
13
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.3
EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MXL, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown
in Figure 5, and Table 12 defines the parameters of signals.
MC9328MXL Technical Data, Rev. 8
30
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Seq/Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1
weim_hready
BCLK (burst clock)
ADDR
Last Valid Address
V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
V1
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 10. WSC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
31
Functional Description and Application Information
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid Data
weim_hrdata
Write Data (V1)
Unknown
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Address
V1
CS0
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (V1)
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
32
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS0
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
33
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1 + 2
Address V1
CS0
R/W
Write
LBA
OE
EB
DATA
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
34
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS[3]
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
35
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata Last Valid
Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS3
Write
R/W
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
36
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1 + 2
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
37
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
Valid
hwdata Last
Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
38
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
39
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
V1 Word
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
40
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
weim_hrdata
Unknown
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
41
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
Valid
hwdata Last
Data
Unknown
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
42
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CS2
R/W
Write
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
43
Functional Description and Application Information
Read
Idle
Write
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Write Data
Last Valid Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CS2
R/W
Read
Write
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
44
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata Last Valid
Data
Write Data (Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
45
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CS4
R/W
Write
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
46
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Read
Read
haddr
V1
V2
Idle
Seq
hready
weim_hrdata
Last Valid Data
Read Data (V1)
Read Data (V2)
weim_hready
BCLK (burst clock)
ADDR
Last Valid
Address V1
Address V2
CNC
CS4
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Read Data
(V1)
Read Data
(V2)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
47
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Read
Write
haddr
V1
V8
Idle
Nonseq
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CNC
CS4
R/W
Read
Write
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
48
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonse
hwrite
Read
Read
haddr
V1
V5
Idle
hready
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V5
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V5 Word
V6 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
49
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
Seq
Seq
hwrite
Read
Read
Read
Read
haddr
V1
V2
V3
V4
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V3 Word
V4 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MXL Technical Data, Rev. 8
50
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid
Address V1
Address V2
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
51
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
52
Freescale Semiconductor
Functional Description and Application Information
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
53
Functional Description and Application Information
4.4.4
Non-TFT Panel Timing
T1
T1
VSYN
T3
T2
T4
XMAX
T2
HSYN
SCLK
Ts
LD[15:0]
Figure 33. Non-TFT Panel Timing
Table 17. Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register
Minimum Value1, 2
Actual Value
Unit
T1
HSYN to VSYN delay3
0
HWAIT2+2
Tpix4
T2
HSYN pulse width
0
HWIDTH+1
Tpix
T3
VSYN to SCLK
–
0 ≤ T3 ≤ Ts5
–
T4
SCLK to HSYN
0
HWAIT1+1
Tpix
1
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
3 VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
4 Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
5 Ts is the shift clock period. Ts = Tpix * (panel data bus width).
2
4.5
SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI1 Sample Period Control Register (PERIODREG1) and the SPI2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or
SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input
signal, and is used to latch data into or load data out to the internal data shift registers, as well as to
increment the data FIFO. Figure 34 through Figure 38 show the timing relationship of the master SPI using
different triggering mechanisms.
MC9328MXL Technical Data, Rev. 8
54
Freescale Semiconductor
Functional Description and Application Information
2
SS
5
3
1
4
SPIRDY
SCLK, MOSI, MISO
Figure 34. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 35. Master SPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input)
6
7
SCLK, MOSI, MISO
Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
55
Functional Description and Application Information
Table 18. Timing Parameter Table for Figure 34 through Figure 38
3.0 ± 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
2T1
–
ns
1
SPI_RDY to SS output low
2
SS output low to first SCLK edge
3 • Tsclk2
–
ns
3
Last SCLK edge to SS output high
2 • Tsclk
–
ns
4
SS output high to SPI_RDY low
0
–
ns
5
SS output pulse width
Tsclk + WAIT 3
–
ns
6
SS input low to first SCLK edge
T
–
ns
7
SS input pulse width
T
–
ns
1
T = CSPI system clock period (PERCLK2).
Tsclk = Period of SCLK.
3
WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
2
8
SCLK
9
9
Figure 39. SPI SCLK Timing Diagram
Table 19. Timing Parameter Table for SPI SCLK
3.0 ± 0.3 V
Ref No.
4.6
Parameter
8
SCLK frequency
9
SCLK pulse width
Unit
Minimum
Maximum
0
10
MHz
100
–
ns
LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.
LSCLK
1
LD[15:0]
Figure 40. SCLK to LD Timing Diagram
MC9328MXL Technical Data, Rev. 8
56
Freescale Semiconductor
Functional Description and Application Information
Table 20. LCDC SCLK Timing Parameter Table
3.0 ± 0.3 V
Ref No.
1
Parameter
Minimum
Maximum
Unit
–
2
ns
SCLK to LD valid
Non-display
VSYN
Display region
T3
T1
T4
T2
HSYN
OE
LD[15:0]
Line Y
Line 1
T5
T6
Line Y
T7
XMAX
HSYN
SCLK
OE
T8
LD[15:0]
(1,1)
(1,2)
(1,X)
VSYN
T9
T10
Figure 41. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol
Description
Minimum
Corresponding Register Value
Unit
T1
End of OE to beginning of VSYN
T5+T6
+T7+T9
(VWAIT1·T2)+T5+T6+T7+T9
Ts
T2
HSYN period
XMAX+5
XMAX+T5+T6+T7+T9+T10
Ts
T3
VSYN pulse width
T2
VWIDTH·(T2)
Ts
T4
End of VSYN to beginning of OE
2
VWAIT2·(T2)
Ts
T5
HSYN pulse width
1
HWIDTH+1
Ts
T6
End of HSYN to beginning to T9
1
HWAIT2+1
Ts
T7
End of OE to beginning of HSYN
1
HWAIT1+1
Ts
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
57
Functional Description and Application Information
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum
Corresponding Register Value
Unit
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
(for non-display region)
2
2
Ts
T9
End of HSYN idle2 to VSYN edge
(for Display region)
1
1
Ts
T10
VSYN to OE active (Sharp = 0) when VWAIT2 = 0
1
1
Ts
T10
VSYN to OE active (Sharp = 1) when VWAIT2 = 0
2
2
Ts
Note:
•
•
•
•
•
•
4.7
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals
are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In Figure 41, SCLK is always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
3a
1
2
4b
3b
Bus Clock
4a
5b
5a
CMD_DAT Input
Valid Data
Valid Data
7
CMD_DAT Output
Valid Data
Valid Data
6a
6b
Figure 42. Chip-Select Read Cycle Timing Diagram
MC9328MXL Technical Data, Rev. 8
58
Freescale Semiconductor
Functional Description and Application Information
Table 22. SDHC Bus Timing Parameter Table
1.8 ± 0.1 V
Ref
No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency at Data transfer Mode
(PP)1—10/30 cards
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
0
400
0
400
kHz
1
3a
Clock high time —10/30 cards
6/33
–
10/50
–
ns
3b
Clock low time1—10/30 cards
15/75
–
10/50
–
ns
4a
1
Clock fall time —10/30 cards
–
10/50
(5.00)3
–
10/50
ns
4b
Clock rise time1—10/30 cards
–
14/67
(6.67)3
–
10/50
ns
5a
Input hold time3—10/30 cards
10.3/10.3
–
9/9
–
ns
10.3/10.3
–
9/9
–
ns
5.7/5.7
–
5/5
–
ns
5.7/5.7
–
5/5
–
ns
0
16
0
14
ns
time3—10/30
5b
Input setup
cards
6a
Output hold time3—10/30 cards
time3—10/30
6b
Output setup
7
Output delay time3
cards
CL ≤ 100 pF / 250 pF (10/30 cards)
CL ≤ 250 pF (21 cards)
3 C ≤ 25 pF (1 card)
L
1
2
4.7.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 43. The symbols for Figure 43 through
Figure 47 are defined in Table 23.
Table 23. State Signal Parameters for Figure 43 through Figure 47
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit (Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC
Cyclic redundancy check bits (7 bits)
E
End bit (1)
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
59
Functional Description and Application Information
NID cycles
Host Command
CMD S T
Content
CID/OCR
******
CRC E Z
Content
Z ST
ZZZ
Identification Timing
NCR cycles
Host Command
CMD S T
Content
CID/OCR
******
CRC E Z
Content
Z ST
ZZZ
SET_RCA Timing
Figure 43. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 44, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods NRC and NCC.
NCR cycles
Host Command
CMD S T
Content
Response
CRC E Z Z P
******
PST
Content
CRC E Z Z Z
Command response timing (data transfer mode)
NRC cycles
Response
CMD S T
Content
Host Command
CRC E Z
******
Z ST
Content
CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
NCC cycles
Host Command
CMD S T
Content
CRC E Z
Host Command
******
Z ST
Content
CRC E Z Z Z
Timing of command sequences (all modes)
Figure 44. Timing Diagrams at Data Transfer Mode
Figure 45 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the
SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC , beginning
from the last bit of the read command. If the system is in multiple block read mode, the card sends a
continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The
data stops two clock cycles after the end bit of the stop command.
MC9328MXL Technical Data, Rev. 8
60
Freescale Semiconductor
Functional Description and Application Information
NCR cycles
Host Command
CMD S T
Content
DAT
Response
CRC E Z Z P ****** P S T
Z****Z
Content
CRC E Z
*****
Z Z P ****** P S D D D D
Read Data
NAC cycles
Timing of single block read
NCR cycles
Host Command
CMD S T
DAT
Content
Response
CRC E Z Z P ****** P S T
Z****Z
******
ZZP
Content
P S DDDD
CRC E Z
*****
*****
P
P S DDDD
Read Data
*****
Read Data
NAC cycles
NAC cycles
Timing of multiple block read
NCR cycles
Host Command
CMD S T
Content
Response
CRC E Z Z P ****** P S T
Content
CRC E Z
NST
DAT D D D D
*****
DDDDE Z Z Z
Valid Read Data
*****
Timing of stop command
(CMD12, data transfer mode)
Figure 45. Timing Diagrams at Data Read
Figure 46 shows the basic write operation timing. As with the read operation, after the card response, the
data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check
for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If
there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC
status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple
block mode, with the flow terminated by a stop transmission command.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
61
62
Z****Z
Z****Z
CRC E Z Z P
NWR cycles
CRC status
Timing of the multiple block write command
NWR cycles
Write Data
Content
DAT Z Z P P S
CRC E Z Z X X X X X X X X Z P P S
EZPPS
Content
Content
Status
PST
DAT Z Z P P S
CRC E Z Z S
******
Write Data
Content
******
Status
ES
L*L
EZ
PP P
ES
L*L
EZ
CRC status
Busy
CRC E Z Z X X X X X X X X X X X X X X X X Z
Status
PPP
CRC status
Busy
CRC E Z Z X X X X X X X X X X X X X X X X Z
CRC E Z Z S
Write Data
Content
Content
CRC E Z Z S
NWR cycles
Z ZZPPS
Z ZZPPS
CRC E Z Z P
Content
Response
******
Timing of the block write command
Content
NCR cycles
CMD E Z Z P
DAT
DAT
CMD S T
Host Command
Functional Description and Application Information
Figure 46. Timing Diagrams at Data Write
The stop transmission command may occur when the card is in different states. Figure 47 shows the
different scenarios on the bus.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
Parameter
Freescale Semiconductor
Content
CRC E Z Z P
Symbol
Minimum
DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L
DAT S L
DAT D D D D D D D Z Z S CRC E Z Z S L
Write Data
PST
******
Content
******
******
******
ST
Content
CRC E
Host Command
Stop transmission received after last data block.
Card becomes busy programming.
EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ
Stop transmission received after last data block.
Card becomes busy programming.
EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ
Stop transmission during CRC status transfer
from the card.
EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ
Stop transmission during data transfer
from the host.
EZZ Z Z Z ZZ ZZ ZZ ZZ ZZ Z Z ZZ Z ZZ ZZ ZZ
CRC E Z Z Z
Card Response
Busy (Card is programming)
******
NCR cycles
DAT D D D D D D D D D D D D D E Z Z S L
CMD S T
Host Command
Functional Description and Application Information
Figure 47. Stop Transmission During Different Scenarios
Table 24. Timing Values for Figure 43 through Figure 47
Maximum
Unit
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Command response cycle
NCR
2
64
Clock cycles
Identification response cycle
NID
5
5
Clock cycles
Access time delay cycle
NAC
2
TAAC + NSAC
Clock cycles
MC9328MXL Technical Data, Rev. 8
63
Functional Description and Application Information
Table 24. Timing Values for Figure 43 through Figure 47 (Continued)
Parameter
Symbol
Minimum
Maximum
Unit
Command read cycle
NRC
8
–
Clock cycles
Command-command cycle
NCC
8
–
Clock cycles
Command write cycle
NWR
2
–
Clock cycles
Stop transmission cycle
NST
2
2
Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
4.7.2
SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the “Interrupt
Period” during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
CMD
ST
DAT[1]
Content
CRC E Z Z P S
Interrupt Period
Response
S
******
EZZZ
Block Data
E
IRQ
S
ZZZ
Block Data
E
IRQ
For 4-bit
LH
DAT[1]
Interrupt Period
For 1-bit
Figure 48. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps
the clock running, and allows the user to submit commands as normal. After all commands are submitted,
the user can switch back to the data transfer operation and all counter and status values are resumed as
access continues.
MC9328MXL Technical Data, Rev. 8
64
Freescale Semiconductor
Functional Description and Application Information
CMD
DAT[1]
P S T CMD52
******
CRC E Z Z Z
******
S
Block Data
EZZL H
S
Block Data
E
S
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S
Block Data
E
For 4-bit
DAT[2]
For 4-bit
Figure 49. SDIO ReadWait Timing Diagram
4.8
Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
65
Functional Description and Application Information
2
1
3
4
5
MS_SCLKI
6
8
7
MS_SCLKO
9
11
10
11
MS_BS
12
12
MS_SDIO(output)
14
13
MS_SDIO (input)
(RED bit = 0)
15
16
MS_SDIO (input)
(RED bit = 1)
Figure 50. MSHC Signal Timing Diagram
Table 25. MSHC Signal Timing Parameter Table
3.0 ± 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
1
MS_SCLKI frequency
–
25
MHz
2
MS_SCLKI high pulse width
20
–
ns
3
MS_SCLKI low pulse width
20
–
ns
4
MS_SCLKI rise time
–
3
ns
5
MS_SCLKI fall time
–
3
ns
–
25
MHz
20
–
ns
15
–
ns
–
5
ns
–
5
ns
–
3
ns
1
6
MS_SCLKO frequency
7
MS_SCLKO high pulse width1
8
MS_SCLKO low pulse
9
MS_SCLKO rise time1
width1
time1
10
MS_SCLKO fall
11
MS_BS delay time1
MC9328MXL Technical Data, Rev. 8
66
Freescale Semiconductor
Functional Description and Application Information
Table 25. MSHC Signal Timing Parameter Table (Continued)
3.0 ± 0.3 V
Ref
No.
12
Parameter
Unit
Minimum
Maximum
–
3
ns
18
–
ns
0
–
ns
23
–
ns
0
–
ns
MS_SDIO output delay time1,2
13
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)
14
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3
3
15
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)
16
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
4
1
Loading capacitor condition is less than or equal to 30pF.
An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
3 If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
4 If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
2
4.9
Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 51 and the parameters are listed in Table 26.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 51. PWM Output Timing Diagram
Table 26. PWM Output Timing Parameter Table
1.8 ± 0.1 V
Ref No.
3.0 ± 0.3 V
Parameter
1
System CLK frequency1
2a
Clock high time1
1
2b
Clock low time
3a
Clock fall time1
Unit
Minimum
Maximum
Minimum
Maximum
0
87
0
100
MHz
3.3
–
5/10
–
ns
7.5
–
5/10
–
ns
–
5
–
5/10
ns
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
67
Functional Description and Application Information
Table 26. PWM Output Timing Parameter Table (Continued)
1.8 ± 0.1 V
Ref No.
3b
1
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
Clock rise time1
–
6.67
–
5/10
ns
4a
1
Output delay time
5.7
–
5
–
ns
4b
Output setup time1
5.7
–
5
–
ns
CL of PWMO = 30 pF
4.10
SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic
random access memory) Controller.
1
SDCLK
2
3S
3
CS
3H
3S
RAS
3S
3H
CAS
3S
3H
3H
WE
4S
ADDR
4H
ROW/BA
COL/BA
5
8
DQ
6
Data
7
3S
DQM
3H
Note:
CKE is high during the read/write cycle.
Figure 52. SDRAM Read Cycle Timing Diagram
MC9328MXL Technical Data, Rev. 8
68
Freescale Semiconductor
Functional Description and Application Information
Table 27. SDRAM Read Timing Parameter Table
1.8 ± 0.1 V
Ref
No.
1
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2.67
–
4
–
ns
2
SDRAM clock low-level width
6
–
4
–
ns
3
SDRAM clock cycle time
11.4
–
10
–
ns
3S
CS, RAS, CAS, WE, DQM setup time
3.42
–
3
–
ns
3H
CS, RAS, CAS, WE, DQM hold time
2.28
–
2
–
ns
4S
Address setup time
3.42
–
3
–
ns
4H
Address hold time
2.28
–
2
–
ns
5
SDRAM access time (CL = 3)
–
6.84
–
6
ns
5
SDRAM access time (CL = 2)
–
6.84
–
6
ns
5
SDRAM access time (CL = 1)
–
22
–
22
ns
6
Data out hold time
2.85
–
2.5
–
ns
7
Data out high-impedance time (CL = 3)
–
6.84
–
6
ns
7
Data out high-impedance time (CL = 2)
–
6.84
–
6
ns
7
Data out high-impedance time (CL = 1)
–
22
–
22
ns
8
Active to read/write command period (RC = 1)
tRCD1
–
tRCD1
–
ns
tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
69
Functional Description and Application Information
SDCLK
1
2
3
CS
RAS
6
CAS
WE
5
7
4
ADDR
/ BA
COL/BA
ROW/BA
8
9
DATA
DQ
DQM
Figure 53. SDRAM Write Cycle Timing Diagram
Table 28. SDRAM Write Timing Parameter Table
1.8 ± 0.1 V
Ref No.
1
2
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2.67
–
4
–
ns
2
SDRAM clock low-level width
6
–
4
–
ns
3
SDRAM clock cycle time
11.4
–
10
–
ns
4
Address setup time
3.42
–
3
–
ns
5
Address hold time
2.28
–
2
–
ns
tRP2
–
tRP2
–
ns
tRCD2
–
tRCD2
–
ns
period1
6
Precharge cycle
7
Active to read/write command delay
8
Data setup time
4.0
–
2
–
ns
9
Data hold time
2.28
–
2
–
ns
Precharge cycle timing is included in the write timing diagram.
tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
70
Freescale Semiconductor
Functional Description and Application Information
SDCLK
1
3
2
CS
RAS
6
CAS
7
7
WE
4
ADDR
5
ROW/BA
BA
DQ
DQM
Figure 54. SDRAM Refresh Timing Diagram
Table 29. SDRAM Refresh Timing Parameter Table
1.8 ± 0.1 V
Ref No.
1
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2.67
–
4
–
ns
2
SDRAM clock low-level width
6
–
4
–
ns
3
SDRAM clock cycle time
11.4
–
10
–
ns
4
Address setup time
3.42
–
3
–
ns
5
Address hold time
2.28
–
2
–
ns
6
Precharge cycle period
tRP1
–
tRP1
–
ns
7
Auto precharge command period
tRC1
–
tRC1
–
ns
tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
71
Functional Description and Application Information
SDCLK
CS
RAS
CAS
WE
ADDR
BA
DQ
DQM
CKE
Figure 55. SDRAM Self-Refresh Cycle Timing Diagram
4.11
USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous
transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is
identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section
covers the transfer modes and how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same
packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved
in the form of packets, however, because isochronous pipes are given a fixed portion of the USB
bandwidth at all times, there is no end-of-transfer.
MC9328MXL Technical Data, Rev. 8
72
Freescale Semiconductor
Functional Description and Application Information
USBD_AFE
(Output)
1
t VMO_ROE 4
t ROE_VPO
USBD_ROE
(Output)
tPERIOD
6
3
tVPO_ROE
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
tROE_VMO
2
tFEOPT
5
(Output)
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
Figure 56. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 30. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)
3.0 ± 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
1
tROE_VPO; USBD_ROE active to USBD_VPO low
83.14
83.47
ns
2
tROE_VMO; USBD_ROE active to USBD_VMO high
81.55
81.98
ns
3
tVPO_ROE; USBD_VPO high to USBD_ROE deactivated
83.54
83.80
ns
4
tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0)
248.90
249.13
ns
5
tFEOPT; SE0 interval of EOP
160.00
175.00
ns
6
tPERIOD; Data transfer rate
11.97
12.03
Mb/s
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
73
Functional Description and Application Information
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
1
tFEOPR
USBD_VP
(Input)
USBD_VM
(Input)
Figure 57. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 31. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
3.0 ± 0.3 V
Ref No.
1
4.12
Parameter
Unit
tFEOPR; Receiver SE0 interval of EOP
Minimum
Maximum
82
–
ns
I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5
3
4
SCL
1
2
6
Figure 58. Definition of Bus Timing for I2C
MC9328MXL Technical Data, Rev. 8
74
Freescale Semiconductor
Functional Description and Application Information
Table 32. I2C Bus Timing Parameter Table
1.8 ± 0.1 V
Ref No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
182
–
160
–
ns
1
Hold time (repeated) START condition
2
Data hold time
0
171
0
150
ns
3
Data setup time
11.4
–
10
–
ns
4
HIGH period of the SCL clock
80
–
120
–
ns
5
LOW period of the SCL clock
480
–
320
–
ns
6
Setup time for STOP condition
182.4
–
160
–
ns
4.13
Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated
clock mode, the clock functions only during transmission. The internal and external clock timing diagrams
are shown in Figure 60 through Figure 62.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
1
STCK Output
4
2
STFS (bl) Output
6
8
STFS (wl) Output
12
10
11
STXD Output
31
32
SRXD Input
Note: SRXD input in synchronous mode only.
Figure 59. SSI Transmitter Internal Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
75
Functional Description and Application Information
1
SRCK Output
3
5
SRFS (bl) Output
7
9
SRFS (wl) Output
13
14
SRXD Input
Figure 60. SSI Receiver Internal Clock Timing Diagram
15
16
17
STCK Input
18
20
STFS (bl) Input
24
22
STFS (wl) Input
27
26
28
STXD Output
33
34
SRXD Input
Note: SRXD Input in Synchronous mode only
Figure 61. SSI Transmitter External Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8
76
Freescale Semiconductor
Functional Description and Application Information
15
16
17
SRCK Input
19
21
SRFS (bl) Input
25
23
SRFS (wl) Input
30
29
SRXD Input
Figure 62. SSI Receiver External Clock Timing Diagram
Table 33. SSI (Port C Primary Function) Timing Parameter Table
1.8 ± 0.1 V
Ref No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (Port C Primary Function2)
1
STCK/SRCK clock period1
95
–
83.3
–
ns
2
STCK high to STFS (bl) high3
1.5
4.5
1.3
3.9
ns
3
SRCK high to SRFS (bl)
high3
-1.2
-1.7
-1.1
-1.5
ns
4
STCK high to STFS (bl) low3
2.5
4.3
2.2
3.8
ns
5
SRCK high to SRFS (bl)
low3
0.1
-0.8
0.1
-0.8
ns
6
STCK high to STFS (wl) high3
1.48
4.45
1.3
3.9
ns
7
3
SRCK high to SRFS (wl) high
-1.1
-1.5
-1.1
-1.5
ns
8
STCK high to STFS (wl) low3
2.51
4.33
2.2
3.8
ns
9
3
SRCK high to SRFS (wl) low
0.1
-0.8
0.1
-0.8
ns
10
STCK high to STXD valid from high impedance
14.25
15.73
12.5
13.8
ns
11a
STCK high to STXD high
0.91
3.08
0.8
2.7
ns
11b
STCK high to STXD low
0.57
3.19
0.5
2.8
ns
12
STCK high to STXD high impedance
12.88
13.57
11.3
11.9
ns
13
SRXD setup time before SRCK low
21.1
–
18.5
–
ns
14
SRXD hold time after SRCK low
0
–
0
–
ns
External Clock Operation (Port C Primary Function2)
15
STCK/SRCK clock period1
92.8
–
81.4
–
ns
16
STCK/SRCK clock high period
27.1
–
40.7
–
ns
17
STCK/SRCK clock low period
61.1
–
40.7
–
ns
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
77
Functional Description and Application Information
Table 33. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8 ± 0.1 V
Ref No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
18
STCK high to STFS (bl) high3
–
92.8
0
81.4
ns
19
3
SRCK high to SRFS (bl) high
–
92.8
0
81.4
ns
20
STCK high to STFS (bl) low3
–
92.8
0
81.4
ns
21
3
SRCK high to SRFS (bl) low
–
92.8
0
81.4
ns
22
STCK high to STFS (wl) high3
–
92.8
0
81.4
ns
23
3
SRCK high to SRFS (wl) high
–
92.8
0
81.4
ns
24
STCK high to STFS (wl) low3
–
92.8
0
81.4
ns
25
SRCK high to SRFS (wl)
low3
–
92.8
0
81.4
ns
26
STCK high to STXD valid from high impedance
18.01
28.16
15.8
24.7
ns
27a
STCK high to STXD high
8.98
18.13
7.0
15.9
ns
27b
STCK high to STXD low
9.12
18.24
8.0
16.0
ns
28
STCK high to STXD high impedance
18.47
28.5
16.2
25.0
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hole time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port C Primary Function2)
31
SRXD setup before STCK falling
32
SRXD hold after STCK falling
15.4
–
13.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port C Primary Function2)
33
SRXD setup before STCK falling
34
SRXD hold after STCK falling
1.14
–
1.0
–
ns
0
–
0
–
ns
1
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2
There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on
status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary
function.
3
bl = bit length; wl = word length.
MC9328MXL Technical Data, Rev. 8
78
Freescale Semiconductor
Functional Description and Application Information
Table 34. SSI (Port B Alternate Function) Timing Parameter Table
1.8 ± 0.1 V
Ref
No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (Port B Alternate Function2)
1
STCK/SRCK clock period1
95
–
83.3
–
ns
2
STCK high to STFS (bl) high3
1.7
4.8
1.5
4.2
ns
3
SRCK high to SRFS (bl) high3
-0.1
1.0
-0.1
1.0
ns
4
STCK high to STFS (bl) low3
3.08
5.24
2.7
4.6
ns
5
SRCK high to SRFS (bl) low3
1.25
2.28
1.1
2.0
ns
6
STCK high to STFS (wl) high3
1.71
4.79
1.5
4.2
ns
7
SRCK high to SRFS (wl) high3
-0.1
1.0
-0.1
1.0
ns
8
STCK high to STFS (wl) low3
3.08
5.24
2.7
4.6
ns
9
SRCK high to SRFS (wl) low3
1.25
2.28
1.1
2.0
ns
10
STCK high to STXD valid from high impedance
14.93
16.19
13.1
14.2
ns
11a
STCK high to STXD high
1.25
3.42
1.1
3.0
ns
11b
STCK high to STXD low
2.51
3.99
2.2
3.5
ns
12
STCK high to STXD high impedance
12.43
14.59
10.9
12.8
ns
13
SRXD setup time before SRCK low
20
–
17.5
–
ns
14
SRXD hold time after SRCK low
0
–
0
–
ns
External Clock Operation (Port B Alternate Function2)
15
STCK/SRCK clock period1
92.8
–
81.4
–
ns
16
STCK/SRCK clock high period
27.1
–
40.7
–
ns
17
STCK/SRCK clock low period
61.1
–
40.7
–
ns
18
STCK high to STFS (bl) high3
–
92.8
0
81.4
ns
19
3
SRCK high to SRFS (bl) high
–
92.8
0
81.4
ns
20
STCK high to STFS (bl) low3
–
92.8
0
81.4
ns
21
SRCK high to SRFS (bl)
low3
–
92.8
0
81.4
ns
22
STCK high to STFS (wl) high3
–
92.8
0
81.4
ns
23
SRCK high to SRFS (wl)
high3
–
92.8
0
81.4
ns
24
STCK high to STFS (wl) low3
–
92.8
0
81.4
ns
25
SRCK high to SRFS (wl)
low3
–
92.8
0
81.4
ns
26
STCK high to STXD valid from high impedance
18.9
29.07
16.6
25.5
ns
27a
STCK high to STXD high
9.23
20.75
8.1
18.2
ns
27b
STCK high to STXD low
10.60
21.32
9.3
18.7
ns
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
79
Functional Description and Application Information
Table 34. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
1.8 ± 0.1 V
Ref
No.
3.0 ± 0.3 V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hold time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port B Alternate Function2)
31
SRXD setup before STCK falling
32
SRXD hold after STCK falling
18.81
–
16.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33
SRXD setup before STCK falling
34
SRXD hold after STCK falling
1.14
–
1.0
–
ns
0
–
0
–
ns
1
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3 bl = bit length; wl = word length.
4.14
CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive
FIFO, and a 16 × 32 statistic data FIFO.
4.14.1
Gated Clock Mode
Figure 63 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 64 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 35.
MC9328MXL Technical Data, Rev. 8
80
Freescale Semiconductor
Functional Description and Application Information
1
VSYNC
7
HSYNC
5
6
2
PIXCLK
Valid Data
DATA[7:0]
3
Valid Data
Valid Data
4
Figure 63. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
7
HSYNC
6
5
2
PIXCLK
Valid Data
DATA[7:0]
3
Valid Data
Valid Data
4
Figure 64. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 35. Gated Clock Mode Timing Parameters
Ref No.
Parameter
Min
Max
Unit
1
csi_vsync to csi_hsync
180
–
ns
2
csi_hsync to csi_pixclk
1
–
ns
3
csi_d setup time
1
–
ns
4
csi_d hold time
1
–
ns
5
csi_pixclk high time
10.42
–
ns
6
csi_pixclk low time
10.42
–
ns
7
csi_pixclk frequency
0
48
MHz
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
81
Functional Description and Application Information
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
4.14.2
Non-Gated Clock Mode
Figure 65 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 66 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 36.
1
6
VSYNC
4
5
PIXCLK
DATA[7:0]
Valid Data
2
Valid Data
Valid Data
3
Figure 65. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MXL Technical Data, Rev. 8
82
Freescale Semiconductor
Functional Description and Application Information
1
VSYNC
6
4
5
PIXCLK
Valid Data
DATA[7:0]
2
Valid Data
Valid Data
3
Figure 66. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 36. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Min
Max
Unit
180
–
ns
1
csi_vsync to csi_pixclk
2
csi_d setup time
1
–
ns
3
csi_d hold time
1
–
ns
4
csi_pixclk high time
10.42
–
ns
5
csi_pixclk low time
10.42
–
ns
6
csi_pixclk frequency
0
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
83
Pin-Out and Package Information
Table 37 illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal
Multiplexing Table 3 on page 9.
Table 37. i.MXL 256 MAPBGA Pin Assignments
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
NVSS
SD_DAT3
SD_CLK
NVSS
USBD_
AFE
NVDD4
NVSS
UART1_
RTS
UART1_
RXD
NVDD3
N.C.
N.C.
QVDD4
N.C.
N.C.
N.C.
A
B
A24
SD_DAT1
SD_CMD
PB16
USBD_
ROE
USBD_VP
SSI_
RXCLK
SSI_
TXCLK
SPI1_
SCLK
N.C.
N.C.
N.C.
QVSS
N.C.
N.C.
N.C.
B
C
A23
D31
SD_DAT0
PB15
USBD_
RCV
UART2_
CTS
UART2_
RXD
SSI_
RXFS
UART1_
TXD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
C
D
A22
D30
D29
PB14
USBD_
SUSPND
USBD_
VPO
USBD_
VMO
SSI_
RXDAT
SPI1_
SPI_RDY
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D
E
A20
A21
D28
D26
SD_DAT2
USBD_VM
UART2_
RTS
SSI_
TXDAT
SPI1_SS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
E
F
A18
D27
D25
A19
A16
PB18
UART2_
TXD
SSI_
TXFS
SPI1_
MISO
N.C.
N.C.
REV
N.C.
N.C.
LSCLK
SPL_SPR
F
G
A15
A17
D24
D23
D21
PB17
PB19
UART1_
CTS
SPI1_
MOSI
N.C.
CLS
CONTRAST
ACD/OE
LP/
HSYNC
FLM/
VSYNC
LD1
G
H
A13
D22
A14
D20
NVDD1
NVDD1
NVSS
QVSS
QVDD1
PS
LD0
LD2
LD4
LD5
LD9
LD3
H
J
A12
A11
D18
D19
NVDD1
NVDD1
NVSS
NVDD1
NVSS
NVSS
LD6
LD7
LD8
LD11
QVDD3
QVSS
J
K
A10
D16
A9
D17
NVDD1
NVSS
NVSS
NVDD1
NVDD2
NVDD2
LD10
LD12
LD13
LD14
TMR2OUT
LD15
K
L
A8
A7
D13
D15
D14
NVDD1
NVSS
CAS
TCK
TIN
PWMO
CSI_MCLK
CSI_D0
CSI_D1
CSI_D2
CSI_D3
L
M
A5
D12
D11
A6
SDCLK
NVSS
RW
MA10
RAS
RESET_IN
BIG_
ENDIAN
CSI_D4
CSI_
HSYNC
CSI_VSYNC
CSI_D6
CSI_D5
M
N
A4
EB1
D10
D7
A0
D4
PA17
D1
DQM1
RESET_SF1
RESET_
OUT
BOOT2
CSI_
PIXCLK
CSI_D7
TMS
TDI
N
P
A3
D9
EB0
CS3
D6
ECB
D2
D3
DQM3
SDCKE1
BOOT3
BOOT0
TRST
I2C_SCL
I2C_SDA
XTAL32K
P
R
EB2
EB3
A1
CS4
D8
D5
LBA
BCLK2
D0
DQM0
SDCKE0
POR
BOOT1
TDO
QVDD2
EXTAL32K
R
T
NVSS
A2
OE
CS5
CS2
CS1
CS0
MA11
DQM2
SDWE
CLKO
AVDD1
TRISTATE
EXTAL16M
XTAL16M
QVSS
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
This signal is not used and should be floated in an actual application.
2
burst clock
N.C.
Pin-Out and Package Information
84
5
reescale Semiconductor
Table 38 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the
Signal Multiplexing Table 3 on page 9.
Table 38. i.MXL 225 MAPBGA Pin Assignments
MC9328MXL Technical Data, Rev. 8
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
SD_CMD
PB15
PB19
USBD_
ROE
USBD_
SUSPND
USBD_VM
SSI_
RXFS
SSI_
TXCLK
SPI1_SPI_
RDY
SPI1_
SCLK
REV
PS
LD2
LD4
LD5
A
B
SD_DAT3
SD_CLK
PB16
USBD_
AFE
USBD_
RCV
USBD_
VMO
SSI_
RXDAT
UART1_
TXD
SPI1_SS
LSCLK
SPL_
SPR
LD0
LD3
LD6
LD7
B
C
D31
SD_DAT0
PB14
PB18
SD_DAT2
USBD_
VPO
UART2_
RXD
SSI_
TXFS
UART1_
RTS
LD8
LD9
LD12
NVDD2
C
D
A23
A24
SD_DAT1
PB17
NVDD1
USBD_
VP
QVDD4
UART2_
TXD
NVDD3
SPI1_
MOSI
LP/HSYNC
LD1
LD11
TMR2OUT
LD13
D
E
A21
A22
D30
D29
NVDD1
QVSS
UART2_
RTS
UART1_
RXD
UART1_
CTS
SPI1_
MISO
ACD/OE
LD10
TIN
CSI_D0
CSI_
MCLK
E
F
A20
A19
D28
D27
NVDD1
NVDD1
UART2_
CTS
SSI_
RXCLK
SSI_
TXDAT
CLS
QVDD3
LD14
LD15
CSI_D2
CSI_D4
F
G
A17
A18
D26
D25
NVDD1
NVSS
NVDD4
NVSS
NVSS
QVSS
PWMO
CSI_D3
CSI_D7
CSI_HSYNC
CSI_D5
G
H
A15
A16
D23
D24
D22
NVSS
NVSS
NVSS
NVSS
NVDD2
CSI_D1
CSI_
VSYNC
CSI_
PIXCLK
I2C_SDA
TMS
H
J
A14
A12
D21
D20
NVDD1
NVSS
NVSS
QVDD1
NVSS
CSI_D6
I2C_SCL
TCK
TDO
BOOT1
BOOT0
J
K
A13
A11
CS2
D19
NVDD1
NVSS
QVSS
NVDD1
NVSS
D1
BOOT2
TDI
BIG_
ENDIAN
RESET_
OUT
XTAL32K
K
L
A10
A9
D17
D18
NVDD1
NVDD1
CS5
D2
ECB
NVSS
NVSS
POR
QVSS
XTAL16M
EXTAL32K
L
M
D16
D15
D13
D10
EB3
NVDD1
CS4
CS1
BCLK1
RW
NVSS
BOOT3
QVDD2
RESET_IN
EXTAL16M
M
N
A8
A7
D12
EB0
D9
D8
CS3
CS0
PA17
D0
DQM2
DQM0
SDCKE0
TRISTATE
TRST
N
P
D14
A5
A4
A3
A2
A1
D6
D5
MA10
MA11
DQM1
RAS
SDCKE1
CLKO
RESET_SF2
P
R
A6
D11
EB1
EB2
OE
D7
A0
SDCLK
D4
LBA
D3
DQM3
CAS
SDWE
AVDD1
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Burst Clock
This signal is not used and should be floated in an actual application.
CONTRAST FLM/VSYNC
85
Pin-Out and Package Information
1
1
Pin-Out and Package Information
5.1
MAPBGA 256 Package Dimensions
Figure 67 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, with an 0.8 mm pad pitch.
The device designator for the MAPBGA package is VH.
Case Outline 1367
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 67. i.MXL 256 MAPBGA Mechanical Drawing
MC9328MXL Technical Data, Rev. 8
86
Freescale Semiconductor
Pin-Out and Package Information
5.2
MAPBGA 225 Package Dimensions
Figure 68 illustrates the 225 MAPBGA 13 mm × 13 mm package.
Case Outline 1304B
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER
BALLS.
5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE
OF PACKAGE
Figure 68. i.MXL 225 MAPBGA Mechanical Drawing
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
87
Product Documentation
6
6.1
Product Documentation
Revision History
Table 39 provides revision history for this release. This history includes technical content revisions only
and not stylistic or grammatical changes.
Table 39. i.MXL Data Sheet Revision History Rev. 8
Location
Revision
Table 2 on page 4
Signal Names and
Descriptions
• Added the DMA_REQ signal to table.
• Corrected signal name from USBD_OE to USBD_ROE
Table 3 on page 9
Signal Multiplex Table i.MXL
Added Signal Multiplex table from Reference Manual with the following changes:
• Changed I/O Supply Voltage,PB31–20, from NVDD3 to NVDD4
• Added 225 BGA column.
• Removed 69K pull-up resistor from EB1, EB2, and added to D9
Table 10 on page 21
Changed first and second parameters descriptions:
From: Reference Clock freq range, To: DPLL input clock freq range
From: Double clock freq range, To: DPLL output freq range
Table 3 on page 9
Added Signal Multiplex table.
6.2
Reference Documents
The following documents are required for a complete description of the MC9328MXL and are necessary
to design properly with the device. Especially for those not familiar with the ARM920T processor or
previous i.MX processor products, the following documents are helpful when used in conjunction with this
document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXL Product Brief (order number MC9328MXLP)
MC9328MXL Reference Manual (order number MC9328MXLRM)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from
http://www.arm.com.
MC9328MXL Technical Data, Rev. 8
88
Freescale Semiconductor
NOTES
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
89
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Document Number: MC9328MXL
Rev. 8
12/2006
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