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MC9S08AW16CFGER

MC9S08AW16CFGER

  • 厂商:

    NXP(恩智浦)

  • 封装:

    LQFP44

  • 描述:

    IC MCU 8BIT 16KB FLASH 44LQFP

  • 数据手册
  • 价格&库存
MC9S08AW16CFGER 数据手册
Freescale Semiconductor Addendum Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. © Freescale Semiconductor, Inc., 2014. All rights reserved. Part Number MC68HC908JW32 Package Description Original (gold wire) Current (copper wire) package document number package document number 48 QFN 98ARH99048A 98ASA00466D MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D 6 DFN 98ARL10602D 98ASA00735D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9S08QB8 MC9S08QG8 MC9RS08KA2 Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 Data Sheet HCS08 Microcontrollers MC9S08AW60 Rev 2 12/2006 freescale.com MC9S08AW60 Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • • 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Single-wire background debug mode interface Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) On-chip real-time in-circuit emulation (ICE) with two comparators (plus one in BDM), nine trigger modes, and on-chip bus capture buffer. Typically shows approximately 50 instructions before or after the trigger point. Support for up to 32 interrupt/reset sources Memory Options • • Up to 60 KB of on-chip in-circuit programmable FLASH memory with block protection and security options Up to 2 KB of on-chip RAM Clock Source Options • Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming System Protection • • • • Optional computer operating properly (COP) reset Low-voltage detection with reset or interrupt Illegal opcode detection with reset Illegal address detection with reset (some devices don’t have illegal addresses) Power-Saving Modes • Wait plus two stops Peripherals • • • ADC — Up to 16-channel, 10-bit analog-to-digital converter with automatic compare function SCI — Two serial communications interface modules with optional 13-bit break SPI — Serial peripheral interface module • • • IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baud rates with reduced loading Timers — One 2-channel and one 6-channel 16-bit timer/pulse-width modulator (TPM) module: Selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels KBI — Up to 8-pin keyboard interrupt module Input/Output • • • • • • Up to 54 general-purpose input/output (I/O) pins Software-selectable pullups on ports when used as inputs Software-selectable slew rate control on ports when used as outputs Software-selectable drive strength on ports when used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost Package Options MC9S08AW60/48/32 • 64-pin quad flat package (QFP) • 64-pin low-profile quad flat package (LQFP) • 48-pin low-profile quad flat package (QFN) • 44-pin low-profile quad flat package (LQFP) MC9S08AW16 • 48-pin low-profile quad flat package (QFN) • 44-pin low-profile quad flat package (LQFP) MC9S08AW60 Data Sheet Covers: MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 MC9S08AW60 Rev 2 12/2006 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision Number Revision Date 1 1/2006 Initial external release. 12/2006 Includes KBI block changes; new VOL / IOL figures; RIDD spec changes; SC part numbers with ICG trim modifications; addition of Temp Sensor to ADC. Resolved the stop IDD issues, added RTI figure, bandgap information, and incorporated electricals edits and any ProjectSync issues. 2 Description of Changes This product incorporates SuperFlash® technology licensed from SST. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved. List of Chapters Chapter Title Page Chapter 1 Introduction...................................................................................... 19 Chapter 2 Pins and Connections ..................................................................... 23 Chapter 3 Modes of Operation ......................................................................... 33 Chapter 4 Memory ............................................................................................. 39 Chapter 5 Resets, Interrupts, and System Configuration ............................. 65 Chapter 6 Parallel Input/Output ....................................................................... 81 Chapter 7 Central Processor Unit (S08CPUV2) ............................................ 109 Chapter 8 Internal Clock Generator (S08ICGV4) .......................................... 129 Chapter 9 Keyboard Interrupt (S08KBIV1) .................................................... 157 Chapter 10 Timer/PWM (S08TPMV2) ............................................................... 165 Chapter 11 Serial Communications Interface (S08SCIV2)............................. 181 Chapter 12 Serial Peripheral Interface (S08SPIV3) ........................................ 199 Chapter 13 Inter-Integrated Circuit (S08IICV1) ............................................... 215 Chapter 14 Analog-to-Digital Converter (S08ADC10V1)................................ 233 Chapter 15 Development Support ................................................................... 261 Appendix A Electrical Characteristics and Timing Specifications ................ 283 Appendix B Ordering Information and Mechanical Drawings........................ 309 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 7 Contents Section Number Title Page Chapter 1 Introduction 1.1 1.2 1.3 Overview .........................................................................................................................................19 MCU Block Diagrams .....................................................................................................................19 System Clock Distribution ..............................................................................................................21 Chapter 2 Pins and Connections 2.1 2.2 2.3 Introduction .....................................................................................................................................23 Device Pin Assignment ...................................................................................................................24 Recommended System Connections ...............................................................................................26 2.3.1 Power (VDD, 2 x VSS, VDDAD, VSSAD) .........................................................................28 2.3.2 Oscillator (XTAL, EXTAL) ............................................................................................28 RESET Pin ......................................................................................................................29 2.3.3 2.3.4 Background/Mode Select (BKGD/MS) .........................................................................29 2.3.5 ADC Reference Pins (VREFH, VREFL) ...........................................................................29 2.3.6 External Interrupt Pin (IRQ) ...........................................................................................29 2.3.7 General-Purpose I/O and Peripheral Ports .....................................................................30 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................33 Features ...........................................................................................................................................33 Run Mode ........................................................................................................................................33 Active Background Mode ................................................................................................................33 Wait Mode .......................................................................................................................................34 Stop Modes ......................................................................................................................................34 3.6.1 Stop2 Mode ....................................................................................................................35 3.6.2 Stop3 Mode ....................................................................................................................36 3.6.3 Active BDM Enabled in Stop Mode ...............................................................................36 3.6.4 LVD Enabled in Stop Mode ...........................................................................................37 3.6.5 On-Chip Peripheral Modules in Stop Modes .................................................................37 Chapter 4 Memory 4.1 4.2 4.3 MC9S08AW60 Series Memory Map ..............................................................................................39 4.1.1 Reset and Interrupt Vector Assignments ........................................................................42 Register Addresses and Bit Assignments ........................................................................................43 RAM ................................................................................................................................................49 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 9 Section Number 4.4 4.5 4.6 Title Page FLASH ............................................................................................................................................50 4.4.1 Features ...........................................................................................................................51 4.4.2 Program and Erase Times ...............................................................................................51 4.4.3 Program and Erase Command Execution .......................................................................52 4.4.4 Burst Program Execution ...............................................................................................53 4.4.5 Access Errors ..................................................................................................................55 4.4.6 FLASH Block Protection ...............................................................................................55 4.4.7 Vector Redirection ..........................................................................................................56 Security ............................................................................................................................................56 FLASH Registers and Control Bits .................................................................................................58 4.6.1 FLASH Clock Divider Register (FCDIV) ......................................................................58 4.6.2 FLASH Options Register (FOPT and NVOPT) .............................................................59 4.6.3 FLASH Configuration Register (FCNFG) .....................................................................60 4.6.4 FLASH Protection Register (FPROT and NVPROT) ....................................................61 4.6.5 FLASH Status Register (FSTAT) ...................................................................................61 4.6.6 FLASH Command Register (FCMD) ............................................................................63 Chapter 5 Resets, Interrupts, and System Configuration 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Introduction .....................................................................................................................................65 Features ...........................................................................................................................................65 MCU Reset ......................................................................................................................................65 Computer Operating Properly (COP) Watchdog .............................................................................66 Interrupts .........................................................................................................................................66 5.5.1 Interrupt Stack Frame .....................................................................................................67 5.5.2 External Interrupt Request (IRQ) Pin .............................................................................68 5.5.3 Interrupt Vectors, Sources, and Local Masks .................................................................69 Low-Voltage Detect (LVD) System ................................................................................................71 5.6.1 Power-On Reset Operation .............................................................................................71 5.6.2 LVD Reset Operation .....................................................................................................71 5.6.3 LVD Interrupt Operation ................................................................................................71 5.6.4 Low-Voltage Warning (LVW) ........................................................................................71 Real-Time Interrupt (RTI) ...............................................................................................................71 MCLK Output .................................................................................................................................72 Reset, Interrupt, and System Control Registers and Control Bits ...................................................72 5.9.1 Interrupt Pin Request Status and Control Register (IRQSC) .........................................73 5.9.2 System Reset Status Register (SRS) ...............................................................................74 5.9.3 System Background Debug Force Reset Register (SBDFR) ..........................................75 5.9.4 System Options Register (SOPT) ...................................................................................75 5.9.5 System MCLK Control Register (SMCLK) ...................................................................76 5.9.6 System Device Identification Register (SDIDH, SDIDL) ..............................................77 5.9.7 System Real-Time Interrupt Status and Control Register (SRTISC) .............................78 MC9S08AW60 Data Sheet, Rev 2 10 Freescale Semiconductor Section Number 5.9.8 5.9.9 Title Page System Power Management Status and Control 1 Register (SPMSC1) .........................79 System Power Management Status and Control 2 Register (SPMSC2) .........................80 Chapter 6 Parallel Input/Output 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Introduction .....................................................................................................................................81 Features ...........................................................................................................................................81 Pin Descriptions ..............................................................................................................................82 6.3.1 Port A ..............................................................................................................................82 6.3.2 Port B ..............................................................................................................................82 6.3.3 Port C ..............................................................................................................................83 6.3.4 Port D ..............................................................................................................................83 6.3.5 Port E ..............................................................................................................................84 6.3.6 Port F ..............................................................................................................................85 6.3.7 Port G ..............................................................................................................................85 Parallel I/O Control .........................................................................................................................86 Pin Control ......................................................................................................................................87 6.5.1 Internal Pullup Enable ....................................................................................................87 6.5.2 Output Slew Rate Control Enable ..................................................................................87 6.5.3 Output Drive Strength Select ..........................................................................................87 Pin Behavior in Stop Modes ............................................................................................................88 Parallel I/O and Pin Control Registers ............................................................................................88 6.7.1 Port A I/O Registers (PTAD and PTADD) .....................................................................88 6.7.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) ..............................................89 6.7.3 Port B I/O Registers (PTBD and PTBDD) .....................................................................91 6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) ..............................................92 6.7.5 Port C I/O Registers (PTCD and PTCDD) .....................................................................94 6.7.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) ..............................................95 6.7.7 Port D I/O Registers (PTDD and PTDDD) ....................................................................97 6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) .............................................98 6.7.9 Port E I/O Registers (PTED and PTEDD) ....................................................................100 6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) .............................................101 6.7.11 Port F I/O Registers (PTFD and PTFDD) ....................................................................103 6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ..............................................104 6.7.13 Port G I/O Registers (PTGD and PTGDD) ..................................................................106 6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ...........................................107 Chapter 7 Central Processor Unit (S08CPUV2) 7.1 7.2 Introduction ...................................................................................................................................109 7.1.1 Features .........................................................................................................................109 Programmer’s Model and CPU Registers .....................................................................................110 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 11 Section Number 7.3 7.4 7.5 Title Page 7.2.1 Accumulator (A) ...........................................................................................................110 7.2.2 Index Register (H:X) ....................................................................................................110 7.2.3 Stack Pointer (SP) .........................................................................................................111 7.2.4 Program Counter (PC) ..................................................................................................111 7.2.5 Condition Code Register (CCR) ...................................................................................111 Addressing Modes .........................................................................................................................113 7.3.1 Inherent Addressing Mode (INH) ................................................................................113 7.3.2 Relative Addressing Mode (REL) ................................................................................113 7.3.3 Immediate Addressing Mode (IMM) ...........................................................................113 7.3.4 Direct Addressing Mode (DIR) ....................................................................................113 7.3.5 Extended Addressing Mode (EXT) ..............................................................................114 7.3.6 Indexed Addressing Mode ............................................................................................114 Special Operations .........................................................................................................................115 7.4.1 Reset Sequence .............................................................................................................115 7.4.2 Interrupt Sequence ........................................................................................................115 7.4.3 Wait Mode Operation ...................................................................................................116 7.4.4 Stop Mode Operation ...................................................................................................116 7.4.5 BGND Instruction ........................................................................................................117 HCS08 Instruction Set Summary ..................................................................................................118 Chapter 8 Internal Clock Generator (S08ICGV4) 8.1 8.2 8.3 8.4 Introduction ...................................................................................................................................131 8.1.1 Features .........................................................................................................................131 8.1.2 Modes of Operation ......................................................................................................132 8.1.3 Block Diagram ..............................................................................................................133 External Signal Description ..........................................................................................................133 8.2.1 EXTAL — External Reference Clock / Oscillator Input ..............................................133 8.2.2 XTAL — Oscillator Output ..........................................................................................133 8.2.3 External Clock Connections .........................................................................................134 8.2.4 External Crystal/Resonator Connections ......................................................................134 Register Definition ........................................................................................................................135 8.3.1 ICG Control Register 1 (ICGC1) .................................................................................135 8.3.2 ICG Control Register 2 (ICGC2) .................................................................................137 8.3.3 ICG Status Register 1 (ICGS1) ....................................................................................138 8.3.4 ICG Status Register 2 (ICGS2) ....................................................................................139 8.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL) ...............................................................139 8.3.6 ICG Trim Register (ICGTRM) .....................................................................................140 Functional Description ..................................................................................................................140 8.4.1 Off Mode (Off) .............................................................................................................141 8.4.2 Self-Clocked Mode (SCM) ...........................................................................................141 8.4.3 FLL Engaged, Internal Clock (FEI) Mode ...................................................................142 MC9S08AW60 Data Sheet, Rev 2 12 Freescale Semiconductor Section Number 8.5 Title Page 8.4.4 FLL Engaged Internal Unlocked ..................................................................................143 8.4.5 FLL Engaged Internal Locked ......................................................................................143 8.4.6 FLL Bypassed, External Clock (FBE) Mode ...............................................................143 8.4.7 FLL Engaged, External Clock (FEE) Mode .................................................................143 8.4.8 FLL Lock and Loss-of-Lock Detection ........................................................................144 8.4.9 FLL Loss-of-Clock Detection ......................................................................................145 8.4.10 Clock Mode Requirements ...........................................................................................146 8.4.11 Fixed Frequency Clock .................................................................................................147 8.4.12 High Gain Oscillator .....................................................................................................147 Initialization/Application Information ..........................................................................................147 8.5.1 Introduction ..................................................................................................................147 8.5.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz ........................149 8.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................151 8.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency ....................153 8.5.5 Example #4: Internal Clock Generator Trim ................................................................155 Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 9.2 9.3 9.4 9.5 Introduction ...................................................................................................................................157 Keyboard Pin Sharing ....................................................................................................................157 Features .........................................................................................................................................158 9.3.1 KBI Block Diagram ......................................................................................................160 Register Definition ........................................................................................................................160 9.4.1 KBI Status and Control Register (KBI1SC) .................................................................161 9.4.2 KBI Pin Enable Register (KBI1PE) .............................................................................162 Functional Description ..................................................................................................................162 9.5.1 Pin Enables ...................................................................................................................162 9.5.2 Edge and Level Sensitivity ...........................................................................................162 9.5.3 KBI Interrupt Controls .................................................................................................163 Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction ...................................................................................................................................165 10.2 Features .........................................................................................................................................165 10.2.1 Features .........................................................................................................................167 10.2.2 Block Diagram ..............................................................................................................167 10.3 External Signal Description ..........................................................................................................169 10.3.1 External TPM Clock Sources .......................................................................................169 10.3.2 TPMxCHn — TPMx Channel n I/O Pins .....................................................................169 10.4 Register Definition ........................................................................................................................169 10.4.1 Timer x Status and Control Register (TPMxSC) ..........................................................170 10.4.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) .............................................171 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 13 Section Number Title Page 10.4.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) .............................172 10.4.4 Timer x Channel n Status and Control Register (TPMxCnSC) ....................................173 10.4.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ....................................174 10.5 Functional Description ..................................................................................................................175 10.5.1 Counter .........................................................................................................................175 10.5.2 Channel Mode Selection ...............................................................................................176 10.5.3 Center-Aligned PWM Mode ........................................................................................178 10.6 TPM Interrupts ..............................................................................................................................179 10.6.1 Clearing Timer Interrupt Flags .....................................................................................179 10.6.2 Timer Overflow Interrupt Description ..........................................................................179 10.6.3 Channel Event Interrupt Description ............................................................................180 10.6.4 PWM End-of-Duty-Cycle Events .................................................................................180 Chapter 11 Serial Communications Interface (S08SCIV2) 11.1 Introduction ...................................................................................................................................181 11.1.1 Features .........................................................................................................................183 11.1.2 Modes of Operation ......................................................................................................183 11.1.3 Block Diagram ..............................................................................................................183 11.2 Register Definition ........................................................................................................................185 11.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBHL) ........................................................186 11.2.2 SCI Control Register 1 (SCIxC1) .................................................................................187 11.2.3 SCI Control Register 2 (SCIxC2) .................................................................................188 11.2.4 SCI Status Register 1 (SCIxS1) ....................................................................................189 11.2.5 SCI Status Register 2 (SCIxS2) ....................................................................................191 11.2.6 SCI Control Register 3 (SCIxC3) .................................................................................191 11.2.7 SCI Data Register (SCIxD) ..........................................................................................192 11.3 Functional Description ..................................................................................................................192 11.3.1 Baud Rate Generation ...................................................................................................193 11.3.2 Transmitter Functional Description ..............................................................................193 11.3.3 Receiver Functional Description ..................................................................................194 11.3.4 Interrupts and Status Flags ...........................................................................................196 11.3.5 Additional SCI Functions .............................................................................................197 Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.0.1 Features .........................................................................................................................201 12.0.2 Block Diagrams ............................................................................................................201 12.0.3 SPI Baud Rate Generation ............................................................................................203 12.1 External Signal Description ..........................................................................................................204 12.1.1 SPSCK — SPI Serial Clock .........................................................................................204 12.1.2 MOSI — Master Data Out, Slave Data In ....................................................................204 MC9S08AW60 Data Sheet, Rev 2 14 Freescale Semiconductor Section Number Title Page 12.1.3 MISO — Master Data In, Slave Data Out ....................................................................204 12.1.4 SS — Slave Select ........................................................................................................204 12.2 Modes of Operation .......................................................................................................................205 12.2.1 SPI in Stop Modes ........................................................................................................205 12.3 Register Definition ........................................................................................................................205 12.3.1 SPI Control Register 1 (SPI1C1) ..................................................................................205 12.3.2 SPI Control Register 2 (SPI1C2) ..................................................................................206 12.3.3 SPI Baud Rate Register (SPI1BR) ...............................................................................207 12.3.4 SPI Status Register (SPI1S) ..........................................................................................208 12.3.5 SPI Data Register (SPI1D) ...........................................................................................209 12.4 Functional Description ..................................................................................................................210 12.4.1 SPI Clock Formats ........................................................................................................210 12.4.2 SPI Interrupts ................................................................................................................213 12.4.3 Mode Fault Detection ...................................................................................................213 Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction ...................................................................................................................................215 13.1.1 Features .........................................................................................................................217 13.1.2 Modes of Operation ......................................................................................................217 13.1.3 Block Diagram ..............................................................................................................218 13.2 External Signal Description ..........................................................................................................218 13.2.1 SCL — Serial Clock Line .............................................................................................218 13.2.2 SDA — Serial Data Line ..............................................................................................218 13.3 Register Definition ........................................................................................................................218 13.3.1 IIC Address Register (IIC1A) .......................................................................................219 13.3.2 IIC Frequency Divider Register (IIC1F) ......................................................................219 13.3.3 IIC Control Register (IIC1C) ........................................................................................222 13.3.4 IIC Status Register (IIC1S) ..........................................................................................223 13.3.5 IIC Data I/O Register (IIC1D) ......................................................................................224 13.4 Functional Description ..................................................................................................................225 13.4.1 IIC Protocol ..................................................................................................................225 13.5 Resets ............................................................................................................................................228 13.6 Interrupts .......................................................................................................................................228 13.6.1 Byte Transfer Interrupt .................................................................................................229 13.6.2 Address Detect Interrupt ...............................................................................................229 13.6.3 Arbitration Lost Interrupt .............................................................................................229 13.7 Initialization/Application Information ..........................................................................................230 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 15 Section Number Title Page Chapter 14 Analog-to-Digital Converter (S08ADC10V1) 14.1 Overview .......................................................................................................................................233 14.2 Channel Assignments ....................................................................................................................233 14.2.1 Alternate Clock .............................................................................................................234 14.2.2 Hardware Trigger ..........................................................................................................234 14.2.3 Temperature Sensor ......................................................................................................235 14.2.4 Features .........................................................................................................................237 14.2.5 Block Diagram ..............................................................................................................237 14.3 External Signal Description ..........................................................................................................238 14.3.1 Analog Power (VDDAD) ................................................................................................239 14.3.2 Analog Ground (VSSAD) ..............................................................................................239 14.3.3 Voltage Reference High (VREFH) .................................................................................239 14.3.4 Voltage Reference Low (VREFL) ..................................................................................239 14.3.5 Analog Channel Inputs (ADx) ......................................................................................239 14.4 Register Definition ........................................................................................................................239 14.4.1 Status and Control Register 1 (ADC1SC1) ..................................................................239 14.4.2 Status and Control Register 2 (ADC1SC2) ..................................................................241 14.4.3 Data Result High Register (ADC1RH) ........................................................................242 14.4.4 Data Result Low Register (ADC1RL) ..........................................................................242 14.4.5 Compare Value High Register (ADC1CVH) ................................................................243 14.4.6 Compare Value Low Register (ADC1CVL) .................................................................243 14.4.7 Configuration Register (ADC1CFG) ............................................................................243 14.4.8 Pin Control 1 Register (APCTL1) ................................................................................245 14.4.9 Pin Control 2 Register (APCTL2) ................................................................................246 14.4.10 Pin Control 3 Register (APCTL3) ................................................................................247 14.5 Functional Description ..................................................................................................................248 14.5.1 Clock Select and Divide Control ..................................................................................248 14.5.2 Input Select and Pin Control .........................................................................................249 14.5.3 Hardware Trigger ..........................................................................................................249 14.5.4 Conversion Control .......................................................................................................249 14.5.5 Automatic Compare Function ......................................................................................252 14.5.6 MCU Wait Mode Operation .........................................................................................252 14.5.7 MCU Stop3 Mode Operation .......................................................................................252 14.5.8 MCU Stop1 and Stop2 Mode Operation ......................................................................253 14.6 Initialization Information ..............................................................................................................253 14.6.1 ADC Module Initialization Example ...........................................................................253 14.7 Application Information ................................................................................................................255 14.7.1 External Pins and Routing ............................................................................................255 14.7.2 Sources of Error ............................................................................................................257 MC9S08AW60 Data Sheet, Rev 2 16 Freescale Semiconductor Section Number Title Page Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................261 15.1.1 Features .........................................................................................................................262 15.2 Background Debug Controller (BDC) ..........................................................................................262 15.2.1 BKGD Pin Description .................................................................................................263 15.2.2 Communication Details ................................................................................................264 15.2.3 BDC Commands ...........................................................................................................268 15.2.4 BDC Hardware Breakpoint ..........................................................................................270 15.3 On-Chip Debug System (DBG) ....................................................................................................271 15.3.1 Comparators A and B ...................................................................................................271 15.3.2 Bus Capture Information and FIFO Operation .............................................................271 15.3.3 Change-of-Flow Information ........................................................................................272 15.3.4 Tag vs. Force Breakpoints and Triggers .......................................................................272 15.3.5 Trigger Modes ..............................................................................................................273 15.3.6 Hardware Breakpoints ..................................................................................................275 15.4 Register Definition ........................................................................................................................275 15.4.1 BDC Registers and Control Bits ...................................................................................275 15.4.2 System Background Debug Force Reset Register (SBDFR) ........................................277 15.4.3 DBG Registers and Control Bits ..................................................................................278 Appendix A Electrical Characteristics and Timing Specifications A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 Introduction ....................................................................................................................................283 Parameter Classification.................................................................................................................283 Absolute Maximum Ratings...........................................................................................................283 Thermal Characteristics..................................................................................................................285 ESD Protection and Latch-Up Immunity .......................................................................................286 DC Characteristics..........................................................................................................................287 Supply Current Characteristics.......................................................................................................291 ADC Characteristics.......................................................................................................................293 Internal Clock Generation Module Characteristics ........................................................................296 A.9.1 ICG Frequency Specifications.......................................................................................297 AC Characteristics..........................................................................................................................300 A.10.1 Control Timing ..............................................................................................................300 A.10.2 Timer/PWM (TPM) Module Timing.............................................................................302 SPI Characteristics .........................................................................................................................303 FLASH Specifications....................................................................................................................306 EMC Performance..........................................................................................................................307 A.13.1 Radiated Emissions .......................................................................................................307 A.13.2 Conducted Transient Susceptibility...............................................................................307 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 17 Section Number Title Page Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................309 B.2 Orderable Part Numbering System ................................................................................................310 B.2.1 Consumer and Industrial Orderable Part Numbering System .......................................310 B.2.2 Automotive Orderable Part Numbering System............................................................310 B.3 Mechanical Drawings.....................................................................................................................310 MC9S08AW60 Data Sheet, Rev 2 18 Freescale Semiconductor Chapter 1 Introduction 1.1 Overview The MC9S08AW60, MC9S08AW48, MC9S08AW32, and MC9S08AW16 are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for memory sizes and package types. Table 1-2 summarizes the peripheral availability per package type for the devices available in the MC9S08AW60 Series. Table 1-1. Devices in the MC9S08AW60 Series Device FLASH MC9S08AW60 63,280 MC9S08AW48 49,152 MC9S08AW32 32,768 MC9S08AW16 16,384 RAM Package 2048 64 QFP 64 LQFP 48 QFN 44 LQFP 1024 48 QFN 44 LQFP Table 1-2. Peripherals Available per Package Type Package Options 1.2 Feature 64-pin 48-pin 44-pin ADC 16-channel 8-channel 8-channel IIC yes yes yes IRQ yes yes yes KBI1 8 7 6 SCI1 yes yes yes SCI2 yes yes yes SPI1 yes yes yes TPM1 6-channel 4-channel 4-channel TPM1CLK yes no no TPM2 2-channel 2-channel 2-channel TPM2CLK yes no no I/O pins 54 38 34 MCU Block Diagrams The block diagram shows the structure of the MC9S08AW60 Series. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 19 HCS08 CORE BDC DEBUG MODULE (DBG) RTI COP IRQ LVD SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) IIC MODULE (IIC1) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC1) TxD2 SDA1 SCL1 LOW-POWER OSCILLATOR SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR 2-CHANNEL TIMER/PWM MODULE (TPM2) PTE7/SPSCK1 MISO1 SS1 TPM1CLK TPM1CH5– TPM1CH0 RxD1 TxD1 PORT E INTERNAL CLOCK GENERATOR (ICG) 6-CHANNEL TIMER/PWM MODULE (TPM1) SPSCK1 MOSI1 6 TPM2CLK PORT F USER RAM AW60/48/32 = 2048 BYTES AW16 = 1024 BYTES PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTD5/AD1P13 PTD4/AD1P12/TPM2CLK PTD3/AD1P11/KBI1P6 PTD2/AD1P10/KBI1P5 PTD1/AD1P9 PTD0/AD1P8 8 8 AD1P15–AD1P8 USER FLASH (AW60 = 63,280 BYTES) (AW48 = 49,152 BYTES) (AW32 = 32,768 BYTES) (AW16 = 16,384 BYTES) SERIAL PERIPHERAL INTERFACE MODULE (SPI1) PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PTC1/SDA1 PTC0/SCL1 RxD2 AD1P7–AD1P0 VSSAD VREFL VREFH VSS PTB7/AD1P7– PTB0/AD1P0 PORT C RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VDDAD VDD 8 PORT D IRQ PTA7– PTA0 HCS08 SYSTEM CONTROL TPM2CH1–TPM2CH0 2 KBI1P7–KBI1P5 3 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) KBI1P4–KBI1P0 EXTAL XTAL 5 NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software-configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1) 3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD. 4. Pin contains integrated pullup device. 5. Pins PTD7, PTD3, PTD2, and PTG4 contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). PORT G RESET 8 CPU PORT B BKGD/MS PORT A Chapter 1 Introduction PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTE3/TPM1CH1 PTE2/TPM1CH0 PTE1/RxD1 PTE0/TxD1 PTF7 PTF6 PTF5/TPM2CH1 PTF4/TPM2CH0 PTF3/TPM1CH5 PTF2/TPM1CH4 PTF1/TPM1CH3 PTF0/TPM1CH2 PTG6/EXTAL PTG5/XTAL PTG4/KBI1P4 PTG3/KBI1P3 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 Figure 1-1. MC9S08AW60 Series Block Diagram MC9S08AW60 Data Sheet, Rev 2 20 Freescale Semiconductor Chapter 1 Introduction Table 1-3 lists the functional versions of the on-chip modules. Table 1-3. Versions of On-Chip Modules Module Analog-to-Digital Converter Version (S08ADC10) 1 (S08ICG) 4 (S08IIC) 1 Keyboard Interrupt (S08KBI) 1 Serial Communications Interface (S08SCI) 2 Serial Peripheral Interface (S08SPI) 3 Timer Pulse-Width Modulator (S08TPM) 2 Central Processing Unit (S08CPU) 2 (DBG) 2 Internal Clock Generator Inter-Integrated Circuit Debug Module 1.3 System Clock Distribution ICGERCLK SYSTEM CONTROL LOGIC TPM1 TPM2 IIC1 SCI1 SCI2 SPI1 RTI FFE ÷2 ICG FIXED FREQ CLOCK (XCLK) ICGOUT ÷2 BUSCLK ICGLCLK* CPU BDC * ICGLCLK is the alternate BDC clock source for the MC9S08AW60 Series. ADC1 RAM ADC has min and max frequency requirements. See Chapter 14, “Analog-to-Digital Converter (S08ADC10V1) and Appendix A, “Electrical Characteristics and Timing Specifications FLASH FLASH has frequency requirements for program and erase operation. See Appendix A, “Electrical Characteristics and Timing Specifications. Figure 1-2. System Clock Distribution Diagram Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 21 Chapter 1 Introduction • • • — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module — Control bits inside the ICG determine which source is connected. FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be ICGERCLK/2. Otherwise the fixed-frequency clock will be BUSCLK. ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. Can also be used as the ALTCLK input to the ADC module. MC9S08AW60 Data Sheet, Rev 2 22 Freescale Semiconductor Chapter 2 Pins and Connections 2.1 Introduction This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 23 Chapter 2 Pins and Connections PTC2/MCLK PTC1/SDA1 PTC0/SCL1 VSS PTG6/EXTAL PTG5/XTAL BKGD/MS VREFL VREFH PTD7/KBI1P7/AD1P15 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 PTC4 1 PTG4/KBI1P4 PTC3/TxD2 Device Pin Assignment PTC5/RxD2 2.2 49 48 PTG3/KBI1P3 IRQ 2 47 PTD3/KBI1P6/AD1P11 RESET 3 46 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 45 VSSAD PTF1/TPM1CH3 5 44 VDDAD PTF2/TPM1CH4 6 43 PTD1/AD1P9 PTF3/TPM1CH5 7 42 PTD0/AD1P8 PTF4/TPM2CH0 8 41 PTB7/AD1P7 PTC6 9 40 PTB6/AD1P6 PTF7 10 39 PTB5/AD1P5 PTF5/TPM2CH1 11 38 PTB4/AD1P4 PTF6 12 37 PTB3/AD1P3 PTE0/TxD1 13 36 PTB2/AD1P2 PTE1/RxD1 14 35 PTB1/AD1P1 PTE2/TPM1CH0 15 34 PTB0/AD1P0 64-Pin QFP 64-Pin LQFP PTE3/TPM1CH1 16 33 PTA7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VDD VSS PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTA6 32 17 Figure 2-1. MC9S08AW60 Series in 64-Pin QFP/LQFP Package MC9S08AW60 Data Sheet, Rev 2 24 Freescale Semiconductor VREFH PTG4/KB1IP4 38 37 39 VREFL 40 BKGD/MS 41 PTG5/XTAL 42 PTG6/EXTAL 43 VSS 44 PTC0/SCL1 45 PTC1/SDA1 46 PTC2/MCLK 47 PTC3/TxD2 48 PTC5/RxD2 Chapter 2 Pins and Connections PTC4 1 36 PTG3/KBI1P3 IRQ 2 35 PTD3/KBI1P6/AD1P11 RESET 3 34 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 33 VSSAD PTF1/TPM1CH3 5 32 VDDAD PTF4/TPM2CH0 6 31 PTD1/AD1P9 48-Pin QFN PTA2 24 25 PTA7 PTA1 23 PTE3/TPM1CH1 12 PTA0 22 26 PTB0/AD1P0 PTG2/KBI1P2 21 PTE2/TPM1CH0 11 PTG1/KBI1P1 20 27 PTB1/AD1P1 PTG0/KBI1P0 19 PTE1/RxD1 10 VDD 18 28 PTB2/AD1P2 VSS 17 PTE0/TxD1 9 PTE7/SPSCK1 16 29 PTB3/AD1P3 PTE6/MOSI1 15 PTF6 8 PTE5/MISO1 14 30 PTD0/AD1P8 PTE4/SS1 13 PTF5/TPM2CH1 7 Figure 2-2. MC9S08AW60 Series in 48-Pin QFN Package MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 25 34 44 43 PTC4 1 VREFH VREFL BKGD/MS PTG5/XTAL PTG6/EXTAL VSS PTC0/SCL1 PTC1/SDA1 PTC2/MCLK PTC3/TxD2 PTC5/RxD2 Chapter 2 Pins and Connections 42 41 40 39 38 37 36 35 33 PTG3/KBI1P3 IRQ 2 32 PTD3/KBI1P6/AD1P11 RESET 3 31 PTD2/KBI1P5/AD1P10 PTF0/TPM1CH2 4 30 VSSAD PTF1/TPM1CH3 5 29 VDDAD 28 PTD1/AD1P9 44-Pin LQFP PTF4/TPM2CH0 6 PTF5/TPM2CH1 7 27 PTD0/AD1P8 PTE0/TxD1 8 26 PTB3/AD1P3 PTE1/RxD1 9 25 PTB2/AD1P2 PTE2/TPM1CH0 10 24 PTB1/AD1P1 PTE3/TPM1CH1 11 23 PTB0/AD1P0 13 14 15 16 17 18 19 20 21 PTA0 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VDD VSS PTE7/SPSCK1 PTE6/MOSI1 PTE5/MISO1 PTE4/SS1 PTA1 22 12 Figure 2-3. MC9S08AW60 Series in 44-Pin LQFP Package 2.3 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08AW60 Series application systems. MC9S08AW60 Data Sheet, Rev 2 26 Freescale Semiconductor Chapter 2 Pins and Connections VREFH CBYAD 0.1 μF PTA0 + CBLK + 10 μF 5V PTA1 VSSAD VREFL VDD VDD SYSTEM POWER MC9S08AW60 VDDAD PTA2 PORT A CBY 0.1 μF PTA3 PTA4 PTA5 VSS (x2) PTA6 PTA7 NOTE 1 RF C1 PTB0/AD1P0 RS XTAL NOTE 2 C2 X1 EXTAL NOTE 2 PTB1/AD1P1 PTB2/AD1P2 PORT B 1 BKGD/MS VDD 4.7 kΩ–10 kΩ PORT C INTERRUPT INPUT 0.1 μF I/O AND PTB7/AD1P7 PERIPHERAL PTC0/SCL1 INTERFACE TO PTC1/SDA1 APPLICATION PTC3/TxD2 SYSTEM PTC4 PTC5/RxD2 4.7 kΩ– 10 kΩ ASYNCHRONOUS PTB6/AD1P6 PTC2/MCLK RESET NOTE 3 0.1 μF VDD OPTIONAL MANUAL RESET PTB4/AD1P4 PTB5/AD1P5 BACKGROUND HEADER VDD PTB3/AD1P3 PTC6 IRQ NOTE 3 PTD0/AD1P8 PTD1/AD1P9 PTG0/KBI1P0 PTD2/AD1P10/KBI1P5 PTG1/KBI1P1 PTG2/KBI1P2 PTG3/KBI1P3 NOTES: 1. Not required if using the internal clock option. 2. These are the same pins as PTG5 and PTG6 3. RC filters on RESET and IRQ are recommended for EMC-sensitive applications. PORT G PORT D PTD3/AD1P11/KBI1P6 PTD4/AD1P12/TPM2CLK PTG4/KBI1P4 PTG5/XTAL PTD5/AD1P13 PTG6/EXTAL PTD7/AD1P15/KBI1P7 PTD6/AD1P14/TPM1CLK PTF0/TPM1CH2 PTE0/TxD1 PTF1/TPM1CH3 PTE1/RxD1 PTE2/TPM1CH0 PTF2/TPM1CH4 PTF3/TPM1CH5 PTF4/TPM2CH0 PORT F PORT E PTE3/TPM1CH1 PTE4/SS1 PTE5/MISO1 PTF5/TPM2CH1 PTF6 PTE6/MOSI1 PTF7 PTE7/SPSCK1 Figure 2-4. Basic System Connections MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 27 Chapter 2 Pins and Connections 2.3.1 Power (VDD, 2 x VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the paired VDD and VSS power pins as practical to suppress high-frequency noise. The MC9S08AW60 has a second VSS pin. This pin should be connected to the system ground plane or to the primary VSS pin through a low-impedance connection. VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to the ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the analog power pins as practical to suppress high-frequency noise. 2.3.2 Oscillator (XTAL, EXTAL) Out of reset, the MCU uses an internally generated clock (self-clocked mode — fSelf_reset) equivalent to about 8-MHz crystal rate. This frequency source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU. For more information on the ICG, see the Chapter 8, “Internal Clock Generator (S08ICGV4).” The oscillator amplitude on XTAL and EXTAL is gain limited for low-power oscillation. Typically, these pins have a 1-V peak-to-peak signal. For noisy environments, the high gain output (HGO) bit can be set to enable rail-to-rail oscillation. The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin. Refer to Figure 2-4 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size. As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). MC9S08AW60 Data Sheet, Rev 2 28 Freescale Semiconductor Chapter 2 Pins and Connections 2.3.3 RESET Pin RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver, and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 bus cycles, released, and sampled again approximately 38 bus cycles later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry expects the reset pin sample to return a logic 1. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS). In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See Figure 2-4 for an example. 2.3.4 Background/Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and can be used for background debug communication. While functioning as a background/mode select pin, the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew rate control. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the rising edge of reset which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin. 2.3.5 ADC Reference Pins (VREFH, VREFL) The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs respectively for the ADC module. 2.3.6 External Interrupt Pin (IRQ) The IRQ pin is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. If the IRQ function is not enabled, this pin does not perform any function. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 29 Chapter 2 Pins and Connections When IRQ is configured as the IRQ input and is set to detect rising edges, a pulldown device rather than a pullup device is enabled. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-4 for an example. 2.3.7 General-Purpose I/O and Peripheral Ports The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and serial I/O systems. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the appropriate chapter from Table 2-1. Table 2-1. Pin Sharing Priority Lowest Highest Port Pins Alternate Function Reference1 Alternate Function PTB7–PTB0 AD1P7–AD1P0 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” PTC5, PTC3 RxD2–TxD2 Chapter 11, “Serial Communications Interface (S08SCIV2)” PTC2 MCLK Chapter 5, “Resets, Interrupts, and System Configuration” PTC1–PTC0 SCL1–SDA1 Chapter 13, “Inter-Integrated Circuit (S08IICV1)” PTD7 KBI1P7 AD1P15 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 9, “Keyboard Interrupt (S08KBIV1)” PTD6 TPM1CLK AD1P14 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 10, “Timer/PWM (S08TPMV2)” PTD5 AD1P13 AD1P13 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” PTD4 TPM2CLK AD1P12 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 10, “Timer/PWM (S08TPMV2)” PTD3–PTD2 KBI1P6–KBI1P5 AD1P11–AD1P10 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” Chapter 9, “Keyboard Interrupt (S08KBIV1)” PTD1–PTD0 AD1P9–AD1P8 Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” PTE7 PTE6 PTE5 PTE4 SPSCK1 MOSI1 MISO1 SS1 Chapter 12, “Serial Peripheral Interface (S08SPIV3)” PTE3–PTE2 TPM1CH1– TPM1CH0 Chapter 10, “Timer/PWM (S08TPMV2)” PTE1–PTE0 RxD1–TxD1 Chapter 11, “Serial Communications Interface (S08SCIV2)” PTF5–PTF4 TPM2CH1– TPM2CH0 Chapter 10, “Timer/PWM (S08TPMV2)” MC9S08AW60 Data Sheet, Rev 2 30 Freescale Semiconductor Chapter 2 Pins and Connections Table 2-1. Pin Sharing Priority Lowest Highest Port Pins 1 Alternate Function Reference1 Alternate Function PTF3–PTF0 TPM1CH5– TPM1CH2 Chapter 10, “Timer/PWM (S08TPMV2)” PTG4–PTG0 KBI1P4–KBI1P0 Chapter 9, “Keyboard Interrupt (S08KBIV1)” PTG6–PTG5 EXTAL–XTAL Chapter 8, “Internal Clock Generator (S08ICGV4)” See the listed chapter for information about modules that share these pins. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output” chapter for more details. Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD7, PTD3, PTD2, and PTG4 pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices. NOTE When an alternative function is first enabled it is possible to get a spurious edge to the module, user software should clear out any associated flags before interrupts are enabled. Table 2-1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. It is recommended that all modules that share a pin be disabled before enabling another module. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 31 Chapter 2 Pins and Connections MC9S08AW60 Data Sheet, Rev 2 32 Freescale Semiconductor Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08AW60 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.3 Features Active background mode for code development Wait mode: — CPU shuts down to conserve power — System clocks running — Full voltage regulation maintained Stop modes: — System clocks stopped; voltage regulator in standby — Stop2 — Partial power down of internal circuits, RAM contents retained — Stop3 — All internal circuits powered for fast recovery Run Mode This is the normal operating mode for the MC9S08AW60 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at $FFFE:$FFFF after reset. 3.4 Active Background Mode The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for analyzing MCU operation during software development. Active background mode is entered in any of five ways: • When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 33 Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BDC register access commands — The BACKGROUND command • Active background commands, which can only be executed while the MCU is in active background mode. Active background commands include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user’s application program (GO) The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08AW60 Series is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed. The active background mode can also be used to erase and reprogram the FLASH memory after it has been previously programmed. For additional information about the active background mode, refer to Chapter 15, “Development Support.” 3.5 Wait Mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. 3.6 Stop Modes One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when MC9S08AW60 Data Sheet, Rev 2 34 Freescale Semiconductor Chapter 3 Modes of Operation the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The MC9S08AW60 Series family of devices does not include stop1 mode. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1. Stop Mode Behavior 1 Mode PPDC CPU, Digital Peripherals, FLASH RAM ICG ADC1 Regulator I/O Pins RTI Stop2 1 Off Standby Off Disabled Standby States held Optionally on Stop3 0 Standby Standby Off1 Optionally on Standby States held Optionally on Crystal oscillator can be configured to run in stop3. Please see the ICG registers. 3.6.1 Stop2 Mode The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2 selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to operate in stop (LVDSE = 0 or LVDE = 0). If the LVD is enabled in stop, then the MCU enters stop3 upon the execution of the STOP instruction regardless of the state of PPDC. Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a logic 1 is written to PPDACK in SPMSC2. Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before entering stop2. NOTE Although this IRQ pin is automatically configured as active low input, the pullup associated with the IRQ pin is not automatically enabled. Therefore, if an external pullup is not used, the internal pullup must be enabled by setting IRQPE in IRQSC. Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default reset states and must be initialized. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 35 Chapter 3 Modes of Operation After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2. To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. 3.6.2 Stop3 Mode Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time interrupt (RTI), LVD, ADC, IRQ, or the KBI. If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector. 3.6.3 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in Chapter 15, “Development Support” of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled. MC9S08AW60 Data Sheet, Rev 2 36 Freescale Semiconductor Chapter 3 Modes of Operation Table 3-2. BDM Enabled Stop Mode Behavior Mode PPDC CPU, Digital Peripherals, FLASH RAM ICG ADC1 Regulator I/O Pins RTI Stop3 0 Standby Standby Active Optionally on Active States held Optionally on 3.6.4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the LVD is enabled. Table 3-3. LVD Enabled Stop Mode Behavior 1 Mode PPDC CPU, Digital Peripherals, FLASH RAM ICG ADC1 Regulator I/O Pins RTI Stop3 0 Standby Standby Off1 Optionally on Active States held Optionally on Crystal oscillator can be configured to run in stop3. Please see the ICG registers. 3.6.5 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2 Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-4. Stop Mode Behavior Mode Peripheral Stop2 Stop3 CPU Off Standby RAM Standby Standby FLASH Off Standby Parallel Port Registers Off Standby ADC1 Off Optionally On1 ICG Off Optionally On2 IIC Off Standby MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 37 Chapter 3 Modes of Operation Table 3-4. Stop Mode Behavior (continued) Mode Peripheral Stop2 Stop3 KBI Off Optionally On3 RTI Optionally On4 Optionally On4 SCI Off Standby SPI Off Standby TPM Off Standby Standby Standby States Held States Held Voltage Regulator I/O Pins 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. 2 OSCSTEN set in ICSC1, else in standby. For high frequency range (RANGE in ICSC2 set) requires the LVD to also be enabled in stop3. 3 During stop3, KBI pins that are enabled continue to function as interrupt sources that are capable of waking the MCU from stop3. 4 This RTI can be enabled to run in stop2 or stop3 with the internal RTI clock source (RTICLKS = 0, in SRTISC). The RTI also can be enabled to run in stop3 with the external clock source (RTICLKS = 1 and OSCSTEN = 1). MC9S08AW60 Data Sheet, Rev 2 38 Freescale Semiconductor Chapter 4 Memory 4.1 MC9S08AW60 Series Memory Map Figure 4-1 shows the memory map for the MC9S08AW60 and MC9S08AW48 MCUs. Figure 4-2 shows the memory map for the MC9S08AW32 and MC9S08AW16 MCUs. On-chip memory in the MC9S08AW60 Series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers ($0000 through $006F) • High-page registers ($1800 through $185F) • Nonvolatile registers ($FFB0 through $FFBF) MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 39 Chapter 4 Memory $0000 $006F $0070 DIRECT PAGE REGISTERS $0000 DIRECT PAGE REGISTERS $006F $0070 RAM RAM 2048 BYTES $086F $0870 $17FF $1800 2048 BYTES $086F $0870 FLASH RESERVED 3984 BYTES 3984 BYTES $17FF $1800 HIGH PAGE REGISTERS $185F $1860 HIGH PAGE REGISTERS $185F $1860 RESERVED 10,144 BYTES $3FFF $4000 FLASH 59,296 BYTES FLASH 49,152 BYTES $FFFF $FFFF MC9S08AW60 MC9S08AW48 Figure 4-1. MC9S08AW60 and MC9S08AW48 Memory Map MC9S08AW60 Data Sheet, Rev 2 40 Freescale Semiconductor Chapter 4 Memory $0000 $006F $0070 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS $006F $0070 RAM RAM 1024 BYTES $046F $0470 2048 BYTES $086F $0870 $0000 RESERVED RESERVED 5008 BYTES 3984 BYTES $17FF $1800 $17FF $1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS $185F $1860 $185F $1860 RESERVED RESERVED 26,528 BYTES 42,912 BYTES $7FFF $8000 $BFFF $C000 FLASH FLASH 32,768 BYTES 16,384 BYTES $FFFF $FFFF MC9S08AW32 MC9S08AW16 Figure 4-2. MC9S08AW32 and MC9S08AW16 Memory Map MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 41 Chapter 4 Memory 4.1.1 Reset and Interrupt Vector Assignments Figure 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08AW60 Series. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1. Reset and Interrupt Vectors Address (High/Low) $FFC0:FFC1 Vector Vector Name Unused Vector Space (available for user program) $FFCA:FFCB $FFCC:FFCD RTI Vrti $FFCE:FFCF IIC1 Viic1 $FFD0:FFD1 ADC1 Conversion Vadc1 $FFD2:FFD3 KBI1 Vkeyboard1 $FFD4:FFD5 SCI2 Transmit Vsci2tx $FFD6:FFD7 SCI2 Receive Vsci2rx $FFD8:FFD9 SCI2 Error Vsci2err $FFDA:FFDB SCI1 Transmit Vsci1tx $FFDC:FFDD SCI1 Receive Vsci1rx $FFDE:FFDF SCI1 Error Vsci1err $FFE0:FFE1 SPI1 Vspi1 $FFE2:FFE3 TPM2 Overflow Vtpm2ovf $FFE4:FFE5 TPM2 Channel 1 Vtpm2ch1 $FFE6:FFE7 TPM2 Channel 0 Vtpm2ch0 $FFE8:FFE9 TPM1 Overflow Vtpm1ovf $FFEA:FFEB TPM1 Channel 5 Vtpm1ch5 $FFEC:FFED TPM1 Channel 4 Vtpm1ch4 $FFEE:FFEF TPM1 Channel 3 Vtpm1ch3 $FFF0:FFF1 TPM1 Channel 2 Vtpm1ch2 $FFF2:FFF3 TPM1 Channel 1 Vtpm1ch1 $FFF4:FFF5 TPM1 Channel 0 Vtpm1ch0 $FFF6:FFF7 ICG Vicg $FFF8:FFF9 Low Voltage Detect Vlvd $FFFA:FFFB IRQ Virq $FFFC:FFFD SWI Vswi $FFFE:FFFF Reset Vreset MC9S08AW60 Data Sheet, Rev 2 42 Freescale Semiconductor Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08AW60 Series are divided into these three groups: • Direct-page registers are located in the first 112 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above $1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables. • The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0–$FFBF. Nonvolatile register locations include: — Three values which are loaded into working registers at reset — An 8-byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH memory locations. Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits. The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only requires the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s. MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 43 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 1 of 3) Address Register Name $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B PTAD PTADD PTBD PTBDD PTCD PTCDD PTDD PTDDD PTED PTEDD PTFD PTFDD $000C $000D $000E– $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A– $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 PTGD PTGDD Reserved ADC1SC1 ADC1SC2 ADC1RH ADC1RL ADC1CVH ADC1CVL ADC1CFG APCTL1 APCTL2 APCTL3 Reserved IRQSC Reserved KBI1SC KBI1PE TPM1SC TPM1CNTH TPM1CNTL TPM1MODH TPM1MODL TPM1C0SC TPM1C0VH TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0 PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0 0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0 PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0 PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0 PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0 PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0 0 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0 — — — — — — — — — — — — — — — — COCO AIEN ADCO ADACT ADTRG ACFE ACFGT 0 0 R R 0 0 0 0 0 0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 ADCV9 ADCV8 ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 ADLPC ADIV ADCH ADLSMP MODE ADICLK ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16 — — — — — — — — — — — — — — — — 0 0 IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD — — — — — — — — KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBF KBACK KBIE KBIMOD KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 MC9S08AW60 Data Sheet, Rev 2 44 Freescale Semiconductor Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 2 of 3) Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 TPM1C1SC TPM1C1VH TPM1C1VL TPM1C2SC TPM1C2VH TPM1C2VL TPM1C3SC TPM1C3VH TPM1C3VL TPM1C4SC TPM1C4VH TPM1C4VL CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F TPM1C5SC TPM1C5VH TPM1C5VL Reserved SCI1BDH SCI1BDL SCI1C1 SCI1C2 SCI1S1 SCI1S2 SCI1C3 SCI1D SCI2BDH SCI2BDL SCI2C1 SCI2C2 SCI2S1 SCI2S2 SCI2C3 SCI2D ICGC1 ICGC2 ICGS1 ICGS2 ICGFLTU ICGFLTL ICGTRM Reserved Bit 7 6 5 4 3 2 1 Bit 0 CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CH3F CH3IE MS3B MS3A ELS3B ELS3A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CH4F CH4IE MS4B MS4A ELS4B ELS4A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CH5F CH5IE MS5B MS5A ELS5B ELS5A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 — — — — — — — — 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 LOOPS SCISWAI RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 0 0 0 BRK13 0 RAF R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 LOOPS SCISWAI RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 0 0 0 BRK13 0 RAF R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE Bit 7 6 5 4 3 2 1 Bit 0 HGO RANGE REFS OSCSTEN LOCD 0 LOLRE CLKS MFD CLKST LOCRE RFD REFST LOLS LOCK LOCS ERCS ICGIF 0 0 0 0 0 0 0 DCOS 0 0 0 0 — — FLT FLT TRIM — — — — — — MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 45 Chapter 4 Memory Table 4-2. Direct-Page Register Summary (Sheet 3 of 3) Address Register Name $0050 $0051 $0052 $0053 $0054 $0055 $0056– $0057 $0058 $0059 $005A $005B SPI1C1 SPI1C2 SPI1BR SPI1S Reserved SPI1D $005C $005D– $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A $006B– $006F IIC1D Reserved IIC1A IIC1F IIC1C IIC1S Reserved TPM2SC TPM2CNTH TPM2CNTL TPM2MODH TPM2MODL TPM2C0SC TPM2C0VH TPM2C0VL TPM2C1SC TPM2C1VH TPM2C1VL Reserved Bit 7 6 5 4 3 2 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 SPRF 0 SPTEF MODF 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 — — — — — — — — — — — — — — — — ADDR 0 MULT ICR IICEN IICIE MST TX TCF IAAS BUSY ARBL TXAK RSTA 0 0 0 SRW IICIF RXAK DATA — — — — — — — — — — — — — — — — TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 — — — — — — — — — — — — — — — — MC9S08AW60 Data Sheet, Rev 2 46 Freescale Semiconductor Chapter 4 Memory High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at $1800. Table 4-3. High-Page Register Summary (Sheet 1 of 2) Address $1800 $1801 $1802 $1803 $1804 – $1805 $1806 $1807 $1808 $1809 $180A $180B– $180F $1810 $1811 $1812 $1813 $1814 $1815 $1816 $1817 $1818 $1819– $181F $1820 $1821 $1822 $1823 $1824 $1825 $1826 $1827– $183F $1840 $1841 $1842 $1843 $1844 $1845 Register Name SRS SBDFR SOPT SMCLK Reserved SDIDH SDIDL SRTISC SPMSC1 SPMSC2 Reserved DBGCAH DBGCAL DBGCBH DBGCBL DBGFH DBGFL DBGC DBGT DBGS Reserved FCDIV FOPT Reserved FCNFG FPROT FSTAT FCMD Reserved PTAPE PTASE PTADS Reserved PTBPE PTBSE Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP 0 ICG LVD 0 0 0 0 0 0 0 0 BDFR COPE COPT STOPE — 0 0 — — 0 0 0 MPE 0 — — — — — — — — — — — — — — — — REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 MCSEL RTIF RTIACK RTICLKS RTIE 0 RTIS2 RTIS1 RTIS0 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 01 BGBE LVWF LVWACK LVDV LVWV PPDF PPDACK — PPDC — — — — — — — — — — — — — — — — Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN TRGSEL BEGIN 0 0 TRG3 TRG2 TRG1 TRG0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 — — — — — — — — — — — — — — — — DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 KEYEN FNORED 0 0 0 0 SEC01 SEC00 — — — — — — — — 0 0 KEYACC 0 0 0 0 0 FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0 FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 — — — — — — — — — — — — — — — — PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0 — — — — — — — — PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 MC9S08AW60 Data Sheet, Rev 2 Freescale Semiconductor 47 Chapter 4 Memory Table 4-3. High-Page Register Summary (Sheet 2 of 2) Address $1846 $1847 $1848 $1849 $184A $184B $184C $184D $184E $184F $1850 $1851 $1852 $1853 $1854 $1855 $1856 $1857 $1858 $1859 $185A $185B– $185F 1 Register Name PTBDS Reserved PTCPE PTCSE PTCDS Reserved PTDPE PTDSE PTDDS Reserved PTEPE PTESE PTEDS Reserved PTFPE PTFSE PTFDS Reserved PTGPE PTGSE PTGDS Reserved Bit 7 6 5 4 3 2 1 Bit 0 PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 — — — — — — — — 0 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0 0 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 — — — — — — — — PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0 PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 — — — — — — — — PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0 PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0 — — — — — — — — PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0 PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0 PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0 — — — — — — — — 0 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0 0 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0 — — — — — — — — — — — — — — — — This reserved bit must always be written to 0. Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. MC9S08AW60 Data Sheet, Rev 2 48 Freescale Semiconductor Chapter 4 Memory Table 4-4. Nonvolatile Register Summary Address $FFB0 – $FFB7 $FFB8 – $FFBB $FFBC $FFBD $FFBE $FFBF Register Name Bit 7 6 5 NVBACKKEY Reserved Reserved for storage of 250 kHz ICGTRM value NVPROT Reserved for storage of 243 kHz ICGTRM value NVOPT 4 3 2 1 Bit 0 8-Byte Comparison Key — — — — — — — — — — — — — — — — FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS — — — — — — — — KEYEN FNORED 0 0 0 0 SEC01 SEC00 Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. This key mechanism can be accessed only through user code running in secure memory. (A security key cannot be entered directly through background debug commands.) This security key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08AW60 Series includes static RAM. The locations in RAM below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to $00FF. In the MC9S08AW60 Series, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale-provided equate file). LDHX TXS #RamLast+1 ;point one past RAM ;SP
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