MC9S08EL32CTL

MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 Data Sheet HCS08 Microcontrollers MC9S08EL32 Rev. 3 7/2008 freescale.com MC9S08EL32 Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating voltage and temperature • EEPROM in-circuit programmable memory; program and erase while executing FLASH; erase abort • Random-access memory (RAM) • Security circuitry to prevent unauthorized access to RAM and NVM contents Power-Saving Modes • Two very low-power stop modes • Reduced power wait mode • Very low-power real-time interrupt for use in run, wait, and stop Clock Source Options • Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz • Internal clock source (ICS) — Contains a frequency-locked loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 2–20 MHz System Protection • Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock • Low-voltage detection with reset or interrupt; selectable trip points • Illegal opcode detection with reset • Illegal address detection with reset • FLASH and EEPROM block protect Development Support • Single-wire background debug interface • Breakpoint capability allows single breakpoint setting during in-circuit debugging (plus two more breakpoints in the on-chip debug module) • In-circuit emulation (ICE) debug module — contains two comparators and nine trigger modes; eight-deep FIFO for storing change-of-flow address and event-only data; supports both tag and force breakpoints Peripherals • ADC — 16-channel, 10-bit resolution, 2.5 μs conversion time, automatic compare function, temperature sensor, internal bandgap reference channel; runs in stop3 • ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; output can optionally be routed to TPM module; runs in stop3 • SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake-up on active edge • SLIC — Supports LIN 2.0 and SAE J2602 protocols; up to 120 kbps, full LIN message buffering, automatic bit rate and frame synchronization, checksum generation and verification, UART-like byte transfer mode • SPI — Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting • IIC — Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer • TPMx — One 4-channel (TPM1) and one 2-channel (TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel • RTC — 8-bit modulus real-time counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar, or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components Input/Output • 22 general purpose I/O pins • 16 interrupt pins with selectable polarity • Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive strength on all output pins. Package Options • 28-TSSOP • 20-TSSOP MC9S08EL32 Data Sheet Covers MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 MC9S08EL32 Rev. 3 7/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number Revision Date 3 07/2008 Description of Changes Initial public revision © Freescale Semiconductor, Inc., 2008. All rights reserved. This product incorporates SuperFlash® Technology licensed from SST. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 6 Freescale Semiconductor List of Chapters Chapter 1 Device Overview ...................................................................... 19 Chapter 2 Pins and Connections ............................................................. 25 Chapter 3 Modes of Operation ................................................................. 31 Chapter 4 Memory ..................................................................................... 37 Chapter 5 Resets, Interrupts, and General System Control.................. 63 Chapter 6 Parallel Input/Output Control.................................................. 79 Chapter 7 Central Processor Unit (S08CPUV3) ...................................... 95 Chapter 8 Internal Clock Source (S08ICSV2)........................................ 115 Chapter 9 5-V Analog Comparator (S08ACMPV2)................................ 129 Chapter 10 Analog-to-Digital Converter (S08ADCV1)............................ 137 Chapter 11 Inter-Integrated Circuit (S08IICV2) ....................................... 165 Chapter 12 Slave LIN Interface Controller (S08SLICV1) ........................ 185 Chapter 13 Serial Peripheral Interface (S08SPIV3) ................................ 233 Chapter 14 Serial Communications Interface (S08SCIV4)..................... 249 Chapter 15 Real-Time Counter (S08RTCV1) ........................................... 269 Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) ......................... 279 Chapter 17 Development Support ........................................................... 307 Appendix A Electrical Characteristics...................................................... 331 Appendix B Ordering Information and Mechanical Drawings................ 355 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 7 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 8 Freescale Semiconductor Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 Devices in the MC9S08EL32 Series and MC9S08SL16 Series .....................................................19 MCU Block Diagram ......................................................................................................................20 System Clock Distribution ..............................................................................................................23 Chapter 2 Pins and Connections 2.1 2.2 Device Pin Assignment ...................................................................................................................25 Recommended System Connections ...............................................................................................26 2.2.1 Power ................................................................................................................................26 2.2.2 Oscillator ...........................................................................................................................27 2.2.3 RESET ..............................................................................................................................27 2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................28 2.2.5 General-Purpose I/O and Peripheral Ports ........................................................................28 Chapter 3 Modes of Operation 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Introduction .....................................................................................................................................31 Features ...........................................................................................................................................31 Run Mode ........................................................................................................................................31 Active Background Mode ...............................................................................................................31 Wait Mode .......................................................................................................................................32 Stop Modes ......................................................................................................................................32 3.6.1 Stop3 Mode .......................................................................................................................33 Stop2 Mode .....................................................................................................................................34 On-Chip Peripheral Modules in Stop Modes ..................................................................................34 Chapter 4 Memory 4.1 4.2 4.3 4.4 4.5 MC9S08EL32 Series and MC9S08SL16 Series Memory Map ......................................................37 Reset and Interrupt Vector Assignments .........................................................................................38 Register Addresses and Bit Assignments ........................................................................................39 RAM ................................................................................................................................................46 FLASH and EEPROM ....................................................................................................................47 4.5.1 Features .............................................................................................................................47 4.5.2 Program and Erase Times .................................................................................................47 4.5.3 Program and Erase Command Execution .........................................................................48 4.5.4 Burst Program Execution ..................................................................................................49 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 9 Section Number 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11 Title Page Sector Erase Abort ............................................................................................................51 Access Errors ....................................................................................................................52 Block Protection ...............................................................................................................53 Vector Redirection ............................................................................................................53 Security .............................................................................................................................53 EEPROM Mapping ...........................................................................................................55 FLASH and EEPROM Registers and Control Bits ..........................................................55 Chapter 5 Resets, Interrupts, and General System Control 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Introduction .....................................................................................................................................63 Features ...........................................................................................................................................63 MCU Reset ......................................................................................................................................63 Computer Operating Properly (COP) Watchdog .............................................................................64 Interrupts .........................................................................................................................................65 5.5.1 Interrupt Stack Frame .......................................................................................................66 5.5.2 Interrupt Vectors, Sources, and Local Masks ...................................................................67 Low-Voltage Detect (LVD) System ................................................................................................68 5.6.1 Power-On Reset Operation ...............................................................................................69 5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................69 5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................69 Reset, Interrupt, and System Control Registers and Control Bits ...................................................70 5.7.1 System Reset Status Register (SRS) .................................................................................71 5.7.2 System Background Debug Force Reset Register (SBDFR) ............................................72 5.7.3 System Options Register 1 (SOPT1) ................................................................................73 5.7.4 System Options Register 2 (SOPT2) ................................................................................74 5.7.5 System Device Identification Register (SDIDH, SDIDL) ................................................75 5.7.6 System Power Management Status and Control 1 Register (SPMSC1) ...........................76 5.7.7 System Power Management Status and Control 2 Register (SPMSC2) ...........................77 Chapter 6 Parallel Input/Output Control 6.1 6.2 6.3 6.4 6.5 Port Data and Data Direction ..........................................................................................................79 Pull-up, Slew Rate, and Drive Strength ..........................................................................................80 Pin Interrupts ...................................................................................................................................81 6.3.1 Edge Only Sensitivity .......................................................................................................81 6.3.2 Edge and Level Sensitivity ...............................................................................................81 6.3.3 Pull-up/Pull-down Resistors .............................................................................................82 6.3.4 Pin Interrupt Initialization .................................................................................................82 Pin Behavior in Stop Modes ............................................................................................................82 Parallel I/O and Pin Control Registers ............................................................................................82 6.5.1 Port A Registers ................................................................................................................83 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 10 Freescale Semiconductor Section Number Title Page 6.5.2 Port B Registers ................................................................................................................87 6.5.3 Port C Registers ................................................................................................................91 Chapter 7 Central Processor Unit (S08CPUV3) 7.1 7.2 7.3 7.4 7.5 Introduction .....................................................................................................................................95 7.1.1 Features .............................................................................................................................95 Programmer’s Model and CPU Registers .......................................................................................96 7.2.1 Accumulator (A) ...............................................................................................................96 7.2.2 Index Register (H:X) ........................................................................................................96 7.2.3 Stack Pointer (SP) .............................................................................................................97 7.2.4 Program Counter (PC) ......................................................................................................97 7.2.5 Condition Code Register (CCR) .......................................................................................97 Addressing Modes ...........................................................................................................................99 7.3.1 Inherent Addressing Mode (INH) .....................................................................................99 7.3.2 Relative Addressing Mode (REL) ....................................................................................99 7.3.3 Immediate Addressing Mode (IMM) ................................................................................99 7.3.4 Direct Addressing Mode (DIR) ........................................................................................99 7.3.5 Extended Addressing Mode (EXT) ................................................................................100 7.3.6 Indexed Addressing Mode ..............................................................................................100 Special Operations .........................................................................................................................101 7.4.1 Reset Sequence ...............................................................................................................101 7.4.2 Interrupt Sequence ..........................................................................................................101 7.4.3 Wait Mode Operation ......................................................................................................102 7.4.4 Stop Mode Operation ......................................................................................................102 7.4.5 BGND Instruction ...........................................................................................................103 HCS08 Instruction Set Summary ..................................................................................................103 Chapter 8 Internal Clock Source (S08ICSV2) 8.1 8.2 8.3 8.4 Introduction ...................................................................................................................................115 8.1.1 Module Configuration .....................................................................................................115 8.1.2 Features ...........................................................................................................................117 8.1.3 Block Diagram ................................................................................................................117 8.1.4 Modes of Operation ........................................................................................................118 External Signal Description ..........................................................................................................119 Register Definition ........................................................................................................................119 8.3.1 ICS Control Register 1 (ICSC1) .....................................................................................120 8.3.2 ICS Control Register 2 (ICSC2) .....................................................................................121 8.3.3 ICS Trim Register (ICSTRM) .........................................................................................122 8.3.4 ICS Status and Control (ICSSC) .....................................................................................122 Functional Description ..................................................................................................................123 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 11 Section Number 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 Title Page Operational Modes ..........................................................................................................123 Mode Switching ..............................................................................................................125 Bus Frequency Divider ...................................................................................................126 Low Power Bit Usage .....................................................................................................126 Internal Reference Clock ................................................................................................126 Optional External Reference Clock ................................................................................126 Fixed Frequency Clock ...................................................................................................127 Chapter 9 5-V Analog Comparator (S08ACMPV2) 9.1 9.2 9.3 9.4 Introduction ...................................................................................................................................129 9.1.1 ACMPx Configuration Information ................................................................................129 9.1.2 ACMP1/TPM1 Configuration Information ....................................................................129 9.1.3 Features ...........................................................................................................................131 9.1.4 Modes of Operation ........................................................................................................131 9.1.5 Block Diagram ................................................................................................................132 External Signal Description ..........................................................................................................133 Memory Map ................................................................................................................................133 9.3.1 Register Descriptions ......................................................................................................133 Functional Description ..................................................................................................................135 Chapter 10 Analog-to-Digital Converter (S08ADCV1) 10.1 Introduction ...................................................................................................................................137 10.1.1 Channel Assignments .....................................................................................................137 10.1.2 Alternate Clock ...............................................................................................................138 10.1.3 Hardware Trigger ............................................................................................................138 10.1.4 Temperature Sensor ........................................................................................................138 10.1.5 Features ...........................................................................................................................141 10.1.6 Block Diagram ................................................................................................................141 10.2 External Signal Description ..........................................................................................................142 10.2.1 Analog Power (VDDAD) ..................................................................................................143 10.2.2 Analog Ground (VSSAD) .................................................................................................143 10.2.3 Voltage Reference High (VREFH) ...................................................................................143 10.2.4 Voltage Reference Low (VREFL) ....................................................................................143 10.2.5 Analog Channel Inputs (ADx) ........................................................................................143 10.3 Register Definition ........................................................................................................................143 10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................143 10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................145 10.3.3 Data Result High Register (ADCRH) .............................................................................146 10.3.4 Data Result Low Register (ADCRL) ..............................................................................146 10.3.5 Compare Value High Register (ADCCVH) ....................................................................147 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 12 Freescale Semiconductor Section Number Title Page 10.3.6 Compare Value Low Register (ADCCVL) .....................................................................147 10.3.7 Configuration Register (ADCCFG) ................................................................................147 10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................149 10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................150 10.3.10Pin Control 3 Register (APCTL3) ..................................................................................151 10.4 Functional Description ..................................................................................................................152 10.4.1 Clock Select and Divide Control ....................................................................................152 10.4.2 Input Select and Pin Control ...........................................................................................153 10.4.3 Hardware Trigger ............................................................................................................153 10.4.4 Conversion Control .........................................................................................................153 10.4.5 Automatic Compare Function .........................................................................................156 10.4.6 MCU Wait Mode Operation ............................................................................................156 10.4.7 MCU Stop3 Mode Operation ..........................................................................................156 10.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................157 10.5 Initialization Information ..............................................................................................................157 10.5.1 ADC Module Initialization Example .............................................................................157 10.6 Application Information ................................................................................................................159 10.6.1 External Pins and Routing ..............................................................................................159 10.6.2 Sources of Error ..............................................................................................................161 Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction ...................................................................................................................................165 11.1.1 Module Configuration .....................................................................................................165 11.1.2 Features ...........................................................................................................................167 11.1.3 Modes of Operation ........................................................................................................167 11.1.4 Block Diagram ................................................................................................................168 11.2 External Signal Description ..........................................................................................................168 11.2.1 SCL — Serial Clock Line ...............................................................................................168 11.2.2 SDA — Serial Data Line ................................................................................................168 11.3 Register Definition ........................................................................................................................168 11.3.1 IIC Address Register (IICA) ...........................................................................................169 11.3.2 IIC Frequency Divider Register (IICF) ..........................................................................169 11.3.3 IIC Control Register (IICC1) ..........................................................................................172 11.3.4 IIC Status Register (IICS) ...............................................................................................172 11.3.5 IIC Data I/O Register (IICD) ..........................................................................................173 11.3.6 IIC Control Register 2 (IICC2) .......................................................................................174 11.4 Functional Description ..................................................................................................................175 11.4.1 IIC Protocol .....................................................................................................................175 11.4.2 10-bit Address .................................................................................................................178 11.4.3 General Call Address ......................................................................................................179 11.5 Resets ............................................................................................................................................179 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 13 Section Number Title Page 11.6 Interrupts .......................................................................................................................................179 11.6.1 Byte Transfer Interrupt ....................................................................................................179 11.6.2 Address Detect Interrupt .................................................................................................180 11.6.3 Arbitration Lost Interrupt ................................................................................................180 11.7 Initialization/Application Information ..........................................................................................181 Chapter 12 Slave LIN Interface Controller (S08SLICV1) 12.1 Introduction ...................................................................................................................................185 12.1.1 Features ...........................................................................................................................187 12.1.2 Modes of Operation ........................................................................................................188 12.1.3 Block Diagram ................................................................................................................191 12.2 External Signal Description ..........................................................................................................191 12.2.1 SLCTx — SLIC Transmit Pin ........................................................................................191 12.2.2 SLCRx — SLIC Receive Pin ..........................................................................................191 12.3 Register Definition ........................................................................................................................191 12.3.1 SLIC Control Register 1 (SLCC1) ..................................................................................191 12.3.2 SLIC Control Register 2 (SLCC2) ..................................................................................193 12.3.3 SLIC Bit Time Registers (SLCBTH, SLCBTL) .............................................................195 12.3.4 SLIC Status Register (SLCS) ..........................................................................................196 12.3.5 SLIC State Vector Register (SLCSV) .............................................................................197 12.3.6 SLIC Data Length Code Register (SLCDLC) ................................................................202 12.3.7 SLIC Identifier and Data Registers (SLCID, SLCD7-SLCD0) ......................................203 12.4 Functional Description ..................................................................................................................204 12.5 Interrupts .......................................................................................................................................204 12.5.1 SLIC During Break Interrupts ........................................................................................204 12.6 Initialization/Application Information ..........................................................................................204 12.6.1 LIN Message Frame Header ...........................................................................................205 12.6.2 LIN Data Field ................................................................................................................205 12.6.3 LIN Checksum Field .......................................................................................................206 12.6.4 SLIC Module Constraints ...............................................................................................206 12.6.5 SLCSV Interrupt Handling .............................................................................................206 12.6.6 SLIC Module Initialization Procedure ............................................................................206 12.6.7 Handling LIN Message Headers .....................................................................................208 12.6.8 Handling Command Message Frames ............................................................................211 12.6.9 Handling Request LIN Message Frames ........................................................................214 12.6.10Handling IMSG to Minimize Interrupts .........................................................................218 12.6.11Sleep and Wakeup Operation ..........................................................................................219 12.6.12Polling Operation ............................................................................................................219 12.6.13LIN Data Integrity Checking Methods ...........................................................................219 12.6.14High-Speed LIN Operation .............................................................................................220 12.6.15Bit Error Detection and Physical Layer Delay ...............................................................223 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 14 Freescale Semiconductor Section Number Title Page 12.6.16Byte Transfer Mode Operation .......................................................................................224 12.6.17Oscillator Trimming with SLIC ......................................................................................228 12.6.18Digital Receive Filter ......................................................................................................230 Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction ...................................................................................................................................233 13.1.1 Features ...........................................................................................................................235 13.1.2 Block Diagrams ..............................................................................................................235 13.1.3 SPI Baud Rate Generation ..............................................................................................237 13.2 External Signal Description ..........................................................................................................238 13.2.1 SPSCK — SPI Serial Clock ............................................................................................238 13.2.2 MOSI — Master Data Out, Slave Data In ......................................................................238 13.2.3 MISO — Master Data In, Slave Data Out ......................................................................238 13.2.4 SS — Slave Select ..........................................................................................................238 13.3 Modes of Operation .......................................................................................................................239 13.3.1 SPI in Stop Modes ..........................................................................................................239 13.4 Register Definition ........................................................................................................................239 13.4.1 SPI Control Register 1 (SPIC1) ......................................................................................239 13.4.2 SPI Control Register 2 (SPIC2) ......................................................................................240 13.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................241 13.4.4 SPI Status Register (SPIS) ..............................................................................................242 13.4.5 SPI Data Register (SPID) ...............................................................................................243 13.5 Functional Description ..................................................................................................................244 13.5.1 SPI Clock Formats ..........................................................................................................244 13.5.2 SPI Interrupts ..................................................................................................................247 13.5.3 Mode Fault Detection .....................................................................................................247 Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction ...................................................................................................................................249 14.1.1 Features ...........................................................................................................................251 14.1.2 Modes of Operation ........................................................................................................251 14.1.3 Block Diagram ................................................................................................................252 14.2 Register Definition ........................................................................................................................254 14.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................254 14.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................255 14.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................256 14.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................257 14.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................259 14.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................260 14.2.7 SCI Data Register (SCIxD) .............................................................................................261 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 15 Section Number Title Page 14.3 Functional Description ..................................................................................................................261 14.3.1 Baud Rate Generation .....................................................................................................261 14.3.2 Transmitter Functional Description ................................................................................262 14.3.3 Receiver Functional Description ....................................................................................263 14.3.4 Interrupts and Status Flags ..............................................................................................265 14.3.5 Additional SCI Functions ...............................................................................................266 Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction ...................................................................................................................................269 15.1.1 Features ...........................................................................................................................272 15.1.2 Modes of Operation ........................................................................................................272 15.1.3 Block Diagram ................................................................................................................273 15.2 External Signal Description ..........................................................................................................273 15.3 Register Definition ........................................................................................................................273 15.3.1 RTC Status and Control Register (RTCSC) ....................................................................274 15.3.2 RTC Counter Register (RTCCNT) ..................................................................................275 15.3.3 RTC Modulo Register (RTCMOD) ................................................................................275 15.4 Functional Description ..................................................................................................................275 15.4.1 RTC Operation Example .................................................................................................276 15.5 Initialization/Application Information ..........................................................................................277 Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) 16.1 Introduction ...................................................................................................................................279 16.1.1 Features ...........................................................................................................................281 16.1.2 Modes of Operation ........................................................................................................281 16.1.3 Block Diagram ................................................................................................................282 16.2 Signal Description .........................................................................................................................284 16.2.1 Detailed Signal Descriptions ..........................................................................................284 16.3 Register Definition ........................................................................................................................288 16.3.1 TPM Status and Control Register (TPMxSC) ................................................................288 16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................289 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................290 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................291 16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................293 16.4 Functional Description ..................................................................................................................294 16.4.1 Counter ............................................................................................................................295 16.4.2 Channel Mode Selection .................................................................................................297 16.5 Reset Overview .............................................................................................................................300 16.5.1 General ............................................................................................................................300 16.5.2 Description of Reset Operation .......................................................................................300 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 16 Freescale Semiconductor Section Number Title Page 16.6 Interrupts .......................................................................................................................................300 16.6.1 General ............................................................................................................................300 16.6.2 Description of Interrupt Operation .................................................................................301 16.7 The Differences from TPM v2 to TPM v3 ....................................................................................302 Chapter 17 Development Support 17.1 Introduction ...................................................................................................................................307 17.1.1 Forcing Active Background ............................................................................................307 17.1.2 Features ...........................................................................................................................310 17.2 Background Debug Controller (BDC) ..........................................................................................310 17.2.1 BKGD Pin Description ...................................................................................................311 17.2.2 Communication Details ..................................................................................................312 17.2.3 BDC Commands .............................................................................................................316 17.2.4 BDC Hardware Breakpoint .............................................................................................318 17.3 On-Chip Debug System (DBG) ....................................................................................................319 17.3.1 Comparators A and B .....................................................................................................319 17.3.2 Bus Capture Information and FIFO Operation ...............................................................319 17.3.3 Change-of-Flow Information ..........................................................................................320 17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................320 17.3.5 Trigger Modes .................................................................................................................321 17.3.6 Hardware Breakpoints ....................................................................................................323 17.4 Register Definition ........................................................................................................................323 17.4.1 BDC Registers and Control Bits .....................................................................................323 17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................325 17.4.3 DBG Registers and Control Bits .....................................................................................326 Appendix A Electrical Characteristics A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 Introduction ...................................................................................................................................331 Parameter Classification ................................................................................................................331 Absolute Maximum Ratings ..........................................................................................................331 Thermal Characteristics .................................................................................................................332 ESD Protection and Latch-Up Immunity ......................................................................................333 DC Characteristics .........................................................................................................................334 Supply Current Characteristics ......................................................................................................338 External Oscillator (XOSC) Characteristics .................................................................................341 Internal Clock Source (ICS) Characteristics .................................................................................342 Analog Comparator (ACMP) Electricals ......................................................................................343 ADC Characteristics ......................................................................................................................344 AC Characteristics .........................................................................................................................347 A.12.1 Control Timing ...............................................................................................................347 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 17 Section Number Title Page A.12.2 TPM/MTIM Module Timing ..........................................................................................348 A.12.3 SPI ...................................................................................................................................349 A.13 Flash and EEPROM Specifications ...............................................................................................352 A.14 EMC Performance .........................................................................................................................353 A.14.1 Radiated Emissions .........................................................................................................353 A.14.2 Conducted Transient Susceptibility ................................................................................354 Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................355 B.1.1 Device Numbering Scheme ............................................................................................355 B.2 Mechanical Drawings ....................................................................................................................356 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 18 Freescale Semiconductor Chapter 1 Device Overview The MC9S08EL32 Series and MC9S08SL16 Series are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 Devices in the MC9S08EL32 Series and MC9S08SL16 Series Table 1-1 summarizes the feature set available in the MC9S08EL32 Series and MC9S08SL16 Series of MCUs. t Table 1-1. MC9S08EL32 Series and MC9S08SL16 Series Features by MCU and Package Feature 9S08EL32 9S08EL16 9S08SL16 9S08SL8 32768 16384 16384 8192 FLASH size (bytes) RAM size (bytes) 1024 EEPROM size (bytes) Pin quantity 512 512 256 28 20 28 20 28 20 28 20 Package type TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Port Interrupts 16 12 16 12 16 12 16 12 ACMP2 yes no yes no ADC channels 16 12 16 12 16 12 ACMP1 yes yes no 16 12 DBG yes yes ICS yes yes IIC yes yes RTC yes yes SCI yes yes SLIC yes yes SPI yes yes TPM1 channels 4 2 TPM2 channels 2 2 yes yes XOSC MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 19 Chapter 1 Device Overview 1.2 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08EL32 Series. Not all features are available on all devices in all packages. See Table 1-1 for details. HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP INT SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B SERIAL COMMUNICATIONS INTERFACE (SCI) PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PORT C LVD PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 IIC MODULE (IIC) USER EEPROM 512 bytes REAL-TIME COUNTER (RTC) USER RAM 1024 bytes OSCILLATOR (XOSC) XTAL EXTAL INTERNAL CLOCK SOURCE (ICS) VDD VSS VOLTAGE REGULATOR VDDA/ VREFH VSSA/ VREFL ON-CHIP IN-CIRCUIT EMULATOR (ICE) DEBUG MODULE (DBG) TCLK 0 4-CHANNEL TIMER/PWM 1 MODULE (TPM1) 2 3 OUT ANALOG COMPARATOR + (ACMP2) – 16-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16 = Not bonded to pins in 20-pin package = In 20-pin packages, VDDA/VREFH is internally connected to VDD and VSSA/VREFL is internally connected to VSS. Figure 1-1. MC9S08EL32 and MC9S08EL16 Block Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 20 Freescale Semiconductor Chapter 1 Device Overview The block diagram in Figure 1-2 shows the structure of the MC9S08SL16 Series. HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP INT SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 16K / 8K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B SERIAL COMMUNICATIONS INTERFACE (SCI) PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PORT C LVD PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/ADP10 PTC3/PIC3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ADP13 PTC6/PIC6/ADP14 PTC7/PIC7/ADP15 IIC MODULE (IIC) USER EEPROM 256 bytes REAL-TIME COUNTER (RTC) USER RAM 512 bytes OSCILLATOR (XOSC) XTAL EXTAL INTERNAL CLOCK SOURCE (ICS) VDD VSS TCLK 0 2-CHANNEL TIMER/PWM 1 MODULE (TPM1) VOLTAGE REGULATOR VDDA/ VREFH VSSA/ VREFL ON-CHIP IN-CIRCUIT EMULATOR (ICE) DEBUG MODULE (DBG) 16-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16 = Not bonded to pins in 20-pin package = In 20-pin packages, VDDA/VREFH is internally connected to VDD and VSSA/VREFL is internally connected to VSS. Figure 1-2. MC9S08SL16 and MC9S08SL8 Block Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 21 Chapter 1 Device Overview Table 1-2 provides the functional version of the on-chip modules Table 1-2. Module Versions Module Version Central Processor Unit (CPU) 3 Internal Clock Source (ICS) 2 5-V Analog Comparator (ACMP_5V) 2 Analog-to-Digital Converter (ADC) 1 Inter-Integrated Circuit (IIC) 2 Slave LIN Interface Controller (SLIC) 1 Serial Peripheral Interface (SPI) 3 Serial Communications Interface (SCI) 4 Real-Time Counter (RTC) 1 Timer Pulse Width Modulator (TPM) 2 On-Chip ICE Debug (DBG) 2 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 22 Freescale Semiconductor Chapter 1 Device Overview 1.3 System Clock Distribution Figure 1-3 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following defines the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of ICSOUT. • ICSOUT — Primary output of the ICS and is twice the bus frequency. • ICSLCLK — Development tools can select this clock source to speed up BDC communications in systems where the bus clock is configured to run at a very slow frequency. • ICSERCLK — External reference clock can be selected as the RTC clock source and as the alternate clock for the ADC module. • ICSIRCLK — Internal reference clock can be selected as the RTC clock source. • ICSFFCLK — Fixed frequency clock can be selected as clock source for the TPM1 and TPM2 modules. • LPO — Independent 1-kHz clock that can be selected as the source for the COP and RTC modules. • TCLK — External input clock source for TPM1 and TPM2 and is referenced as TPMCLK in TPM chapters. TCLK 1 kHZ LPO RTC COP TPM1 TPM2 SCI SLIC SPI ICSERCLK ICSIRCLK ICS ICSFFCLK ÷2 ICSOUT ÷2 FFCLK* BUSCLK ICSLCLK XOSC CPU EXTAL BDC XTAL * The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. ADC IIC ADC has min and max frequency requirements. See the ADC chapter and electricals appendix for details. FLASH EEPROM FLASH and EEPROM have frequency requirements for program and erase operation. See the electricals appendix for details. Figure 1-3. System Clock Distribution Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 23 Chapter 1 Device Overview MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 24 Freescale Semiconductor Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment This section describes pin assignments for the MC9S08EL32 Series and MC9S08SL16 Series devices. Not all features are available in all devices. See Table 1-1 for details. PTC5/PIC5/ACMP2O/ADP13 PTC4/PIC4/ADP12 RESET BKGD/MS VDD VDDA/VREFH VSSA/VREFL VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/PIC3/TPM1CH3/ADP11 PTC2/PIC2/TPM1CH2/ADP10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin TSSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 Figure 2-1. 28-Pin TSSOP RESET BKGD/MS VDD/VDDA/VREFH VSS/VSSA/VREFL PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/PIC3/TPM1CH3/ADP11 PTC2/PIC2/TPM1CH2/ADP10 1 2 3 4 5 6 7 8 9 10 20-Pin TSSOP 20 19 18 17 16 15 14 13 12 11 PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 Figure 2-2. 20-Pin TSSOP MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 25 Chapter 2 Pins and Connections 2.2 Recommended System Connections Figure 2-3 shows pin connections that are common to MC9S08EL32 Series and MC9S08SL16 Series application systems. MC9S08EL32 Background Header PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 RPU VDD PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 BKGD/MS PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 VDD RPU 4.7 kΩ–10 kΩ PORT A PTA3/PIA3/SCL/TxD/ADP3 RESET 0.1 μF Optional Manual Reset PTA6/TPM2CH0 PTA7/TPM2CH1 PTC0/PIC0/TPM1CH0/ADP8 PTB0/PIB0/SLRxD/RxD/ADP4 PTC1/PIC1/TPM1CH1/ADP9 PTB1/PIB1/SLTxD/TxD/ADP5 PTC2/PIC2/TPM1CH2/ADP10 PTB2/PIB2/SDA/SPSCK/ADP6 PTC3/PIC3/TPM1CH3/ADP11 PORT C PTC4/PIC4/ADP12 PTB3/PIB3/SCL/MOSI/ADP7 PORT B PTB4/TPM2CH1/MISO2 PTC5/PIC5/ACMP2O/ADP13 PTB5/TPM1CH1/SS PTC6/PIC6/ACMP2+/ADP14 PTB6/SDA/XTAL PTC7/PIC7/ACMP2–/ADP15 PTB7/SCL/EXTAL VDD + System Power 5V CBLK + 10 μF CBY RF 0.1 μF RS VSS VDDA/VREFH C1 X1 C2 CBY 0.1 μF VSSA/VREFL Figure 2-3. Basic System Connections 2.2.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression. VDDA and VSSA are the analog power supply pins for the MCU. This voltage source supplies power to the ADC module. A 0.1-μF ceramic bypass capacitor should be located as near to the MCU power pins as practical to suppress high-frequency noise. The VREFH and VREFL pins are the voltage reference high and voltage reference low inputs, respectively, for the ADC module. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 26 Freescale Semiconductor Chapter 2 Pins and Connections 2.2.2 Oscillator Immediately after reset, the MCU uses an internally generated clock provided by the clock source generator (ICS) module. This internal clock source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. For more information on the ICS, see Chapter 8, “Internal Clock Source (S08ICSV2).” The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator. Rather than a crystal or ceramic resonator, an external oscillator can be connected to the EXTAL input pin. Refer to Figure 2-3 for the following discussion. RS (when used) and RF should be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically designed for high-frequency applications. RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup. C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL). 2.2.3 RESET RESET is a dedicated pin with a built in pull-up device. It has input hysteresis and an open drain output. Since the pin does not have a clamp diode to VDD, it should not be driven above VDD. Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the RESET pin is driven low for about 66 bus cycles. The reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (SRS). NOTE This pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on the internally-pulled-up RESET pin is not pulled to VDD. The internal gates connected to this pin are pulled to VDD. If the RESET pin is required to drive to a VDD level, use an external pullup. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 27 Chapter 2 Pins and Connections NOTE In EMC-sensitive applications, use an external RC filter on RESET. See Figure 2-3 for an example. 2.2.4 Background / Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin functions as the background pin and can be used for background debug communication. While functioning as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard output driver, and no output slew rate control. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD low during the rising edge of reset which forces the MCU to active background mode. The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall times on the BKGD/MS pin. 2.2.5 General-Purpose I/O and Peripheral Ports The MC9S08EL32 Series and MC9S08SL16 Series of MCUs support up to 22 general-purpose I/O pins which are shared with on-chip peripheral functions (timers, serial I/O, ADC, etc.). When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. When a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pull-up devices disabled. When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output Control.” NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not float. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 28 Freescale Semiconductor Chapter 2 Pins and Connections Table 2-1. Pin Availability by Package Pin-Count Pin Number 28 20 — PTC5 PIC5 — PTC4 PIC4 BKGD ACMP2O ADP13 VDD 3 VDDA VREFH VSSA VREFL 8 4 VSS 9 5 PTB7 SCL2 10 6 PTB6 SDA2 EXTAL XTAL 3 PTB5 TPM1CH1 SS 8 PTB4 TPM2CH14 MISO 13 9 PTC3 PIC3 TPM1CH3 ADP11 14 10 PTC2 PIC2 TPM1CH2 ADP10 PIC1 TPM1CH1 3 ADP9 TPM1CH0 5 ADP8 7 11 12 PTC1 PTC0 PIC0 2 17 13 PTB3 PIB3 SCL MOSI ADP7 18 14 PTB2 PIB2 SDA2 SPSCK ADP6 19 15 PTB1 PIB1 SLTxD TxD6 ADP5 SLRxD RxD6 ADP4 ADP3 20 16 PTB0 PIB0 4 21 — PTA7 TPM2CH1 22 — PTA6 TPM2CH07 23 17 PTA3 24 25 7 Alt5 ADP12 2 16 8 Alt4 1 4 15 5 --> Highest Alt3 RESET 12 6 Alt 2 1 11 4 Priority 3 7 3 Alt 1 2 6 2 Port Pin 1 5 1 fADCK xx 0 20 ADCK cycles Subsequent continuous 8-bit; fBUS > fADCK/11 xx 1 37 ADCK cycles Subsequent continuous 10-bit; fBUS > fADCK/11 xx 1 40 ADCK cycles The maximum total conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is: Conversion time = 23 ADCK cyc 8 MHz/1 + 5 bus cyc 8 MHz = 3.5 μs Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles NOTE The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 155 Analog-to-Digital Converter (S08ADC10V1) 10.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than the compare value, COCO is set. The value generated by the addition of the conversion result and the two’s complement of the compare value is transferred to ADCRH and ADCRL. Upon completion of a conversion while the compare function is enabled, if the compare condition is not true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon the setting of COCO if the ADC interrupt is enabled (AIEN = 1). NOTE The compare function can be used to monitor the voltage on a channel while the MCU is in either wait or stop3 mode. The ADC interrupt will wake the MCU when the compare condition is met. 10.4.6 MCU Wait Mode Operation The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled. The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this MCU. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait mode if the ADC interrupt is enabled (AIEN = 1). 10.4.7 MCU Stop3 Mode Operation The STOP instruction is used to put the MCU in a low power-consumption standby mode during which most or all clock sources on the MCU are disabled. 10.4.7.1 Stop3 Mode With ADACK Disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 156 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 10.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled (AIEN = 1). NOTE It is possible for the ADC module to wake the system from low power stop and cause the MCU to begin consuming run-level currents without generating a system level interrupt. To prevent this scenario, software should ensure that the data transfer blocking mechanism (discussed in Section 10.4.4.2, “Completing Conversions) is cleared when entering stop3 and continuing ADC conversions. 10.4.8 MCU Stop1 and Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module registers contain their reset values following exit from stop1 or stop2. Therefore the module must be re-enabled and re-configured following exit from stop1 or stop2. 10.5 Initialization Information This section gives an example which provides some basic direction on how a user would initialize and configure the ADC module. The user has the flexibility of choosing between configuring the module for 8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. Refer to Table 10-6, Table 10-7, and Table 10-8 for information used in this example. NOTE Hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 10.5.1 10.5.1.1 ADC Module Initialization Example Initialization Sequence Before the ADC module can be used to complete conversions, an initialization procedure must be performed. A typical sequence is as follows: 1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 157 Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 10.5.1.2 Pseudo — Code Example In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will be derived from the bus clock divided by 1. ADCCFG = 0x98 (%10011000) Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed) Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1 Bit 4 ADLSMP 1 Configures for long sample time Bit 3:2 MODE 10 Sets mode at 10-bit conversions Bit 1:0 ADICLK 00 Selects bus clock as input clock source ADCSC2 = 0x00 (%00000000) Bit 7 ADACT 0 Bit 6 ADTRG 0 Bit 5 ACFE 0 Bit 4 ACFGT 0 Bit 3:2 00 Bit 1:0 00 Flag indicates if a conversion is in progress Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero ADCSC1 = 0x41 (%01000001) Bit 7 COCO 0 Bit 6 AIEN 1 Bit 5 ADCO 0 Bit 4:0 ADCH 00001 Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Input channel 1 selected as ADC input channel ADCRH/L = 0xxx Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion data cannot be overwritten with data from the next conversion. ADCCVH/L = 0xxx Holds compare value when compare function enabled APCTL1=0x02 AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins APCTL2=0x00 All other AD pins remain general purpose I/O pins MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 158 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 10-14. Initialization Flowchart for Example 10.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 10.6.1 External Pins and Routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results. 10.6.1.1 Analog Supply Pins The ADC module has analog power and ground supplies (VDDAD and VSSAD) which are available as separate pins on some devices. On other devices, VSSAD is shared on the same pin as the MCU digital VSS, and on others, both VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 159 Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 10.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low reference is VREFL, which may be shared on the same pin as VSSAD on some devices. When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same voltage potential as VSSAD. Both VREFH and VREFL must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. AC current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the path is not recommended because the current will cause a voltage drop which could result in conversion errors. Inductance in this path must be minimum (parasitic only). 10.6.1.3 Analog Input Pins The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be performed on inputs without the associated pin control register bit set. It is recommended that the pin control register bit always be set when using a pin as an analog input. This avoids problems with contention because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input buffer draws dc current when its input is not at either VDD or VSS. Setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to VSSA. For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or exceeds VREFH, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF (full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. There will be a brief current associated with VREFL when the sampling capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high. For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 160 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 10.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 10.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 5 kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time. 10.6.2.2 Pin Leakage Error Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high. If this error cannot be tolerated by the application, keep RAS lower than VDDAD / (2N*ILEAK) for less than 1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode). 10.6.2.3 Noise-Induced Errors System noise which occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met: • There is a 0.1 μF low-ESR capacitor from VREFH to VREFL. • There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD. • If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from VDDAD to VSSAD. • VSSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane. • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion. — For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT instruction or STOP instruction. — For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD noise but increases effective conversion time due to stop recovery. • There is no I/O switching, input or output, on the MCU during the conversion. There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: • Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 161 Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 10.6.2.4 Code Width and Quantization Error The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH - VREFL) / 2N Eqn. 10-2 There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB. 10.6.2.5 Linearity Errors The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. These errors are: • Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is used. • Full-scale error (EFS) — This error is defined as the difference between the actual code width of the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the actual $3FE code width and its ideal (1LSB) is used. • Differential non-linearity (DNL) — This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. • Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the) running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. • Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer function and the ideal straight-line transfer function, and therefore includes all forms of error. 10.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 162 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 10.6.2.3 will reduce this error. Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a higher input voltage. Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 163 Analog-to-Digital Converter (S08ADC10V1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 164 Freescale Semiconductor Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. NOTE The SDA and SCL should not be driven above VDD. These pins are pseudo-open-drain containing a protection diode to VDD. 11.1.1 Module Configuration The IIC module pins, SDA and SCL, can be repositioned under software control using IICPS in SOPT1, as as shown in Table 11-1. This bit selects which general-purpose I/O ports are associated with IIC operation. Table 11-1. IIC Position Options SOPT1[IICPS] Port Pin for SDA Port Pin for SCL 0 (default PTA2 PTA3 1 PTB6 PTB7 Figure 11-1 shows the MC9S08EL32 Series and MC9S08SL16 Series block diagram with the IIC module highlighted. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 165 Chapter 11 Inter-Integrated Circuit (S08IICV2) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B SERIAL COMMUNICATIONS INTERFACE (SCI) INT PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PORT C LVD PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 IIC MODULE (IIC) USER EEPROM 512 bytes REAL-TIME COUNTER (RTC) USER RAM 1024 bytes OSCILLATOR (XOSC) XTAL EXTAL INTERNAL CLOCK SOURCE (ICS) VDD VSS VOLTAGE REGULATOR VDDA/ VREFH VSSA/ VREFL ON-CHIP IN-CIRCUIT EMULATOR (ICE) DEBUG MODULE (DBG) TCLK 0 4-CHANNEL TIMER/PWM 1 MODULE (TPM1) 2 3 OUT ANALOG COMPARATOR + (ACMP2) – 16-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16 = Not bonded to pins in 20-pin package = In 20-pin packages, VDDA/VREFH is internally connected to VDD and VSSA/VREFL is internally connected to VSS. Figure 11-1. MC9S08EL32 Block Diagram Highlighting IIC Block and Pins MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 166 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) 11.1.2 Features The IIC includes these distinctive features: • Compatible with IIC bus standard • Multi-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • General call recognition • 10-bit address extension 11.1.3 Modes of Operation A brief description of the IIC in the various MCU modes is given here. • Run mode — This is the basic mode of operation. To conserve power in this mode, disable the module. • Wait mode — The module continues to operate while the MCU is in wait mode and can provide a wake-up interrupt. • Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The stop instruction does not affect IIC register states. Stop2 resets the register contents. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 167 Inter-Integrated Circuit (S08IICV2) 11.1.4 Block Diagram Figure 11-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.1 SCL — Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 11.2.2 SDA — Serial Data Line The bidirectional SDA is the serial data line of the IIC system. 11.3 Register Definition This section consists of the IIC register descriptions in address order. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 168 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 0 0 0 0 0 0 R 0 0 W Reset 0 = Unimplemented or Reserved Figure 11-3. IIC Address Register (IICA) Table 11-2. IICA Field Descriptions Field Description 7–1 AD[7:1] Slave Address. The AD[7:1] field contains the slave address to be used by the IIC module. This field is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 11.3.2 IIC Frequency Divider Register (IICF) 7 6 5 4 3 2 1 0 0 0 0 R MULT ICR W Reset 0 0 0 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 169 Inter-Integrated Circuit (S08IICV2) Table 11-3. IICF Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time. Table 11-5 provides the SCL divider and hold values for corresponding values of the ICR. The SCL divider multiplied by multiplier factor mul generates IIC baud rate. bus speed (Hz) IIC baud rate = --------------------------------------------mul × SCLdivider Eqn. 11-1 SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data). SDA hold time = bus period (s) × mul × SDA hold value Eqn. 11-2 SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the falling edge of SCL (IIC clock). SCL Start hold time = bus period (s) × mul × SCL Start hold value Eqn. 11-3 SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA SDA (IIC data) while SCL is high (Stop condition). SCL Stop hold time = bus period (s) × mul × SCL Stop hold value Eqn. 11-4 For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different ICR and MULT selections to achieve an IIC baud rate of 100kbps. Table 11-4. Hold Time Values for 8 MHz Bus Speed Hold Times (μs) MULT ICR SDA SCL Start SCL Stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0B 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 170 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) Table 11-5. IIC Divider and Hold Values ICR (hex) SCL Divider SDA Hold Value SCL Hold (Start) Value SDA Hold (Stop) Value ICR (hex) SCL Divider SDA Hold Value SCL Hold (Start) Value SCL Hold (Stop) Value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1A 112 17 54 57 3A 1792 257 894 897 1B 128 17 62 65 3B 2048 257 1022 1025 1C 144 25 70 73 3C 2304 385 1150 1153 1D 160 25 78 81 3D 2560 385 1278 1281 1E 192 33 94 97 3E 3072 513 1534 1537 1F 240 33 118 121 3F 3840 513 1918 1921 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 171 Inter-Integrated Circuit (S08IICV2) 11.3.3 IIC Control Register (IICC1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICC1) Table 11-6. IICC1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested. 0 IIC interrupt request not enabled 1 IIC interrupt request enabled 5 MST Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 Slave mode 1 Master mode 4 TX Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high. When addressed as a slave, this bit should be set by software according to the SRW bit in the status register. 0 Receive 1 Transmit 3 TXAK Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge cycles for master and slave receivers. 0 An acknowledge signal is sent out to the bus after receiving one data byte 1 No acknowledge signal response is sent 2 RSTA Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration. 11.3.4 IIC Status Register (IICS) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-6. IIC Status Register (IICS) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 172 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) Table 11-7. IICS Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address or when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit. 0 Not addressed 1 Addressed as a slave 5 BUSY Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set when a start signal is detected and cleared when a stop signal is detected. 0 Bus is idle 1 Bus is busy 4 ARBL Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software by writing a 1 to it. 0 Standard bus operation 1 Loss of arbitration 2 SRW Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the calling address sent to the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave 1 IICIF IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit: • One byte transfer completes • Match of slave address to calling address • Arbitration lost 0 No interrupt pending 1 Interrupt pending 0 RXAK Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received 1 No acknowledge received 11.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 11-7. IIC Data I/O Register (IICD) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 173 Inter-Integrated Circuit (S08IICV2) Table 11-8. IICD Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data. NOTE When transitioning out of master receive mode, the IIC mode should be switched before reading the IICD register to prevent an inadvertent initiation of a master receive data transfer. In slave mode, the same functions are available after an address match has occurred. The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, reading the IICD does not initiate the receive. Reading the IICD returns the last byte received while the IIC is configured in master receive or slave receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify that a byte has been written to the IICD correctly by reading it back. In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required R/W bit (in position bit 0). 11.3.6 IIC Control Register 2 (IICC2) 7 6 GCAEN ADEXT 0 0 R 5 4 3 0 0 0 2 1 0 AD10 AD9 AD8 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 11-8. IIC Control Register (IICC2) Table 11-9. IICC2 Field Descriptions Field Description 7 GCAEN General Call Address Enable. The GCAEN bit enables or disables general call address. 0 General call address is disabled 1 General call address is enabled 6 ADEXT Address Extension. The ADEXT bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2–0 AD[10:8] Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address scheme. This field is only valid when the ADEXT bit is set. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 174 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: • Start signal • Slave address transmission • Data transfer • Stop signal The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure 11-9. msb SCL 1 SDA lsb 2 3 4 5 6 7 8 msb 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal 1 SDA 3 4 5 Calling Address 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 6 7 8 9 Read/ Ack Write Bit 1 XX Repeated Start Signal 9 No Ack Bit msb AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal 3 Data Byte lsb 2 2 Read/ Ack Write Bit Calling Address msb SCL XXX lsb 1 Stop Signal lsb 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W New Calling Address Read/ Write No Ack Bit Stop Signal Figure 11-9. IIC Bus Transmission Signals 11.4.1.1 Start Signal When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a master may initiate communication by sending a start signal. As shown in Figure 11-9, a start signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 175 Inter-Integrated Circuit (S08IICV2) 11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see Figure 11-9). No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit an address equal to its own slave address. The IIC cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the IIC reverts to slave mode and operates correctly even if it is being addressed by another master. 11.4.1.3 Data Transfer Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master. All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 11-9. There is one clock pulse on SCL for each data bit, the msb being transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one complete data transfer needs nine clock pulses. If the slave receiver does not acknowledge the master in the ninth bit time, the SDA line must be left high by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer. If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the SDA line. In either case, the data transfer is aborted and the master does one of two things: • Relinquishes the bus by generating a stop signal. • Commences a new calling by generating a repeated start signal. 11.4.1.4 Stop Signal The master can terminate the communication by generating a stop signal to free the bus. However, the master may generate a start signal followed by a calling command without generating a stop signal first. This is called repeated start. A stop signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-9). The master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 176 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) 11.4.1.5 Repeated Start Signal As shown in Figure 11-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case, the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 Clock Synchronization Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all the devices connected on the bus. The devices start counting their low period and after a device’s clock has gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 11-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. Delay Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure 11-10. IIC Clock Synchronization MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 177 Inter-Integrated Circuit (S08IICV2) 11.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it. If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 11.4.2 10-bit Address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 Master-Transmitter Addresses a Slave-Receiver The transfer direction is not changed (see Table 11-10). When a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. Only one slave finds a match and generates an acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address. S Slave Address 1st 7 bits R/W 11110 + AD10 + AD9 0 A1 Slave Address 2nd byte AD[8:1] A2 Data A ... Data A/A P Table 11-10. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. 11.4.2.2 Master-Receiver Addresses a Slave-Transmitter The transfer direction is changed after the second R/W bit (see Table 11-11). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3. The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 178 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match. S Slave Address 1st 7 bits R/W 11110 + AD10 + AD9 0 A1 Slave Address 2nd byte A2 AD[8:1] Sr Slave Address 1st 7 bits R/W 11110 + AD10 + AD9 1 A3 Data A ... Data A P Table 11-11. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt. 11.4.3 General Call Address General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches the general call address as well as its own slave address. When the IIC responds to a general call, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after the first byte transfer to determine whether the address matches is its own slave address or a general call. If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied from a general call address by not issuing an acknowledgement. 11.5 Resets The IIC is disabled after reset. The IIC cannot cause an MCU reset. 11.6 Interrupts The IIC generates a single interrupt. An interrupt from the IIC is generated when any of the events in Table 11-12 occur, provided the IICIE bit is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You can determine the interrupt type by reading the status register. Table 11-12. Interrupt Summary 11.6.1 Interrupt Source Status Flag Local Enable Complete 1-byte transfer TCF IICIF IICIE Match of received calling address IAAS IICIF IICIE Arbitration Lost ARBL IICIF IICIE Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 179 Inter-Integrated Circuit (S08IICV2) 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 11.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration process and the ARBL bit in the status register is set. Arbitration is lost in the following circumstances: • SDA sampled as a low when the master drives a high during an address or data transmit cycle. • SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. • A start cycle is attempted when the bus is busy. • A repeated start cycle is requested in slave mode. • A stop condition is detected when the master did not request it. This bit must be cleared by software writing a 1 to it. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 180 Freescale Semiconductor Inter-Integrated Circuit (S08IICV2) 11.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode 2. Write: IICA — to set the slave address 3. Write: IICC1 — to enable IIC and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown in Figure 11-12 Module Initialization (Master) 1. Write: IICF — to set the IIC baud rate (example provided in this chapter) 2. Write: IICC1 — to enable IIC and interrupts 3. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 4. Initialize RAM variables used to achieve the routine shown in Figure 11-12 5. Write: IICC1 — to enable TX Register Model AD[7:1] IICA 0 When addressed as a slave (in slave mode), the module responds to this address MULT IICF ICR Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER)) IICC1 IICEN IICIE MST TX TXAK RSTA 0 0 BUSY ARBL 0 SRW IICIF RXAK AD9 AD8 Module configuration IICS TCF IAAS Module status flags DATA IICD Data register; Write to transmit IIC data read to read IIC data IICC2 GCAEN ADEXT 0 0 0 AD10 Address configuration Figure 11-11. IIC Module Quick Start MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 181 Inter-Integrated Circuit (S08IICV2) Clear IICIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) TX Y Set TX Mode RX TX/RX ? N (Write) N N Data Transfer See Note 2 ACK from Receiver ? N Switch to Rx Mode Dummy Read from IICD Generate Stop Signal (MST = 0) Read Data from IICD and Store Read Data from IICD and Store Tx Next Byte Write Data to IICD Set RX Mode Switch to Rx Mode Dummy Read from IICD Dummy Read from IICD RTI NOTES: 1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a general call address, then the general call must be handled by user software. 2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer Figure 11-12. Typical IIC Interrupt Routine MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 182 Freescale Semiconductor Chapter 12 Slave LIN Interface Controller (S08SLICV1) 12.1 Introduction The slave LIN interface controller (SLIC) is designed to provide slave node connectivity on a local interconnect network (LIN) sub-bus. LIN is an open-standard serial protocol developed for the automotive industry to connect sensors, motors, and actuators. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 185 Chapter 12 Slave LIN Interface Controller (S08SLICV1) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B SERIAL COMMUNICATIONS INTERFACE (SCI) INT PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PORT C LVD PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 IIC MODULE (IIC) USER EEPROM 512 bytes REAL-TIME COUNTER (RTC) USER RAM 1024 bytes OSCILLATOR (XOSC) XTAL EXTAL INTERNAL CLOCK SOURCE (ICS) VDD VSS VOLTAGE REGULATOR VDDA/ VREFH VSSA/ VREFL ON-CHIP IN-CIRCUIT EMULATOR (ICE) DEBUG MODULE (DBG) TCLK 0 4-CHANNEL TIMER/PWM 1 MODULE (TPM1) 2 3 OUT ANALOG COMPARATOR + (ACMP2) – 16-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16 = Not bonded to pins in 20-pin package = In 20-pin packages, VDDA/VREFH is internally connected to VDD and VSSA/VREFL is internally connected to VSS. Figure 12-1. MC9S08EL32 Block Diagram Highlighting SLIC Block and Pins MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 186 Freescale Semiconductor 12.1.1 Features The SLIC includes these distinctive features: • Full LIN message buffering of identifier and 8 data bytes • Automatic bit rate and LIN message frame synchronization: — No prior programming of bit rate required, 1–20 kbps LIN bus speed operation — All LIN messages will be received (no message loss due to synchronization process) — Input clock tolerance as high as ±50%, allowing internal oscillator to remain untrimmed — Incoming break symbols always allowed to be 10 or more bit times without message loss — Supports automatic software trimming of internal oscillator using LIN synchronization data • Automatic processing and verification of LIN SYNCH BREAK and SYNCH BYTE • Automatic checksum calculation and verification with error reporting • Maximum of two interrupts per standard LIN message frame with no errors • Full LIN error checking and reporting • High-speed LIN capability up to 83.33 kbps to 120.00 kbps1 • Configurable digital receive filter • Streamlined interrupt servicing through use of a state vector register • Switchable UART-like byte transfer mode for processing bytes one at a time without LIN message framing constraints • Enhanced checksum (includes ID) generation and verification 1. Maximum bit rate of SLIC module dependent upon frequency of SLIC input clock. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 187 12.1.2 Modes of Operation Figure 12-2 shows the modes in which the SLIC will operate. POWER OFF VDD VDD (MIN) AND ANY MCU RESET SOURCE ASSERTED (FROM ANY MODE) ANY MCU RESET SOURCE ASSERTED SLIC RESET SLIC INIT REQUESTED (FROM ANY MODE) INITREQ SET TO 1 IN SLCC1 REGISTER (INITACK = 1) NO MCU RESET SOURCE ASSERTED INITREQ = 0; (INITACK = 0) SLIC DISABLED SLCE SET IN SLCC2 REGISTER SLCE CLEARED IN SLCC2 REGISTER SLCIE=1 and NETWORK ACTIVITY OR OTHER MCU WAKEUP SLIC STOP STOP INSTRUCTION (WAIT INSTRUCTION AND SLCWCM = 1) SLIC RUN (WAIT INSTRUCTION AND SLCWCM = 0) NETWORK ACTIVITY OR OTHER MCU WAKEUP SLIC WAIT Figure 12-2. SLIC Operating Modes 12.1.2.1 Power Off This mode is entered from the reset mode whenever the SLIC module supply voltage VDD drops below its minimum specified value for the SLIC module to guarantee operation. The SLIC module will be placed in the reset mode by a system low-voltage reset (LVR) before being powered down. In this mode, the pin input and output specifications are not guaranteed. 12.1.2.2 Reset This mode is entered from the power off mode whenever the SLIC module supply voltage VDD rises above its minimum specified value (VDD(MIN)) and some MCU reset source is asserted. To prevent the SLIC from entering an unknown state, the internal MCU reset is asserted while powering up the SLIC module. SLIC reset mode is also entered from any other mode as soon as one of the MCU's possible reset sources (e.g., LVR, POR, COP, RST pin, etc.) is asserted. SLIC reset mode may also be entered by the user software by asserting the INITREQ bit. INITACK indicates whether the SLIC module is in the reset mode as a result of writing INITREQ in SLCC1. While in the reset state the SLIC module clocks are stopped. Clearing the INITREQ allows the SLIC to proceed and enter SLIC run mode (if SLCE is set). The module MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 188 Freescale Semiconductor will clear INITACK after the module has left reset mode and the SLIC will seek the next LIN header. It is the responsibility of the user to verify that this operation is compatible with the application before implementing this feature. In this mode, the internal SLIC module voltage references are operative, VDD is supplied to the internal circuits, which are held in their reset state and the internal SLIC module system clock is running. Registers will assume their reset condition. Outputs are held in their programmed reset state, inputs and network activity are ignored. 12.1.2.3 SLIC Disabled This mode is entered from the reset mode after all MCU reset sources are no longer asserted or INITREQ is cleared by the user and the SLIC module clears INITACK. It is entered from the run mode whenever SLCE in SLCC2 is cleared. In this mode the SLIC clock is stopped to conserve power and allow the SLIC module to be configured for proper operation on the LIN bus. 12.1.2.4 SLIC Run This mode is entered from the SLIC disabled mode when SLCE in SLCC2 is set. It is entered from the SLIC wait mode whenever activity is sensed on the LIN bus or some other MCU source wakes the CPU out of wait mode. It is entered from the SLIC stop mode whenever network activity is sensed or some other MCU source wakes the CPU out of stop mode. Messages will not be received properly until the clocks have stabilized and the CPU is also in the run mode. 12.1.2.5 SLIC Wait This power conserving mode is automatically entered from the run mode whenever the CPU executes a WAIT instruction and SLCWCM in SLCC1 is previously cleared. In this mode, the SLIC module internal clocks continue to run. Any activity on the LIN network will cause the SLIC module to exit SLIC wait mode and return to SLIC run. No activity for an a time on the LIN bus will also cause the No Bus Activity Interrupt source to occur. This will also cause an exit from SLIC wait mode. 12.1.2.6 Wakeup from SLIC Wait with CPU in WAIT If the CPU executes the WAIT instruction and the SLIC module enters the wait mode (SLCWCM = 0), the clocks to the SLIC module as well as the clocks in the MCU continue to run. Therefore, the message that wakes up the SLIC module from WAIT and the CPU from wait mode will also be received correctly by the SLIC module. This is because all of the required clocks continue to run in the SLIC module in wait mode. 12.1.2.7 SLIC Stop This power conserving mode is automatically entered from the run mode whenever the CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and SLCWCM in SLCC1 is previously set. In this mode, the SLIC internal clocks are stopped. If SLIC interrupts are enabled (SLCIE = 1) prior to MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 189 entering SLIC stop mode, any activity on the network will cause the SLIC module to exit SLIC stop mode and generate an unmaskable interrupt of the CPU. This wakeup interrupt state is reflected in the SLCSV, encoded as the highest priority interrupt. This interrupt can be cleared by the CPU with a read of the SLCSV and clearing of the SLCF interrupt flag. Depending upon which low-power mode instruction the CPU executes to cause the SLIC module to enter SLIC stop, the message which wakes up the SLIC module (and the CPU) may or may not be received. There are two different possibilities: 1. Wakeup from SLIC Stop with CPU in STOP When the CPU executes the STOP instruction, all clocks in the MCU, including clocks to the SLIC module, are turned off. Therefore, the message which wakes up the SLIC module and the CPU from stop mode will not be received. This is due primarily to the amount of time required for the MCU's oscillator to stabilize before the clocks can be applied internally to the other MCU modules, including the SLIC module. 2. Wakeup from SLIC Stop with CPU in WAIT. If the CPU executes the WAIT instruction and the SLIC module enters the stop mode (SLCWCM = 1), the clocks to the SLIC module are turned off, but the clocks in the MCU continue to run. Therefore, the message which wakes up the SLIC module from stop and the CPU from wait mode will be received correctly by the SLIC module. This is because very little time is required for the CPU to turn the clocks to the SLIC module back on after the wakeup interrupt occurs. NOTE While the SLIC module will correctly receive a message which arrives when the SLIC module is in stop or wait mode and the MCU is in wait mode, if the user enters this mode while a message is being received, the data in the message will become corrupted. This is due to the steps required for the SLIC module to resume operation upon exiting stop or wait mode, and its subsequent resynchronization with the LIN bus. 12.1.2.8 Normal and Emulation Mode Operation The SLIC module operates in the same manner in all normal and emulation modes. All SLIC module registers can be read and written except those that are reserved, unimplemented, or write once. The user must be careful not to unintentionally change reserved bits to avoid unexpected SLIC module behavior. 12.1.2.9 Special Mode Operation Some aspects of SLIC module operation can be modified in special test mode. This mode is reserved for internal use only. 12.1.2.10 Low-Power Options The SLIC module can save power in disabled, wait, and stop modes. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 190 Freescale Semiconductor 12.1.3 Block Diagram STATUS REGISTERS SLCSV AND SLCF SLCSV REGISTER CONTROL CONTROL REGISTERS LIN PROTOCOL STATE MACHINE (PSM) MESSAGE BUFFER — 9 BYTES SLCID SLCD7, SLCD6, SLCD5, SLCD4 SLCD3, SLCD2, SLCD1, SLCD0 SHADOW REGISTER 1 BYTE SLIC CLOCK BUS CLOCK DIGITAL RX FILTER PRESCALER (RXFP) DIGITAL RX FILTER SLCTx SLCRx Figure 12-3. SLIC Module Block Diagram 12.2 12.2.1 External Signal Description SLCTx — SLIC Transmit Pin The SLCTx pin serves as the serial output of the SLIC module. 12.2.2 SLCRx — SLIC Receive Pin The SLCRx pin serves as the serial input of the SLIC module. This input feeds into the digital receive filter block which filters out noise glitches from the incoming data stream. 12.3 12.3.1 Register Definition SLIC Control Register 1 (SLCC1) SLIC control register 1 (SLCC1) contains bits used to control various basic features of the SLIC module, including features used for initialization and at runtime. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 191 R 7 6 0 0 5 4 3 2 1 0 INITREQ BEDD WAKETX TXABRT IMSG SLCIE 1 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 12-4. SLIC Control Register 1 (SLCC1) Table 12-1. SLCC1 Field Descriptions Field Description 5 INITREQ Initialization Request — Requesting initialization mode by setting this bit will place the SLIC module into its initialized state immediately. As a result of setting INITREQ, INITACK will be set in SLCS. INITACK = 1 causes all SLIC register bits (except SLCWCM: write once) to be held in their reset states and become not writable until INITACK has been cleared. If transmission or reception of data is in progress, the transaction will be terminated immediately upon entry into initialization mode (signified by INITACK being set to 1). To return to normal SLIC operation after the SLIC has been initialized (the INITACK is high), the INITREQ must be cleared by software. 0 Normal operation 1 Request for SLIC to be put into reset state immediately BEDD Bit Error Detection Disable — This bit allows the user to disable bit error detection circuitry. Bit error detection monitors the received bits to determine if they match the state of the corresponding transmitted bits. When bit error detection is enabled and a mismatch between transmitted bit and received bit is detected, a bit error is reported to the user through the SLCSV register and a SLIC interrupt is generated (if SLIC interrupts are enabled). The user must ensure that all physical delays which affect the timing of received bits are not significant enough to cause the bit error detection circuitry to incorrectly detect bit errors at higher LIN bus speeds. See Section 12.6.15, “Bit Error Detection and Physical Layer Delay,” for details. 4 BEDD NOTE Bit Error detection is not recommended for use in BTM mode, as bit errors are reported on bit boundaries, not byte boundaries. This can result in misaligned data. Bit errors must not be disabled during normal LIN operations, as it allows the SLIC module to operate outside of the LIN specification. If you switch off bit error detection, there is no guaranteed way to detect bus collisions and automatically cease transmissions. Therefore pending SLIC transmissions may continue after a bit error should have been detected, potentially corrupting bus traffic. 0 Bit Error Detection Enabled 1 Bit Error Detection Disabled no bit errors will be detected or reported 3 WAKETX Transmit Wakeup Symbol— This bit allows the user to transmit a wakeup symbol on the LIN bus. When set, this sends a wakeup symbol, as defined in the LIN specification a single time, then resets to 0. This bit will read 1 while the wakeup symbol is being transmitted on the bus. This bit will be automatically cleared when the wakeup symbol is complete. 0 Normal operation 1 Send wakeup symbol on LIN bus MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 192 Freescale Semiconductor Table 12-1. SLCC1 Field Descriptions (continued) Field Description 2 TXABRT Transmit Abort Message 0 Normal operation 1 Transmitter aborts current transmission at next byte boundary; TXABRT resets to 0 after the transmission is successfully aborted TXABRT also resets to 0 upon detection of a bit error. 1 IMSG SLIC Ignore Message Bit — IMSG cannot be cleared by a write of 0, but is cleared automatically by the SLIC module after the next BREAK/SYNC symbol pair is validated. After it is set, IMSG will not keep data from being written to the receive data buffer, which means that the buffers cannot be assumed to contain known valid message data until the next receive buffer full interrupt. IMSG must not be used in BTM mode. The SLIC automatically clears the IMSG bit when entering MCU STOP mode or MCU wait mode with SLCWCM bit set. 0 Normal operation1SLIC interrupts (except "No Bus Activity") are suppressed until the next message header arrives 0 SLCIE SLIC Interrupt Enable 0 SLIC interrupt sources are disabled 1 SLIC interrupt sources are enabled 12.3.2 SLIC Control Register 2 (SLCC2) SLIC control register 2 (SLCC2) contains bits used to control various features of the SLIC module. 7 R 6 5 4 3 2 SLCWCM BTM 0 0 0 1 0 0 RXFP SLCE W Reset 0 1 0 0 0 0 = Unimplemented or Reserved Figure 12-5. SLIC Control Register 2 (SLCC2) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 193 Table 12-2. SLCC2 Field Descriptions Field 6:4 RXFP 1 Description Receive Filter Prescaler — These bits configure the effective filter width for the digital receive filter circuit. The RXFP bits control the maximum number of SLIC clock counts required for the filter to change state, which determines the total maximum filter delay. Any pulse which is smaller than the maximum filter delay value will be rejected by the filter and ignored as noise. For this reason, the user must choose the prescaler value appropriately to ensure that all valid message traffic is able to pass the filter for the desired bit rate. For more details about setting up the digital receive filter, please refer to Section 12.6.18, “Digital Receive Filter.” The frequency of the SLIC clock must be between 2 MHz and 20 MHz, factoring in worst case possible numbers due to untrimmed process variations, as well as temperature and voltage variations in oscillator frequency. This will guarantee greater than 1.5% accuracy for all LIN messages from 1–20 kbps. The faster this input clock is, the greater the resulting accuracy and the higher the possible bit rates at which the SLIC can send and receive. In LIN systems, the bit rates will not exceed 20 kbps; however, the SLIC module is capable of much higher speeds without any configuration changes, for cases such as high-speed downloads for reprogramming of FLASH memory or diagnostics in a test environment where radiated emissions requirements are not as stringent. In these situations, the user may choose to run faster than the 20 kbps limit which is imposed by the LIN specification for EMC reasons. Details of how to calculate maximum bit rates and operate the SLIC above 20 kbps are detailed in .” Refer to Section 12.6.6, “SLIC Module Initialization Procedure,” for more information on when to set up this register. See Table 12-3. 3 SLCWCM SLIC Wait Clock Mode — This write-once bit can only be written once out of MCU reset state and should be written before SLIC is first enabled. 0 SLIC clocks continue to run when the CPU is placed into wait mode so that the SLIC can receive messages and wakeup the CPU. 1 SLIC clocks stop when the CPU is placed into wait mode 2 BTM1 UART Byte Transfer Mode — Byte transmit mode bypasses the normal LIN message framing and checksum monitoring and allows the user to send and receive single bytes in a method similar to a half-duplex UART. When enabled, this mode reads the bit time register (SLCBT) value and assumes this is the value corresponding to the number of SLIC clock counts for one bit time to establish the desired UART bit rate. The user software must initialize this register prior to sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate. If this bit is cleared during a byte transmission, that byte transmission is halted immediately. BTM treats any data length in SLCDLC as one byte (DLC = 0x00) and disables the checksum circuitry so that CHKMOD has no effect. Refer to Section 12.6.16, “Byte Transfer Mode Operation,” for more detailed information about how to use this mode. BTM sets up the SLIC module to send and receive one byte at a time, with 8-bit data, no parity, and one stop bit (8-N-1). This is the most commonly used setup for UART communications and should work for most applications. This is fixed in the SLIC and is not configurable. 0 UART byte transfer mode disabled 1 UART byte transfer mode enabled 0 SLCE SLIC Module Enable — Controls the clock to the SLIC module 0 SLIC module disabled 1 SLIC module enabled To guarantee timing, the user must ensure that the SLIC clock used allows the proper communications timing tolerances and therefore internal oscillator circuits might not be appropriate for use with BTM mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 194 Freescale Semiconductor Table 12-3. Digital Receive Filter Clock Prescaler Max Filter Delay (in μs) RXFP[2:0] Digital RX Filter Clock Prescaler (Divide by) Filter Input Clock (SLIC clock in MHz) 2 4 6 8 10 12 14 16 18 20 000 1 8.00 4.00 2.67 2.00 1.60 1.33 1.14 1.00 0.89 0.80 001 2 16.00 8.00 5.33 4.00 3.20 2.67 2.29 2.00 1.78 1.60 010 3 24.00 12.00 8.00 6.00 4.80 4.00 3.43 3.00 2.67 2.40 011 4 32.00 16.00 10.67 8.00 6.40 5.33 4.57 4.00 3.56 3.20 100 5 40.00 20.00 13.33 10.00 8.00 6.67 5.71 5.00 4.44 4.00 101 6 48.00 24.00 16.00 12.00 9.60 8.00 6.86 6.00 5.33 4.80 110 7 56.00 28.00 18.67 14.00 11.20 9.33 8.00 7.00 6.22 5.60 111 8 64.00 32.00 21.33 16.00 12.80 10.67 9.14 8.00 7.11 6.40 12.3.3 SLIC Bit Time Registers (SLCBTH, SLCBTL) NOTE In this subsection, the SLIC bit time registers are collectively referred to as SLCBT. In LIN operating mode (BTM = 0), the SLCBT is updated by the SLIC upon reception of a LIN break-sync combination and provides the number of SLIC clock counts that equal one LIN bit time to the user software. This value can be used by the software to calculate the clock drift in the oscillator as an offset to a known count value (based on nominal oscillator frequency and LIN bus speed). The user software can then trim the oscillator to compensate for clock drift. Refer to Section 12.6.17, “Oscillator Trimming with SLIC,” for more information on this procedure. The user should only read the bit time value from SLCBTH and SLCBTL in the interrupt service routine code for reception of the identifier byte. Reads at any other time during LIN activity may not provide reliable results. When in byte transfer mode (BTM = 1), the SLCBT must be written by the user to set the length of one bit at the desired bit rate in SLIC clock counts. The user software must initialize this number prior to sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate. This setting is similar to choosing an input capture or output compare value for a timer. A write to both registers is required to update the bit time value. NOTE The SLIC bit time will not be updated until a write of the SLCBTL has occurred. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 195 7 R 6 5 4 3 2 1 0 BT14 BT13 BT12 BT11 BT10 BT9 BT8 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved1 Figure 12-6. SLIC Bit Time Register High (SLCBTH) 1 Do not write to unimplemented bits as unexpected operation may occur. Table 12-4. SLCBTH Field Descriptions Field Description 6:0 BT[14:8] Bit Time Value — BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0). For details of the use of the SLCBT registers in LIN mode for trimming of the internal oscillator, refer to Section 12.6.17, “Oscillator Trimming with SLIC.” BT sets the number of SLIC clocks that equals one bit time in byte transfer mode (BTM = 1). For details of the use of the SLCBT registers in BTM mode, refer to Section 12.6.16, “Byte Transfer Mode Operation.” 7 6 5 4 3 2 1 0 BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved1 Figure 12-7. SLIC Bit Time Register Low (SLCBTL) 1 Do not write to unimplemented bits as unexpected operation may occur. Table 12-5. SLCBTL Field Descriptions Field Description 7:0 BT[7:0] Bit Time Value — BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0). For details of the use of the SLCBT registers in LIN mode for trimming of the internal oscillator, refer to Section 12.6.17, “Oscillator Trimming with SLIC.” BT sets the number of SLIC clocks that equals one bit time in byte transfer mode (BTM = 1). For details of the use of the SLCBT registers in BTM mode, refer to Section 12.6.16, “Byte Transfer Mode Operation.” 12.3.4 SLIC Status Register (SLCS) SLIC status register (SLCS) contains bits used to monitor the status of the SLIC module. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 196 Freescale Semiconductor R 7 6 5 4 3 2 1 SLCACT 0 INITACK 0 0 0 0 0 SLCF W Reset 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure 12-8. SLIC Status Register (SLCS) Table 12-6. SLCS Field Descriptions 1 Field Description 7 SLCACT1 SLIC Active (Oscillator Trim Blocking Semaphore) — SLCACT is used to indicate if it is safe to trim the oscillator based upon current SLIC activity in LIN mode. This bit indicates that the SLIC module might be currently receiving a message header, synchronization byte, ID byte, or sending or receiving data bytes. This bit is read-only. This bit has no meaning in BTM mode (BTM =1). 0 SLIC module not active (safe to trim oscillator) SLCACT is cleared by the SLIC module only upon assertion of the RX Message Buffer Full Checksum OK (SLCSV = 0x10) or the TX Message Buffer Empty Checksum Transmitted (SLCSV = 0x08) interrupt sources. 1 SLIC module activity (not safe to trim oscillator) SLCACT is automatically set to 1 if a falling edge is seen on the SLCRX pin and has successfully been passed through the digital RX filter. This edge is the potential beginning of a LIN message frame. 5 INITACK Initialization Mode Acknowledge — INITACK indicates whether the SLIC module is in the reset mode as a result of writing INITREQ in SLCC1. INITACK = 1 causes all SLIC register bits (except SLCWCM: write once) to be held in their reset state and become not writable until INITACK has been cleared. Clear INITACK by clearing INITREQ in SLCC1. After INITACK is cleared, the SLIC module proceeds to SLIC DISABLED mode (see Figure 12-2) in which the other SLIC register bits are writable and can be configured to the desired SLIC operating mode. INITACK is a read-only bit. 0 Normal operation 1 SLIC module is in reset state 0 SLCF SLIC Interrupt Flag — The SLCF interrupt flag indicates if a SLIC module interrupt is pending. If set, the SLCSV is then used to determine what interrupt is pending. This flag is cleared by writing a 1 to the bit. If additional interrupt sources are pending, the bit will be automatically set to 1 again by the SLIC. 0 No SLIC interrupt pending 1 SLIC interrupt pending SLCACT may not be clear during all idle times of the bus. For example, if IMSG was used to ignore the data interrupts of an extended message frame, SLCACT will remain set until another LIN message is received and either the RX Message Buffer Full Checksum OK (SLCSV = 0x10) or the TX Message Buffer Empty Checksum Transmitted (SLCSV = 0x08) interrupt sources are asserted and cleared. When clear, SLCACT always indicates times when the SLIC module is not active, but it is possible for the SLIC module to be not active with SLCACT set. SLCACT has no meaning in BTM mode. 12.3.5 SLIC State Vector Register (SLCSV) SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state machine in software. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 197 R 7 6 5 4 3 2 1 0 0 0 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-9. SLIC State Vector Register (SLCSV) Table 12-7. SLCSV Field Descriptions Field 5:2 I[3:0] Description Interrupt State Vector — These bits indicate the source of the interrupt request that is currently pending. READ: any time WRITE: ignored 12.3.5.1 LIN Mode Operation Table 12-8 shows the possible values for the possible sources for a SLIC interrupt while in LIN mode operation (BTM = 0). Table 12-8. Interrupt Sources Summary (BTM = 0) SLCSV I3 I2 I1 I0 Interrupt Source Priority 0x00 0 0 0 0 No Interrupts Pending 0 (Lowest) 0x04 0 0 0 1 No-Bus-Activity 1 0x08 0 0 1 0 TX Message Buffer Empty Checksum Transmitted 2 0x0C 0 0 1 1 TX Message Buffer Empty 3 0x10 0 1 0 0 RX Message Buffer Full Checksum OK 4 0x14 0 1 0 1 RX Data Buffer Full No Errors 5 0x18 0 1 1 0 Bit-Error 6 0x1C 0 1 1 1 Receiver Buffer Overrun 7 0x20 1 0 0 0 Reserved 8 0x24 1 0 0 1 Checksum Error 9 0x28 1 0 1 0 Byte Framing Error 10 0x2C 1 0 1 1 Identifier Received Successfully 11 0x30 1 1 0 0 Identifier Parity Error 12 0x34 1 1 0 1 Reserved 13 0x38 1 1 1 0 Reserved 14 0x3C 1 1 1 1 Wakeup 15 (Highest) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 198 Freescale Semiconductor • • • • • • • • • No Interrupts Pending This value indicates that all pending interrupt sources have been serviced. In polling mode, the SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate an interrupt of the CPU, regardless of state of SLCIE. No Bus Activity (LIN specified error) The No-Bus-Activity condition occurs if no valid SYNCH BREAK FIELD or BYTE FIELD was received for more than 223 SLIC clock counts since the reception of the last valid message. For example, with 10 MHz SLIC clock frequency, a No-Bus-Activity interrupt will occur approximately 0.839 seconds after the bus begins to idle. TX Message Buffer Empty — Checksum Transmitted When the entire LIN message frame has been transmitted successfully, complete with the appropriately selected checksum byte, this interrupt source is asserted. This source is used for all standard LIN message frames and the final set of bytes with extended LIN message frames. TX Message Buffer Empty This interrupt source indicates that all 8 bytes in the LIN message buffer have been transmitted with no checksum appended. This source is used for intermediate sets of 8 bytes in extended LIN message frames. RX Message Buffer Full — Checksum OK When the entire LIN message frame has been received successfully, complete with the appropriately selected checksum byte, and the checksum calculates correctly, this interrupt source is asserted. This source is used for all standard LIN message frames and the final set of bytes with extended LIN message frames. To clear this source, SLCD0 must be read first. RX Data Buffer Full — No Errors This interrupt source indicates that 8 bytes have been received with no checksum byte and are waiting in the LIN message buffer. This source is used for intermediate sets of 8 bytes in extended LIN message frames. To clear this source, SLCD0 must be read first. Bit Error A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR must be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. The SLIC will terminate the data transmission upon detection of a bit error, according to the LIN specification. Bit errors are not checked when the LIN bus is running at high speed due to the effects of physical layer round trip delay. Bit errors are checked only when BEDD = 0. Receiver Buffer Overrun Error This error is an indication that the receive buffer has not been emptied and additional bytes have been received, resulting in lost data. Because this interrupt is higher priority than the receive buffer full interrupts, it will appear first when an overflow condition occurs. There will, however, be a pending receive interrupt which must also be cleared after the buffer overrun flag is cleared. Buffer overrun errors can be avoided if on reception of data complete with checksum correct (SLCSV=$10) SLCD0 is read, the software sets IMSG after reception of a valid ID, the software enters BTM mode, or received data causes a framing or checksum error to occur. Checksum Error (LIN specified error) The checksum error occurs when the calculated checksum value does not match the expected value. If this error is encountered, it is important to verify that the correct checksum calculation MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 199 • method was employed for this message frame. Refer to the LIN specification for more details on the calculations. Byte Framing Error This error comes from the standard UART definition for byte encoding and occurs when the STOP bit is sampled and reads back as a 090. STOP should always read as 1. NOTE A byte framing error can also be an indication that the number of data bytes received in a LIN message frame does not match the value written to the SLCDLC register. See Section 12.6.7, “Handling LIN Message Headers,” for more details. • • • Identifier Received Successfully This interrupt source indicates that a LIN identifier byte has been received with correct parity and is waiting in the LIN identifier buffer (SLCID). Upon reading this interrupt source from SLCSV, the user can then decode the identifier in software to determine the nature of the LIN message frame. To clear this source, SLCID must be read. Identifier-Parity-Error A parity error in the identifier (i.e., corrupted identifier) will be flagged. Typical LIN slave applications do not distinguish between an unknown but valid identifier, and a corrupted identifier. However, it is mandatory for all slave nodes to evaluate in case of a known identifier all eight bits of the ID-Field and distinguish between a known and a corrupted identifier. The received identifier value is reported in SLCID so that the user software can choose to acknowledge or ignore the parity error message. Once the ID parity error has been detected, the SLIC will begin looking for another LIN header and will not receive message data, even if it appears on the bus. Wakeup The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC stop mode. 12.3.5.2 Byte Transfer Mode Operation When byte transfer mode is enabled (BTM = 1), many of the interrupt sources for the SLCSV no longer apply, as they are specific to LIN operations. Table 12-9 shows those interrupt sources which are applicable to BTM operations. The value of the SLCSV for each interrupt source remains the same, as well as the priority of the interrupt source. I Table 12-9. Interrupt Sources Summary (BTM = 1) SLCSV I3 I2 I1 I0 Interrupt Source Priority 0x00 0 0 0 0 No Interrupts Pending 0 (Lowest) 0x0C 0 0 1 1 TX Message Buffer Empty 3 0x14 0 1 0 1 RX Data Buffer Full No Errors 5 0x18 0 1 1 0 Bit-Error 6 0x1C 0 1 1 1 Receiver Buffer Overrun 7 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 200 Freescale Semiconductor Table 12-9. Interrupt Sources Summary (BTM = 1) • • • • • • • • SLCSV I3 I2 I1 I0 Interrupt Source Priority 0x28 1 0 1 0 Byte Framing Error 10 0x38 1 1 1 0 Reserved 14 0x3C 1 1 1 1 Wakeup 15 (Highest) No Interrupts Pending This value indicates that all pending interrupt sources have been serviced. In polling mode, the SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate an interrupt of the CPU, regardless of state of SLCIE. TX Message Buffer Empty In byte transfer mode, this interrupt source indicates that the byte in the SLCID has been transmitted. RX Data Buffer Full — No Errors This interrupt source indicates that a byte has been received and is waiting in SLCID. To clear this source, SLCID must be read first. Bit Error A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR must be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. The SLIC will terminate the data transmission upon detection of a bit error, according to the LIN specification. Bit errors are not checked when the LIN bus is running at high speed due to the effects of physical layer round trip delay. Bit errors are checked only when BEDD = 0. Receiver Buffer Overrun Error This error is an indication that the receive buffer has not been emptied and additional byte(s) have been received, resulting in lost data. Because this interrupt is higher priority than the receive buffer full interrupts, it will appear first when an overflow condition occurs. There will, however, be a pending receive interrupt which must also be cleared after the buffer overrun flag is cleared. Buffer overrun errors can be avoided if on reception of data (SLCSV=$14) SLCD0 is read or received data causes a framing error to occur. Byte Framing Error This error comes from the standard UART definition for byte encoding and occurs when STOP is sampled and reads back as a 0. STOP should always read as 1. A byte framing error could be encountered if the bit timing value programmed in BTH:L does not match the bit rate of the incoming data. Wakeup The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC wait mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 201 12.3.6 SLIC Data Length Code Register (SLCDLC) The SLIC data length code register (SLCDLC) is the primary functional control register for the SLIC module during normal LIN operations. It contains the data length code of the message buffer, indicating how many bytes of data are to be sent or received, as well as the checksum mode control and transmit enabling bit. 7 6 5 4 3 2 1 0 TXGO CHKMOD DLC5 DLC4 DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 0 0 0 R W Reset Figure 12-10. SLIC Data Length Code Register (SLCDLC) Table 12-10. SLCDLC Field Descriptions Field Description 7 TXGO SLIC Transmit Go — This bit controls whether the SLIC module is sending or receiving data bytes. This bit is automatically reset to 0 after a transmit operation is complete or an error is encountered and transmission has been aborted. 0 SLIC receive data 1 Initiate SLIC transmit— The SLIC assumes the user has loaded the proper data into the message buffer and will begin transmitting the number of bytes indicated in the SLCDLC bits. If the number of bytes is greater than 8, the first 8 bytes will be transmitted and an interrupt will be triggered (if unmasked) for the user to enter the next bytes of the message. If the number of bytes is 8 or fewer, the SLIC will transmit the appropriate number of bytes and automatically append the checksum to the transmission. If IMSG or TXABRT are set or the SLCF flag is set, writes to TXGO will have no effect. 6 CHKMOD LIN Checksum Mode — CHKMOD is used to decide what checksum method to use for this message frame. Resets after error code or message frame complete. CHKMOD must be written (124 desired) only after the reception of an identifier and before the reception or transmission of data bytes. Writing this bit to a one clears the current checksum calculation. 0 Checksum calculated 119 the identifier byte included (SAE J2602/LIN 2.0) 1 Checksum calculated without the identifier byte (LIN spec 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 278 Freescale Semiconductor Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) 16.1 Introduction The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). All MC9S08EL32 Series and MC9S08SL16 Series MCUs have two TPM modules. In all packages, TPM2 is 2-channel. The number of channels available in TPM1 depends on the device, as shown in Table 16-1: t Table 16-1. MC9S08EL32 Series and MC9S08SL16 Series Features by MCU and Package Feature Pin quantity Package type 9S08EL32 9S08EL16 9S08SL16 9S08SL8 28 20 28 20 28 20 28 20 TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TPM1 channels 4 2 TPM2 channels 2 2 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 279 Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B SERIAL COMMUNICATIONS INTERFACE (SCI) INT PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PORT C LVD PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 IIC MODULE (IIC) USER EEPROM 512 bytes REAL-TIME COUNTER (RTC) USER RAM 1024 bytes OSCILLATOR (XOSC) XTAL EXTAL INTERNAL CLOCK SOURCE (ICS) VDD VSS VOLTAGE REGULATOR VDDA/ VREFH VSSA/ VREFL ON-CHIP IN-CIRCUIT EMULATOR (ICE) DEBUG MODULE (DBG) TCLK 0 4-CHANNEL TIMER/PWM 1 MODULE (TPM1) 2 3 OUT ANALOG COMPARATOR + (ACMP2) – 16-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16 = Not bonded to pins in 20-pin package = In 20-pin packages, VDDA/VREFH is internally connected to VDD and VSSA/VREFL is internally connected to VSS. Figure 16-1. MC9S08EL32 Block Diagram Highlighting TPM Block and Pins MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 280 Freescale Semiconductor Timer/PWM Module (S08TPMV3) 16.1.1 Features The TPM includes these distinctive features: • One to eight channels: — Each channel may be input capture, output compare, or edge-aligned PWM — Rising-Edge, falling-edge, or any-edge input capture trigger — Set, clear, or toggle output compare action — Selectable polarity on PWM outputs • Module may be configured for buffered, center-aligned pulse-width-modulation (CPWM) on all channels • Timer clock source selectable as prescaled bus clock, fixed system clock, or an external clock pin — Prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 — Fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit — External clock pin may be shared with any timer channel pin or a separated input pin • 16-bit free-running or modulo up/down count operation • Timer system enable • One interrupt per channel plus terminal count interrupt 16.1.2 Modes of Operation In general, TPM channels may be independently configured to operate in input capture, output compare, or edge-aligned PWM modes. A control bit allows the whole TPM (all channels) to switch to center-aligned PWM mode. When center-aligned PWM mode is selected, input capture, output compare, and edge-aligned PWM functions are not available on any channels of this TPM module. When the microcontroller is in active BDM background or BDM foreground mode, the TPM temporarily suspends all counting until the microcontroller returns to normal user operating mode. During stop mode, all system clocks, including the main oscillator, are stopped; therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to operate normally. Provided the TPM does not need to produce a real time reference or provide the interrupt source(s) needed to wake the MCU from wait mode, the user can save power by disabling TPM functions before entering wait mode. • Input capture mode When a selected edge event occurs on the associated MCU pin, the current value of the 16-bit timer counter is captured into the channel value register and an interrupt flag bit is set. Rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. • Output compare mode When the value in the timer counter register matches the channel value register, an interrupt flag bit is set, and a selected output action is forced on the associated MCU pin. The output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 281 Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point. This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned with the beginning of the period, which is the same for all channels within a TPM. Center-aligned PWM mode Twice the value of a 16-bit modulo register sets the period of the PWM output, and the channel-value register sets the half-duty-cycle duration. The timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. As the count matches the channel value register while counting down, the PWM output becomes active. When the count matches the channel value register while counting up, the PWM output becomes inactive. This type of PWM signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. This type of PWM is required for types of motors used in small appliances. This is a high-level description only. Detailed descriptions of operating modes are in later sections. 16.1.3 Block Diagram The TPM uses one input/output (I/O) pin per channel, TPMxCHn (timer channel n) where n is the channel number (1-8). The TPM shares its I/O pins with general purpose I/O port pins (refer to I/O pin descriptions in full-chip specification for the specific chip implementation). Figure 16-2 shows the TPM structure. The central component of the TPM is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter (the values 0x0000 or 0xFFFF effectively make the counter free running). Software can read the counter value at any time without affecting the counting sequence. Any write to either half of the TPMxCNT counter resets the counter, regardless of the data value written. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 282 Freescale Semiconductor Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK SYNC EXTERNAL CLOCK CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT ³1, 2, 4, 8, 16, 32, 64, or ³128 CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF COUNTER RESET TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC TPMxCH0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERNAL BUS 16-BIT LATCH CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE INTERRUPT LOGIC PORT LOGIC TPMxCH1 16-BIT COMPARATOR TPMxC1VH:TPMxC1VL CH1F 16-BIT LATCH MS1B CH1IE MS1A INTERRUPT LOGIC Up to 8 channels CHANNEL 7 ELS7B ELS7A PORT LOGIC TPMxCH7 16-BIT COMPARATOR TPMxC7VH:TPMxC7VL CH7F 16-BIT LATCH MS7B MS7A CH7IE INTERRUPT LOGIC Figure 16-2. TPM Block Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 283 Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel. The details of how a module interacts with pin controls depends upon the chip implementation because the I/O pins and associated general purpose I/O controls are not part of the module. Refer to the discussion of the I/O port logic in a full-chip specification. Because center-aligned PWMs are usually used to drive 3-phase AC-induction motors and brushless DC motors, they are typically used in sets of three or six channels. 16.2 Signal Description Table 16-2 shows the user-accessible signals for the TPM. The number of channels may be varied from one to eight. When an external clock is included, it can be shared with the same pin as any TPM channel; however, it could be connected to a separate input pin. Refer to the I/O pin descriptions in full-chip specification for the specific chip implementation. Table 16-2. Signal Properties Name Function EXTCLK1 2 TPMxCHn External clock source which may be selected to drive the TPM counter. I/O pin associated with TPM channel n 1 When preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. 2 n=channel number (1 to 8) Refer to documentation for the full-chip for details about reset states, port connections, and whether there is any pullup device on these pins. TPM channel pins can be associated with general purpose I/O pins and have passive pullup devices which can be enabled with a control bit when the TPM or general purpose I/O controls have configured the associated pin as an input. When no TPM function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose I/O controls, including the port-data and data-direction registers. Immediately after reset, no TPM functions are enabled, so all associated pins revert to general purpose I/O control. 16.2.1 Detailed Signal Descriptions This section describes each user-accessible pin signal in detail. Although Table 16-2 grouped all channel pins together, any TPM pin can be shared with the external clock source signal. Since I/O pin logic is not part of the TPM, refer to full-chip documentation for a specific derivative for more details about the interaction of TPM pin functions and general purpose I/O controls including port data, data direction, and pullup controls. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 284 Freescale Semiconductor Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM. The bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the frequency of the bus-rate clock, to meet Nyquist criteria and allowing for jitter. The external clock signal shares the same pin as a channel I/O pin, so the channel pin will not be usable for channel I/O function when selected as the external clock source. It is the user’s responsibility to avoid such settings. If this pin is used as an external clock source (CLKSB:CLKSA = 1:1), the channel can still be used in output compare mode as a software timer (ELSnB:ELSnA = 0:0). 16.2.1.2 TPMxCHn — TPM Channel n I/O Pin(s) Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the channel configuration. The TPM pins share with general purpose I/O pins, where each pin has a port data register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. The TPM channel does not control the I/O pin when (ELSnB:ELSnA = 0:0) or when (CLKSB:CLKSA = 0:0) so it normally reverts to general purpose I/O control. When CPWMS = 1 (and ELSnB:ELSnA not = 0:0), all channels within the TPM are configured for center-aligned PWM and the TPMxCHn pins are all controlled by the TPM system. When CPWMS=0, the MSnB:MSnA control bits determine whether the channel is configured for input capture, output compare, or edge-aligned PWM. When a channel is configured for input capture (CPWMS=0, MSnB:MSnA = 0:0 and ELSnB:ELSnA not = 0:0), the TPMxCHn pin is forced to act as an edge-sensitive input to the TPM. ELSnB:ELSnA control bits determine what polarity edge or edges will trigger input-capture events. A synchronizer based on the bus clock is used to synchronize input edges to the bus clock. This implies the minimum pulse width—that can be reliably detected—on an input capture pin is four bus clock periods (with ideal clock pulses as near as two bus clocks can be detected). TPM uses this pin as an input capture input to override the port data and data direction controls for the same pin. When a channel is configured for output compare (CPWMS=0, MSnB:MSnA = 0:1 and ELSnB:ELSnA not = 0:0), the associated data direction control is overridden, the TPMxCHn pin is considered an output controlled by the TPM, and the ELSnB:ELSnA control bits determine how the pin is controlled. The remaining three combinations of ELSnB:ELSnA determine whether the TPMxCHn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. When the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare event—then the pin is toggled. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 285 Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ... 2 ... TPMxCHn CHnF BIT TOF BIT Figure 16-3. High-True Pulse of an Edge-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 TPMxCHn CHnF BIT TOF BIT Figure 16-4. Low-True Pulse of an Edge-Aligned PWM MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 286 Freescale Semiconductor Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB:ELSnA=1:0, the corresponding TPMxCHn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the TPMxCHn pin is set when the timer counter is counting down, and the channel value register matches the timer counter. If ELSnA=1, the corresponding TPMxCHn pin is set when the timer counter is counting up and the channel value register matches the timer counter; the TPMxCHn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter. TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... 7 8 7 6 5 ... TPMxCHn CHnF BIT TOF BIT Figure 16-5. High-True Pulse of a Center-Aligned PWM TPMxMODH:TPMxMODL = 0x0008 TPMxMODH:TPMxMODL = 0x0005 TPMxCNTH:TPMxCNTL ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 TPMxCHn CHnF BIT TOF BIT Figure 16-6. Low-True Pulse of a Center-Aligned PWM MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 287 Timer/PWM Module (S08TPMV3) 16.3 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.1 TPM Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM configuration, clock source, and prescale factor. These controls relate to all channels within this timer module. 7 R TOF W 0 Reset 0 6 5 4 3 2 1 0 TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0 0 0 0 0 0 0 Figure 16-7. TPM Status and Control Register (TPMxSC) Table 16-3. TPMxSC Field Descriptions Field Description 7 TOF Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect. 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 TOIE Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is generated when TOF equals one. Reset clears TOIE. 0 TOF interrupts inhibited (use for software polling) 1 TOF interrupts enabled 5 CPWMS Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS. 0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register. 1 All channels operate in center-aligned PWM mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 288 Freescale Semiconductor Timer/PWM Module (S08TPMV3) Table 16-3. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 16-4, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the fixed-system clock source is the same as the bus rate clock. The external source is synchronized to the bus clock by TPM module, and the fixed system clock source (when a PLL or FLL is present) is synchronized to the bus clock by an on-chip synchronization circuit. When a PLL or FLL is present but not enabled, the fixed-system clock source is the same as the bus-rate clock. 2–0 PS[2:0] Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in Table 16-5. This prescaler is located after any clock source synchronization or clock source selection so it affects the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits. Table 16-4. TPM-Clock-Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disable) 01 Bus rate clock 10 Fixed system clock 11 External source Table 16-5. Prescale Factor Selection 16.3.2 PS2:PS1:PS0 TPM Clock Source Divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. The coherency mechanism is automatically restarted by an MCU reset or any write to the timer status/control register (TPMxSC). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 289 Timer/PWM Module (S08TPMV3) Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. R 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 W Reset Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 Figure 16-8. TPM Counter Register High (TPMxCNTH) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMxCNTL clears the 16-bit counter 0 0 0 0 0 0 Figure 16-9. TPM Counter Register Low (TPMxCNTL) When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active, even if one or both counter halves are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write. 16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is active or not). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 290 Freescale Semiconductor Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active. 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 16-10. TPM Counter Modulo Register High (TPMxMODH) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 16-11. TPM Counter Modulo Register Low (TPMxMODL) Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. 16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. 7 R 6 5 4 3 2 CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 CHnF W 0 Reset 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 291 Timer/PWM Module (S08TPMV3) Table 16-6. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers. A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous CHnF. Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect. 0 No input capture or output compare event occurred on channel n 1 Input capture or output compare event on channel n 6 CHnIE Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE. 0 Channel n interrupt requests disabled (use for software polling) 1 Channel n interrupt requests enabled 5 MSnB Mode select B for TPM channel n. When CPWMS=0, MSnB=1 configures TPM channel n for edge-aligned PWM mode. Refer to the summary of channel mode and setup controls in Table 16-7. 4 MSnA Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for input-capture mode or output compare mode. Refer to Table 16-7 for a summary of channel mode and setup controls. Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3–2 ELSnB ELSnA Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown in Table 16-7, these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the PWM output. Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does not require the use of a pin. Table 16-7. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA X XX 00 Mode Configuration Pin not used for TPM - revert to general purpose I/O or other peripheral control MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 292 Freescale Semiconductor Timer/PWM Module (S08TPMV3) Table 16-7. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 00 01 Input capture Capture on rising edge only 01 10 Capture on falling edge only 11 Capture on rising or falling edge 01 1X Output compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned PWM X1 1 XX High-true pulses (clear output on compare) Low-true pulses (set output on compare) 10 Center-aligned PWM X1 16.3.5 Toggle output on compare High-true pulses (clear output on compare-up) Low-true pulses (set output on compare-up) TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel registers are cleared by reset. 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 R W Reset Figure 16-13. TPM Channel Value Register High (TPMxCnVH) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 R W Reset Figure 16-14. TPM Channel Value Register Low (TPMxCnVL) In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other half is read. This latching mechanism also resets MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 293 Timer/PWM Module (S08TPMV3) (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. The value read from the TPMxCnVH and TPMxCnVL registers in BDM mode is the value of these registers and not the value of their read buffer. In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. After both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of CLKSB:CLKSA bits and the selected mode, so: • If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written. • If (CLKSB:CLKSA not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the TPM counter (end of the prescaler counting). • If (CLKSB:CLKSA not = 0:0 and in EPWM or CPWM modes), then the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. The latching mechanism may be manually reset by writing to the TPMxCnSC register (whether BDM mode is active or not). This latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active even if one or both halves of the channel register are written while BDM is active. Any write to the channel registers bypasses the buffer latches and directly write to the channel register while BDM is active. The values written to the channel register while BDM is active are used for PWM & output compare operation once normal execution resumes. Writes to the channel registers while BDM is active do not interfere with partial completion of a coherency sequence. After the coherency mechanism has been fully exercised, the channel registers are updated using the buffered values written (while BDM was not active) by the user. 16.4 Functional Description All TPM functions are associated with a central 16-bit counter which allows flexible selection of the clock source and prescale factor. There is also a 16-bit modulo register associated with the main counter. The CPWMS control bit chooses between center-aligned PWM operation for all channels in the TPM (CPWMS=1) or general purpose timing functions (CPWMS=0) where each channel can independently be configured to operate in input capture, output compare, or edge-aligned PWM mode. The CPWMS control bit is located in the main TPM status and control register because it affects all channels within the TPM and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 294 Freescale Semiconductor Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and manual counter reset. 16.4.1.1 Counter Clock Source The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three possible clock sources or OFF (which effectively disables the TPM). See Table 16-4. After any MCU reset, CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA field) does not affect the values in the counter or other timer registers. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 295 Timer/PWM Module (S08TPMV3) Table 16-8. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses. In MCUs that have no PLL and FLL or the PLL and FLL are not engaged, the fixed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. When a PLL or FLL is present and engaged, a synchronizer is required between the crystal divided-by two clock source and the timer counter so counter transitions will be properly aligned to bus-clock transitions. A synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. The external clock source may be connected to any TPM channel pin. This clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the external clock can be as fast as bus clock divided by four. When the external clock source shares the TPM channel pin, this pin should not be used for other channel timing functions. For example, it would be ambiguous to configure channel 0 for input capture when the TPM channel 0 pin was also being used as the timer external clock source. (It is the user’s responsibility to avoid such settings.) The TPM channel could still be used in output compare mode for software timing functions (pin controls set not to affect the TPM channel pin). 16.4.1.2 Counter Overflow and Modulo Reset An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a software-accessible indication that the timer counter has overflowed. The enable signal selects between software polling (TOIE=0) where no hardware interrupt is generated, or interrupt-driven operation (TOIE=1) where a static hardware interrupt is generated whenever the TOF flag is equal to one. The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned PWM (CPWMS=1). In the simplest mode, there is no modulus limit and the TPM is not in CPWMS=1 mode. In this case, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When the TPM is in center-aligned PWM mode (CPWMS=1), the TOF flag gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). This corresponds to the end of a PWM period (the 0x0000 count value corresponds to the center of a period). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 296 Freescale Semiconductor Timer/PWM Module (S08TPMV3) 16.4.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL. When center-aligned PWM operation is specified, the counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up counting. Both 0x0000 and the terminal count value are normal length counts (one timer clock period long). In this mode, the timer overflow flag (TOF) becomes set at the end of the terminal-count period (as the count changes to the next lower count value). 16.4.1.4 Manual Counter Reset The main timer counter can be manually reset at any time by writing any value to either half of TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency mechanism in case only half of the counter was read before resetting the count. 16.4.2 Channel Mode Selection Provided CPWMS=0, the MSnB and MSnA control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. Choices include input capture, output compare, and edge-aligned PWM. 16.4.2.1 Input Capture Mode With the input-capture function, the TPM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input-capture channel, the TPM latches the contents of the TPM counter into the channel-value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. In input capture mode, the TPMxCnVH and TPMxCnVL registers are read only. When either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An input capture event sets a flag bit (CHnF) which may optionally generate a CPU interrupt request. While in BDM, the input capture function works as configured by the user. When an external event occurs, the TPM latches the contents of the TPM counter (which is frozen because of the BDM mode) into the channel value registers and sets the flag bit. 16.4.2.2 Output Compare Mode With the output-compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel-value registers of an output-compare channel, the TPM can set, clear, or toggle the channel pin. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 297 Timer/PWM Module (S08TPMV3) In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. The coherency sequence can be manually reset by writing to the channel status/control register (TPMxCnSC). An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request. 16.4.2.3 Edge-Aligned PWM Mode This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can be used when other channels in the same TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the value of the modulus register (TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. 0% and 100% duty cycle cases are possible. The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal (Figure 16-15). The time between the modulus overflow and the output compare is the pulse width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare forces the PWM signal high. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TPMxCHn OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 16-15. PWM Period and Pulse Width (ELSnA=0) When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle. Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL, actually write to buffer registers. In edge-aligned PWM mode, values are transferred to the corresponding timer-channel registers according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 298 Freescale Semiconductor Timer/PWM Module (S08TPMV3) the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 16.4.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output. pulse width = 2 x (TPMxCnVH:TPMxCnVL) period = 2 x (TPMxMODH:TPMxMODL); TPMxMODH:TPMxMODL=0x0001-0x7FFF If the channel-value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you do not need to generate 100% duty cycle). This is not a significant limitation. The resulting period would be much longer than required for normal applications. TPMxMODH:TPMxMODL=0x0000 is a special case that should not be used with center-aligned PWM mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF, but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle) of the CPWM signal (Figure 16-16). If ELSnA=0, a compare occurred while counting up forces the CPWM output signal low and a compare occurred while counting down forces the output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL. COUNT= 0 OUTPUT COUNT= COMPARE TPMxMODH:TPMxMODL (COUNT DOWN) OUTPUT COMPARE (COUNT UP) COUNT= TPMxMODH:TPMxMODL TPMxCHn PULSE WIDTH 2 x TPMxCnVH:TPMxCnVL PERIOD 2 x TPMxMODH:TPMxMODL Figure 16-16. CPWM Period and Pulse Width (ELSnA=0) Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin transitions are lined up at the same system clock edge. This type of PWM is also required for some types of motor drives. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 299 Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS=1. The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. In center-aligned PWM mode, the TPMxCnVH:L registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. When TPMxCNTH:TPMxCNTL=TPMxMODH:TPMxMODL, the TPM can optionally generate a TOF interrupt (at the end of this count). Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 16.5 16.5.1 Reset Overview General The TPM is reset whenever any MCU reset occurs. 16.5.2 Description of Reset Operation Reset clears the TPMxSC register which disables clocks to the TPM and disables timer overflow interrupts (TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU pins related to the TPM revert to general purpose I/O pins). 16.6 16.6.1 Interrupts General The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each time the main timer counter matches the value in the 16-bit channel value register. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 300 Freescale Semiconductor Timer/PWM Module (S08TPMV3) All TPM interrupts are listed in Table 16-9 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic. Table 16-9. Interrupt Summary Interrupt Local Enable Source Description TOF TOIE Counter overflow Set each time the timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) CHnF CHnIE Channel event An input capture or output compare event took place on channel n The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip integration time in the interrupt module so refer to the user’s guide for the interrupt module or to the chip’s complete documentation for details. 16.6.2 Description of Interrupt Operation For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt-service routine. TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1) followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event. 16.6.2.1 Timer Overflow Interrupt (TOF) Description The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system (general purpose timing functions versus center-aligned PWM operation). The flag is cleared by the two step sequence described above. 16.6.2.1.1 Normal Case Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not configured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning of counter overflow. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 301 Timer/PWM Module (S08TPMV3) 16.6.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 16.6.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.1 Input Capture Events When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge (off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described in Section 16.6.2, “Description of Interrupt Operation.” 16.6.2.2.2 Output Compare Events When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step sequence described Section 16.6.2, “Description of Interrupt Operation.” 16.6.2.2.3 PWM End-of-Duty-Cycle Events For channels configured for PWM operation there are two possibilities. When the channel is configured for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. The flag is cleared by the two-step sequence described Section 16.6.2, “Description of Interrupt Operation.” 16.7 The Differences from TPM v2 to TPM v3 1. Write to TPMxCNTH:L registers (Section 16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7] Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter (TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared in this case. 2. Read of TPMxCNTH:L registers (Section 16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL)) — In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was read before the BDM mode became active, then any read of TPMxCNTH:L registers during MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 302 Freescale Semiconductor Timer/PWM Module (S08TPMV3) BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section 16.3.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)) — In TPM v3, any read of TPMxCnVH:L registers during BDM mode returns the value of the TPMxCnVH:L register. In TPM v2, if only one byte of the TPMxCnVH:L registers was read before the BDM mode became active, then any read of TPMxCnVH:L registers during BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the value in the TPMxCnVH:L registers. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxCnSC. Instead, in this condition the TPM v2 does not clear this read coherency mechanism. 4. Write to TPMxCnVH:L registers — Input Capture Mode (Section 16.4.2.1, “Input Capture Mode) In this mode the TPM v3 does not allow the writes to TPMxCnVH:L registers. Instead, the TPM v2 allows these writes. — Output Compare Mode (Section 16.4.2.2, “Output Compare Mode) In this mode and if (CLKSB:CLKSA not = 0:0), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer at the next change of the TPM counter (end of the prescaler counting) after the second byte is written. Instead, the TPM v2 always updates these registers when their second byte is written. The following procedure can be used in the TPM v3 to verify if the TPMxCnVH:L registers were updated with the new value that was written to these registers (value in their write buffer). ... write the new value to TPMxCnVH:L; read TPMxCnVH and TPMxCnVL registers; while (the read value of TPMxCnVH:L is different from the new value written to TPMxCnVH:L) begin read again TPMxCnVH and TPMxCnVL; end ... In this point, the TPMxCnVH:L registers were updated, so the program can continue and, for example, write to TPMxC0SC without cancelling the previous write to TPMxCnVH:L registers. — Edge-Aligned PWM (Section 16.4.2.3, “Edge-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer after that the both bytes were written and when the MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 303 Timer/PWM Module (S08TPMV3) TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to $0000. — Center-Aligned PWM (Section 16.4.2.4, “Center-Aligned PWM Mode) In this mode and if (CLKSB:CLKSA not = 00), the TPM v3 updates the TPMxCnVH:L registers with the value of their write buffer after that the both bytes were written and when the TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to (TPMxMODH:L - 1). 5. Center-Aligned PWM (Section 16.4.2.4, “Center-Aligned PWM Mode) — TPMxCnVH:L = TPMxMODH:L [SE110-TPM case 1] In this case, the TPM v3 produces 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L = (TPMxMODH:L - 1) [SE110-TPM case 2] In this case, the TPM v3 produces almost 100% duty cycle. Instead, the TPM v2 produces 0% duty cycle. — TPMxCnVH:L is changed from 0x0000 to a non-zero value [SE110-TPM case 3 and 5] In this case, the TPM v3 waits for the start of a new PWM period to begin using the new duty cycle setting. Instead, the TPM v2 changes the channel output at the middle of the current PWM period (when the count reaches 0x0000). — TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4] In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting. Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting. 6. Write to TPMxMODH:L registers in BDM mode (Section 16.3.3, “TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)) In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when there is a write to TPMxSC register. 7. Update of EPWM signal when CLKSB:CLKSA = 00 In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update (it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at the next rising edge of bus clock after a write to TPMxCnSC register. The Figure 0-1 and Figure 0-2 show when the EPWM signals generated by TPM v2 and TPM v3 after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 304 Freescale Semiconductor EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxMODH:TPMxMODL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 6 7 0 1 2 ... 01 00 CLKSB:CLKSA BITS 5 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 10 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure 0-1. Generation of high-true EPWM signal by TPM v2 and v3 after the reset MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 305 Timer/PWM Module (S08TPMV3) EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxMODH:TPMxMODL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 6 7 0 1 2 ... 01 00 CLKSB:CLKSA BITS 5 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 01 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure 0-2. Generation of low-true EPWM signal by TPM v2 and v3 after the reset The following procedure can be used in TPM v3 (when the channel pin is also a port pin) to emulate the high-true EPWM generated by TPM v2 after the reset. ... configure the channel pin as output port pin and set the output pin; configure the channel to generate the EPWM signal but keep ELSnB:ELSnA as 00; configure the other registers (TPMxMODH, TPMxMODL, TPMxCnVH, TPMxCnVL, ...); configure CLKSB:CLKSA bits (TPM v3 starts to generate the high-true EPWM signal, however TPM does not control the channel pin, so the EPWM signal is not available); wait until the TOF is set (or use the TOF interrupt); enable the channel output by configuring ELSnB:ELSnA bits (now EPWM signal is available); ... MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 306 Freescale Semiconductor Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The BDC is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as CPU register modify, breakpoints, and single instruction trace commands. In the HCS08 Family, address and data bus signals are not available on external pins (not even in test modes). Debug is done through commands fed into the target MCU via the single-wire background debug interface. The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 Forcing Active Background The method for forcing active background mode depends on the specific HCS08 derivative. For the MC9S08EL32 Series and MC9S08SL16 Series, you can force active background after a power-on reset by holding the BKGD pin low as the device exits the reset condition (independent of the reset source). You can also force active background by driving BKGD low immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register. If no debug pod is connected to the BKGD pin, the MCU always resets into normal operating mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 307 Development SupportChapter 17 Development Support HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (SPI) PORT B SERIAL COMMUNICATIONS INTERFACE (SCI) INT PTB0/PIB0/SLRxD/RxD/ADP4 PTB1/PIB1/SLTxD/TxD/ADP5 PTB2/PIB2/SDA/SPSCK/ADP6 PTB3/PIB3/SCL/MOSI/ADP7 PTB4/TPM2CH1/MISO PTB5/TPM1CH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL PORT C LVD PTC0/PIC0/TPM1CH0/ADP8 PTC1/PIC1/TPM1CH1/ADP9 PTC2/PIC2/TPM1CH2/ADP10 PTC3/PIC3/TPM1CH3/ADP11 PTC4/PIC4/ADP12 PTC5/PIC5/ACMP2O/ADP13 PTC6/PIC6/ACMP2+/ADP14 PTC7/PIC7/ACMP2–/ADP15 IIC MODULE (IIC) USER EEPROM 512 bytes REAL-TIME COUNTER (RTC) USER RAM 1024 bytes OSCILLATOR (XOSC) XTAL EXTAL INTERNAL CLOCK SOURCE (ICS) VDD VSS VOLTAGE REGULATOR VDDA/ VREFH VSSA/ VREFL ON-CHIP IN-CIRCUIT EMULATOR (ICE) DEBUG MODULE (DBG) TCLK 0 4-CHANNEL TIMER/PWM 1 MODULE (TPM1) 2 3 OUT ANALOG COMPARATOR + (ACMP2) – 16-CHANNEL,10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) 16 = Not bonded to pins in 20-pin package = In 20-pin packages, VDDA/VREFH is internally connected to VDD and VSSA/VREFL is internally connected to VSS. Figure 17-1. MC9S08EL32 Block Diagram Highlighting DBG Block MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 308 Freescale Semiconductor Development SupportChapter 17 Development Support MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 309 Development Support 17.1.2 Features Features of the BDC module include: • Single pin for mode selection and background communications • BDC registers are not located in the memory map • SYNC command to determine target communications rate • Non-intrusive commands for memory access • Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from stop or wait modes • One hardware address breakpoint built into BDC • Oscillator runs in stop mode, if BDC enabled • COP watchdog disabled while in active background mode Features of the ICE system include: • Two trigger comparators: Two address + read/write (R/W) or one full address + data + R/W • Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: — Basic: A-only, A OR B — Sequence: A then B — Full: A AND B data, A AND NOT B data — Event (store data): Event-only B, A then event-only B — Range: Inside range (A ≤ address ≤ B), outside range (address < A or address > B) 17.2 Background Debug Controller (BDC) All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals. BDC commands are divided into two groups: • Active background mode commands require that the target MCU is in active background mode (the user program is not running). Active background mode commands allow the CPU registers to be read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 310 Freescale Semiconductor Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET, and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. BKGD 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 VDD Figure 17-2. BDM Tool Connector 17.2.1 BKGD Pin Description BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication of active background mode commands and data. During reset, this pin is used to select between starting in active background mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer to Section 17.2.2, “Communication Details.” If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 17.2.2, “Communication Details,” for more detail. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 311 Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug interface. 17.2.2 Communication Details The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each bit time. The external controller provides this falling edge whether data is transmitted or received. BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system. The custom serial protocol requires the debug pod to know the target BDC communication clock speed. The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source. The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 312 Freescale Semiconductor Development Support Figure 17-3 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES SYNCHRONIZATION UNCERTAINTY EARLIEST START OF NEXT BIT TARGET SENSES BIT LEVEL PERCEIVED START OF BIT TIME Figure 17-3. BDC Host-to-Target Serial Bit Timing MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 313 Development Support Figure 17-4 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 17-4. BDC Target-to-Host Serial Bit Timing (Logic 1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 314 Freescale Semiconductor Development Support Figure 17-5 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time. BDC CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE SPEEDUP PULSE TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 17-5. BDM Target-to-Host Serial Bit Timing (Logic 0) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 315 Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program. Table 17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the meaning of each command. Coding Structure Nomenclature This nomenclature is used in Table 17-1 to describe the coding structure of the BDC commands. Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / = separates parts of the command d = delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS = the contents of BDCSCR in the target-to-host direction (STATUS) CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 316 Freescale Semiconductor Development Support Table 17-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. BACKGROUND Non-intrusive 90/d Enter active background mode if enabled (ignore if ENBDM bit equals 0) READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status READ_LAST Non-intrusive E8/SS/RD Re-read byte from address just read and report status WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register GO Active BDM 08/d Go to execute the user application program starting at the address currently in the PC TRACE1 Active BDM 10/d Trace 1 user instruction at the address in the PC, then return to active background mode TAGGO Active BDM 18/d Same as GO but enable external tagging (HCS08 devices have no external tagging pin) READ_A Active BDM 68/d/RD Read accumulator (A) READ_CCR Active BDM 69/d/RD Read condition code register (CCR) READ_PC Active BDM 6B/d/RD16 Read program counter (PC) READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X) READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP) READ_NEXT Active BDM 70/d/RD Increment H:X by one then read memory byte located at H:X READ_NEXT_WS Active BDM 71/d/SS/RD Increment H:X by one then read memory byte located at H:X. Report status and data. WRITE_A Active BDM 48/WD/d Write accumulator (A) WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR) WRITE_PC Active BDM 4B/WD16/d Write program counter (PC) WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X) WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP) WRITE_NEXT Active BDM 50/WD/d Increment H:X by one, then write memory byte located at H:X WRITE_NEXT_WS Active BDM 51/WD/d/SS Increment H:X by one, then write memory byte located at H:X. Also report status. The SYNC command is a special operation that does not have a command code. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 317 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) • Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest clock in the system.) • Removes all drive to the BKGD pin so it reverts to high impedance • Monitors the BKGD pin for the sync response pulse The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16 cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128 BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 BDC Hardware Breakpoint The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the BDC module. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 318 Freescale Semiconductor Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture. The system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user’s memory map. These registers are located in the high register space to avoid using valuable direct page memory space. Most of the debug module’s functions are used during development, and user programs rarely access any of the control and status registers for the debug module. The one exception is that the debug system can provide the means to implement a form of ROM patching. This topic is discussed in greater detail in Section 17.3.6, “Hardware Breakpoints.” 17.3.1 Comparators A and B Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking circuit. Separate control bits allow you to ignore R/W for each comparator. The opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the specified address is actually executed as opposed to only being read from memory into the instruction queue. The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. Comparators are disabled temporarily during all BDC accesses. The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0 (write), the CPU’s write data bus is used. Otherwise, the CPU’s read data bus is used. The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match condition. A match can cause: • Generation of a breakpoint to the CPU • Storage of data bus values into the FIFO • Starting to store change-of-flow addresses into the FIFO (begin type trace) • Stopping the storage of change-of-flow addresses into the FIFO (end type trace) 17.3.2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it. If a trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 319 Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port. In the event-only trigger modes (see Section 17.3.5, “Trigger Modes”), 8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted so the next data value is available through the FIFO data port at DBGFL. In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow address or a change-of-flow address appears during the next two bus cycles after a trigger event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run. The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be saved in the FIFO. To use the profiling feature, a host debugger would read addresses out of the FIFO by reading DBGFH then DBGFL at regular periodic intervals. The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO. Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger can develop a profile of executed instruction addresses. 17.3.3 Change-of-Flow Information To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow information stored in the FIFO. For conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are not conditional, these events do not cause change-of-flow information to be stored in the FIFO. Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-flow information. 17.3.4 Tag vs. Force Breakpoints and Triggers Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 320 Freescale Semiconductor Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When a tag-type break request is sent to the CPU, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is set to select tag-type operation, the output from comparator A or B is qualified by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. There is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 17.3.5 Trigger Modes The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected (begin trace), or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected (end trigger). A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and clears the AF and BF flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets full. An end-trace run ends when the selected trigger event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN in DBGC. In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO stores data in the low-order eight bits of the FIFO. The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. When TRGSEL = 1 to select opcode fetch triggers, it is not necessary to use R/W in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a full mode trigger because the opcode value is normally known at a particular address. The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. Either comparator can usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request will be a tag request or a force request. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 321 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of comparator B is not used. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low half of comparator B, and R/W must match RWA if RWAEN = 1. All three conditions must be met within the same bus cycle to cause a trigger. In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the comparator A address matches. Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger event occurs each time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full. Inside Range (A ≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value in comparator A and less than or equal to the value in comparator B at the same time. Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 322 Freescale Semiconductor Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 17.4 Register Definition This section contains the descriptions of the BDC and DBG registers and control bits. Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 17.4.1 BDC Registers and Control Bits The BDC has two registers: • The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background debug controller. • The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address. These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU (so they do not have addresses and cannot be accessed by user programs). Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 323 Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 17-6. BDC Status and Control Register (BDCSCR) Table 17-2. BDCSCR Register Field Descriptions Field Description 7 ENBDM Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 BDM cannot be made active (non-intrusive commands still allowed) 1 BDM can be made active to allow active background mode commands 6 BDMACT Background Mode Active Status — This is a read-only status bit. 0 BDM not active (user application program running) 1 BDM active and waiting for serial commands 5 BKPTEN BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and BDCBKPT match register are ignored. 0 BDC breakpoint disabled 1 BDC breakpoint enabled 4 FTS Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue, the CPU enters active background mode rather than executing the tagged opcode. 0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 CLKSW Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock source. 0 Alternate BDC clock source 1 MCU bus clock MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 324 Freescale Semiconductor Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work. Whenever the host forces the target MCU into active background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting other BDC commands. 0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to active background mode 1 WSF Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the wait or stop instruction.) 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode 0 DVF Data Valid Failure Status — This status bit is not used in the MC9S08EL32 Series and MC9S08SL16 Series because it does not have any slow access memory. 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 17.4.1.2 BDC Breakpoint Match Register (BDCBKPT) This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to Section 17.2.4, “BDC Hardware Breakpoint.” 17.4.2 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 325 Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-7. System Background Debug Force Reset Register (SBDFR) Table 17-3. SBDFR Register Field Description Field Description 0 BDFR Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. 17.4.3 DBG Registers and Control Bits The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. These registers are located in the high register space of the normal memory map so they are accessible to normal application programs. These registers are rarely if ever accessed by normal user application programs with the possible exception of a ROM patching mechanism that uses the breakpoint logic. 17.4.3.1 Debug Comparator A High Register (DBGCAH) This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.2 Debug Comparator A Low Register (DBGCAL) This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.3 Debug Comparator B High Register (DBGCBH) This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. 17.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 326 Freescale Semiconductor Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information. 17.4.3.6 Debug FIFO Low Register (DBGFL) This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect. Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused). When reading 8-bit words out of the FIFO, simply read DBGFL repeatedly to get successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in this case. Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled or ARMF is cleared) because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from the FIFO. Reading DBGFL while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the FIFO. By reading DBGFH then DBGFL periodically, external host software can develop a profile of program execution. After eight reads from the FIFO, the ninth read will return the information that was stored as a result of the first read. To use the profiling feature, read the FIFO eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. The information stored into the FIFO on reads of DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 327 Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 17-8. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure. 0 DBG disabled 1 DBG enabled 6 ARM Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually stopped by writing 0 to ARM or to DBGEN. 0 Debugger not armed 1 Debugger armed 5 TAG Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit has no meaning or effect. 0 CPU breaks requested as force type requests 1 CPU breaks requested as tag type requests 4 BRKEN Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of CPU break requests. 0 CPU break requests not enabled 1 Triggers cause a break request to the CPU 3 RWA R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A. 0 Comparator A can only match on a write cycle 1 Comparator A can only match on a read cycle 2 RWAEN Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match. 0 R/W is not used in comparison A 1 R/W is used in comparison A 1 RWB R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B. 0 Comparator B can match only on a write cycle 1 Comparator B can match only on a read cycle 0 RWBEN Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match. 0 R/W is not used in comparison B 1 R/W is used in comparison B MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 328 Freescale Semiconductor Development Support 17.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 17-9. Debug Trigger Register (DBGT) Table 17-5. DBGT Register Field Descriptions Field Description 7 TRGSEL Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match address is actually executed. 0 Trigger on access to compare address (force) 1 Trigger if opcode at compare address is executed (tag) 6 BEGIN Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 Data stored in FIFO until trigger (end trace) 1 Trigger initiates data storage (begin trace) 3:0 TRG[3:0] Select Trigger Mode — Selects one of nine triggering modes, as described below. 0000 A-only 0001 A OR B 0010 A Then B 0011 Event-only B (store data) 0100 A then event-only B (store data) 0101 A AND B data (full mode) 0110 A AND NOT B data (full mode) 0111 Inside range: A ≤ address ≤ B 1000 Outside range: address < A or address > B 1001 – 1111 (No trigger) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 329 Development Support 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-10. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming. 0 Comparator A has not matched 1 Comparator A match 6 BF Trigger Match B Flag — BF is cleared at the start of a debug run and indicates whether a trigger match B condition was met since arming. 0 Comparator B has not matched 1 Comparator B match 5 ARMF Arm Flag — While DBGEN = 1, this status bit is a read-only image of ARM in DBGC. This bit is set by writing 1 to the ARM control bit in DBGC (while DBGEN = 1) and is automatically cleared at the end of a debug run. A debug run is completed when the FIFO is full (begin trace) or when a trigger event is detected (end trace). A debug run can also be ended manually by writing 0 to ARM or DBGEN in DBGC. 0 Debugger not armed 1 Debugger armed 3:0 CNT[3:0] FIFO Valid Count — These bits are cleared at the start of a debug run and indicate the number of words of valid data in the FIFO at the end of a debug run. The value in CNT does not decrement as data is read out of the FIFO. The external debug host is responsible for keeping track of the count as information is read out of the FIFO. 0000 Number of valid words in FIFO = No valid data 0001 Number of valid words in FIFO = 1 0010 Number of valid words in FIFO = 2 0011 Number of valid words in FIFO = 3 0100 Number of valid words in FIFO = 4 0101 Number of valid words in FIFO = 5 0110 Number of valid words in FIFO = 6 0111 Number of valid words in FIFO = 7 1000 Number of valid words in FIFO = 8 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 330 Freescale Semiconductor Appendix A Electrical Characteristics A.1 Introduction This section contains the most accurate electrical and timing information for the MC9S08EL32 Series and MC9S08SL16 Series of microcontrollers available at the time of publication. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. A.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 331 Appendix A Electrical Characteristics Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +5.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ± 25 mA Tstg –55 to 150 °C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. For example, if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). A.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD is very small. Table A-3. Thermal Characteristics Num C Rating Symbol Value Unit Operating temperature range (packaged) 1 — Temperature Code M Temperature Code V –40 to 125 TA Temperature Code C –40 to 105 °C –40 to 85 Thermal resistance1,2 Single-layer board 2 D 20-pin TSSOP θJA 28-pin TSSOP 113 °C/W 91 Thermal resistance1,2 Four-layer board 3 D 4 D 20-pin TSSOP θJA 28-pin TSSOP Maximum junction temperature 73 °C/W 58 TJ 135 °C MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 332 Freescale Semiconductor Appendix A Electrical Characteristics 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. A-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O VSS 0 — 100 mA 5V 0.65 x VDD — — V 3V 0.7 x VDD — — C voltage D Output low current Max total IOL for all ports P Input high voltage; all digital inputs C IOLT VIH MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 334 Freescale Semiconductor Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C 7 Characteristic P Input low voltage; all digital inputs Condition Min Typ1 Max Unit VIL 5V — — 0.35 x VDD V 3V — — 0.35 x VDD C 8 C Input hysteresis 9 P Input leakage current (per pin) Vhys 0.06 x VDD V |IIn| VIn = VDD or VSS — — 1 μA |IOZ| VIn = VDD or VSS — — 1 μA VIn = VDD or VSS — — 2 μA 17 37 52 kΩ 17 37 52 kΩ VIN > VDD 0 — 2 mA VIN < VSS, 0 — –0.2 mA Total MCU limit, includes VIN > VDD 0 — 25 mA sum of all stressed pins VIN < VSS, 0 — –5 mA CIn — — 8 pF VRAM — 0.6 1.0 V Hi-Z (off-state) leakage current (per pin) 10 Symbol P input/output port pins PTB6/SDA/XTAL, RESET Pullup or Pulldown2 resistors; when enabled 11 I/O pins RPU,RPD P 3 C RESET RPU DC injection current 4, 5, 6, 7 Single pin limit 12 D IIC 13 D Input Capacitance, all pins 14 D RAM retention voltage 8 15 D POR re-arm voltage VPOR 0.9 1.4 2.0 V 16 D POR re-arm time9 tPOR 10 — — μs 17 Low-voltage detection threshold — P high range VDD falling VDD rising 3.9 4.0 4.0 4.1 4.1 4.2 V 18 Low-voltage detection threshold — P low range VDD falling VDD rising 2.48 2.54 2.56 2.62 2.64 2.70 V 19 Low-voltage warning threshold — P high range 1 VDD falling VDD rising 4.5 4.6 4.6 4.7 4.7 4.8 V 20 Low-voltage warning threshold — P high range 0 VDD falling VDD rising 4.2 4.3 4.3 4.4 4.4 4.5 V 21 Low-voltage warning threshold P low range 1 VDD falling VDD rising 2.84 2.90 2.92 2.98 3.00 3.06 V 22 Low-voltage warning threshold — P low range 0 VDD falling VDD rising 2.66 2.72 2.74 2.80 2.82 2.88 V VLVD1 VLVD0 VLVW3 VLVW2 VLVW1 VLVW0 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 335 Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max 5V — 100 — 3V — 60 — 1.18 1.202 1.21 23 T Low-voltage inhibit reset/recover hysteresis Vhys 24 P Bandgap Voltage Reference10 VBG Unit mV V 1 Typical values are measured at 25°C. Characterized, not tested When a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors. 3 The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally on the pin. 4 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. For example, if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 5 All functional non-supply pins except RESET are internally clamped to V SS and VDD. 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 The RESET pin does not have a clamp diode to V . Do not drive this pin above V . DD DD 8 Maximum is highest voltage that POR is guaranteed. 9 Simulated, not tested. 10 Factory trimmed at V DD = 5.0 V, Temp = 25°C. 2 2 1.0 125°C 25°C –40°C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@25mA Max 0.8V@5mA 0.6 0.4 0.2 0 5 10 15 IOL (mA) a) VDD = 5V, High Drive 20 25 0 0 2 4 6 IOL (mA) b) VDD = 3V, High Drive 8 10 Figure A-1. Typical VOL vs IOL, High Drive Strength MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 336 Freescale Semiconductor Appendix A Electrical Characteristics 1.0 2 125°C 25°C –40°C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.2 0 1 2 3 IOL (mA) a) VDD = 5V, Low Drive 4 0 5 0 0.4 0.8 1.2 IOL (mA) b) VDD = 3V, Low Drive 1.6 2.0 Figure A-2. Typical VOL vs IOL, Low Drive Strength 1.0 2 125°C 25°C –40°C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@20mA Max 0.8V@5mA 0.6 0.4 0.2 0 –5 –10 –15 –20 IOH (mA) a) VDD = 5V, High Drive –25 0 0 –2 –4 –6 –8 IOH (mA) b) VDD = 3V, High Drive –10 Figure A-3. Typical VDD – VOH vs IOH, High Drive Strength MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 337 Appendix A Electrical Characteristics 1.0 2 125°C 25°C –40°C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.2 0 –1 –2 –3 IOH (mA) a) VDD = 5V, Low Drive –4 –5 0 0 –0.4 –0.8 –1.2 –1.6 IOH (mA) b) VDD = 3V, Low Drive –2.0 Figure A-4. Typical VDD – VOH vs IOH, Low Drive Strength A.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table A-7. Supply Current Characteristics Num C C 1 2 3 Parameter Symbol 3 Run supply current measured at (CPU clock = 4 MHz, fBus = 2 MHz) RIDD C Run supply current3 measured at (CPU clock = 16 MHz, fBus = 8 MHz) RIDD C 4 C P C Run supply current measured at (CPU clock = 32 MHz, fBus = 16MHz) RIDD VDD (V) Typ1 Max2 5 1.7 2.5 3 1.7 2.4 5 5.1 8.5 3 5.0 8.4 5 7.8 15 3 7.7 14 Unit mA mA mA Stop3 mode supply current 4 C –40°C (C, V, & M suffix) 1.0 – P 25°C (All parts) 1.0 – 5 P 85°C (C suffix only) 6.8 40.0 P5 105°C (V suffix only) 15.6 50.0 P5 125°C (M suffix only) 42 75.0 C –40°C (C,V, & M suffix) 0.9 – P 25°C (All parts) 0.9 – 5 P 85°C (C suffix only) 6.0 35.0 P5 105°C (V suffix only) 13.1 45.0 P5 125°C (M suffix only) 38 70.0 5 S3IDD 3 μA μA MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 338 Freescale Semiconductor Appendix A Electrical Characteristics Table A-7. Supply Current Characteristics (continued) Num C Parameter Symbol VDD (V) Typ1 Max2 Unit Stop2 mode supply current 5 6 7 8 1 2 3 4 5 6 7 C –40°C (C,M, & V suffix) 0.9 – P 25°C (All parts) 0.9 – P5 85°C (C suffix only) 5.0 40.0 P5 105°C (V suffix only) 11.0 50.0 P5 125°C (M suffix only) 29.1 65.0 C –40°C (C,M, & V suffix) 0.9 – P 25°C (All parts) 0.9 – P5 85°C (C suffix only) 4.2 35.0 P5 105°C (V suffix only) 8.8 45.0 P5 125°C (M suffix only) 25 60.0 5 300 500 nA 3 300 500 nA 5 110 180 μA 3 90 160 μA 5,3 5 8 μA C C C RTC adder to stop2 or stop36 LVD adder to stop3 (LVDE = LVDSE = 1) Adder to stop3 for oscillator (EREFSTEN =1) enabled7 5 S2IDD 3 S23IDDRTI S3IDDLVD S3IDDOSC μA μA Typical values for specs 1, 2, 3, 6, 7, and 8 are based on characterization data at 25°C. See Figure A-5 through Figure A-7 for typical curves across temperature and voltage. Max values in this column apply for the full operating temperature range of the device unless otherwise noted. All modules except ADC active, ICS configured for FBELP, and does not include any dc loads on port pins All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins Stop currents are tested in production for 25°C on all parts. Tests at other temperatures depend upon the part number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficient data has been collectd and is approved. Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low power mode (HGO = 0). MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 339 Appendix A Electrical Characteristics 12 FEI FBELP 10 Run IDD (mA) 8 6 4 2 0 0 1 2 4 8 20 16 fbus (MHz) Figure A-5. Typical Run IDD vs. Bus Frequency (VDD = 5V) 6 RUN 5 Run IDD (μA) 4 3 WAIT 2 1 0 –40 0 25 Temperature (°C) 85 105 125 Figure A-6. Typical Run and Wait IDD vs. Temperature (VDD = 5V; fbus = 8MHz) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 340 Freescale Semiconductor Appendix A Electrical Characteristics 60 STOP2 STOP3 STOP IDD (μA) 50 40 30 20 10 0 –40 0 25 Temperature (°C) 85 105 125 Figure A-7. Typical Stop IDD vs. Temperature (VDD = 5V) A.8 External Oscillator (XOSC) Characteristics Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Num Symbol Min Typ1 Max Unit flo 32 — 38.4 kHz fhi 1 — 5 MHz High range (RANGE = 1, HGO = 1) FBELP mode fhi-hgo 1 — 16 MHz High range (RANGE = 1, HGO = 0) FBELP mode fhi-lp 1 — 8 MHz C Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) 1 2 C — High range (RANGE = 1) FEE or FBE mode 2 Load capacitors C1, C2 See crystal or resonator manufacturer’s recommendation. Feedback resistor 3 — Low range (32 kHz to 100 kHz) RF — 10 — — 1 — Low range, low gain (RANGE = 0, HGO = 0) — 0 — Low range, high gain (RANGE = 0, HGO = 1) — 100 — High range, low gain (RANGE = 1, HGO = 0) — 0 — ≥ 8 MHz — 0 0 4 MHz — 0 10 1 MHz — 0 20 High range (1 MHz to 16 MHz) MΩ Series resistor 4 — High range, high gain (RANGE = 1, HGO = 1) RS kΩ MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 341 Appendix A Electrical Characteristics Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) (continued) Num C Symbol Min Typ1 Max t CSTL-LP — 200 — CSTL-HGO — 400 — t CSTH-LP — 5 — CSTH-HGO — 20 — fextal 0.03125 — 5 MHz 0 — 40 MHz Rating Crystal start-up time Low range, low gain (RANGE = 0, HGO = 0) 5 T Unit 3 Low range, high gain (RANGE = 0, HGO = 1) t High range, low gain (RANGE = 1, HGO = 0)4 High range, high gain (RANGE = 1, HGO = 1) 4 t ms Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) 6 T FEE or FBE mode 2 FBELP mode 1 Typical data was characterized at 5.0 V, 25°C or is recommended value. The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 Characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 4 4 MHz crystal 2 MCU EXTAL XTAL RS RF C1 A.9 Crystal or Resonator C2 Internal Clock Source (ICS) Characteristics Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit Internal reference frequency — factory trimmed at VDD = 5 V and temperature = 25°C fint_ft — 31.25 — kHz 1 P 2 T Internal reference frequency — untrimmed1 fint_ut 25 36 41.66 kHz P Internal reference frequency — trimmed fint_t 31.25 — 39.0625 kHz D Internal reference startup time tirefst — 55 100 μs fdco_ut 25.6 36.86 42.66 MHz fdco_t 32 — 40 MHz 3 4 untrimmed1 DCO output frequency range — value provided for reference: fdco_ut = 1024 x fint_ut 5 — 6 D DCO output frequency range — trimmed 7 Resolution of trimmed DCO output frequency at fixed D voltage and temperature (using FTRIM) Δfdco_res_t — ± 0.1 ± 0.2 %fdco 8 D Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Δfdco_res_t — ± 0.2 ± 0.4 %fdco MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 342 Freescale Semiconductor Appendix A Electrical Characteristics Table A-9. ICS Frequency Specifications (continued) (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit 9 D Total deviation of trimmed DCO output frequency over voltage and temperature Δfdco_t — + 0.5 – 1.0 ±2 %fdco 10 D Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0°C to 70 °C Δfdco_t — ± 0.5 ±1 %fdco 11 D FLL acquisition time 2 1 ms 0.2 %fdco 12 tacquire D DCO output clock long term jitter (over 2 ms interval) 3 CJitter — 0.02 1 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. Deviation from Trimmed Frequency 2 +2% +1% 0 –1% –2% –40 0 25 Temperature (°C) 85 125 105 Figure A-8. Typical Frequency Deviation vs Temperature (ICS Trimmed to 16MHz bus@25°C, 5V, FEI)1 A.10 Analog Comparator (ACMP) Electricals Table A-10. Analog Comparator Electrical Specifications Num C 1 — 2 C/T 3 D Rating Symbol Min Typical Max Unit VDD 2.7 — 5.5 V Supply current (active) IDDAC — 20 35 μA Analog input voltage VAIN VSS – 0.3 — VDD V Supply voltage 1. Based on the average of several hundred units from a typical characterization lot. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 343 Appendix A Electrical Characteristics Table A-10. Analog Comparator Electrical Specifications (continued) Num C Rating 4 D Analog input offset voltage 5 D Analog Comparator hysteresis 6 D 7 D A.11 Symbol Min Typical Max Unit 20 40 mV VAIO VH 3.0 6.0 20.0 mV Analog input leakage current IALKG — — 1.0 μA Analog Comparator initialization delay tAINIT — — 1.0 μs ADC Characteristics Table A-11. ADC Operating Conditions Symb Min Typ1 Max Unit VDDAD 2.7 — 5.5 V Input Voltage VADIN VREFL — VREFH V 3 Input Capacitance CADIN — 4.5 5.5 pF 4 Input Resistance RADIN — 3 5 kΩ — — — — 5 10 — — 10 0.4 — 8.0 0.4 — 4.0 Num Characteristic 1 Supply voltage 2 5 Analog Source Resistance 6 7 8 1 Conditions Absolute 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) ADC Conversion Clock Freq. High Speed (ADLPC=0) Low Power (ADLPC=1) kΩ RAS fADCK Comment External to MCU MHz Typical values assume VDDAD = VDD = 5.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 344 Freescale Semiconductor Appendix A Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS – CAS + – RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure A-9. ADC Input Impedance Equivalency Diagram Table A-12. ADC Characteristics C Symb Min Typ1 Max Unit Comment ADLPC=1 ADLSMP=1 ADCO=1 T IDD + IDDAD — 133 — μA ADC current only ADLPC=1 ADLSMP=0 ADCO=1 T IDD + IDDAD — 218 — μA ADC current only ADLPC=0 ADLSMP=1 ADCO=1 T IDD + IDDAD — 327 — μA ADC current only ADLPC=0 ADLSMP=0 ADCO=1 P IDD + IDDAD — 0.582 1 mA ADC current only High speed (ADLPC=0) P fADACK 2 3.3 5 MHz 1.25 2 3.3 tADACK = 1/fADACK Characteristic Conditions Supply current ADC asynchronous clock source Low power (ADLPC=1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 345 Appendix A Electrical Characteristics Table A-12. ADC Characteristics (continued) Characteristic Conditions C Symb Min Typ1 Max Unit Comment Conversion time (including sample time) Short sample (ADLSMP=0) D tADC — 20 — — 40 — ADCK cycles — 3.5 — See ADC Chapter for conversion time variances — 23.5 — — ±1 ±2.5 — ±0.5 ±1 — ±.5 ±3.5 — ±0.7 ±1.5 — ±0.5 ±1.0 — ±0.3 ±0.5 Long sample (ADLSMP=1) Short sample (ADLSMP=0) D Sample time tADS Long sample (ADLSMP=1) ADCK cycles 28-pin packages only 10 bit mode Total unadjusted error (includes quantization) P ETUE 8 bit mode 20-pin packages only 10 bit mode P ETUE 8 bit mode 10-bit mode Differential Non-Linearity LSB2 P DNL 8-bit mode LSB2 LSB2 Monotonicity and No-Missing-Codes guaranteed Integral non-linearity 10-bit mode T INL 8-bit mode — ±0.5 ±1.0 — ±0.3 ±0.5 — ±0.5 ±1.5 — ±0.5 ±0.5 — ±1.5 ±2.5 — ±0.5 ±0.7 0 ±0.5 ±1 0 ±0.5 ±0.5 0 ±1.0 ±1.5 0 ±0.5 ±0.5 — — ±0.5 — — ±0.5 0 ±0.2 ±2.5 0 ±0.1 ±1 LSB2 28-pin packages only 10-bit mode P EZS 8-bit mode LSB2 Zero-scale error 20-pin packages only 10-bit mode P EZS 8-bit mode LSB2 28-pin packages only 10-bit mode T EFS 8-bit mode LSB2 Full-scale error 20-pin packages only 10-bit mode T EFS 8-bit mode 10-bit mode D Quantization error EQ 8-bit mode 10-bit mode Input leakage error 8-bit mode D EIL LSB2 LSB2 LSB2 Pad leakage3 * RAS MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 346 Freescale Semiconductor Appendix A Electrical Characteristics Table A-12. ADC Characteristics (continued) Characteristic Conditions Temp sensor slope -40°C to 25°C Temp sensor voltage 25°C C Symb Min Typ1 Max Unit D m — 3.266 — mV/°C — 3.638 — — 1.396 — 25°C to 125°C D VTEMP25 Comment V 1 Typical values assume VDD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Based on input pad leakage current. Refer to pad electricals. A.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. A.12.1 Control Timing Table A-13. Control Timing Symbol Min Typ1 Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz D Internal low power oscillator period tLPO 800 1500 μs 3 D External reset pulse width2 textrst 100 — ns 4 D Reset low drive3 trstdrv 66 x tcyc — ns 5 D Pin interrupt pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 x tcyc — — ns Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 40 75 — — Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 11 35 — — Num C 1 D 2 6 Rating ns C ns 1 Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of tcyc. After POR reset, the bus clock frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 125°C. 2 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 347 Appendix A Electrical Characteristics textrst RESET PIN Figure A-10. Reset Timing tIHIL Pin Interrupts Pin Interrupts tILIH Figure A-11. Pin Interrupt Timing A.12.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14. TPM Input Timing Num C 1 — 2 Rating Symbol Min Max Unit External clock frequency (1/tTCLK) fTCLK dc fBus/4 MHz — External clock period tTCLK 4 — tcyc 3 — External clock high time tclkh 1.5 — tcyc 4 — External clock low time tclkl 1.5 — tcyc 5 — Input capture pulse width tICPW 1.5 — tcyc tTCLK tclkh TCLK tclkl Figure A-12. Timer External Clock MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 348 Freescale Semiconductor Appendix A Electrical Characteristics tICPW TPMCHn TPMCHn tICPW Figure A-13. Timer Input Capture Pulse A.12.3 SPI Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system. Table A-15. SPI Electrical Characteristic Num1 C 1 D 2 3 4 5 6 7 D D D D D D Rating2 Symbol Min Max Unit Master Slave tSCK tSCK 2 4 2048 — tcyc tcyc Master Slave tLead tLead — 1/2 1/2 — tSCK tSCK Master Slave tLag tLag — 1/2 1/2 — tSCK tSCK Clock (SPSCK) high time Master and Slave tSCKH 1/2 tSCK – 25 — ns Clock (SPSCK) low time Master and Slave tSCKL 1/2 tSCK – 25 — ns Master Slave tSI(M) tSI(S) 30 30 — — ns ns Master Slave tHI(M) tHI(S) 30 30 — — ns ns tA 0 40 ns tdis — 40 ns tSO tSO — — 25 25 ns ns Cycle time Enable lead time Enable lag time Data setup time (inputs) Data hold time (inputs) D Access time, slave3 9 D 4 Disable time, slave 10 D Data setup time (outputs) Master Slave 8 MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 349 Appendix A Electrical Characteristics Table A-15. SPI Electrical Characteristic (continued) Num1 C 11 D 12 D Rating2 Symbol Min Max Unit Master Slave tHO tHO –10 –10 — — ns ns Master Slave fop fop fBus/2048 dc 55 fBus/4 MHz Data hold time (outputs) Operating frequency 1 Refer to Figure A-14 through Figure A-17. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 5 Maximum baud rate must be limited to 5 MHz due to input filter characteristics. 2 SS1 (OUTPUT) 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 10 MOSI (OUTPUT) 3 1 2 SCK (CPOL = 0) (OUTPUT) BIT 6 . . . 1 LSB IN 11 10 MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-14. SPI Master Timing (CPHA = 0) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 350 Freescale Semiconductor Appendix A Electrical Characteristics SS(1) (OUTPUT) 1 3 2 SCK (CPOL = 0) (OUTPUT) 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN(2) BIT 6 . . . 1 LSB IN 11 10 MOSI (OUTPUT) MSB OUT(2) BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-15. SPI Master Timing (CPHA = 1) SS (INPUT) 3 1 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) 9 11 10 MSB OUT BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-16. SPI Slave Timing (CPHA = 0) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 351 Appendix A Electrical Characteristics SS (INPUT) 3 1 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 10 MISO (OUTPUT) SEE NOTE 11 SLAVE MSB OUT 6 8 MOSI (INPUT) 9 BIT 6 . . . 1 SLAVE LSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure A-17. SPI Slave Timing (CPHA = 1) A.13 Flash and EEPROM Specifications This section provides details about program/erase times and program-erase endurance for the Flash and EEPROM memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table A-16. Flash Characteristics Num C 1 — 2 — Characteristic Symbol Min Supply voltage for program/erase Vprog/erase Supply voltage for read operation 1 3 — Internal FCLK frequency 4 — Internal FCLK period (1/fFCLK) 5 6 7 8 — — — — Byte program time (random Byte program time (burst location)2 mode)2 Typical Max Unit 2.7 5.5 V VRead 2.7 5.5 V fFCLK 150 200 kHz tFcyc 5 6.67 μs tprog 9 tFcyc tBurst 4 tFcyc Page erase time2 tPage 4000 tFcyc Mass erase time2 tMass 20,000 tFcyc endurance3 9 C Program/erase TL to TH = –40°C to +125°C T = 25°C nFLPE 10,000 — 100,000 — — cycles MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 352 Freescale Semiconductor Appendix A Electrical Characteristics Table A-16. Flash Characteristics (continued) Num 10 11 C Characteristic C EEPROM Program/erase endurance3 TL to TH = –40°C to + 0°C TL to TH = 0°C to + 125°C T = 25°C C Data retention4 Symbol Min nEEPE 10,000 50,000 tD_ret 15 Typical Max Unit cycles 100,000 — — — 100 — years 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for Flash is based upon the intrinsic bit cell performance. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 2 A.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. A.14.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table A-17. Radiated Emissions, Electric Field Parameter Radiated emissions, electric field Symbol VRE_TEM Conditions VDD = 5.0V TA = +25oC package type 28 TSSOP Frequency fOSC/fBUS Level1 (Max) 0.15 – 50 MHz 11 50 – 150 MHz 12 Unit dBμV 150 – 500 MHz 500 – 1000 MHz 4MHz crystal 20MHz bus 3 −10 IEC Level N/A — SAE Level 2 — MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 353 Appendix A Electrical Characteristics 1 Data based on qualification test results. A.14.2 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table A-18. Table A-18. Conducted Susceptibility, EFT/B Parameter Symbol Conducted susceptibility, electrical fast transient/burst (EFT/B) 1 VCS_EFT Conditions VDD = 5.0V TA = +25oC 28 TSSOP package type fOSC/fBUS 4MHz crystal 20MHz bus Result Amplitude1 (Min) A N/A B ±300 – ±3700 C N/A D N/A E −3800 Unit V Data based on qualification test results. Not tested in production. The susceptibility performance classification is described in Table A-19. Table A-19. Susceptibility Performance Classification Result Performance Criteria A No failure The MCU performs as designed during and after exposure. B Self-recovering failure C Soft failure The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. D Hard failure The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. E Damage The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 354 Freescale Semiconductor Appendix B Ordering Information and Mechanical Drawings Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08EL32 Series and MC9S08SL16 Series devices. Table B-1. Devices in the MC9S08EL32 Series and MC9S08SL16 Series Memory Device Number1 FLASH 1 2 B.1.1 MC9S08EL32 32,768 MC9S08EL16 16,384 MC9S08SL16 16,384 MC9S08SL8 8,192 Available Packages2 RAM EEPROM 1024 512 512 256 28-TSSOP, 20-TSSOP See Table 1-1 for a complete description of modules included on each device. See Table B-2 for package information. Device Numbering Scheme This device uses a smart numbering system. Refer to the following diagram to understand what each element of the device number represents. S 9 S08 EL n E1 C xx R Tape and Reel Suffix (optional) - R = Tape and Reel Status - S = Auto Qualified Package Designator Two letter descriptor (refer to Table B-2). Main Memory Type - 9 = Flash-based Temperature Option - C = –40 to 85 °C - V = –40 to 105 °C - M = –40 to 125 °C Core Family - EL or SL Memory Size - 32 Kbytes - 16 Kbytes Mask Set Identifier — this field only appears in “Auto Qualified” part numbers - Alpha character references wafer fab. - Numeric character identifies mask. Figure B-1. MC9S08EL32 and MC9S08SL16 Device Numbering Scheme MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 355 Appendix B Ordering Information and Mechanical Drawings B.2 Mechanical Drawings The latest package outline drawings are available on the product summary pages on http://www.freescale.com. Table B-2 lists the document numbers per package type. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. Table B-2. Package Descriptions Pin Count Type Abbreviation Designator Document No. 28 Thin shrink small outline package TSSOP TL 98ARS23923W 20 Thin shrink small outline package TSSOP TJ 98ASH70169A MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3 356 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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