MC9S08GB60
MC9S08GB32
MC9S08GT60
MC9S08GT32
MC9S08GT16
Data Sheet
HCS08
Microcontrollers
MC9S08GB60/D
Rev. 2.3
12/2004
freescale.com
MC9S08GB/GT Data Sheet
Covers: MC9S08GB60
MC9S08GB32
MC9S08GT60
MC9S08GT32
MC9S08GT16
MC9S08GB60
Rev. 2.3
12/2004
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
1.0
4/25/2003
Description of Changes
Initial release
1.1
Electricals change, appendix A only
1.2
Electricals change, appendix A only
1.3
10/2/2003
Added module version table; clarifications
1.4
10/29/2003
Fixed typos and made corrections and clarifications
1.5
11/12/2003
Added 1-MHz IDD values to Electricals, appendix A
2
2/10/2004
Changed format of register names to enable reuse of code (from SCIBD to SCI1BD, even when
only one instance of a module on a chip)
Added new device: MC9S08GT16 to book. Added new 48-pin QFN package to book. BKGDPE
description in Section 5 — changed PTD0 to PTG0. Changed typo in CPU section that listed
MOV instruction as being 6 cycles instead of 5 (Table 8-2).
2.2
9/2/2004
Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5;
updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1;
updated ICG electricals Table A-9 and added a figure
12/01/2004
Minor changes to Table 7-4, Table 7-5, Table A-9;
Clarifications in Section 11.10.6, “SCI x Control Register 3 (SCIxC3)”, Section 11.7, “Interrupts
and Status Flags”, Section 11.8.1, “8- and 9-Bit Data Modes”, PTG availability in 48-pin
package (see Table 2-2)
2.3
This product incorporates SuperFlash® technology licensed from SST.
Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC9S08GB/GT Data Sheet, Rev. 2.3
4
Freescale Semiconductor
List of Chapters
Chapter 1
Introduction.............................................................................. 17
Chapter 2
Pins and Connections ............................................................. 23
Chapter 3
Modes of Operation ................................................................. 33
Chapter 4
Memory ..................................................................................... 39
Chapter 5
Resets, Interrupts, and System Configuration ..................... 61
Chapter 6
Parallel Input/Output ............................................................... 77
Chapter 7
Internal Clock Generator (ICG) Module ................................. 97
Chapter 8
Central Processor Unit (CPU)............................................... 125
Chapter 9
Keyboard Interrupt (KBI) Module ......................................... 145
Chapter 10
Timer/PWM (TPM) Module..................................................... 151
Chapter 11
Serial Communications Interface (SCI) Module.................. 167
Chapter 12
Serial Peripheral Interface (SPI) Module.............................. 187
Chapter 13
Inter-Integrated Circuit (IIC) Module .................................... 203
Chapter 14
Analog-to-Digital Converter (ATD) Module ......................... 219
Chapter 15
Development Support ........................................................... 235
Appendix A
Electrical Characteristics...................................................... 259
Appendix B
Ordering Information and Mechanical Drawings................ 281
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
5
Contents
Section Number
Title
Page
Chapter 1
Introduction
1.1
1.2
1.3
1.4
Overview .........................................................................................................................................17
Features ...........................................................................................................................................17
1.2.1 Standard Features of the HCS08 Family .........................................................................17
1.2.2 Features of MC9S08GB/GT Series of MCUs .................................................................17
1.2.3 Devices in the MC9S08GB/GT Series ............................................................................18
MCU Block Diagrams .....................................................................................................................19
System Clock Distribution ..............................................................................................................21
Chapter 2
Pins and Connections
2.1
2.2
2.3
Introduction .....................................................................................................................................23
Device Pin Assignment ...................................................................................................................23
Recommended System Connections ...............................................................................................26
2.3.1 Power ...............................................................................................................................28
2.3.2 Oscillator ..........................................................................................................................28
2.3.3 Reset ................................................................................................................................28
2.3.4 Background / Mode Select (PTG0/BKGD/MS) ..............................................................29
2.3.5 General-Purpose I/O and Peripheral Ports .......................................................................29
2.3.6 Signal Properties Summary .............................................................................................31
Chapter 3
Modes of Operation
3.1
3.2
3.3
3.4
3.5
3.6
Introduction .....................................................................................................................................33
Features ...........................................................................................................................................33
Run Mode ........................................................................................................................................33
Active Background Mode ................................................................................................................33
Wait Mode .......................................................................................................................................34
Stop Modes ......................................................................................................................................34
3.6.1 Stop1 Mode ......................................................................................................................35
3.6.2 Stop2 Mode ......................................................................................................................35
3.6.3 Stop3 Mode ......................................................................................................................36
3.6.4 Active BDM Enabled in Stop Mode ................................................................................36
3.6.5 LVD Enabled in Stop Mode .............................................................................................37
3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................37
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
7
Section Number
Title
Page
Chapter 4
Memory
4.1
4.2
4.3
4.4
4.5
4.6
MC9S08GB/GT Memory Map .......................................................................................................39
4.1.1 Reset and Interrupt Vector Assignments ..........................................................................39
Register Addresses and Bit Assignments ........................................................................................41
RAM ................................................................................................................................................46
FLASH ............................................................................................................................................46
4.4.1 Features ............................................................................................................................47
4.4.2 Program and Erase Times ................................................................................................47
4.4.3 Program and Erase Command Execution ........................................................................48
4.4.4 Burst Program Execution .................................................................................................49
4.4.5 Access Errors ...................................................................................................................50
4.4.6 FLASH Block Protection .................................................................................................51
4.4.7 Vector Redirection ...........................................................................................................52
Security ............................................................................................................................................52
FLASH Registers and Control Bits .................................................................................................53
4.6.1 FLASH Clock Divider Register (FCDIV) .......................................................................54
4.6.2 FLASH Options Register (FOPT and NVOPT) ..............................................................55
4.6.3 FLASH Configuration Register (FCNFG) .......................................................................56
4.6.4 FLASH Protection Register (FPROT and NVPROT) ......................................................56
4.6.5 FLASH Status Register (FSTAT) .....................................................................................58
4.6.6 FLASH Command Register (FCMD) ..............................................................................59
Chapter 5
Resets, Interrupts, and System Configuration
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction .....................................................................................................................................61
Features ...........................................................................................................................................61
MCU Reset ......................................................................................................................................61
Computer Operating Properly (COP) Watchdog .............................................................................62
Interrupts .........................................................................................................................................62
5.5.1 Interrupt Stack Frame ......................................................................................................63
5.5.2 External Interrupt Request (IRQ) Pin ..............................................................................64
5.5.2.1 Pin Configuration Options ..............................................................................64
5.5.2.2 Edge and Level Sensitivity ..............................................................................65
5.5.3 Interrupt Vectors, Sources, and Local Masks ..................................................................65
Low-Voltage Detect (LVD) System ................................................................................................67
5.6.1 Power-On Reset Operation ..............................................................................................67
5.6.2 LVD Reset Operation .......................................................................................................67
5.6.3 LVD Interrupt Operation .................................................................................................67
5.6.4 Low-Voltage Warning (LVW) ..........................................................................................67
Real-Time Interrupt (RTI) ...............................................................................................................67
MC9S08GB/GT Data Sheet, Rev. 2.3
8
Freescale Semiconductor
Section Number
5.8
Title
Page
Reset, Interrupt, and System Control Registers and Control Bits ...................................................68
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ...........................................68
5.8.2 System Reset Status Register (SRS) ................................................................................69
5.8.3 System Background Debug Force Reset Register (SBDFR) ...........................................71
5.8.4 System Options Register (SOPT) ....................................................................................71
5.8.5 System Device Identification Register (SDIDH, SDIDL) ...............................................72
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) ...............................73
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ..........................74
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ..........................75
Chapter 6
Parallel Input/Output
6.1
6.2
6.3
6.4
6.5
6.6
Introduction .....................................................................................................................................77
Features ...........................................................................................................................................79
Pin Descriptions ..............................................................................................................................79
6.3.1 Port A and Keyboard Interrupts .......................................................................................79
6.3.2 Port B and Analog to Digital Converter Inputs ...............................................................80
6.3.3 Port C and SCI2, IIC, and High-Current Drivers ............................................................80
6.3.4 Port D, TPM1 and TPM2 .................................................................................................81
6.3.5 Port E, SCI1, and SPI ......................................................................................................81
6.3.6 Port F and High-Current Drivers .....................................................................................82
6.3.7 Port G, BKGD/MS, and Oscillator ..................................................................................82
Parallel I/O Controls ........................................................................................................................82
6.4.1 Data Direction Control ....................................................................................................83
6.4.2 Internal Pullup Control ....................................................................................................83
6.4.3 Slew Rate Control ............................................................................................................83
Stop Modes ......................................................................................................................................84
Parallel I/O Registers and Control Bits ...........................................................................................84
6.6.1 Port A Registers (PTAD, PTAPE, PTASE, and PTADD) ................................................84
6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) ...............................................86
6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) ...............................................87
6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ..............................................89
6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ................................................90
6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) ..................................................92
6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ..............................................93
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
9
Section Number
Title
Page
Chapter 7
Internal Clock Generator (ICG) Module
7.1
7.2
7.3
7.4
7.5
Introduction .....................................................................................................................................99
7.1.1 Features ..........................................................................................................................100
7.1.2 Modes of Operation .......................................................................................................101
External Signal Description ..........................................................................................................101
7.2.1 Overview ........................................................................................................................101
7.2.2 Detailed Signal Descriptions .........................................................................................102
7.2.2.1 EXTAL— External Reference Clock / Oscillator Input ...............................102
7.2.2.2 XTAL— Oscillator Output ...........................................................................102
7.2.3 External Clock Connections ..........................................................................................102
7.2.4 External Crystal/Resonator Connections .......................................................................102
Functional Description ..................................................................................................................103
7.3.1 Off Mode (Off) ..............................................................................................................103
7.3.1.1 BDM Active .................................................................................................103
7.3.1.2 OSCSTEN Bit Set .........................................................................................103
7.3.1.3 Stop/Off Mode Recovery ..............................................................................104
7.3.2 Self-Clocked Mode (SCM) ............................................................................................104
7.3.3 FLL Engaged, Internal Clock (FEI) Mode ....................................................................105
7.3.3.1 FLL Engaged Internal Unlocked ..................................................................105
7.3.3.2 FLL Engaged Internal Locked ......................................................................106
7.3.4 FLL Bypassed, External Clock (FBE) Mode ................................................................106
7.3.5 FLL Engaged, External Clock (FEE) Mode ..................................................................106
7.3.5.1 FLL Engaged External Unlocked .................................................................106
7.3.5.2 FLL Engaged External Locked .....................................................................107
7.3.6 FLL Lock and Loss-of-Lock Detection .........................................................................107
7.3.7 FLL Loss-of-Clock Detection ........................................................................................107
7.3.8 Clock Mode Requirements ............................................................................................108
7.3.9 Fixed Frequency Clock ..................................................................................................109
Initialization/Application Information ..........................................................................................110
7.4.1 Introduction ....................................................................................................................110
7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz .........................112
7.4.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................113
7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency .....................114
7.4.5 Example #4: Internal Clock Generator Trim .................................................................116
ICG Registers and Control Bits .....................................................................................................117
7.5.1 ICG Control Register 1 (ICGC1) ......................................................................118
7.5.2 ICG Control Register 2 (ICGC2) ......................................................................119
7.5.3 ICG Status Register 1 (ICGS1) .................................................................................120
7.5.4 ICG Status Register 2 (ICGS2) ........................................................................122
7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL) .......................................................122
7.5.6 ICG Trim Register (ICGTRM) ...........................................................................123
MC9S08GB/GT Data Sheet, Rev. 2.3
10
Freescale Semiconductor
Section Number
Title
Page
Chapter 8
Central Processor Unit (CPU)
8.1
8.2
8.3
8.4
8.5
8.6
Introduction ...................................................................................................................................125
Features .........................................................................................................................................126
Programmer’s Model and CPU Registers .....................................................................................126
8.3.1 Accumulator (A) ............................................................................................................127
8.3.2 Index Register (H:X) .....................................................................................................127
8.3.3 Stack Pointer (SP) ..........................................................................................................128
8.3.4 Program Counter (PC) ...................................................................................................128
8.3.5 Condition Code Register (CCR) ....................................................................................128
Addressing Modes .........................................................................................................................130
8.4.1 Inherent Addressing Mode (INH) ..................................................................................130
8.4.2 Relative Addressing Mode (REL) .................................................................................130
8.4.3 Immediate Addressing Mode (IMM) .............................................................................130
8.4.4 Direct Addressing Mode (DIR) .....................................................................................130
8.4.5 Extended Addressing Mode (EXT) ...............................................................................131
8.4.6 Indexed Addressing Mode .............................................................................................131
8.4.6.1 Indexed, No Offset (IX) ................................................................................131
8.4.6.2 Indexed, No Offset with Post Increment (IX+) .............................................131
8.4.6.3 Indexed, 8-Bit Offset (IX1) ...........................................................................131
8.4.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .......................................131
8.4.6.5 Indexed, 16-Bit Offset (IX2) .........................................................................131
8.4.6.6 SP-Relative, 8-Bit Offset (SP1) ....................................................................131
8.4.6.7 SP-Relative, 16-Bit Offset (SP2) ..................................................................132
Special Operations .........................................................................................................................132
8.5.1 Reset Sequence ..............................................................................................................132
8.5.2 Interrupt Sequence .........................................................................................................132
8.5.3 Wait Mode Operation .....................................................................................................133
8.5.4 Stop Mode Operation .....................................................................................................133
8.5.5 BGND Instruction ..........................................................................................................134
HCS08 Instruction Set Summary ..................................................................................................134
Chapter 9
Keyboard Interrupt (KBI) Module
9.1
9.2
9.3
9.4
9.5
Introduction ...................................................................................................................................145
9.1.1 Port A and Keyboard Interrupt Pins ..............................................................................145
Features .........................................................................................................................................145
KBI Block Diagram ......................................................................................................................147
Keyboard Interrupt (KBI) Module ................................................................................................147
9.4.1 Pin Enables ....................................................................................................................147
9.4.2 Edge and Level Sensitivity ............................................................................................147
9.4.3 KBI Interrupt Controls ...................................................................................................148
KBI Registers and Control Bits .....................................................................................................148
9.5.1 KBI Status and Control Register (KBI1SC) ..................................................................148
9.5.2 KBI Pin Enable Register (KBI1PE) ..............................................................................150
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
11
Section Number
Title
Page
Chapter 10
Timer/PWM (TPM) Module
10.1
10.2
10.3
10.4
Introduction ...................................................................................................................................151
Features .........................................................................................................................................151
TPM Block Diagram .....................................................................................................................153
Pin Descriptions ............................................................................................................................154
10.4.1 External TPM Clock Sources ........................................................................................154
10.4.2 TPMxCHn — TPMx Channel n I/O Pins ......................................................................154
10.5 Functional Description ..................................................................................................................154
10.5.1 Counter ..........................................................................................................................155
10.5.2 Channel Mode Selection ................................................................................................156
10.5.2.1 Input Capture Mode ......................................................................................156
10.5.2.2 Output Compare Mode .................................................................................156
10.5.2.3 Edge-Aligned PWM Mode ...........................................................................156
10.5.3 Center-Aligned PWM Mode ..........................................................................................157
10.6 TPM Interrupts ..............................................................................................................................159
10.6.1 Clearing Timer Interrupt Flags ......................................................................................159
10.6.2 Timer Overflow Interrupt Description ...........................................................................159
10.6.3 Channel Event Interrupt Description .............................................................................159
10.6.4 PWM End-of-Duty-Cycle Events ..................................................................................160
10.7 TPM Registers and Control Bits ...................................................................................................160
10.7.1 Timer x Status and Control Register (TPMxSC) ...........................................................160
10.7.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ..............................................162
10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ..............................163
10.7.4 Timer x Channel n Status and Control Register (TPMxCnSC) .....................................163
10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) .....................................165
Chapter 11
Serial Communications Interface (SCI) Module
11.1
11.2
11.3
11.4
11.5
Introduction ...................................................................................................................................167
Features .........................................................................................................................................169
SCI System Description ................................................................................................................169
Baud Rate Generation ...................................................................................................................169
Transmitter Functional Description ...............................................................................................170
11.5.1 Transmitter Block Diagram ...........................................................................................170
11.5.2 Send Break and Queued Idle .........................................................................................172
11.6 Receiver Functional Description ...................................................................................................172
11.6.1 Receiver Block Diagram ................................................................................................172
11.6.2 Data Sampling Technique ..............................................................................................174
11.6.3 Receiver Wakeup Operation ..........................................................................................174
11.6.3.1 Idle-Line Wakeup ..........................................................................................175
11.6.3.2 Address-Mark Wakeup .................................................................................175
11.7 Interrupts and Status Flags ............................................................................................................175
MC9S08GB/GT Data Sheet, Rev. 2.3
12
Freescale Semiconductor
Section Number
Title
Page
11.8 Additional SCI Functions ..............................................................................................................176
11.8.1 8- and 9-Bit Data Modes ................................................................................................176
11.9 Stop Mode Operation ....................................................................................................................176
11.9.1 Loop Mode .....................................................................................................................177
11.9.2 Single-Wire Operation ...................................................................................................177
11.10 SCI Registers and Control Bits .....................................................................................................177
11.10.1 SCI x Baud Rate Registers (SCIxBDH, SCIxBDL) ......................................................177
11.10.2 SCI x Control Register 1 (SCIxC1) ...............................................................................178
11.10.3 SCI x Control Register 2 (SCIxC2) ...............................................................................180
11.10.4 SCI x Status Register 1 (SCIxS1) ..................................................................................181
11.10.5 SCI x Status Register 2 (SCIxS2) ..................................................................................183
11.10.6 SCI x Control Register 3 (SCIxC3) ...............................................................................184
11.10.7 SCI x Data Register (SCIxD) ........................................................................................185
Chapter 12
Serial Peripheral Interface (SPI) Module
12.1 Features .........................................................................................................................................189
12.2 Block Diagrams .............................................................................................................................189
12.2.1 SPI System Block Diagram ...........................................................................................189
12.2.2 SPI Module Block Diagram ...........................................................................................190
12.2.3 SPI Baud Rate Generation .............................................................................................192
12.3 Functional Description ..................................................................................................................192
12.3.1 SPI Clock Formats .........................................................................................................193
12.3.2 SPI Pin Controls ............................................................................................................195
12.3.2.1 SPSCK1 — SPI Serial Clock ........................................................................195
12.3.2.2 MOSI1 — Master Data Out, Slave Data In ..................................................195
12.3.2.3 MISO1 — Master Data In, Slave Data Out ..................................................195
12.3.2.4 SS1 — Slave Select .......................................................................................195
12.3.3 SPI Interrupts .................................................................................................................196
12.3.4 Mode Fault Detection ....................................................................................................196
12.4 SPI Registers and Control Bits ......................................................................................................196
12.4.1 SPI Control Register 1 (SPI1C1) ...................................................................................197
12.4.2 SPI Control Register 2 (SPI1C2) ...................................................................................198
12.4.3 SPI Baud Rate Register (SPI1BR) .................................................................................199
12.4.4 SPI Status Register (SPI1S) ...........................................................................................201
12.4.5 SPI Data Register (SPI1D) ............................................................................................202
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
13
Section Number
Title
Page
Chapter 13
Inter-Integrated Circuit (IIC) Module
13.1 Introduction ...................................................................................................................................205
13.1.1 Features ..........................................................................................................................205
13.1.2 Modes of Operation .......................................................................................................205
13.1.3 Block Diagram ...............................................................................................................206
13.1.4 Detailed Signal Descriptions .........................................................................................206
13.1.4.1 SCL1 — Serial Clock Line ...........................................................................206
13.1.4.2 SDA1 — Serial Data Line ............................................................................206
13.2 Functional Description ..................................................................................................................207
13.2.1 IIC Protocol ...................................................................................................................207
13.2.1.1 START Signal ...............................................................................................208
13.2.1.2 Slave Address Transmission .........................................................................208
13.2.1.3 Data Transfer .................................................................................................208
13.2.1.4 STOP Signal ..................................................................................................209
13.2.1.5 Repeated START Signal ...............................................................................209
13.2.1.6 Arbitration Procedure ....................................................................................209
13.2.1.7 Clock Synchronization ..................................................................................209
13.2.1.8 Handshaking .................................................................................................210
13.2.1.9 Clock Stretching ............................................................................................210
13.3 Resets ............................................................................................................................................210
13.4 Interrupts .......................................................................................................................................211
13.4.1 Byte Transfer Interrupt ..................................................................................................211
13.4.2 Address Detect Interrupt ................................................................................................211
13.4.3 Arbitration Lost Interrupt ..............................................................................................211
13.5 IIC Registers and Control Bits ......................................................................................................212
13.5.1 IIC Address Register (IIC1A) ........................................................................................212
13.5.2 IIC Frequency Divider Register (IIC1F) ........................................................................212
13.5.3 IIC Control Register (IIC1C) .........................................................................................215
13.5.4 IIC Status Register (IIC1S) ............................................................................................216
13.5.5 IIC Data I/O Register (IIC1D) .......................................................................................217
Chapter 14
Analog-to-Digital Converter (ATD) Module
14.1 Introduction ...................................................................................................................................221
14.1.1 Features ..........................................................................................................................221
14.1.2 Modes of Operation .......................................................................................................221
14.1.2.1 Stop Mode .....................................................................................................221
14.1.2.2 Power Down Mode .......................................................................................221
14.1.3 Block Diagram ...............................................................................................................221
14.2 Signal Description .........................................................................................................................222
14.2.1 Overview ........................................................................................................................222
14.2.1.1 Channel Input Pins — AD1P7–AD1P0 ........................................................223
MC9S08GB/GT Data Sheet, Rev. 2.3
14
Freescale Semiconductor
Section Number
14.3
14.4
14.5
14.6
Title
Page
14.2.1.2 ATD Reference Pins — VREFH, VREFL ........................................................223
14.2.1.3 ATD Supply Pins — VDDAD, VSSAD ...........................................................223
Functional Description ..................................................................................................................223
14.3.1 Mode Control .................................................................................................................223
14.3.2 Sample and Hold ............................................................................................................224
14.3.3 Analog Input Multiplexer ..............................................................................................226
14.3.4 ATD Module Accuracy Definitions ...............................................................................226
Resets ............................................................................................................................................229
Interrupts .......................................................................................................................................229
ATD Registers and Control Bits ....................................................................................................229
14.6.1 ATD Control (ATDC) ....................................................................................................230
14.6.2 ATD Status and Control (ATD1SC) ..............................................................................232
14.6.3 ATD Result Data (ATD1RH, ATD1RL) ........................................................................234
14.6.4 ATD Pin Enable (ATD1PE) ...........................................................................................234
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................235
15.2 Features .........................................................................................................................................236
15.3 Background Debug Controller (BDC) ..........................................................................................237
15.3.1 BKGD Pin Description ..................................................................................................237
15.3.2 Communication Details .................................................................................................238
15.3.3 BDC Commands ............................................................................................................242
15.3.4 BDC Hardware Breakpoint ............................................................................................244
15.4 On-Chip Debug System (DBG) ....................................................................................................245
15.4.1 Comparators A and B ....................................................................................................245
15.4.2 Bus Capture Information and FIFO Operation ..............................................................245
15.4.3 Change-of-Flow Information .........................................................................................246
15.4.4 Tag vs. Force Breakpoints and Triggers ........................................................................246
15.4.5 Trigger Modes ................................................................................................................247
15.4.6 Hardware Breakpoints ...................................................................................................249
15.5 Registers and Control Bits .............................................................................................................249
15.5.1 BDC Registers and Control Bits ....................................................................................249
15.5.1.1 BDC Status and Control Register (BDCSCR) ..............................................250
15.5.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................251
15.5.2 System Background Debug Force Reset Register (SBDFR) .........................................251
15.5.3 DBG Registers and Control Bits ....................................................................................252
15.5.3.1 Debug Comparator A High Register (DBGCAH) ........................................252
15.5.3.2 Debug Comparator A Low Register (DBGCAL) .........................................252
15.5.3.3 Debug Comparator B High Register (DBGCBH) .........................................252
15.5.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................252
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
15
Section Number
15.5.3.5
15.5.3.6
15.5.3.7
15.5.3.8
15.5.3.9
Title
Page
Debug FIFO High Register (DBGFH) ..........................................................253
Debug FIFO Low Register (DBGFL) ...........................................................253
Debug Control Register (DBGC) ..................................................................254
Debug Trigger Register (DBGT) ..................................................................255
Debug Status Register (DBGS) .....................................................................256
Appendix A
Electrical Characteristics
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
Introduction ...................................................................................................................................259
Absolute Maximum Ratings ..........................................................................................................259
Thermal Characteristics .................................................................................................................260
Electrostatic Discharge (ESD) Protection Characteristics ............................................................261
DC Characteristics .........................................................................................................................261
Supply Current Characteristics ......................................................................................................265
ATD Characteristics ......................................................................................................................269
Internal Clock Generation Module Characteristics .......................................................................271
A.8.1 ICG Frequency Specifications ........................................................................................271
A.9 AC Characteristics .........................................................................................................................273
A.9.1 Control Timing ...............................................................................................................273
A.9.2 Timer/PWM (TPM) Module Timing ..............................................................................274
A.9.3 SPI Timing ......................................................................................................................275
A.10 FLASH Specifications ...................................................................................................................279
Appendix B
Ordering Information and Mechanical Drawings
B.1
B.2
B.3
B.4
B.5
B.6
Ordering Information ....................................................................................................................281
Mechanical Drawings ....................................................................................................................281
64-Pin LQFP Package Drawing ....................................................................................................282
48-Pin QFN Package Drawing ......................................................................................................283
44-Pin QFP Package Drawing .......................................................................................................284
42-Pin SDIP Package Drawing .....................................................................................................285
MC9S08GB/GT Data Sheet, Rev. 2.3
16
Freescale Semiconductor
Chapter 1 Introduction
1.1
Overview
The MC9S08GB/GT are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types.
1.2
Features
Features have been organized to reflect:
• Standard features of the HCS08 Family
• Features of the MC9S08GB/GT MCU
1.2.1
•
•
•
•
•
•
•
•
1.2.2
•
•
•
•
•
Standard Features of the HCS08 Family
40-MHz HCS08 CPU (central processor unit)
HC08 instruction set with added BGND instruction
Background debugging system (see also Chapter 15, “Development Support”)
Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data. Debug module supports both tag and force
breakpoints.
Support for up to 32 interrupt/reset sources
Power-saving modes: wait plus three stops
System protection features:
— Optional computer operating properly (COP) reset
— Low-voltage detection with reset or interrupt
— Illegal opcode detection with reset
— Illegal address detection with reset (some devices don’t have illegal addresses)
Features of MC9S08GB/GT Series of MCUs
On-chip in-circuit programmable FLASH memory with block protection and security options (see
Table 1-1 for device specific information)
On-chip random-access memory (RAM) (see Table 1-1 for device specific information)
8-channel, 10-bit analog-to-digital converter (ATD)
Two serial communications interface modules (SCI)
Serial peripheral interface module (SPI)
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
17
Chapter 1 Introduction
•
Multiple clock source options:
— Internally generated clock with ±0.2% trimming resolution and ±0.5% deviation across
voltage.
— Crystal
— Resonator, or
— External clock
Inter-integrated circuit bus module to operate up to 100 kbps (IIC)
One 3-channel and one 5-channel 16-bit timer/pulse width modulator (TPM) modules with
selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each
timer module may be configured for buffered, centered PWM (CPWM) on all channels (TPMx).
8-pin keyboard interrupt module (KBI)
16 high-current pins (limited by package dissipation)
Software selectable pullups on ports when used as input. Selection is on an individual port bit basis.
During output mode, pullups are disengaged.
Internal pullup on RESET and IRQ pin to reduce customer system cost
Up to 56 general-purpose input/output (I/O) pins, depending on package selection
64-pin low-profile quad flat package (LQFP) — MC9S08GBxx
48-pin quad flat package, no lead (QFN) — MC9S08GTxx
44-pin quad flat package (QFP) — MC9S08GTxx
42-pin shrink dual in-line package (SDIP) — MC9S08GTxx
•
•
•
•
•
•
•
•
•
•
•
1.2.3
Devices in the MC9S08GB/GT Series
Table 1-1 lists the devices available in the MC9S08GB/GT series and summarizes the differences among
them.
Table 1-1. Devices in the MC9S08GB/GT Series
1
Device
FLASH
RAM
TPM
I/O
Packages
MC9S08GB60
60K
4K
56
64 LQFP
MC9S08GB32
32K
2K
56
64 LQFP
MC9S08GT60
60K
4K
One 3-channel and one
5-channel, 16-bit timer
One 3-channel and one
5-channel, 16-bit timer
Two 2-channel,
16-bit timers
MC9S08GT32
32K
2K
Two 2-channel,
16-bit timers
MC9S08GT16
16K
1K
Two 2-channel,
16-bit timers
39
36
34
39
36
34
39
36
34
48 QFN1
44 QFP
42 SDIP
48 QFN(1)
44 QFP
42 SDIP
48 QFN(1)
44 QFP
42 SDIP
The 48-pin QFN package has one 3-channel and one 2-channel 16-bit TPM.
MC9S08GB/GT Data Sheet, Rev. 2.3
18
Freescale Semiconductor
MCU Block Diagrams
1.3
MCU Block Diagrams
These block diagrams show the structure of the MC9S08GB/GT MCUs.
RTI
COP
IRQ
LVD
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
USER RAM
(GB60 = 4096 BYTES)
(GB32 = 2048 BYTES)
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD1)
INTERNAL CLOCK
GENERATOR (ICG)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
VDD
VSS
VOLTAGE
REGULATOR
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ
enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven
above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown
available when KBI enabled (KBIPn = 1).
PORT B
PTB7/AD1P7–
PTB0/AD1P0
NOTE 1
PTE7
PTE6
PTE5/SPSCK1
PTE4/MOSI1
PTE3/MISO1
PTE2/SS1
PTE1/RxD1
PTE0/TxD1
NOTE 1
PTF7–PTF0
NOTES 1, 5
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
LOW-POWER OSCILLATOR
NOTES 1, 6
PTD7/TPM2CH4
PTD6/TPM2CH3
PTD5/TPM2CH2
PTD4/TPM2CH1
PTD3/TPM2CH0
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CH0
3-CHANNEL TIMER/PWM
MODULE (TPM1)
5-CHANNEL TIMER/PWM
MODULE (TPM2)
PTA7/KBI1P7–
PTA0/KBI1P0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL1
PTC2/SDA1
PTC1/RxD2
PTC0/TxD2
PORT F
USER FLASH
(GB60 = 61,268 BYTES)
(GB32 = 32,768 BYTES)
VDDAD
VSSAD
VREFH
VREFL
8
IIC MODULE (IIC1)
PORT G
IRQ
NOTES 2, 3
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
8
PORT C
HCS08 SYSTEM CONTROL
RESET
NOTE 4
DEBUG
MODULE (DBG)
PORT D
CPU
PORT E
BDC
PORT A
INTERNAL BUS
HCS08 CORE
NOTES 1, 5
NOTE 1
8
PTG7
PTG6
PTG5
PTG4
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
NOTE 1
Figure 1-1. MC9S08GBxx Block Diagram
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
19
Chapter 1 Introduction
CPU
HCS08 SYSTEM CONTROL
COP
IRQ
LVD
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
USER FLASH
(GT60 = 61,268 BYTES)
(GT32 = 32,768 BYTES)
(GT16 = 16,384 BYTES)
USER RAM
(GT60 = 4096 BYTES)
(GT32 = 2048 BYTES)
(GT16 = 1024 BYTES)
VDDAD
VSSAD
VREFH
VREFL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD1)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
3-CHANNEL TIMER/PWM
MODULE (TPM1)
(NOTE 8)
PORT C
IIC MODULE (IIC1)
RTI
8
8
PTA7/KBI1P7–
PTA0/KBI1P0
PTB7/AD1P7–
PTB0/AD1P0
PTC6 (NOTE 6)
PTC5 (NOTE 6)
PTC4
PTC3/SCL1
PTC2/SDA1
PTC1/RxD2
PTC0/TxD2
NOTES 1, 7
NOTE 1
NOTES 1, 5
PTD4/TPM2CH1
PORT D
IRQ
NOTES 2, 3
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
PTD3/TPM2CH0
NOTE 1
PTD1/TPM1CH1
PTD0/TPM1CH0
PTE5/SPSCK1
5-CHANNEL TIMER/PWM
MODULE (TPM2)
(NOTE 8)
PORT E
RESET
NOTE 4
DEBUG
MODULE (DBG)
PORT B
BDC
PORT A
INTERNAL BUS
HCS08 CORE
PTE4/MOSI1
PTE3/MISO1
PTE2/SS1
NOTE 1
PTE1/RxD1
INTERNAL CLOCK
GENERATOR (ICG)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
PTE0/TxD1
PORT G
PTG2/EXTAL
LOW-POWER OSCILLATOR
VDD
VSS
PTG1/XTAL
NOTE 1
PTG0/BKGD/MS
VOLTAGE
REGULATOR
NOTES:
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1).
3. IRQ does not have a clamp diode to VDD. IRQ should not be driven above VDD.
4. Pin contains integrated pullup device.
5. High current drive
6. PTC[6:5] are not available on the 42-pin SDIP package.
7. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1).
8. Only two timer channels per TPM are bonded out. All channels are available for use as software compare.
Figure 1-2. MC9S08GTxx Block Diagram
MC9S08GB/GT Data Sheet, Rev. 2.3
20
Freescale Semiconductor
System Clock Distribution
Table 1-2 lists the functional versions of the on-chip modules.
Table 1-2. Block Versions
1.4
Module
Version
Analog-to-Digital Converter (ATD)
3
Internal Clock Generator (ICG)
2
Inter-Integrated Circuit (IIC)
1
Keyboard Interrupt (KBI)
1
Serial Communications Interface (SCI)
1
Serial Peripheral Interface (SPI)
3
Timer Pulse-Width Modulator (TPM)
1
Central Processing Unit (CPU)
2
System Clock Distribution
ICGERCLK
SYSTEM
CONTROL
LOGIC
TPM1
TPM2
IIC1
SCI1
SCI2
SPI1
RTI
FFE
÷2
ICG
FIXED FREQ CLOCK (XCLK)
ICGOUT
÷2
BUSCLK
ICGLCLK*
CPU
BDC
* ICGLCLK is the alternate BDC clock source for the MC9S08GB/GT.
ATD1
RAM
ATD has min and max
frequency requirements.
See Chapter 1, “Introduction”
and Appendix A, “Electrical
Characteristics.
FLASH
FLASH has frequency
requirements for program
and erase operation.
See Appendix A, “Electrical
Characteristics.
Figure 1-3. System Clock Distribution Diagram
Some of the modules inside the MCU have clock source choices. Figure 1-3 shows a simplified clock
connection diagram. The ICG supplies the clock sources:
• ICGOUT is an output of the ICG module. It is one of the following:
— The external crystal oscillator
— An external clock source
— The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop
sub-module
Control bits inside the ICG determine which source is connected.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
21
Chapter 1 Introduction
•
•
•
FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency
of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK.
Otherwise the fixed-frequency clock will be BUSCLK.
ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed
up BDC communications in systems where the bus clock is slow.
ICGERCLK — External reference clock can be selected as the real-time interrupt clock source.
MC9S08GB/GT Data Sheet, Rev. 2.3
22
Freescale Semiconductor
Chapter 2 Pins and Connections
2.1
Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
PTG4
PTG3
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
VSSAD
VDDAD
PTF1
PTF0
PTA7/KBI1P7
PTA6/KBI1P6
PTA5/KBI1P5
PTA4/KBI1P4
63
62
61
60
59
58
57
56
55
54
53
52
51
50
64
PTA3/KBI1P3
PTG5
Device Pin Assignment
PTG6
2.2
49
RESET 1
48 PTA2/KBI1P2
PTG7
2
47
PTA1/KBI1P1
PTC0/TxD2
3
46
PTA0/KBI1P0
PTC1/RxD2
4
45
PTF7
PTC2/SDA1
5
44
PTF6
PTC3/SCL1
6
43
PTF5
PTC4
7
42
VREFL
PTC5
8
41
VREFH
PTC6
9
40
PTB7/AD1P7
PTC7
10
39
PTB6/AD1P6
PTF2
11
38
PTB5/AD1P5
PTF3
12
37
PTB4/AD1P4
PTF4
13
36
PTB3/AD1P3
PTE0/TxD1
14
35
PTB2/AD1P2
PTE1/RxD1
15
34
PTB1/AD1P1
IRQ 16
33 PTB0/AD1P0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PTD6/TPM2CH3
PTD5/TPM2CH2
PTD4/TPM2CH1
PTD3/TPM2CH0
PTD2/TPM1CH2
PTD1/TPM1CH1
PTD0/TPM1CH0
VDD
VSS
PTE7
PTE6
PTE5/SPSCK1
PTE4/MOSI1
PTE3/MISO1
PTE2/SS1
PTD7/TPM2CH4
32
17
Figure 2-1. MC9S08GBxx in 64-Pin LQFP Package
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
23
PTA2/KBI1P2
37
PTA4/KBI1P4
39
38 PTA3/KBI1P3
PTA5/KBI1P5
40
41 PTA6/KBI1P6
42 PTA7/KBI1P7
VDDAD
44 VSSAD
45 PTG0/BKGD/MS
46 PTG1/XTAL
43
RESET 1
47 PTG2/EXTAL
48 PTG3
Chapter 2 Pins and Connections
36
PTA1/KBI1P1
IRQ 12
25
PTB0/AD1P0
24
PTB1/AD1P1
PTD4/TPM2CH1
26
23
PTE1/RxD1 11
PTD3/TPM2CH0
PTB2/AD1P2
22
27
PTD2/TPM1CH2
PTE0/TxD1 10
21
PTB3/AD1P3
PTD1/TPM1CH1
28
20
PTC7 9
PTD0/TPM1CH0
PTB4/AD1P4
19
29
VDD
PTC6 8
18
30 PTB5/AD1P5
VSS2
PTC5 7
17
31 PTB6/AD1P6
VSS1
PTC4 6
16
32 PTB7/AD1P7
PTE5/SPSCK1
PTC3/SCL1 5
15
33 VREFH
PTE4/MOSI1
PTC2/SDA1 4
14
34 VREFL
PTE3/MISO1
PTC1/RxD2 3
13
35 PTA0/KBI1P0
PTE2/SS1
PTC0/TxD2 2
Figure 2-2. MC9S08GTxx in 48-Pin QFN Package
MC9S08GB/GT Data Sheet, Rev. 2.3
24
Freescale Semiconductor
34 PTA2/KBI1P2
PTA3/KBI1P3
PTA6/KBI1P6
38
35
PTA7/KBI1P7
39
PTA4/KBI1P4
VDDAD
40
36
VSSAD
41
PTA5/KBI1P5
PTG0/BKGD/MS
42
RESET 1
37
PTG1/XTAL
43
44 PTG2/EXTAL
Device Pin Assignment
33 PTA1/KBI1P1
28
PTB6/AD1P6
PTC5
7
27
PTB5/AD1P5
PTC6
8
26
PTB4/AD1P4
PTE0/TxD1
9
25
PTB3/AD1P3
PTE1/RxD1
10
24
PTB2/AD1P2
23
PTB1/AD1P1
PTB0/AD1P0 22
PTE2/SS1 12
IRQ 11
21
6
PTD4/TPM2CH1
PTC4
20
PTB7/AD1P7
PTD3/TPM2CH0
29
19
5
PTD1/TPM1CH1
PTC3/SCL1
18
VREFH
PTD0/TPM1CH0
30
17
4
VDD
PTC2/SDA1
16
VREFL
VSS
31
15
3
PTE5/SPSCK1
PTC1/RxD2
14
PTA0/KBI1P0
PTE4/MOSI1
32
13
2
PTE3/MISO1
PTC0/TxD2
Figure 2-3. MC9S08GTxx in 44-Pin QFP Package
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
25
Chapter 2 Pins and Connections
VDDAD
1
42
PTA7/KBI1P7
VSSAD
2
41
PTA6/KBI1P6
PTG0/BKGD/MS
3
40
PTA5/KBI1P5
PTG1/XTAL
4
39
PTA4/KBI1P4
PTG2/EXTAL
5
38
PTA3/KBI1P3
RESET
6
37
PTA2/KBI1P2
PTC0/TxD2
7
36
PTA1/KBI1P1
PTC1/RXD2
8
35
PTA0/KBI1P0
PTC2/SDA1
9
34
VREFL
PTC3/SCL1
10
33
VREFH
PTC4
11
32
PTB7/AD1P7
PTE0/TxD1
12
31
PTB6/AD1P6
PTE1/RxD1
13
30
PTB5/AD1P5
IRQ
14
29
PTB4/AD1P4
PTE2/SS1
15
28
PTB3/AD1P3
PTE3/MISO1
16
27
PTB2/AD1P2
PTE4/MOSI1
17
26
PTB1/AD1P1
PTE5/SPSCK1
18
25
PTB0/AD1P0
VSS
19
24
PTD4/TPM2CH1
VDD
20
23
PTD3/TPM2CH0
PTD0/TPM1CH0
21
22
PTD1/TPM1CH1
Figure 2-4. MC9S08GTxx in 42-Pin SDIP Package
2.3
Recommended System Connections
Figure 2-5 shows pin connections that are common to almost all MC9S08GB60 application systems.
MC9S08GTxx connections will be similar except for the number of I/O pins available. A more detailed
discussion of system connections follows.
MC9S08GB/GT Data Sheet, Rev. 2.3
26
Freescale Semiconductor
Recommended System Connections
VREFH
CBYAD
0.1 µF
+
3V
MC9S08GBxx
PTA0/KBI1P0
VSSAD
VREFL
VDD
VDD
SYSTEM
POWER
VDDAD
CBLK +
10 µF
CBY
0.1 µF
PTA1/KBI1P1
PTA2/KBI1P2
PORT
A
VSS
NOTE 4
PTA3/KBI1P3
PTA4/KBI1P4
PTA5/KBI1P5
PTA6/KBI1P6
PTA7/KBI1P7
NOTE 1
RF
C1
RS
C2
X1
PTB0/AD1P0
XTAL
NOTE 2
PTB1/AD1P1
PTB2/AD1P2
EXTAL
NOTE 2
PORT
B
PTB3/AD1P3
PTB4/AD1P4
PTB5/AD1P5
BACKGROUND HEADER
VDD
BKGD/MS
NOTE 3
PTB6/AD1P6
I/O AND
PTB7/AD1P7
PERIPHERAL
PTC0/TxD2
INTERFACE TO
PTC1/RxD2
APPLICATION
PTC2/SDA1
RESET
OPTIONAL
MANUAL
RESET
PORT
C
PTC3/SCL1
SYSTEM
PTC4
PTC5
ASYNCHRONOUS
INTERRUPT
INPUT
PTC6
IRQ
PTC7
PTG0/BKDG/MS
PTD0/TPM1CH0
PTG1/XTAL
PTD1/TPM1CH1
PTG2/EXTAL
PTD2/TPM1CH2
NOTES:
1. Not required if
using the internal
oscillator option.
2. These are the
same pins as
PTG1 and PTG2.
3. BKGD/MS is the
same pin as PTG0.
4. The 48-pin QFN
has 2 VSS pins
(VSS1 and VSS2),
both of which must
be connected to
GND.
PTG3
PTG4
PORT
G
PORT
D
PTD3/TPM2CH0
PTD4/TPM2CH1
PTG5
PTD5/TPM2CH2
PTG6
PTD6/TPM2CH3
PTG7
PTD7/TPM2CH4
PTF0
PTE0/TxD1
PTF1
PTE1/RxD1
PTE2/SS1
PTF2
PTF3
PTF4
PORT
F
PORT
E
PTE3/MISO1
PTE4/MOSI1
PTF5
PTE5/SPSCK1
PTF6
PTE6
PTF7
PTE7
Figure 2-5. Basic System Connections
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
27
Chapter 2 Pins and Connections
2.3.1
Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-µF tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-µF ceramic bypass capacitor located as close to the MCU power pins as
practical to suppress high-frequency noise.
VDDAD and VSSAD are the analog power supply pins for the MCU. This voltage source supplies power to
the ATD. A 0.1-µF ceramic bypass capacitor should be located as close to the MCU power pins as practical
to suppress high-frequency noise.
2.3.2
Oscillator
Out of reset, the MCU uses an internally generated clock (self-clocked mode — fSelf_reset) that is
approximately equivalent to an 8-MHz crystal rate. This frequency source is used during reset startup and
can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. This
MCU also contains a trimmable internal clock generator (ICG) module that can be used to run the MCU.
For more information on the ICG, see Chapter 7, “Internal Clock Generator (ICG) Module.”
The oscillator in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator in
either of two frequency ranges selected by the RANGE bit in the ICGC1 register. Rather than a crystal or
ceramic resonator, an external oscillator can be connected to the EXTAL input pin, and the XTAL output
pin can be used as general I/O.
Refer to Figure 2-5 for the following discussion. RS (when used) and RF should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity
and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2 which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.3.3
Reset
RESET is a dedicated pin with a pullup device built in. It has input hysteresis, a high current output driver,
and no output slew rate control. Internal power-on reset and low-voltage reset circuitry typically make
external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background
MC9S08GB/GT Data Sheet, Rev. 2.3
28
Freescale Semiconductor
Recommended System Connections
debug connector so a development system can directly reset the MCU system. If desired, a manual external
reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for approximately 34 cycles of fSelf_reset, released, and sampled again approximately 38
cycles of fSelf_reset later. If reset was caused by an internal source such as low-voltage reset or watchdog
timeout, the circuitry expects the reset pin sample to return a logic 1. If the pin is still low at this sample
point, the reset is assumed to be from an external source. The reset circuitry decodes the cause of reset and
records it by setting a corresponding bit in the system control reset status register (SRS).
Never connect any significant capacitance to the reset pin because that would interfere with the circuit and
sequence that detects the source of reset. If an external capacitance prevents the reset pin from rising to a
valid logic 1 before the reset sample point, all resets will appear to be external resets.
2.3.4
Background / Mode Select (PTG0/BKGD/MS)
The background/mode select (BKGD/MS) shares its function with an I/O port pin. While in reset, the pin
functions as a mode select pin. Immediately after reset rises the pin functions as the background pin and
can be used for background debug communication. While functioning as a background/mode select pin,
the pin includes an internal pullup device, input hysteresis, a standard output driver, and no output slew
rate control. When used as an I/O port (PTG0) the pin is limited to output only.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5
General-Purpose I/O and Peripheral Ports
The remaining 55 pins are shared among general-purpose I/O and on-chip peripheral functions such as
timers and serial I/O systems. (Sixteen of these pins are not bonded out on the 48-pin package, twenty of
these pins are not bonded out on the 44-pin package, and twenty-two are not bonded out on the 42-pin
package.) Immediately after reset, all 55 of these pins are configured as high-impedance general-purpose
inputs with internal pullup devices disabled.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
29
Chapter 2 Pins and Connections
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from Table 2-1.
Table 2-1. Pin Sharing References
Port Pins
Alternate
Function
PTA7–PTA0
KBI1P7–KBI1P0
Chapter 2, “Pins and Connections”
PTB7–PTB0
AD1P7–AD1P0
Chapter 14, “Analog-to-Digital Converter (ATD) Module”
PTC7–PTC4
—
Chapter 6, “Parallel Input/Output”
PTC3–PTC2
SCL1–SDA1
Chapter 13, “Inter-Integrated Circuit (IIC) Module”
PTC1–PTC0
RxD2–TxD2
Chapter 11, “Serial Communications Interface (SCI) Module”
PTD7–PTD3
TPM2CH4–
TPM2CH0
Chapter 10, “Timer/PWM (TPM) Module”
PTD2–PTD0
TPM1CH2–
TPM1CH0
Chapter 10, “Timer/PWM (TPM) Module”
PTE7–PTE6
1
Reference1
—
Chapter 6, “Parallel Input/Output”
PTE5
PTE4
PTE3
PTE2
SPSCK1
MISO1
MOSI1
SS1
Chapter 12, “Serial Peripheral Interface (SPI) Module”
PTE1–PTE0
RxD1–TxD1
Chapter 11, “Serial Communications Interface (SCI) Module”
PTF7–PTF0
—
Chapter 6, “Parallel Input/Output”
PTG7–PTG3
—
Chapter 6, “Parallel Input/Output”
PTG2–PTG1
EXTAL–XTAL
Chapter 7, “Internal Clock Generator (ICG) Module”
PTG0
BKGD/MS
Chapter 15, “Development Support”
See this section for information about modules that share these pins.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output” for details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured
MC9S08GB/GT Data Sheet, Rev. 2.3
30
Freescale Semiconductor
Recommended System Connections
as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device
rather than a pullup device.
2.3.6
Signal Properties Summary
Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hardwired to internal circuits.
Table 2-2. Signal Properties
Pin
Name
High Current
Pin
Output
Slew 1
Pull-Up2
VDD
—
—
—
VSS
—
—
—
VDDAD
—
—
—
VSSAD
—
—
—
VREFH
—
—
—
VREFL
—
—
—
Y
N
Y
Pin contains integrated pullup.
IRQPE must be set to enable IRQ function.
IRQ does not have a clamp diode to VDD. IRQ should
not be driven above VDD.
Pullup/pulldown active when IRQ pin function
enabled. Pullup forced on when IRQ enabled for
falling edges; pulldown forced on when IRQ enabled
for rising edges.
RESET
Dir
I/O
IRQ
I
—
—
Y
PTA0/KBI1P0
I/O
N
SWC
SWC
PTA1/KBI1P1
I/O
N
SWC
SWC
PTA2/KBI1P2
I/O
N
SWC
SWC
PTA3/KBI1P3
I/O
N
SWC
SWC
PTA4/KBI1P4
I/O
N
SWC
SWC
PTA5/KBI1P5
I/O
N
SWC
SWC
PTA6/KBI1P6
I/O
N
SWC
SWC
PTA7/KBI1P7
I/O
N
SWC
SWC
PTB0/AD1P0
I/O
N
SWC
SWC
PTB1/AD1P1
I/O
N
SWC
SWC
PTB2/AD1P2
I/O
N
SWC
SWC
PTB3/AD1P3
I/O
N
SWC
SWC
PTB4/AD1P4
I/O
N
SWC
SWC
PTB5/AD1P5
I/O
N
SWC
SWC
PTB6/AD1P6
I/O
N
SWC
SWC
PTB7/AD1P7
I/O
N
SWC
SWC
PTC0/TxD2
I/O
Y
SWC
SWC
PTC1/RxD2
I/O
Y
SWC
SWC
PTC2/SDA1
I/O
Y
SWC
SWC
PTC3/SCL1
I/O
Y
SWC
SWC
Comments
The 48-pin QFN package has two VSS pins — VSS1
and VSS2.
Pullup/pulldown active when KBI pin function
enabled. Pullup forced on when KBI1Px enabled for
falling edges; pulldown forced on when KBI1Px
enabled for rising edges.
When pin is configured for SCI function, pin is
configured for partial output drive.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
31
Chapter 2 Pins and Connections
Table 2-2. Signal Properties (continued)
1
2
Pin
Name
Dir
High Current
Pin
Output
Slew 1
Pull-Up2
PTC4
I/O
Y
SWC
SWC
PTC5
I/O
Y
SWC
SWC
Not available on 42-pin pkg
PTC6
I/O
Y
SWC
SWC
Not available on 42-pin pkg
PTC7
I/O
Y
SWC
SWC
Not available on 42- or 44-pin pkg
PTD0/TPM1CH0
I/O
N
SWC
SWC
PTD1/TPM1CH1
I/O
N
SWC
SWC
PTD2/TPM1CH2
I/O
N
SWC
SWC
PTD3/TPM2CH0
I/O
N
SWC
SWC
PTD4/TPM2CH1
I/O
N
SWC
SWC
PTD5/TPM2CH2
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTD6/TPM2CH3
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTD7/TPM2CH4
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTE0/TxD1
I/O
N
SWC
SWC
PTE1/RxD1
I/O
N
SWC
SWC
PTE2/SS1
I/O
N
SWC
SWC
PTE3/MISO1
I/O
N
SWC
SWC
Comments
Not available on 42- or 44-pin pkg
PTE4/MOSI1
I/O
N
SWC
SWC
PTE5/SPSCK1
I/O
N
SWC
SWC
PTE6
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTE7
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF0
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF1
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF2
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF3
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF4
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF5
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF6
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTF7
I/O
Y
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTG0/BKGD/MS
O
N
SWC
SWC
Pullup enabled and slew rate disabled when BDM
function enabled.
PTG1/XTAL
I/O
N
SWC
SWC
Pullup and slew rate disabled when XTAL pin
function.
PTG2/EXTAL
I/O
N
SWC
SWC
Pullup and slew rate disabled when EXTAL pin
function.
PTG3
I/O
N
SWC
SWC
Not available on 42-, or 44-pin pkg
PTG4
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTG5
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTG6
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
PTG7
I/O
N
SWC
SWC
Not available on 42-, 44-, or 48-pin pkg
SWC is software controlled slew rate, the register is associated with the respective port.
SWC is software controlled pullup resistor, the register is associated with the respective port.
MC9S08GB/GT Data Sheet, Rev. 2.3
32
Freescale Semiconductor
Chapter 3 Modes of Operation
3.1
Introduction
The operating modes of the MC9S08GB/GT are described in this section. Entry into each mode, exit from
each mode, and functionality while in each of the modes are described.
3.2
•
•
•
3.3
Features
Active background mode for code development
Wait mode:
— CPU shuts down to conserve power
— System clocks running
— Full voltage regulation maintained
Stop modes:
— System clocks stopped; voltage regulator in standby
— Stop1 — Full power down of internal circuits for maximum power savings
— Stop2 — Partial power down of internal circuits, RAM contents retained
— Stop3 — All internal circuits powered for fast recovery
Run Mode
This is the normal operating mode for the MC9S08GB/GT. This mode is selected when the BKGD/MS
pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with
execution beginning at the address fetched from memory at $FFFE:$FFFF after reset.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
• When encountering a DBG breakpoint
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user’s application program.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
33
Chapter 3 Modes of Operation
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed while the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can be executed only while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user’s application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the MC9S08GB/GT is
shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default
unless specifically noted so there is no program that could be executed in run mode until the FLASH
memory is initially programmed. The active background mode can also be used to erase and reprogram
the FLASH memory after it has been previously programmed.
For additional information about the active background mode, refer to Chapter 15, “Development
Support.”
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6
Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the
system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set
when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
MC9S08GB/GT Data Sheet, Rev. 2.3
34
Freescale Semiconductor
Stop Modes
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
Table 3-1. Stop Mode Behavior
1
2
Mode
PDC
PPDC
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ATD
Regulator
I/O Pins
RTI
Stop1
1
0
Off
Off
Off
Disabled1
Off
Reset
Off
Stop2
1
1
Off
Standby
Off
Disabled
Standby
States
held
Optionally on
Stop3
0
Don’t
care
Standby
Standby
Off2
Disabled
Standby
States
held
Optionally on
Either ATD stop mode or power-down mode depending on the state of ATDPU.
Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
3.6.1
Stop1 Mode
The stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry
of the MCU to be powered down. Stop1 can be entered only if the LVD circuit is not enabled in stop modes
(either LVDE or LVDSE not set).
When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned
off. The voltage regulator is in a low-power standby state, as is the ATD.
Exit from stop1 is performed by asserting either of the wake-up pins on the MCU: RESET or IRQ. IRQ is
always an active low input when the MCU is in stop1, regardless of how it was configured before entering
stop1.
Entering stop1 mode automatically asserts LVD. Stop1 cannot be exited until VDD > VLVDH/L rising (VDD
must rise above the LVI rearm voltage).
Upon wake-up from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will
take the reset vector.
3.6.2
Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in stop
modes (either LVDE or LVDSE not set).
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2,
these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ATD. Upon entry
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a 1 is written to PPDACK in SPMSC2.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
35
Chapter 3 Modes of Operation
Exit from stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI
interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured
before entering stop2.
Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3
Stop3 Mode
Upon entering the stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
ICG is turned off, the ATD is disabled, and the voltage regulator is put in standby. The states of all of the
internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched
at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving the
pins being maintained.
Exit from stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time
interrupt. The asynchronous interrupt pins are the IRQ or KBI pins.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
3.6.4
Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM
is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain
active when the MCU enters stop mode so background debug communication is still possible. In addition,
MC9S08GB/GT Data Sheet, Rev. 2.3
36
Freescale Semiconductor
Stop Modes
the voltage regulator does not enter its low-power standby state but maintains full internal regulation. If
the user attempts to enter either stop1 or stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After the device enters background debug mode, all
background commands are available. The table below summarizes the behavior of the MCU in stop when
entry into the background debug mode is enabled.
Table 3-2. BDM Enabled Stop Mode Behavior
1
Mode
PDC
PPDC
Stop3
Don’t
care
Don’t
care
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ATD
Regulator
I/O Pins
RTI
Standby
Standby
Active
Disabled1
Active
States
held
Optionally on
Either ATD stop mode or power-down mode depending on the state of ATDPU.
3.6.5
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits in SPMSC1 when
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the
user attempts to enter either stop1 or stop2 with the LVD enabled for stop (LVDSE = 1), the MCU will
instead enter stop3. The table below summarizes the behavior of the MCU in stop when the LVD is
enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
1
Mode
PDC
PPDC
Stop3
Don’t
care
Don’t
care
CPU, Digital
Peripherals,
FLASH
RAM
ICG
ATD
Regulator
I/O Pins
RTI
Standby
Standby
Standby
Disabled1
Active
States
held
Optionally on
Either ATD stop mode or power-down mode depending on the state of ATDPU.
3.6.6
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop1
Mode,” Section 3.6.2, “Stop2 Mode,” and Section 3.6.3, “Stop3 Mode,” for specific information on system
behavior in stop modes.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
37
Chapter 3 Modes of Operation
I/O Pins
• All I/O pin states remain unchanged when the MCU enters stop3 mode.
• If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop.
• If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state
upon entry into stop.
Memory
• All RAM and register contents are preserved while the MCU is in stop3 mode.
• All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and
pin states remain latched until the PPDACK bit is written. The user may save any memory-mapped
register data into RAM before entering stop2 and restore the data upon exit from stop2.
• All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved.
The MCU must be initialized as upon reset. The contents of the FLASH memory are nonvolatile
and are preserved in any of the stop modes.
ICG — In stop3 mode, the ICG enters its low-power standby state. Either the oscillator or the internal
reference may be kept running when the ICG is in standby by setting the appropriate control bit. In both
stop2 and stop1 modes, the ICG is turned off. Neither the oscillator nor the internal reference can be kept
running in stop2 or stop1, even if enabled within the ICG module.
TPM — When the MCU enters stop mode, the clock to the TPM1 and TPM2 modules stop. The modules
halt operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM modules will be reset
upon wake-up from stop and must be reinitialized.
ATD — When the MCU enters stop mode, the ATD will enter a low-power standby state. No conversion
operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the ATD will
be reset upon wake-up from stop and must be reinitialized.
KBI — During stop3, the KBI pins that are enabled continue to function as interrupt sources that are
capable of waking the MCU from stop3. The KBI is disabled in stop1 and stop2 and must be reinitialized
after waking up from either of these modes.
SCI — When the MCU enters stop mode, the clocks to the SCI1 and SCI2 modules stop. The modules
halt operation. If the MCU is configured to go into stop2 or stop1 mode, the SCI modules will be reset
upon wake-up from stop and must be reinitialized.
SPI — When the MCU enters stop mode, the clocks to the SPI module stop. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wake-up from
stop and must be reinitialized.
IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from
stop and must be reinitialized.
Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any
of the stop modes unless the LVD is enabled in stop mode or BDM is enabled.
MC9S08GB/GT Data Sheet, Rev. 2.3
38
Freescale Semiconductor
Chapter 4 Memory
4.1
MC9S08GB/GT Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08GB/GT series of MCUs consists of RAM,
FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers
are divided into three groups:
• Direct-page registers ($0000 through $007F)
• High-page registers ($1800 through $182B)
• Nonvolatile registers ($FFB0 through $FFBF)
DIRECT PAGE REGISTERS
$0000
$007F
$0080
$0000
DIRECT PAGE REGISTERS
$007F
$0080
RAM
2048 BYTES
RAM
4096 BYTES
$0000
DIRECT PAGE REGISTERS
RAM 1024 BYTES
$007F
$0080
$047F
$0480
$087F
$0880
UNIMPLEMENTED
$107F
$1080
UNIMPLEMENTED
4992 BYTES
3968 BYTES
FLASH
1920 BYTES
$17FF
$1800
$17FF
$1800
HIGH PAGE REGISTERS
HIGH PAGE REGISTERS
$182B
$182C
$17FF
$1800
HIGH PAGE REGISTERS
$182B
$182C
$182B
$182C
UNIMPLEMENTED
26580 BYTES
$7FFF
$8000
UNIMPLEMENTED
42964 BYTES
FLASH
59348 BYTES
FLASH
$BFFF
$C000
32768 BYTES
FLASH
16384 BYTES
$FFFF
$FFFF
MC9S08GB60/MC9S08GT60
MC9S08GB32/MC9S08GT32
$FFFF
MC9S08GT16
Figure 4-1. MC9S08GB/GT Memory Map
4.1.1
Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale-provided equate file for the MC9S08GB/GT. For more details about
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
39
Chapter 4 Memory
resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets,
Interrupts, and System Configuration.”
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low)
Vector
Vector Name
$FFC0:FFC1
Unused Vector Space
(available for user program)
$FFCA:FFCB
$FFCC:FFCD
RTI
Vrti
$FFCE:FFCF
IIC
Viic1
$FFD0:FFD1
ATD Conversion
Vatd1
$FFD2:FFD3
Keyboard
Vkeyboard1
$FFD4:FFD5
SCI2 Transmit
Vsci2tx
$FFD6:FFD7
SCI2 Receive
Vsci2rx
$FFD8:FFD9
SCI2 Error
Vsci2err
$FFDA:FFDB
SCI1 Transmit
Vsci1tx
$FFDC:FFDD
SCI1 Receive
Vsci1rx
$FFDE:FFDF
SCI1 Error
Vsci1err
$FFE0:FFE1
SPI
Vspi1
$FFE2:FFE3
TPM2 Overflow
Vtpm2ovf
$FFE4:FFE5
TPM2 Channel 4
Vtpm2ch4
$FFE6:FFE7
TPM2 Channel 3
Vtpm2ch3
$FFE8:FFE9
TPM2 Channel 2
Vtpm2ch2
$FFEA:FFEB
TPM2 Channel 1
Vtpm2ch1
$FFEC:FFED
TPM2 Channel 0
Vtpm2ch0
$FFEE:FFEF
TPM1 Overflow
Vtpm1ovf
$FFF0:FFF1
TPM1 Channel 2
Vtpm1ch2
$FFF2:FFF3
TPM1 Channel 1
Vtpm1ch1
$FFF4:FFF5
TPM1 Channel 0
Vtpm1ch0
$FFF6:FFF7
ICG
Vicg
$FFF8:FFF9
Low Voltage Detect
Vlvd
$FFFA:FFFB
IRQ
Virq
$FFFC:FFFD
SWI
Vswi
$FFFE:FFFF
Reset
Vreset
MC9S08GB/GT Data Sheet, Rev. 2.3
40
Freescale Semiconductor
Register Addresses and Bit Assignments
4.2
Register Addresses and Bit Assignments
The registers in the MC9S08GB/GT are divided into these three groups:
• Direct-page registers are located in the first 128 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above $1800 in the memory map.
This leaves more room in the direct page for more frequently used registers and variables.
• The nonvolatile register area consists of a block of 16 locations in FLASH memory at
$FFB0–$FFBF.
Nonvolatile register locations include:
— Three values which are loaded into working registers at reset
— An 8-byte backdoor comparison key which optionally allows a user to gain controlled access
to secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode which only
requires the lower byte of the address. Because of this, the lower byte of the address in column one is
shown in bold text. In Table 4-3 and Table 4-4 the whole address in column one is shown in bold. In
Table 4-2, Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart
from the bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with
a 0 indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
41
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Address
Register Name
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
PTAD
PTAPE
PTASE
PTADD
PTBD
PTBPE
PTBSE
PTBDD
PTCD
PTCPE
PTCSE
PTCDD
PTDD
PTDPE
PTDSE
PTDDD
PTED
PTEPE
PTESE
PTEDD
IRQSC
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Reserved
KBI1SC
KBI1PE
SCI1BDH
SCI1BDL
SCI1C1
SCI1C2
SCI1S1
SCI1S2
SCI1C3
SCI1D
SCI2BDH
SCI2BDL
SCI2C1
SCI2C2
SCI2S1
SCI2S2
SCI2C3
SCI2D
Bit 7
6
5
4
3
2
1
Bit 0
PTAD7
PTAPE7
PTASE7
PTADD7
PTBD7
PTBPE7
PTBSE7
PTBDD7
PTCD7
PTCPE7
PTCSE7
PTCDD7
PTDD7
PTDPE7
PTDSE7
PTDDD7
PTED7
PTEPE7
PTESE7
PTEDD7
PTAD6
PTAPE6
PTASE6
PTADD6
PTBD6
PTBPE6
PTBSE6
PTBDD6
PTCD6
PTCPE6
PTCSE6
PTCDD6
PTDD6
PTDPE6
PTDSE6
PTDDD6
PTED6
PTEPE6
PTESE6
PTEDD6
PTAD5
PTAPE5
PTASE5
PTADD5
PTBD5
PTBPE5
PTBSE5
PTBDD5
PTCD5
PTCPE5
PTCSE5
PTCDD5
PTDD5
PTDPE5
PTDSE5
PTDDD5
PTED5
PTEPE5
PTESE5
PTEDD5
PTAD4
PTAPE4
PTASE4
PTADD4
PTBD4
PTBPE4
PTBSE4
PTBDD4
PTCD4
PTCPE4
PTCSE4
PTCDD4
PTDD4
PTDPE4
PTDSE4
PTDDD4
PTED4
PTEPE4
PTESE4
PTEDD4
PTAD3
PTAPE3
PTASE3
PTADD3
PTBD3
PTBPE3
PTBSE3
PTBDD3
PTCD3
PTCPE3
PTCSE3
PTCDD3
PTDD3
PTDPE3
PTDSE3
PTDDD3
PTED3
PTEPE3
PTESE3
PTEDD3
PTAD2
PTAPE2
PTASE2
PTADD2
PTBD2
PTBPE2
PTBSE2
PTBDD2
PTCD2
PTCPE2
PTCSE2
PTCDD2
PTDD2
PTDPE2
PTDSE2
PTDDD2
PTED2
PTEPE2
PTESE2
PTEDD2
PTAD1
PTAPE1
PTASE1
PTADD1
PTBD1
PTBPE1
PTBSE1
PTBDD1
PTCD1
PTCPE1
PTCSE1
PTCDD1
PTDD1
PTDPE1
PTDSE1
PTDDD1
PTED1
PTEPE1
PTESE1
PTEDD1
PTAD0
PTAPE0
PTASE0
PTADD0
PTBD0
PTBPE0
PTBSE0
PTBDD0
PTCD0
PTCPE0
PTCSE0
PTCDD0
PTDD0
PTDPE0
PTDSE0
PTDDD0
PTED0
PTEPE0
PTESE0
PTEDD0
0
—
KBEDG7
KBIPE7
0
SBR7
LOOPS
TIE
TDRE
0
R8
Bit 7
0
SBR7
LOOPS
TIE
TDRE
0
R8
Bit 7
0
—
KBEDG6
KBIPE6
0
SBR6
SCISWAI
TCIE
TC
0
T8
6
0
SBR6
SCISWAI
TCIE
TC
0
T8
6
IRQEDG
—
KBEDG5
KBIPE5
0
SBR5
RSRC
RIE
RDRF
0
TXDIR
5
0
SBR5
RSRC
RIE
RDRF
0
TXDIR
5
IRQPE
—
KBEDG4
KBIPE4
SBR12
SBR4
M
ILIE
IDLE
0
0
4
SBR12
SBR4
M
ILIE
IDLE
0
0
4
IRQF
—
KBF
KBIPE3
SBR11
SBR3
WAKE
TE
OR
0
ORIE
3
SBR11
SBR3
WAKE
TE
OR
0
ORIE
3
IRQACK
—
KBACK
KBIPE2
SBR10
SBR2
ILT
RE
NF
0
NEIE
2
SBR10
SBR2
ILT
RE
NF
0
NEIE
2
IRQIE
—
KBIE
KBIPE1
SBR9
SBR1
PE
RWU
FE
0
FEIE
1
SBR9
SBR1
PE
RWU
FE
0
FEIE
1
IRQMOD
—
KBIMOD
KBIPE0
SBR8
SBR0
PT
SBK
PF
RAF
PEIE
Bit 0
SBR8
SBR0
PT
SBK
PF
RAF
PEIE
Bit 0
MC9S08GB/GT Data Sheet, Rev. 2.3
42
Freescale Semiconductor
Register Addresses and Bit Assignments
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address
Register Name
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
SPI1C1
SPI1C2
SPI1BR
SPI1S
Reserved
SPI1D
Reserved
Reserved
TPM1SC
TPM1CNTH
TPM1CNTL
TPM1MODH
TPM1MODL
TPM1C0SC
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E–
$003F
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
$004C
$004D
$004E
TPM1C0VH
TPM1C0VL
TPM1C1SC
TPM1C1VH
TPM1C1VL
TPM1C2SC
TPM1C2VH
TPM1C2VL
Reserved
PTFD
PTFPE
PTFSE
PTFDD
PTGD
PTGPE
PTGSE
PTGDD
ICGC1
ICGC2
ICGS1
ICGS2
ICGFLTU
ICGFLTL
ICGTRM
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
0
0
SPRF
0
Bit 7
0
0
TOF
Bit 15
Bit 7
Bit 15
Bit 7
CH0F
SPE
0
SPPR2
0
0
6
0
0
TOIE
14
6
14
6
CH0IE
SPTIE
0
SPPR1
SPTEF
0
5
0
0
CPWMS
13
5
13
5
MS0B
MSTR
MODFEN
SPPR0
MODF
0
4
0
0
CLKSB
12
4
12
4
MS0A
CPOL
BIDIROE
0
0
0
3
0
0
CLKSA
11
3
11
3
ELS0B
CPHA
0
SPR2
0
0
2
0
0
PS2
10
2
10
2
ELS0A
SSOE
SPISWAI
SPR1
0
0
1
0
0
PS1
9
1
9
1
LSBFE
SPC0
SPR0
0
0
Bit 0
0
0
PS0
Bit 8
Bit 0
Bit 8
Bit 0
13
5
MS1B
13
5
MS2B
13
5
—
—
PTFD5
PTFPE5
PTFSE5
PTFDD5
PTGD5
PTGPE5
PTGSE5
PTGDD5
REFS
MFD
REFST
0
0
12
11
4
3
MS1A
ELS1B
12
11
4
3
MS2A
ELS2B
12
11
4
3
—
—
—
—
PTFD4
PTFD3
PTFPE4
PTFPE3
PTFSE4
PTFSE3
PTFDD4
PTFDD3
PTGD4
PTGD3
PTGPE4
PTGPE3
PTGSE4
PTGSE3
PTGDD4 PTGDD3
CLKS
LOCRE
LOLS
LOCK
0
0
0
FLT
TRIM
0
9
1
0
9
1
0
9
1
—
—
PTFD1
PTFPE1
PTFSE1
PTFDD1
PTGD1
PTGPE1
PTGSE1
PTGDD1
0*
RFD
ERCS
0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
—
—
PTFD0
PTFPE0
PTFSE0
PTFDD0
PTGD0
PTGPE0
PTGSE0
PTGDD0
0
Bit 15
14
Bit 7
6
CH1F
CH1IE
Bit 15
14
Bit 7
6
CH2F
CH2IE
Bit 15
14
Bit 7
6
—
—
—
—
PTFD7
PTFD6
PTFPE7
PTFPE6
PTFSE7
PTFSE6
PTFDD7
PTFDD6
PTGD7
PTGD6
PTGPE7
PTGPE6
PTGSE7
PTGSE6
PTGDD7 PTGDD6
0
RANGE
LOLRE
CLKST
0
0
0
0
10
2
ELS1A
10
2
ELS2A
10
2
—
—
PTFD2
PTFPE2
PTFSE2
PTFDD2
PTGD2
PTGPE2
PTGSE2
PTGDD2
OSCSTEN
LOCS
0
ICGIF
DCOS
FLT
* This bit is reserved for Freescale Semiconductor internal use only. Always write a 0 to this bit.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
43
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
$004F
Reserved
0
0
0
0
$0050
$0051
$0052
$0053
$0054
$0055–
$0057
$0058
$0059
$005A
$005B
ATD1C
ATD1SC
ATD1RH
ATD1RL
ATD1PE
ATDPU
CCF
Bit 7
Bit 7
ATDPE7
—
—
DJM
ATDIE
6
6
ATDPE6
—
—
RES8
ATDCO
5
5
ATDPE5
—
—
SGN
$005C
$005D–
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
$0068
$0069
$006A
$006B
$006C
$006D
$006E
$006F
$0070
$0071
$0072
$0073
$0074–
$007F
Reserved
IIC1A
IIC1F
IIC1C
IIC1S
TPM2SC
TPM2CNTH
TPM2CNTL
TPM2MODH
TPM2MODL
TPM2C0SC
TPM2C0VH
TPM2C0VL
TPM2C1SC
TPM2C1VH
TPM2C1VL
TPM2C2SC
TPM2C2VH
TPM2C2VL
TPM2C3SC
TPM2C3VH
TPM2C3VL
TPM2C4SC
TPM2C4VH
TPM2C4VL
Reserved
3
3
ATDPE3
—
—
MULT
IICEN
TCF
Bit 0
Bit 0
ATDPE0
—
—
0
ICR
IICIE
IAAS
MST
BUSY
IIC1D
Reserved
4
4
ATDPE4
—
—
ADDR
PRS
ATDCH
2
1
2
1
ATDPE2
ATDPE1
—
—
—
—
TX
ARBL
TXAK
RSTA
0
0
0
SRW
IICIF
RXAK
—
—
CLKSA
11
3
11
3
ELS0B
11
3
ELS1B
11
3
ELS2B
11
3
ELS3B
11
3
ELS4B
11
3
—
—
—
—
PS2
10
2
10
2
ELS0A
10
2
ELS1A
10
2
ELS2A
10
2
ELS3A
10
2
ELS4A
10
2
—
—
—
—
PS1
9
1
9
1
0
9
1
0
9
1
0
9
1
0
9
1
0
9
1
—
—
—
—
PS0
Bit 8
Bit 0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
—
—
DATA
—
—
TOF
Bit 15
Bit 7
Bit 15
Bit 7
CH0F
Bit 15
Bit 7
CH1F
Bit 15
Bit 7
CH2F
Bit 15
Bit 7
CH3F
Bit 15
Bit 7
CH4F
Bit 15
Bit 7
—
—
—
—
TOIE
14
6
14
6
CH0IE
14
6
CH1IE
14
6
CH2IE
14
6
CH3IE
14
6
CH4IE
14
6
—
—
—
—
CPWMS
13
5
13
5
MS0B
13
5
MS1B
13
5
MS2B
13
5
MS3B
13
5
MS4B
13
5
—
—
—
—
CLKSB
12
4
12
4
MS0A
12
4
MS1A
12
4
MS2A
12
4
MS3A
12
4
MS4A
12
4
—
—
MC9S08GB/GT Data Sheet, Rev. 2.3
44
Freescale Semiconductor
Register Addresses and Bit Assignments
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at $1800.
Table 4-3. High-Page Register Summary
Address
$1800
$1801
$1802
$1803 –
$1805
$1806
$1807
$1808
$1809
$180A
$180B–
$180F
$1810
$1811
$1812
$1813
$1814
$1815
$1816
$1817
$1818
$1819–
$181F
$1820
$1821
$1822
$1823
$1824
$1825
$1826
$1827–
$182B
Register Name
SRS
SBDFR
SOPT
Reserved
SDIDH
SDIDL
SRTISC
SPMSC1
SPMSC2
Reserved
DBGCAH
DBGCAL
DBGCBH
DBGCBL
DBGFH
DBGFL
DBGC
DBGT
DBGS
Reserved
FCDIV
FOPT
Reserved
FCNFG
FPROT
FSTAT
FCMD
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
POR
0
COPE
—
—
REV3
ID7
RTIF
LVDF
LVWF
PIN
0
COPT
—
—
REV2
ID6
RTIACK
LVDACK
LVWACK
COP
0
STOPE
—
—
REV1
ID5
RTICLKS
LVDIE
LVDV
ILOP
0
—
—
—
REV0
ID4
RTIE
LVDRE
LVWV
0
0
0
—
—
ID11
ID3
0
LVDSE
PPDF
ICG
0
0
—
—
ID10
ID2
RTIS2
LVDE
PPDACK
LVD
0
BKGDPE
—
—
ID9
ID1
RTIS1
0
PDC
0
BDFR
—
—
—
ID8
ID0
RTIS0
0
PPDC
—
—
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
DBGEN
TRGSEL
AF
—
—
DIVLD
KEYEN
—
0
FPOPEN
FCBEF
FCMD7
—
—
—
—
14
6
14
6
14
6
ARM
BEGIN
BF
—
—
PRDIV8
FNORED
—
0
FPDIS
FCCF
FCMD6
—
—
—
—
13
5
13
5
13
5
TAG
0
ARMF
—
—
DIV5
0
—
KEYACC
FPS2
FPVIOL
FCMD5
—
—
—
—
12
4
12
4
12
4
BRKEN
0
0
—
—
DIV4
0
—
0
FPS1
FACCERR
FCMD4
—
—
—
—
11
3
11
3
11
3
RWA
TRG3
CNT3
—
—
DIV3
0
—
0
FPS0
0
FCMD3
—
—
—
—
10
2
10
2
10
2
RWAEN
TRG2
CNT2
—
—
DIV2
0
—
0
0
FBLANK
FCMD2
—
—
—
—
9
1
9
1
9
1
RWB
TRG1
CNT1
—
—
DIV1
SEC01
—
0
0
0
FCMD1
—
—
—
—
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
RWBEN
TRG0
CNT0
—
—
DIV0
SEC00
—
0
0
0
FCMD0
—
—
Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers
include an 8-byte backdoor key which optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
45
Chapter 4 Memory
Table 4-4. Nonvolatile Register Summary
Address
$FFB0 –
$FFB7
$FFB8 –
$FFBC
$FFBD
$FFBE
$FFBF
1
Register Name
Bit 7
6
5
NVBACKKEY
Reserved
NVPROT
Reserved1
NVOPT
4
3
2
1
Bit 0
—
—
0
—
0
—
—
0
—
SEC01
—
—
0
—
SEC00
8-Byte Comparison Key
—
—
FPOPEN
—
KEYEN
—
—
FPDIS
—
FNORED
—
—
FPS2
—
0
—
—
FPS1
—
0
—
—
FPS0
—
0
This location is used to store the factory trim value for the ICG.
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3
RAM
The MC9S08GB/GT includes static RAM. The locations in RAM below $0100 can be accessed using the
more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to $00FF. In the
MC9S08GB/GT, it is usually best to re-initialize the stack pointer to the top of the RAM so the direct page
RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include
the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the
highest address of the RAM in the Freescale-provided equate file).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP
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