MC9S08JS16LCFK557

Freescale Semiconductor Addendum Document Number: QFN_Addendum Rev. 0, 07/2014 Addendum for New QFN Package Migration This addendum provides the changes to the 98A case outline numbers for products covered in this book. Case outlines were changed because of the migration from gold wire to copper wire in some packages. See the table below for the old (gold wire) package versus the new (copper wire) package. To view the new drawing, go to Freescale.com and search on the new 98A package number for your device. For more information about QFN package use, see EB806: Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages. © Freescale Semiconductor, Inc., 2014. All rights reserved. Part Number MC68HC908JW32 Package Description Original (gold wire) Current (copper wire) package document number package document number 48 QFN 98ARH99048A 98ASA00466D MC9RS08LA8 48 QFN 98ARL10606D 98ASA00466D MC9S08GT16A 32 QFN 98ARH99035A 98ASA00473D MC9S908QE32 32 QFN 98ARE10566D 98ASA00473D MC9S908QE8 32 QFN 98ASA00071D 98ASA00736D MC9S08JS16 24 QFN 98ARL10608D 98ASA00734D MC9S08QG8 24 QFN 98ARL10605D 98ASA00474D MC9S08SH8 24 QFN 98ARE10714D 98ASA00474D MC9RS08KB12 24 QFN 98ASA00087D 98ASA00602D MC9S08QG8 16 QFN 98ARE10614D 98ASA00671D MC9RS08KB12 8 DFN 98ARL10557D 98ASA00672D 6 DFN 98ARL10602D 98ASA00735D MC9S08AC16 MC9S908AC60 MC9S08AC128 MC9S08AW60 MC9S08GB60A MC9S08GT16A MC9S08JM16 MC9S08JM60 MC9S08LL16 MC9S08QE128 MC9S08QE32 MC9S08RG60 MCF51CN128 MC9S08QB8 MC9S08QG8 MC9RS08KA2 Addendum for New QFN Package Migration, Rev. 0 2 Freescale Semiconductor Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08JS16 Rev. 4, 4/2009 MC9S08JS16 MC9S08JS16 Series Covers: MC9S08JS16 MC9S08JS8 MC9S08JS16L MC9S08JS8L Features: • 8-Bit HCS08 Central Processor Unit (CPU) – 48 MHz HCS08 CPU (central processor unit) – 24 MHz internal bus frequency – Support for up to 32 interrupt/reset sources • Memory Options – Up to 16 KB of on-chip in-circuit programmable flash memory with block protection and security options – Up to 512 bytes of on-chip RAM – 256 bytes of USB RAM • Clock Source Options – Clock source options include crystal, resonator, external clock – MCG (multi-purpose clock generator) — PLL and FLL; internal reference clock with trim adjustment • System Protection – Optional computer operating properly (COP) reset with option to run from independent 1 kHz internal clock source or the bus clock – Low-voltage detection – Illegal opcode detection with reset – Illegal address detection with reset • Power-Saving Modes – Wait plus two stops • USB Bootload – Mass erase entire flash array – Partial erase flash array — erase all flash blocks except for the first 1 KB of flash – Program flash • Peripherals – USB — USB 2.0 full-speed (12 Mbps) with dedicated on-chip 3.3 V regulator and transceiver; supports endpoint 0 and up to 6 additional endpoints TBD 20 W-SOIC Case 751D – SPI — One 8- or 16-bit selectable serial peripheral interface module with a receive data buffer hardware match function – SCI — One serial communications interface module with optional 13 bit break. Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge – MTIM — One 8-bit modulo counter with 8-bit prescaler and overflow interrupt – TPM — One 2-channel 16-bit timer/pulse-width modulator (TPM) module; selectable input capture, output compare, and edge-aligned PWM capability on each channel; timer module may be configured for buffered, centered PWM (CPWM) on all channels – KBI — 8-pin keyboard interrupt module – RTC — Real-time counter with binary- or decimal-based prescaler – CRC — Hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16+x12+x5+1 polynomial • Input/Output – Software selectable pullups on ports when used as inputs – Software selectable slew rate control on ports when used as outputs – Software selectable drive strength on ports when used as outputs – Master reset pin and power-on reset (POR) – Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost • Package Options – 24-pin quad flat no-lead (QFN) – 20-pin small outline IC package (SOIC) This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008-2009. All rights reserved. 24 QFN Case 1982-01 Table of Contents 1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .6 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .6 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4 Electrostatic Discharge (ESD) Protection Characteristics8 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 3.7 External Oscillator (XOSC) Characteristics . . . . . . . . .17 3.8 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.9 4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . 3.10 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 21 24 25 26 26 26 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 1 9/1/2008 Initial public released 2 1/8/2009 In Table 7, changed the parameter description of RIDD and S3IDD, the typicals of RIDD were changed as well. 3 3/9/2009 Corrected the 24-pin QFN case number and doc. number information. 4 4/24/2009 Added new parts information about MC9S08JS16L and MC9S08JS8L. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08JS16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08JS16 Series MCU Data Sheet, Rev. 4 2 Freescale Semiconductor MCU Block Diagram 1 MCU Block Diagram The block diagram, Figure 1, shows the structure of the MC9S08JS16 series MCU. ON-CHIP ICE AND DEBUG MODULE (DBG) HCS08 CORE RESET IRQ USB MODULE FULL SPEED USB USB ENDPOINT TRANSCEIVER RAM CPU BDC PTA1/KBIP1/MISO HCS08 SYSTEM CONTROL 8-BIT KEYBOARD INTERRUPT MODULE (KBI) RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT IRQ KBIPx 8 PTA2/KBIP2/MOSI MISO 8-/16-BIT COP PTA0/KBIP0/TPMCH0 LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI) USER FLASH (IN BYTES) MC9S08JS16 = 16,384 MC9S08JS16L = 16,384 MC9S08JS8 = 8,192 MC9S08JS8L = 8,192 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) PORT A BKGD/MS USBDP USBDN MOSI SPSCK SS PTA3/KBIP3/SPSCK PTA4/KBIP4/SS PTA5/KBIP5/TPMCH1 RxD PTA6/KBIP6/RxD TxD PTA7/KBIP7/TxD TPMCH0 USER RAM (IN BYTES) 512 2-CHANNEL TIMER/PWM TPMCH1 MODULE (TPM) Bootloader ROM (IN BYTES) 4096 EXTAL MULTI-PURPOSE CLOCK GENERATOR (MCG) VDD VSS VUSB33 XTAL PORT B PTB3/BLMS 8-BIT MODULO TIMER MODULE (MTIM) VSSOSC PTB0/IRQ/TCLK PTB1/RESET PTB2/BKGD/MS TCLK PTB4/XTAL PTB5/EXTAL LOW-POWER OSCILLATOR 16-BIT Cyclic Redundancy Check Generator MODULE (CRC) SYSTEM VOLTAGE REGULATOR USB 3.3 V VOLTAGE REGULATOR REAL-TIME COUNTER (RTC) NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1). 3. IRQ does not have a clamp diode to VDD. IRQ must not be driven above VDD. 4. RESET contains integrated pullup device if PTB1 enabled as reset pin function (RSTPE = 1). 5. Pin contains integrated pullup device. 6. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device. Figure 1. MC9S08JS16 Series Block Diagram MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 3 Pin Assignments 2 Pin Assignments This section shows the pin assignments in the packages available for the MC9S08JS16 series. Table 1. Pin Availability by Package Pin-Count Pin Number (Package) Highest 24 (QFN) 20 (SOIC) Port Pin Alt 1 Alt 2 1 4 PTB0 2 5 PTB1 3 6 PTB2 4 7 PTB3 5 8 PTA0 6 — NC 7 9 8 IRQ TCLK RESET BKGD MS BLMS KBIP0 TPMCH0 PTA1 KBIP1 MISO 10 PTA2 KBIP2 MOSI 9 11 PTA3 KBIP3 SPSCK 10 12 PTA4 KBIP4 SS 11 13 12 — 13 14 VSS 14 15 USBDN 15 16 USBDP 16 17 VUSB33 17 18 PTA5 18 — NC 19 19 20 VDD NC KBIP5 TPMCH1 PTA6 KBIP6 RxD 20 PTA7 KBIP7 TxD 21 1 PTB4 XTAL 22 2 PTB5 EXTAL 23 3 24 — VSSOSC NC MC9S08JS16 Series MCU Data Sheet, Rev. 4 4 Freescale Semiconductor PTB4/XTAL PTA7/KBIP7/TxD PTA6/KBIP6/RxD 24 23 PTB5/EXTAL VSSOSC NC Pin Assignments 22 21 20 19 18 NC PTB0/IRQ/TCLK 1 17 PTA5/KBIP5/TPMCH1 PTB1/RESET 2 16 VUSB33 PTB2/BKGD/MS 3 24-Pin QFN PTB3/BLMS 4 15 USBDP PTA0/KBIP0/TPMCH0 5 14 USBDN 9 10 11 PTA3/KBIP3/SPSCK PTA4/KBIP4/SS VDD 12 NC 8 PTA2/KBIP2/MOSI 13 VSS 7 PTA1/KBIP1/MISO NC 6 Figure 2. MC9S08JS16 Series in 24-QFN Package PTB4/XTAL 1 20 PTA7/KBIP7/TxD PTB5/EXTAL 2 19 PTA6/KBIP6/RxD VSSOSC 3 18 PTA5/KBIP5/TPMCH1 PTB0/IRQ/TCLK 4 17 VUSB33 PTB1/RESET 5 16 USBDP PTB2/BKGD/MS 6 15 USBDN PTB3/BLMS 7 14 VSS PTA0/KBIP0/TPMCH0 8 13 VDD PTA1/KBIP1/MISO 9 12 PTA4/KBIP4/SS PTA2/KBIP2/MOSI 10 11 PTA3/KBIP3/SPSCK Figure 3. MC9S08JS16 Series in 20-pin SOIC Package MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 5 Electrical Characteristics 3 Electrical Characteristics This chapter contains electrical and timing specifications. 3.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The above classifications are used in the column labeled “C” in applicable tables of this data sheet. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). Table 3. Absolute Maximum Ratings Rating Supply voltage Input voltage Instantaneous maximum current (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature Maximum junction temperature Single pin limit Symbol Value Unit VDD 2.7 to 5.5 V VIn –0.3 to VDD + 0.3 V ID ±25 mA IDD 120 mA Tstg –55 to 150 °C TJ 150 °C MC9S08JS16 Series MCU Data Sheet, Rev. 4 6 Freescale Semiconductor Electrical Characteristics 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. 3.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics Rating Operating temperature range (packaged) Symbol Value Unit TA TL to TH -40 to 85 °C θJA 92 33 °C/W Thermal resistance 1,2,3,4 24-pin QFN 1s 2s2p 20-pin SOIC 1s 2s2p 86 58 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2 Junction to Ambient Natural Convection 3 1s — Single layer board, one signal layer 4 2s2p — Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 7 Electrical Characteristics PD = Pint + PI/OPint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O