MC9S08PA60VLDR

NXP Semiconductors Data Sheet: Technical Data Document Number MC9S08PA4 Rev. 10, 03/2020 MC9S08PA4 MC9S08PA4 Data Sheet Supports: MC9S08PA4(A) Key features • 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across operating temperature range – Supporting up to 40 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 4 KB flash read/program/erase over full operating voltage and temperature – Up to 128 byte EEPROM; 2-byte erase sector; program and erase while executing flash – Up to 512 byte random-access memory (RAM) – Flash and RAM access protection • Power-saving modes – One low-power stop mode; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode • Clocks – Oscillator (XOSC) - loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz – Internal clock source (ICS) - containing a frequencylocked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 2% deviation across whole operating temperature range; up to 20 MHz • System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset • Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints setting during in-circuit debugging – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes • Peripherals – ACMP - one analog comparator with both positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering – ADC - 8-channel, 12-bit resolution; 2.5 µs conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger – FTM - Three 2-channel flex timer modulators modules; 16-bit counter; each channel can be configured for input capture, output compare, edgeor center-aligned PWM mode – RTC - 16-bit real timer counter (RTC) – SCI - one serial communication interface (SCI/ UART) modules optional 13-bit break; full duplex non-return to zero (NRZ); LIN extension support • Input/Output – Up to 18 GPIOs including one output-only pin – One 8-bit keyboard interrupt module (KBI) – Two, ultra-high current sink pins supporting 20 mA source/sink current • Package options – 20-pin SOIC – 20-pin TSSOP – 16-pin TSSOP – 8-pin DFN – 8-pin SOIC NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Table of Contents 1 MCU block diagram...........................................................................3 6.2 Switching specifications............................................................ 16 2 Orderable part numbers......................................................................4 6.2.1 Control timing..............................................................16 3 Part identification............................................................................... 4 6.2.2 Debug trace timing specifications................................17 3.1 Description.................................................................................4 6.2.3 FTM module timing.....................................................18 3.2 Format........................................................................................4 6.3 Thermal specifications...............................................................19 3.3 Fields..........................................................................................5 3.4 Example..................................................................................... 5 6.3.1 7 Thermal characteristics................................................ 19 Peripheral operating requirements and behaviors.............................. 20 4 Parameter Classification.....................................................................5 7.1 External oscillator (XOSC) and ICS characteristics..................20 5 Ratings................................................................................................6 7.2 NVM specifications................................................................... 21 5.1 Thermal handling ratings...........................................................6 7.3 Analog........................................................................................23 5.2 Moisture handling ratings.......................................................... 6 7.3.1 ADC characteristics..................................................... 23 5.3 ESD handling ratings.................................................................6 7.3.2 Analog comparator (ACMP) electricals...................... 25 5.4 Voltage and current operating ratings........................................7 6 8 General............................................................................................... 8 6.1 Nonswitching electrical specifications...................................... 8 Dimensions.........................................................................................26 8.1 Obtaining package dimensions.................................................. 26 9 Pinout................................................................................................. 26 6.1.1 DC characteristics........................................................ 8 9.1 Signal multiplexing and pin assignments.................................. 26 6.1.2 Supply current characteristics...................................... 14 9.2 Device pin assignment...............................................................27 6.1.3 EMC performance........................................................15 10 Revision history................................................................................. 28 MC9S08PA4 Data Sheet, Rev. 10, 03/2020 2 NXP Semiconductors MCU block diagram 1 MCU block diagram Port A CPU PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3 PTA4/ACMPO/BKGD/MS 1 PTA5/IRQ/FTM1CH0/RESET Port B HCS08 CORE PTB0/KBI0P4/RxD0/TCLK0/ADP4 2 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/ADP6 PTB3/KBI0P7/TCLK1/ADP7 PTB4/FTM1CH03 PTB5/FTM1CH1 3 PTB6/XTAL PTB7/EXTAL Port C The block diagram below shows the structure of the MCUs. PTC0 PTC1 PTC2 PTC3 BDC KEYBOARD INTERRUPT MODULE (KBI0) SYSTEM INTEGRATION MODULE (SIM) WDG IRQ 1 kHz OSC LVD INTERRUPT PRIORITY CONTROLLER(IPC) 2-CH FLEX TIMER MODULE (FTM2 ) 2-CH FLEX TIMER MODULE (FTM1) 2-CH FLEX TIMER MODULE (FTM0) SERIAL COMMUNICATION ON-CHIP ICE AND DEBUG MODUE (DBG) USER FLASH MC9S08PA4 = 4,096 bytes INTERFACE (SCI0) ANALOG COMPARATOR (ACMP) REAL-TIME CLOCK (RTC) USER EEPROM MC9S08PA4 = 128 bytes USER RAM MC9S08PA4 = 512 bytes 20 MHz INTERNAL CLOCK SOURCE (ICS) EXTAL XTAL VDD VSS VREFH VDDA VREFL VSSA EXTERNAL OSCILLATOR SOURCE (XOSC) POWER MANAGEMENT CONTROLLER (PMC) 8-CH 12-BIT ANALOG-TO-DIGITAL CONVERTER(ADC) 1. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true open drain when working as output. 3. PTB4 and PTB5 can provide high sink/source current drive. Figure 1. MCU block diagram MC9S08PA4 Data Sheet, Rev. 10, 03/2020 NXP Semiconductors 3 Orderable part numbers 2 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. Table 1. Ordering information Feature Part Number MC9S08PA4(A) VWJ VTJ VTG VSC MTG MSC VDC Max. frequency (MHz) 20 20 20 20 20 Flash memory (KB) 4 4 4 4 4 RAM (B) 512 512 512 512 512 EEPROM (B) 128 128 128 128 128 12-bit ADC 8ch 8ch 8ch 4ch 4ch 2ch+2ch+2ch1 2ch+2ch+2ch1 2ch+2ch+2ch1 2ch+2ch+2ch1, 2 2ch+2ch+2ch1, 2 1 1 1 1 1 Yes Yes Yes Yes Yes 1 1 1 1 1 Yes Yes Yes Yes Yes 2 2 2 - - 16-bit FlexTimer ACMP RTC SCI (LIN Capable) Watchdog 20mA high-drive pins KBI pins 8 8 8 4 4 GPIO 18 18 14 6 6 20-SOIC 20-TSSOP 16-TSSOP 8-SOIC 8-DFN Package 1. FTM2 has no external pins available. 2. FTM1 channel 1 has no external pins available. 3 Part identification 3.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 3.2 Format Part numbers for this device have the following format: MC9S08PA4 Data Sheet, Rev. 10, 03/2020 4 NXP Semiconductors Parameter Classification MC 9 S08 PA AA (V) B CC 3.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values MC Qualification status • MC = fully qualified, general market flow 9 Memory • 9 = flash based S08 Core • S08 = 8-bit CPU PA Device family • PA AA Approximate flash size in KB • 4 = 4 KB (V) Mask set version • (blank) = Any version1 • A = Rev. 2 or later version, this is recommended for new design1 B Operating temperature range (°C) • M = –40 to 125 • V = –40 to 105 CC Package designator • • • • • WJ = 20-SOIC TJ = 20-TSSOP TG = 16-TSSOP DC = 8-DFN SC = 8-SOIC 1. From June 1, 2017, (blank) and A share the same mask set version. 3.4 Example This is an example part number: MC9S08PA4AVWJ 4 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. Table continues on the next page... MC9S08PA4 Data Sheet, Rev. 10, 03/2020 NXP Semiconductors 5 Ratings Table 2. Parameter Classifications (continued) C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 5 Ratings 5.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 125 °C -100 +100 mA 3 ILAT MC9S08PA4 Data Sheet, Rev. 10, 03/2020 6 NXP Semiconductors Ratings 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test. • Test was performed at 125 °C case temperature (Class II). • I/O pins pass +100/-100 mA I-test with IDD current limit at 200 mA. • I/O pins pass +20/-100 mA I-test with IDD current limit at 1000mA. • Supply groups pass 1.5 Vccmax. • RESET pin was only tested with negative I-test due to product conditioning requirement. 5.4 Voltage and current operating ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Symbol Description Min. Max. Unit VDD Supply voltage –0.3 6.0 V IDD Maximum current into VDD — 120 mA Digital input voltage (except RESET, EXTAL, XTAL, or true open drain pin PTB0) –0.3 VDD + 0.3 V Digital input voltage (true open drain pin PTB0) -0.3 6 V Analog1, –0.3 VDD + 0.3 V –25 25 mA VDD – 0.3 VDD + 0.3 V VDIO VAIO ID VDDA RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage 1. All digital I/O pins, except open-drain pin PTB0, are internally clamped to VSS and VDD. PTB0 is only clamped to VSS. MC9S08PA4 Data Sheet, Rev. 10, 03/2020 NXP Semiconductors 7 General 6 General 6.1 Nonswitching electrical specifications 6.1.1 DC characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 3. DC characteristics Symbol C — — VOH C Min Typical1 Max Unit — 2.7 — 5.5 V 5 V, Iload = -5 mA VDD - 0.8 — — V 3 V, Iload = -2.5 mA VDD - 0.8 — — V High current drive pins, high-drive strength2 5 V, Iload = -20 mA VDD - 0.8 — — V 3 V, Iload = -10 mA VDD - 0.8 — — V Max total IOH for all ports 5V — — -100 mA 3V — — -50 — — 0.8 V 3 V, Iload = 2.5 mA — — 0.8 V 5 V, Iload =20 mA — — 0.8 V 3 V, Iload = 10 mA — — 0.8 V — — 100 mA Descriptions Operating voltage Output high voltage All I/O pins, standarddrive strength C C C IOHT VOL D C Output high current Output low voltage All I/O pins, standard- 5 V, Iload = 5 drive strength mA C C High current drive pins, high-drive strength2 C IOLT D Output low current Max total IOL for all ports 5V 3V — — 50 VIH P Input high voltage All digital inputs VDD>4.5V 0.70 × VDD — — VDD>2.7V 0.75 × VDD — — Input low voltage All digital inputs VDD>4.5V — — 0.30 × VDD VDD>2.7V — — 0.35 × VDD C VIL P C V V Vhys C Input hysteresis All digital inputs — 0.06 × VDD — — mV |IIn| P Input leakage current All input only pins (per pin) VIN = VDD or VSS — 0.1 1 µA Table continues on the next page... MC9S08PA4 Data Sheet, Rev. 10, 03/2020 8 NXP Semiconductors Nonswitching electrical specifications Table 3. DC characteristics (continued) Min Typical1 Max Unit VIN = VDD or VSS — 0.1 1 µA Total leakage All input only and I/O VIN = VDD or combined for VSS all inputs and Hi-Z pins — — 2 µA — 30.0 — 50.0 kΩ PTB0 pin — 30.0 — 60.0 kΩ Single pin limit VIN < VSS, VIN > VDD -0.2 — 2 mA -5 — 25 Symbol C Descriptions |IOZ| P Hi-Z (offstate) leakage current |IOZTOT| C RPU P Pullup resistors All digital inputs, when enabled (all I/O pins other than PTB0) RPU3 P Pullup resistors IIC D DC injection current4, 5, 6 All input/output (per pin) Total MCU limit, includes sum of all stressed pins CIn C Input capacitance, all pins — — — 7 pF VRAM C RAM retention voltage — 2.0 — — V 1. Typical values are measured at 25 °C. Characterized, not tested. 2. Only PTB4, PTB5 support ultra high current output. 3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. 4. All functional non-supply pins, except for PTB0, are internally clamped to VSS and VDD. 5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). Table 4. LVD and POR Specification Symbol C VPOR D VLVDH C VLVW1H C VLVW2H C VLVW3H C VLVW4H C VHYSH C Description POR re-arm Min Typ Max Unit 1.5 1.75 2.0 V 4.2 4.3 4.4 V Level 1 falling (LVWV = 00) 4.3 4.4 4.5 V Level 2 falling (LVWV = 01) 4.5 4.5 4.6 V Level 3 falling (LVWV = 10) 4.6 4.6 4.7 V Level 4 falling (LVWV = 11) 4.7 4.7 4.8 V — 100 — mV voltage1, 2 Falling low-voltage detect threshold - high range (LVDV = 1)3 Falling lowvoltage warning threshold high range High range low-voltage detect/warning hysteresis Table continues on the next page... MC9S08PA4 Data Sheet, Rev. 10, 03/2020 NXP Semiconductors 9 Nonswitching electrical specifications Table 4. LVD and POR Specification (continued) 1. 2. 3. 4. Symbol C Description Min Typ Max Unit VLVDL C Falling low-voltage detect threshold - low range (LVDV = 0) 2.56 2.61 2.66 V VLVDW1L C Level 1 falling (LVWV = 00) 2.62 2.7 2.78 V VLVDW2L C Level 2 falling (LVWV = 01) 2.72 2.8 2.88 V VLVDW3L C Level 3 falling (LVWV = 10) 2.82 2.9 2.98 V VLVDW4L C Level 4 falling (LVWV = 11) 2.92 3.0 3.08 V VHYSDL C Low range low-voltage detect hysteresis — 40 — mV VHYSWL C Low range low-voltage warning hysteresis — 80 — mV VBG P Buffered bandgap output 4 1.14 1.16 1.18 V Falling lowvoltage warning threshold low range Maximum is highest voltage that POR is guaranteed. POR ramp time must be longer than 20us/V to get a stable startup. Rising thresholds are falling threshold + hysteresis. Voltage factory trimmed at VDD = 5.0 V, Temp = 25 °C 0.6 0.5 0.4 VDD-VOH(V) 125°C 105°C 0.3 25°C 0.2 -40°C 0.1 0 1 2 3 4 5 6 IOH(mA) Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V) MC9S08PA4 Data Sheet, Rev. 10, 03/2020 10 NXP Semiconductors Nonswitching electrical specifications 1 0.9 0.8 0.7 VDD-VOH(V) 0.6 125°C 0.5 105°C 0.4 25°C 0.3 -40°C 0.2 0.1 0 1 2 3 4 5 6 IOH(mA) Figure 3. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V) 0.7 0.6 0.5 125°C 0.4 VDD-VOH(V) 105°C 0.3 25°C 0.2 -40°C 0.1 0 5 10 15 20 25 IOH(mA) Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V) MC9S08PA4 Data Sheet, Rev. 10, 03/2020 NXP Semiconductors 11 Nonswitching electrical specifications 1.2 1 0.8 VDD-VOH(V) 125°C 105°C 0.6 25°C 0.4 -40°C 0.2 0 0 5 10 15 20 25 30 IOH(mA) Figure 5. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V) 0.5 0.4 VOL(V) 125°C 0.3 105°C 25°C 0.2 -40°C 0.1 0.0 1 2 3 4 5 6 IOL(mA) Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V) MC9S08PA4 Data Sheet, Rev. 10, 03/2020 12 NXP Semiconductors Nonswitching electrical specifications 0.9 0.8 0.7 0.6 VOL(V) 125°C 0.5 105°C 0.4 25°C 0.3 -40°C 0.2 0.1 0 1 2 3 4 5 6 IOL(mA) Figure 7. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V) 0.6 0.5 VOL(V) 0.4 125°C 0.3 105°C 25°C 0.2 -40°C 0.1 0 5 10 15 20 25 IOL(mA) Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V) MC9S08PA4 Data Sheet, Rev. 10, 03/2020 NXP Semiconductors 13 Nonswitching electrical specifications 1 0.9 0.8 0.7 VOL(V) 0.6 125°C 0.5 105°C 0.4 25°C 0.3 -40°C 0.2 0.1 0 5 10 15 20 25 IOL(mA) Figure 9. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V) 6.1.2 Supply current characteristics This section includes information about power supply current in various operating modes. Table 5. Supply current characteristics in operating temperature range Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit 1 C Run supply current FEI mode, all modules on; run from flash RIDD 20 MHz 5 5.43 — mA 10 MHz 3.46 — 1 MHz 1.71 — 5.35 — C 2 C 20 MHz C 10 MHz 3.45 — 1 MHz 1.69 — C C 3 Run supply current FEI mode, all modules off and gated; run from flash RIDD 20 MHz 3 4.51 — 10 MHz 5 3.01 — 1 MHz 1.68 — 4.47 — C 20 MHz C 10 MHz 2.99 — 1 MHz 1.65 — 5.31 7.41 3.17 — 1.25 — 5.29 — 3.17 — P C Run supply current FBE mode, all modules on; run from RAM RIDD 20 MHz 3 5 10 MHz 1 MHz C 20 MHz C 10 MHz 3 mA mA Table continues on the next page... MC9S08PA4 Data Sheet, Rev. 10, 03/2020 14 NXP Semiconductors Nonswitching electrical specifications Table 5. Supply current characteristics in operating temperature range (continued) Num C Parameter Symbol Typical1 Max 1.24 — 4.39 6.59 10 MHz 2.71 — 1 MHz 1.21 — 4.39 — Bus Freq VDD (V) 1 MHz 4 P C 5 Run supply current FBE mode, all modules off and gated; run from RAM RIDD 20 MHz C 10 MHz 2.71 — 1 MHz 1.20 — C Wait mode current FEI mode, all modules on WIDD C 7 5 C C 6 20 MHz C 20 MHz 3.62 — 10 MHz 2.27 — 1 MHz 1.11 — 3.61 — 10 MHz 2.31 — 1 MHz 1.10 — 20 MHz S3IDD C Stop3 mode supply current no clocks active (except 1 kHz LPO clock)2, 3 C ADC adder to stop3 C ADLPC = 1 3 5 3 — 5 1.5 — — 3 0.85 — — — 5 96.0 — — — 3 88.3 — — — 5 129 — 3 126 — Unit mA mA µA µA ADLSMP = 1 ADCO = 1 MODE = 10B ADICLK = 11B 8 C LVD adder to stop34 C 1. 2. 3. 4. µA Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. RTC adder cause