MC9S08PL16SCTG

NXP Semiconductors Data Sheet: Technical Data MC9S08PL16S Data Sheet Document Number MC9S08PL16S Rev. 3, 06/2020 MC9S08PL16S Supports: MC9S08PL16S and MC9S08PL8S Key features • 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across operating temperature range – Supporting up to 30 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 1 KB random-access memory (RAM) – Flash and RAM access protection • Power-saving modes – One low power stop mode; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode • Clocks – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution; 1% deviation across temperature range of 0 ºC to 70ºC, 1.5% deviation across temperature range of –40 ºC to 85 ºC; Up to 20 MHz – Oscillator (XOSC) — Loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz • System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset • Peripherals – ADC - 12-channel, 10-bit resolution; 2.5 µs conversion time; eight-level data FIFO with optional watermark; automatic compare function; 1.7 mV/ºC temperature sensor; internal bandgap reference channel; operation in stop; optional hardware trigger – FTM - Two flex timer modulators (FTM) modules including one 6-channel (FTM2) and one 2-channel (FTM0) backward compatible with TPM modules; 16-bit counter; each channel can be configured for input capture, output compare, edge- or centeraligned PWM mode – MTIM - One modulo timer with 8-bit prescaler and overflow interrupt – SCI - One serial communications interface (SCI/ UART) modules optional 13-bit break; Full duplex non-return to zero (NRZ); LIN extension support – I2C - One inter-integrated circuit module; up to 400 kbps; multi-master operation; programmable slave address; supporting broadcast mode and 10-bit addressing; supporting SMBUS – ACMP - One analog comparator with both positive and negative inputs; selectable voltage reference provided by on-chip 6-bit DAC; separately selectable interrupt on rising and falling comparator output – RTC - 16-bit real timer counter (RTC) – CRC - Cyclic Redundancy Check with programmable 16-/32-bit polynomial generator – KBI — Up to 8 keyboard interrupt inputs • Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints setting during in-circuit debugging – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes • Input/Output – Up to 18 GPIOs including one output-only pin (PTA4) – One 8-bit keyboard interrupt modules (KBI) – One true open drain pin (PTB0) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. • Package options – 20-pin TSSOP – 16-pin TSSOP – 8-pin SOIC MC9S08PL16S Data Sheet, Rev. 3, 06/2020 2 NXP Semiconductors Table of Contents 1 Overview............................................................................................ 4 6.2 Switching specifications............................................................ 17 1.1 MCU block diagram.................................................................. 4 6.2.1 Control timing..............................................................17 1.2 Peripheral register addresses......................................................5 6.2.2 Debug trace timing specifications................................18 1.3 System interconnection..............................................................5 6.2.3 FTM module timing.....................................................19 2 Orderable part numbers......................................................................6 3 Part identification............................................................................... 7 3.1 Description.................................................................................7 6.3 Thermal specifications...............................................................20 6.3.1 7 Thermal characteristics................................................ 20 Peripheral operating requirements and behaviors.............................. 21 3.2 Format........................................................................................7 7.1 External oscillator (XOSC) and ICS characteristics..................21 3.3 Fields..........................................................................................7 7.2 NVM specifications................................................................... 23 3.4 Example..................................................................................... 8 7.3 Analog........................................................................................24 4 Parameter Classification.....................................................................8 7.3.1 ADC characteristics..................................................... 24 5 Ratings................................................................................................9 7.3.2 Analog comparator (ACMP) electricals...................... 26 5.1 Thermal handling ratings...........................................................9 7.4 Communication interfaces......................................................... 27 5.2 Moisture handling ratings.......................................................... 9 5.3 ESD handling ratings.................................................................9 7.4.1 8 5.4 Voltage and current operating ratings........................................10 6 General............................................................................................... 11 6.1 Nonswitching electrical specifications...................................... 11 Inter-Integrated Circuit Interface (I2C) timing............ 27 Dimensions.........................................................................................28 8.1 Obtaining package dimensions.................................................. 28 9 Pinout................................................................................................. 28 9.1 Signal multiplexing and pin assignments.................................. 28 6.1.1 DC characteristics........................................................ 11 9.2 Device pin assignment...............................................................29 6.1.2 Supply current characteristics...................................... 15 10 Hardware design consideration.......................................................... 30 6.1.3 EMC performance........................................................16 11 Revision history................................................................................. 31 MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 3 Overview 1 Overview 1.1 MCU block diagram The block diagram below shows the structure of the MCUs. Port A PTA0/KBI0P0/FTM0CH0/ACMP0IN0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP0IN1/ADP1 PTA2/KBI0P2/RxD0/SDA/ADP2 PTA3/KBI0P3/TxD0/SCL/ADP3 1 PTA4/FTM0CH1O/ACMP0O/BKGD/MS PTA5/IRQ/FTM0CH0/TCLK0/RESET Port B KEYBOARD INTERRUPT PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SDA/ADP6 PTB3/KBI0P7/SCL/TCLK2/ADP7 PTB4/FTM2CH4 PTB5/FTM2CH5 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C HCS08 CORE PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9 PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 MODULE (KBI0) CPU BDC 8-BIT MODULO TIMER (MTIM0) SYSTEM CONTROL MODULE (SYS) WDG IRQ 1 kHz OSC LVD INTERRUPT PRIORITY CONTROLLER(IPC) ON-CHIP ICE AND DEBUG MODUE (DBG) USER FLASH MC9S08PL16S = 16,384 bytes MC9S08PL8S = 8,192 bytes 2-CH FLEX TIMER MODULE (FTM0) 2 6-CH FLEX TIMER MODULE (FTM2) SERIAL COMMUNICATION INTERFACE (SCI0) ANALOG COMPARATOR (ACMP0) REAL-TIME CLOCK (RTC) INTER-INTEGRATED CIRCUIT BUS (IIC) USER RAM MC9S08PL16S = 1,024 bytes MC9S08PL8S = 1,024 bytes 10 MHz INTERNAL CLOCK SOURCE ( ICS) EXTAL XTAL VDD V SS VSS VREFH VDDA VREFL VSSA EXTERNAL OSCILLATOR SOURCE (XOSC) POWER MANAGEMENT CONTROLLER (PMC) 12-CH 10-BIT ANALOG-TO-DIGITAL CONVERTER(ADC) CYCLIC REDUNDANCY CHECK (CRC) 1. PTA4/FTM0CH1O/ACMP0O/BKGD/MS is an output-only pin when used as port pin. 2. PTB0 operates as true-open drain when working as output. Figure 1. MCU block diagram MC9S08PL16S Data Sheet, Rev. 3, 06/2020 4 NXP Semiconductors Overview 1.2 Peripheral register addresses The following table shows the register availability of the devices. Table 1. Peripheral register addresses Address Size (Byte) Peripheral 0x0000-0x0002 3 Port data 0x0010-0x0017 8 ADC 0x0018-0x001B 4 MTIM0 0x0020-0x002A 11 FTM0 0x002C-0x002F 4 ACMP0 0x003B-0x003B 1 IRQ 0x003C-0x003C 1 KBI0 0x003E-0x003F 2 IPC 0x3000-0x300B 12 SYS 0x300C-0x300F 4 SCG 0x3010-0x301F 16 DBG 0x3020-0x302C 13 NVM 0x3038-0x303C 5 ICS 0x303E-0x303E 1 OSC 0x3040-0x3041 2 PMC 0x304A-0x304B 2 SYS (ILLA) 0x3050-0x305A 11 IPC 0x3060-0x3068 9 CRC 0x306A-0x306F 6 RTC 0x3070-0x307B 12 I2C 0x307C-0x307D 2 KBI0 0x3080-0x3087 8 SCI0 0x30AC-0x30AD 2 ADC 0x30B0-0x30B2 3 Port output enable 0x30B8-0x30BA 3 Port input enable 0x30C0-0x30D6 23 FTM2 0x30EC-0x30EF 4 Port filter 0x30F0-0x30F2 3 Port pullup 0x30F8-0x30FF 8 SYS (UUID) MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 5 Orderable part numbers 1.3 System interconnection This device contains a set of system-level logics for module-to-module interconnection for flexible configuration. These interconnections provide the hardware trigger function between modules with least software configuration, which is ideal for infrared communication, serial communication baudrate detection, low-end motor control, metering clock calibration, and other general-purpose applications. RXDCE 00 01 10 11 ADC trg ovf RTC ovf MTIM0 1 0 SCI0 00 01 10 11 0 ovf ICSOUT 1 o DELAY FTM0 RxD0 rxd txd 0 TxD0 1 ch0 1 ch1 0 FTM0CH1 0 ÷2N BUSREF + ACMP0 – 1 FTM2 ADHWTS RXDFE FTMCHS FTMES ACMP output selection SCI0 RxD filter ch0 ch1 ch2 ch3 ch4 ch5 ACIC FTM2CH0 1 0 FTM2CH1 FTM2CH2 FTM2CH3 FTM2CH4 FTM2CH5 RTCC SCI0 TxD modulation RTC capture TXDME SCI0 RxD capture ADC hardware trigger Figure 2. System interconnection diagram 2 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. Table 2. Orderable part numbers summary Feature MC9S08PL16S Part number CTJ MC9S08PL8S CSC1 CTG CTJ CSC1 CTG Max. frequency (MHz) 20 20 20 20 20 20 Flash memory (KB) 16 16 16 8 8 8 RAM (KB) 1 1 1 1 1 1 Table continues on the next page... MC9S08PL16S Data Sheet, Rev. 3, 06/2020 6 NXP Semiconductors Part identification Table 2. Orderable part numbers summary (continued) Feature MC9S08PL16S Part number CTJ MC9S08PL8S CSC1 CTG CTJ CSC1 CTG 10-bit ADC 12ch 8ch 4ch 12ch 8ch 4ch ACMP 1 1 1 1 1 1 16-bit FlexTimer 6ch+2ch 2ch+2ch 2ch 6ch+2ch 2ch+2ch 2ch 8-bit Modulo timer 1 1 1 1 1 1 RTC Yes Yes Yes Yes Yes Yes I2C 1 1 1 1 1 1 SCI (LIN Capable) 1 1 1 1 1 1 WCOP Yes Yes Yes Yes Yes Yes CRC Yes Yes Yes Yes Yes Yes KBI pins 8 8 4 8 8 4 GPIO 18 14 6 18 14 6 Package 20-TSSOP 16-TSSOP 8-SOIC 20-TSSOP 16-TSSOP 8-SOIC 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. 3 Part identification 3.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 3.2 Format Part numbers for this device have the following format: MC 9 S08 PL AA S B CC 3.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 7 Parameter Classification Field Description Values MC Qualification status • MC = fully qualified, general market flow 9 Memory • 9 = flash based S08 Core • S08 = 8-bit CPU PL Device family • PL AA Approximate flash size in KB • 16 = 16 KB • 8 = 8 KB S Sub-family • S B Operating temperature range (°C) • C = -40 to 85 CC Package designator • TJ = 20-TSSOP • TG = 16-TSSOP • SC = 8-SOIC 3.4 Example This is an example part number: MC9S08PL16SCTG 4 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. MC9S08PL16S Data Sheet, Rev. 3, 06/2020 8 NXP Semiconductors Ratings 5 Ratings 5.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 5.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 125 °C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test. • Test was performed at 125 °C case temperature (Class II). • I/O pins pass +100/-100 mA I-test with IDD current limit at 400 mA. • I/O pins pass +30/-100 mA I-test with IDD current limit at 1000mA. • Supply groups pass 1.5 Vccmax. • RESET_b pin was only tested with negative I-test due to product conditioning requirement. MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 9 Ratings 5.4 Voltage and current operating ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Symbol Description Min. Max. Unit VDD Supply voltage –0.3 6.0 V IDD Maximum current into VDD — 120 mA Digital input voltage (except RESET, EXTAL, XTAL, or true open drain pin ) –0.3 VDD + 0.3 V Digital input voltage (true open drain pin ) -0.3 6 V Analog1, –0.3 VDD + 0.3 V –25 25 mA VDD – 0.3 VDD + 0.3 V VDIO VAIO ID VDDA RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage 1. All digital I/O pins, except open-drain pin , are internally clamped to VSS and VDD. is only clamped to VSS. MC9S08PL16S Data Sheet, Rev. 3, 06/2020 10 NXP Semiconductors General 6 General 6.1 Nonswitching electrical specifications 6.1.1 DC characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 4. DC characteristics Symbol C — — VOH P Operating voltage Output high voltage All I/O pins, standarddrive strength C IOHT VOL D Output high current P Output low voltage Max total IOH for all ports VIH D P C VIL Typical1 Max Unit — 2.7 — 5.5 V 5 V, Iload = -5 mA VDD - 0.8 — — V 3 V, Iload = -2.5 mA VDD - 0.8 — — V 5V — — -100 mA 3V — — -50 — — 0.8 V 3 V, Iload = 2.5 mA — — 0.8 V mA All I/O pins, standard- 5 V, Iload = 5 drive strength mA C IOLT Min Descriptions P C Output low current Max total IOL for all ports 5V — — 100 3V — — 50 Input high voltage All digital inputs VDD>4.5V 0.70 × VDD — — VDD>2.7V 0.75 × VDD — — Input low voltage All digital inputs VDD>4.5V — — 0.30 × VDD V V VDD>2.7V — — 0.35 × VDD Vhys C Input hysteresis All digital inputs — 0.06 × VDD — — mV |IIn| P Input leakage current All input only pins (per pin) VIN = VDD or VSS — 0.1 1 µA |IOZ| P Hi-Z (offstate) leakage current All input/output (per pin) VIN = VDD or VSS — 0.1 1 µA |IOZTOT| C Total leakage All input only and I/O VIN = VDD or combined for VSS all inputs and Hi-Z pins — — 2 µA RPU P 30.0 — 50.0 kΩ Pullup resistors All digital inputs, when enabled (all I/O pins other than PTB0) — Table continues on the next page... MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 11 Nonswitching electrical specifications Table 4. DC characteristics (continued) Symbol C RPU2 P Pullup resistors PTB0 pin IIC D DC injection current3, 4, 5 Single pin limit Min Typical1 Max Unit — 30.0 — 60.0 kΩ VIN < VSS, VIN > VDD -0.2 — 2 mA -5 — 25 Descriptions Total MCU limit, includes sum of all stressed pins CIn C Input capacitance, all pins — — — 7 pF VRAM C RAM retention voltage — 2.0 — — V 1. Typical values are measured at 25 °C. Characterized, not tested. 2. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. 3. All functional non-supply pins, except for PTB0, are internally clamped to VSS and VDD. 4. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 5. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). Table 5. LVD and POR Specification Symbol C Description POR re-arm Min Typ Max Unit 1.5 1.75 2.0 V 4.2 4.3 4.4 V Level 1 falling (LVWV = 00) 4.3 4.4 4.5 V Level 2 falling (LVWV = 01) 4.5 4.5 4.6 V Level 3 falling (LVWV = 10) 4.6 4.6 4.7 V Level 4 falling (LVWV = 11) 4.7 4.7 4.8 V voltage1, 2 VPOR D VLVDH C VLVW1H C VLVW2H C VLVW3H C VLVW4H C VHYSH C High range low-voltage detect/warning hysteresis — 100 — mV VLVDL C Falling low-voltage detect threshold - low range (LVDV = 0) 2.56 2.61 2.66 V VLVDW1L C Level 1 falling (LVWV = 00) 2.62 2.7 2.78 V VLVDW2L C Level 2 falling (LVWV = 01) 2.72 2.8 2.88 V VLVDW3L C Level 3 falling (LVWV = 10) 2.82 2.9 2.98 V Falling low-voltage detect threshold - high range (LVDV = 1)3 Falling lowvoltage warning threshold high range Falling lowvoltage warning threshold low range Table continues on the next page... MC9S08PL16S Data Sheet, Rev. 3, 06/2020 12 NXP Semiconductors Nonswitching electrical specifications Table 5. LVD and POR Specification (continued) 1. 2. 3. 4. Symbol C Description Min Typ Max Unit VLVDW4L C Level 4 falling (LVWV = 11) 2.92 3.0 3.08 V VHYSDL C Low range low-voltage detect hysteresis — 40 — mV VHYSWL C Low range low-voltage warning hysteresis — 80 — mV VBG P Buffered bandgap output 4 1.14 1.16 1.18 V Maximum is highest voltage that POR is guaranteed. POR ramp time must be longer than 20us/V to get a stable startup. Rising thresholds are falling threshold + hysteresis. Voltage factory trimmed at VDD = 5.0 V, Temp = 25 °C 0.4 VDD-VOH (V) 0.3 85°C 0.2 25 °C -40 °C 0.1 0 1 2 3 4 5 IOH (mA) Figure 3. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V) MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 13 Nonswitching electrical specifications 0.6 VDD-VOH (V) 0.5 0.4 85°C 0.3 25 °C 0.2 -40 °C 0.1 0 1 2 3 4 5 IOH (mA) Figure 4. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3.5 V) 0.4 VOL (V) 0.3 85°C 0.2 25 °C -40 °C 0.1 0 1 2 3 4 5 IOL (mA) Figure 5. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V) MC9S08PL16S Data Sheet, Rev. 3, 06/2020 14 NXP Semiconductors Nonswitching electrical specifications 0.5 VOL (V) 0.4 0.3 85°C 0.2 25 °C -40 °C 0.1 0 1 2 3 4 5 IOL (mA) Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 3.5 V) 6.1.2 Supply current characteristics This section includes information about power supply current in various operating modes. Table 6. Supply current characteristics in operating temperature range Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit 1 C Run supply current FEI mode, all modules on; run from flash RIDD 20 MHz 5 mA C 2 5.60 — 10 MHz 3.91 — 1 MHz 2.34 — 5.57 — C 20 MHz C 10 MHz 3.91 — 1 MHz 2.34 — 4.44 — 3.34 — 2.29 — 4.43 — C C Run supply current FEI mode, all modules off and gated; run from flash RIDD 20 MHz 3 5 10 MHz 1 MHz C 20 MHz 3 C 10 MHz 3.34 — 1 MHz 2.29 — mA Table continues on the next page... MC9S08PL16S Data Sheet, Rev. 3, 06/2020 NXP Semiconductors 15 Nonswitching electrical specifications Table 6. Supply current characteristics in operating temperature range (continued) Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit 3 P Run supply current FBE mode, all modules on; run from RAM RIDD 20 MHz 5 5.52 7 mA 10 MHz 3.51 — 1 MHz 1.70 — 5.51 — C 4 C 20 MHz C 10 MHz 3.50 — 1 MHz 1.69 — 4.37 5.5 2.94 — 1.64 — 4.36 — P C 5 Run supply current FBE mode, all modules off and gated; run from RAM RIDD 10 MHz 1 MHz 20 MHz C 10 MHz 2.93 — 1 MHz 1.64 — 4.17 — 10 MHz 2.87 — 1 MHz 1.64 — 4.16 — 10 MHz 2.87 — 1 MHz 1.63 — C Wait mode current FEI mode, all modules on WIDD C 7 5 C C 6 20 MHz 3 C 20 MHz 20 MHz S3IDD C Stop3 mode supply current no clocks active (except 1 kHz LPO clock)2, 3 C ADC adder to stop3 C ADLPC = 1 3 5 3 — 5 1.3 — — 3 1.2 — — — 5 85 — — — 3 80 — — — 5 126 — 3 123 — mA mA µA µA ADLSMP = 1 ADCO = 1 MODE = 10B ADICLK = 11B 8 C LVD adder to stop34 C 1. 2. 3. 4. µA Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. RTC adder cause