NXP Semiconductors
Data Sheet: Technical Data
Document Number: MC9S08QL8
Rev. 1, 07/2018
An Energy Efficient Solution by NXP
MC9S08QL8 Series
Covers: MC9S08QL8 and
MC9S08QL4
Features
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 3.6 V to 1.8 V across temperature
range of –40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Up to 8 KB flash memory read/program/erase over full
operating voltage and temperature
– Up to 512 bytes random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Two very low power stop modes
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low power run
– Low power wait
– 6 s typical wakeup time from stop3 mode
– Typical stop current of 250 nA at 3 V, 25 °C
• Clock Source Options
– Oscillator (XOSC) — Very low-power, loop-control
Pierce oscillator; crystal or ceramic resonator range of
31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports bus
frequencies from 1 MHz to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
MC9S08QL8
20-Pin TSSOP
Case 948E
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
– ADC — 8-channel, 12-bit resolution; 2.5 s conversion
time; automatic compare function; 1.7 mV/°C
temperature sensor; internal bandgap reference channel;
operation in stop3; fully functional from 3.6 V to 1.8 V.
– ACMP — Analog comparator with selectable interrupt
on rising, falling, or either edge of comparator output;
compare option to fixed internal bandgap reference
voltage; output can be tied internally to TPM input
capture; operation in stop3
– TPM — One 1-channel timer/pulse-width modulator
(TPM) module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on
each channel; ACMP output can be tied internally to
input capture
– MTIM — 8-bit modulo timer module with optional
prescaler
– RTC — (Real-time counter) 8-bit modulo counter with
binary or decimal based prescaler; external clock source
for precise time base, time-of-day, calendar or task
scheduling functions; free running on-chip low power
oscillator (1 kHz) for cyclic wakeup without external
components; runs in all MCU modes
– SCI — Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended
break detection; wakeup on active edge
– KBI — 8-pin keyboard interrupt with selectable edge
and level detection modes
• Input/Output
– 18 GPIOs include one input-only and one output-only
pin.
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins except PTA5.
• Package Options
– 20-pin TSSOP, 16-pin TSSOP
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
© 2018 NXP B.V. All rights reserved.
16-Pin TSSOP
Case 948F
Table of Contents
1.
2.
3.
4.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2. Parameter Classification . . . . . . . . . . . . . . . . . . . 7
4.3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . 7
4.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . 8
4.5. ESD Protection and Latch-Up Immunity . . . . . . . 9
4.6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
4.7. Supply Current Characteristics . . . . . . . . . . . . . 14
4.8. External Oscillator (XOSC) Characteristics . . . 15
4.9. Internal Clock Source (ICS) Characteristics . . . 17
4.10. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . 19
4.10.1.Control Timing . . . . . . . . . . . . . . . . . . . . 19
4.10.2.TPM Module Timing . . . . . . . . . . . . . . .
4.11. Analog Comparator (ACMP) Electricals . . . . . .
4.12. ADC Characteristics . . . . . . . . . . . . . . . . . . . . .
4.13. Flash Specifications . . . . . . . . . . . . . . . . . . . . .
4.14. EMC Performance . . . . . . . . . . . . . . . . . . . . . .
5. Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. Package Information . . . . . . . . . . . . . . . . . . . . . . . . .
6.1. Mechanical Drawings . . . . . . . . . . . . . . . . . . . .
20
21
21
25
26
27
28
28
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://nxp.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
0
06/12/2018
Initial creation.
1
07/16/2018
Added TSSOP 20 package mechanical drawing.
Related Documentation
Find the most current versions of all documents at: http://www.nxp.com
Reference Manual
(MC9S08QL8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
2
NXP Semiconductors
Ordering Information
1
Ordering Information
Table 1. Ordering Information
Part Number
MC9S08QL4
CTJ
CTG
CTJ
CTG
Max. frequency (MHz)
20
20
20
20
Flash memory (KB)
8
8
4
4
RAM (B)
512
512
256
256
12-bit ADC
8 ch
8 ch
8 ch
8 ch
1
1
1
1
1 ch
1 ch
1 ch
1 ch
1
1
1
1
Yes
Yes
Yes
Yes
SCI (LIN Capable)
1
1
1
1
KBI pins
8
8
8
8
GPIO1
18
14
18
14
20-TSSOP
16-TSSOP
20-TSSOP
16-TSSOP
ACMP
16-bit TPM
8-bit Modulo timer
RTC
Package
1
MC9S08QL8
Port I/O count includes the output-only PTA4 and the input-only PTA5 pins.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
3
MCU Block Diagram
2
MCU Block Diagram
The block diagram shows the structure of the MC9S08QL8 MCU.
PORT A
HCS08 CORE
BDC
ANALOG COMPARATOR
(ACMP)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
IRQ
VREFL/VSSA
VREFH/VDDA
LVD
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
8-BIT MODULO TIMER
MODULE (MTIM)
REAL-TIME COUNTER
(RTC)
USER FLASH
(MC9S08QL8 = 8192 BYTES)
(MC9S08QL4 = 4096 BYTES)
PTB6/XTAL
PTB5/TPMCH0
PTB4
PTB3/KBIP7/ADP7
PTB2/KBIP6/ADP6
PTB1/KBIP5/TxD/ADP5
16-BIT TIMER/PWM
MODULE (TPM)
USER RAM
(MC9S08QL8 = 512 BYTES)
(MC9S08QL4 = 256 BYTES)
PTA5/IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/ADP3
PTA2/KBIP2/ADP2
PTA1/KBIP1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP
PTB7/EXTAL
PORT B
HCS08 SYSTEM CONTROL
PTB0/KBIP4/RxD/ADP4
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
KEYBOARD INTERRUPT
(KBI)
20 MHz INTERNAL CLOCK
SOURCE (ICS)
PORT C
CPU
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
PTC3
PTC2
PTC1
PTC0
VSS
VDD
VOLTAGE REGULATOR
pins not available on 16-pin package
1
VDDA/VREFH and VSSA/VREFL are double bonded to VDD and VSS
Figure 1. MC9S08QL8 Series Block Diagram
MC9S08QL8 Series MCU Data Sheet, Rev. 1
4
NXP Semiconductors
Pin Assignments
3
Pin Assignments
This chapter shows the pin assignments for the MC9S08QL8 series devices.
Table 2. Pin Availability by Package Pin-Count
Pin
Number
Highest
20
20
Port Pin
Priority
Alt 4
EXTAL
XTAL
TPMCH01
KBIP7
ADP7
ADP6
TPMCH0
1
TPMCH0 pin can be repositioned using at PTB5 TPMCH0PS in SOPT2,
default reset location is PTA0.
2 If ADC and ACMP are enabled, both modules will have access to the pin.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
5
Pin Assignments
PTA5/IRQ/TCLK/RESET
1
20
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA4/ACMPO/BKGD/MS
2
19
PTA1/KBIP1/ADP1/ACMP–
VDD
3
18
PTA2/KBIP2/ADP2
VSS
4
17
PTA3/KBIP3/ADP3
PTB7/EXTAL
5
16
PTB0/KBIP4/RxD/ADP4
PTB6/XTAL
6
15
PTB1/KBIP5/TxD/ADP5
PTB5/TPMCH0
7
14
PTB2/KBIP6/ADP6
PTB4
8
13
PTB3/KBIP7/ADP7
PTC3
9
12
PTC0
PTC2
10
11
PTC1
Pins shown in bold type are lost in the next lower pin count package.
Figure 2. MC9S08QL8 Series in 20-Pin TSSOP Package
PTA5/IRQ/TCLK/RESET
1
16
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA4/ACMPO/BKGD/MS
2
15
PTA1/KBIP1/ADP1/ACMP–
VDD
3
14
PTA2/KBIP2/ADP2
VSS
4
13
PTA3/KBIP3/ADP3
PTB7/EXTAL
5
12
PTB0/KBIP4/RxD/ADP4
PTB6/XTAL
6
11
PTB1/KBIP5/TxD/ADP5
PTB5/TPMCH0
7
10
PTB2/KBIP6/ADP6
PTB4
8
9
PTB3/KBIP7/ADP7
Figure 3. MC9S08QL8 Series in 16-Pin TSSOP Package
MC9S08QL8 Series MCU Data Sheet, Rev. 1
6
NXP Semiconductors
Electrical Characteristics
4
Electrical Characteristics
4.1
Introduction
This chapter contains electrical and timing specifications for the MC9S08QL8 series of microcontrollers
available at the time of publication.
4.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
4.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
7
Electrical Characteristics
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
25
mA
Tstg
–55 to 150
C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
4.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
TA
TL to TH
–40 to 85
C
Maximum junction temperature
TJM
95
C
Thermal resistance 16-pin TSSOP
JA
129
C/W
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)
Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
MC9S08QL8 Series MCU Data Sheet, Rev. 1
8
NXP Semiconductors
Electrical Characteristics
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
4.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Latch-up
Description
Symbol
Value
Unit
Series resistance
R1
1500
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
Series resistance
R1
0
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
9
Electrical Characteristics
Table 7. ESD and Latch-Up Protection Characteristics
Rating1
No.
1
4.6
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
2000
—
V
2
Charge device model (CDM)
VCDM
500
—
V
3
Latch-up current at TA = 85C
ILAT
100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
1
Characteristic
P Operating Voltage
P
Output high
voltage
C
3
D
Output high
current
P
Output low
voltage
C
5
D
Min
Typical1
Max
Unit
VDD
—
1.8
—
3.6
V
VDD > 1.8 V,
ILoad = –2 mA
VDD – 0.5
—
—
VDD > 2.7 V,
ILoad = –10 mA
All I/O pins,
high-drive strength
VDD – 0.5
—
—
VDD > 1.8V,
ILoad = –2 mA
VDD – 0.5
—
—
Max total IOH for all ports
VOUT < VDD
0
—
–80
VDD > 1.8 V,
ILoad = 0.6 mA
—
—
0.5
VDD > 2.7 V,
ILoad = 10 mA
—
—
0.5
VDD > 1.8 V,
ILoad = 3 mA
—
—
0.5
VOUT VSS
0
—
80
VDD 2.7 V
0.70 x VDD
—
—
VOH
IOHT
All I/O pins,
low-drive strength
C
4
Condition
All I/O pins,
low-drive strength
C
2
Symbol
Output low
current
6
P Input high
C voltage
7
P Input low
C voltage
8
C
9
Input
P leakage
current
10
Hi-Z
(off-state)
P
leakage
current
Input
hysteresis
All I/O pins,
high-drive strength
VOL
Max total IOL for all ports
IOLT
all digital inputs
VIH
VDD 1.8 V
0.85 x VDD
—
—
VDD 2.7 V
—
—
0.35 x VDD
VDD 1.8 V
—
—
0.30 x VDD
V
mA
V
mA
V
all digital inputs
VIL
all digital inputs
Vhys
—
0.06 x VDD
—
—
mV
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
—
200
nA
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
—
200
nA
MC9S08QL8 Series MCU Data Sheet, Rev. 1
10
NXP Semiconductors
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
2
3
4
5
6
7
Symbol
Condition
Min
Typical1
Max
Unit
VIn = VDD or VSS
—
—
2
A
10
Total
leakage
combined
C
for all inputs
and Hi-Z
pins
11
Pullup,
P Pulldown
resistors
all digital inputs except
PTA5/IRQ/TCLK/RESET,
when enabled
RPU,
RPD
—
17.5
—
52.5
k
12
Pullup,
C Pulldown
resistors
PTA5/IRQ/TCLK/RESET,
when enabled2
RPU,
RPD
—
17.5
—
52.5
k
–0.2
—
0.2
mA
–5
—
5
mA
13
1
Characteristic
DC injection
D current 3, 4,
5
All input only and I/O |IOZTOT|
Single pin limit
Total MCU limit, includes
sum of all stressed pins
14
C Input Capacitance, all pins
15
C RAM retention voltage
6
IIC
VIN < VSS, VIN > VDD
CIn
—
—
—
8
pF
VRAM
—
—
0.6
1.0
V
16
C POR re-arm voltage
VPOR
—
0.9
1.4
2.0
V
17
D POR re-arm time
tPOR
—
10
—
—
s
18
P Low-voltage detection threshold
VLVD
VDD falling
VDD rising
1.80
1.88
1.84
1.92
1.88
1.96
V
19
P Low-voltage warning threshold
VLVW
VDD falling
VDD rising
2.08
2.14
2.26
V
20
C
Vhys
—
—
80
—
mV
21
P Bandgap Voltage Reference7
VBG
—
1.15
1.17
1.18
V
Low-voltage inhibit reset/recover
hysteresis
Typical values are measured at 25 C. Characterized, not tested
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear lower when
measured externally on the pin.
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 3.0 V, Temp = 25 C
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
11
Electrical Characteristics
PULL-UP RESISTOR (k)
PULLDOWN RESISTANCE (k)
PULLUP RESISTOR TYPICALS
40
85C
25C
–40C
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
PULLDOWN RESISTOR TYPICALS
85C
25C
–40C
40
35
30
25
20
1.8
3.6
2.3
2.8
VDD (V)
3.3
3.6
Figure 4. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
TYPICAL VOL VS IOL AT VDD = 3.0 V
1.2
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
85C
25C
–40C
0.6
0.4
0.2
0.1
85C, IOL = 2 mA
25C, IOL = 2 mA
–40C, IOL = 2 mA
0.05
0
0
0
5
10
IOL (mA)
15
1
20
2
3
VDD (V)
4
Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
0.4
85C
25C
–40C
0.8
0.4
0.2
0.2
0.1
0
0
0
85C
25C
–40C
0.3
0.6
VOL (V)
VOL (V)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
10
20
30
IOL = 10 mA
IOL = 6 mA
IOL = 3 mA
1
2
3
4
VDD (V)
IOL (mA)
Figure 6. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
MC9S08QL8 Series MCU Data Sheet, Rev. 1
12
NXP Semiconductors
Electrical Characteristics
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
85C
25C
–40C
1
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.25
VDD – VOH (V)
VDD – VOH (V)
1.2
0.8
0.6
0.4
85C, IOH = 2 mA
25C, IOH = 2 mA
–40C, IOH = 2 mA
0.2
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA))
–15
–20
1
2
VDD (V)
3
4
Figure 7. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VDD – VOH VS VDD AT SPEC IOH
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
0.8
VDD – VOH (V)
VDD – VOH (V)
0.4
85C
25C
–40C
0.6
0.4
0.2
0
0
–5
–10
–15
–20
IOH (mA)
–25
–30
85C
25C
–40C
0.3
0.2
IOH = –10 m
IOH = –6 mA
0.1
IOH = –3 mA
0
1
2
3
4
VDD (V)
Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
13
Electrical Characteristics
4.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Num
1
2
C
P
T
T
T
T
3
Parameter
Symbol
Run supply current
FEI mode, all modules on
RIDD
Run supply current
FEI mode, all modules off
RIDD
Run supply current
LPRS=0, all modules off
RIDD
T
4
5
6
7
8
1
T
T
T
T
Run supply current
LPRS=1, all modules off
RIDD
Wait mode supply current
FEI mode, all modules off
WIDD
Wait mode supply current
LPRS = 1, all mods off
WIDD
Bus
Freq
10 MHz
1 MHz
1 MHz
16 kHz
FBILP
16 kHz
FBELP
3
1 MHz
—
C
3
10 MHz
16 kHz
FBELP
Typical1
Max
5.60
6
0.80
—
3.60
—
0.75
—
165
3
C
S2IDD
3
16 kHz
FBELP
—
Stop2 mode supply current
3
10 MHz
P
P
VDD
(V)
105
7.3
mA
–40 to 85C
mA
–40 to 85C
A
–40 to 85C
—
—
—
290
—
1
Temp
(C)
—
570
3
Unit
—
A
–40 to 85C
A
–40 to 85C
A
–40 to 85C
0.25
0.65
–40 to 25C
0.5
0.8
70C
—
1
2
—
0.2
0.5
0.3
0.6
70C
3
85C
–40 to 25C
C
—
C
—
0.7
1.6
85C
P
—
0.45
0.80
–40 to 25C
C
—
1
1.8
70C
—
3
5.8
—
0.3
0.6
0.8
1.5
70C
2.5
5.0
85C
P
C
Stop3 mode supply current
no clocks active
S3IDD
C
—
C
—
2
A
3
2
A
85C
–40 to 25C
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
14
NXP Semiconductors
Electrical Characteristics
Table 10. Stop Mode Adders
Temperature
Num
Parameter
Condition
Units
–40C
25C
70C
85C
50
75
100
150
nA
1000
1000
1100
1500
nA
1
T
LPO
—
2
T
ERREFSTEN
RANGE = HGO = 0
3
T
IREFSTEN1
—
63
70
77
81
A
4
T
RTC
Does not include clock source
current
50
75
100
150
nA
5
T
LVD1
LVDSE = 1
90
100
110
115
A
Not using the bandgap (BGBE = 0)
18
20
22
23
A
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
95
106
114
120
A
6
T
7
1
C
T
1
ACMP
1
ADC
Not available in stop2 mode.
4.8
External Oscillator (XOSC) Characteristics
Reference Figure 9 and Figure 10 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85C Ambient)
Num
1
2
C
Characteristic
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
Load capacitors
Low range (RANGE=0), low power (HGO=0)
D
Other oscillator settings
3
Feedback resistor
Low range, low power (RANGE = 0, HGO = 0)2
D
Low range, high gain (RANGE = 0, HGO = 1)
High range (RANGE = 1, HGO = X)
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
8 MHz
4 MHz
1 MHz
5
Crystal start-up time 4
Low range, low power
Low range, high gain
C
High range, low power
High range, high gain
Symbol
Min
Typ1
Max
Unit
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
See Note 2
See Note 3
C1,C2
RF
RS
t
CSTL
t
CSTH
—
—
—
—
10
1
—
—
—
—
—
—
—
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
600
400
5
15
—
—
—
—
M
k
ms
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
15
Electrical Characteristics
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85C Ambient)
Num
6
C
Characteristic
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
D
FBE or FBELP mode
Symbol
Min
Typ1
Max
Unit
fextal
0.03125
0
—
—
20
20
MHz
1
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.
3
See crystal or resonator manufacturer’s recommendation.
4
Proper PC board layout procedures must be followed to achieve specifications.
2
XOSCVLP
EXTAL
XTAL
RF
C1
RS
Crystal or Resonator
C2
Figure 9. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 10. Typical Crystal or Resonator Circuit: Low Range/Low Power
MC9S08QL8 Series MCU Data Sheet, Rev. 1
16
NXP Semiconductors
Electrical Characteristics
4.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient)
Symbol
Min.
Typical1
Max.
Unit
Average internal reference frequency — factory trimmed
at VDD = 3.6 V and temperature = 25 C
fint_t
—
32.768
—
kHz
P
Internal reference frequency — user trimmed
fint_ut
31.25
—
39.06
kHz
3
T
Internal reference start-up time
tIRST
—
60
100
s
4
P
DCO output frequency range — Low range (DRS = 00)
trimmed2
fdco_t
16
—
20
MHz
5
P
DCO output frequency2
Reference = 32768 Hz and DMX32 = 1
fdco_DMX32
—
19.92
—
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (using FTRIM)
fdco_res_t
—
0.1
0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (not using FTRIM)
fdco_res_t
—
0.2
0.4
%fdco
8
C
Total deviation of DCO output from trimmed frequency3
Over full voltage and temperature range
Over fixed voltage and temperature range of 0 to 70 C
fdco_t
—
–1.0 to 0.5
0.5
2
1
%fdco
10
C FLL acquisition time4
tAcquire
—
—
1
ms
11
C
CJitter
—
0.02
0.2
%fdco
Num
C
1
P
2
Characteristic
Long term jitter of DCO output clock (averaged over 2-ms
interval)5
1
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This parameter is characterized and not tested on each device.
4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
2
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
17
Electrical Characteristics
1.00%
0.50%
Deviation (%)
0.00%
-60
-40
-20
0
20
40
60
80
100
120
-0.50%
-1.00%
TBD
-1.50%
-2.00%
Temperature
Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
MC9S08QL8 Series MCU Data Sheet, Rev. 1
18
NXP Semiconductors
Electrical Characteristics
4.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
4.10.1
Control Timing
Table 13. Control Timing
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
DC
—
10
MHz
D
Internal low power oscillator period
tLPO
700
—
1300
s
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
s
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
—
—
16
23
—
—
—
—
5
9
—
—
—
4
—
Num
C
1
D
2
9
10
D
D
Rating
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise,
tFall
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise,
tFall
Voltage regulator recovery time
tVRR
ns
ns
s
1
Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 85C.
2
textrst
RESET PIN
Figure 12. Reset Timing
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
19
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 13. IRQ/KBIPx Timing
4.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 14. TPM Input Timing
No.
C
1
D
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTEXT
DC
1/4 fop
MHz
D
External clock period
tTEXT
4
—
tCYC
3
D
External clock high time
tTCLKH
1.5
—
tCYC
4
D
External clock low time
tTCLKL
1.5
—
tCYC
5
D
Input capture pulse width
fICPW
1.5
—
tCYC
tCYC
ipg_clk
tTEXT
EXTERNAL
CLOCK
tTCLKH
tTCLKL
tICPW
INPUT
CAPTURE
Figure 14. Timer Input Capture Pulse
MC9S08QL8 Series MCU Data Sheet, Rev. 1
20
NXP Semiconductors
Electrical Characteristics
4.11
Analog Comparator (ACMP) Electricals
Table 15. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage
VPWR
1.8
—
3.6
V
D
Supply current (active)
IDDAC
—
20
35
A
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
P
Analog input offset voltage
VAIO
—
20
40
mV
C
Analog comparator hysteresis
VH
3.0
9.0
15.0
mV
P
Analog input leakage current
IALKG
—
—
1.0
A
C
Analog comparator initialization delay
tAINIT
—
—
1.0
s
4.12
ADC Characteristics
Table 16. 12-Bit ADC Operating Conditions
Characteristic
Conditions
Absolute
Symbol
Min
Typical1
Max
Unit
VDDA
1.8
—
3.6
V
VDDA
–100
0
100
mV
Supply voltage
Delta to VDD (VDD – VDDA)2
Ground voltage
Delta to VSS (VSS – VSSA)2
VSSA
–100
0
100
mV
Supply Current
Stop, Reset, Module Off
IDDAD
—
0.007
0.8
A
Input Voltage
VADIN
VREFL
—
VREFH
V
Input
Capacitance
CADIN
—
4.5
5.5
pF
Input
Resistance
RADIN
—
5
7
k
—
—
—
—
2
5
—
—
—
—
5
10
—
—
10
0.4
—
8.0
0.4
—
4.0
Comment
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
Analog Source
Resistance
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
RAS
8 bit mode (all valid fADCK)
ADC
Conversion
Clock Freq.
High Speed (ADLPC = 0)
Low Power (ADLPC = 1)
fADCK
k
External to MCU
MHz
1
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
21
Electrical Characteristics
NOTE
VDDA/VSSA pins do not exist in package. The signals are derived internally
by double bonding to VDD/VSS pair of pins.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
VAS
+
–
CAS
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
+
VADIN
–
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure 15. ADC Input Impedance Equivalency Diagram
MC9S08QL8 Series MCU Data Sheet, Rev. 1
22
NXP Semiconductors
Electrical Characteristics
Table 17. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
C
Symbol
Min
Typical1
Max
Unit
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
120
—
A
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
IDDAD
—
202
—
A
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
T
IDDAD
—
288
—
A
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
T
IDDAD
—
0.532
1
mA
T
IDDAD
—
0.007
0.8
A
2
3.3
5
P
fADACK
Characteristic
Conditions
Supply Current
Stop, Reset, Module Off
ADC
Asynchronous
Clock Source
High Speed (ADLPC = 0)
Conversion
Time (Including
sample time)
Sample Time
Total
Unadjusted
Error
Differential
Non-Linearity
Low Power (ADLPC = 1)
Short Sample
(ADLSMP = 0)
Long Sample
(ADLSMP = 1)
Short Sample
(ADLSMP = 0)
Long Sample
(ADLSMP = 1)
T
T
1.25
2
3.3
—
20
—
—
40
—
—
3.5
—
—
23.5
—
—
—
—
—
1.5
—
tADC
tADS
12-bit mode
T
10-bit mode
P
8-bit mode
T
—
0.7
—
12-bit mode
T
—
—
—
10-bit mode
P
—
0.5
—
8-bit mode
T
—
0.3
—
—
—
—
—
0.5
—
—
0.3
—
ETUE
DNL
MHz
ADCK
cycles
ADCK
cycles
LSB2
Comment
tADACK =
1/fADACK
See reference
manual for
conversion
time variances
Includes
quantization
LSB2
Monotonicity and No-Missing-Codes guaranteed
12-bit mode
Integral
Non-Linearity
10-bit mode
8-bit mode
T
C
INL
LSB2
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
23
Electrical Characteristics
Table 17. 12-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Zero-Scale
Error
Full-Scale
Error
Conditions
C
Symbol
Input Leakage
Error
Temp Sensor
Voltage
Max
—
—
—
—
1.5
2.1
C
10-bit mode
P
8-bit mode
T
—
0.5
0.7
12-bit mode
T
—
—
—
10-bit mode
T
—
1
1.5
8-bit mode
T
—
0.5
0.5
—
—
—
—
—
0.5
8-bit mode
—
—
0.5
12-bit mode
—
—
—
0
0.2
4
0
0.1
1.2
—
1.646
—
—
1.769
—
—
701.2
—
EZS
EFS
10-bit mode
10-bit mode
D
D
EQ
EIL
8-bit mode
Temp Sensor
Slope
Typical1
12-bit mode
12-bit mode
Quantization
Error
Min
40C– 25C
25C– 85C
25C
D
m
D
VTEMP25
Unit
Comment
LSB2
VADIN = VSSA
LSB2
VADIN = VDDA
LSB2
LSB2
Pad leakage3 *
RAS
mV/C
mV
1
Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V
N
REFH – VREFL)/2
3
Based on input pad leakage current. Refer to pad electricals.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
24
NXP Semiconductors
Electrical Characteristics
4.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the memory section.
Table 18. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
-40C to 85C
Vprog/erase
1.8
3.6
V
D
Supply voltage for read operation
VRead
1.8
3.6
V
fFCLK
150
200
kHz
tFcyc
5
6.67
s
1
D
Internal FCLK frequency
D
Internal FCLK period (1/FCLK)
D
D
D
D
D
D
Byte program time (random
Byte program time (burst
location)(2)
mode)(2)
tprog
9
tFcyc
tBurst
4
tFcyc
Page erase
time2
tPage
4000
tFcyc
Mass erase
time(2)
tMass
20,000
tFcyc
Byte program
Page erase
current3
current3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
—
10,000
—
100,000
—
—
cycles
tD_ret
15
100
—
years
endurance4
C
Program/erase
TL to TH = –40C to + 85C
T = 25 C
C
Data retention5
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures
DD
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
NXP defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25C using the Arrhenius equation. For additional information on how NXP defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
MC9S08QL8 Series MCU Data Sheet, Rev. 1
NXP Semiconductors
25
4.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult NXP applications notes such as AN2321, AN1050, AN1263, AN2764, and
AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
5
Part Identification
This section contains ordering information for the device numbering system.
Example of the device numbering system:
MC 9 S08 QL 8
Status
(MC = Fully Qualified)
Memory
(9 = Flash-based)
Core
Family
C XX
Package designator (see Table 19)
Temperature range
(C = –40 C to 85 C)
Approximate flash size in KB
Package Information
6
Package Information
Table 19. Package Descriptions
Pin Count
Package Type
Abbreviation
20
Thin Shrink Small Outline Package
16
Thin Shrink Small Outline Package
6.1
Designator
Case No.
Document No.
TSSOP
TJ
948E
98ASH70169A
TSSOP
TG
948F
98ASH70247A
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 19.
MC9S08QL8 Series MCU Data Sheet, Rev. 1
28
NXP Semiconductors
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Document Number MC9S08QL8
Revision 1, 07/2018
