MC9S12DP512CPVE

Freescale Semiconductor DOCUMENT NUMBER 9S12DP512DGV1/D MC9S12DP512 Device Guide V01.25 Covers also MC9S12DT512, MC9S12DJ512, MC9S12A512 Original Release Date: 27 Nov 2001 Revised: 05 Jul 2005 Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2004. All rights reserved. 1 DOCUMENT NUMBER 9S12DP512DGV1/D Revision History Version Revision Effective Number Date Date V01.00 27 Nov 2001 Author Description of Changes 11 Feb 2002 - Initial version based on DP256 V2.09. V01.01 13 Mar 2002 13 Mar 2002 - Updated document formats. - Removed reference to SIM in overview. - Changed XCLKS to PE7 in signal description. - Removed "Oscillator start-up time from POR or STOP" from Oscillator Characterisitcs. - Changed VDD and VDDPLL to 2.35V. - Updated CINS. - Updated IOL/IOH values. - Updated input capacitance. - Updated NVM timing characteristics. V01.02 02 Apr 2002 02 Apr 2002 - Updated document reference (SPI, SCI). V01.03 15 Apr 2002 15 Apr 2002 - Corrected values in device memory map (RAM start, flash protected sector sizes). - Updated document reference (SCI). V01.04 06 Jun 2002 06 Jun 2002 - Changed all operating frequency references to 50MHz EXTAL and removed references to 80 pin LQFP. 05 Jul 2002 - Preface Table "Document References": Changed to full naming for each block. - Table "Interrupt Vector Locations", Column "Local Enable": Corrected several register and bit names. - Table "Signal Properties": Added column "Internal Pull Resistor". - Table "PLL Characteristics": Updated parameters K1 and f1 - Figure "Basic Pll functional diagram": Inserted XFC pin in diagram - Enhanced section "XFC Component Selection" - Added to Sections ATD, ECT and PWM: freeze mode = active BDM mode. V01.05 05 Jul 2002 Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or design.Freescale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. MC9S12DP512 Device Guide V01.25 Version Revision Effective Number Date Date V01.06 24 Jul 2002 24 Jul 2002 Author Description of Changes - Updated SPI electrical characteristics. - Updated Derivative Differences table. - Added ordering number example. - Added Detailed Register Map. - Changed Internal Pull Resistor column of signal table. - Added pull device description for MODC pin. - Corrected XCLKS figure titles. Moved table to section Modes of Operation. - Removed ’1/2’ from BDM in Figure Clock Connections. - Completely reworked section Modes of Operation. Added Chip Configuration Summary and Low Power Mode description. - Changed classification to C for internal pull currents inTable 5V I/O Characteristics. - Changed input leakage to 1uA for all pins. - Updated VREG section and layout recommendation. - Moved Power and Gound Connection Summary table to start of Power Supply Pins section. - Added ROMONE to pinout - Corrected mem map: ’MEBI map x of 3’ - Corrected mem map: KEYEN bits in FSEC. - Added section Printed Circuit Board Layout Proposal. - Corrected addresses in Reserved, CAN and EEP buffer map. - Updated NVM electricals. V01.07 29 Jul 2002 05 Aug 2002 V01.08 21 Aug 2002 21 Aug 2002 - Updated table ’Document References’ - Added section ’Oscillator (OSC) Block Description’ V01.09 24 Sep 2002 24 Sep 2002 - Section HCS12 Core Block Desciption: mentioned alternalte clock of BDM to be equivalent to oscillator clock - Corrected tables 0-1 and 0-2 V01.10 18 Oct 2002 18 Oct 2002 - Added derivatives to cover sheet. - Added part ID for 1L00M maskset. - Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz. V01.11 29 Oct 2002 29 Oct 2002 - Renamed Preface section to Derivative Differences and Document references. - Added A512 derivative. - Updated module set of DJ512 in Table 0-1. - Added details for derivatives without CAN and/or BDLC modules. V01.12 03 Dec 2002 03 Dec 2002 - Corrected several entries in ’Detailed Memory Map’. - Removed footnote on input leakage current from table ’5V I/O Characteristics’. V01.13 08 Jan 2003 08 Jan 2003 - Updated section ’Unsecuring the Microcontroller’. - Updated footnote 1 in table ’Operating Conditions’. V01.14 23 Jan 2003 23 Jan 2003 - Renamed ROMONE pin to ROMCTL. V01.15 28 Feb 2003 28 Feb 2003 - Corrected PE[1,0] pull specification in Signal Properties Summary Table. 3 MC9S12DP512 Device Guide V01.25 Version Revision Effective Number Date Date Author Description of Changes V01.16 31 Mar 2003 31 Mar 2003 - Corrections in App. A ’NVM, Flash and EEPROM’: - Number of words per flash row = 64 - Replaced ’burst programming’ with ’row programming’ - Sector erase size = 1024 bytes - Corrected feature description ECT - Corrected min. bus freq. in table ’Operating Conditions’ V01.17 30 May 2003 30 May 2003 - Replaced references to HCS12 Core Guide with the individual HCS12 Block guides throughout document - Table ’Absolute Maximum Ratings’ corrected footnote on clamp of TEST pin V01.18 23 Jul 2003 23 Jul 2003 - Mentioned ’S12 LRAE’ bootloader in Flash section - Document References: corrected S12 CPU document reference V01.19 24 Jul 2003 24 Jul 2003 - Added part ID for 2L00M maskset. V01.20 01 Sep 2003 01 Sep 2003 - Added part ID for 3L00M maskset. - Added cycle definition to ’CPU 12 Block Description’. - Diagram ’Clock Connections’: Connected Bus Clock to HCS12 Core. - Corrected ’Background Debug Module’ to ’HCS12 Breakpoint’ at address $0028 - $002F in table 1-1. - Corrected ’Blank Check Time Flash’ value in table ’NVM Timing Characteristics’ - Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to ’Oscillator Characteristics’. Updated oscillator description and table note. V01.21 08 Mar 2004 08 Mar 2004 - Added part ID for 4L00M maskset. - Corrected pin name KWP5 in device pinout. V01.22 23 Aug 2004 23 Aug 2004 - Updated VIH,EXTAL and VIL,EXTAL in table ’Oscillator Characteristics’ - Removed item ’Oscillator’ from table ’Operating Conditions’ as already covered in table ’Oscillator Characteristics’ V01.23 09 Feb 2005 09 Feb 2005 - Corrected Flash Row Programming Time in NVM Timing Characteristics V01.24 01 Apr 2005 01 Apr 2005 - Changed TJavg and added footnote to data retention time in NVM Reliability Characteristics V01.25 05 Jul 2005 05 Jul 2005 - Updated NVM Reliability Characteristics MC9S12DP512 Device Guide V01.25 Table of Contents Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Memory Size Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Section 2 Signal Description 2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.3 TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.4 VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.5 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56 2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .56 2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .56 2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .56 2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .56 2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57 2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5 MC9S12DP512 Device Guide V01.25 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH4 / KWH4 / MISO2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . . . .60 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . . . .60 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PM7 / TXCAN3 / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PM6 / RXCAN3 / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5. . . . . . . . . . . . . . .61 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . . .61 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .61 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .61 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .63 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 MC9S12DP512 Device Guide V01.25 2.3.56 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.3.57 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . .65 2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & Internal Voltage Regulator65 2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins . . . . . . . . . . . . . . .65 2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .65 2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.4.7 VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Section 3 System Clock Description 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Section 4 Modes of Operation 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Section 5 Resets and Interrupts 5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Section 6 HCS12 Core Block Description 7 MC9S12DP512 Device Guide V01.25 6.1 6.1.1 6.2 6.2.1 6.3 6.3.1 6.4 6.5 6.5.1 6.6 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . . . .77 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .77 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .78 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Section 7 Clock and Reset Generator (CRG) Block Description 7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Section 8 Oscillator (OSC) Block Description 8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Section 9 Enhanced Capture Timer (ECT) Block Description Section 10 Analog to Digital Converter (ATD) Block Description Section 11 Inter-IC Bus (IIC) Block Description Section 12 Serial Communications Interface (SCI) Block Description Section 13 Serial Peripheral Interface (SPI) Block Description Section 14 J1850 (BDLC) Block Description Section 15 Pulse Width Modulator (PWM) Block Description Section 16 Flash EEPROM 512K Block Description Section 17 EEPROM 4K Block Description Section 18 RAM Block Description Section 19 MSCAN Block Description MC9S12DP512 Device Guide V01.25 Section 20 Port Integration Module (PIM) Block Description Section 21 Voltage Regulator (VREG) Block Description Section 22 Printed Circuit Board Layout Proposal Appendix A Electrical Characteristics A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9 MC9S12DP512 Device Guide V01.25 Appendix B Package Information B.1 B.2 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 MC9S12DP512 Device Guide V01.25 List of Figures Figure 0-1 Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 3-1 Figure 22-1 Figure 22-2 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure A-10 Figure B-1 Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 MC9S12DP512 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 MC9S12DP512 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Pin Assignments in 112-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .82 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .83 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 122 11 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 List of Tables Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 $0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .27 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) . . . . . . . . . . . . . . . . . .27 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $0017 - $0019 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $001A - $001B Device ID Register (Table 1-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4) . . . . . . . . .28 $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .28 $001F - $001F INT map 2 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $0020 - $0027 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $0028 - $002F BKP (HCS12 Breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) . . . . . . . . . . . . . . . . . .29 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .29 $0034 - $003F CRG (Clock and Reset Generator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 $0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) . . . . . . . . . . . . . . . . . .30 $0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .33 $00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel). . . . . . . . . . . . . . . . . . . . . .34 $00C8 - $00CF SCI0 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 $00D0 - $00D7 SCI1 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 $00D8 - $00DF SPI0 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 $00E0 - $00E7 IIC (Inter IC Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 $00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850) . . . . . . . . . . . . . . . . . . . . . . .37 $00F0 - $00F7 SPI1 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 $00F8 - $00FF SPI2 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 $0100 - $010F Flash Control Register (fts512k4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 $0110 - $011B EEPROM Control Register (eets4k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 $011C - $011F Reserved for RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .40 $0140 - $017F CAN0 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .42 $0180 - $01BF CAN1 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .43 13 MC9S12DP512 Device Guide V01.25 $01C0 - $01FF CAN2 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .44 $0200 - $023F CAN3 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .45 $0240 - $027F PIM (Port Integration Module PIM_9DP256) . . . . . . . . . . . . . . . . . . . . . . . .46 $0280 - $02BF CAN4 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .48 $02C0 - $03FF Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 2-2 MC9S12DP512 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . .64 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table A-3 ESD and Latch-up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . .103 Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Table A-18 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Table A-19 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Table A-20 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Table A-21 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 MC9S12DP512 Device Guide V01.25 Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Table 0-1 Derivative Differences1 Modules MC9S12DP512 MC9S12DT512 MC9S12DJ512 MC9S12A512 # of CANs 5 3 2 0 CAN0 ✓ ✓ ✓ — CAN1 ✓ ✓ — — CAN2 ✓ — — — CAN3 ✓ — — — CAN4 ✓ ✓ ✓ — J1850/BDLC ✓ — ✓ — Package 112 LQFP 112 LQFP 112 LQFP 112 LQFP Package Code PV PV PV PV Mask set L00M L00M L00M L00M Temp Options M, V, C M, V, C M, V, C C Notes An errata exists contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office NOTES: 1. ✓: Available for this device, —: Not available for this device The following figure provides an ordering number example for the MC9S12D-Family devices. MC9S12 DP512 C PV Package Option Temperature Option Device Title Controller Family Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Package Options FU = 80 QFP PV = 112 LQFP Figure 0-1 Order Part Number Example 15 MC9S12DP512 Device Guide V01.25 The following items should be considered when using a derivative (Table 0-1): • • • Registers – Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without CAN0. – Do not write or read CAN1registers (after reset: address range $0180 - $01BF), if using a derivative without CAN1. – Do not write or read CAN2 registers (after reset: address range $01C0 - $01FF), if using a derivative without CAN2. – Do not write or read CAN3 registers (after reset: address range $0200 - $023F), if using a derivative without CAN3. – Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a derivative without CAN4. – Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a derivative without BDLC. Interrupts – Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for unused interrupts, if using a derivative without CAN0. – Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for unused interrupts, if using a derivative without CAN1. – Fill the four CAN2 interrupt vectors ($FFA0 - $FFA7) according to your coding policies for unused interrupts, if using a derivative without CAN2. – Fill the four CAN3 interrupt vectors ($FF98 - $FF9F) according to your coding policies for unused interrupts, if using a derivative without CAN3. – Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for unused interrupts, if using a derivative without CAN4. – Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused interrupts, if using a derivative without BDLC. Ports – The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5, PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0. – The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if using a derivative without CAN1. – The CAN2 pin functionality (TXCAN2, RXCAN2) is not available on port PM5 and PM4, if using a derivative without CAN2. – The CAN3 pin functionality (TXCAN3, RXCAN3) is not available on port PM7 and PM6, if using a derivative without CAN3. MC9S12DP512 Device Guide V01.25 – The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7, PM6, PM5 and PM4, if using a derivative without CAN0. – The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a derivative without BDLC. – Do not write MODRR1 and MODRR0 bits of Module Routing Register (PIM_9DP256 Block Guide), if using a derivative without CAN0. – Do not write MODRR3 and MODRR2 bits of Module Routing Register (PIM_9DP256 Block Guide), if using a derivative without CAN4. Document References The Device Guide provides information about the MC9S12DP512 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the individual Block Guides of the implemented modules. In an effort to reduce redundancy, all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-2 for names and versions of the referenced documents throughout the Device Guide. Table 0-2 Document References Block Guide Version Document Order Number HCS12 CPU Reference Manual V02 S12CPUV2/D HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D HCS12 Breakpoint (BKP) Block Guide V01 S12BKPV1/D Clock and Reset Generator (CRG) Block Guide V04 S12CRGV4/D Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block Guide V01 S12ECT16B8V1/D Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block Guide V02 S12ATD10B8CV2/D Inter IC Bus (IIC) Block Guide V02 S12IICV2/D Asynchronous Serial Interface (SCI) Block Guide V02 S12SCIV2/D Serial Peripheral Interface (SPI) Block Guide V03 S12SPIV3/D Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide V01 S12PWM8B8CV1/D 512K Byte Flash (FTS512K4) Block Guide V01 S12FTS512K4V1/D 4K Byte EEPROM (EETS4K) Block Guide V02 S12EETS4KV2/D Byte Level Data Link Controller -J1850 (BDLC) Block Guide V01 S12BDLCV1/D Freescale Scalable CAN (MSCAN) Block Guide V02 S12MSCANV2/D Voltage Regulator (VREG) Block Guide V01 S12VREGV1/D Port Integration Module (PIM_9DP256) Block Guide1 V03 S12DP256PIMV3/D Oscillator (OSC) Block Guide V02 S12OSCV2/D 17 MC9S12DP512 Device Guide V01.25 NOTES: 1. Reused due to functional equivalence. MC9S12DP512 Device Guide V01.25 Section 1 Introduction 1.1 Overview The MC9S12DP512 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 512K bytes of Flash EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wake up capability, five CAN 2.0 A, B software compatible modules (MSCAN12), and an Inter-IC Bus. The MC9S12DP512 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. 1.2 Features • HCS12 Core – 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing • • – MEBI (Multiplexed External Bus Interface) – MMC (Module Mapping Control) – INT (Interrupt control) – BKP (Breakpoints) – BDM (Background Debug Mode) CRG (Clock and Reset Generation) – Low current Colpitts oscillator or – Pierce oscillator – PLL – COP watchdog – Real Time Interrupt – Clock Monitor 8-bit and 4-bit ports with interrupt functionality 19 MC9S12DP512 Device Guide V01.25 • • • • • • • – Digital filtering – Programmable rising or falling edge trigger Memory – 512K Flash EEPROM – 4K byte EEPROM – 14K byte RAM Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability Five 1M bit per second, CAN 2.0 A, B software compatible modules – Five receive and three transmit buffers – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit – Four separate interrupt channels for Rx, Tx, error and wake-up – Low-pass filter wake-up function – Loop-back for self test operation Enhanced Capture Timer – 16-bit main counter with 7-bit prescaler – 8 programmable input capture or output compare channels – Four 8-bit or two 16-bit pulse accumulators 8 PWM channels – Programmable period and duty cycle – 8-bit 8-channel or 16-bit 4-channel – Separate control for each pulse width and duty cycle – Center-aligned or left-aligned outputs – Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input – Usable as interrupt inputs Serial interfaces – Two asynchronous Serial Communications Interfaces (SCI) – Three Synchronous Serial Peripheral Interface (SPI) Byte Data Link Controller (BDLC) – SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed ( VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit 1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.0 V 2 Digital Logic Supply Voltage 2 VDD -0.3 3.0 V 3 PLL Supply Voltage (2) VDDPLL -0.3 3.0 V 4 Voltage difference VDDX to VDDR and VDDA ∆VDDX -0.3 0.3 V 5 Voltage difference VSSX to VSSR and VSSA ∆VSSX -0.3 0.3 V 6 Digital I/O Input Voltage VIN -0.3 6.0 V 7 Analog Reference VRH, VRL -0.3 6.0 V 8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V 9 TEST input VTEST -0.3 10.0 V 10 Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 ID -25 +25 mA 11 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 IDL -25 +25 mA 12 Instantaneous Maximum Current Single pin limit for TEST 5 IDT -0.25 0 mA 13 Storage Temperature Range T – 65 155 °C stg NOTES: 1. Beyond absolute maximum ratings device might be damaged. 87 MC9S12DP512 Device Guide V01.25 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions Model Human Body Machine Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 3 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin positive negative - 3 3 Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V Latch-up Table A-3 ESD and Latch-up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model (HBM) VHBM 2000 - V 2 C Machine Model (MM) VMM 200 - V 3 C Charge Device Model (CDM) VCDM 500 - V 4 Latch-up Current at TA = 125°C C positive negative ILAT +100 -100 - mA 5 Latch-up Current at TA = 27°C C positive negative ILAT +200 -200 - mA MC9S12DP512 Device Guide V01.25 A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions Rating Symbol Min Typ Max Unit I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.25 V Digital Logic Supply Voltage 1 VDD 2.35 2.5 2.75 V PLL Supply Voltage (1) VDDPLL 2.35 2.5 2.75 V Voltage Difference VDDX to VDDR and VDDA ∆VDDX -0.1 0 0.1 V Voltage Difference VSSX to VSSR and VSSA ∆VSSX -0.1 0 0.1 V fbus 0.25 2 - 25 MHz Operating Junction Temperature Range T J -40 - 100 °C Operating Ambient Temperature Range 3 T A -40 27 85 °C Operating Junction Temperature Range TJ -40 - 120 °C Operating Ambient Temperature Range (3) TA -40 27 105 °C Operating Junction Temperature Range TJ -40 - 140 °C Operating Ambient Temperature Range (3) TA -40 27 125 °C Bus Frequency (MC9S12DP512C, V, M) MC9S12DP512C MC9S12DP512V MC9S12DP512M NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The given operating range applies when this regulator is disabled and the device is powered from an external source. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. 3. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ. A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: 89 MC9S12DP512 Device Guide V01.25 T J = T A + ( P D • Θ JA ) T J = Junction Temperature, [°C ] T A = Ambient Temperature, [°C ] P D = Total Chip Power Dissipation, [W] Θ JA = Package Thermal Resistance, [°C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA 2 P IO = R DSON ⋅ I IO i i ∑ PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ------------ ;for outputs driven low I OL respectively V DD5 – V OH R DSON = ------------------------------------ ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON ⋅ I IO i i ∑ PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. MC9S12DP512 Device Guide V01.25 Table A-5 Thermal Package Characteristics1 Num C Rating Symbol Min Typ Max Unit 1 T Thermal Resistance LQFP112, single sided PCB2 θJA - - 54 oC/W 2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 θJA - - 41 o C/W NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7 A.1.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. 91 MC9S12DP512 Device Guide V01.25 Table A-6 5V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol Min Typ Max Unit 0.65*VDD5 - - V P Input High Voltage V T Input High Voltage VIH - - VDD5 + 0.3 V P Input Low Voltage V - - 0.35*VDD5 V T Input Low Voltage VIL VSS5 - 0.3 - - V - 250 - mV –1 - 1 µA VDD5 – 0.8 - - V IH IL V 3 C Input Hysteresis 4 Input Leakage Current (pins in high impedance input P mode) V =V or VSS5 in DD5 5 Output High Voltage (pins in output mode) P Partial Drive IOH = –2mA Full Drive IOH = –10mA V 6 Output Low Voltage (pins in output mode) P Partial Drive IOL = +2mA Full Drive IOL = +10mA V OL - - 0.8 V 7 Internal Pull Up Device Current, P tested at V Max. IPUL - - -130 µA Internal Pull Up Device Current, C tested at V Min. IPUH -10 - - µA 9 Internal Pull Down Device Current, P tested at V Min. IH IPDH - - 130 µA 10 Internal Pull Down Device Current, C tested at V Max. IPDL 10 - - µA 11 D Input Capacitance Cin - 6 - pF 12 Injection current1 T Single Pin limit Total Device Limit. Sum of all injected currents IICS IICP -2.5 -25 - 2.5 25 mA 13 P Port H, J, P Interrupt Input Pulse filtered2 tPIGN - - 3 µs 14 P Port H, J, P Interrupt Input Pulse passed(2) tPVAL 10 - - µs IL 8 IH IL HYS Iin OH NOTES: 1. Refer to Section A.1.4 Current Injection, for more details 2. Parameter only applies in STOP or Pseudo STOP mode. A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. MC9S12DP512 Device Guide V01.25 A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Run supply currents Single Chip, Internal regulator enabled IDD5 1 P 2 P P All modules enabled, PLL on only RTI enabled (1) C P C C P C P C P Pseudo Stop Current (RTI and COP disabled) 1, 2 -40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C C C C C C C C Pseudo Stop Current (RTI and COP enabled) (1), (2) -40°C 27°C 70°C 85°C 105°C 125°C 140°C Min Typ - - - - Max 65 Unit mA Wait Supply current 3 4 IDDW IDDPS IDDPS - - 370 400 450 550 600 650 800 850 1200 570 600 650 750 850 1200 1500 40 5 mA 500 1600 µA 2100 5000 - µA Stop Current (2) 5 C P C C P C P C P -40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C IDDS - 12 25 100 130 160 200 350 400 600 100 1200 µA 1700 5000 93 MC9S12DP512 Device Guide V01.25 NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed MC9S12DP512 Device Guide V01.25 A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-8 ATD Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 - VDDA/2 VDDA V V Reference Potential 1 D Low High 2 C Differential Reference Voltage1 VRH-VRL 4.50 5.00 5.25 V 3 D ATD Clock Frequency fATDCLK 0.5 - 2.0 MHz 4 D NCONV10 TCONV10 14 7 - 28 14 Cycles µs 5 D NCONV8 TCONV8 12 6 - 26 13 Cycles µs 6 D Recovery Time (VDDA=5.0 Volts) tREC - - 20 µs 7 P Reference Supply current 2 ATD blocks on IREF - - 0.750 mA 8 P Reference Supply current 1 ATD block on IREF - - 0.375 mA ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK ATD 8-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.2.2 Factors influencing accuracy Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS 95 MC9S12DP512 Device Guide V01.25 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN). A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-9 ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit RS - - 1 KΩ CINN CINS - - 10 22 pF 1 C Max input Source Resistance 2 Total Input Capacitance T Non Sampling Sampling 3 C Disruptive Analog Input Current INA -2.5 - 2.5 mA 4 C Coupling Ratio positive current injection Kp - - 10-4 A/A 5 C Coupling Ratio negative current injection Kn - - 10-2 A/A MC9S12DP512 Device Guide V01.25 A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10-Bit Resolution LSB - 5 - mV 2 P 10-Bit Differential Nonlinearity DNL –1 - 1 Counts 3 P 10-Bit Integral Nonlinearity INL –2.5 ±1.5 2.5 Counts 4 P 10-Bit Absolute Error1 AE -3 ±2.0 3 Counts 5 P 8-Bit Resolution LSB - 20 - mV 6 P 8-Bit Differential Nonlinearity DNL –0.5 - 0.5 Counts 7 P 8-Bit Integral Nonlinearity INL –1.0 ±0.5 1.0 Counts 8 P 8-Bit Absolute Error(1) AE -1.5 ±1.0 1.5 Counts NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter. For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. Vi – Vi – 1 DNL ( i ) = ------------------------ – 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ i=1 Vn – V0 DNL ( i ) = -------------------- – n 1LSB 97 MC9S12DP512 Device Guide V01.25 DNL 10-Bit Absolute Error Boundary LSB Vi-1 Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $FF $3FB $3FA $3F9 $3F8 $FE $3F7 $3F6 $3F4 8-Bit Resolution 10-Bit Resolution $3F5 $FD $3F3 9 Ideal Transfer Curve 8 2 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-1 ATD Accuracy Definitions NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10. MC9S12DP512 Device Guide V01.25 A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz. A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula. 1 1 t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP f bus A.3.1.2 Row Programming This applies only to the Flash where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: 1 1 t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f NVMOP f bus The time to program a whole row is: t brpgm = t swpgm + 63 ⋅ t bwpgm Row programming is more than 2 times faster than single word programming. A.3.1.3 Sector Erase Erasing a 1024 byte Flash sector or a 4 byte EEPROM sector takes: 1 t era ≈ 4000 ⋅ --------------------f NVMOP 99 MC9S12DP512 Device Guide V01.25 The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: 1 t mass ≈ 20000 ⋅ --------------------f NVMOP The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ≈ location ⋅ t cyc + 10 ⋅ t cyc Table A-11 NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D External Oscillator Clock fNVMOSC 0.5 - 50 1 MHz 2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 - - MHz 3 D Operating Frequency fNVMOP 150 - 200 kHz 4 P Single Word Programming Time tswpgm 46 2 - 74.5 3 µs 5 D Flash Row Programming consecutive word 4 tbwpgm 20.4 (2) - 31 (3) µs 6 D Flash Row Programming Time for 64 Words (4) tbrpgm 1331.2 (2) - 2027.5 (3) µs 7 P Sector Erase Time tera 20 5 - 26.7 (3) ms 8 P Mass Erase Time tmass 100 (5) - 133 (3) ms 9 D Blank Check Time Flash per block tcheck 11 6 - 65546 7 tcyc 10 D Blank Check Time EEPROM per block tcheck 11 (6) - 2058 (7) tcyc NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1 Single Word Programming- Section A.3.1.4 Mass Erasefor guidance. 4. Row Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block MC9S12DP512 Device Guide V01.25 A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table A-12 NVM Reliability Characteristics1 Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max 15 1002 — Unit Flash Reliability Characteristics Data retention after 10,000 program/erase cycles at an average junction temperature of TJavg ≤ 85°C 1 C 2 Data retention with