MC9S12DT128CPVE

MC9S12DT128 Device User Guide Covers MC9S12DT128E, MC9S12DG128E, MC9S12DJ128E, MC9S12DG128, MC9S12DJ128, MC9S12DB128, MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG, SC101161DJ, SC102202, SC102203, SC102204, SC102205 HCS12 Microcontrollers 9S12DT128DGV2/D V02.17 03 Jun 2010 freescale.com Device User Guide — 9S12DT128DGV2/D V02.17 Revision History Version Revision Effective Number Date Date Author Description of Changes V01.00 18 Jun 2001 18 June 2001 Initial version (parent doc v2.03 dug for dp256). V01.01 23 July 2001 23 July 2001 Updated version after review V01.02 23 Sep 2001 23 Sep 2001 Changed Partname, added pierce mode, updated electrical characteristics some minor corrections V01.03 12 Oct 2001 12 Oct 2001 Replaced Star12 by HCS12 V01.04 27 Feb 2002 27 Feb 2002 Updated electrical spec after MC-Qualification (IOL/IOH), Data for Pierce, NVM reliability New document numbering. Corrected Typos V01.05 4 Mar 2002 4 Mar 2002 Increased VDD to 2.35V, removed min. oscillator startup Removed Document order number except from Cover Sheet 22 July 2002 Added: Pull-up columns to signal table, example for PLL Filter calculation, Thermal values for junction to board and package, BGND pin pull-up Part Order Information Global Register Table Chip Configuration Summary Modified: Reduced Wait and Run IDD values Mode of Operation chapter changed leakage current for ADC inputs down to +-1uA Corrected: Interrupt vector table enable register inconsistencies PCB layout for 80QFP VREGEN position V01.06 8 July 2002 V02.00 11 Jan 2002 11 Jan 2002 NEW MASKSET Changed part number from DTB128 to DT128 Functional Changes: ROMCTL changes in Emulation Mode 80 Pin Byteflight package Option available Flash with 2 Bit Backdoor Key Enable Additional CAN0 routing to PJ7,6 Improved BDM with sync and acknowledge capabilities New Part ID number Improvements: Significantly improved NVM reliability data Corrections: Interrupt vector Table V02.01 01 Feb 2002 01 Feb 2002 Updated Block User Guide versions in preface Updated Appendix A Electrical Characteristics 2 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Version Revision Effective Number Date Date V02.02 V02.03 08 Mar 2002 14 Mar 2002 Author Description of Changes 08 Mar 2002 Changed XCLKS to PE7 in Table 2-2 Updated device part numbers in Figure 2-1 Updated BDM clock in Figure 3-1 Removed SIM description in overview & nUPOSC spec in Table A-15 Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH (Table A-6), CINS (Table A-9), CIN (Table A-6 & A-15), Updated interrupt pulse timing variables in Table A-6 Updated device part numbers in Figure 2-1 Added document numbers on cover page and Table 0-2 14 Mar 2002 Cleaned up Fig. 1-1, 2-1 Updated Section 1.5 descriptions Corrected PE assignment in Table 2-2, Fig. 2-5,6,7. Corrected NVM sizes in Sections 16, 17 Added IREF spec for 1ATD in Table A-8 Added Blank Check in A.3.1.5 and Table A-11 Updated CRG spec in Table A-15 V02.04 16 Aug 2002 16 Aug 2002 Added: Pull-up columns to signal table, Example for PLL Filter calculation, Thermal values for junction to board and package, BGND pin pull-up Part Order Information Global Register Table Chip Configuration Summary Device specific info on CRG Modified: Reduced Wait and Run IDD values Mode of Operation chapter Changed leakage current for ADC inputs down to +-1uA Minor modification of PLL frequency/ voltage gain values Corrected: Pin names/functions on 80 pin packages Interrupt vector table enable register inconsistencies PCB layout for 80QFP VREGEN position V02.05 12 Sep 2002 12 Sep 2002 Corrected: Register address mismatches in 1.5.1 06 Nov 2002 Removed document order no. from Revision History pages Renamed "Preface" section to "Derivative Differences and Document references". Added details for derivatives missing CAN0/1/4, BDLC, IIC and/or Byteflight Added 2L40K mask set in section 1.6 Added OSC User Guide in Preface, “Document References” Added oscillator clock connection to BDM in S12_CORE in fig 3-1 Corrected several register and bit names in “Local Enable” column of Table 5.1 Interrupt Vector Locations Section HCS12 Core Block Description: mentioned alternate clock of BDM to be equivalent to oscillator clock Added new section: “Oscillator (OSC) Block Description” Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz V02.06 06 Nov 2002 Freescale Semiconductor 3 Device User Guide — 9S12DT128DGV2/D V02.17 Version Revision Effective Number Date Date Author Description of Changes V02.07 29 Jan 2003 29 Jan 2003 Added 3L40K mask set in section 1.6 Corrected register entries in section 1.5.1 “Detailed Memory Map” Updated description for ROMCTL in section 2.3.31 Updated section 4.3.3 “Unsecuring the Microcontroller” Corrected and updated device-specific information for OSC (section 8.1) & Byteflight (section 15.1) Updated footnote in Table A-4 “Operating Conditions” Changed reference of VDDM to VDDR in section A.1.8 Removed footnote on input leakage current in Table A-6 “5V I/O Characteristics” V02.08 26 Feb 2003 26 Feb 2003 Added part numbers MC9S12DT128E, MC9S12DG128E, and MC9S12DJ128E in “Preface” and related part number references Removed mask sets 0L40K and 2L40K from Table 1-3 15 Oct 2003 Replaced references to HCS12 Core Guide by the individual HCS12 Block guides in Table 0-2, section 1.5.1, and section 6; updated Fig.3-1 “Clock Connections” to show the individual HCS12 blocks Corrected PIM module name and document order number in Table 0-2 “Document References” Corrected ECT pulse accumulators description in section 1.2 “Features” Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in Table 2.1 “Signal Properties” Mentioned “S12LRAE” bootloader in Flash section 17 Corrected footnote on clamp of TEST pin under Table A-1 “Absolute Maximum Ratings” Corrected minimum bus frequency to 0.25MHz in Table A-4 “Operating Conditions” Replaced “burst programming” by “row programming” in A.3 “NVM, Flash and EEPROM” Corrected blank check time for EEPROM in Table A-11 “NVM Timing Characteristics” Corrected operating frequency in Table A-18 “SPI Master/Slave Mode Timing Characteristics 6 Feb 2004 Added A128 information in “Derivative Differences”, 2.1 “Device Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4 Added lead-free package option (PVE) in Table 0-2 “Derivative Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber Example” Added an “AEC qualified” row in the “Derivative Differences” tables 0-1 & 0-2. 3 May 2004 Added part numbers SC515846, SC515847, SC515848, and SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2, and section 23. Corrected and added maskset 4L40K in tables 0-1 & 0-2 and section 1.6. Corrected BDLC module availability in DB128 80QFP part in “Derivative Differences” table 0-2. V02.09 V02.10 V02.11 4 15 Oct 2003 6 Feb 2004 3 May 2004 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Version Revision Effective Number Date Date Author Description of Changes V02.12 06 Dec 2004 06 Dec 2004 Added maskset 0L94R Added items VIH,EXTAL, VIL,EXTAL, & VHYS,EXTAL in table A-15 “Oscillator characteristics” Removed item “Oscillator” from table A-4 “Operating Conditions” as it is already covered in table “Oscillator Characteristics” V02.13 04 Mar 2005 04 Mar 2005 Amended feature list of A128 in Table 0-1 “Derivative Differences” V02.14 28 Apr 2005 28 Apr 2005 Updated cover page Added part numbers SC101161DT, SC101161DG, SC101161DJ, SC102202, SC102203, SC102204, & SC102205 Added masksets 5L40K &1L59W Changed TJavg to 85°C in table A-12 “NVM Reliability” & added footnote concerning data retention V02.15 05 Oct 2005 05 Oct 2005 Updated “NVM Reliability” table A-12 format with added data. Added figure A-2 “Typical Endurance vs Temperature” V02.16 12 Apr 2008 12 Apr 2008 Added maskset 2L94R V02.17 3 Jun 2010 3 Jun 2010 Added maskset 1L59W for MC9S12A128 Freescale Semiconductor 5 Device User Guide — 9S12DT128DGV2/D V02.17 6 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Table of Contents Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Section 2 Signal Description 2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.3 TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 64 2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . 65 2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 65 2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 65 2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.18 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Freescale Semiconductor 7 Device User Guide — 9S12DT128DGV2/D V02.17 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56 8 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . 68 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . 69 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 69 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . 69 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . 69 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . 69 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . 70 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . 70 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . 70 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 71 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 71 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 71 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . 73 2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins . . . . . . . . . . . . 73 2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 74 2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.7 VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . 74 Section 3 System Clock Description 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Section 4 Modes of Operation 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Section 5 Resets and Interrupts 5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Section 6 HCS12 Core Block Description 6.1 CPU Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Freescale Semiconductor 9 Device User Guide — 9S12DT128DGV2/D V02.17 6.1.1 6.2 6.2.1 6.3 6.3.1 6.4 6.5 6.5.1 6.6 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . 85 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 85 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 86 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Section 7 Clock and Reset Generator (CRG) Block Description 7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Section 8 Oscillator (OSC) Block Description 8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Section 9 Enhanced Capture Timer (ECT) Block Description Section 10 Analog to Digital Converter (ATD) Block Description Section 11 Inter-IC Bus (IIC) Block Description Section 12 Serial Communications Interface (SCI) Block Description Section 13 Serial Peripheral Interface (SPI) Block Description Section 14 J1850 (BDLC) Block Description Section 15 Byteflight (BF) Block Description 15.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Section 16 Pulse Width Modulator (PWM) Block Description Section 17 Flash EEPROM 128K Block Description Section 18 EEPROM 2K Block Description Section 19 RAM Block Description 10 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Section 20 MSCAN Block Description Section 21 Port Integration Module (PIM) Block Description Section 22 Voltage Regulator (VREG) Block Description Section 23 Printed Circuit Board Layout Proposal Appendix A Electrical Characteristics A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 101 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Freescale Semiconductor 11 Device User Guide — 9S12DT128DGV2/D V02.17 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 A.8.1 General Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Appendix B Package Information B.1 B.2 B.3 12 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 List of Figures Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 1-1 MC9S12DT128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 1-2 MC9S12DT128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128E, MC9S12DT128, MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12DB128 MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG, SC101161DJ, SC102202, SC102203, SC102204, and SC102205 . . . . . . . . . . . . . . . . . . 58 Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Bondout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 2-3 Pin Assignments in 80 QFP for MC9S12DB128, SC515846, and SC102202 Bondout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . 91 Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . 92 Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . 93 Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Pierce Oscillator . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and SC102202) Pierce Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure A-2 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure A-4 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure A-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure A-6 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure A-7 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure A-8 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure A-9 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Freescale Semiconductor 13 Device User Guide — 9S12DT128DGV2/D V02.17 Figure A-10 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . 138 14 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 List of Tables Table 0-1 Derivative Differences1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 0-2 Derivative Differences for MC9S12DB1281. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 0-3 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 $0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................... 32 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ................................. 32 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) .............................................................. 33 $0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) .................................. 33 $0018 - $0019Reserved ..................................................................................................... 33 $001A - $001B Device ID Register ((Table 1-3)) ............................................................... 33 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, (Table 1-4)) ............ 33 $001E - $001EMEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) .................. 33 $001F - $001FINT map 2 of 2 (HCS12 Interrupt) ............................................................... 34 $0020 - $0027 Reserved .................................................................................................... 34 $0028 - $002F BKP (HCS12 Breakpoint) ........................................................................... 34 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ................................. 34 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) .................. 34 $0034 - $003F CRG (Clock and Reset Generator) ............................................................ 35 $0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) ................................... 35 $0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 38 $00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) ........................................ 39 $00C8 - $00CF SCI0 (Asynchronous Serial Interface) ...................................................... 41 $00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ....................................................... 41 $00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................. 42 $00E0 - $00E7 IIC (Inter IC Bus) ....................................................................................... 42 $00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ......................................... 43 $00F0 - $00F7 SPI1 (Serial Peripheral Interface) .............................................................. 43 $00F8 - $00FF Reserved ................................................................................................... 43 $0100 - $010F Flash Control Register (fts128k2) .............................................................. 44 $0110 - $011B EEPROM Control Register (eets2k) .......................................................... 44 $011C - $011F Reserved for RAM Control Register .......................................................... 45 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 45 $0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ................................................ 46 Freescale Semiconductor 15 Device User Guide — 9S12DT128DGV2/D V02.17 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 47 $0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ................................................ 48 $01C0 - $01FF Reserved ................................................................................................... 49 $0200 - $023F Reserved .................................................................................................... 49 $0240 - $027F PIM (Port Integration Module) .................................................................... 50 $0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ................................................ 52 $02C0 - $02FF Reserved ................................................................................................... 53 $0300 - $035F Byteflight .................................................................................................... 53 $0360 - $03FF Reserved ................................................................................................... 55 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 2-2 MC9S12DT128 Power and Ground Connection Summary . . . . . . . . . . . . . . . 72 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 23-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . 117 Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Freescale Semiconductor 17 Device User Guide — 9S12DT128DGV2/D V02.17 18 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Derivative Differences and Document References Derivative Differences (Table 0-1) and (Table 0-2) show the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Table 0-1 Derivative Differences1 Modules # of CANs CAN4 CAN1 CAN0 J1850/BDLC IIC Byteflight MC9S12DT128E3 MC9S12DG128E3 MC9S12DT128 MC9S12DG128 SC5158494 SC5158474 5 SC101161DT SC101161DG5 6 SC102205 SC1022036 3 2 ✓ ✓ ✓ ✕ ✓ ✓ ✕ ✕ ✓ ✓ ✕ ✕ Package 112 LQFP Package Code PV MC9S12DJ128E3 MC9S12DJ128 SC5158484 SC101161DJ5 SC1022046 2 ✓ ✕ ✓ ✓ ✓ ✕ 0 ✕ ✕ ✕ ✕ ✓ ✕ 112 LQFP/80 QFP2 112 LQFP/80 QFP2 112 LQFP/80 QFP2 PV/FU PV/FU PV/FU 1L40K3, 3L40K, 0L94R, 4L40K4, Mask set 1L59W5, 5L40K6, 2L94R Temp Options M, V, C AEC qualified Yes 1L40K3, 3L40K, 0L94R, 4L40K4, 1L59W5, 5L40K6, 2L94R M, V, C Yes 1L40K3, 3L40K, 0L94R, 4L40K4, 1L59W5, 5L40K6, 2L94R M, V, C Yes An errata exists contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office Notes MC9S12A128 3L40K, 0L94R, 2L94R, 1L59W C No An errata exists contact Sales Office Table 0-2 Derivative Differences for MC9S12DB1281 # of CANs CAN4 CAN1 CAN0 J1850/BDLC IIC Byteflight MC9S12DB128 SC5158464 SC1022026 2 ✓ ✕ ✓ ✕ ✕ ✓ MC9S12DB128 SC5158464 SC1022026 0 ✕ ✕ ✕ ✕ ✕ ✓ Package 112 LQFP 80 QFP2 Modules Freescale Semiconductor 19 Device User Guide — 9S12DT128DGV2/D V02.17 Modules Package Code Mask set Temp Options AEC qualified Notes MC9S12DB128 SC5158464 SC1022026 PV/PVE 3L40K, 0L94R, 4L40K4, 5L40K6, 2L94R M, V, C/M, V Yes 3L40K, 0L94R, 4L40K4, 5L40K6, 2L94R M, V, C Yes An errata exists contact Sales Office An errata exists contact Sales Office MC9S12DB128 SC5158464 SC1022026 FU NOTE: 1. ✓: Available for this device, ✕: Not available for this device. 2. 80 Pin bond-out for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 is the same; MC9S12DB128, SC515846, and SC102202 have a different bond-out. 3. Part numbers MC9S12DT128E, MC9S12DG128E, and MC9S12DJ128E are associated with the mask set 1L40K. 4. Part numbers SC515846, SC515847, SC515848, and SC515849 are associated with the mask set 4L40K. 5. Part numbers SC101161DT, SC101161DG, SC101161DJ are associated with the mask set 1L59W. 6. Part numbers SC102202, SC102203, SC102204, and SC102205 are associated with the mask set 5L40K which is not for volume production. The following figure provides an ordering number example for the MC9S12D128 devices. MC9S12 DJ128 C FU Package Option Temperature Option Device Title Controller Family Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Package Options FU = 80QFP PV = 112LQFP PVE = lead-free 112LQFP Figure 0-1 Order Partnumber Example The following items should be considered when using a derivative. • 20 Registers – Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without CAN0 (see (Table 0-1) and (Table 0-2)). – Do not write or read CAN1 registers (after reset: address range $0180 - $01BF), if using a derivative without CAN1 (see (Table 0-1) and (Table 0-2)). – Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)). – Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a derivative without BDLC (see (Table 0-1) and (Table 0-2)). – Do not write or read IIC registers (after reset: address range $00E0 - $00E7), if using a derivative without IIC (see (Table 0-1) and (Table 0-2)). Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 – • • • Do not write or read Byteflight registers (after reset: address range $0300 - $035F), if using a derivative without Byteflight registers (see (Table 0-1) and (Table 0-2)). Interrupts – Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for unused interrupts, if using a derivative without CAN0 (see (Table 0-1) and (Table 0-2)). – Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for unused interrupts, if using a derivative without CAN1 (see (Table 0-1) and (Table 0-2)). – Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for unused interrupts, if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)). – Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused interrupts, if using a derivative without BDLC (see (Table 0-1) and (Table 0-2)). – Fill the IIC interrupt vector ($FFC0, $FFC1) according to your coding policies for unused interrupts, if using a derivative without IIC (see (Table 0-1) and (Table 0-2)). – Fill the four Byteflight interrupt vectors ($FFA0 - $FFA7) according to your coding policies for unused interrupts, if using a derivative without Byteflight (see (Table 0-1) and (Table 0-2)). Ports – The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5, PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0 (see (Table 0-1) and (Table 0-2)). – The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if using a derivative without CAN1 (see (Table 0-1) and (Table 0-2)). – The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7, PM6, PM5 and PM4, if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)). – The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a derivative without BDLC (see (Table 0-1) and (Table 0-2)). – The IIC pin functionality (SCL, SCA) is not available on port PJ7 and PJ6, if using a derivative without IIC (see (Table 0-1) and (Table 0-2)). – The Byteflight pin functionality (BF_PSLM, BF_PERR, BF_PROK, BF_PSYN, TX_BF, RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative without Byteflight (see (Table 0-1) and (Table 0-2)). – Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DTB128 Block User Guide), if using a derivative without CAN0 (see (Table 0-1) and (Table 0-2)). – Do not write MODRR3 and MODRR2 Bit of Module Routing Register (PIM_9DTB128 Block User Guide), if using a derivative without CAN4 (see (Table 0-1) and (Table 0-2)). Pins not available in 80 pin QFP package for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 Freescale Semiconductor 21 Device User Guide — 9S12DT128DGV2/D V02.17 • 22 – Port H In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing a $FF to the pull enable register (PERH at Base+$0264). – Port J[1:0] Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at Base+$026C. – Port K Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at Base+$000C. Therefore care must be taken not to clear this bit. – Port M[7:6] PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. – Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input. – Port S[7:4] PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. – PAD[15:8] (ATD1 channels) Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1 registers! Pins not available in 80 pin QFP package for MC9S12DB128, SC515846, and SC102202 – Port H In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing a $FF to the pull enable register (PERH at Base+$0264). – Port J[7:6, 1:0] Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must be taken not to disable the pull enables on PJ[7:6, 1:0] by clearing the bits PERJ7, PERJ6, PERJ1 and PERJ0 at Base+$026C. – Port K Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at Base+$000C. Therefore care must be taken not to clear this bit. – Port M[1:0] PM1:0 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. – Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 – Port S[3:2] PS3:2 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. – PAD[15:8] (ATD1 channels) Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1 registers! Document References The Device User Guide provides information about the MC9S12DT128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes all the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-3 for names and versions of the referenced documents throughout the Device User Guide. Table 0-3 Document References User Guide Version Document Order Number HCS12 CPU Reference Manual V02 S12CPUV2/D HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D HCS12 Background Debug Module (BDM) Block Guide V04 S12BDMV4/D HCS12 Breakpoint (BKP) Block Guide V01 S12BKPV1/D Clock and Reset Generator (CRG) Block User Guide V04 S12CRGV4/D Oscillator (OSC) Block User Guide V02 S12OSCV2/D Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide V01 S12ECT16B8CV1/D Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide V02 S12ATD10B8CV2/D Inter IC Bus (IIC) Block User Guide V02 S12IICV2/D Asynchronous Serial Interface (SCI) Block User Guide V02 S12SCIV2/D Serial Peripheral Interface (SPI) Block User Guide V02 S12SPIV2/D Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide V01 S12PWM8B8CV1/D 128K Byte Flash (FTS128K) Block User Guide V02 S12FTS128KV2/D 2K Byte EEPROM (EETS2K) Block User Guide V01 S12EETS2KV1/D Byte Level Data Link Controller -J1850 (BDLC) Block User Guide V01 S12BDLCV1/D Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2/D Voltage Regulator (VREG) Block User Guide V01 S12VREGV1/D Port Integration Module (PIM_9DTB128) Block User Guide V02 S12DTB128PIMV2/D Byteflight (BF) Block User Guide V01 S12BFV1/D Freescale Semiconductor 23 Device User Guide — 9S12DT128DGV2/D V02.17 24 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Section 1 Introduction 1.1 Overview The MC9S12DT128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules (MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. 1.2 Features • HCS12 Core – 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. 20-bit ALU iv. Instruction queue v. Enhanced indexed addressing • • – MEBI (Multiplexed External Bus Interface) – MMC (Module Mapping Control) – INT (Interrupt control) – BKP (Breakpoints) – BDM (Background Debug Module) CRG (Clock and Reset Generator) – Choice of low current Colpitts oscillator or standard Pierce Oscillator – PLL – COP watchdog – real time interrupt – clock monitor 8-bit and 4-bit ports with interrupt functionality Freescale Semiconductor 25 Device User Guide — 9S12DT128DGV2/D V02.17 • • • • • • • 26 – Digital filtering – Programmable rising or falling edge trigger Memory – 128K Flash EEPROM – 2K byte EEPROM – 8K byte RAM Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability Three 1M bit per second, CAN 2.0 A, B software compatible modules – Five receive and three transmit buffers – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit – Four separate interrupt channels for Rx, Tx, error and wake-up – Low-pass filter wake-up function – Loop-back for self test operation Enhanced Capture Timer – 16-bit main counter with 7-bit prescaler – 8 programmable input capture or output compare channels – Four 8-bit or two 16-bit pulse accumulators 8 PWM channels – Programmable period and duty cycle – 8-bit 8-channel or 16-bit 4-channel – Separate control for each pulse width and duty cycle – Center-aligned or left-aligned outputs – Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input – Usable as interrupt inputs Serial interfaces – Two asynchronous Serial Communications Interfaces (SCI) – Two Synchronous Serial Peripheral Interface (SPI) – Byteflight Byte Data Link Controller (BDLC) Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 • SAE J1850 Class B Data Communications Network Interface – • • Compatible and ISO Compatible for Low-Speed (= 100nF C5 VDDPLL filter cap ceramic X7R 100nF C6 VDDX filter cap X7R/tantalum >= 100nF C7 OSC load cap C8 OSC load cap C9 / CS PLL loop filter cap C10 / CP PLL loop filter cap C11 / CDC DC cutoff cap Colpitts mode only, if recommended by quartz manufacturer R1 / R PLL loop filter res See PLL Specification chapter See PLL specification chapter R2 / RB Pierce mode only R3 / RS Q1 Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 – C6). • Central point of the ground star should be the VSSR pin. • Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. • VSSPLL must be directly connected to VSSR. • Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. • Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. • Central power input should be fed in at the VDDA/VSSA pins. Freescale Semiconductor 89 Device User Guide — 9S12DT128DGV2/D V02.17 Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR C4 C7 90 C8 C10 C9 R1 C11 C5 VDDR Q1 VSSPLL VDDPLL Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Colpitts Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 VDD2 VSSR C4 C5 VDDR C7 C8 C11 Q1 C10 C9 R1 Freescale Semiconductor VSSPLL VDDPLL 91 Device User Guide — 9S12DT128DGV2/D V02.17 Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR VSSPLL C4 R3 C5 VDDR R2 Q1 C7 C8 C10 C9 VDDPLL R1 92 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204) Pierce Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 VDD2 VSSPLL VSSR C4 R3 C5 VDDR R2 Q1 C7 Freescale Semiconductor C8 C10 C9 R1 VSSPLL VDDPLL 93 Device User Guide — 9S12DT128DGV2/D V02.17 Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and SC102202) Pierce Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 VDD2 VSSPLL VSSR C4 R3 C5 VDDR R2 Q1 C7 94 C8 C10 C9 R1 VSSPLL VDDPLL Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Appendix A Electrical Characteristics A.1 General This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. A.1.2 Power Supply The MC9S12DT128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. Freescale Semiconductor 97 Device User Guide — 9S12DT128DGV2/D V02.17 NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. A.1.3 Pins There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This class is made up by the two VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator. A.1.4 Current Injection Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. 98 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit 1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.0 V 2 Digital Logic Supply Voltage 2 VDD -0.3 3.0 V 3 PLL Supply Voltage (2) VDDPLL -0.3 3.0 V 4 Voltage difference VDDX to VDDR and VDDA ∆VDDX -0.3 0.3 V 5 Voltage difference VSSX to VSSR and VSSA ∆VSSX -0.3 0.3 V 6 Digital I/O Input Voltage VIN -0.3 6.0 V 7 Analog Reference VRH, VRL -0.3 6.0 V 8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V 9 TEST input VTEST -0.3 10.0 V 10 Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 ID -25 +25 mA 11 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 I DL -25 +25 mA 12 Instantaneous Maximum Current Single pin limit for TEST 5 IDT -0.25 0 mA 13 Storage Temperature Range T – 65 155 °C stg NOTES: 1. Beyond absolute maximum ratings device might be damaged. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. Freescale Semiconductor 99 Device User Guide — 9S12DT128DGV2/D V02.17 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions Model Human Body Machine Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative – – 3 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin positive negative – – 3 3 Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V Latch-up Table A-3 ESD and Latch-Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model (HBM) VHBM 2000 – V 2 C Machine Model (MM) VMM 200 – V 3 C Charge Device Model (CDM) VCDM 500 – V 4 Latch-up Current at 125°C C positive negative ILAT +100 –100 – mA 5 Latch-up Current at 27°C C positive negative ILAT +200 –200 – mA A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: 100 Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions Rating Symbol Min Typ Max Unit I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.25 V Digital Logic Supply Voltage 1 VDD 2.35 2.5 2.75 V PLL Supply Voltage 1 VDDPLL 2.25 2.5 2.75 V Voltage Difference VDDX to VDDR and VDDA ∆VDDX -0.1 0 0.1 V Voltage Difference VSSX to VSSR and VSSA ∆VSSX -0.1 0 0.1 V fbus 0.252 - 25 MHz Operating Junction Temperature Range T J -40 - 100 °C Operating Ambient Temperature Range 3 T A -40 27 85 °C Operating Junction Temperature Range TJ -40 - 120 °C Operating Ambient Temperature Range 3 TA -40 27 105 °C Operating Junction Temperature Range TJ -40 - 140 °C Operating Ambient Temperature Range 3 TA -40 27 125 °C Bus Frequency MC9S12DT128C MC9S12DT128V MC9S12DT128M NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The given operating range applies when this regulator is disabled and the device is powered from an external source. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. 3. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ. A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D • Θ JA ) T J = Junction Temperature, [°C ] T A = Ambient Temperature, [°C ] Freescale Semiconductor 101 Device User Guide — 9S12DT128DGV2/D V02.17 P D = Total Chip Power Dissipation, [W] Θ JA = Package Thermal Resistance, [°C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA 2 P IO = R DSON ⋅ I IO i i ∑ Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ------------ ;for outputs driven low I OL respectively V DD5 – V OH R DSON = ------------------------------------ ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA IDDR is the current shown in (Table A-7) and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. P IO = ∑ RDSON ⋅ IIOi 2 i Which is the sum of all output currents on I/O ports associated with VDDX and VDDR. 102 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 Table A-5 Thermal Package Characteristics1 Num C Rating Symbol Min Typ Max Unit 1 T Thermal Resistance LQFP112, single sided PCB2 θJA – – 54 o 2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 θJA – – 41 oC/W 3 T Junction to Board LQFP112 θJB – – 31 o C/W 4 T Junction to Case LQFP112 θJC – – 11 o C/W 5 T Junction to Package Top LQFP112 ΨJT – – 2 o C/W 6 T Thermal Resistance QFP 80, single sided PCB θJA – – 51 o C/W 7 T θJA – – 41 oC/W 8 T Junction to Board QFP80 θJB – – 27 oC/W 9 T Junction to Case QFP80 θJC – – 14 oC/W 10 T Junction to Package Top QFP80 ΨJT – – 3 oC/W Thermal Resistance QFP 80, double sided PCB with 2 internal planes C/W NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-3 3. PC Board according to EIA/JEDEC Standard 51-7 A.1.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Freescale Semiconductor 103 Device User Guide — 9S12DT128DGV2/D V02.17 Table A-6 5V I/O Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C 1 2 Rating Symbol Min Typ Max IH 0.65*VDD5 – IH – – VDD5 + 0.3 Unit P Input High Voltage V T Input High Voltage V P Input Low Voltage V – – 0.35*VDD5 V T Input Low Voltage V VSS5 – 0.3 – – V IL IL V 3 C Input Hysteresis 4 Input Leakage Current (pins in high ohmic input P mode) V =V or VSS5 in DD5 5 Output High Voltage (pins in output mode) C Partial Drive IOH = –2.0mA P Full Drive IOH = –10.0mA V 6 Output Low Voltage (pins in output mode) C Partial Drive IOL = +2.0mA P Full Drive IOL = +10.0mA 7 V 250 HYS mV -1.0 – 1.0 µA VDD5 – 0.8 – – V V OL – – 0.8 V Internal Pull Up Device Current, P tested at V Max. IPUL – – –130 µA Internal Pull Up Device Current, C tested at V Min. IPUH –10 – – µA Internal Pull Down Device Current, P tested at V Min. IPDH – – 130 µA Internal Pull Down Device Current, C tested at V Max. IPDL 10 – – µA 11 D Input Capacitance Cin 6 – pF 12 Injection current1 T Single Pin limit Total Device Limit. Sum of all injected currents IICS IICP – 2.5 25 mA 13 P Port H, J, P Interrupt Input Pulse filtered 2 tPULSE 3 µs 14 P Port H, J, P Interrupt Input Pulse passed 2 tPULSE IL 8 IH 9 IH 10 IL Iin OH –2.5 –25 10 µs NOTES: 1. Refer to Section A.1.4 Current Injection, for more details 2. Parameter only applies in STOP or Pseudo STOP mode. A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. 104 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Run supply currents Single Chip, Internal regulator enabled IDD5 55 IDDW 30 5 1 P 2 P P All modules enabled, PLL on only RTI enabled (1) C P C C P C P C P Pseudo Stop Current (RTI and COP disabled) 1, 2 -40°C 27°C 70°C 85°C “C” Temp Option 100°C 105°C “V” Temp Option 120°C 125°C “M” Temp Option 140°C Min Typ Max Unit mA Wait Supply current 3 Pseudo Stop Current (RTI and COP enabled) 4 C C C C C C C IDDPS 370 400 450 550 600 650 800 850 1200 mA 500 1600 µA 2100 5000 (1), (2) -40°C 27°C 70°C 85°C 105°C 125°C 140°C IDDPS 570 600 650 750 850 1200 1500 µA Stop Current (2) 5 C P C C P C P C P Freescale Semiconductor -40°C 27°C 70°C 85°C “C” Temp Option 100°C 105°C “V” Temp Option 120°C 125°C “M” Temp Option 140°C IDDS 12 25 100 130 160 200 350 400 600 100 1200 µA 1700 5000 105 Device User Guide — 9S12DT128DGV2/D V02.17 NOTES: 1. PLL off, Oscillator in Colpitts Mode 2. At those low power dissipation levels TJ = TA can be assumed 106 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The (Table A-8) shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-8 ATD Operating Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Min VRL VRH VSSA VDDA/2 Typ Max Unit VDDA/2 VDDA V V 5.25 V Reference Potential 1 D Low High 2 C Differential Reference Voltage1 VRH-VRL 4.50 3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz 4 D 14 7 28 14 Cycles µs 5 D 12 6 26 13 Cycles µs 6 D Stop Recovery Time (VDDA=5.0 Volts) tSR 20 µs 7 P Reference Supply current (Both ATD modules on) IREF 0.75 mA 8 P Reference Supply current (Only one ATD module on) IREF 0.375 mA 5.00 ATD 10-Bit Conversion Period Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK NCONV8 TCONV8 NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.2.2 Factors influencing accuracy Three factors – source resistance, source capacitance and current injection – have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance: Due to the input pin leakage current as specified in (Table A-6) in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS Freescale Semiconductor 107 Device User Guide — 9S12DT128DGV2/D V02.17 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS– CINN). A.2.2.3 Current injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-9 ATD Electrical Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Min Typ Max Unit RS - - 1 KΩ 10 22 pF 2.5 mA 1 C Max input Source Resistance 2 Total Input Capacitance T Non Sampling Sampling 3 C Disruptive Analog Input Current INA 4 C Coupling Ratio positive current injection Kp 10-4 A/A 5 C Coupling Ratio negative current injection Kn 10-2 A/A 108 CINN CINS -2.5 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 A.2.3 ATD accuracy (Table A-10) specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in (Table A-4) unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num C Rating Symbol Min 1 P 10-Bit Resolution LSB 2 P 10-Bit Differential Nonlinearity DNL –1 3 P 10-Bit Integral Nonlinearity INL –2.5 4 P 10-Bit Absolute Error1 AE -3 5 P 8-Bit Resolution LSB 6 P 8-Bit Differential Nonlinearity DNL –0.5 7 P 8-Bit Integral Nonlinearity INL –1.0 8 P 8-Bit Absolute Error(1) AE -1.5 Typ Max 5 Unit mV 1 Counts ±1.5 2.5 Counts ±2.0 3 Counts 20 mV 0.5 Counts ±0.5 1.0 Counts ±1.0 1.5 Counts NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter. For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. Vi – Vi – 1 DNL ( i ) = ------------------------ – 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ i=1 Freescale Semiconductor Vn – V0 DNL ( i ) = -------------------- – n 1LSB 109 Device User Guide — 9S12DT128DGV2/D V02.17 DNL 10-Bit Absolute Error Boundary LSB Vi-1 Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $FF $3FB $3FA $3F9 $3F8 $FE $3F7 $3F6 $3F4 8-Bit Resolution 10-Bit Resolution $3F5 $FD $3F3 9 Ideal Transfer Curve 8 2 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-1 ATD Accuracy Definitions NOTE: 110 Figure A-1 shows only definitions, for specification values refer to Table A-10. Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in (Table A-11) are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz. A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula. 1 1 t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP f bus A.3.1.2 Row Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: 1 1 t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f NVMOP f bus The time to program a whole row is: t brpgm = t swpgm + 31 ⋅ t bwpgm Row programming is more than 2 times faster than single word programming. A.3.1.3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes: Freescale Semiconductor 111 Device User Guide — 9S12DT128DGV2/D V02.17 1 t era ≈ 4000 ⋅ --------------------f NVMOP The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: 1 t mass ≈ 20000 ⋅ --------------------f NVMOP The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ≈ location ⋅ t cyc + 10 ⋅ t cyc Table A-11 NVM Timing Characteristics Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Min Typ Max Unit 50 1 MHz 1 D External Oscillator Clock fNVMOSC 0.5 2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 3 D Operating Frequency fNVMOP 150 200 kHz 4 P Single Word Programming Time tswpgm 46 2 74.5 3 µs 5 D Flash Row Programming consecutive word 4 tbwpgm 20.4 (2) 31 (3) µs 6 D Flash Row Programming Time for 32 Words (4) tbrpgm 678.4 (2) 1035.5 (3) µs 7 P Sector Erase Time tera 20 5 26.7 (3) ms 8 P Mass Erase Time tmass 100 (5) 133 (3) ms 9 D Blank Check Time Flash per block tcheck 11 6 32778 7 tcyc 10 D Blank Check Time EEPROM per block tcheck 11 (6) 1034(7) tcyc MHz NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1 Single Word Programming- Section A.3.1.4 Mass Erasefor guidance. 4. Row Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block 112 Freescale Semiconductor Device User Guide — 9S12DT128DGV2/D V02.17 A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Freescale Semiconductor 113 Device User Guide — 9S12DT128DGV2/D V02.17 Table A-12 NVM Reliability Characteristics1 Conditions are shown in (Table A-4) unless otherwise noted Num C Rating Symbol Min Typ Max 15 1002 20 1002 10,000 — 10,000 100,0003 15 1002 20 1002 — 10,000 — — 100,000 300,0003 Unit Flash Reliability Characteristics Data retention after 10,000 program/erase cycles at an average junction temperature of TJavg ≤ 85°C 1 C 2 Data retention with