MC9S12H256 Device User Guide — V01.20
MC9S12H256
Device User Guide
V01.20
Covers also MC9S12H128
Original Release Date: 29 SEP 2000
Revised: 28 JUL 2008
Freescale Semiconductor Inc.
1
DOCUMENT NUMBER
9S12H256BDGV1/D
Revision History
Version Revision Effective
Number
Date
Date
Author
Description of Changes
V01.00
07 MAR
2001
03 APR
2001
Initial version.
V01.01
10 MAI
2001
10 MAY
2001
- Minor formal corrections
- Changed ATD coupling ratio to10-2
- Changed VDD5 to 4.5V
V01.02
14 MAY
2001
14 MAY
2001
- Removed 112-pin package references
- Changed ATD Electrical Characteristics separate coupling ratio for
positive and negative bulk current injection
V01.03
30 MAY
2001
30 MAY
2001
- Reinserted 112-pin package information.
V01.04
11 JUN
2001
11 JUN
2001
- Removed SRSv2 comment from preface
- Corrected RESET pin to active low in table 2-1
V01.05
18 JUN
2001
18 JUN
2001
- Adapted style and wording to 9DP256 device user guide
- Minor format and wording improvements
- Added SRAM data retention disclaimer
28 JUN
2001
- Changed Oscillator Characteristics tCQOUT max 2.5s and replaced
Clock Monitor Time-out by Clock Monitor Failure Assert Frequency
- Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz
- Changed IDDPS (RTI and COP disabled) to 400µA
- Corrected typo in Figure 2-1 pin 76: PK3 -> PK2
V01.06
28 JUN
2001
V01.07
12 JUL
2001
12 JUL
2001
- Added tEXTR and tEXTF to Oscillator Characteristics
- Added typ value for tUPOSC
- Corrected tEXTL and tEXTH values
- Updated thermal resistances as per Thermal Simulation Report,
July 10, 2001
V01.08
16 JUL
2001
16 JUL
2001
- updated EEPROM size
- added DC cutoff capacitor into layout proposals
V01.09
03 AUG
2001
03 AUG
2001
- minor updates
V01.10
29 AUG
2001
29 AUG
2001
- updated electrical spec
Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Freescale does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Freescale products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Freescale was negligent regarding the design or manufacture of the part.
2
MC9S12H256 Device User Guide — V01.20
Version Revision Effective
Number
Date
Date
Author
Description of Changes
V01.11
11 OCT
2001
11 OCT
2001
- Replaced references w.r.t. new family name HCS12.
- Corrected XCLKS reference in CRG electrical spec.
V01.12
07 NOV
2001
07 NOV
2001
- added ‘powered by’ column in pin list table
08 MAR
2002
- new document numbering
- removed document order number except from cover sheet
- updated min VDD, VDDPLL
- updated currents on VOH,VOL for standard pins
- updated CIN, IDDS, IREF, CINS, TEXTL, TEXTH
- included missing lcd electrical spec
- updated NVM spec
V01.13
08 MAR
2002
V01.14
16 DEC
2002
16 DEC
2002
- updated input leakage
- updated slew rate spec on PU,PV, PW
- updated supply currents
- included 1K78X
- added detailed register map
V01.15
31 MAR
2003
31 MAR
2003
- added K1 max value
- added chragepump current min/max values
V01.16
05 NOV
2003
05 NOV
2003
- corrected pinout problem in LQFP112 layout proposal
V01.17
04 AUG
2004
04 AUG
2004
- added MC9S12H128
V01.18
13 AUG
2004
13 AUG
2004
- added Internal Pull Resistor columns to signal properties table
V01.19
05 NOV
2004
05 NOV
2004
- changed SPI0 to SPI, ATD0 to ATD
V01.20
28 JUL
2008
28 JUL
2008
- changed PU,PV,PW rise/fall times in EPP package at cold.
3
MC9S12H256 Device User Guide — V01.20
4
MC9S12H256 Device User Guide — V01.20
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2
Signal Properties Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.3
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.1
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.2
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.3
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.4
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.5
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin. . . . . . . . . . . . . 60
2.3.6
PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.7
PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.8
PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . 60
2.3.9
PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 61
2.3.10
PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.11
PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.12
PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.13
PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.14
PE3 / FP21 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.15
PE2 / FP20 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.16
PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.17
PE0 / XIRQ — Port E Input Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.18
PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.19
PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.20
PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.21
PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . 62
2.3.22
PL[7:4] / FP[31:28] — Port L I/O Pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.23
PL[3:0] / FP[19:16] — Port L I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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MC9S12H256 Device User Guide — V01.20
2.3.24
PM5 / TXCAN1 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.25
PM4 / RXCAN1 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.26
PM3 / TXCAN0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.27
PM2 / RXCAN0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.28
PM1 / SCL — Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.29
PM0 / SDA — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.30
PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.31
PP[1:0] / PWM[1:0] — Port P I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.32
PS7 / SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.33
PS6 / SCK — Port S I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.34
PS5 / MOSI — Port S I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.35
PS4 / MISO — Port S I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.36
PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.37
PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.38
PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.39
PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.40
PT[7:4] / IOC[7:4] — Port T I/O Pins [7:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.41
PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.42
PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M — Port U I/O Pins [7:4] . . . . . . . . . . . . . . . . 65
2.3.43
PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M — Port U I/O Pins [3:0] . . . . . . . . . . . . . . . . 65
2.3.44
PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M — Port V I/O Pins [7:4] . . . . . . . . . . . . . . . . 65
2.3.45
PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0] . . . . . . . . . . . . . . . . 66
2.3.46
PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M — Port W I/O Pins [7:4] . . . . . . . . . . . . . . . 66
2.3.47
PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M — Port W I/O Pins [3:0] . . . . . . . . . . . . . . . 66
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.1
VDDR — External Power Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.2
VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins . . . . . . . . . . . . . . . 66
2.4.3
VDD1, VSS1, VSS2 — Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.4
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.5
VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . 67
2.4.6
VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 5 . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.7
VLCD — Power Supply Reference Pin for LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.8
VRH, VRL — ATD Reference Voltage Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4.9
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Section 3 System Clock Description
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MC9S12H256 Device User Guide — V01.20
3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Section 4 Modes of Operation
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Normal Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Test Operating Mode (Freescale Use Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Section 5 Resets and Interrupts
5.1
5.2
5.2.1
5.3
5.3.1
5.3.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Section 6 HCS12 Core Block Description
Section 7 Clock and Reset Generator (CRG) Block Description
7.1
7.1.1
Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
XCLKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Section 8 Timer (TIM) Block Description
Section 9 Analog to Digital Converter (ATD) Block Description
Section 10 Inter-IC Bus (IIC) Block Description
Section 11 Serial Communications Interface (SCI) Block Description
Section 12 Serial Peripheral Interface (SPI) Block Description
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MC9S12H256 Device User Guide — V01.20
Section 13 Pulse Width Modulator (PWM) Block Description
Section 14 Flash EEPROM 256K Block Description
Section 15 EEPROM 4K Block Description
Section 16 RAM Block Description
Section 17 Liquid Crystal Display Driver (LCD) Block Description
Section 18 MSCAN Block Description
Section 19 PWM Motor Control (MC) Block Description
Section 20 Port Integration Module (PIM) Block Description
Section 21 Voltage Regulator (VREG) Block Description
21.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.1.1
VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.1.2
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
21.2 Recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Appendix A Electrical Characteristics
A.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.1
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.2
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.3
Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
A.1.4
Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
A.1.5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.1.6
ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
A.1.7
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
A.1.8
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
A.1.9
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.2
ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.2.1
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.2.2
Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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MC9S12H256 Device User Guide — V01.20
A.2.3
A.3
A.3.1
A.3.2
A.4
A.4.1
A.4.2
A.4.3
A.5
A.6
A.6.1
A.6.2
A.7
A.8
A.8.1
ATD accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
NVM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LCD_32F4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
General Muxed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Appendix B Package Information
B.1
B.2
B.3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
112-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
144-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 2-1
Figure 2-2
Figure 3-1
Figure 21-1
Figure 21-2
Figure A-1
Figure A-2
Figure A-3
Figure A-4
Figure A-5
Figure A-6
Figure A-7
Figure A-8
Figure A-9
Figure B-1
Figure B-2
MC9S12H256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MC9S12H128 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MC9S12H256 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MC9S12H128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128 . . . . . . . . . . 56
Pin Assignments in 144-pin LQFP for MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . 57
Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LQFP112 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LQFP144 recommended PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SPI Slave Timing (CPHA =1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
General External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . . . . . . 126
144-pin LQFP mechanical dimensions (case no. 918-03) . . . . . . . . . . . . . . . . . . . . . 127
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Table 0-1
Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 1-1
Device Memory Map MC9S12H256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 1-2
Device Memory Map MC9S12H128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 1-3
Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 44
Table 1-4
Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . . . . . . . . 46
Table 1-5
Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 1-6
Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 2-1
Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 4-1
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 5-1
Reset and Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 21-1 Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table A-2 ESD and Latch-up Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table A-13 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table A-14 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-15 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table A-16 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table A-17 SPI Master Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table A-18 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LCD_32F4B Driver Electrical Characteristics 119
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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MC9S12H256 Device User Guide — V01.20
14
MC9S12H256 Device User Guide — V01.20
Preface
The Device User Guide provides information about the MC9S12H256 and MC9S12H128 device made up
of standard HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In an
effort to reduce redundancy all module specific information is located only in the respective Block User
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-1 Document References
User Guide
Version
Document Order Number
HCS12 V1.5 Core User Guide
1.2
HCS12COREUG
CRG Block User Guide
V02
S12CRGV2/D
TIM_16B8C Block User Guide
V01
S12TIM16B8CV1/D
ATD_10B16C Block User Guide
V02
S12ATD10B16CV2/D
IIC Block User Guide
V02
S12IICV2/D
SCI Block User Guide
V02
S12SCIV2/D
SPI Block User Guide
V02
S12SPIV2/D
PWM_8B6C Block User Guide
V01
S12PWM8B6CV1/D
FTS256K Block User Guide
V02
S12FTS256KV2/D
EETS4K Block User Guide
V02
S12EETS4KV2/D
LCD_32F4B Block User Guide
V01
S12LCD32F4BV1/D
MSCAN Block User Guide
V02
S12MSCANV2/D
MC_10B12C Block User Guide
V02
S12MC10B12CV2/D
PIM_9H256 Block User Guide
V01
S12PIMH256V1/D
VREG Block User Guide
V01
S12VREGV1/D
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MC9S12H256 Device User Guide — V01.20
16
MC9S12H256 Device User Guide — V01.20
Section 1 Introduction
1.1 Overview
The MC9S12H256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial
peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit
analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B
software compatible modules (MSCAN).
The MC9S12H128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 6K
bytes of RAM, 2K bytes of EEPROM, one asynchronous serial communications interface (SCI), a serial
peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 8-channel, 10-bit
analog-to-digital converter (ATD), a two-channel pulse width modulator (PWM), and two CAN 2.0 A, B
software compatible modules (MSCAN).
In addition, it features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width
modulator (MC) consisting of 24 high current outputs suited to drive up to 6 stepper motors. System
resource mapping, clock generation, interrupt control, and bus interfacing are managed by the HCS12
Core.
The MC9S12H256 has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports
available in each module, 12 general purpose I/O pins are available with interrupt and wake-up capability
from STOP or WAIT mode.
1.2 Features
•
HCS12 Core
–
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. 20-bit ALU
iv. Instruction queue
v. Enhanced indexed addressing
–
MEBI (Multiplexed External Bus Interface)
–
MMC (Module Mapping Control)
–
INT (Interrupt control)
–
BKP (Breakpoints)
17
MC9S12H256 Device User Guide — V01.20
–
BDM (Background Debug Mode)
•
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
•
8-bit and 4-bit ports with interrupt functionality
•
•
•
•
•
•
18
–
Digital filtering
–
Programmable rising or falling edge trigger
Memory
–
128K, 256K Flash EEPROM
–
2K, 4K byte EEPROM
–
6K, 12K byte RAM
Analog-to-Digital Converter
–
8, 16 channels, 10-bit resolution
–
External conversion trigger capability
Two 1M bit per second, CAN 2.0 A, B software compatible modules
–
Five receive and three transmit buffers
–
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
–
Four separate interrupt channels for Rx, Tx, error and wake-up
–
Low-pass filter wake-up function
–
Loop-back for self test operation
Timer
–
16-bit main counter with 7-bit prescaler
–
8 programmable input capture or output compare channels
–
Two 8-bit or one 16-bit pulse accumulators
2, 6 PWM channels
–
Programmable period and duty cycle
–
8-bit 2, 6-channel or 16-bit 1, 3-channel
–
Separate control for each pulse width and duty cycle
–
Center-aligned or left-aligned outputs
–
Programmable clock select logic with a wide range of frequencies
–
Fast emergency shutdown input
Serial interfaces
–
Two asynchronous Serial Communications Interfaces (SCI)
–
Synchronous Serial Peripheral Interface (SPI)
MC9S12H256 Device User Guide — V01.20
–
•
•
•
Inter-Integrated Circuit interface (IIC)
Liquid Crystal Display driver with variable input voltage
–
Configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output
–
5 modes of operation allow for different display sizes to meet application requirements
–
Unused frontplane and backplane pins can be used as general purpose I/O
16, 24 high current drivers suited for PWM motor control
–
Each PWM channel switchable between two drivers in an H-bridge configuration
–
Left, right and center aligned outputs
–
Support for sine and cosine drive
–
Dithering
–
Output slew rate control
144-Pin or 112-Pin LQFP package
–
I/O lines with 5V input and drive capability
–
5V A/D converter inputs
–
Operation at 32MHz equivalent to 16MHz Bus Speed
–
Development support
–
Single-wire background debug™ mode (BDM)
–
On-chip hardware breakpoints
1.3 Modes of Operation
User modes
•
•
Normal and Emulation Operating Modes
–
Normal Single-Chip Mode
–
Normal Expanded Wide Mode
–
Normal Expanded Narrow Mode
–
Emulation Expanded Wide Mode
–
Emulation Expanded Narrow Mode
Special Operating Modes
–
Special Single-Chip Mode with active Background Debug Mode
–
Special Test Mode (Freescale Use Only)
–
Special Peripheral Mode (Freescale Use Only)
Low power modes
19
MC9S12H256 Device User Guide — V01.20
•
Stop Mode
•
Pseudo Stop Mode
•
Wait Mode
1.4 Block Diagram
Figure 1-1 is a block diagram of the MC9S12H256 device.
20
MC9S12H256 Device User Guide — V01.20
4k Bytes EEPROM
12K Bytes RAM
Single-wire Background
Debug Module
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PLL
Clock and
Reset
Generation
Module
CPU12
Analog to
Digital
Converter
(ATD)
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PTE
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PW0
PW1
PW2
PW3
PW4
PW5
Pulse
Width
Modulator
(PWM)
PP0
PP1
PP2
PP3
PP4
PP5
SDA
SCL
CAN0
RXCAN0
TXCAN0
CAN1
RXCAN1
TXCAN1
PTS
IIC
PS4
PS5
PS6
PS7
PM0
PM1
PTM
SDI/MISO
SDO/MOSI
SCK
SS
DDRM
SPI
DDRS
PS2
PS3
PM2
PM3
PM4
PM5
VDDM1
MOTOR0 and MOTOR1 Supply
MOTOR0
VSSM1
PU0
PU1
PTU
M0C0M
M0C0P
M0C1M
M0C1P
M1C0M
M1C0P
M1C1M
M1C1P
PWM0
PWM3
PU2
PU3
PU4
PU5
PU6
PU7
VDDM2
MOTOR2 and MOTOR3 Supply
IOC0
IOC1
IOC2
IOC3
MOTOR2
PWM5
PWM6
MOTOR3
PWM7
MOTOR4 and MOTOR5 Supply
PWM8
Input Capture and
Output Compare
Timer
MOTOR4
PWM9
PWM10
MOTOR5
PWM11
Supply pins
Pin
Interrupt
Logic
VSSM2
PV0
PV1
A/D Converter 5V &
Voltage Regulator
Reference
M4C0M
M4C0P
M4C1M
M4C1P
M5C0M
M5C0P
M5C1M
M5C1P
PV2
PV3
PTV
ECS/ROMONE
M2C0M
M2C0P
M2C1M
M2C1P
M3C0M
M3C0P
M3C1M
M3C1P
PWM4
DDRV
FP23
KWJ0
KWJ1
KWJ2
KWJ3
RXD1
TXD1
PWM2
R/W
LSTRB/TAGLO
NOACC/XCLKS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
SCI1
MOTOR1
FP20
FP21
FP22
IOC4
IOC5
IOC6
IOC7
PS0
PS1
PWM1
FP16
FP17
FP18
FP19
FP28
FP29
FP30
FP31
FP24
FP25
FP26
FP27
RXD0
TXD0
DDRU
PPAGE
PTK
DDRK
PTB
DDRB
DDRA
PTA
PTL
DDRL
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
SCI0
PTW
NOTE: Not all
functionality shown
in this block
diagram is
available in all
packages!
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
DDRW
PK7
PTE
PE2
PE3
PE7
FP8
FP9
FP10
FP11
FP12
FP13
FP14
FP15
LCD
Driver
DDRE
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PTK
Multiplexed
Wide
Bus
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
DDRK
Multiplexed
Narrow
Bus
PTT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
DDRT
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
PTH
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PIX0
PIX1
PIX2
PIX3
DDRH
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PTJ
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
BP0
BP1
BP2
BP3
DDRJ
PK0
PK1
PK2
PK3
Integration
Module
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
VLCD
VLCD
XADDR14
XADDR15
XADDR16
XADDR17
XIRQ
IRQ
ECLK
MODA
MODB
Multiplexed Address/Data Bus
PE0
PE1
PE4
PE5
PE6
DDRE
TEST
VDDA
VSSA
VRH
VRL
PTAD
256k Bytes Flash EEPROM
VDDA
VSSA
VRH
VRL
PTP
Voltage Regulator
VDD1
VSS1,VSS2
DDRP
VDDR
PV4
PV5
PV6
PV7
VDDM3
VSSM3
PW0
PW1
PW2
PW3
PW4
PW5
PW6
PW7
Internal Logic 2.5V
I/O Driver 5V
VDD1
VDDX1,2
VSS1,2
VSSX1,2
PLL 2.5V
VDDA
VDDPLL
VSSA
VSSPLL
VREG Input 5V
VDDR
Figure 1-1 MC9S12H256 Block Diagram
21
MC9S12H256 Device User Guide — V01.20
Figure 1-2 is a block diagram of the MC9S12H128 device.
22
MC9S12H256 Device User Guide — V01.20
Voltage Regulator
VDD1
VSS1,VSS2
128k Bytes Flash EEPROM
2k Bytes EEPROM
6K Bytes RAM
Single-wire Background
Debug Module
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PLL
Clock and
Reset
Generation
Module
CPU12
Analog to
Digital
Converter
(ATD)
VDDA
VSSA
VRH
VRL
VDDA
VSSA
VRH
VRL
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
PAD00
PAD01
PAD02
PAD03
PAD04
PAD05
PAD06
PAD07
PTAD
VDDR
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PP0
PP1
PP2
PP3
PP4
PP5
PTP
PW0
PW1
PW2
PW3
PW4
PW5
Pulse
Width
Modulator
(PWM)
CAN0
RXCAN0
TXCAN0
CAN1
RXCAN1
TXCAN1
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
VDDM1
MOTOR0 and MOTOR1 Supply
M0C0M
M0C0P
M0C1M
M0C1P
M1C0M
M1C0P
M1C1M
M1C1P
PWM0
MOTOR0
PWM1
FP16
FP17
FP18
FP19
PTS
SDA
SCL
DDRS
IIC
PTM
SDI/MISO
SDO/MOSI
SCK
SS
DDRM
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
SPI
PS0
PS1
PWM2
MOTOR1
PWM3
VSSM1
PU0
PU1
PTU
FP8
FP9
FP10
FP11
FP12
FP13
FP14
FP15
LCD
Driver
PPAGE
PTK
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
RXD0
TXD0
SCI0
DDRU
PL0
PL1
PL2
PL3
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
Multiplexed Address/Data Bus
Multiplexed
Wide
Bus
DDRK
Multiplexed
Narrow
Bus
PTB
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
DDRB
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
PTA
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
PIX0
PIX1
PIX2
PIX3
DDRA
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PTL
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
BP0
BP1
BP2
BP3
DDRL
PK0
PK1
PK2
PK3
Integration
Module
VLCD
VLCD
XADDR14
XADDR15
XADDR16
XADDR17
XIRQ
IRQ
ECLK
MODA
MODB
DDRP
PTE
PE0
PE1
PE4
PE5
PE6
DDRE
TEST
PU2
PU3
PU4
PU5
PU6
PU7
VDDM2
PT4
PT5
PT6
PT7
FP24
FP25
FP26
FP27
IOC4
IOC5
IOC6
IOC7
IOC0
IOC1
IOC2
IOC3
PWM5
PWM6
MOTOR3
PWM7
MOTOR4 and MOTOR5 Supply
PWM8
Input Capture and
Output Compare
Timer
MOTOR4
PWM9
PWM10
MOTOR5
PWM11
Supply pins
A/D Converter 5V &
Voltage Regulator
Reference
M4C0M
M4C0P
M4C1M
M4C1P
M5C0M
M5C0P
M5C1M
M5C1P
PV2
PV3
PTV
ECS/ROMONE
MOTOR2
VSSM2
PV0
PV1
DDRV
PTE
DDRE
PTK
FP23
M2C0M
M2C0P
M2C1M
M2C1P
M3C0M
M3C0P
M3C1M
M3C1P
PWM4
PTW
PT0
PT1
PT2
PT3
R/W
LSTRB/TAGLO
NOACC/XCLKS
DDRW
NOTE: Not all
functionality shown
in this block
diagram is
available in all
packages!
PTT
PK7
FP20
FP21
FP22
DDRT
PE2
PE3
PE7
DDRK
MOTOR2 and MOTOR3 Supply
PV4
PV5
PV6
PV7
VDDM3
VSSM3
PW0
PW1
PW2
PW3
PW4
PW5
PW6
PW7
Internal Logic 2.5V
I/O Driver 5V
VDD1
VDDX1,2
VSS1,2
VSSX1,2
PLL 2.5V
VDDA
VDDPLL
VSSA
VSSPLL
VREG Input 5V
VDDR
Figure 1-2 MC9S12H128 Block Diagram
23
MC9S12H256 Device User Guide — V01.20
1.5 Device Memory Map
24
MC9S12H256 Device User Guide — V01.20
25
MC9S12H256 Device User Guide — V01.20
Table 1-1 and Figure 1-3 show the device memory map of the MC9S12H256.
Table 1-1 Device Memory Map MC9S12H256
Address
26
Module
$0000 – $0017
CORE (Ports A, B, E, Modes, Inits, Test)
Size
(Bytes)
24
$0018 – $0019
Reserved
2
$001A – $001B
Device ID register (PARTID)
2
$001C – $001F
CORE (MEMSIZ, IRQ, HPRIO)
4
$0020 – $0027
Reserved
8
$0028 – $002F
CORE (Background Debug Mode)
8
$0030 – $0033
CORE (PPAGE, Port K)
4
$0034 – $003F
Clock and Reset Generator (PLL, RTI, COP)
12
$0040 – $006F
Standard Timer Module 16-bit 8 channels (TIM)
48
$0070 – $007F
Reserved
16
$0080 – $00AF
Analog to Digital Converter 10-bit 16 channels (ATD)
48
$00B0 – $00BF
Reserved
16
$00C0 – $00C7
Inter Integrated Circuit (IIC)
8
$00C8 – $00CF
Serial Communications Interface 0 (SCI0)
8
$00D0 – $00D7
Serial Communications Interface 1 (SCI1)
8
$00D8 – $00DF
Serial Peripheral Interface (SPI)
$00E0 – $00FF
Pulse Width Modulator 8-bit 6 channels (PWM)
32
8
$0100 – $010F
Flash control registers
16
$0110 – $011B
EEPROM control registers
12
$011C – $011F
Reserved
$0120 – $0137
Liquid Crystal Display Driver 32x4 (LCD)
24
$0140 – $017F
Freescale Scalable Controller Area Network 0
(MSCAN0)
64
$0180 – $01BF
Freescale Scalable Controller Area Network 1
(MSCAN1)
64
$01C0 – $01FF
Motor Control Module (MC)
64
4
$0200 – $027F
Port Integration Module (PIM)
128
$0280 – $03FF
Reserved
384
$0000 – $0FFF
EEPROM array
$1000 – $3FFF
RAM array
12288
$4000 – $7FFF
Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
16384
$8000 – $BFFF
Flash EEPROM Page Window
16384
$C000 – $FFFF
Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 – $FFFF
16384
4096
MC9S12H256 Device User Guide — V01.20
$0000
$0400
$0800
$1000
$0000
1K Register Space
$03FF
Mappable to any 2K Boundary
$0000
4K Bytes EEPROM
initially overlapped by register space
$0FFF
Mappable to any 4K Boundary
$1000
12K Bytes RAM
Alignable to top ($1000 – $3FFF)
or bottom ($0000 – $2FFF)
$4000
$3FFF
Mappable to any 16K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED*
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
* Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode
Figure 1-3 MC9S12H256 Memory Map
Table 1-2 and Figure 1-4 show the device memory map of the MC9S12H128.
Table 1-2 Device Memory Map MC9S12H128
Address
Module
Size
(Bytes)
$0000 – $0017
CORE (Ports A, B, E, Modes, Inits, Test)
$0018 – $0019
Reserved
24
2
$001A – $001B
Device ID register (PARTID)
2
$001C – $001F
CORE (MEMSIZ, IRQ, HPRIO)
4
$0020 – $0027
Reserved
8
$0028 – $002F
CORE (Background Debug Mode)
8
$0030 – $0033
CORE (PPAGE, Port K)
$0034 – $003F
Clock and Reset Generator (PLL, RTI, COP)
4
12
$0040 – $006F
Standard Timer Module 16-bit 8 channels (TIM)
48
$0070 – $007F
Reserved
16
$0080 – $00AF
Analog to Digital Converter 10-bit 16 channels (ATD)
48
$00B0 – $00BF
Reserved
16
$00C0 – $00C7
Inter Integrated Circuit (IIC)
8
27
MC9S12H256 Device User Guide — V01.20
Table 1-2 Device Memory Map MC9S12H128
Address
28
Module
Size
(Bytes)
$00C8 – $00CF
Serial Communications Interface 0 (SCI0)
8
8
$00D0 – $00D7
Reserved
$00D8 – $00DF
Serial Peripheral Interface (SPI)
$00E0 – $00FF
Pulse Width Modulator 8-bit 6 channels (PWM)
32
$0100 – $010F
Flash control registers
16
$0110 – $011B
EEPROM control registers
12
$011C – $011F
Reserved
8
4
$0120 – $0137
Liquid Crystal Display Driver 32x4 (LCD)
24
$0140 – $017F
Freescale Scalable Controller Area Network 0
(MSCAN0)
64
$0180 – $01BF
Freescale Scalable Controller Area Network 1
(MSCAN1)
64
$01C0 – $01FF
Motor Control Module (MC)
$0200 – $027F
Port Integration Module (PIM)
$0280 – $03FF
Reserved
$0000 – $07FF
EEPROM array
64
128
384
2048
$1000 – $3FFF
RAM array
12288
$4000 – $7FFF
Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
16384
$8000 – $BFFF
Flash EEPROM Page Window
16384
$C000 – $FFFF
Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 – $FFFF
16384
MC9S12H256 Device User Guide — V01.20
$0000
$0400
$0800
$2800
$0000
1K Register Space
$03FF
Mappable to any 2K Boundary
$0000
2K Bytes EEPROM
initially overlapped by register space
$07FF
Mappable to any 4K Boundary
$2800
6K Bytes RAM
Alignable to top ($2800 – $3FFF)
or bottom ($0000 – $17FF)
$4000
$3FFF
Mappable to any 16K Boundary
$4000
0.5K, 1K, 2K or 4K Protected Sector
$7FFF
16K Fixed Flash EEPROM
$8000
$8000
16K Page Window
Sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
$C000
16K Fixed Flash EEPROM
$FFFF
2K, 4K, 8K or 16K Protected Boot Sector
$FF00
$FF00
$FFFF
VECTORS
VECTORS
VECTORS
NORMAL
SINGLE CHIP
EXPANDED*
SPECIAL
SINGLE CHIP
$FFFF
BDM
(If Active)
* Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode
Figure 1-4 MC9S12H128 Memory Map
29
MC9S12H256 Device User Guide — V01.20
1.5.1 Detailed Register Map
$0000 - $000F
Address
Name
$0000
PORTA
$0001
PORTB
$0002
DDRA
$0003
DDRB
$0004
Reserved
$0005
Reserved
$0006
Reserved
$0007
Reserved
$0008
PORTE
$0009
DDRE
$000A
PEAR
$000B
MODE
$000C
PUCR
$000D
RDRIV
$000E
EBICTL
$000F
Reserved
$0010 - $0014
Address
30
Name
$0010
INITRM
$0011
INITRG
$0012
INITEE
$0013
MISC
$0014
MTST0
Test Only
MEBI map 1 of 3 (Core User Guide)
Bit 7
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
NOACCE
Write:
Read:
MODC
Write:
Read:
PUPKE
Write:
Read:
RDPK
Write:
Read:
0
Write:
Read:
0
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
Bit 1
Bit 0
6
5
4
3
Bit 2
0
0
PIPOE
NECLK
LSTRE
RDWE
0
0
EMK
EME
PUPBE
PUPAE
RDPB
RDPA
0
MODB
MODA
0
0
0
0
0
0
0
0
0
IVIS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
PUPEE
RDPE
ESTR
MMC map 1 of 4 (Core User Guide)
Bit 7
Read:
RAM15
Write:
Read:
0
Write:
Read:
EE15
Write:
Read:
0
Write:
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
RAM14
RAM13
RAM12
RAM11
REG14
REG13
REG12
REG11
EE14
EE13
EE12
0
0
0
6
5
4
0
RAMHAL
0
EEON
EXSTR1 EXSTR0 ROMHM ROMON
3
2
1
Bit 0
MC9S12H256 Device User Guide — V01.20
$0015 - $0016
Address
INT map 1 of 2 (Core User Guide)
Name
$0015
ITCR
$0016
ITEST
Read:
Write:
Read:
Write:
$0017 - $0017
Address
$0017
Name
MTST1
Test Only
Read:
Write:
Reserved
$0019
Reserved
$001A
PARTIDH
$001B
PARTIDL
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$001C - $001D
Address
Name
$001C
MEMSIZ0
$001D
MEMSIZ1
$001E
$001F
Read:
Write:
Bit 1
Bit 0
WRINT
ADR3
ADR2
ADR1
ADR0
INT8
INT6
INT4
INT2
INT0
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Bit 4
4
Bit 3
3
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bit 3
0
0
Bit 2
Bit 1
Bit 0
ram_sw2 ram_sw1 ram_sw0
0
pag_sw1 pag_sw0
Bit 7
Bit 6
IRQE
IRQEN
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 0
0
INT map 2 of 2 (Core User Guide)
Name
HPRIO
INTA
Bit 2
MEBI map 2 of 3 (Core User Guide)
$001F - $001F
Address
INTC
Bit 3
Bit 7
Bit 6
Bit 5
Bit 4
Read: reg_sw0
0
eep_sw1 eep_sw0
Write:
Read: rom_sw1 rom_sw0
0
0
Write:
Name
INTCR
INTE
Bit 4
MMC map 3 of 4 (Core and Device User Guide, Table 1-6)
$001E - $001E
Address
Bit 5
0
Miscellaneous Peripherals (Device User Guide, Table 1-5)
Name
$0018
Bit 6
0
MMC map 2 of 4 (Core User Guide)
$0018 - $001B
Address
Bit 7
0
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
31
MC9S12H256 Device User Guide — V01.20
$0020 - $0027
Address
$0020 $0027
Reserved
Name
Reserved
Read:
Write:
$0028 - $002F
Address
Name
$0028
BKPCT0
$0029
BKPCT1
$002A
BKP0X
$002B
BKP0H
$002C
BKP0L
$002D
BKP1X
$002E
BKP1H
$002F
BKP1L
PPAGE
$0031
Reserved
Read:
Write:
Read:
Write:
32
PORTK
$0033
DDRK
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 7
0
Bit 6
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
0
0
0
0
0
0
MEBI map 3 of 3 (Core User Guide)
Name
$0032
Bit 4
0
MMC map 4 of 4 (Core User Guide)
$0032 - $0033
Address
Bit 5
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
0
0
0
0
BKEN
BKFULL BKBDM BKTAG
Write:
Read:
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Write:
Read:
0
0
BK0V5
BK0V4
BK0V3
BK0V2
BK0V1
BK0V0
Write:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Read:
0
0
BK1V5
BK1V4
BK1V3
BK1V2
BK1V1
BK1V0
Write:
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Name
$0030
Bit 6
0
BKP (Core User Guide)
$0030 - $0031
Address
Bit 7
0
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
MC9S12H256 Device User Guide — V01.20
$0034 - $003F
Address
Name
$0034
SYNR
$0035
REFDV
$0036
CTFLG
TEST ONLY
$0037
CRGFLG
$0038
CRGINT
$0039
CLKSEL
$003A
PLLCTL
$003B
RTICTL
$003C
COPCTL
$003D
$003E
$003F
FORBYP
TEST ONLY
CTCTL
TEST ONLY
ARMCOP
$0040 - $006F
Address
Name
$0040
TIOS
$0041
CFORC
$0042
OC7M
$0043
OC7D
$0044
TCNT (hi)
$0045
TCNT (lo)
$0046
TSCR1
$0047
TTOV
$0048
TCTL1
$0049
TCTL2
CRG (Clock and Reset Generator)
Bit 7
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
RTIF
Write:
Read:
RTIE
Write:
Read:
PLLSEL
Write:
Read:
CME
Write:
Read:
0
Write:
Read:
WCOP
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
0
0
0
0
0
0
PORF
0
PSTP
0
0
LOCKIF
LOCKIE
SYSWAI ROAWAI
REFDV3 REFDV2 REFDV1 REFDV0
0
0
LOCK
TRACK
0
0
PLLWAI
CWAI
RTIWAI
COPWAI
PRE
PCE
SCME
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
0
SCMIF
SCMIE
0
SCM
0
PLLON
AUTO
ACQ
RTR6
RTR5
RTR4
RTR3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
RSBCK
TIM (Timer 16 Bit 8 Channels)
Bit 7
Read:
IOS7
Write:
Read:
0
Write: FOC7
Read:
OC7M7
Write:
Read:
OC7D7
Write:
Read: Bit 15
Write:
Read:
Bit 7
Write:
Read:
TEN
Write:
Read:
TOV7
Write:
Read:
OM7
Write:
Read:
OM3
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
FOC6
0
FOC5
0
FOC4
0
FOC3
0
FOC2
0
FOC1
0
FOC0
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
TSWAI
TSFRZ
TFFCA
0
0
0
0
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OL7
OM6
OL6
OM5
OL5
OM4
OL4
OL3
OM2
OL2
OM1
OL1
OM0
OL0
33
MC9S12H256 Device User Guide — V01.20
$0040 - $006F
34
Address
Name
$004A
TCTL3
$004B
TCTL4
$004C
TIE
$004D
TSCR2
$004E
TFLG1
$004F
TFLG2
$0050
TC0 (hi)
$0051
TC0 (lo)
$0052
TC1 (hi)
$0053
TC1 (lo)
$0054
TC2 (hi)
$0055
TC2 (lo)
$0056
TC3 (hi)
$0057
TC3 (lo)
$0058
TC4 (hi)
$0059
TC4 (lo)
$005A
TC5 (hi)
$005B
TC5 (lo)
$005C
TC6 (hi)
$005D
TC6 (lo)
$005E
TC7 (hi)
$005F
TC7 (lo)
$0060
PACTL
$0061
PAFLG
$0062
PACNT (hi)
TIM (Timer 16 Bit 8 Channels)
Bit 7
Read:
EDG7B
Write:
Read:
EDG3B
Write:
Read:
C7I
Write:
Read:
TOI
Write:
Read:
C7F
Write:
Read:
TOF
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
Bit 15
Write:
Read:
Bit 7
Write:
Read:
0
Write:
Read:
0
Write:
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
TCRE
PR2
PR1
PR0
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
14
13
12
11
10
9
Bit 8
6
5
4
3
2
1
Bit 0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
PAOVF
PAIF
6
5
4
3
2
1
Bit 0
MC9S12H256 Device User Guide — V01.20
$0040 - $006F
Address
TIM (Timer 16 Bit 8 Channels)
Name
$0063
PACNT (lo)
$0064
Reserved
$0065
Reserved
$0066
Reserved
$0067
Reserved
$0068
Reserved
$0069
Reserved
$006A
Reserved
$006B
Reserved
$006C
Reserved
$006D
TIMTST
Test Only
$006E
Reserved
$006F
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0070 - $007F
Address
$0070 $007F
$0080 - $00AF
Address
Name
$0080
ATDCTL0
$0081
ATDCTL1
$0082
ATDCTL2
$0083
ATDCTL3
$0084
ATDCTL4
$0085
ATDCTL5
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
TCBYP
PCBYP
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Name
Reserved
Bit 7
Read:
Write:
Bit 7
0
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Bit 7
Read:
0
Write:
Read:
0
Write:
Read:
ADPU
Write:
Read:
0
Write:
Read:
SRES8
Write:
Read:
DJM
Write:
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
AFFC
AWAI
ETRIG
ASCIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DSGN
SCAN
MULT
CD
CC
CB
CA
ETRIGLE ETRIGP
ASCIF
35
MC9S12H256 Device User Guide — V01.20
$0080 - $00AF
Address
36
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Name
$0086
ATDSTAT0
$0087
Reserved
$0088
ATDTEST0
$0089
ATDTEST1
$008A
ATDSTAT2
$008B
ATDSTAT1
$008C
ATDDIEN0
$008D
ATDDIEN1
$008E
PORTAD0
$008F
PORTAD1
$0090
ATDDR0H
$0091
ATDDR0L
$0092
ATDDR1H
$0093
ATDDR1L
$0094
ATDDR2H
$0095
ATDDR2L
$0096
ATDDR3H
$0097
ATDDR3L
$0098
ATDDR4H
$0099
ATDDR4L
$009A
ATDDR5H
$009B
ATDDR5L
$009C
ATDDR6H
$009D
ATDDR6L
$009E
ATDDR7H
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
SCF
Bit 6
0
Bit 5
ETORF
Bit 4
FIFOR
Bit 3
CC3
Bit 2
CC2
Bit 1
CC1
Bit 0
CC0
0
0
0
0
0
0
0
0
SAR9
SAR8
SAR7
SAR6
SAR5
SAR4
SAR3
SAR2
SAR1
SAR0
0
0
0
CCF15
CCF14
CCF13
CCF12
CCF11
CCF10
CCF9
CCF8
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
BIT 0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
RST
ATDCLK
SC
MC9S12H256 Device User Guide — V01.20
$0080 - $00AF
Address
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Name
$009F
ATDDR7L
$00A0
ATDDR8H
$00A1
ATDDR8L
$00A2
ATDDR9H
$00A3
ATDDR9L
$00A4
ATDDR10H
$00A5
ATDDR10L
$00A6
ATDDR11H
$00A7
ATDDR11L
$00A8
ATDDR12H
$00A9
ATDDR12L
$00AA
ATDDR13H
$00AB
ATDDR13L
$00AC
ATDDR14H
$00AD
ATDDR14L
$00aE
ATDDR15H
$00AF
ATDDR15L
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00B0 - $00BF
Address
$00B0 $00BF
Read:
Write:
$00C0 - $00C7
Address
IBAD
$00E1
IBFD
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit15
14
13
12
11
10
9
Bit8
Bit7
6
5
4
3
2
1
Bit0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 7
0
IIC (Inter IC Bus)
Name
$00C0
Bit 6
6
Reserved
Name
Reserved
Bit 7
Bit7
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
37
MC9S12H256 Device User Guide — V01.20
$00C0 - $00C7
Address
Name
$00C2
IBCR
$00C3
IBSR
$00C4
IBDR
$00C5
Reserved
$00C6
Reserved
$00C7
Reserved
$00C8 - $00CF
Address
Name
$00C8
SCI0BDH
$00C9
SCI0BDL
$00CA
SCI0CR1
$00CB
SCI0CR2
$00CC
SCI0SR1
$00CD
SCI0SR2
$00CE
SCI0DRH
$00CF
SCI0DRL
$00D0 - $00D7
Address
38
IIC (Inter IC Bus)
Name
$00D0
SCI1BDH
$00D1
SCI1BDL
$00D2
SCI1CR1
$00D3
SCI1CR2
$00D4
SCI1SR1
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
0
0
Bit 2
0
RSTA
SRW
IBEN
IBIE
MS/SL
TX/RX
TXAK
TCF
IAAS
IBB
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IBAL
IBIF
Bit 0
IBSWAI
RXAK
SCI0 (Asynchronous Serial Interface)
Bit 7
Bit 6
Read:
0
0
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Read:
0
0
Write:
Read:
R8
T8
Write:
Read:
R7
R6
Write:
T7
T6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
0
0
0
BRK13
TXDIR
0
0
0
0
0
0
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
RAF
SCI1 (Asynchronous Serial Interface) only on MC9S12H256
Bit 7
Bit 6
Read:
0
0
Write:
Read:
SBR7
SBR6
Write:
Read:
LOOPS SCISWAI
Write:
Read:
TIE
TCIE
Write:
Read: TDRE
TC
Write:
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RSRC
M
WAKE
ILT
PE
PT
RIE
ILIE
TE
RE
RWU
SBK
RDRF
IDLE
OR
NF
FE
PF
MC9S12H256 Device User Guide — V01.20
$00D0 - $00D7
Address
SCI1 (Asynchronous Serial Interface) only on MC9S12H256
Name
$00D5
SCI1SR2
$00D6
SCI1DRH
$00D7
SCI1DRL
Read:
Write:
Read:
Write:
Read:
Write:
$00D8 - $00DF
Address
SPICR1
$00D9
SPICR2
$00DA
SPIBR
$00DB
SPISR
$00DC
Reserved
$00DD
SPIDR
$00DE
Reserved
$00DF
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$00E0 - $00FF
Address
PWME
$00E1
PWMPOL
$00E2
PWMCLK
$00E3
PWMPRCLK
$00E4
PWMCAE
$00E5
PWMCTL
$00E6
$00E7
$00E8
PWMTST
Test Only
PWMPRSC
Test Only
PWMSCLA
R7
T7
T8
R6
T6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
0
0
R5
T5
R4
T4
Bit 0
RAF
BRK13
TXDIR
0
0
0
0
R3
T3
R2
T2
R1
T1
R0
T0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
SPISWAI
SPC0
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODFEN BIDIROE
0
0
PWM (Pulse Width Modulator 8 Bit 6 Channel)
Name
$00E0
R8
Bit 6
0
SPI (Serial Peripheral Interface)
Name
$00D8
Bit 7
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
0
0
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
0
0
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
CON45
CON23
CON01
PSWAI
PFRZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
PCKB2
0
0
39
MC9S12H256 Device User Guide — V01.20
$00E0 - $00FF
Address
$00E9
$00EA
$00EB
$00EC
$00ED
$00EE
$00EF
$00F0
$00F1
$00F2
$00F3
$00F4
$00F5
$00F6
$00F7
$00F8
$00F9
$00FA
$00FB
$00FC
$00FD
$00FE
$00FF
40
Name
PWM (Pulse Width Modulator 8 Bit 6 Channel)
Bit 7
Read:
PWMSCLB
Bit 7
Write:
0
PWMSCNTA Read:
Test Only
Write:
0
PWMSCNTB Read:
Test Only
Write:
Read:
Bit 7
PWMCNT0
Write:
0
Read:
Bit 7
PWMCNT1
Write:
0
Read:
Bit 7
PWMCNT2
Write:
0
Read:
Bit 7
PWMCNT3
Write:
0
Read:
Bit 7
PWMCNT4
Write:
0
Read:
Bit 7
PWMCNT5
Write:
0
Read:
PWMPER0
Bit 7
Write:
Read:
PWMPER1
Bit 7
Write:
Read:
PWMPER2
Bit 7
Write:
Read:
PWMPER3
Bit 7
Write:
Read:
PWMPER4
Bit 7
Write:
Read:
PWMPER5
Bit 7
Write:
Read:
PWMDTY0
Bit 7
Write:
Read:
PWMDTY1
Bit 7
Write:
Read:
PWMDTY2
Bit 7
Write:
Read:
PWMDTY3
Bit 7
Write:
Read:
PWMDTY4
Bit 7
Write:
Read:
PWMDTY5
Bit 7
Write:
Read:
PWMSDN
PWMIF
Write:
Read:
0
Reserved
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
PWM5IN
0
0
PWMIE
0
PWMRSTRT PWMLVL
0
0
PWM5INL PWM5ENA
0
0
MC9S12H256 Device User Guide — V01.20
$0100 - $010F
Address
Name
$0100
FCLKDIV
$0101
FSEC
$0102
Reserved
$0103
FCNFG
$0104
FPROT
$0105
FSTAT
$0106
FCMD
$0107
Reserved for
Factory Test
$0108
FADDRHI
$0109
FADDRLO
$010A
FDATAHI
$010B
FDATALO
$010C $010F
Reserved
$0110 - $011B
Address
Name
$0110
ECLKDIV
$0111
Reserved
$0112
Reserved for
Factory Test
$0113
ECNFG
$0114
EPROT
$0115
ESTAT
$0116
ECMD
$0117
Reserved for
Factory Test
$0118
EADDRHI
Flash Control Register (fts256k)
Bit 7
Bit 6
Read: FDIVLD
PRDIV8
Write:
Read: KEYEN
NV6
Write:
Read:
0
0
Write:
Read:
CBEIE
CCIE
Write:
Read:
FPOPEN
NV6
Write:
Read:
CCIF
CBEIF
Write:
Read:
0
CMDB6
Write:
Read:
0
0
Write:
Read:
0
Bit 14
Write:
Read:
Bit 7
6
Write:
Read:
Bit 15
14
Write:
Read:
Bit 7
6
Write:
Read:
0
0
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
NV5
NV4
NV3
NV2
SEC1
SEC0
0
WRALL
0
0
0
0
0
0
FPHDIS
FPHS1
FPHS0
FPLDIS
PVIOL
ACCERR
KEYACC
0
BLANK
0
BKSEL1
BKSEL0
FPLS1
FPLS0
0
0
0
0
0
0
0
0
0
0
13
12
11
10
9
Bit 8
5
4
3
2
1
Bit 0
13
12
11
10
9
Bit 8
5
4
3
2
1
Bit 0
0
0
0
0
0
0
CMDB5
CMDB2
0
CMDB0
EEPROM Control Register (eets4k)
Bit 7
Bit 6
Read: EDIVLD
PRDIV8
Write:
Read:
0
0
Write:
Read:
0
0
Write:
Read:
CBEIE
CCIE
Write:
Read:
EPOPEN
NV6
Write:
Read:
CCIF
CBEIF
Write:
Read:
0
CMDB6
Write:
Read:
0
0
Write:
Read:
0
0
Write:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDIV5
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NV5
NV4
EPDIS
EP2
EP1
EP0
PVIOL
ACCERR
0
0
0
0
0
0
0
0
0
0
0
CMDB5
BLANK
CMDB2
0
CMDB0
0
0
0
10
9
Bit 8
41
MC9S12H256 Device User Guide — V01.20
$0110 - $011B
Address
EEPROM Control Register (eets4k)
Name
$0119
EADDRLO
$011A
EDATAHI
$011B
EDATALO
Read:
Write:
Read:
Write:
Read:
Write:
$011C - $011F
Address
$011C $011F
Read:
Write:
$0120 - $0137
Address
42
LCDCR0
$0121
LCDCR1
$0122
FPENR0
$0123
FPENR1
$0124
FPENR2
$0125
FPENR3
$0126
Reserved
$0127
Reserved
$0128
LCDRAM0
$0129
LCDRAM1
$012A
LCDRAM2
$012B
LCDRAM3
$012C
LCDRAM4
$012D
LCDRAM5
$012E
LCDRAM6
$012F
LCDRAM7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
Bit 2
0
Bit 1
0
Bit 0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
Name
$0120
Bit 6
Reserved for RAM Control Register
Name
Reserved
Bit 7
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
LCDEN
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCLK2
LCLK1
LCLK0
BIAS
DUTY1
DUTY0
LCDSWAI
LCDRPSTP
0
0
0
0
0
0
FPEN7
FPEN6
FPEN5
FPEN4
FPEN3
FPEN2
FPEN1
FPEN0
FPEN15
FPEN14
FPEN13
FPEN12
FPEN11
FPEN10
FPEN9
FPEN8
FPEN23
FPEN22
FPEN21
FPEN20
FPEN19
FPEN18
FPEN17
FPEN16
FPEN31
FPEN30
FPEN29
FPEN28
FPEN27
FPEN26
FPEN25
FPEN24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FP1BP3
FP1BP2
FP1BP1
FP1BP0
FP0BP3
FP0BP2
FP0BP1
FP0BP0
FP3BP3
FP3BP2
FP3BP1
FP3BP0
FP2BP3
FP2BP2
FP2BP1
FP2BP0
FP5BP3
FP5BP2
FP5BP1
FP5BP0
FP4BP3
FP4BP2
FP4BP1
FP4BP0
FP7BP3
FP7BP2
FP7BP1
FP7BP0
FP6BP3
FP6BP2
FP6BP1
FP6BP0
FP9BP3
FP9BP2
FP9BP1
FP9BP0
FP8BP3
FP8BP2
FP8BP1
FP8BP0
FP11BP3 FP11BP2 FP11BP1 FP11BP0 FP10BP3 FP10BP2 FP10BP1 FP10BP0
FP13BP3 FP13BP2 FP13BP1 FP13BP0 FP12BP3 FP12BP2 FP12BP1 FP12BP0
FP15BP3 FP15BP2 FP15BP1 FP15BP0 FP14BP3 FP14BP2 FP14BP1 FP14BP0
MC9S12H256 Device User Guide — V01.20
$0120 - $0137
Address
Name
$0130
LCDRAM8
$0131
LCDRAM9
$0132
LCDRAM10
$0133
LCDRAM11
$0134
LCDRAM12
$0135
LCDRAM13
$0136
LCDRAM14
$0137
LCDRAM15
$0140 - $017F
Address
$0140
$0141
$0142
$0143
$0144
$0145
$0146
$0147
$0148
$0149
$014A
$014B
$014C
$014D
$014E
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
Name
Bit 7
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FP17BP3 FP17BP2 FP17BP1 FP17BP0 FP16BP3 FP16BP2 FP16BP1 FP16BP0
FP19BP3 FP19BP2 FP19BP1 FP19BP0 FP18BP3 FP18BP2 FP18BP1 FP18BP0
FP21BP3 FP21BP2 FP21BP1 FP21BP0 FP20BP3 FP20BP2 FP20BP1 FP20BP0
FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0
FP25BP3 FP25BP2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0
FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0
FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0
FP31BP3 FP31BP2 FP31BP1 FP31BP0 FP30BP3 FP30BP2 FP30BP1 FP30BP0
CAN0 (Freescale Scalable CAN - MSCAN)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Read:
RXACT
SYNCH
CAN0CTL0
RXFRM
CSWAI
TIME
Write:
Read:
0
CAN0CTL1
CANE CLKSRC LOOPB LISTEN
Write:
Read:
CAN0BTR0
SJW1
SJW0
BRP5
BRP4
BRP3
Write:
Read:
CAN0BTR1
SAMP TSEG22 TSEG21 TSEG20 TSEG13
Write:
Read:
RSTAT1 RSTAT0 TSTAT1
CAN0RFLG
WUPIF
CSCIF
Write:
Read:
CAN0RIER
WUPIE
CSCIE RSTATE1 RSTATE0 TSTATE1
Write:
Read:
0
0
0
0
0
CAN0TFLG
Write:
Read:
0
0
0
0
0
CAN0TIER
Write:
Read:
0
0
0
0
0
CAN0TARQ
Write:
Read:
0
0
0
0
0
CAN0TAAK
Write:
Read:
0
0
0
0
0
CAN0TBSEL
Write:
Read:
0
0
0
CAN0IDAC
IDAM1
IDAM0
Write:
Read:
0
0
0
0
0
Reserved
Write:
Read:
0
0
0
0
0
Reserved
Write:
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3
CAN0RXERR
Write:
Bit 2
Bit 1
Bit 0
WUPE
SLPRQ
INITRQ
SLPAK
INITAK
BRP1
BRP0
WUPM
BRP2
TSEG12 TSEG11 TSEG10
TSTAT0
OVRIF
RXF
TSTATE0
OVRIE
RXFIE
TXE2
TXE1
TXE0
TXEIE2
TXEIE1
TXEIE0
ABTRQ2 ABTRQ1 ABTRQ0
ABTAK2
ABTAK1
ABTAK0
TX2
TX1
TX0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
RXERR2 RXERR1 RXERR0
43
MC9S12H256 Device User Guide — V01.20
$0140 - $017F
Address
Name
$014F
CAN0TXERR
$0150 $0153
$0154 $0157
$0158 $015B
$015C $015F
$0160 $016F
$0170 $017F
CAN0IDAR0 CAN0IDAR3
CAN0IDMR0 CAN0IDMR3
CAN0IDAR4 CAN0IDAR7
CAN0IDMR4 CAN0IDMR7
CAN0RXFG
CAN0TXFG
CAN0 (Freescale Scalable CAN - MSCAN)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
FOREGROUND RECEIVE BUFFER see Table 1-3
Write:
Read:
FOREGROUND TRANSMIT BUFFER see Table 1-3
Write:
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$0160
$0161
$0162
$0163
$0164$016B
$016C
$016D
$016E
$016F
$0170
$0171
44
Name
Extended ID
Standard ID
CAN0RIDR0
Extended ID
Standard ID
CAN0RIDR1
Extended ID
Standard ID
CAN0RIDR2
Extended ID
Standard ID
CAN0RIDR3
CAN0RDSR0 CAN0RDSR7
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Write:
Read:
CAN0RDLR
Write:
Read:
Reserved
Write:
Read:
CAN0RTSRH
Write:
Read:
CAN0RTSRL
Write:
Extended ID Read:
CAN0TIDR0 Write:
Standard ID Read:
Write:
Extended ID Read:
CAN0TIDR1 Write:
Standard ID Read:
Write:
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID20
ID19
ID18
SRR=1
IDE=1
ID17
ID16
ID15
ID2
ID1
ID0
RTR
IDE=0
MC9S12H256 Device User Guide — V01.20
Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$0172
$0173
Name
Extended ID
CAN0TIDR2
Standard ID
Extended ID
CAN0TIDR3
Standard ID
$0174$017B
CAN0TDSR0 CAN0TDSR7
$017C
CAN0TDLR
$017D
CON0TTBPR
$017E
CAN0TTSRH
$017F
CAN0TTSRL
$0180 - $01BF
Address
$0180
$0181
$0182
$0183
$0184
$0185
$0186
$0187
$0188
$0189
$018A
$018B
$018C
$018D
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
CAN1 (Freescale Scalable CAN - MSCAN)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
RXACT
SYNCH
CAN1CTL0
RXFRM
CSWAI
TIME
WUPE
SLPRQ INITRQ
Write:
Read:
0
SLPAK
INITAK
CAN1CTL1
CANE CLKSRC LOOPB LISTEN
WUPM
Write:
Read:
CAN1BTR0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Write:
Read:
CAN1BTR1
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Read:
RSTAT1 RSTAT0 TSTAT1 TSTAT0
CAN1RFLG
WUPIF
CSCIF
OVRIF
RXF
Write:
Read:
CAN1RIER
WUPIE
CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE
RXFIE
Write:
Read:
0
0
0
0
0
CAN1TFLG
TXE2
TXE1
TXE0
Write:
Read:
0
0
0
0
0
CAN1TIER
TXEIE2 TXEIE1 TXEIE0
Write:
Read:
0
0
0
0
0
CAN1TARQ
ABTRQ2 ABTRQ1 ABTRQ0
Write:
Read:
0
0
0
0
0
ABTAK2 ABTAK1 ABTAK0
CAN1TAAK
Write:
Read:
0
0
0
0
0
CAN1TBSEL
TX2
TX1
TX0
Write:
Read:
0
0
0
IDHIT2
IDHIT1
IDHIT0
CAN1IDAC
IDAM1
IDAM0
Write:
Read:
0
0
0
0
0
0
0
0
Reserved
Write:
Read:
0
0
0
0
0
0
0
0
Reserved
Write:
45
MC9S12H256 Device User Guide — V01.20
$0180 - $01BF
Address
Name
$018E
CAN1RXERR
$018F
CAN1TXERR
$0190 $0193
$0194 $0197
$0198 $019B
$019C $019F
$01A0 $01AF
$01B0 $01BF
CAN1IDAR0 CAN1IDAR3
CAN1IDMR0 CAN1IDMR3
CAN1IDAR4 CAN1IDAR7
CAN1IDMR4 CAN1IDMR7
CAN1RXFG
CAN1TXFG
CAN1 (Freescale Scalable CAN - MSCAN)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
Write:
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Write:
Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Write:
Read:
FOREGROUND RECEIVE BUFFER see Table 1-3
Write:
Read:
FOREGROUND TRANSMIT BUFFER see Table 1-3
Write:
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$01A0
$01A1
$01A2
$01A3
$01A4$01AB
$01AC
$01AD
$01AE
$01AF
$01B0
46
Name
Extended ID
Standard ID
CAN1RIDR0
Extended ID
Standard ID
CAN1RIDR1
Extended ID
Standard ID
CAN1RIDR2
Extended ID
Standard ID
CAN1RIDR3
CAN1RDSR0 CAN1RDSR7
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Read:
Write:
Read:
Write:
Read:
CAN1RDLR
Write:
Read:
Reserved
Write:
Read:
CAN1RTSRH
Write:
Read:
CAN1RTSRL
Write:
Extended ID Read:
CAN1TIDR0 Write:
Standard ID Read:
Write:
Bit 7
ID28
ID10
Bit 6
ID27
ID9
Bit 5
ID26
ID8
Bit 4
ID25
ID7
Bit 3
ID24
ID6
Bit 2
ID23
ID5
Bit 1
ID22
ID4
Bit 0
ID21
ID3
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
MC9S12H256 Device User Guide — V01.20
Table 1-4 Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address
$01B1
$01B2
$01B3
Name
Extended ID
CAN1TIDR1
Standard ID
Extended ID
CAN1TIDR2
Standard ID
Extended ID
CAN1TIDR3
Standard ID
$01B4$01BB
CAN1TDSR0 CAN1TDSR7
$01BC
CAN1TDLR
$01BD
CON1TTBPR
$01BE
CAN1TTSRH
$01BF
CAN1TTSRL
$01C0 - $01FF
Address
Name
$01C0
MCCTL0
$01C1
MCCTL1
$01C2
MCPER (hi)
$01C3
MCPER (lo)
$01C4
Reserved
$01C5
Reserved
$01C6
Reserved
$01C7
Reserved
$01C8
Reserved
$01C9
Reserved
$01CA
Reserved
$01CB
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID20
ID19
ID18
SRR=1
IDE=1
ID17
ID16
ID15
ID2
ID1
ID0
RTR
IDE=0
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
Bit 1
0
Bit 0
MC (Motor Controller 10bit 12 channels)
Bit 7
Bit 6
Bit 5
Bit 4
Read:
0
MCPRE1 MCPRE0 MCSWAI
Write:
Read:
0
0
0
RECIRC
Write:
Read:
0
0
0
0
Write:
Read:
P7
P6
P5
P4
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Read:
0
0
0
0
Write:
Bit 3
Bit 2
FAST
DITH
0
0
0
P10
P9
P8
P3
P2
P1
P0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCTOIF
MCTOIE
47
MC9S12H256 Device User Guide — V01.20
$01C0 - $01FF
Address
48
MC (Motor Controller 10bit 12 channels)
Name
$01CC
Reserved
$01CD
Reserved
$01CE
Reserved
$01CF
Reserved
$01D0
MCCC0
$01D1
MCCC1
$01D2
MCCC2
$01D3
MCCC3
$01D4
MCCC4
$01D5
MCCC5
$01D6
MCCC6
$01D7
MCCC7
$01D8
MCCC8
$01D9
MCCC9
$01DA
MCCC10
$01DB
MCCC11
$01DC
Reserved
$01DD
Reserved
$01DE
Reserved
$01DF
Reserved
$01E0
MCDC0 (hi)
$01E1
MCDC0 (lo)
$01E2
MCDC1 (hi)
$01E3
MCDC1 (lo)
$01E4
MCDC2 (hi)
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
OM1
OM0
AM1
AM0
0
0
CD1
CD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
S
D7
S
D7
S
MC9S12H256 Device User Guide — V01.20
$01C0 - $01FF
Address
MC (Motor Controller 10bit 12 channels)
Name
$01E5
MCDC2 (lo)
$01E6
MCDC3 (hi)
$01E7
MCDC3 (lo)
$01E8
MCDC4 (hi)
$01E9
MCDC4 (lo)
$01EA
MCDC5 (hi)
$01EB
MCDC5 (lo)
$01EC
MCDC6 (hi)
$01ED
MCDC6 (lo)
$01EE
MCDC7 (hi)
$01EF
MCDC7 (lo)
$01F0
MCDC8 (hi)
$01F1
MCDC8 (lo)
$01F2
MCDC9 (hi)
$01F3
MCDC9 (lo)
$01F4
MCDC10 (hi)
$01F5
MCDC10 (lo)
$01F6
MCDC11 (hi)
$01F7
MCDC11 (lo)
$01F8
Reserved
$01F9
Reserved
$01FA
Reserved
$01FB
Reserved
$01FC
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
S
S
S
S
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S
D7
S
D7
S
D7
S
D7
S
D7
S
D7
S
D7
S
D7
S
49
MC9S12H256 Device User Guide — V01.20
$01C0 - $01FF
Address
MC (Motor Controller 10bit 12 channels)
Name
$01FD
Reserved
$01FE
Reserved
$01FF
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
$0200 - $027F
Address
50
PTT
$0201
PTIT
$0202
DDRT
$0203
RDRT
$0204
PERT
$0205
PPST
$0206
Reserved
$0207
Reserved
$0208
PTS
$0209
PTIS
$020A
DDRS
$020B
RDRS
$020C
PERS
$020D
PPSS
$020E
WOMS
$020F
Reserved
$0210
PTM
$0211
PTIM
$0212
DDRM
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PIM (Port Integration Module)
Name
$0200
Bit 7
0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT7
DDRT7
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
DDRS7
DDRS7
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
0
0
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
0
0
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
0
0
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
MC9S12H256 Device User Guide — V01.20
$0200 - $027F
Address
PIM (Port Integration Module)
Name
$0213
RDRM
$0214
PERM
$0215
PPSM
$0216
WOMM
$0217
Reserved
$0218
PTP
$0219
PTIP
$021A
DDRP
$021B
RDRP
$021C
PERP
$021D
PPSP
$021E
Reserved
$021F
Reserved
$0220
PTH
$0221
PTIH
$0222
DDRH
$0223
RDRH
$0224
PERH
$0225
PPSH
$0226
PIEH
$0227
PIFH
$0228
PTJ
$0229
PTIJ
$022A
DDRJ
$022B
RDRJ
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
0
0
0
0
0
0
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
DDRH7
DDRH7
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
0
0
0
0
PTJ3
PTJ2
PTJ1
PTJ0
0
0
0
0
PTIJ3
PTIJ2
PTIJ1
PTIJ0
0
0
0
0
DDRJ3
DDRJ2
DDRJ1
DDRJ0
0
0
0
0
RDRJ3
RDRJ2
RDRJ1
RDRJ0
51
MC9S12H256 Device User Guide — V01.20
$0200 - $027F
Address
52
PIM (Port Integration Module)
Name
$022C
PERJ
$022D
PPSJ
$022E
PIEJ
$022F
PIFJ
$0230
PTL
$0231
PTIL
$0232
DDRL
$0233
RDRL
$0234
PERL
$0235
PPSL
$0236
Reserved
$0237
Reserved
$0238
PTU
$0239
PTIU
$023A
DDRU
$023B
SRRU
$023C
PERU
$023D
PPSU
$023E
Reserved
$023F
Reserved
$0240
PTV
$0241
PTIV
$0242
DDRV
$0243
SRRV
$0244
PERV
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
PERJ3
PERJ2
PERJ1
PERJ0
0
0
0
0
PPSJ3
PPSJ2
PPSJ1
PPSJ0
0
0
0
0
PIEJ3
PIEJ2
PIEJ1
PIEJ0
0
0
0
0
PIFJ3
PIFJ2
PIFJ1
PIFJ0
PTL7
PTL6
PTL5
PTL4
PTL3
PTL2
PTL1
PTL0
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
DDRL7
DDRL7
DDRL5
DDRL4
DDRL3
DDRL2
DDRL1
DDRL0
RDRL7
RDRL6
RDRL5
RDRL4
RDRL3
RDRL2
RDRL1
RDRL0
PERL7
PERL6
PERL5
PERL4
PERL3
PERL2
PERL1
PERL0
PPSL7
PPSL6
PPSL5
PPSL4
PPSL3
PPSL2
PPSL1
PPSL0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTU7
PTU6
PTU5
PTU4
PTU3
PTU2
PTU1
PTU0
PTIU7
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
DDRU7
DDRU7
DDRU5
DDRU4
DDRU3
DDRU2
DDRU1
DDRU0
SRRU7
SRRU6
SRRU5
SRRU4
SRRU3
SRRU2
SRRU1
SRRU0
PERU7
PERU6
PERU5
PERU4
PERU3
PERU2
PERU1
PERU0
PPSU7
PPSU6
PPSU5
PPSU4
PPSU3
PPSU2
PPSU1
PPSU0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTV7
PTV6
PTV5
PTV4
PTV3
PTV2
PTV1
PTV0
PTIV7
PTIV6
PTIV5
PTIV4
PTIV3
PTIV2
PTIV1
PTIV0
DDRV7
DDRV7
DDRV5
DDRV4
DDRV3
DDRV2
DDRV1
DDRV0
SRRV7
SRRV6
SRRV5
SRRV4
SRRV3
SRRV2
SRRV1
SRRV0
PERV7
PERV6
PERV5
PERV4
PERV3
PERV2
PERV1
PERV0
MC9S12H256 Device User Guide — V01.20
$0200 - $027F
Address
PIM (Port Integration Module)
Name
$0245
PPSV
$0246
Reserved
$0247
Reserved
$0248
PTW
$0249
PTIW
$024A
DDRW
$024B
SRRW
$024C
PERW
$024D
PPSW
$024E
Reserved
$024F
Reserved
$0250 $027F
Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0280 - $03FF
Address
$0280 $03FF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PPSV7
PPSV6
PPSV5
PPSV4
PPSV3
PPSV2
PPSV1
PPSV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTW7
PTW6
PTW5
PTW4
PTW3
PTW2
PTW1
PTW0
PTIW7
PTIW6
PTIW5
PTIW4
PTIW3
PTIW2
PTIW1
PTIW0
DDRW7
DDRW7
DDRW5
DDRW4
DDRW3
DDRW2
DDRW1
DDRW0
SRRW7
SRRW6
SRRW5
SRRW4
SRRW3
SRRW2
SRRW1
SRRW0
PERW7
PERW6
PERW5
PERW4
PERW3
PERW2
PERW1
PERW0
PPSW7
PPSW6
PPSW5
PPSW4
PPSW3
PPSW2
PPSW1
PPSW0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Name
Reserved
Read:
Write:
Bit 7
0
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL at addresses $001A,$001B,
respectively. The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the
assigned part ID numbers.
Table 1-5 Assigned Part ID Numbers
Device
Mask Set Number
MC9S12H256
MC9S12H256
0K78X
1K78X
Part ID1
$1000
$1001
53
MC9S12H256 Device User Guide — V01.20
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-6 shows the read-only values of these registers. Refer to section Module
Mapping and Control (MMC) of HCS12 Core User Guide for further details.
Table 1-6 Memory size registers
Register name
MEMSIZ0
MEMSIZ1
54
Value
$25
$81
MC9S12H256 Device User Guide — V01.20
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12H256 is available in a 112-pin and 144-pin quad flat pack (LQFP), the MC9S12H128 is
available in a 112-pin quad flat pack (LQFP). Most pins perform two or more functions, as described in
the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
NOTE:
In expanded narrow modes the lower byte data is multiplexed with higher byte data
through pins 64-71 on the 112-pin LQFP or through pins 111-118 on the 144-pin
LQFP version.
55
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12H-Family
112 LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VDDA
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
PE6/IPIPE1/MODB
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
RXD0/PS0
TXD0/PS1
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
RXCAN0/PM2
TXCAN0/PM3
RXCAN1/PM4
TXCAN1/PM5
MODA/IPIP0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
M0C0M/PU0
M0C0P/PU1
M0C1M/PU2
M0C1P/PU3
VDDM1
VSSM1
M1C0M/PU4
M1C0P/PU5
M1C1M/PU6
M1C1P/PU7
M2C0M/PV0
M2C0P/PV1
M2C1M/PV2
M2C1P/PV3
VDDM2
VSSM2
M3C0M/PV4
M3C0P/PV5
M3C1M/PV6
M3C1P/PV7
M4C0M/PW0
M4C0P/PW1
M4C1M/PW2
M4C1P/PW3
VDDM3
VSSM3
M5C0M/PW4
M5C0P/PW5
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
VSSX1
VDDX1
PK7/ECS/ROMONE/FP23
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PE2/R/W/FP20
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
MC9S12H256 Device User Guide — V01.20
Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12H256 and MC9S12H128
56
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PT7/IOC7
PT6/IOC6
PT5/IOC5
PT4/IOC4
PT3/IOC3/FP27
PT2/IOC2/FP26
PT1/IOC1/FP25
PT0/IOC0/FP24
PJ3/KWJ3
PJ2/KWJ2
PJ1/KWJ1
PJ0/KWJ0
VSSX1
VDDX1
PK7/ECS/ROMONE/FP23
PE7/NOACC/XCLKS/FP22
PE3/LSTRB/TAGLO/FP21
PE2/R/W/FP20
PL7/FP31
PL6/FP30
PL5/FP29
PL4/FP28
PL3/FP19
PL2/FP18
PL1/FP17
PL0/FP16
PA7/ADDR15/DATA15/FP15
PA6/ADDR14/DATA14/FP14
PA5/ADDR13/DATA13/FP13
PA4/ADDR12/DATA12/FP12
PA3/ADDR11/DATA11/FP11
PA2/ADDR10/DATA10/FP10
PA1/ADDR9/DATA9/FP9
PA0/ADDR8/DATA8/FP8
PB7/ADDR7/DATA7/FP7
PB6/ADDR6/DATA6/FP6
MC9S12H256 Device User Guide — V01.20
MC9S12H-Family
144 LQFP
Pins shown in BOLD are not available in the 112 LQFP package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PB5/ADDR5/DATA5/FP5
PB4/ADDR4/DATA4/FP4
PB3/ADDR3/DATA3/FP3
PB2/ADDR2/DATA2/FP2
PB1/ADDR1/DATA1/FP1
PB0/ADDR0/DATA0/FP0
PK0/XADDR14/BP0
PK1/XADDR15/BP1
PK2/XADDR16/BP2
PK3/XADDR17/BP3
VLCD
VSS1
VDD1
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VDDA
VRH
VRL
VSSA
PE0/XIRQ
PE4/ECLK
PE6/IPIPE1/MODB
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
M5C1M/PW6
M5C1P/PW7
PWM0/PP0
PWM1/PP1
PWM2/PP2
PWM3/PP3
PWM4/PP4
PWM5/PP5
RXD0/PS0
TXD0/PS1
RXD1/PS2
TXD1/PS3
VSS2
VDDR
VDDX2
VSSX2
MODC/TAGHI/BKGD
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
SDA/PM0
SCL/PM1
RXCAN0/PM2
TXCAN0/PM3
RXCAN1PM4
TXCAN1/PM5
MODA/IPIPE0/PE5
MISO/PS4
MOSI/PS5
SCK/PS6
SS/PS7
IRQ/PE1
M0C0M/PU0
M0C0P/PU1
M0C1M/PU2
M0C1P/PU3
VDDM1
VSSM1
M1C0M/PU4
M1C0P/PU5
M1C1M/PU6
M1C1P/PU7
KWH0/PH0
KWH1/PH1
KWH2/PH2
KWH3/PH3
M2C0M/PV0
M2C0P/PV1
M2C1M/PV2
M2C1P/PV3
VDDM2
VSSM2
M3C0M/PV4
M3C0P/PV5
M3C1M/PV6
M3C1P/PV7
KWH4/PH4
KWH5/PH5
KWH6/PH6
KWH7/PH7
M4C0M/PW0
M4C0P/PW1
M4C1M/PW2
M4C1P/PW3
VDDM3
VSSM3
M5C0M/PW4
M5C0P/PW5
Figure 2-2 Pin Assignments in 144-pin LQFP for MC9S12H256
57
MC9S12H256 Device User Guide — V01.20
2.2 Signal Properties Summary
Table 2-1 summarizes all pin functions.
NOTE:
Bold entries determine pins not available on 112-pin LQFP.
Table 2-1 Signal Properties
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name Powered
Function 4
by
EXTAL
—
—
—
VDDPLL
XTAL
—
—
—
VDDPLL
RESET
—
—
—
VDDX2
TEST
—
—
—
VDDX2
XFC
—
—
—
VDDPLL
BKGD
TAGHI
MODC
—
VDDX2
PAD[7:0]
AN[7:0]
—
—
VDDA
Internal Pull
Resistor
Reset
CTRL
State
Description
Oscillator Pins
None
None
External Reset Pin
Test Input
PLL Loop Filter
Always
Up
Background Debug, Tag High, Mode
Pin
Up
None
None
Port AD Inputs, Analog Inputs
(ATD)
Port AD Inputs, Analog Inputs (ATD)
PAD[15:8]
AN[15:8]
—
—
VDDA
PA[7:0]
FP[15:8]
ADDR[15:8]/
DATA[15:8]
—
VDDX1
PUCR/
PUPAE
Down
Port A I/O, Multiplexed Address/Data
PB[7:0]
FP[7:0]
ADDR[7:0]/
DATA[7:0]
—
VDDX1
PUCR/
PUPBE
Down
Port B I/O, Multiplexed Address/Data
PE7
FP22
XCLKS
NOACC
VDDX1
PUCR/
PUPEE
Down
Port E I/O, Access, Clock Select,
LCD driver
PE6
IPIPE1
MODB
—
VDDX2
PE5
IPIPE0
MODA
—
VDDX2
PE4
ECLK
—
—
VDDX2
PE3
FP21
LSTRB
TAGLO
VDDX1
PE2
FP20
R/W
—
VDDX1
PE1
IRQ
—
—
VDDX2
PE0
XIRQ
—
—
VDDX2
While RESET pin is
low: Down
Port E I/O, Pipe Status, Mode Input
Port E I/O, Bus Clock Output
PUCR/
PUPEE
Mode de- Port E I/O, LCD driver, Byte Strobe,
pendent Tag Low
Port E I/O, R/W in expanded modes
Up
PH[7:0]
KWH[7:0]
—
—
VDDM
PERH/
PPSH
PJ[3:0]
KWJ[3:0]
—
—
VDDX1
PERJ/
PPSJ
PK7
FP23
ECS
ROMONE
VDDX1
PK[3:0]
BP[3:0]
XADDR[17:14]
—
VDDX1
PL[3:0]
FP[19:16]
—
—
VDDX1
PL[7:4]
FP[31:28]
—
—
VDDX1
58
Port E I/O, Pipe Status, Mode Input
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
Disabled Port H I/O, Interrupts
Disabled Port J I/O, Interrupts
PUCR/
PUPKE
Down
PERL/
PPSL
Down
Port K I/O, Emulation Chip Select,
ROM On Enable
Port K I/O, LCD driver, Extended
Addresses
Port L I/O, LCD drivers
Port L I/O, LCD drivers
MC9S12H256 Device User Guide — V01.20
Pin Name Pin Name
Function 1 Function 2
Pin Name
Function 3
Pin Name Powered
Function 4
by
Internal Pull
Resistor
Reset
CTRL
State
Description
PM5
TXCAN1
—
—
VDDX2
Port M I/O, TX of CAN1
PM4
RXCAN1
—
—
VDDX2
Port M I/O, RX of CAN1
PM3
TXCAN0
—
—
VDDX2
PM2
RXCAN0
—
—
VDDX2
PERM/
PPSM
Disabled
Port M I/O, TX of CAN0
Port M I/O, RX of CAN0
PM1
SCL
—
—
VDDX2
Port M I/O, SCL of IIC
PM0
SDA
—
—
VDDX2
Port M I/O, SDA of IIC
PP[5:2]
PWM[5:2]
—
—
VDDX2
PP[1:0]
PWM[1:0]
—
—
VDDX2
PERP/
PPSP
Disabled
Port P I/O, PWM channels
Port P I/O, PWM channels
PS7
SS
—
—
VDDX2
Port S I/O, SS of SPI
PS6
SCK
—
—
VDDX2
Port S I/O, SCK of SPI
PS5
MOSI
—
—
VDDX2
Port S I/O, MOSI of SPI
PS4
MISO
—
—
VDDX2
PERS/
PPSS
Disabled
Port S I/O, MISO of SPI
PS3
TXD1
—
—
VDDX2
PS2
RXD1
—
—
VDDX2
Port S I/O, RXD of SCI1
PS1
TXD0
—
—
VDDX2
Port S I/O, TXD of SCI0
PS0
RXD0
—
—
VDDX2
Port S I/O, RXD of SCI0
PT[7:4]
IOC[7:4]
—
—
VDDX1
PERT/
PPST
Port S I/O, TXD of SCI1
Port T I/O, Timer channels
Down
Port T I/O, Timer channels, LCD
driver
PT[3:0]
IOC[3:0]
FP[27:24]
—
VDDX1
PU[3:0]
M0C0M
M0C0P
M0C1M
M0C1P
—
—
VDDM
PU[7:4]
M1C0M
M1C0P
M1C1M
M1C1P
—
—
VDDM
Port U I/O, Motor1 of MC
PV[3:0]
M2C0M
M2C0P
M2C1M
M2C1P
—
—
VDDM
Port V I/O, Motor2 of MC
PV[7:4]
M3C0M
M3C0P
M3C1M
M3C1P
—
—
VDDM
Port V I/O, Motor3 of MC
PW[3:0]
M4C0M
M4C0P
M4C1M
M4C1P
—
—
VDDM
Port W I/O, Motor4 of MC
PW[7:4]
M5C0M
M5C0P,
M5C1M
M5C1P
—
Port U I/O, Motor0 of MC
PERU/
PPSU
PERV/
PPSV
PERW/
PPSW
—
VDDM
Disabled
Disabled
Disabled
Port W I/O, Motor5 of MC
59
MC9S12H256 Device User Guide — V01.20
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter.
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.6 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]
PAD15-PAD8 are general purpose input pins and analog inputs for the analog to digital converter.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.7 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]
PAD7-PAD0 are general purpose input pins and analog inputs for the analog to digital converter.
2.3.8 PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
60
MC9S12H256 Device User Guide — V01.20
2.3.9 PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7
PE7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP22
of the LCD module. The XCLKS signal selects between an external clock or oscillator configuration
during reset.
The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is
latched at the rising edge of RESET. If the input is a logic high the EXTAL pin is configured for an
external clock drive. If input is a logic low an oscillator circuit is configured on EXTAL and XTAL. Since
this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration
is an oscillator circuit on EXTAL and XTAL.
During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the
current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus.
2.3.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.13 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
2.3.14 PE3 / FP21 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP21
of the LCD module. In MCU expanded modes of operation, LSTRB is used for the low-byte strobe
function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the
low half of the instruction word being read into the instruction queue.
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2.3.15 PE2 / FP20 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP20
of the LCD module. In MCU expanded modes of operations, this pin performs the read/write output signal
for the external bus. It indicates the direction of data on the external bus.
2.3.16 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and also the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.17 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and also the non-maskable interrupt request input that provides a means
of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.18 PH[7:0] / KWH[7:0] — Port H I/O Pins [7:0]
PH7-PH0 are general purpose input or output pins. They can be configured to generate an interrupt causing
the MCU to exit STOP or WAIT mode.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.19 PJ[3:0] / KWJ[3:0] — Port J I/O Pins [3:0]
PJ3-PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing
the MCU to exit STOP or WAIT mode.and are shared with the interrupt function.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.20 PK7 / FP23 / ECS / ROMONE — Port K I/O Pin 7
PK7 is a general purpose input or output pin. It can be configured as frontplane segment driver output FP23
of the LCD module. During MCU expanded modes of operation, this pin is used as the emulation chip
select signal (ECS). During reset of the MCU to normal expanded modes of operation, this pin is used to
enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.
2.3.21 PK[3:0] / BP[3:0] / XADDR[17:14] — Port K I/O Pins [3:0]
PK3-PK0 are general purpose input or output pins. They can be configured as backplane segment driver
outputs BP3-BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the
expanded address XADDR[17:14] for the external bus.
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2.3.22 FreescalePL[7:4] / FP[31:28] — Port L I/O Pins [7:4]
PL7-PL4 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP31-FP28 of the LCD module.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.23 PL[3:0] / FP[19:16] — Port L I/O Pins [3:0]
PL3-PL0 are general purpose input or output pins. They can be configured as frontplane segment driver
outputs FP19-FP16 of the LCD module.
2.3.24 PM5 / TXCAN1 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the
Freescale Scalable Controller Area Network controller 1 (CAN1)
2.3.25 PM4 / RXCAN1 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN1 of the
Freescale Scalable Controller Area Network controller 1 (CAN1)
2.3.26 PM3 / TXCAN0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the
Freescale Scalable Controller Area Network controller 0 (CAN0)
2.3.27 PM2 / RXCAN0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN0 of the
Freescale Scalable Controller Area Network controller 0 (CAN0)
2.3.28 PM1 / SCL — Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the serial clock pin SCL of the
Inter-IC Bus Interface (IIC).
NOTE:
This pin is not available in the 112-pin LQFP version.
2.3.29 PM0 / SDA — Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the serial data pin SDA of the Inter-IC
Bus Interface (IIC).
NOTE:
This pin is not available in the 112-pin LQFP version.
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2.3.30 PP[5:2] / PWM[5:2] — Port P I/O Pins [5:2]
PP5-PP2 are general purpose input or output pins. They can be configured as Pulse Width Modulator
(PWM) channel outputs PWM5-PWM2.
NOTE:
These pins are not available in the 112-pin LQFP version.
2.3.31 PP[1:0] / PWM[1:0] — Port P I/O Pins [1:0]
PP1-PP0 are general purpose input or output pins. They can be configured as Pulse Width Modulator
(PWM) channel outputs PWM1-PWM0.
2.3.32 PS7 / SS — Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as slave select pin SS of the Serial
Peripheral Interface (SPI).
2.3.33 PS6 / SCK — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as serial clock pin SCK of the Serial
Peripheral Interface (SPI).
2.3.34 PS5 / MOSI — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as the master output (during master
mode) or slave input (during slave mode) pin MOSI of the Serial Peripheral Interface (SPI).
2.3.35 PS4 / MISO — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output (during slave mode) pin MISO for the Serial Peripheral Interface (SPI).
2.3.36 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as transmit pin TXD1 of the Serial
Communication Interface 1 (SCI1).
NOTE:
This pin is not available in the 112-pin LQFP version.
2.3.37 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as receive pin RXD1 of the Serial
Communication Interface 1 (SCI1).
NOTE:
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MC9S12H256 Device User Guide — V01.20
2.3.38 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as transmit pin TXD0 of the Serial
Communication Interface 0 (SCI0).
2.3.39 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as receive pin RXD0 of the Serial
Communication Interface 0 (SCI0).
2.3.40 PT[7:4] / IOC[7:4] — Port T I/O Pins [7:4]
PT7-PT4 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC4 of the Timer (TIM).
2.3.41 PT[3:0] / IOC[3:0] / FP[27:24] — Port T I/O Pins [3:0]
PT3-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC3-IOC0 of the Timer (TIM). They can be configured as frontplane segment driver
outputs FP27-FP24 of the LCD module.
2.3.42 PU[7:4] / M1C1P, M1C1M, M1C0P, M1C0M — Port U I/O Pins [7:4]
PU7-PU4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on
M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM
output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high
state.
2.3.43 PU[3:0] / M0C1P, M0C1M, M0C0P, M0C0M — Port U I/O Pins [3:0]
PU3-PU0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on
M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM
output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high
state.
2.3.44 PV[7:4] / M3C1P, M3C1M, M3C0P, M3C0M — Port V I/O Pins [7:4]
PV7-PV4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on
M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM
output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high
state.
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2.3.45 PV[3:0] / M2C1P, M2C1M, M2C0P, M2C0M — Port V I/O Pins [3:0]
PV3-PV0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on
M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. PWM
output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high
state.
2.3.46 PW[7:4] / M5C1P, M5C1M, M5C0P, M5C0M — Port W I/O Pins [7:4]
PW7-PW4 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on
M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. PWM
output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high
state.
2.3.47 PW[3:0] / M4C1P, M4C1M, M4C0P, M4C0M — Port W I/O Pins [3:0]
PW3-PW0 are general purpose input or output pins. They can be configured as high current PWM output
pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on
M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. PWM
output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high
state.
2.4 Power Supply Pins
MC9S12H256 power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application (21.2 Recommended
PCB layout).
Because fast signal transitions place high, short-duration current demands on the
power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily
the MCU pins are loaded (Table 21-1).
2.4.1 VDDR — External Power Pin
VDDR is the power supply pin for the internal voltage regulator.
2.4.2 VDDX1, VDDX2, VSSX1, VSSX2 — External Power and Ground Pins
VDDX1, VDDX2, VSSX1 and VSSX2 are the power supply and ground pins for input/output
drivers.VDDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.
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2.4.3 VDD1, VSS1, VSS2 — Core Power Pins
VDD1, VSS1 and VSS2 are the core power and ground pins and related to the voltage regulator output.
These pins serve as connection points for filter capacitors. VSS1 and VSS2 are internally connected.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog to digital
converter.
2.4.5 VDDM1, VDDM2, VDDM3 — Power Supply Pins for Motor 0 to 5
VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U,V and W. VDDM1, VDDM2 and
VDDM3 are internally connected.
2.4.6 VSSM1, VSSM2, VSSM3 — Ground Pins for Motor 0 to 5
VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U,V and W. VSSM1, VSSM2 and VSSM3
are internally connected.
2.4.7 VLCD — Power Supply Reference Pin for LCD driver
VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the
display contrast.
2.4.8 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the voltage reference pins for the analog to digital converter.
2.4.9 VDDPLL, VSSPLL — Power Supply Pins for PLL
VDDPLL and VSSPLL are the PLL supply pins and serve as connection points for external loop filter
components.
NOTE:
No load allowed except for bypass capacitors.
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Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
S12_CORE
core clock
Flash
RAM
EEPROM
TIM
EXTAL
ATD
CRG
bus clock
PWM
SCI0, SCI1
oscillator clock
XTAL
SPI
CAN0, CAN1
IIC
MC
LCD
PIM
Figure 3-1 Clock Connections
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12H256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
Table 4-1 Mode Selection
MODC
MODB
MODA
Mode Description
0
0
0
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
0
0
1
Emulation Expanded Narrow, BDM allowed
0
1
0
Special Test (Expanded Wide) (Freescale Use Only), BDM allowed
0
1
1
Emulation Expanded Wide, BDM allowed
1
0
0
Normal Single Chip, BDM allowed
1
0
1
Normal Expanded Narrow, BDM allowed
1
1
0
Peripheral (Freescale Use Only); BDM allowed but bus operations
would cause bus conflicts (must not be used)
1
1
1
Normal Expanded Wide, BDM allowed
There are two basic types of operating modes:
1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
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even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as high-impedance mode select inputs during reset.
The following paragraphs discuss the default bus setup and describe which aspects of the bus can be
changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.
4.2.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general
purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups
enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance
inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their
internal pull-ups disabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated Port E pins.
In normal single chip mode, the MODE register is writable one time. This allows a user program to change
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.1.2 Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance
inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
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would need to be set before any attempt to write to an external location. If there are no writable resources
in the external system, PE2 can be left as a general purpose I/O pin. The
Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit in
PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not
needed in all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as
a constant speed clock for use in the external application system.
4.2.1.3 Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such
systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of
additional external memory devices.
Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility
is not available in this mode because the internal cycles would need to be split into two 8-bit cycles.
Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired
states during the single allowed write.
The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it
is possible to write the LSTRE bit in PEAR to “1” in this mode, the state of LSTRE is overridden and Port
E bit 3 cannot be reconfigured as the LSTRB output.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system
activity. Development systems where pipe status signals are monitored would typically use special
expanded wide mode or occasionally special expanded narrow mode.
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use
in external select decode logic or as a constant speed clock for use in the external application system.
The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be
reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded
narrow system includes external devices that can be written such as RAM, the RDWE bit would need to
be set before any attempt to write to an external location. If there are no writable resources in the external
system, PE2 can be left as a general purpose I/O pin.
4.2.1.4 Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or special narrow
mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is
enabled by setting the IVIS bit in the MODE register.
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If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal
visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the
LSTRB pins will remain at their previous state.
When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external.
During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and
address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their
previous state.
4.2.1.5 Emulation Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. These signals allow external memory and peripheral devices
to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of
application programs.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
4.2.1.6 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for
lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal
resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR,
PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external
words to addresses which are normally mapped external will be broken into two separate 8-bit accesses
using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only
visible externally as 16-bit information if IVIS=1.
Ports A and B are configured as multiplexed address and data output ports. During external accesses,
address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8
and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that
have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data
D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in special mode are restricted.
4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.
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4.2.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Instead the active
background mode is in control of CPU execution and BDM firmware is waiting for additional serial
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unless the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional
I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to
the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.
All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance
inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.2.2 Special Test Mode (Freescale Use Only)
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. In special test mode, the write protection of many control
bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.2.3 Test Operating Mode (Freescale Use Only)
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip
peripherals.
4.2.3.1 Peripheral Mode
This mode is intended for Freescale factory testing of the MCU. In this mode, the CPU is inactive and an
external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In
effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster
testing of on-chip memory and peripherals than previous testing methods. Since the mode control register
is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a
different mode. Background debugging should not be used while the MCU is in special peripheral mode
as internal bus conflicts between BDM and the external master can cause improper operation of both
functions.
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MC9S12H256 Device User Guide — V01.20
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
Protection of the contents of FLASH,
•
Protection of the contents of EEPROM,
•
Operation in single-chip mode,
•
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
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MC9S12H256 Device User Guide — V01.20
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop,
and Wait Mode.
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Reset and Interrupt Vector Table
Interrupt Source
CCR
Mask
Local Enable
HPRIO Value
to Elevate
$FFFE, $FFFF
External or Power On Reset
None
None
-
$FFFC, $FFFD
Clock Monitor fail reset
None
COPCTL (CME, FCME)
-
$FFFA, $FFFB
COP failure reset
None
COP rate select
-
Vector Address
$FFF8, $FFF9
Unimplemented instruction trap None
None
-
None
-
$FFF6, $FFF7
SWI
None
$FFF4, $FFF5
XIRQ
X-Bit
None
-
$FFF2, $FFF3
IRQ
I-Bit
INTCR (IRQEN)
$F2
$FFF0, $FFF1
Real Time Interrupt
I-Bit
RTICTL (RTIE)
$F0
$FFEE, $FFEF
Timer channel 0
I-Bit
TIE (C0I)
$EE
$FFEC, $FFED
Timer channel 1
I-Bit
TIE (C1I)
$EC
$FFEA, $FFEB
Timer channel 2
I-Bit
TIE (C2I)
$EA
$FFE8, $FFE9
Timer channel 3
I-Bit
TIE (C3I)
$E8
$FFE6, $FFE7
Timer channel 4
I-Bit
TIE (C4I)
$E6
$FFE4, $FFE5
Timer channel 5
I-Bit
TIE (C5I)
$E4
$FFE2, $FFE3
Timer channel 6
I-Bit
TIE (C6I)
$E2
$FFE0, $FFE1
Timer channel 7
I-Bit
TIE (C7I)
$E0
$FFDE, $FFDF
Timer overflow
I-Bit
TSCR2 (TOI)
$DE
$FFDC, $FFDD
Pulse accumulator A overflow
I-Bit
PACTL (PAOVI)
$DC
$FFDA, $FFDB
Pulse accumulator input edge
I-Bit
PACTL (PAI)
$DA
$FFD8, $FFD9
SPI
I-Bit
SPICR1 (SPIE)
$D8
$D6
$FFD6, $FFD7
SCI0
I-Bit
SC0CR2
(TIE, TCIE, RIE, ILIE)
$FFD4, $FFD5
SCI1
I-Bit
SC1CR2
(TIE, TCIE, RIE, ILIE)
$D4
$FFD2, $FFD3
ATD
I-Bit
ATDCTL2 (ASCIE)
$D2
$FFD0, $FFD1
Reserved
$FFCE, $FFCF
Port J
I-Bit
PTJIF (PTJIE)
$CE
$FFCC, $FFCD
Port H
I-Bit
PTHIF (PTHIE)
$CC
$FFCA, $FFCB
Reserved
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MC9S12H256 Device User Guide — V01.20
Table 5-1 Reset and Interrupt Vector Table
Vector Address
Interrupt Source
$FFC8, $FFC9
CCR
Mask
Local Enable
HPRIO Value
to Elevate
Reserved
$FFC6, $FFC7
CRG PLL lock
I-Bit
CRGINT (LOCKIE)
$C6
$FFC4, $FFC5
CRG Self Clock Mode
I-Bit
CRGINT (SCMIE)
$C4
$FFC2, $FFC3
Reserved
$FFC0, $FFC1
IIC Bus
I-Bit
IBCR (IBIE)
$C0
$FFBE, $FFBF
Reserved
$FFBC, $FFBD
Reserved
$FFBA, $FFBB
EEPROM
I-Bit
EECTL (CCIE, CBEIE)
$BA
$FFB8, $FFB9
FLASH
I-Bit
FCTL (CCIE, CBEIE)
$B8
$FFB6, $FFB7
CAN0 wake-up
I-Bit
CAN0RIER (WUPIE)
$B6
$B4
$B2
$FFB4, $FFB5
CAN0 errors
I-Bit
CAN0RIER (CSCIE,
OVRIE)
$FFB2, $FFB3
CAN0 receive
I-Bit
CAN0RIER (RXFIE)
$FFB0, $FFB1
CAN0 transmit
I-Bit
CAN0TIER (TXEIE[2:0])
$B0
$FFAE, $FFAF
CAN1 wake-up
I-Bit
CAN0RIER (WUPIE)
$AE
$FFAC, $FFAD
CAN1 errors
I-Bit
CAN1RIER (CSCIE,
OVRIE)
$AC
$FFAA, $FFAB
CAN1 receive
I-Bit
CAN1RIER (RXFIE)
$AA
$FFA8, $FFA9
CAN1 transmit
I-Bit
CAN1TIER (TXEIE[2:0])
$A8
$FF98 to
$FFA7
$FF96, $FF97
Reserved
Motor Control Timer Overflow
$FF9E to
$FF95
$FF8C, $FF8D
I-Bit
MCCTL1 (MCOCIE)
$96
Reserved
PWM Emergency Shutdown
$FF80 to
$FF8B
I-Bit
PWMSDN(PWMIE)
$8C
Reserved
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of
reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
NOTE:
80
For devices assembled in 112-pin LQFP packages all non-bonded out pins should
be configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 for affected pins.
MC9S12H256 Device User Guide — V01.20
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset
The RAM array is not automatically initialized out of reset.
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active high (see 2.3.10 PE7 / FP22 / XCLKS / NOACC — Port E I/O Pin 7).
Section 8 Timer (TIM) Block Description
Consult the TIM_16B8C Block User Guide for information about the Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter
module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the IIC Block User Guide for information about the Inter-IC Bus module.
Section 11 Serial Communications Interface (SCI) Block
Description
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MC9S12H256 Device User Guide — V01.20
There are two Serial Communications Interfaces (SCI0 and SCI1) implemented on the MC9S12H256
device and one SCI (SCI0) on MC9S12H128. Consult the SCI Block User Guide for information about
each Serial Communications Interface module.
Section 12 Serial Peripheral Interface (SPI) Block
Description
Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.
Section 13 Pulse Width Modulator (PWM) Block
Description
Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator module.
Section 14 Flash EEPROM 256K Block Description
Consult the FTS256K Block User Guide for information about the flash module.
Section 15 EEPROM 4K Block Description
Consult the EETS4K Block User Guide for information about the EEPROM module.
Section 16 RAM Block Description
The RAM module does not contain any control registers. Thus no Block User Guide is available.
This module supports single-cycle misaligned word accesses without wait states.
Section 17 Liquid Crystal Display Driver (LCD) Block
Description
Consult the LCD_32F4B Block User Guide for information about the Liquid Crystal Display Driver
module.
Section 18 MSCAN Block Description
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MC9S12H256 Device User Guide — V01.20
There are two MSCAN modules (CAN0 and CAN1) implemented on the MC9S12H256 device. Consult
the MSCAN Block User Guide for information on each MSCAN.
Section 19 PWM Motor Control (MC) Block Description
Consult the MC_10B12C Block User Guide for information about the PWM Motor Control module.
Section 20 Port Integration Module (PIM) Block Description
Consult the PIM_9H256 Block User Guide for information about the Port Integration Module.
Section 21 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
21.1 Device-specific information
21.1.1 VREGEN
There is no VREGEN pin implemented on this device.
21.1.2 Modes of Operation
21.1.2.1 Run Mode
VREG enters run mode whenever the CPU is neither in Stop nor in Pseudo Stop mode. Both regulating
loops operate in Run mode with full performance.
21.1.2.2 Standby Mode
VREG enters Standby mode when the CPU operates either in Stop or in Pseudo Stop mode. The supply of
the core logic as well as the oscillators are derived from two voltage clamps. Standby mode minimizes
quiescent current drawn by the voltage regulator block.
21.1.2.3 Shutdown Mode
VREG Shutdown mode is not available on MC9S12H family devices.
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MC9S12H256 Device User Guide — V01.20
21.2 Recommended PCB layout
Figure 21-1 LQFP112 recommended PCB layout
C8
VSSX1
VDDX1
VDDM1
C7
VSSM1
VSS1
C1
VDD1
VDDM2
C6
VSSM2
VDDA
VDDM3
C2
C5
VSSA
VSSM3
C3
C4
C11
C10
VDDX2
C14
C9
VDDR/
Q1
C13
C12
R1
86
VSSPLL
VDDPLL
MC9S12H256 Device User Guide — V01.20
Figure 21-2 LQFP144 recommended PCB layout
VSSX1
C8
VDDX1
VDDM1
C7
VSSM1
VSS1
C1
VDD1
VDDM2
C6
VSSM2
VDDA
VDDM3
C2
C5
VSSA
VSSM3
C3
C4
Q1
C13
C12
R1
C11
C10
VDDX2
C14
C9
VDDR/
VSSPLL
VDDPLL
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MC9S12H256 Device User Guide — V01.20
Table 21-1 Recommended Components
Component
Purpose
Type
Value
C1
VDD1 filter cap
ceramic X7R
100 .. 220nF
C2
VDDA filter cap
X7R/tantalum
>=100nF
C3
VDDX2 filter cap
X7R/tantalum
>=100nF
C4
VDDR filter cap
X7R/tantalum
>=100nF
C5
VDDM3 filter cap
X7R/tantalum
>=100nF
C6
VDDM2 filter cap
X7R/tantalum
>=100nF
C7
VDDM1 filter cap
X7R/tantalum
>=100nF
C8
VDDX1 filter cap
X7R/tantalum
>=100nF
C9
VDDPLL filter cap
ceramic X7R
100nF .. 220nF
C10
OSC load cap
C11
OSC load cap
C12
PLL loop filter cap
C13
PLL loop filter cap
C14
DC cutoff cap
R1
PLL loop filter res
Q1
Quartz/Resonator
See CRG Block User Guide
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible
to the corresponding pins(C1 – C9).
•
Central point of the ground star should be the VSS1 pin.
•
Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and
VSSM1,2,3.
•
VSSPLL must be directly connected to VSS1.
•
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10,
C11, C14 and Q1 as small as possible.
•
Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the
connection area to the MCU.
•
Central power input should be fed in at the VDDA/VSSA pins.
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MC9S12H256 Device User Guide — V01.20
Appendix A Electrical Characteristics
A.1 General
This supplement contains the most accurate electrical information for the MC9S12H256 and
MC9S12H128 microcontroller available at the time of publication.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE:
This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12H256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL
as well as the digital core.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
The VDDX1/VSSX1 and VDDX2/VSSX2 pairs supply the I/O pins except PH, PU, PV and PW. VDDR
supplies the internal voltage regulator.
VDDM1/VSSM1, VDDM2/VSSM2 and VDDM3/VSSM3 pairs supply the ports PH, PU, PV and PW.
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MC9S12H256 Device User Guide — V01.20
VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator
and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX1, VDDX2, VDDM as well as VSSA, VSSX1, VSSX2 and VSSM are connected by
anti-parallel diodes for ESD protection.
NOTE:
In the following context VDD5 is used for either VDDA, VDDM, VDDR and
VDDX1/2; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX1/2, VDDM
and VDDR pins.
VDD is used for VDD1 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDDPLL.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
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MC9S12H256 Device User Guide — V01.20
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1 Absolute Maximum Ratings1
Num
Rating
Symbol
Min
Max
Unit
1
I/O, Regulator and Analog Supply Voltage
VDD5
–0.3
6.0
V
2
Digital Logic Supply Voltage 2
VDD
–0.3
3.0
V
3
PLL Supply Voltage 2
VDDPLL
–0.3
3.0
V
4
Voltage difference VDDX1 to VDDX2 to VDDM and
VDDA
∆VDDX
–0.3
0.3
V
5
Voltage difference VSSX to VSSR and VSSA
∆VSSX
–0.3
0.3
V
6
Digital I/O Input Voltage
VIN
–0.3
6.0
V
7
Analog Reference
VRH, VRL
–0.3
6.0
V
8
XFC, EXTAL, XTAL inputs
VILV
–0.3
3.0
V
9
TEST input
VTEST
–0.3
10.0
V
10
Instantaneous Maximum Current
Single pin limit for all digital I/O pins except PU, PV
and PW 3
ID
–25
+25
mA
11
Instantaneous Maximum Current
Single pin limit for Port PU, PV and PW 4
I
D
–55
+55
mA
12
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL5
IDL
–25
+25
mA
13
Instantaneous Maximum Current
Single pin limit for TEST 6
IDT
–0.25
0
mA
14
Storage Temperature Range
T
– 65
155
°C
stg
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to VSSX1/2 and VDDX1/2, VSSM and VDDM or VSSA and VDDA.
4. Ports PU, PV, PW are internally clamped to VSSM and VDDM.
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MC9S12H256 Device User Guide — V01.20
5. Those pins are internally clamped to VSSPLL and VDDPLL.
6. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
positive
negative
–
–
3
3
Series Resistance
R1
0
Ω
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
–
–
3
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
Latch-up
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
92
Rating
Symbol
Min
Max
Unit
1
C Human Body Model (HBM)
VHBM
2000
–
V
2
C Machine Model (MM)
VMM
200
–
V
3
C Charge Device Model (CDM)
VCDM
500
–
V
4
Latch-up Current at TA = 125°C
C positive
negative
ILAT
+100
–100
–
mA
5
Latch-up Current at TA = 27°C
C positive
negative
ILAT
+200
–200
–
mA
MC9S12H256 Device User Guide — V01.20
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the
ambient temperature TA and the junction temperature TJ. For power dissipation
calculations refer to Section A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
Typ
Max
Unit
I/O, Regulator and Analog Supply Voltage
VDD5
4.5
5
5.25
V
Digital Logic Supply Voltage 1
VDD
2.35
2.5
2.75
V
PLL Supply Voltage 2
VDDPLL
2.35
2.5
2.75
V
Voltage Difference VDDX to VDDR and VDDA
∆VDDX
–0.1
0
0.1
V
Voltage Difference VSSX to VSSR and VSSA
∆VSSX
–0.1
0
0.1
V
Oscillator
fosc
0.5
–
16
MHz
Bus Frequency
fbus
0.5
–
16
MHz
TJ
–40
–
100
°C
T
A
–40
27
85
°C
Operating Junction Temperature Range
TJ
–40
–
120
°C
Operating Ambient Temperature Range 2
TA
–40
27
105
°C
T
J
–40
–
140
°C
TA
–40
27
125
°C
MC9S12H256C, MC9S12H128C
Operating Junction Temperature Range
Operating Ambient Temperature Range 2
MC9S12H256V, MC9S12H128V
MC9S12H256M, MC9S12H128M
Operating Junction Temperature Range
Operating Ambient Temperature Range 2
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
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MC9S12H256 Device User Guide — V01.20
T J = T A + ( P D • Θ JA )
T J = Junction Temperature, [°C ]
T A = Ambient Temperature, [°C ]
P D = Total Chip Power Dissipation, [W]
Θ JA = Package Thermal Resistance, [°C/W]
The total power dissipation can be calculated from:
P D = P INT + P IO
P INT = Chip Internal Power Dissipation, [W]
P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA
P IO =
∑ RDSON ⋅ IIOi
2
i
PIO is the sum of all output currents on I/O ports associated with VDDX1,2 and VDDM1,2,3.
Table A-5 Thermal Package Characteristics1
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
T Thermal Resistance LQFP112, single sided PCB2
θJA
–
–
54
oC/W
2
T
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
θJA
–
–
41
oC/W
3
T Thermal Resistance LQFP 144, single sided PCB
θJA
–
–
45
oC/W
4
T
θJA
–
–
37
oC/W
Thermal Resistance LQFP 144, double sided PCB
with 2 internal planes
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.
not all pins feature pull up/down resistances.
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MC9S12H256 Device User Guide — V01.20
95
MC9S12H256 Device User Guide — V01.20
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
0.65*VDD5
–
VDD5 + 0.3
V
VSS5 – 0.3
–
0.35*VDD5
V
1
P Input High Voltage
V
2
P Input Low Voltage
V
3
C Input Hysteresis
4
Input Leakage Current except PU, PV, PW (pins in
P high impedance input mode)1
Vin = VDD5 or VSS5
Iin
–1.0
–
1.0
µA
5
Input Leakage Current PU, PV, PW (pins in high
P impedance input mode)2
Vin = VDD5 or VSS5
Iin
–2.5
–
2.5
µA
VOH
VDD5 – 0.8
–
–
V
–
–
0.8
V
–
V
6
Output High Voltage (pins in output mode, except PU,
PV and PW)
P Partial Drive I
OH = –1.0mA
IH
IL
V
250
HYS
mV
Full Drive IOH = –10mA
7
Output Low Voltage (pins in output mode except PU,
PV and PW)
P Partial Drive I
OL = +1.0mA
V
OL
Full Drive IOL = +10mA
8
Output High Voltage (pins PU, PV and PW in output
P mode) I
OH = –20mA
V
9
Output Low Voltage (pins PU, PV and PW in output
P mode) I
OL = +20mA
V
10
Output Rise Time (pins PU, PV and PW in output
mode with slew control enabled) VDD5=5V,
P Rload=1KΩ, 10% to 90% of VOH
-40°C, EPP package
25°C, 140°C
11
12
Output Fall Time (pins PU, PV and PW in output
mode with slew control enabled) VDD5=5V,
P Rload=1KΩ, 10% to 90% of VOH
-40°C, EPP package
25°C, 140°C
0.32
V
60
60
1203
100
1803
130
ns
60
60
1203
100
1803
130
ns
tf
–
–130
µA
Internal Pull Up Device Current,
P tested at V Min.
IPUH
–10
–
–
µA
Internal Pull Down Device Current,
P tested at V Min.
IPDH
–
–
130
µA
Internal Pull Down Device Current,
P tested at V Max.
IPDL
10
–
–
µA
IL
96
.2
–
IH
15
tr
–
IPUL
IH
14
OL
VDD5 – 0.32 VDD5 – 0.2
Internal Pull Up Device Current,
P tested at V Max.
IL
13
OH
MC9S12H256 Device User Guide — V01.20
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
16
D Input Capacitance
Cin
17
Injection current4
T Single Pin limit
Total Device Limit. Sum of all injected currents
IICS
IICP
18
P Port H, J Interrupt Input Pulse filtered5
tPULSE
19
P Port H, J Interrupt Input Pulse passed5
tPULSE
–2.5
–25
10
6
–
pF
–
2.5
25
mA
3
µs
µs
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
3. This only applies to the EPP package, non-EPP packages retain the 100ns typ and 130ns max spec.
4. Refer to Section A.1.4 Current Injection, for more details
5. Parameter only applies in STOP or Pseudo STOP mode.
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 16MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
97
MC9S12H256 Device User Guide — V01.20
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Run supply currents
Single Chip, Internal regulator enabled
IDD5
65
IDDW
40
5
1
P
2
P
P
All modules enabled, PLL on
only RTI enabled 1
C
P
C
C
P
C
P
C
P
Pseudo Stop Current (RTI and COP disabled) 1, 2
–40°C
27°C
70°C
85°C
C Temp Option 100°C
105°C
V Temp Option 120°C
125°C
M Temp Option 140° C
C
C
C
C
C
C
C
Pseudo Stop Current (RTI and COP enabled) 1, 2
–40°C
27°C
70°C
85°C
105°C
125°C
140°C
Min
Typ
Max
Unit
mA
Wait Supply current
3
4
IDDPS
IDDPS
360
420
760
800
950
1000
1500
1700
2500
mA
520
2000
µA
3300
4800
420
480
820
860
1050
1700
2500
µA
Stop Current 2
5
C
P
C
C
P
C
P
C
P
–40°C
27°C
70°C
85°C
C Temp Option 100°C
105°C
V Temp Option 120°C
125°C
M Temp Option 140°C
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
98
IDDS
20
40
200
300
550
700
1200
1400
2200
100
1500
2900
4500
µA
MC9S12H256 Device User Guide — V01.20
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
VRL
VRH
VSSA
VDDA/2
VRH–VRL
4.50
fATDCLK
Typ
Max
Unit
VDDA/2
VDDA
V
V
5.25
V
0.5
2.0
MHz
14
7
28
14
Cycles
µs
12
6
26
13
Cycles
µs
Reference Potential
1
D
Low
High
2
C Differential Reference Voltage1
3
D ATD Clock Frequency
4
D
5.00
ATD 10-Bit Conversion Period
Clock Cycles2 NCONV10
Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10
ATD 8-Bit Conversion Period
Clock Cycles2
Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8
TCONV8
5
D
6
D Stop Recovery Time (VDDA=5.0 Volts)
tSR
20
µs
7
P Reference Supply current
IREF
0.375
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
A.2.2 Factors influencing accuracy
Three factors – source resistance, source capacitance and current injection – have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
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MC9S12H256 Device User Guide — V01.20
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS– CINN).
A.2.2.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
RS
–
–
1
KΩ
10
22
pF
2.5
mA
1
C Max input Source Resistance
2
Total Input Capacitance
T Non Sampling
Sampling
3
C Disruptive Analog Input Current
INA
4
C Coupling Ratio positive current injection
Kp
10–4
A/A
5
C Coupling Ratio negative current injection
Kn
10–2
A/A
100
CINN
CINS
–2.5
MC9S12H256 Device User Guide — V01.20
A.2.3 ATD accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input
capacitance and source resistance.
Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH – VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz
Num C
Rating
Symbol
Min
1
P 10-Bit Resolution
LSB
2
P 10-Bit Differential Nonlinearity
DNL
–1
3
P 10-Bit Integral Nonlinearity
INL
–2.5
4
P 10-Bit Absolute Error1
AE
–3
5
P 8-Bit Resolution
LSB
6
P 8-Bit Differential Nonlinearity
DNL
–0.5
7
P 8-Bit Integral Nonlinearity
INL
–1.0
8
P 8-Bit Absolute Error1
AE
–1.5
Typ
Max
5
Unit
mV
1
Counts
±1.5
2.5
Counts
±2.0
3
Counts
20
mV
0.5
Counts
±0.5
1.0
Counts
±1.0
1.5
Counts
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi – Vi – 1
DNL ( i ) = ------------------------ – 1
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
∑
i=1
Vn – V0
DNL ( i ) = -------------------- – n
1LSB
101
MC9S12H256 Device User Guide — V01.20
DNL
10-Bit Absolute Error Boundary
LSB
Vi–1
Vi
$3FF
8-Bit Absolute Error Boundary
$3FE
$3FD
$3FC
$FF
$3FB
$3FA
$3F9
$3F8
$FE
$3F7
$3F6
$3F4
8-Bit Resolution
10-Bit Resolution
$3F5
$FD
$3F3
9
Ideal Transfer Curve
8
2
7
10-Bit Transfer Curve
6
5
4
1
3
8-Bit Transfer Curve
2
1
0
5
10
15
20
25
30
35
40
45
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-1 ATD Accuracy Definitions
NOTE:
102
Figure A-1 shows only definitions, for specification values refer to Table A-10.
MC9S12H256 Device User Guide — V01.20
A.3 NVM, Flash and EEPROM
NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP.
The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1
1
t swpgm = 9 ⋅ --------------------- + 25 ⋅ ---------f NVMOP
f bus
A.3.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1
1
t bwpgm = 4 ⋅ --------------------- + 9 ⋅ ---------f NVMOP
f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 ⋅ t bwpgm
Burst programming is more than 2 times faster than single word programming.
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MC9S12H256 Device User Guide — V01.20
A.3.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
1
t era ≈ 4000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
1
t mass ≈ 20000 ⋅ --------------------f NVMOP
The setup time can be ignored for this operation.
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
32 1
MHz
1
D External Oscillator Clock
fNVMOSC
0.5
2
D Bus frequency for Programming or Erase Operations
fNVMBUS
1
3
D Operating Frequency
fNVMOP
150
200
kHz
4
P Single Word Programming Time
tswpgm
46 2
74.5 3
µs
5
D Flash Burst Programming consecutive word 4
tbwpgm
20.4 2
31 3
µs
6
D Flash Burst Programming Time for 32 Words 4
tbrpgm
678.4 2
1035.5 3
µs
7
P Sector Erase Time
tera
20 5
26.7 3
ms
8
P Mass Erase Time
tmass
100 5
133 3
ms
MHz
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency
fbus.
3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. urst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
104
MC9S12H256 Device User Guide — V01.20
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
1
C Flash/EEPROM (-40˚C to +125˚C)
2
C EEPROM (-40˚C to +125˚C)
Cycles
Data Retention
Lifetime
Unit
10
15
Years
10,000
5
Years
NOTE:
Flash cycling performance is 10 cycles at -40˚C to +125˚C. Data retention is
specified for 15 years.
NOTE:
EEPROM cycling performance is 10K cycles at -40˚C to 125˚C. Data retention is
specified for 5 years on words after cycling 10K times. However if only 10 cycles
are executed on a word the data retention is specified for 15 years.
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MC9S12H256 Device User Guide — V01.20
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MC9S12H256 Device User Guide — V01.20
A.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.4.1 Startup
Table A-13 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-13 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
2.07
V
1
T POR release level
VPORR
2
T POR assert level
VPORA
0.97
V
3
D Reset input pulse width, minimum input time
PWRSTL
2
tosc
4
D Startup from Reset
nRST
192
5
D Interrupt pulse width, IRQ edge-sensitive mode
PWIRQ
20
6
D Wait recovery startup time
tWRS
196
nosc
ns
14
tcyc
A.4.1.1 POR
The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
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MC9S12H256 Device User Guide — V01.20
A.4.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
A.4.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.
A.4.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is
asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA.
Table A-14 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
16
MHz
1
C Crystal oscillator range
fOSC
0.5
2
P Startup Current
iOSC
100
µA
3
D Oscillator start-up time from POR or STOP
nUPOSC
4100
cycOSC
4
C Oscillator start-up time
tUPOSC
5
D Clock Quality check time-out
tCQOUT
0.45
6
P Clock Monitor Failure Assert Frequency
fCMFA
50
7
P External square wave input frequency3
fEXT
0.5
8
D External square wave pulse width low
tEXTL
15
ns
9
D External square wave pulse width high
tEXTH
15
ns
10
D External square wave rise time
tEXTR
1
ns
11
D External square wave fall time
tEXTF
1
ns
12
D Input Capacitance EXTAL pin
CIN
9
pF
13
D Input Capacitance XTAL pin
CIN
13
pF
14
C
VDCBIAS
1.1
V
DC Operating Bias in Colpitts Configuration on
EXTAL Pin
NOTES:
1. fosc = 4MHz, C = 22pF.
2. Maximum value is for extreme cases using high Q, low frequency crystals
108
81
100
1002
ms
2.5
s
200
KHz
32
MHz
MC9S12H256 Device User Guide — V01.20
3. XCLKS =1 during reset
A.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL
Cs
Cp
R
fosc
1
refdv+1
fref
∆
Phase
VCO
KΦ
KV
fvco
Detector
fcmp
Loop Divider
1
synr+1
1
2
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table A-15.
The VCO Gain at the desired VCO output frequency is approximated by:
KV = K1 ⋅ e
( f 1 – f vco )
----------------------K 1 ⋅ 1V
The phase detector relationship is given by:
K Φ = i ch ⋅ K V
ich is the current in tracking mode.
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MC9S12H256 Device User Guide — V01.20
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f ref
f ref
1
f C < ------------------------------------------ ------ → f C < -------------- ;( ζ = 0.9 )
4 ⋅ 50
2⎞ 50
⎛
π⋅ ζ+ 1+ζ
⎝
⎠
And finally the frequency relationship is defined as
f VCO
n = ------------- = 2 ⋅ ( synr + 1 )
f ref
With the above inputs the resistance can be calculated as:
2 ⋅ π ⋅ n ⋅ fC
R = ----------------------------KΦ
The capacitance Cs can now be calculated as:
2
0.516
2⋅ζ
C s = ---------------------- ≈ --------------- ;( ζ = 0.9 )
π ⋅ fC ⋅ R fC ⋅ R
The capacitance Cp should be chosen in the range of:
C s ⁄ 20 ≤ C p ≤ C s ⁄ 10
The stabilization delays shown in Table A-15 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.4.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
110
MC9S12H256 Device User Guide — V01.20
1
0
2
3
N–1
N
tmin1
tnom
tmax1
tminN
tmaxN
Figure A-3 Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
t max ( N )
t min ( N ) ⎞
⎛
J ( N ) = max ⎜ 1 – --------------------- , 1 – --------------------- ⎟
N ⋅ t nom
N ⋅ t nom ⎠
⎝
For N < 100, the following equation is a good fit for the maximum jitter:
j1
J ( N ) = -------- + j 2
N
J(N)
1
5
10
20
N
Figure A-4 Maximum bus clock jitter approximation
111
MC9S12H256 Device User Guide — V01.20
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table A-15 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Self Clock Mode frequency
fSCM
1
5.5
MHz
2
D VCO locking range
fVCO
8
32
MHz
3
D
|∆trk|
3
4
%1
4
D Lock Detection
|∆Lock|
0
1.5
%1
5
D Un-Lock Detection
|∆unl|
0.5
2.5
%1
6
D
|∆unt|
6
8
%1
7
C PLLON Total Stabilization delay (Auto Mode) 2
tstab
0.5
ms
8
D PLLON Acquisition mode stabilization delay 2
tacq
0.3
ms
9
D PLLON Tracking mode stabilization delay 2
tal
0.2
ms
10
P Fitting parameter VCO loop gain3
K1
–120
11
D Fitting parameter VCO loop frequency
f1
75
12
P Charge pump current acquisition mode
| ich |
20
38.5
60
µA
13
P Charge pump current tracking mode
| ich |
2
3.5
6
µA
14
C Jitter fit parameter 12
j1
1.1
%
15
C Jitter fit parameter 22
j2
0.13
%
Lock Detector transition from Acquisition to Tracking
mode
Lock Detector transition from Tracking to Acquisition
mode
-224
MHz/V
MHz
NOTES:
1. % deviation from target frequency
2. fREF = 4MHz, fBUS = 16MHz equivalent fVCO = 32MHz: REFDV = #$03, SYNR = #$0F, Cs = 4.7nF, Cp = 470pF, Rs = 10KΩ.
3. K1 is measured with VXFC = 1.4V and VXFC = 1.7V @ VDD5 = 5.25V
112
MC9S12H256 Device User Guide — V01.20
A.5 MSCAN
Table A-16 MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
1
P MSCAN Wake-up dominant pulse filtered
tWUP
2
P MSCAN Wake-up dominant pulse pass
tWUP
Min
5
Typ
Max
Unit
2
µs
µs
113
MC9S12H256 Device User Guide — V01.20
114
MC9S12H256 Device User Guide — V01.20
A.6 SPI
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
SS1
(OUTPUT)
2
1
SCK
(CPOL = 0)
(OUTPUT)
4
4
12
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
9
MOSI
(OUTPUT)
3
11
BIT 6 . . . 1
LSB IN
9
MSB OUT2
BIT 6 . . . 1
10
LSB OUT
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5 SPI Master Timing (CPHA = 0)
115
MC9S12H256 Device User Guide — V01.20
SS1
(OUTPUT)
1
2
12
11
11
12
3
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
LSB IN
10
9
MOSI
(OUTPUT) PORT DATA
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA =1)
Table A-17 SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Operating Frequency
fop
DC
1/4
fbus
1
P SCK Period tsck = 1./fop
tsck
4
2048
tbus
2
D Enable Lead Time
tlead
1/2
—
tsck
3
D Enable Lag Time
tlag
1/2
4
D Clock (SCK) High or Low Time
twsck
tbus − 30
5
D Data Setup Time (Inputs)
tsu
25
ns
6
D Data Hold Time (Inputs)
thi
0
ns
9
D Data Valid (after SCK Edge)
tv
10
D Data Hold Time (Outputs)
tho
11
D Rise Time Inputs and Outputs
tr
25
ns
12
D Fall Time Inputs and Outputs
tf
25
ns
tsck
1024 tbus
25
0
ns
ns
ns
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-18.
116
MC9S12H256 Device User Guide — V01.20
A.6.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS
(INPUT)
1
12
11
11
12
3
SCK
(CPOL = 0)
(INPUT)
4
2
4
SCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
9
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB OUT
SLAVE
10
10
SLAVE LSB OUT
6
BIT 6 . . . 1
MSB IN
LSB IN
Figure A-7 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
2
12
11
11
12
SCK
(CPOL = 0)
(INPUT)
4
4
SCK
(CPOL = 1)
(INPUT)
SLAVE
7
MOSI
(INPUT)
8
10
9
MISO
(OUTPUT)
MSB OUT
5
BIT 6 . . . 1
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
Figure A-8 SPI Slave Timing (CPHA =1)
117
MC9S12H256 Device User Guide — V01.20
Table A-18 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Operating Frequency
fop
DC
1/4
fbus
1
P SCK Period tsck = 1./fop
tsck
4
2048
tbus
2
D Enable Lead Time
tlead
1
tcyc
3
D Enable Lag Time
tlag
1
tcyc
4
D Clock (SCK) High or Low Time
twsck
tcyc − 30
ns
5
D Data Setup Time (Inputs)
tsu
25
ns
6
D Data Hold Time (Inputs)
thi
25
ns
7
D Slave Access Time
ta
1
tcyc
8
D Slave MISO Disable Time
tdis
1
tcyc
9
D Data Valid (after SCK Edge)
tv
25
ns
10
D Data Hold Time (Outputs)
tho
11
D Rise Time Inputs and Outputs
tr
25
ns
12
D Fall Time Inputs and Outputs
tf
25
ns
118
0
ns
MC9S12H256 Device User Guide — V01.20
A.7 LCD_32F4B
Table A.7-19 LCD_32F4B Driver Electrical Characteristics
Characteristic
Symbol
Min.
Typ.
Max.
Unit
LCD Supply Voltage
LCD Output Impedance(BP[3:0],FP[31:0])
for outputs to charge to higher voltage level or to
GND 1
LCD Output Current (BP[3:0],FP[31:0])
for outputs to discharge to lower voltage level
except GND 2
VLCD
-0.25
-
VDDX + 0.25
V
ZBP/FP
-
-
5.0
kOhm
IBP/FP
50
-
-
uA
NOTES:
1. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
2. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
119
MC9S12H256 Device User Guide — V01.20
120
MC9S12H256 Device User Guide — V01.20
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values
shown on table Table A-20. All major bus signals are included in the diagram. While both a data write
and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
121
MC9S12H256 Device User Guide — V01.20
1, 2
3
4
ECLK
PE4
5
9
Addr/Data
(read)
PA, PB
6
16
15
7
data
8
14
13
data
addr
17
11
data
addr
data
12
Addr/Data
(write)
PA, PB
10
19
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
23
ECS
PK7
24
25
26
27
28
29
30
31
32
33
34
R/W
PE2
LSTRB
PE3
NOACC
PE7
35
36
IPIPO0
IPIPO1, PE6,5
Figure A-9 General External Bus Timing
122
MC9S12H256 Device User Guide — V01.20
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
Min
Typ
Max
Unit
fo
0
16.0
MHz
tcyc
62.5
ns
1
P Frequency of operation (E-clock)
2
P Cycle time
3
D Pulse width, E low
PWEL
30
ns
4
D Pulse width, E high1
PWEH
30
ns
5
D Address delay time
tAD
6
D Address valid time to E rise (PWEL–tAD)
tAV
22
ns
7
D Muxed address hold time
tMAH
2
ns
8
D Address hold to data valid
tAHDS
7
ns
9
D Data hold to address
tDHA
2
ns
10
D Read data setup time
tDSR
24
ns
11
D Read data hold time
tDHR
0
ns
12
D Write data delay time
tDDW
13
D Write data hold time
tDHW
2
ns
14
D Write data setup time1 (PWEH–tDDW)
tDSW
23
ns
15
D Address access time1 (tcyc–tAD–tDSR)
tACCA
30
ns
16
D E high access time1 (PWEH–tDSR)
tACCE
6
ns
17
D Non-multiplexed address delay time
tNAD
18
D Non-muxed address valid to E rise (PWEL–tNAD)
tNAV
26
ns
19
D Non-multiplexed address hold time
tNAH
2
ns
20
D Chip select delay time
tCSD
21
D Chip select access time1 (tcyc–tCSD–tDSR)
tACCS
tcyc/4 – 2
ns
22
D Chip select hold time
tCSH
2
ns
23
D Chip select negated time
tCSN
8
ns
24
D Read/write delay time
tRWD
25
D Read/write valid time to E rise (PWEL–tRWD)
tRWV
25
ns
26
D Read/write hold time
tRWH
2
ns
27
D Low strobe delay time
tLSD
28
D Low strobe valid time to E rise (PWEL–tLSD)
tLSV
25
ns
29
D Low strobe hold time
tLSH
2
ns
30
D NOACC strobe delay time
tNOD
31
D NOACC valid time to E rise (PWEL–tNOD)
tNOV
8
7
6
6 + tcyc/4
7
7
7
25
ns
ns
ns
ns
ns
ns
ns
ns
123
MC9S12H256 Device User Guide — V01.20
Table A-20 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF
Num C
Rating
Symbol
Min
32
D NOACC hold time
tNOH
2
33
D IPIPO[1:0] delay time
tP0D
2
34
D IPIPO[1:0] valid time to E rise (PWEL–tP0D)
tP0V
22
35
D IPIPO[1:0] delay time1 (PWEH–tP1V)
tP1D
2
36
D IPIPO[1:0] valid time to E fall
tP1V
22
Typ
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
124
Max
Unit
ns
7
ns
ns
25
ns
ns
MC9S12H256 Device User Guide — V01.20
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12H256 and MC9S12H128 packages.
125
MC9S12H256 Device User Guide — V01.20
B.2 112-pin LQFP package
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
108X
G
X
X=L, M OR N
VIEW Y
B
L
V
M
B1
28
57
29
F
D
56
0.13
N
S1
A
S
C2
VIEW AB
θ2
0.050
0.10 T
112X
SEATING
PLANE
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
E
(Y)
(Z)
VIEW AB
M
T L-M N
θ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--1.600
0.050
0.150
1.350
1.450
0.270
0.370
0.450
0.750
0.270
0.330
0.650 BSC
0.090
0.170
0.500 REF
0.325 BSC
0.100
0.200
0.100
0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090
0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure B-1 112-pin LQFP mechanical dimensions (case no. 987)
126
BASE
METAL
SECTION J1-J1
ROTATED 90 ° COUNTERCLOCKWISE
A1
C
AA
J
V1
MC9S12H256 Device User Guide — V01.20
B.3 144-pin LQFP package
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 36 TIPS
144
109
1
108
4X
J1
P
J1
L
M
CL
B
V
140X
B1
VIEW Y
36
VIEW Y
V1
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M, N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.
73
37
X
X=L, M OR N
G
72
N
A1
S1
A
S
VIEW AB
C
0.1 T
θ2
144X
SEATING
PLANE
θ2
T
PLATING
J
F
AA
C2
0.05
R2
θ
R1
D
0.08
M
0.25
BASE
METAL
GAGE PLANE
T L-M N
SECTION J1-J1
(ROTATED 90 ° )
144 PL
(K)
C1
E
(Y)
VIEW AB
(Z)
θ1
MILLIMETERS
DIM MIN MAX
A
20.00 BSC
A1
10.00 BSC
B
20.00 BSC
B1
10.00 BSC
C
1.40
1.60
C1
0.05
0.15
C2
1.35
1.45
D
0.17
0.27
E
0.45
0.75
F
0.17
0.23
G
0.50 BSC
J
0.09
0.20
K
0.50 REF
P
0.25 BSC
R1
0.13
0.20
R2
0.13
0.20
S
22.00 BSC
S1
11.00 BSC
V
22.00 BSC
V1
11.00 BSC
Y
0.25 REF
Z
1.00 REF
AA
0.09
0.16
θ
0°
θ1
0°
7°
θ2
11°
13 °
CASE 918-03
ISSUE C
Figure B-2 144-pin LQFP mechanical dimensions (case no. 918-03)
127
MC9S12H256 Device User Guide — V01.20
128
MC9S12H256 Device User Guide — V01.20
User Guide End Sheet
129
MC9S12H256 Device User Guide — V01.20
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