MC9S12P128
Reference Manual
Covers also MC9S12P-Family
MC9S12P96
MC9S12P64
MC9S12P32
S12
Microcontrollers
MC9S12P128RMV1
Rev. 1.13
23 April 2010
freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual.
Revision History
Date
Revision
Level
April 2008
1.07
PRELIMINARY
July 2008
1.08
Minor Corrections
Added typ. IDD values
December 2008
1.09
Completed Electricals
Minor Corrections
March 2009
1.10
Final Electricals
June 2009
1.11
Corrected section 1.11.3.4 Memory
Corrected 1.7.3.16 - 1.7.3.19 SPI pin description
Removed reference to MMCCTL1 register from Table 13-5
Removed item 4b from Table A-6 and A-7
Changed Version ID in Table 1-5 from $FF to $00
October 2009
1.12
Added Register Summary Appendix D
Updated FTMRC Blockguide . See Revision History Chapter 13
Updated CPMU Blockguide . See Revision History Chapter 7
April 2010
1.13
Updated S12PMMCV1 Blockguide. See Revision History Chapter 3
Updated S12CPMU Blockguide. See Revision History Chapter 7
Description
Chapter 1
Device Overview MC9S12P-Family . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2
Port Integration Module (S12PPIMV1) . . . . . . . . . . . . . . . . . . . 49
Chapter 3
Memory Map Control (S12PMMCV1). . . . . . . . . . . . . . . . . . . . 107
Chapter 4
Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 5
Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . 131
Chapter 6
S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . 155
Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU) 197
Chapter 8
251
Freescale’s Scalable Controller Area Network (S12MSCANV3).
Chapter 9
Analog-to-Digital Converter (ADC12B10C) . . . . . . . . . . . . . . 305
Chapter 10
Pulse-Width Modulator (PWM8B6CV1) Block Description . . 329
Chapter 11
Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 363
Chapter 12
Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 399
Chapter 13
128 KByte Flash Module (S12FTMRC128K1V1). . . . . . . . . . . 425
Chapter 14
Timer Module (TIM16B8CV2) Block Description . . . . . . . . . . 473
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Appendix B Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Appendix D Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . 545
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Chapter 1Device Overview MC9S12P-Family
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.1 MC9S12P Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2.2 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.1 S12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.4 Main External Oscillator (XOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.5 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.6 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.7 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.8 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.9 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.10 Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.11 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.13 Analog-to-Digital Converter Module (ATD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.14 On-Chip Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.15 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.16 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.7.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.7.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.9.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.9.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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1.14 S12CPMU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 2
Port Integration Module (S12PPIMV1)
2.1
2.2
2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.7 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.8 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.9 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.10 Ports A, B, E, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . 67
2.3.11 Ports A, B, E Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.12 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.13 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.15 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.16 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.17 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.18 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.19 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.3.20 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.3.21 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3.22 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3.23 Port T Routing Register (PTTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.24 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.25 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.26 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.3.27 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.3.28 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.3.29 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.30 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.31 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.32 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.33 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.3.34 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.35 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.36 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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2.5
2.3.37 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.38 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.39 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.40 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.41 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.42 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.43 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.3.44 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.3.45 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.3.46 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.3.47 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.3.48 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.3.49 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.3.50 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.3.51 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.3.52 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.53 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.54 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3.55 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3.56 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.3.57 Port AD Data Register (PT0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.3.58 Port AD Data Register (PT1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.3.59 Port AD Data Direction Register (DDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.3.60 Port AD Data Direction Register (DDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.3.61 Port AD Reduced Drive Register (RDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.3.62 Port AD Reduced Drive Register (RDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.3.63 Port AD Pull Up Enable Register (PER0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.3.64 Port AD Pull Up Enable Register (PER1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.3.65 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Chapter 3
Memory Map Control (S12PMMCV1)
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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3.2
3.3
3.4
3.5
3.6
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Implemented Memory in the System Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.5.1 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.5.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.6.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Chapter 4
Interrupt Module (S12SINTV1)
4.1
4.2
4.3
4.4
4.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Chapter 5
Background Debug Module (S12SBDMV1)
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 6
S12S Debug Module (S12SDBGV2)
6.1
6.2
6.3
6.4
6.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU)
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.3 S12CPMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.2.3 TEMPSENSE — temperature sensor output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.4 VDDR — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.5 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.6 VSS, VSSPLL— Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.7 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.8 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.4.3 Stop Mode using PLLCLK as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 240
7.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Chapter 8
Freescale’s Scalable Controller Area Network (S12MSCANV3)
8.1
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
8.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
8.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
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8.3
8.4
8.5
8.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
8.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
8.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
8.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
8.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
8.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
8.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
8.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Chapter 9
Analog-to-Digital Converter (ADC12B10C)
9.1
9.2
9.3
9.4
9.5
9.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
9.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
9.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Chapter 10
Pulse-Width Modulator (PWM8B6CV1) Block Description
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
10.2.1 PWM5 — Pulse Width Modulator Channel 5 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
10.2.2 PWM4 — Pulse Width Modulator Channel 4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
10.2.3 PWM3 — Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
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10.4
10.5
10.6
10.2.4 PWM2 — Pulse Width Modulator Channel 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10.2.5 PWM1 — Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10.2.6 PWM0 — Pulse Width Modulator Channel 0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
10.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
10.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Chapter 11
Serial Communication Interface (S12SCIV5)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
11.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
11.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
11.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
11.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
11.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
11.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
11.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
11.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
11.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
11.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
11.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Chapter 12
Serial Peripheral Interface (S12SPIV5)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
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12.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
12.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Chapter 13
128 KByte Flash Module (S12FTMRC128K1V1)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
13.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.4.3 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
13.4.4 Allowed Simultaneous P-Flash and D-Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . 455
13.4.5 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
13.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
13.4.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
13.4.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
13.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
13.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
13.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 471
13.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 472
13.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
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Chapter 14
Timer Module (TIM16B8CV2) Block Description
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
14.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
14.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 477
14.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 477
14.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 477
14.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 477
14.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 477
14.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 477
14.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 478
14.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 478
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
14.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
14.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
14.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
14.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
14.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
14.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
14.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
14.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
14.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
14.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Appendix A
Electrical Characteristics
A.1 General
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
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A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
A.4.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
A.4.2 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Electrical Characteristics for the Oscillator (OSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
A.11.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
A.11.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Appendix B
Ordering Information
Appendix C
Package Information
C.1 80 QFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
C.2 48 QFN Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
C.3 64 LQFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Appendix D
Detailed Register Address Map
D.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
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Chapter 1 Device Overview MC9S12P-Family
1.1
Introduction
The MC9S12P family is an optimized, automotive, 16-bit microcontroller product line focused on lowcost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit
microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS family. The
MC9S12P family is targeted at generic automotive applications requiring CAN or LIN/J2602
communication. Typical examples of these applications include body controllers, occupant detection, door
modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.
The MC9S12P family uses many of the same features found on the MC9S12XS family, including error
correction code (ECC) on flash memory, a separate data-flash module for diagnostic or data storage, a fast
analog-to-digital converter (ATD) and a frequency modulated phase locked loop (IPLL) that improves the
EMC performance.
The MC9S12P family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low
cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of
Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the MC9S12P family run
16-bit wide accesses without wait states for all peripherals and memories. The MC9S12P family is
available in 80-pin QFP, 64-pin LQFP, and 48-pin QFN package options and aims to maximize pin
compatibility with the MC9S12XS family. In addition to the I/O ports available in each module, further
I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.
1.2
Features
This section describes the key features of the MC9S12P family.
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Device Overview MC9S12P-Family
1.2.1
MC9S12P Family Comparison
Table 1 provides a summary of different members of the MC9S12P family and their proposed features.
This information is intended to provide an understanding of the range of functionality offered by this
microcontroller family.
Table 1. MC9S12P Family
Feature
MC9S12P32
MC9S12P64
CPU
MC9S12P96
MC9S12P128
96 Kbytes
128 Kbytes
CPU12-V1
Flash memory (ECC)
32 Kbytes
64 Kbytes
Data flash (ECC)
RAM
4 Kbytes
2 Kbytes
4 Kbytes
6 Kbytes
MSCAN
1
SCI
1
SPI
1
Timer
8 ch x 16-bit
PWM
6 ch x 8-bit
ADC
10 ch x 12-bit
Frequency modulated PLL
Yes
External oscillator
(4 – 16 MHz Pierce with
loop control)
Yes
Internal 1 MHz RC
oscillator
Yes
Supply voltage
3.15 V – 5.5 V
Static(1) – 32 MHz
Execution speed
Package
80 QFP, 64 LQFP, 48 QFN
1. P or D Flash erasing or programming requires a minimum bus frequency of 1MHz
1.2.2
Chip-Level Features
On-chip modules available within the family include the following features:
• S12 CPU core
• Up to 128 Kbyte on-chip flash with ECC
• 4 Kbyte data flash with ECC
• Up to 6 Kbyte on-chip SRAM
• Phase locked loop (IPLL) frequency multiplier with internal filter
• 4–16 MHz amplitude controlled Pierce oscillator
• 1 MHz internal RC oscillator
• Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture,
output compare, counter, and pulse accumulator functions
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Device Overview MC9S12P-Family
•
•
•
•
•
•
•
1.3
Pulse width modulation (PWM) module with 6 x 8-bit channels
10-channel, 12-bit resolution successive approximation analog-to-digital converter (ATD)
One serial peripheral interface (SPI) module
One serial communication interface (SCI) module supporting LIN communications
One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
Module Features
The following sections provide more details of the modules implemented on the MC9S12P family.
1.3.1
S12 16-Bit Central Processor Unit (CPU)
S12 CPU is a high-speed 16-bit processing unit:
• Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
• Includes many single-byte instructions. This allows much more efficient use of ROM space.
• Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
1.3.2
On-Chip Flash with ECC
On-chip flash memory on the MC9S12P features the following:
• Up to 128 Kbyte of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
• 4 Kbyte data flash space
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 256 bytes
— Automated program and erase algorithm
— User margin level setting for reads
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Device Overview MC9S12P-Family
1.3.3
•
1.3.4
•
1.3.5
•
1.3.6
•
1.3.7
•
•
•
•
•
•
On-Chip SRAM
Up to 6 Kbytes of general-purpose RAM
Main External Oscillator (XOSC)
Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal
— Current gain control on amplitude output
— Signal with low harmonic distortion
— Low power
— Good noise immunity
— Eliminates need for external current limiting resistor
— Transconductance sized for optimum start-up margin for typical crystals
Internal RC Oscillator (IRC)
Trimmable internal reference clock.
— Frequency: 1 MHz
— Trimmed accuracy over –40˚C to +125˚C ambient temperature range: ±1.5%
Internal Phase-Locked Loop (IPLL)
Phase-locked-loop clock frequency multiplier
— No external components required
— Reference divider and multiplier allow large variety of clock rates
— Automatic bandwidth control mode for low-jitter operation
— Automatic frequency lock detector
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
— Reference clock sources:
– External 4–16 MHz resonator/crystal (XOSC)
– Internal 1 MHz RC oscillator (IRC)
System Integrity Support
Power-on reset (POR)
System reset generation
Illegal address detection with reset
Low-voltage detection with interrupt or reset
Real time interrupt (RTI)
Computer operating properly (COP) watchdog
— Configurable as window COP for enhanced failure detection
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Device Overview MC9S12P-Family
•
— Initialized out of reset using option bits located in flash memory
Clock monitor supervising the correct function of the oscillator
1.3.8
•
•
•
Timer (TIM)
8 x 16-bit channels for input capture or output compare
16-bit free-running counter with 7-bit precision prescaler
1 x 16-bit pulse accumulator
1.3.9
•
Pulse Width Modulation Module (PWM)
6 channel x 8-bit or 3 channel x 16-bit pulse width modulator
— Programmable period and duty cycle per channel
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
1.3.10
•
•
•
•
•
•
•
•
•
1 Mbit per second, CAN 2.0 A, B software compatible
— Standard and extended data frames
— 0–8 bytes data length
— Programmable bit rate up to 1 Mbps
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization
Flexible identifier acceptance filter programmable as:
— 2 x 32-bit
— 4 x 16-bit
— 8 x 8-bit
Wakeup with integrated low pass filter option
Loop back for self test
Listen-only mode to monitor CAN bus
Bus-off recovery by software intervention or automatically
16-bit time stamp of transmitted/received messages
1.3.11
•
•
•
•
Controller Area Network Module (MSCAN)
Serial Communication Interface Module (SCI)
Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
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Device Overview MC9S12P-Family
•
•
•
•
Programmable character length
Programmable polarity for transmitter and receiver
Active edge receive wakeup
Break detect and transmit collision detect supporting LIN
1.3.12
•
•
•
•
•
•
Configurable 8- or 16-bit data size
Full-duplex or single-wire bidirectional
Double-buffered transmit and receive
Master or slave mode
MSB-first or LSB-first shifting
Serial clock phase and polarity options
1.3.13
•
•
On-Chip Voltage Regulator (VREG)
Linear voltage regulator with bandgap reference
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR) circuit
Low-voltage reset (LVR)
High temperature sensor
1.3.15
•
•
Analog-to-Digital Converter Module (ATD)
10-channel, 12-bit analog-to-digital converter
— 3 us single conversion time
— 8-/10-/12-bit resolution
— Left or right justified result data
— Internal oscillator for conversion in stop modes
— Wakeup from low power modes on analog comparison > or CompB_Addr)
In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons.
A single match condition on either of the comparators is recognized as valid. An aligned word access
which straddles the range boundary is valid only if the aligned address is outside the range.
Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an
unexpected range. In forced match mode the outside range match would typically be activated at any
interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or
lower range limit to $00000 respectively.
6.4.3
Match Modes (Forced or Tagged)
Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register
TAG bits select the match mode. The modes are described in the following sections.
6.4.3.1
Forced Match
When configured for forced matching, a comparator channel match can immediately initiate a transition
to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control
register for the current state determines the next state. Forced matches are typically generated 2-3 bus
cycles after the final matching address bus cycle, independent of comparator RWE/RW settings.
Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an
opcode address typically precedes a tagged match at the same address.
6.4.3.2
Tagged Match
If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding
DBGSR flags are set. For a comparator related taghit to occur, the DBG must first attach tags to
instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of
the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition.
6.4.3.3
Immediate Trigger
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into
the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the
session and issues a forced breakpoint request to the CPU.
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of
the current state of ARM.
6.4.3.4
Channel Priorities
In case of simultaneous matches the priority is resolved according to Table 6-36. The lower priority is
suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher
priority. The priorities described in Table 6-36 dictate that in the case of simultaneous matches, the match
pointing to final state has highest priority followed by the lower channel number (0,1,2).
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S12S Debug Module (S12SDBGV2)
Table 6-36. Channel Priorities
Priority
Source
Action
Highest
TRIG
Enter Final State
Channel pointing to Final State
Transition to next state as defined by state control registers
Match0 (force or tag hit)
Transition to next state as defined by state control registers
Match1 (force or tag hit)
Transition to next state as defined by state control registers
Match2 (force or tag hit)
Transition to next state as defined by state control registers
Lowest
6.4.4
State Sequence Control
ARM = 0
State 0
(Disarmed)
ARM = 1
State1
State2
ARM = 0
Session Complete
(Disarm)
Final State
State3
ARM = 0
Figure 6-24. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the
SSF[2:0] flags in DBGSR accordingly to indicate the current state.
Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of
comparator matches.
Independent of the state sequencer, each comparator channel can be individually configured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel
the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing
and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and
the debug module is disarmed.
6.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control
as defined by the TALIGN bit (see 6.3.2.3”). If the TSOURCE bit in DBGTCR is clear then the trace buffer
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S12S Debug Module (S12SDBGV2)
is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon
completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared,
returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end
of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it
returns automatically to state0 and the debug module is disarmed.
6.4.5
Trace Buffer Operation
The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information
in the RAM array in a circular buffer format. The system accesses the RAM array through a register
window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer
line is read, an internal pointer into the RAM increments so that the next read receives fresh information.
Data is stored in the format shown in Table 6-37 and Table 6-40. After each store the counter register
DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace
buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.
6.4.5.1
Trace Trigger Alignment
Using the TALIGN bit (see 6.3.2.3) it is possible to align the trigger with the end or the beginning of a
tracing session.
If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the
transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the
opcode of the trigger. Using end alignment or when the tracing is initiated by writing to the TRIG bit whilst
configured for begin alignment, tracing starts in the second cycle after the DBGC1 write cycle.
6.4.5.1.1
Storing with Begin Trigger Alignment
Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once
the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer.
If the trigger is at the address of the change-of-flow instruction the change of flow associated with the
trigger is stored in the Trace Buffer. Using begin alignment together with tagging, if the tagged instruction
is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
6.4.5.1.2
Storing with End Trigger Alignment
Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point
the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change
of flow instruction, the trigger event is not stored in the Trace Buffer. If all trace buffer lines have been
used before a trigger event occurrs then the trace continues at the first line, overwriting the oldest entries.
6.4.5.2
Trace Modes
Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register.
Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the
following subsections.
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6.4.5.2.1
Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses are stored.
COF addresses are defined as follows:
• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a
source/destination bit to indicate whether the stored address was a source address or destination address.
NOTE
When a COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets executed after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
MARK1
MARK2
LDX
JMP
NOP
#SUB_1
0,X
SUB_1
BRN
*
ADDR1
NOP
DBNE
A,PART5
IRQ_ISR
LDAB
STAB
RTI
#$F0
VAR_C1
; IRQ interrupt occurs during execution of this
;
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
The execution flow taking into account the IRQ is as follows
MARK1
IRQ_ISR
SUB_1
ADDR1
LDX
JMP
LDAB
STAB
RTI
BRN
NOP
DBNE
#SUB_1
0,X
#$F0
VAR_C1
;
;
;
*
A,PART5
;
;
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6.4.5.2.2
Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
DBG module writes this value into a background register. This prevents consecutive duplicate address
entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG
module is designed to help find.
6.4.5.2.3
Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode is intended to supply additional information on indexed, indirect addressing modes where storing
only the destination address would not provide all information required for a user to determine where the
code is in error. This mode also features information bit storage to the trace buffer, for each address byte
storage. The information bits indicate the size of access (word or byte) and the type of access (read or
write).
When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode
fetch cycle.
6.4.5.2.4
Compressed Pure PC Mode
In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are
stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is
achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte
boundary has been crossed, in which case the full PC is stored.
Each Trace Buffer row consists of 2 information bits and 18 PC address bits
NOTE:
When tracing is terminated using forced breakpoints, latency in breakpoint
generation means that opcodes following the opcode causing the breakpoint
can be stored to the trace buffer. The number of opcodes is dependent on
program flow. This can be avoided by using tagged breakpoints.
6.4.5.3
Trace Buffer Organization (Normal, Loop1, Detail modes)
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers
to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the
address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32.
In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on
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each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and
CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL)
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte1 and the byte at the higher address is stored to byte0.
Table 6-37. Trace Buffer Organization (Normal,Loop1,Detail modes)
Entry 1
Detail Mode
8-bits
8-bits
Field 2
Field 1
Field 0
CINF1,ADRH1
ADRM1
ADRL1
0
DATAH1
DATAL1
CINF2,ADRH2
ADRM2
ADRL2
0
DATAH2
DATAL2
Entry 1
PCH1
PCM1
PCL1
Entry 2
PCH2
PCM2
PCL2
Entry 2
Normal/Loop1
Modes
6.4.5.3.1
4-bits
Entry
Number
Mode
Information Bit Organization
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
Bit 3
Bit 2
CSZ
CRW
Bit 1
Bit 0
ADDR[17] ADDR[16]
Figure 6-25. Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 6-38. Field Descriptions
Bit
Description
3
CSZ
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
2
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
1
ADDR[17]
Address Bus bit 17— Corresponds to system address bus bit 17.
0
ADDR[16]
Address Bus bit 16— Corresponds to system address bus bit 16.
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Field2 Bits in Normal and Loop1 Modes
Bit 3
Bit 2
Bit 1
Bit 0
CSD
CVA
PC17
PC16
Figure 6-26. Information Bits PCH
Table 6-39. PCH Field Descriptions
Bit
Description
3
CSD
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
2
CVA
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
1
PC17
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
0
PC16
Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16.
6.4.5.4
Trace Buffer Organization (Compressed Pure PC mode)
Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode)
2-bits
Line
Number Field 3
Mode
Compressed
Pure PC Mode
6-bits
Field 2
6-bits
6-bits
Field 1
Field 0
Line 1
00
PC1 (Initial 18-bit PC Base Address)
Line 2
11
PC4
PC3
PC2
Line 3
01
0
0
PC5
Line 4
00
Line 5
10
Line 6
00
PC6 (New 18-bit PC Base Address)
0
PC8
PC7
PC9 (New 18-bit PC Base Address)
NOTE
Configured for end aligned triggering in compressed PurePC mode, then
after rollover it is possible that the oldest base address is overwritten. In this
case all entries between the pointer and the next base address have lost their
base address following rollover. For example in Table 6-40 if one line of
rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the
entries on Lines 2 and 3 have lost their base address. For reconstruction of
program flow the first base address following the pointer must be used, in
the example, Line 4. The pointer points to the oldest entry, Line 2.
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Field3 Bits in Compressed Pure PC Modes
Table 6-41. Compressed Pure PC Mode Field 3 Information Bit Encoding
INF1
INF0
TRACE BUFFER ROW CONTENT
0
0
Base PC address TB[17:0] contains a full PC[17:0] value
0
1
Trace Buffer[5:0] contain incremental PC relative to base address zero value
1
0
Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value
1
1
Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value
Each time that PC[17:6] differs from the previous base PC[17:6], then a new base address is stored. The
base address zero value is the lowest address in the 64 address range
The first line of the trace buffer always gets a base PC address, this applies also on rollover.
6.4.5.5
Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read provided the DBG module is not armed, is configured for
tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer
is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word
write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid lines can be determined. DBGCNT does not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no rollover has occurred, the pointer points to line0, otherwise
it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest
data entry may also contain newer data entries in fields 0 and 1. Thus if rollover is indicated by the TBF
bit, the line status must be decoded using the INF bits in field3 of that line. If both INF bits are clear then
the line contains only entries from before the last rollover.
If INF0=1 then field 0 contains post rollover data but fields 1 and 2 contain pre rollover data.
If INF1=1 then fields 0 and 1 contain post rollover data but field 2 contains pre rollover data.
The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables
an interrupted trace buffer read sequence to be easily restarted from the oldest data entry.
The least significant word of line is read out first. This corresponds to the fields 1 and 0 of Table 6-37. The
next word read returns field 2 in the least significant bits [3:0] and “0” for bits [15:4].
Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM
pointer occurs.
6.4.5.6
Trace Buffer Reset State
The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system
reset occur, the trace session information from immediately before the reset occurred can be read out and
the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current
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trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data even if a
reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set,
otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best
handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin
trigger alignment case means no information would be stored in the trace buffer.
The Trace Buffer contents and DBGCNT bits are undefined following a POR.
NOTE
An external pin RESET that occurs simultaneous to a trace buffer entry can,
in very seldom cases, lead to either that entry being corrupted or the first
entry of the session being corrupted. In such cases the other contents of the
trace buffer still contain valid tracing information. The case occurs when the
reset assertion coincides with the trace buffer entry clock edge.
6.4.6
Tagging
A tag follows program information as it advances through the instruction queue. When a tagged instruction
reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition.
Each comparator control register features a TAG bit, which controls whether the comparator match causes
a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is
enabled for tagged comparisons, the address stored in the comparator match address registers must be an
opcode address.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the
transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started.
Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when
the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is
generated immediately, before the tagged instruction is carried out.
R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected,
since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on
the type of access. Thus these bits are ignored if tagging is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
Tagging is disabled when the BDM becomes active.
6.4.7
Breakpoints
It is possible to generate breakpoints from channel transitions to final state or using software to write to
the TRIG bit in the DBGC1 register.
6.4.7.1
Breakpoints From Comparator Channels
Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for
tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the
instruction queue.
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If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session
has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion
of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are requested
immediately.
If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing
trigger alignment.
Table 6-42. Breakpoint Setup For CPU Breakpoints
BRK
TALIGN
DBGBRK
Breakpoint Alignment
0
0
0
Fill Trace Buffer until trigger then disarm (no breakpoints)
0
0
1
Fill Trace Buffer until trigger, then breakpoint request occurs
0
1
0
Start Trace Buffer at trigger (no breakpoints)
0
1
1
Start Trace Buffer at trigger
A breakpoint request occurs when Trace Buffer is full
1
x
1
Terminate tracing and generate breakpoint immediately on trigger
1
x
0
Terminate tracing immediately on trigger
6.4.7.2
Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the
TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the
tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace (see Table 6-42). If no tracing session is selected, breakpoints are
requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and
TRIG simultaneously.
6.4.7.3
Breakpoint Priorities
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an
effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is
followed by a subsequent comparator channel match, it has no effect, since tracing has already started.
If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is
activated by the BGND and the breakpoint to SWI is suppressed.
6.4.7.3.1
DBG Breakpoint Priorities And BDM Interfacing
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU
is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In
addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active,
the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide
with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed.
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Table 6-43. Breakpoint Mapping Summary
DBGBRK
BDM Bit
(DBGC1[4])
BDM
Enabled
BDM
Active
Breakpoint
Mapping
0
X
X
X
No Breakpoint
1
0
X
0
Breakpoint to SWI
X
X
1
1
No Breakpoint
1
1
0
X
Breakpoint to SWI
1
1
1
0
Breakpoint to BDM
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes
the BDM firmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the
monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than
SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated
breakpoint at the same address.
Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows
the BGND instruction is the first instruction executed when normal program execution resumes.
NOTE
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modification it returns to the
instruction whose tag generated the breakpoint. To avoid a repeated
breakpoint at the same location reconfigure the DBG module in the SWI
routine, if configured for an SWI breakpoint, or over the BDM interface by
executing a TRACE command before the GO to increment the program flow
past the tagged instruction.
6.5
6.5.1
Application Information
State Machine scenarios
Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2
respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only
in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR
register. Thus the existing encoding for SCRx[2:0] is not changed.
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6.5.2
Scenario 1
A trigger is generated if a given sequence of 3 code events is executed.
Figure 6-27. Scenario 1
SCR2=0010
SCR1=0011
State1
M1
SCR3=0111
M2
State2
State3
M0
Final State
Scenario 1 is possible with S12SDBGV1 SCR encoding
6.5.3
Scenario 2
A trigger is generated if a given sequence of 2 code events is executed.
Figure 6-28. Scenario 2a
SCR2=0101
SCR1=0011
State1
M1
M2
State2
Final State
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
Figure 6-29. Scenario 2b
SCR2=0101
SCR1=0111
State1
M01
M2
State2
Final State
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
Figure 6-30. Scenario 2c
SCR2=0011
SCR1=0010
State1
M2
State2
M0
Final State
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
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6.5.4
Scenario 3
A trigger is generated immediately when one of up to 3 given events occurs
Figure 6-31. Scenario 3
SCR1=0000
State1
M012
Final State
Scenario 3 is possible with S12SDBGV1 SCR encoding
6.5.5
Scenario 4
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
event B cause a trigger. Similarly 2 consecutive occurrences of event B without an intermediate event A
cause a trigger. This is possible by using CompA and CompC to match on the same address as shown.
Figure 6-32. Scenario 4a
SCR1=0100 State1
M1
SCR3=0001
State 3
M0
State2
M2
M0
M1
M1
SCR2=0011
Final State
This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2
comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
Figure 6-33. Scenario 4b (with 2 comparators)
SCR1=0110 State1
M2
SCR3=1110
State 3
M0
State2
M0
M01
M2
M2
SCR2=1100
M1 disabled in
range mode
Final State
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
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This however violates the S12SDBGV1 specification, which states that a match leading to final state
always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel
number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on
simultaneous taghits, taghits pointing to final state have highest priority. If no taghit points to final state
then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG
would break on a simultaneous M0/M2.
6.5.6
Scenario 5
Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C.
Figure 6-34. Scenario 5
SCR2=0110
SCR1=0011
State1
M1
State2
M0
Final State
M2
Scenario 5 is possible with the S12SDBGV1 SCR encoding
6.5.7
Scenario 6
Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is
not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The
change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible.
This is advantageous because range and data bus comparisons use channel0 only.
Figure 6-35. Scenario 6
SCR3=1010
SCR1=1001
State1
M0
State3
M0
Final State
M12
6.5.8
Scenario 7
Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run
in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the
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S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding
OR forks as shown in red this scenario is possible.
Figure 6-36. Scenario 7
M01
SCR2=1100
SCR1=1101
State1
M1
SCR3=1101
M2
State2
State3
M12
Final State
M0
M02
On simultaneous matches the lowest channel number has priority so with this configuration the forking
from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a
simultaneous match2/match1transitions to state2.
6.5.9
Scenario 8
Trigger when a routine/event at M2 follows either M1 or M0.
Figure 6-37. Scenario 8a
SCR2=0101
SCR1=0111
State1
M01
M2
State2
Final State
Trigger when an event M2 is followed by either event M0 or event M1
Figure 6-38. Scenario 8b
SCR2=0111
SCR1=0010
State1
M2
State2
M01
Final State
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding
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S12S Debug Module (S12SDBGV2)
6.5.10
Scenario 9
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed
again. This cannot be realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing
the SCR2 encoding as shown in red this scenario becomes possible.
Figure 6-39. Scenario 9
SCR2=1111
SCR1=0111
State1
M01
State2
M01
Final State
M2
6.5.11
Scenario 10
Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1.
As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one
or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger
is generated. Configuring CompA and CompC the same, it is possible to generate a breakpoint on the third
consecutive occurrence of event M0 without a reset M1.
Figure 6-40. Scenario 10a
M1
SCR1=0010
State1
M2
SCR2=0100
SCR3=0010
M2
State2
M0
State3
Final State
M1
Figure 6-41. Scenario 10b
M0
SCR2=0011
SCR1=0010
State1
M2
State2
SCR3=0000
M1
State3
Final State
M0
Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point
in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before
M1 then a trigger is generated.
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S12S Debug Module (S12SDBGV2)
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S12S Debug Module (S12SDBGV2)
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Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU)
Revision History
Version Revision Effective
Number
Date
Date
V01.00
16 Jan.07
16 Jan. 07
Author
Description of Changes
Initial release
V01.01
9 July 08
9 July 08
added IRCLK to Block Diagram
V01.02
7 Oct. 08
7 Oct. 08
clarified and detailed oscillator filter functionality
V01.03
11 Dec. 08 11 Dec. 08
added note, that startup time of external oscillator tUPOSC must be
considered, especially when entering Pseudo Stop Mode
V01.04
17 Jun. 09 17 Jun. 09
Modified reset phase descriptions to reference fVCORST instead of
fPLLRST and correct typo of RESET pin sample point from 64 to 256
cycles in section: Description of Reset Operation
V01.05
27 Apr. 10
Major rework fixing typos, figures and tables and improved
description of Adaptive Oscillator Filter.
7.1
27 Apr. 10
Introduction
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
• The Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source.
It is designed for optimal start-up margin with typical crystal oscillators.
• The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
• The Internal Reference Clock (IRC1M) provides a1MHz clock.
7.1.1
Features
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
• Supports crystals or resonators from 4MHz to 16MHz.
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S12 Clock, Reset and Power Management Unit (S12CPMU)
•
•
•
•
•
•
High noise immunity due to input hysteresis and spike filtering.
Low RF emissions with peak-to-peak swing limited dynamically
Transconductance (gm) sized for optimum start-up margin for typical crystals
Dynamic gain control eliminates the need for external current limiting resistor
Integrated resistor eliminates the need for external bias resistor.
Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power
The Voltage Regulator (IVREG) has the following features:
• Input voltage range from 3.13V to 5.5V
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR)
• Low-voltage reset (LVR)
The Phase Locked Loop (PLL) has the following features:
• highly accurate and phase locked frequency multiplier
• Configurable internal filter for best stability and lock time.
• Frequency modulation for defined jitter and reduced emission
• Automatic frequency lock detector
• Interrupt request on entry or exit from locked condition
• Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
• PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock
The Internal Reference Clock (IRC1M) has the following features:
• Trimmable in frequency
• Factory trimmed value for 1MHz in Flash Memory, can be overwritten by application if required
Other features of the S12CPMU include
• Clock monitor to detect loss of crystal
• Autonomous periodical interrupt (API)
• Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock
— PLLCLK divider to adjust system speed
• System Reset generation from the following possible sources:
— Power-on reset (POR)
— Low-voltage reset (LVR)
— Illegal address access
— COP time out
— Loss of oscillation (clock monitor fail)
— External pin RESET
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12CPMU.
7.1.2.1
Run Mode
The voltage regulator is in Full Performance Mode (FPM).
The Phase Locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
• PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-On Reset.
— The Bus Clock is based on the PLLCLK.
— After reset the PLL is configured for 64MHz VCOCLK operation
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 16MHz and Bus Clock is
8MHz.
The PLL can be re-configured for other bus frequencies.
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
• PLL Engaged External (PEE)
— The Bus Clock is based on the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if
necessary.
– Enable the external oscillator (OSCE bit)
• PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock (OSCCLK).
— This mode can be entered from default mode PEI by performing the following steps:
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0).
— The PLLCLK is still on to filter possible spikes of the external oscillator clock.
7.1.2.2
Wait Mode
For S12CPMU Wait Mode is the same as Run Mode.
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.1.2.3
Stop Mode
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Power Mode (RPM).
The API is available.
The Phase Locked Loop (PLL) is off.
The Internal Reference Clock (IRC1M) is off.
Core Clock, Bus Clock and BDM Clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full
Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1).
• Full Stop Mode (PSTP=0 or OSCE=0)
The external oscillator (OSCLCP) is disabled.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). After wake-up from Full Stop Mode COP and RTI are running on IRCCLK
(COPOSCSEL=0, RTIOSCSEL=0).
• Pseudo Stop Mode (PSTP=1 and OSCE=1)
The external oscillator (OSCLCP) continues torun. If the respective enable bits are set the COP and
RTI will continue to run.
The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged.
NOTE
When starting up the external oscillator (either by programming OSCE bit
to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software
must wait for a minimum time equivalent to the startup-time of the external
oscillator tUPOSC before entering Pseudo Stop Mode.
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.1.3
S12CPMU Block Diagram
Illegal Address Access
MMC
VDDR
VDD, VDDPLL, VDDF
(core supplies)
Low Voltage Detect VDDA
VSSPLL
VSS
VDDX
VSSX
LVIE Low Voltage Interrupt
LVDS
Low Voltage Detect VDDX
Voltage
Regulator
3.13 to 5.5V
VDDA
VSSA
ILAF
LVRF
Power-On Detect
S12CPMU
PORF
RESET
UPOSC
Loop
EXTAL Controlled
Pierce
Oscillator
XTAL (OSCLCP)
4MHz-16MHz REFDIV[3:0]
OSCBW
Reference
Divider
Internal
Reference
Clock
(IRC1M)
oscillator status Interrupt
OSCIE
UPOSC=0 sets PLLSEL bit
adaptive
spike
filter
IRCTRIM[9:0]
Power-On Reset
System Reset
Reset
Generator
monitor fail
Clock
Monitor
PSTP
COP time out
&
OSCCLK
CAN_OSCCLK
(to MSCAN)
OSCFILT[4:0]
PLLSEL
POSTDIV[4:0]
ECLK2X
(Core Clock)
Post
Divider
1,2,..,32
divide
by 4
PLLCLK
ECLK
divide
by 2 (Bus Clock)
IRCCLK
(to LCD)
OSCE
VCOFRQ[1:0]
divide
by 8
VCOCLK
Lock
detect
REFCLK
FBCLK
Phase
locked
Loop with
internal
Filter (PLL)
HTDS
HTIE
HT Interrupt
High
Temperature
Sense
REFFRQ[1:0]
LOCK
LOCKIE
Divide by
2*(SYNDIV+1)
BDM Clock
Bus Clock
RC
Osc.
ACLK
PLL Lock Interrupt
Autonomous
API_EXTCLK
Periodic
Interrupt (API)
SYNDIV[5:0]
APICLK
UPOSC
UPOSC=0 clears
IRCCLK
COPCLK COP
OSCCLK
COPOSCSEL
Watchdog
PCE
COP time out
to Reset
Generator
CPMUCOP
IRCCLK
RTICLK
OSCCLK
RTIOSCSEL
APIE
API Interrupt
RTIE
RTI Interrupt
Real Time
Interrupt (RTI)
PRE
CPMURTI
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S12 Clock, Reset and Power Management Unit (S12CPMU)
Figure 7-1. Block diagram of S12CPMU
Figure 7-2 shows a block diagram of the OSCLCP.
OSCCLK
Peak
Detector
Gain Control
VDDPLL = 1.8 V
VSSPLL
Rf
XTAL
EXTAL
Figure 7-2. OSCLCP Block Diagram
7.2
Signal Description
This section lists and describes the signals that connect off chip.
7.2.1
RESET
RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known
start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
7.2.2
EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal
oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL input frequency. If OSCE=0,
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S12 Clock, Reset and Power Management Unit (S12CPMU)
the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL pin is pulled
down by an internal resistor of approximately 700 kΩ.
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
Loop controlled circuit is not suited for overtone resonators and crystals.
7.2.3
TEMPSENSE — temperature sensor output voltage
Depending on the VSEL value either the voltage level generated by the temperature sensor or the VREG
bandgap voltage is driven to a special channel of the ATD Converter. See device level specification for
connectivity.
7.2.4
VDDR — Regulator Power Input Pin
VDDR is the power input of IVREG. All currents sourced into the regulator loads flow through this pin.
A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can
smooth ripple on VDDR.
7.2.5
VDDA, VSSA — Regulator Reference Supply Pins
VDDA/VSSA, which are relatively quiet, are used to supply the analog parts of the regulator. Internal
precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100
nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
7.2.6
VSS, VSSPLL— Ground Pins
VSS and VSSPLL must be grounded.
7.2.7
VDDX, VSSX— Pad Supply Pins
This supply domain is monitored by the Low Voltage Reset circuit.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can further
improve the quality of this supply.
7.2.8
API_EXTCLK — API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification
to which pin it connects.
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3
Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
7.3.1
Module Memory Map
The S12CPMU registers are shown in Figure 7-3.
Addres
s
Name
0x0034
CPMU
SYNR
0x0035
CPMU
REFDIV
W
0x0036
CPMU
POSTDIV
W
0x0037
CPMUFLG
0x0038
CPMUINT
0x0039 CPMUCLKS
0x003A
CPMUPLL
0x003B
CPMURTI
0x003C CPMUCOP
Bit 7
R
W
R
R
R
W
R
W
R
W
R
6
W
R
W
4
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
RTIF
PORF
LVRF
0
0
RTIE
PLLSEL
PSTP
0
0
RTDEC
RTR6
WCOP
RSBCK
3
2
1
Bit 0
SYNDIV[5:0]
0
W
R
5
0
REFDIV[3:0]
POSTDIV[4:0]
LOCKIF
LOCKIE
LOCK
ILAF
OSCIF
UPOSC
0
0
PRE
PCE
RTI
OSCSEL
COP
OSCSEL
0
0
0
0
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
0
FM1
FM0
RTR5
RTR4
RTR3
0
0
0
WRTMASK
OSCIE
0
0x003D
RESERVED R
CPMUTEST0 W
0
0
0
0
0
0
0
0
0x003E
RESERVED R
CPMUTEST1 W
0
0
0
0
0
0
0
0
0x003F
CPMU
ARMCOP
R
0
0
0
0
0
0
0
0
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x02F0
CPMU
HTCTL
R
0
0
W
HTIE
HTIF
0x02F1
CPMU
LVCTL
0
0
0
W
LVIE
LVIF
0x02F2
CPMU
APICTL
0
0
W
APIE
APIF
R
R
APICLK
VSEL
0
HTE
HTDS
0
0
LVDS
APIES
APIEA
APIFE
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
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Addres
s
Name
0x02F3 CPMUAPITR
0x02F4 CPMUAPIRH
0x02F5 CPMUAPIRL
0x02F6
R
W
R
W
R
W
RESERVED R
CPMUTEST3 W
0x02F7 CPMUHTTR
R
W
CPMU
IRCTRIMH
W
0x02F9
CPMU
IRCTRIML
W
0x02FA
CPMUOSC
0x02FC
6
5
4
3
2
APITR5
APITR4
APITR3
APITR2
APITR1
APITR0
APIR15
APIR14
APIR13
APIR12
APIR11
APIR7
APIR6
APIR5
APIR4
0
0
0
0
0
0
0
HTOE
R
0x02F8
0x02FB CPMUPROT
Bit 7
TCTRIM[3:0]
R
R
W
R
1
Bit 0
0
0
APIR10
APIR9
APIR8
APIR3
APIR2
APIR1
APIR0
0
0
0
0
HTTR3
HTTR2
HTTR1
HTTR0
0
0
IRCTRIM[9:8]
IRCTRIM[7:0]
0
OSCE
OSCBW
OSCFILT[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESERVED R
CPMUTEST2 W
PROT
0
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
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S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2
Register Descriptions
This section describes all the S12CPMU registers and their individual bits.
Address order is as listed in Figure 7-3.
7.3.2.1
S12CPMU Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
0x0034
7
6
5
4
3
2
1
0
1
1
1
R
VCOFRQ[1:0]
SYNDIV[5:0]
W
Reset
0
1
0
1
1
Figure 7-4. S12CPMU Synthesizer Register (CPMUSYNR)
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
If PLL has locked (LOCK=1)
f VCO = 2 × f REF × ( SYNDIV + 1 )
NOTE
fVCO must be within the specified VCO frequency lock range. Bus
frequency fbus must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 7-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufficient stability).
Table 7-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
VCOFRQ[1:0]
32MHz = PWMPERx
XX
1
Always High
>= PWMPERx
XX
0
Always Low
1. Counter = 0x0000 and does not count.
10.5
Resets
The reset state of each individual bit is listed within the register description section (see Section 10.3,
“Memory Map and Register Definition,” which details the registers and their bit-fields. All special
functions or modes which are initialized during or just following reset are described within this section.
• The 8-bit up/down counter is configured as an up counter out of reset.
• All the channels are disabled and all the counters don’t count.
10.6
Interrupts
The PWM8B6CV1 module has only one interrupt which is generated at the time of emergency shutdown,
if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag
PWMIF is set whenever the input level of the PWM5 channel changes while PWM5ENA=1 or when
PWMENA is being asserted while the level at PWM5 is active.
A description of the registers involved and affected due to this interrupt is explained in Section 10.3.2.15,
“PWM Shutdown Register (PWMSDN).”
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Chapter 11
Serial Communication Interface (S12SCIV5)
Table 11-1. Revision History
Version
Number
Revision
Date
05.01
04/16/2004
05.02
10/14/2005
05.03
12/25/2008
05.04
08/05/2009
11.1
Effective
Date
Author
Description of Changes
Update OR and PF flag description; Correct baud rate
tolerance in 4.7.5.1 and 4.7.5.2; Clean up classification and
NDA message banners
Correct alternative registers address;
Remove unavailable baud rate in Table1-16
remove redundancy comments in Figure1-2
fix typo, SCIBDL reset value be 0x04, not 0x00
Introduction
This block guide provides an overview of the serial communication interface (SCI) module.
The SCI allows asynchronous serial communications with peripheral devices and other CPUs.
11.1.1
Glossary
IR: InfraRed
IrDA: Infrared Design Associate
IRQ: Interrupt Request
LIN: Local Interconnect Network
LSB: Least Significant Bit
MSB: Most Significant Bit
NRZ: Non-Return-to-Zero
RZI: Return-to-Zero-Inverted
RXD: Receive Pin
SCI : Serial Communication Interface
TXD: Transmit Pin
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Serial Communication Interface (S12SCIV5)
11.1.2
Features
The SCI includes these distinctive features:
• Full-duplex or single-wire operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
• 13-bit baud rate selection
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable polarity for transmitter and receiver
• Programmable transmitter output parity
• Two receiver wakeup methods:
— Idle line wakeup
— Address mark wakeup
• Interrupt-driven operation with eight flags:
— Transmitter empty
— Transmission complete
— Receiver full
— Idle receiver input
— Receiver overrun
— Noise error
— Framing error
— Parity error
— Receive wakeup on active edge
— Transmit collision detect supporting LIN
— Break Detect supporting LIN
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
11.1.3
Modes of Operation
The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait
and stop modes.
• Run mode
• Wait mode
• Stop mode
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Serial Communication Interface (S12SCIV5)
11.1.4
Block Diagram
Figure 11-1 is a high level block diagram of the SCI module, showing the interaction of various function
blocks.
SCI Data Register
RXD Data In
Infrared
Decoder
Receive Shift Register
Receive & Wakeup
Control
Bus Clock
Baud Rate
Generator
IDLE
Receive
RDRF/OR
Interrupt
Generation BRKD
RXEDG
BERR
Data Format Control
Transmit Control
1/16
Transmit Shift Register
SCI
Interrupt
Request
Transmit
TDRE
Interrupt
Generation TC
Infrared
Encoder
Data Out TXD
SCI Data Register
Figure 11-1. SCI Block Diagram
11.2
External Signal Description
The SCI module has a total of two external pins.
11.2.1
TXD — Transmit Pin
The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high
impedance anytime the transmitter is disabled.
11.2.2
RXD — Receive Pin
The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is
ignored when the receiver is disabled and should be terminated to a known voltage.
11.3
Memory Map and Register Definition
This section provides a detailed description of all the SCI registers.
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Serial Communication Interface (S12SCIV5)
11.3.1
Module Memory Map and Register Definition
The memory map for the SCI module is given below in Figure 11-2. The address listed for each register is
the address offset. The total address for each register is the sum of the base address for the SCI module and
the address offset for each register.
11.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
0x0000
SCIBDH1
0x0001
SCIBDL1
0x0002
SCICR11
0x0000
SCIASR12
0x0001
SCIACR12
R
W
R
W
R
W
R
W
R
W
0x0002
SCIACR22
W
0x0003
SCICR2
W
0x0004
SCISR1
0x0005
SCISR2
R
R
R
Bit 7
6
5
4
3
2
1
Bit 0
IREN
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0
0
0
0
BERRV
BERRIF
BKDIF
0
0
0
0
BERRIE
BKDIE
0
0
0
0
0
BERRM1
BERRM0
BKDFE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0
0
TXPOL
RXPOL
BRK13
TXDIR
RXEDGIF
RXEDGIE
0
W
R
W
AMAP
RAF
= Unimplemented or Reserved
Figure 11-2. SCI Register Summary (Sheet 1 of 2)
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Freescale Semiconductor
Serial Communication Interface (S12SCIV5)
Register
Name
Bit 7
R
6
R8
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0x0006
SCIDRH
W
0x0007
SCIDRL
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
T8
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
= Unimplemented or Reserved
Figure 11-2. SCI Register Summary (Sheet 2 of 2)
11.3.2.1
SCI Baud Rate Registers (SCIBDH, SCIBDL)
Module Base + 0x0000
R
W
Reset
7
6
5
4
3
2
1
0
IREN
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
0
0
0
Figure 11-3. SCI Baud Rate Register (SCIBDH)
Module Base + 0x0001
R
W
Reset
7
6
5
4
3
2
1
0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
Figure 11-4. SCI Baud Rate Register (SCIBDL)
Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until
SCIBDL is written to as well, following a write to SCIBDH.
Write: Anytime, if AMAP = 0.
NOTE
Those two registers are only visible in the memory map if AMAP = 0 (reset
condition).
The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared
modulation/demodulation submodule.
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Serial Communication Interface (S12SCIV5)
Table 11-2. SCIBDH and SCIBDL Field Descriptions
Field
7
IREN
Description
Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.
0 IR disabled
1 IR enabled
6:5
TNP[1:0]
Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow
pulse. See Table 11-3.
4:0
7:0
SBR[12:0]
SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is
calculated two different ways depending on the state of the IREN bit.
The formulas for calculating the baud rate are:
When IREN = 0 then,
SCI baud rate = SCI bus clock / (16 x SBR[12:0])
When IREN = 1 then,
SCI baud rate = SCI bus clock / (32 x SBR[12:1])
Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the
first time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and
IREN = 1).
Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in
a temporary location until SCIBDL is written to.
Table 11-3. IRSCI Transmit Pulse Width
TNP[1:0]
11.3.2.2
Narrow Pulse Width
11
1/4
10
1/32
01
1/16
00
3/16
SCI Control Register 1 (SCICR1)
Module Base + 0x0002
R
W
Reset
7
6
5
4
3
2
1
0
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0
0
0
0
0
0
0
0
Figure 11-5. SCI Control Register 1 (SCICR1)
Read: Anytime, if AMAP = 0.
Write: Anytime, if AMAP = 0.
NOTE
This register is only visible in the memory map if AMAP = 0 (reset
condition).
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Serial Communication Interface (S12SCIV5)
Table 11-4. SCICR1 Field Descriptions
Field
Description
7
LOOPS
Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI
and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must
be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit.
6
SCISWAI
5
RSRC
4
M
SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
0 SCI enabled in wait mode
1 SCI disabled in wait mode
Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register
input. See Table 11-5.
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.
0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
3
WAKE
Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the
most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
2
ILT
Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
0 Idle character bit count begins after start bit
1 Idle character bit count begins after stop bit
1
PE
Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the
most significant bit position.
0 Parity function disabled
1 Parity function enabled
0
PT
Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even
parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.
1 Even parity
1 Odd parity
Table 11-5. Loop Functions
LOOPS
RSRC
Function
0
x
Normal operation
1
0
Loop mode with transmitter output internally connected to receiver input
1
1
Single-wire mode with TXD pin connected to receiver input
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Serial Communication Interface (S12SCIV5)
11.3.2.3
SCI Alternative Status Register 1 (SCIASR1)
Module Base + 0x0000
7
R
W
Reset
RXEDGIF
0
6
5
4
3
2
0
0
0
0
BERRV
0
0
0
0
0
1
0
BERRIF
BKDIF
0
0
= Unimplemented or Reserved
Figure 11-6. SCI Alternative Status Register 1 (SCIASR1)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 11-6. SCIASR1 Field Descriptions
Field
7
RXEDGIF
Description
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active receive on the receive input has occurred
1 An active edge on the receive input has occurred
2
BERRV
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
1
BERRIF
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
0
BKDIF
11.3.2.4
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
SCI Alternative Control Register 1 (SCIACR1)
Module Base + 0x0001
7
R
W
Reset
RXEDGIE
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
1
0
BERRIE
BKDIE
0
0
= Unimplemented or Reserved
Figure 11-7. SCI Alternative Control Register 1 (SCIACR1)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
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Freescale Semiconductor
Serial Communication Interface (S12SCIV5)
Table 11-7. SCIACR1 Field Descriptions
Field
Description
7
RSEDGIE
Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
1
BERRIE
0
BKDIE
11.3.2.5
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
SCI Alternative Control Register 2 (SCIACR2)
Module Base + 0x0002
R
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
W
Reset
2
1
0
BERRM1
BERRM0
BKDFE
0
0
0
= Unimplemented or Reserved
Figure 11-8. SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 11-8. SCIACR2 Field Descriptions
Field
Description
2:1
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 11-9.
BERRM[1:0]
0
BKDFE
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
Table 11-9. Bit Error Mode Coding
BERRM1
BERRM0
Function
0
0
Bit error detect circuit is disabled
0
1
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to Figure 11-19)
1
0
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to Figure 11-19)
1
1
Reserved
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Serial Communication Interface (S12SCIV5)
11.3.2.6
SCI Control Register 2 (SCICR2)
Module Base + 0x0003
R
W
Reset
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Figure 11-9. SCI Control Register 2 (SCICR2)
Read: Anytime
Write: Anytime
Table 11-10. SCICR2 Field Descriptions
Field
7
TIE
Description
Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
6
TCIE
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
5
RIE
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
4
ILIE
Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
3
TE
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
2
RE
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
1
RWU
Receiver Wakeup Bit — Standby state
0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes
the receiver by automatically clearing RWU.
0
SBK
Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s
if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As
long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13
or 14 bits).
0 No break characters
1 Transmit break characters
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11.3.2.7
SCI Status Register 1 (SCISR1)
The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also,
these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures
require that the status register be read followed by a read or write to the SCI data register.It is permissible
to execute other instructions between the two steps as long as it does not compromise the handling of I/O,
but the order of operations is important for flag clearing.
Module Base + 0x0004
R
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
0
0
0
0
0
0
W
Reset
1
= Unimplemented or Reserved
Figure 11-10. SCI Status Register 1 (SCISR1)
Read: Anytime
Write: Has no meaning or effect
Table 11-11. SCISR1 Field Descriptions
Field
Description
7
TDRE
Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the
SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value
to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data
register low (SCIDRL).
0 No byte transferred to transmit shift register
1 Byte transferred to transmit shift register; transmit data register empty
6
TC
Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break
character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being
transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1
(SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data,
preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of
the TC flag (transmission not complete).
0 Transmission in progress
1 No transmission in progress
5
RDRF
Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI
data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data
register low (SCIDRL).
0 Data not available in SCI data register
1 Received data available in SCI data register
4
IDLE
Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear
on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle
condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then
reading SCI data register low (SCIDRL).
0 Receiver input is either active now or has never become active since the IDLE flag was last cleared
1 Receiver input has become idle
Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag.
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Serial Communication Interface (S12SCIV5)
Table 11-11. SCISR1 Field Descriptions (continued)
Field
Description
3
OR
Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register
receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the
second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low
(SCIDRL).
0 No overrun
1 Overrun
Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of
events occurs:
1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear);
2. Receive second frame without reading the first frame in the data register (the second frame is not
received and OR flag is set);
3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register);
4. Read status register SCISR1 (returns RDRF clear and OR set).
Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy
SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received.
2
NF
Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as
the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1),
and then reading SCI data register low (SCIDRL).
0 No noise
1 Noise
1
FE
Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle
as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is
cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register
low (SCIDRL).
0 No framing error
1 Framing error
0
PF
Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not
match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
0 No parity error
1 Parity error
11.3.2.8
SCI Status Register 2 (SCISR2)
Module Base + 0x0005
7
R
W
Reset
AMAP
0
6
5
0
0
0
0
4
3
2
1
TXPOL
RXPOL
BRK13
TXDIR
0
0
0
0
0
RAF
0
= Unimplemented or Reserved
Figure 11-11. SCI Status Register 2 (SCISR2)
Read: Anytime
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Serial Communication Interface (S12SCIV5)
Write: Anytime
Table 11-12. SCISR2 Field Descriptions
Field
Description
7
AMAP
Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset
condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and
status registers and hides the baud rate and SCI control Register 1.
0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible
1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible
4
TXPOL
Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by
a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
3
RXPOL
Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a
mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
2
BRK13
Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit
respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.
0 Break character is 10 or 11 bit long
1 Break character is 13 or 14 bit long
1
TXDIR
Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to
be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire
mode of operation.
0 TXD pin to be used as an input in single-wire mode
1 TXD pin to be used as an output in single-wire mode
0
RAF
Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start
bit search. RAF is cleared when the receiver detects an idle character.
0 No reception in progress
1 Reception in progress
11.3.2.9
SCI Data Registers (SCIDRH, SCIDRL)
Module Base + 0x0006
7
R
6
R8
T8
W
Reset
0
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-12. SCI Data Registers (SCIDRH)
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Serial Communication Interface (S12SCIV5)
Module Base + 0x0007
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
0
0
0
0
0
0
0
0
Reset
Figure 11-13. SCI Data Registers (SCIDRL)
Read: Anytime; reading accesses SCI receive data register
Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Table 11-13. SCIDRH and SCIDRL Field Descriptions
Field
Description
SCIDRH
7
R8
Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
SCIDRH
6
T8
Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
SCIDRL
7:0
R[7:0]
T[7:0]
R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats
T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
NOTE
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to SCI data register high (SCIDRH), then SCIDRL.
11.4
Functional Description
This section provides a complete functional description of the SCI block, detailing the operation of the
design from the end user perspective in a number of subsections.
Figure 11-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial
communication between the CPU and remote devices, including other CPUs. The SCI transmitter and
receiver operate independently, although they use the same baud rate generator. The CPU monitors the
status of the SCI, writes the data to be transmitted, and processes received data.
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Serial Communication Interface (S12SCIV5)
R8
IREN
SCI Data
Register
NF
FE
Ir_RXD
Bus
Clock
Receive
Shift Register
SCRXD
Receive
and Wakeup
Control
PF
RAF
RE
IDLE
RWU
RDRF
LOOPS
OR
RSRC
M
Baud Rate
Generator
IDLE
ILIE
RDRF/OR
Infrared
Receive
Decoder
R16XCLK
RXD
RIE
TIE
WAKE
Data Format
Control
ILT
PE
SBR12:SBR0
TDRE
TDRE
TC
SCI
Interrupt
Request
PT
TC
TCIE
TE
÷16
Transmit
Control
LOOPS
SBK
RSRC
T8
Transmit
Shift Register
RXEDGIE
Active Edge
Detect
RXEDGIF
BKDIF
RXD
SCI Data
Register
Break Detect
BKDFE
SCTXD
BKDIE
LIN Transmit BERRIF
Collision
Detect
BERRIE
R16XCLK
Infrared
Transmit
Encoder
BERRM[1:0]
Ir_TXD
TXD
R32XCLK
TNP[1:0]
IREN
Figure 11-14. Detailed SCI Block Diagram
11.4.1
Infrared Interface Submodule
This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow
pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer
specification defines a half-duplex infrared communication link for exchange data. The full standard
includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2
Kbits/s.
The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The
SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse
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Serial Communication Interface (S12SCIV5)
for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be
detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external
from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit
stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be
inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low
pulses.
The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in
the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during
transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK,
which are configured to generate the narrow pulse width during transmission. The R16XCLK and
R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both
R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the
R16XCLK clock.
11.4.1.1
Infrared Transmit Encoder
The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A
narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle
of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a
zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.
11.4.1.2
Infrared Receive Decoder
The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is
expected for each zero received and no pulse is expected for each one received. A narrow high pulse is
expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when
RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared
physical layer specification.
11.4.2
LIN Support
This module provides some basic support for the LIN protocol. At first this is a break detect circuitry
making it easier for the LIN software to distinguish a break character from an incoming data stream. As a
further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.
11.4.3
Data Format
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data
format where zeroes are represented by light pulses and ones remain low. See Figure 11-15 below.
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Serial Communication Interface (S12SCIV5)
8-Bit Data Format
(Bit M in SCICR1 Clear)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Possible
Parity
Bit
Bit 6
STOP
Bit
Bit 7
Next
Start
Bit
Standard
SCI Data
Infrared
SCI Data
9-Bit Data Format
(Bit M in SCICR1 Set)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
POSSIBLE
PARITY
Bit
Bit 6
Bit 7
Bit 8
STOP
Bit
NEXT
START
Bit
Standard
SCI Data
Infrared
SCI Data
Figure 11-15. SCI Data Formats
Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit.
Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight
data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame
with nine data bits has a total of 11 bits.
Table 11-14. Example of 8-Bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
1
8
0
0
1
1
7
0
1
1
(1)
0
1
1
7
1
1. The address bit identifies the frame as an address
character. See Section 11.4.6.6, “Receiver Wakeup”.
When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register
high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it.
A frame with nine data bits has a total of 11 bits.
Table 11-15. Example of 9-Bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
1
9
0
0
1
1
8
0
1
1
(1)
0
1
1
8
1
1. The address bit identifies the frame as an address
character. See Section 11.4.6.6, “Receiver Wakeup”.
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Serial Communication Interface (S12SCIV5)
11.4.4
Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is
synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
• Integer division of the bus clock may not give the exact target frequency.
Table 11-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.
When IREN = 0 then,
SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])
Table 11-16. Baud Rates (Example: Bus Clock = 25 MHz)
Bits
SBR[12:0]
Receiver
Clock (Hz)
Transmitter
Clock (Hz)
Target
Baud Rate
Error
(%)
41
609,756.1
38,109.8
38,400
.76
81
308,642.0
19,290.1
19,200
.47
163
153,374.2
9585.9
9,600
.16
326
76,687.1
4792.9
4,800
.15
651
38,402.5
2400.2
2,400
.01
1302
19,201.2
1200.1
1,200
.01
2604
9600.6
600.0
600
.00
5208
4800.0
300.0
300
.00
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Freescale Semiconductor
Serial Communication Interface (S12SCIV5)
11.4.5
Transmitter
Internal Bus
Bus
Clock
÷ 16
Baud Divider
SCI Data Registers
11-Bit Transmit Register
H
8
7
6
5
4
3
2
1
0
TXPOL
SCTXD
L
MSB
M
Start
Stop
SBR12:SBR0
LOOP
CONTROL
TIE
TDRE IRQ
Break (All 0s)
Parity
Generation
Preamble (All 1s)
PT
Shift Enable
PE
Load from SCIDR
T8
To Receiver
LOOPS
RSRC
TDRE
Transmitter Control
TC
TC IRQ
TCIE
TE
BERRIF
BER IRQ
TCIE
SBK
BERRM[1:0]
Transmit
Collision Detect
SCTXD
SCRXD
(From Receiver)
Figure 11-16. Transmitter Block Diagram
11.4.5.1
Transmitter Character Length
The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8
in SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.5.2
Character Transmission
To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn
are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through
the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data
registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit
shift register.
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Serial Communication Interface (S12SCIV5)
The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the
buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by
writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting
out the first byte.
To initiate an SCI transmission:
1. Configure the SCI:
a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud
rate generator. Remember that the baud rate generator is disabled when the baud rate is zero.
Writing to the SCIBDH has no effect without also writing to SCIBDL.
b) Write to SCICR1 to configure word length, parity, and other configuration bits
(LOOPS,RSRC,M,WAKE,ILT,PE,PT).
c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2
register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now
be shifted out of the transmitter shift register.
2. Transmit Procedure for each byte:
a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind
that the TDRE bit resets to one.
b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is
written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not
result until the TDRE flag has been cleared.
3. Repeat step 2 for each subsequent transmission.
NOTE
The TDRE flag is set when the shift register is loaded with the next data to
be transmitted from SCIDRH/L, which happens, generally speaking, a little
over half-way through the stop bit of the previous frame. Specifically, this
transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the
previous frame.
Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic
1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from
the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data
character is the parity bit.
The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI
data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data
register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI
control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.
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Serial Communication Interface (S12SCIV5)
When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic
1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal
goes low and the transmit signal goes idle.
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register
continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE
to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use this sequence between messages:
1. Write the last byte of the first message to SCIDRH/L.
2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift
register.
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCIDRH/L.
11.4.5.3
Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift
register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit.
Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic
1, transmitter logic continuously loads break characters into the transmit shift register. After software
clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least
one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit
of the next frame.
The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received.
Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI
registers.
If the break detect feature is disabled (BKDFE = 0):
• Sets the framing error flag, FE
• Sets the receive data register full flag, RDRF
• Clears the SCI data registers (SCIDRH/L)
• May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF
(see 3.4.4 and 3.4.5 SCI Status Register 1 and 2)
If the break detect feature is enabled (BKDFE = 1) there are two scenarios1
The break is detected right from a start bit or is detected during a byte reception.
• Sets the break detect interrupt flag, BLDIF
• Does not change the data register full flag, RDRF or overrun flag OR
• Does not change the framing error flag FE, parity error flag PE.
• Does not clear the SCI data registers (SCIDRH/L)
• May set noise flag NF, or receiver active flag RAF.
1. A Break character in this context are either 10 or 11 consecutive zero received bits
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Serial Communication Interface (S12SCIV5)
Figure 11-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit,
while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there
will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing
error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later
during the transmission. At the expected stop bit position the byte received so far will be transferred to the
receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate
a parity error will be set. Once the break is detected the BRKDIF flag will be set.
Start Bit Position
Stop Bit Position
BRKDIF = 1
RXD_1
Zero Bit Counter
1
2
3
4
5
6
7
8
9
10 . . .
BRKDIF = 1
FE = 1
RXD_2
Zero Bit Counter
1
2
3
4
5
6
7
8
9
10
...
Figure 11-17. Break Detection if BRKDFE = 1 (M = 0)
11.4.5.4
Idle Characters
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character
length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle
character that begins the first transmission initiated after writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the frame currently being transmitted.
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out through the TXD pin. Setting TE after the
stop bit appears on TXD causes data previously written to the SCI data
register to be lost. Toggle the TE bit for a queued idle character while the
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
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Serial Communication Interface (S12SCIV5)
11.4.5.5
LIN Transmit Collision Detection
This module allows to check for collisions on the LIN bus.
LIN Physical Interface
Synchronizer Stage
Receive Shift
Register
Compare
RXD Pin
Bit Error
LIN Bus
Bus Clock
Sample
Point
Transmit Shift
Register
TXD Pin
Figure 11-18. Collision Detect Principle
If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the
transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run
when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received
data is detected the following happens:
• The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
• The transmission is aborted and the byte in transmit buffer is discarded.
• the transmit data register empty and the transmission complete flag will be set
• The bit error interrupt flag, BERRIF, will be set.
• No further transmissions will take place until the BERRIF is cleared.
4
5
6
7
8
BERRM[1:0] = 0:1
9
10
11
12
13
14
15
0
Sampling End
3
Sampling Begin
Input Receive
Shift Register
2
Sampling End
Output Transmit
Shift Register
1
Sampling Begin
0
BERRM[1:0] = 1:1
Compare Sample Points
Figure 11-19. Timing Diagram Bit Error Detection
If the bit error detect feature is disabled, the bit error interrupt flag is cleared.
NOTE
The RXPOL and TXPOL bit should be set the same when transmission
collision detect feature is enabled, otherwise the bit error interrupt flag may
be set incorrectly.
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Serial Communication Interface (S12SCIV5)
11.4.6
Receiver
Internal Bus
SBR12:SBR0
RXPOL
Data
Recovery
Loop
Control
H
Start
11-Bit Receive Shift Register
8
7
6
5
4
3
2
1
0
L
All 1s
SCRXD
From TXD Pin
or Transmitter
Stop
Baud Divider
MSB
Bus
Clock
SCI Data Register
RE
RAF
LOOPS
RSRC
FE
M
WAKE
ILT
PE
PT
RWU
NF
Wakeup
Logic
PE
R8
Parity
Checking
Idle IRQ
IDLE
ILIE
BRKDFE
OR
Break
Detect Logic
RIE
BRKDIF
BRKDIE
Active Edge
Detect Logic
RDRF/OR
IRQ
RDRF
Break IRQ
RXEDGIF
RXEDGIE
RX Active Edge IRQ
Figure 11-20. SCI Receiver Block Diagram
11.4.6.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.6.2
Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
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Freescale Semiconductor
Serial Communication Interface (S12SCIV5)
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
11.4.6.3
Data Sampling
The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust
for baud rate mismatch, the RT clock (see Figure 11-21) is re-synchronized:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic
1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Start Bit
LSB
RXD
Samples
1
1
1
1
1
1
1
1
0
0
Start Bit
Qualification
0
0
Start Bit
Verification
0
0
0
Data
Sampling
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT CLock Count
RT1
RT Clock
Reset RT Clock
Figure 11-21. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Figure 11-17 summarizes the results of the start bit verification samples.
Table 11-17. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
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Serial Communication Interface (S12SCIV5)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 11-18 summarizes the results of the data bit samples.
Table 11-18. Data Bit Recovery
RT8, RT9, and RT10 Samples
Data Bit Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit (logic 0).
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-19
summarizes the results of the stop bit samples.
Table 11-19. Stop Bit Recovery
RT8, RT9, and RT10 Samples
Framing Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
In Figure 11-22 the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
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Serial Communication Interface (S12SCIV5)
LSB
Start Bit
0
0
0
0
0
0
RT9
1
RT10
RT1
1
RT8
RT1
1
RT7
0
RT1
1
RT1
1
RT5
1
RT1
Samples
RT1
RXD
0
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT6
RT5
RT4
RT3
RT2
RT4
RT3
RT Clock Count
RT2
RT Clock
Reset RT Clock
Figure 11-22. Start Bit Search Example 1
In Figure 11-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Perceived Start Bit
Actual Start Bit
LSB
1
0
RT1
RT1
RT1
RT1
RT1
1
0
0
0
0
0
RT10
1
RT9
1
RT8
1
RT7
1
RT1
RXD
Samples
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT6
RT5
RT4
RT3
RT Clock Count
RT2
RT Clock
Reset RT Clock
Figure 11-23. Start Bit Search Example 2
In Figure 11-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
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Serial Communication Interface (S12SCIV5)
Perceived Start Bit
LSB
Actual Start Bit
RT1
RT1
0
1
0
0
0
0
RT10
0
RT9
1
RT8
1
RT7
1
RT1
Samples
RT1
RXD
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT6
RT5
RT4
RT3
RT Clock Count
RT2
RT Clock
Reset RT Clock
Figure 11-24. Start Bit Search Example 3
Figure 11-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper
synchronization with the start bit time, it does set the noise flag.
Perceived and Actual Start Bit
LSB
1
RT1
RT1
RT1
1
1
1
1
0
RT1
1
RT1
1
RT1
1
RT1
1
RT1
Samples
RT1
RXD
1
0
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT9
RT10
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT Clock Count
RT1
RT Clock
Reset RT Clock
Figure 11-25. Start Bit Search Example 4
Figure 11-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample
after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error flag.
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Serial Communication Interface (S12SCIV5)
Start Bit
0
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
0
1
1
0
0
0
0
0
0
0
0
RT1
1
RT1
1
RT1
1
RT1
1
RT1
1
RT1
1
RT1
1
RT1
1
RT7
1
RT1
RXD
Samples
LSB
No Start Bit Found
RT1
RT1
RT1
RT1
RT6
RT5
RT4
RT3
RT Clock Count
RT2
RT Clock
Reset RT Clock
Figure 11-26. Start Bit Search Example 5
In Figure 11-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the
noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.
Start Bit
LSB
RT1
RT1
1
0
0
0
0
1
0
1
RT10
RT1
1
RT9
RT1
1
RT8
1
RT7
1
RT1
1
RT1
1
RT1
1
RT1
1
RT1
Samples
RT1
RXD
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT6
RT5
RT4
RT3
RT Clock Count
RT2
RT Clock
Reset RT Clock
Figure 11-27. Start Bit Search Example 6
11.4.6.4
Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it
sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag
because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
11.4.6.5
Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated
bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside
the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical
values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the
RT8, RT9, and RT10 stop bit samples are a logic zero.
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As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge
within the frame. Re synchronization within frames will correct a misalignment between transmitter bit
times and receiver bit times.
11.4.6.5.1
Slow Data Tolerance
Figure 11-28 shows how much a slow received frame can be misaligned without causing a noise error or
a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
MSB
Stop
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
Receiver
RT Clock
Data
Samples
Figure 11-28. Slow Data
Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles
to start data sampling of the stop bit.
With the misaligned character shown in Figure 11-28, the receiver counts 151 RTr cycles at the point when
the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data
character with no errors is:
((151 – 144) / 151) x 100 = 4.63%
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles
to start data sampling of the stop bit.
With the misaligned character shown in Figure 11-28, the receiver counts 167 RTr cycles at the point when
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
((167 – 160) / 167) X 100 = 4.19%
11.4.6.5.2
Fast Data Tolerance
Figure 11-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
instead of RT16 but is still sampled at RT8, RT9, and RT10.
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Stop
Idle or Next Frame
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
Receiver
RT Clock
Data
Samples
Figure 11-29. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 11-29, the receiver counts 154 RTr cycles at the point when
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is:
((160 – 154) / 160) x 100 = 3.75%
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles
to finish data sampling of the stop bit.
With the misaligned character shown in Figure 11-29, the receiver counts 170 RTr cycles at the point when
the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is:
((176 – 170) /176) x 100 = 3.40%
11.4.6.6
Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2
(SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will
still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag.
The transmitting device can address messages to selected receivers by including addressing information in
the initial frame or frames of each message.
The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby
state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark
wakeup.
11.4.6.6.1
Idle Input line Wakeup (WAKE = 0)
In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The
initial frame or frames of every message contain addressing information. All receivers evaluate the
addressing information, and receivers for which the message is addressed process the frames that follow.
Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The
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RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD
pin.
Idle line wakeup requires that messages be separated by at least one idle character and that no message
contains idle characters.
The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register
full flag, RDRF.
The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1).
11.4.6.6.2
Address Mark Wakeup (WAKE = 1)
In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit
and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains
addressing information. All receivers evaluate the addressing information, and the receivers for which the
message is addressed process the frames that follow.Any receiver for which a message is not addressed can
set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on
standby until another address frame appears on the RXD pin.
The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets
the RDRF flag.
Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames.
NOTE
With the WAKE bit clear, setting the RWU bit after the RXD pin has been
idle can cause the receiver to wake up immediately.
11.4.7
Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is
disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.
Transmitter
Receiver
TXD
RXD
Figure 11-30. Single-Wire Operation (LOOPS = 1, RSRC = 1)
Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control
register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting
the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as
an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.
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NOTE
In single-wire operation data from the TXD pin is inverted if RXPOL is set.
11.4.8
Loop Operation
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the
SCI.
Transmitter
TXD
Receiver
RXD
Figure 11-31. Loop Operation (LOOPS = 1, RSRC = 0)
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1
(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC
bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).
NOTE
In loop operation data from the transmitter is not recognized by the receiver
if RXPOL and TXPOL are not the same.
11.5
Initialization/Application Information
11.5.1
Reset Initialization
See Section 11.3.2, “Register Descriptions”.
11.5.2
11.5.2.1
Modes of Operation
Run Mode
Normal mode of operation.
To initialize a SCI transmission, see Section 11.4.5.2, “Character Transmission”.
11.5.2.2
Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
• If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
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If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
11.5.2.3
Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input
can be used to bring the CPU out of stop mode.
11.5.3
Interrupt Operation
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt
requests. Table 11-20 lists the eight interrupt sources of the SCI.
Table 11-20. SCI Interrupt Sources
Interrupt
Source
Local Enable
TDRE
SCISR1[7]
TIE
TC
SCISR1[6]
TCIE
RDRF
SCISR1[5]
RIE
OR
SCISR1[3]
IDLE
SCISR1[4]
RXEDGIF SCIASR1[7]
Description
Active high level. Indicates that a byte was transferred from SCIDRH/L to the
transmit shift register.
Active high level. Indicates that a transmit is complete.
Active high level. The RDRF interrupt indicates that received data is available
in the SCI data register.
Active high level. This interrupt indicates that an overrun condition has occurred.
ILIE
Active high level. Indicates that receiver input has become idle.
RXEDGIE
Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for
RXPOL = 1) was detected.
BERRIF
SCIASR1[1]
BERRIE
Active high level. Indicates that a mismatch between transmitted and received data
in a single wire application has happened.
BKDIF
SCIASR1[0]
BRKDIE
Active high level. Indicates that a break character has been received.
11.5.3.1
Description of Interrupt Operation
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request
and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are
chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and
all the following interrupts, when generated, are ORed together and issued through that port.
11.5.3.1.1
TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI
data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a
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new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1
with TDRE set and then writing to SCI data register low (SCIDRL).
11.5.3.1.2
TC Description
The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed
when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be
transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing
there is no more data queued for transmission) when the break character has been shifted out. A TC
interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and
no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle
(logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data
register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to
be sent.
11.5.3.1.3
RDRF Description
The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A
RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the
byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one
(SCISR1) and then reading SCI data register low (SCIDRL).
11.5.3.1.4
OR Description
The OR interrupt is set when software fails to read the SCI data register before the receive shift register
receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data
already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status
register one (SCISR1) and then reading SCI data register low (SCIDRL).
11.5.3.1.5
IDLE Description
The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1)
appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before
an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE
set and then reading SCI data register low (SCIDRL).
11.5.3.1.6
RXEDGIF Description
The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the
RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.
11.5.3.1.7
BERRIF Description
The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single
wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative
status register 1. This flag is also cleared if the bit error detect feature is disabled.
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11.5.3.1.8
BKDIF Description
The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the
SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.
11.5.4
Recovery from Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode.
11.5.5
Recovery from Stop Mode
An active edge on the receive input can be used to bring the CPU out of stop mode.
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Chapter 12
Serial Peripheral Interface (S12SPIV5)
Table 12-1. Revision History
Revision
Number
Revision Date
Sections
Affected
V05.00
24 Mar 2005
12.3.2/12-403
12.1
Description of Changes
- Added 16-bit transfer width feature.
Introduction
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
12.1.1
Glossary of Terms
SPI
SS
SCK
MOSI
MISO
MOMI
SISO
12.1.2
Serial Peripheral Interface
Slave Select
Serial Clock
Master Output, Slave Input
Master Input, Slave Output
Master Output, Master Input
Slave Input, Slave Output
Features
The SPI includes these distinctive features:
• Master mode and slave mode
• Selectable 8 or 16-bit transfer width
• Bidirectional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode
12.1.3
Modes of Operation
The SPI functions in three modes: run, wait, and stop.
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•
•
•
Run mode
This is the basic mode of operation.
Wait mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock
generation turned off. If the SPI is configured as a master, any transmission in progress stops, but
is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of data continues, so that the slave stays synchronized to the master.
Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of data continues, so that the slave stays
synchronized to the master.
For a detailed description of operating modes, please refer to Section 12.4.7, “Low Power Mode Options”.
12.1.4
Block Diagram
Figure 12-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and
data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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SPI
2
SPI Control Register 1
BIDIROE
2
SPI Control Register 2
SPC0
SPI Status Register
SPIF MODF SPTEF
Slave
Control
CPOL
CPHA
Phase + SCK In
Slave Baud Rate Polarity
Control
Master Baud Rate
Phase + SCK Out
Polarity
Control
Interrupt Control
SPI
Interrupt
Request
Baud Rate Generator
Master
Control
Counter
Bus Clock
Prescaler Clock Select
SPPR
3
SPR
MOSI
Port
Control
Logic
SCK
SS
Baud Rate
Shift
Clock
Sample
Clock
3
Shifter
SPI Baud Rate Register
Data In
LSBFE=1
LSBFE=0
LSBFE=1
MSB
SPI Data Register
LSBFE=0
LSBFE=0 LSB
LSBFE=1
Data Out
Figure 12-1. SPI Block Diagram
12.2
External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPI module has a total of four external pins.
12.2.1
MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
12.2.2
MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
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12.2.3
SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
12.2.4
SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
12.3.1
Module Memory Map
The memory map for the SPI is given in Figure 12-2. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
MODFEN
BIDIROE
SPISWAI
SPC0
SPR2
SPR1
SPR0
0x0000
SPICR1
R
W
0x0001
SPICR2
R
W
0
0x0002
SPIBR
R
W
0
0x0003
SPISR
R
W
0x0004
SPIDRH
XFRW
0
0
0
SPPR2
SPPR1
SPPR0
SPIF
0
SPTEF
MODF
0
0
0
0
R
W
R15
T15
R14
T14
R13
T13
R12
T12
R11
T11
R10
T10
R9
T9
R8
T8
0x0005
SPIDRL
R
W
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
0x0006
Reserved
R
W
0x0007
Reserved
R
W
= Unimplemented or Reserved
Figure 12-2. SPI Register Summary
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12.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
12.3.2.1
SPI Control Register 1 (SPICR1)
Module Base +0x0000
R
W
Reset
7
6
5
4
3
2
1
0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0
0
0
0
0
1
0
0
Figure 12-3. SPI Control Register 1 (SPICR1)
Read: Anytime
Write: Anytime
Table 12-2. SPICR1 Field Descriptions
Field
Description
7
SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
6
SPE
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
5
SPTIE
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
4
MSTR
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
3
CPOL
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
2
CPHA
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
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Table 12-2. SPICR1 Field Descriptions (continued)
Field
Description
1
SSOE
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in Table 12-3. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
0
LSBFE
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
Table 12-3. SS Input / Output Selection
MODFEN
12.3.2.2
SSOE
Master Mode
Slave Mode
0
0
SS not used by SPI
SS input
0
1
SS not used by SPI
SS input
1
0
SS input with MODF feature
SS input
1
1
SS is slave select output
SS input
SPI Control Register 2 (SPICR2)
Module Base +0x0001
7
R
0
W
Reset
0
6
XFRW
0
5
0
0
4
3
MODFEN
BIDIROE
0
0
2
0
0
1
0
SPISWAI
SPC0
0
0
= Unimplemented or Reserved
Figure 12-4. SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
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Table 12-4. SPICR2 Field Descriptions
Field
Description
6
XFRW
Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL
becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and
SPIDRL form a 16-bit data register. Please refer to Section 12.3.2.4, “SPI Status Register (SPISR) for
information about transmit/receive data handling and the interrupt flag clearing mechanism. In master mode, a
change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 8-bit Transfer Width (n = 8)(1)
1 16-bit Transfer Width (n = 16)1
4
MODFEN
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to Table 12-3. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
3
BIDIROE
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
1
SPISWAI
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
0
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 12-5. In master
SPC0
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
1. n is used later in this document as a placeholder for the selected transfer width.
Table 12-5. Bidirectional Pin Configurations
Pin Mode
SPC0
BIDIROE
MISO
MOSI
Master Mode of Operation
Normal
0
Bidirectional
1
X
Master In
0
MISO not used by SPI
1
Master Out
Master In
Master I/O
Slave Mode of Operation
Normal
0
Bidirectional
1
X
Slave Out
Slave In
0
Slave In
MOSI not used by SPI
1
Slave I/O
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Serial Peripheral Interface (S12SPIV5)
12.3.2.3
SPI Baud Rate Register (SPIBR)
Module Base +0x0002
7
R
6
0
W
Reset
0
5
4
3
SPPR2
SPPR1
SPPR0
0
0
0
0
0
2
1
0
SPR2
SPR1
SPR0
0
0
0
= Unimplemented or Reserved
Figure 12-5. SPI Baud Rate Register (SPIBR)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 12-6. SPIBR Field Descriptions
Field
Description
6–4
SPPR[2:0]
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 12-7. In master
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
2–0
SPR[2:0]
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 12-7. In master mode,
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = (SPPR + 1) • 2(SPR + 1)
Eqn. 12-1
The baud rate can be calculated with the following equation:
Baud Rate = BusClock / BaudRateDivisor
Eqn. 12-2
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 1 of 3)
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Baud Rate
Divisor
Baud Rate
0
0
0
0
0
0
2
12.5 Mbit/s
0
0
0
0
0
1
4
6.25 Mbit/s
0
0
0
0
1
0
8
3.125 Mbit/s
0
0
0
0
1
1
16
1.5625 Mbit/s
0
0
0
1
0
0
32
781.25 kbit/s
0
0
0
1
0
1
64
390.63 kbit/s
0
0
0
1
1
0
128
195.31 kbit/s
0
0
0
1
1
1
256
97.66 kbit/s
0
0
1
0
0
0
4
6.25 Mbit/s
0
0
1
0
0
1
8
3.125 Mbit/s
0
0
1
0
1
0
16
1.5625 Mbit/s
0
0
1
0
1
1
32
781.25 kbit/s
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Freescale Semiconductor
Serial Peripheral Interface (S12SPIV5)
Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3)
Baud Rate
Divisor
Baud Rate
0
64
390.63 kbit/s
1
128
195.31 kbit/s
1
0
256
97.66 kbit/s
1
1
512
48.83 kbit/s
0
0
0
6
4.16667 Mbit/s
0
0
1
12
2.08333 Mbit/s
0
0
1
0
24
1.04167 Mbit/s
0
0
1
1
48
520.83 kbit/s
1
0
1
0
0
96
260.42 kbit/s
1
0
1
0
1
192
130.21 kbit/s
0
1
0
1
1
0
384
65.10 kbit/s
0
1
0
1
1
1
768
32.55 kbit/s
0
1
1
0
0
0
8
3.125 Mbit/s
0
1
1
0
0
1
16
1.5625 Mbit/s
0
1
1
0
1
0
32
781.25 kbit/s
0
1
1
0
1
1
64
390.63 kbit/s
0
1
1
1
0
0
128
195.31 kbit/s
0
1
1
1
0
1
256
97.66 kbit/s
0
1
1
1
1
0
512
48.83 kbit/s
0
1
1
1
1
1
1024
24.41 kbit/s
1
0
0
0
0
0
10
2.5 Mbit/s
1
0
0
0
0
1
20
1.25 Mbit/s
1
0
0
0
1
0
40
625 kbit/s
1
0
0
0
1
1
80
312.5 kbit/s
1
0
0
1
0
0
160
156.25 kbit/s
1
0
0
1
0
1
320
78.13 kbit/s
1
0
0
1
1
0
640
39.06 kbit/s
1
0
0
1
1
1
1280
19.53 kbit/s
1
0
1
0
0
0
12
2.08333 Mbit/s
1
0
1
0
0
1
24
1.04167 Mbit/s
1
0
1
0
1
0
48
520.83 kbit/s
1
0
1
0
1
1
96
260.42 kbit/s
1
0
1
1
0
0
192
130.21 kbit/s
1
0
1
1
0
1
384
65.10 kbit/s
1
0
1
1
1
0
768
32.55 kbit/s
1
0
1
1
1
1
1536
16.28 kbit/s
1
1
0
0
0
0
14
1.78571 Mbit/s
1
1
0
0
0
1
28
892.86 kbit/s
1
1
0
0
1
0
56
446.43 kbit/s
1
1
0
0
1
1
112
223.21 kbit/s
1
1
0
1
0
0
224
111.61 kbit/s
1
1
0
1
0
1
448
55.80 kbit/s
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
0
1
0
0
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Serial Peripheral Interface (S12SPIV5)
Table 12-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
Baud Rate
Divisor
Baud Rate
0
896
27.90 kbit/s
1
1792
13.95 kbit/s
0
0
16
1.5625 Mbit/s
0
1
32
781.25 kbit/s
0
1
0
64
390.63 kbit/s
0
1
1
128
195.31 kbit/s
1
1
0
0
256
97.66 kbit/s
1
1
0
1
512
48.83 kbit/s
1
1
1
1
0
1024
24.41 kbit/s
1
1
1
1
1
2048
12.21 kbit/s
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
12.3.2.4
SPI Status Register (SPISR)
Module Base +0x0003
R
7
6
5
4
3
2
1
0
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
1
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 12-6. SPI Status Register (SPISR)
Read: Anytime
Write: Has no effect
Table 12-8. SPISR Field Descriptions
Field
Description
7
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to Table 12-9.
0 Transfer not yet complete.
1 New data copied to SPIDR.
5
SPTEF
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to Table 12-10.
0 SPI data register not empty.
1 SPI data register empty.
4
MODF
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 12.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
S12P-Family Reference Manual, Rev. 1.13
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Serial Peripheral Interface (S12SPIV5)
Table 12-9. SPIF Interrupt Flag Clearing Sequence
XFRW Bit
SPIF Interrupt Flag Clearing Sequence
0
Read SPISR with SPIF == 1
1
Read SPISR with SPIF == 1
then
Read SPIDRL
Byte Read SPIDRL (1)
or
then Byte Read SPIDRH (2)
Byte Read SPIDRL
or
Word Read (SPIDRH:SPIDRL)
1. Data in SPIDRH is lost in this case.
2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
of SPIDRL after reading SPISR with SPIF == 1.
Table 12-10. SPTEF Interrupt Flag Clearing Sequence
XFRW Bit
SPTEF Interrupt Flag Clearing Sequence
0
Read SPISR with SPTEF == 1 then
1
Read SPISR with SPTEF == 1
Write to SPIDRL (1)
Byte Write to SPIDRL 1(2)
or
then Byte Write to SPIDRH 1(3) Byte Write to SPIDRL 1
or
Word Write to (SPIDRH:SPIDRL) 1
1. Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.
2. Data in SPIDRH is undefined in this case.
3. SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by
writing to SPIDRL after reading SPISR with SPTEF == 1.
S12P-Family Reference Manual, Rev. 1.13
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Serial Peripheral Interface (S12SPIV5)
12.3.2.5
SPI Data Register (SPIDR = SPIDRH:SPIDRL)
Module Base +0x0004
7
6
5
4
3
2
1
0
R
R15
R14
R13
R12
R11
R10
R9
R8
W
T15
T14
T13
T12
T11
T10
T9
T8
0
0
0
0
0
0
0
0
Reset
Figure 12-7. SPI Data Register High (SPIDRH)
Module Base +0x0005
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
0
0
0
0
0
0
0
0
Reset
Figure 12-8. SPI Data Register Low (SPIDRL)
Read: Anytime; read data only valid when SPIF is set
Write: Anytime
The SPI data register is both the input and output register for SPI data. A write to this register
allows data to be queued and transmitted. For an SPI configured as a master, queued data is
transmitted immediately after the previous transmission has completed. The SPI transmitter empty
flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and data has been received, the received data is transferred from the receive shift
register to the SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second data value has been received, the second received data
is kept as valid data in the receive shift register until the start of another transmission. The data in
the SPIDR does not change.
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of
a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF
remains set (see Figure 12-9).
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a
third transmission, the data in the receive shift register has become invalid and is not transferred
into the SPIDR (see Figure 12-10).
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Serial Peripheral Interface (S12SPIV5)
Data A Received
Data B Received
Data C Received
SPIF Serviced
Receive Shift Register
Data B
Data A
Data C
SPIF
SPI Data Register
Data B
Data A
= Unspecified
Data C
= Reception in progress
Figure 12-9. Reception with SPIF serviced in Time
Data A Received
Data B Received
Data C Received
Data B Lost
SPIF Serviced
Receive Shift Register
Data B
Data A
Data C
SPIF
SPI Data Register
Data A
= Unspecified
Data C
= Reception in progress
Figure 12-10. Reception with SPIF serviced too late
12.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,
the four associated SPI port pins are dedicated to the SPI function as:
• Slave select (SS)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
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Serial Peripheral Interface (S12SPIV5)
The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the
n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1
register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions
by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the
master SPI data register becomes the output data for the slave, and data read from the master SPI data
register after a transfer operation is the input data from the slave.
A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register.
When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This
data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes.
A common SPI data register address is shared for reading data from the read data buffer and for writing
data to the transmit data register.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1
(SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply
selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally
different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see
Section 12.4.3, “Transmission Formats”).
The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1
is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
NOTE
A change of CPOL or MSTR bit while there is a received byte pending in
the receive shift register will destroy the received byte and must be avoided.
12.4.1
Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate
transmissions. A transmission begins by writing to the master SPI data register. If the shift register is
empty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under the
control of the serial clock.
• Serial clock
The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and
SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and
determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK
pin, the baud rate generator of the master controls the shift register of the slave peripheral.
• MOSI, MISO pin
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin
(MISO) is determined by the SPC0 and BIDIROE control bits.
• SS pin
If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output
becomes low during each transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault
error. If the SS input becomes low this indicates a mode fault error where another master tries to
1. n depends on the selected transfer width, please refer to Section 12.3.2.2, “SPI Control Register 2 (SPICR2)
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Serial Peripheral Interface (S12SPIV5)
drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by
clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional
mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a
transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is
forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If
the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt
sequence is also requested.
When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After
the delay, SCK is started within the master. The rest of the transfer operation differs slightly,
depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1
(see Section 12.4.3, “Transmission Formats”).
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN,
SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in
master mode will abort a transmission in progress and force the SPI into idle
state. The remote slave cannot detect this, therefore the master must ensure
that the remote slave is returned to idle state.
12.4.2
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.
• Serial clock
In slave mode, SCK is the SPI clock input from the master.
• MISO, MOSI pin
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI)
is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.
• SS pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI
must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is
forced into idle state.
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data
output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of
the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is
ignored and no internal shifting of the SPI shift register occurs.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only
receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.
NOTE
When peripherals with duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the same
system slave’s serial data output line.
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Serial Peripheral Interface (S12SPIV5)
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a master, although the master would not receive return
information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at
the serial data input pin to be latched. Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to
be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
output pin. After the nth1 shift, the transfer is considered complete and the received data is transferred into
the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set.
NOTE
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or
BIDIROE with SPC0 set in slave mode will corrupt a transmission in
progress and must be avoided.
12.4.3
Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially)
simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two
serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that
are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select
line can be used to indicate multiple-master bus contention.
MASTER SPI
SHIFT REGISTER
BAUD RATE
GENERATOR
SLAVE SPI
MISO
MISO
MOSI
MOSI
SCK
SCK
SS
VDD
SHIFT REGISTER
SS
Figure 12-11. Master/Slave Transfer Block Diagram
12.4.3.1
Clock Phase and Polarity Controls
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase
and polarity.
1. n depends on the selected transfer width, please refer to Section 12.3.2.2, “SPI Control Register 2 (SPICR2)
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Serial Peripheral Interface (S12SPIV5)
The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on
the transmission format.
The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
Clock phase and polarity should be identical for the master SPI device and the communicating slave
device. In some cases, the phase and polarity are changed between transmissions to allow a master device
to communicate with peripheral slaves having different requirements.
12.4.3.2
CPHA = 0 Transfer Format
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first
data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the
slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle
after SS has become low.
A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value
previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register,
depending on LSBFE bit.
After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of
the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK
line, with data being latched on odd numbered edges and shifted on even numbered edges.
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and
is transferred to the parallel SPI data register after the last bit is shifted in.
After 2n1 (last) SCK edges:
• Data that was previously in the master SPI data register should now be in the slave data register and
the data that was in the slave data register should be in the master.
• The SPIF flag in the SPI status register is set, indicating that the transfer is complete.
Figure 12-12 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for
CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because
the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal
is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master
must be either high or reconfigured as a general-purpose output not affecting the SPI.
1. n depends on the selected transfer width, please refer to Section 12.3.2.2, “SPI Control Register 2 (SPICR2)
S12P-Family Reference Manual, Rev. 1.13
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End of Idle State
Begin
1
SCK Edge Number
2
3
4
5
6
7
8
Begin of Idle State
End
Transfer
9
10
11
12
13 14
15
16
Bit 1
Bit 6
LSB Minimum 1/2 SCK
for tT, tl, tL
MSB
SCK (CPOL = 0)
SCK (CPOL = 1)
If next transfer begins here
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tT
tL
MSB first (LSBFE = 0): MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LSB first (LSBFE = 1): LSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
tL = Minimum leading time before the first SCK edge
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time)
tL, tT, and tI are guaranteed for the master mode and required for the slave mode.
tI
tL
Figure 12-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)
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End of Idle State
SCK Edge Number
Begin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Begin of Idle State
End
Transfer
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCK (CPOL = 0)
SCK (CPOL = 1)
If next transfer begins here
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
tL
tT tI tL
MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
Minimum 1/2 SCK
LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14 MSB
for tT, tl, tL
tL = Minimum leading time before the first SCK edge
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time)
tL, tT, and tI are guaranteed for the master mode and required for the slave mode.
Figure 12-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the
SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted
for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the
SPI data register is transmitted.
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between
successive transfers for at least minimum idle time.
12.4.3.3
CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin,
the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the n1-cycle transfer operation.
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first
edge commands the slave to transfer its first data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the
master and slave.
1. n depends on the selected transfer width, please refer to Section 12.3.2.2, “SPI Control Register 2 (SPICR2)
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When the third edge occurs, the value previously latched from the serial data input pin is shifted into the
LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master
data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
This process continues for a total of n1 edges on the SCK line with data being latched on even numbered
edges and shifting taking place on odd numbered edges.
Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and
is transferred to the parallel SPI data register after the last bit is shifted in.
After 2n1 SCK edges:
• Data that was previously in the SPI data register of the master is now in the data register of the
slave, and data that was in the data register of the slave is in the master.
• The SPIF flag bit in SPISR is set indicating that the transfer is complete.
Figure 12-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or
slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master
and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the
master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or
reconfigured as a general-purpose output not affecting the SPI.
End of Idle State
Begin
SCK Edge Number
1
2
3
4
End
Transfer
5
6
7
8
9
10
11
12
13 14
Begin of Idle State
15
16
SCK (CPOL = 0)
SCK (CPOL = 1)
If next transfer begins here
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tT
tL
tI
tL
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB Minimum 1/2 SCK
for tT, tl, tL
LSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
Figure 12-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0)
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Serial Peripheral Interface (S12SPIV5)
End of Idle State
SCK Edge Number
Begin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Begin of Idle State
End
Transfer
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCK (CPOL = 0)
SCK (CPOL = 1)
If next transfer begins here
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
tT tI tL
Minimum 1/2 SCK
for tT, tl, tL
tL
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14 MSB
tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers
tT = Minimum trailing time after the last SCK edge
tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
Figure 12-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1)
The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.
• Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register,
this data is sent out immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge.
12.4.4
SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2,
SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in
the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor
equation is shown in Equation 12-3.
BaudRateDivisor = (SPPR + 1) • 2(SPR + 1)
Eqn. 12-3
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When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection
bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor
becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When
the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 12-7 for baud rate calculations
for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided
by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease IDD current.
NOTE
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
12.4.5
12.4.5.1
Special Features
SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and
MODFEN bit as shown in Table 12-3.
The mode fault feature is disabled while SS output is enabled.
NOTE
Care must be taken when using the SS output feature in a multimaster
system because the mode fault feature is not available for detecting system
errors between masters.
12.4.5.2
Bidirectional Mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 12-11). In
this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit
decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and
the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and
MOSI pin in slave mode are not used by the SPI.
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Serial Peripheral Interface (S12SPIV5)
Table 12-11. Normal Mode and Bidirectional Mode
When SPE = 1
Master Mode MSTR = 1
Serial Out
Normal Mode
SPC0 = 0
MOSI
MOSI
Serial In
SPI
SPI
Serial In
MISO
Serial Out
Bidirectional Mode
SPC0 = 1
Slave Mode MSTR = 0
MOMI
Serial Out
MISO
Serial In
BIDIROE
SPI
BIDIROE
Serial In
SPI
Serial Out
SISO
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output,
serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift
register.
• The SCK is output for the master mode and input for the slave mode.
• The SS is the input or output for the master mode, and it is always the input for the slave mode.
• The bidirectional mode does not affect SCK and SS functions.
NOTE
In bidirectional master mode, with mode fault enabled, both data pins MISO
and MOSI can be occupied by the SPI, though MOSI is normally used for
transmissions in bidirectional mode and MISO is not used by the SPI. If a
mode fault occurs, the SPI is automatically switched to slave mode. In this
case MISO becomes occupied by the SPI and MOSI is not used. This must
be considered, if the MISO pin is used for another purpose.
12.4.6
Error Conditions
The SPI has one error condition:
• Mode fault error
12.4.6.1
Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more
than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not
permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the
MODFEN bit is set.
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by
the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case
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Serial Peripheral Interface (S12SPIV5)
the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur
in slave mode.
If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output
buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any
possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is
forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output
enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in
the bidirectional mode for SPI system configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed
by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or
slave again.
NOTE
If a mode fault error occurs and a received data byte is pending in the receive
shift register, this data byte will be lost.
12.4.7
12.4.7.1
Low Power Mode Options
SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a
low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are
disabled.
12.4.7.2
SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.
• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation
state when the CPU is in wait mode.
–
If SPISWAI is set and the SPI is configured for master, any transmission and reception in
progress stops at wait mode entry. The transmission and reception resumes when the SPI exits
wait mode.
–
If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in
progress continues if the SCK continues to be driven from the master. This keeps the slave
synchronized to the master and the SCK.
If the master transmits several bytes while the slave is in wait mode, the slave will continue to
send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is
currently sending its SPIDR to the master, it will continue to send the same byte. Else if the
slave is currently sending the last received byte from the master, it will continue to send each
previous master byte).
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NOTE
Care must be taken when expecting data from a master while the slave is in
wait or stop mode. Even though the shift register will continue to operate,
the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated
until exiting stop or wait mode). Also, the byte from the shift register will
not be copied into the SPIDR register until after the slave SPI has exited wait
or stop mode. In slave mode, a received byte pending in the receive shift
register will be lost when entering wait or stop mode. An SPIF flag and
SPIDR copy is generated only if wait mode is entered or exited during a
tranmission. If the slave enters wait mode in idle mode and exits wait mode
in idle mode, neither a SPIF nor a SPIDR copy will occur.
12.4.7.3
SPI in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held
high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the
transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is
exchanged correctly. In slave mode, the SPI will stay synchronized with the master.
The stop mode is not dependent on the SPISWAI bit.
12.4.7.4
Reset
The reset values of registers and signals are described in Section 12.3, “Memory Map and Register
Definition”, which details the registers and their bit fields.
• If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the data last received from the master before the reset.
• Reading from the SPIDR after reset will always read zeros.
12.4.7.5
Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is
a description of how the SPI makes a request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
12.4.7.5.1
MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see Table 12-3). After MODF is set, the current transfer is aborted and the following bit is
changed:
• MSTR = 0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in Section 12.3.2.4, “SPI Status Register (SPISR)”.
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12.4.7.5.2
SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does
not clear until it is serviced. SPIF has an automatic clearing process, which is described in
Section 12.3.2.4, “SPI Status Register (SPISR)”.
12.4.7.5.3
SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process, which is described in Section 12.3.2.4, “SPI
Status Register (SPISR)”.
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Chapter 13
128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-1. Revision History
Revision
Number
Revision
Date
Sections
Affected
V01.09
28 Jul 2008
13.1.1/13-426
13.3.1/13-429
V01.10
19 Dec 2008
13.1/13-425
13.4.5.4/13-457
13.4.5.6/13-459
13.4.5.11/13463
13.4.5.11/13463
13.4.5.11/13463
13.5.2/13-471
V01.11
25 Sep 2009
-The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
13.3.2/13-432 - Add caution concerning register writes while command is active
13.3.2.1/13-433 - Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
13.4.3.2/13-451 - Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
13.6/13-472
reset sequence
13.1
Description of Changes
- Remove reference to IFRON in Program IFR definition
- Remove reference to IFRON in Table 13-4 and Figure 13-3
- Clarify single bit fault correction for P-Flash phrase
- Add statement concerning code runaway when executing Read Once,
Program Once, and Verify Backdoor Access Key commands from Flash block
containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Reformat section on unsecuring MCU using BDM
Introduction
The FTMRC128K1 module implements the following:
• 128 Kbytes of P-Flash (Program Flash) memory
• 4 Kbytes of D-Flash (Data Flash) memory
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents. The user interface to the
memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is
written to with the command, global address, data, and any required command parameters. The memory
controller must complete the execution of a command before the FCCOB register can be written to with a
new command.
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CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus
cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory, an erased
bit reads 1 and a programmed bit reads 0.
It is possible to read from P-Flash memory while some commands are executing on D-Flash memory. It
is not possible to read from D-Flash memory while a command is executing on P-Flash memory.
Simultaneous P-Flash and D-Flash operations are discussed in Section 13.4.4.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read
by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word
accessed will be corrected.
13.1.1
Glossary
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
The D-Flash sector consists of four 64 byte rows for a total of 256 bytes.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two
sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double
bit fault detection within each double word.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 512 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device
ID, Version ID, and the Program Once field.
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128 KByte Flash Module (S12FTMRC128K1V1)
13.1.2
13.1.2.1
•
•
•
•
•
•
•
•
•
•
•
D-Flash Features
4 Kbytes of D-Flash memory composed of one 4 Kbyte Flash block divided into 16 sectors of 256
bytes
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Protection scheme to prevent accidental program or erase of D-Flash memory
Ability to program up to four words in a burst sequence
13.1.2.3
•
•
•
P-Flash Features
128 Kbytes of P-Flash memory composed of one 128 Kbyte Flash block divided into 256 sectors
of 512 bytes
Single bit fault correction and double bit fault detection within a 32-bit double word during read
operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to read the P-Flash memory while programming a word in the D-Flash memory
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
13.1.2.2
•
Features
Other Flash Module Features
No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory
13.1.3
Block Diagram
The block diagram of the Flash module is shown in Figure 13-1.
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128 KByte Flash Module (S12FTMRC128K1V1)
Flash
Interface
Command
Interrupt
Request
Error
Interrupt
Request
16bit
internal
bus
Registers
P-Flash
32Kx39
sector 0
sector 1
Protection
sector 255
Security
Bus
Clock
CPU
Clock
Divider FCLK
Memory
Controller
D-Flash
2Kx22
sector 0
sector 1
sector 15
Scratch RAM
384x16
Figure 13-1. FTMRC128K1 Block Diagram
13.2
External Signal Description
The Flash module contains no signals that connect off-chip.
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13.3
Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
13.3.1
Module Memory Map
The S12 architecture places the P-Flash memory between global addresses 0x2_0000 and 0x3_FFFF as
shown in Table 13-2.The P-Flash memory map is shown in Figure 13-2.
Table 13-2. P-Flash Memory Addressing
Global Address
Size
(Bytes)
0x2_0000 – 0x3_FFFF
128 K
Description
P-Flash Block
Contains Flash Configuration Field
(see Table 13-3)
The FPROT register, described in Section 13.3.2.9, can be set to protect regions in the Flash memory from
accidental program or erase. Three separate memory regions, one growing upward from global address
0x3_8000 in the Flash memory (called the lower region), one growing downward from global address
0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash
memory, can be activated for protection. The Flash memory addresses covered by these protectable regions
are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader
code since it covers the vector space. Default protection settings as well as security information that allows
the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in
Table 13-3.
Table 13-3. Flash Configuration Field
Global Address
Size
(Bytes)
0x3_FF00-0x3_FF07
8
Backdoor Comparison Key
Refer to Section 13.4.5.11, “Verify Backdoor Access Key Command,” and
Section 13.5.1, “Unsecuring the MCU using Backdoor Key Access”
0x3_FF08-0x3_FF0B(1)
4
Reserved
0x3_FF0C1
1
P-Flash Protection byte.
Refer to Section 13.3.2.9, “P-Flash Protection Register (FPROT)”
0x3_FF0D1
1
D-Flash Protection byte.
Refer to Section 13.3.2.10, “D-Flash Protection Register (DFPROT)”
0x3_FF0E1
1
Flash Nonvolatile byte
Refer to Section 13.3.2.16, “Flash Option Register (FOPT)”
Description
Flash Security byte
Refer to Section 13.3.2.2, “Flash Security Register (FSEC)”
1. 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in
the 0x3_FF08 - 0x3_FF0B reserved field should be programmed to 0xFF.
0x3_FF0F1
1
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128 KByte Flash Module (S12FTMRC128K1V1)
P-Flash START = 0x2_0000
Flash Protected/Unprotected Region
96 Kbytes
0x3_8000
0x3_8400
0x3_8800
0x3_9000
Protection
Fixed End
Flash Protected/Unprotected Lower Region
1, 2, 4, 8 Kbytes
0x3_A000
Flash Protected/Unprotected Region
8 Kbytes (up to 29 Kbytes)
Protection
Movable End
0x3_C000
Protection
Fixed End
0x3_E000
Flash Protected/Unprotected Higher Region
2, 4, 8, 16 Kbytes
0x3_F000
0x3_F800
P-Flash END = 0x3_FFFF
Flash Configuration Field
16 bytes (0x3_FF00 - 0x3_FF0F)
Figure 13-2. P-Flash Memory Map
Table 13-4. Program IFR Fields
Global Address
Size
(Bytes)
0x0_4000 – 0x0_4007
8
Reserved
0x0_4008 – 0x0_40B5
174
Reserved
0x0_40B6 – 0x0_40B7
2
Field Description
Version ID(1)
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-4. Program IFR Fields
Global Address
Size
(Bytes)
0x0_40B8 – 0x0_40BF
8
Field Description
Reserved
Program Once Field
Refer to Section 13.4.5.6, “Program Once Command”
1. Used to track firmware patch versions, see Section 13.4.2
0x0_40C0 – 0x0_40FF
64
Table 13-5. D-Flash and Memory Controller Resource Fields
Global Address
Size
(Bytes)
0x0_4000 – 0x0_43FF
1,024
Reserved
0x0_4400 – 0x0_53FF
4,096
D-Flash Memory
0x0_5400 – 0x0_57FF
1,024
Reserved
0x0_5800 – 0x0_5AFF
768
0x0_5B00 – 0x0_5FFF
1,280
Reserved
0x0_6000 – 0x0_67FF
2,048
Reserved
0x0_6800 – 0x0_7FFF
1. MMCCTL1 register bit
6,144
Reserved
Description
Memory Controller Scratch RAM (RAMON(1) = 1)
0x0_4000
0x0_40FF
P-Flash IFR 1 Kbyte
D-Flash Start = 0x0_4400
D-Flash Memory
4 Kbytes
D-Flash End = 0x0_53FF
Reserved 1 Kbyte
RAM Start = 0x0_5800
RAM End = 0x0_5AFF
Scratch Ram 768 bytes (RAMON)
Reserved 1280 bytes
0x0_6000
Reserved 2 Kbytes
0x0_6800
Reserved 6 Kbytes
0x0_7FFF
Figure 13-3. D-Flash and Memory Controller Resource Memory Map
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128 KByte Flash Module (S12FTMRC128K1V1)
13.3.2
Register Descriptions
The Flash module contains a set of 20 control and status registers located between Flash module base +
0x0000 and 0x0013. A summary of the Flash module registers is given in Figure 13-4 with detailed
descriptions in the following subsections.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
adversely affect Memory Controller behavior.
Address
& Name
0x0000
FCLKDIV
0x0001
FSEC
0x0002
FCCOBIX
0x0003
FRSV0
0x0004
FCNFG
0x0005
FERCNFG
0x0006
FSTAT
0x0007
FERSTAT
0x0008
FPROT
0x0009
DFPROT
7
R
6
5
4
3
2
1
0
FDIVLCK
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
0
0
0
0
0
0
FDFD
FSFD
DFDIE
SFDIE
MGSTAT1
MGSTAT0
DFDIF
SFDIF
FDIVLD
W
R
W
R
W
R
0
0
0
0
0
0
W
R
CCIE
IGNSF
W
R
0
0
0
0
0
0
W
R
0
CCIF
ACCERR
FPVIOL
0
0
MGBUSY
RSVD
0
0
W
R
0
0
W
R
RNV6
FPOPEN
FPHDIS
FPHS1
0
0
FPHS0
FPLDIS
FPLS1
FPLS0
DPS3
DPS2
DPS1
DPS0
W
R
0
DPOPEN
W
Figure 13-4. FTMRC128K1 Register Summary
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128 KByte Flash Module (S12FTMRC128K1V1)
Address
& Name
0x000A
FCCOBHI
0x000B
FCCOBLO
0x000C
FRSV1
0x000D
FRSV2
0x000E
FRSV3
0x000F
FRSV4
0x0010
FOPT
0x0011
FRSV5
0x0012
FRSV6
0x0013
FRSV7
7
6
5
4
3
2
1
0
CCOB15
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB7
CCOB6
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
= Unimplemented or Reserved
Figure 13-4. FTMRC128K1 Register Summary (continued)
13.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
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128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x0000
7
R
6
5
4
3
2
1
0
0
0
0
FDIVLD
FDIVLCK
FDIV[5:0]
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field.
CAUTION
The FCLKDIV register must never be written to while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
Table 13-6. FCLKDIV Field Descriptions
Field
7
FDIVLD
Description
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
6
FDIVLCK
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV field.
5–0
FDIV[5:0]
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms. Table 13-7 shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to Section 13.4.3, “Flash Command Operations,” for more information.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-7. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
MIN(1)
MAX(2)
1.0
1.6
1.6
BUSCLK Frequency
(MHz)
FDIV[5:0]
MAX
0x00
16.6
17.6
0x10
2.6
0x01
17.6
18.6
0x11
2.6
3.6
0x02
18.6
19.6
0x12
3.6
4.6
0x03
19.6
20.6
0x13
4.6
5.6
0x04
20.6
21.6
0x14
5.6
6.6
0x05
21.6
22.6
0x15
6.6
7.6
0x06
22.6
23.6
0x16
7.6
8.6
0x07
23.6
24.6
0x17
8.6
9.6
0x08
24.6
25.6
0x18
9.6
10.6
0x09
25.6
26.6
0x19
10.6
11.6
0x0A
26.6
27.6
0x1A
11.6
12.6
0x0B
27.6
28.6
0x1B
12.6
13.6
0x0C
28.6
29.6
0x1C
13.6
14.6
0x0D
29.6
30.6
0x1D
14.6
15.6
0x0E
30.6
31.6
0x1E
31.6
32.6
0x1F
MIN
15.6
16.6
0x0F
1. BUSCLK is Greater Than this value.
2. BUSCLK is Less Than or Equal to this value.
13.3.2.2
FDIV[5:0]
1
2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
R
6
5
4
KEYEN[1:0]
3
2
1
RNV[5:2]
0
SEC[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 13-6. Flash Security Register (FSEC)
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 13-3) as
indicated by reset condition F in Figure 13-6. If a double bit fault is detected while reading the P-Flash
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128 KByte Flash Module (S12FTMRC128K1V1)
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be
set to leave the Flash module in a secured state with backdoor key access disabled.
Table 13-8. FSEC Field Descriptions
Field
Description
7–6
Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 13-9.
5–2
RNV[5:2}
Reserved Nonvolatile Bits — The RNV bits should remain in the erased state for future enhancements.
1–0
SEC[1:0]
Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 13-10. If the
Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 13-9. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED(1)
10
ENABLED
11
DISABLED
1. Preferred KEYEN state to disable backdoor key access.
Table 13-10. Flash Security States
SEC[1:0]
Status of Security
00
SECURED
01
SECURED(1)
10
UNSECURED
11
SECURED
1. Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 13.5.
13.3.2.3
Flash CCOB Index Register (FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
Offset Module Base + 0x0002
R
7
6
5
4
3
0
0
0
0
0
2
1
0
CCOBIX[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-7. FCCOB Index Register (FCCOBIX)
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-11. FCCOBIX Field Descriptions
Field
Description
2–0
CCOBIX[1:0]
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
array is being read or written to. See Section 13.3.2.11, “Flash Common Command Object Register (FCCOB),”
for more details.
13.3.2.4
Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000C
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-8. Flash Reserved0 Register (FRSV0)
All bits in the FRSV0 register read 0 and are not writable.
13.3.2.5
Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU.
Offset Module Base + 0x0004
7
R
6
5
0
0
CCIE
4
3
2
0
0
IGNSF
1
0
FDFD
FSFD
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-9. Flash Configuration Register (FCNFG)
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-12. FCNFG Field Descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 13.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 13.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
1
FDFD
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The
FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual
double bit fault is detected.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 13.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 13.3.2.6)
0
FSFD
Force Single Bit Fault Detect — The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD. The
FECCR registers will not be updated during the Flash array read operation with FSFD set unless an actual single
bit fault is detected.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 13.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 13.3.2.6)
13.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0005
R
7
6
5
4
3
2
0
0
0
0
0
0
1
0
DFDIE
SFDIE
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-10. Flash Error Configuration Register (FERCNFG)
All assigned bits in the FERCNFG register are readable and writable.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-13. FERCNFG Field Descriptions
Field
Description
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 13.3.2.8)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 13.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 13.3.2.8)
13.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
7
6
R
5
4
ACCERR
FPVIOL
0
0
0
CCIF
3
2
MGBUSY
RSVD
0
0
1
0
MGSTAT[1:0]
W
Reset
1
0
0(1)
01
= Unimplemented or Reserved
Figure 13-11. Flash Status Register (FSTAT)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 13.6).
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Table 13-14. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see Section 13.4.3.2) or issuing an illegal Flash
command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is
cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash or D-Flash memory during a command write sequence. The FPVIOL
bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL
is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-14. FSTAT Field Descriptions (continued)
Field
3
MGBUSY
2
RSVD
Description
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit — This bit is reserved and always reads 0.
1–0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
MGSTAT[1:0] is detected during execution of a Flash command or during the Flash reset sequence. See Section 13.4.5,
“Flash Command Description,” and Section 13.6, “Initialization” for details.
13.3.2.8
Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
Offset Module Base + 0x0007
R
7
6
5
4
3
2
0
0
0
0
0
0
1
0
DFDIF
SFDIF
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-12. Flash Error Status Register (FERSTAT)
All flags in the FERSTAT register are readable and only writable to clear the flag.
Table 13-15. FERSTAT Field Descriptions
Field
Description
1
DFDIF
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
was attempted on a Flash block that was under a Flash command operation.(1) The DFDIF flag is cleared by
writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or an invalid Flash array read operation attempted
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation was attempted on a Flash block that was under a Flash command operation.1
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or an invalid Flash array read operation attempted
1. The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either
single fault or double fault but never both). A simultaneous access collision (read attempted while command running) is
indicated when both SFDIF and DFDIF flags are high.
13.3.2.9
P-Flash Protection Register (FPROT)
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
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128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x0008
7
6
R
5
4
3
2
1
0
RNV6
FPOPEN
FPHDIS
FPHS[1:0]
FPLDIS
FPLS[1:0]
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 13-13. Flash Protection Register (FPROT)
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see Section 13.3.2.9.1, “P-Flash Protection Restrictions,” and Table 13-20).
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see Table 13-3)
as indicated by reset condition ‘F’ in Figure 13-13. To change the P-Flash protection that will be loaded
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible
if any of the P-Flash sectors contained in the same P-Flash block are protected.
Table 13-16. FPROT Field Descriptions
Field
Description
7
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in Table 13-17 for the P-Flash block.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
corresponding FPHS and FPLS bits
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
corresponding FPHS and FPLS bits
6
RNV[6]
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
5
FPHDIS
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
4–3
FPHS[1:0]
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown inTable 13-18. The FPHS bits can only be written to while the FPHDIS bit is set.
2
FPLDIS
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory beginning with global address 0x3_8000.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
1–0
FPLS[1:0]
Flash Protection Lower Address Size — The FPLS bits determine the size of the protected/unprotected area
in P-Flash memory as shown in Table 13-19. The FPLS bits can only be written to while the FPLDIS bit is set.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-17. P-Flash Protection Function
Function(1)
FPOPEN
FPHDIS
FPLDIS
1
1
1
No P-Flash Protection
1
1
0
Protected Low Range
1
0
1
Protected High Range
1
0
0
Protected High and Low Ranges
0
1
1
Full P-Flash Memory Protected
0
1
0
Unprotected Low Range
0
0
1
Unprotected High Range
0
0
0
Unprotected High and Low Ranges
1. For range sizes, refer to Table 13-18 and Table 13-19.
Table 13-18. P-Flash Protection Higher Address Range
FPHS[1:0]
Global Address Range
Protected Size
00
0x3_F800–0x3_FFFF
2 Kbytes
01
0x3_F000–0x3_FFFF
4 Kbytes
10
0x3_E000–0x3_FFFF
8 Kbytes
11
0x3_C000–0x3_FFFF
16 Kbytes
Table 13-19. P-Flash Protection Lower Address Range
FPLS[1:0]
Global Address Range
Protected Size
00
0x3_8000–0x3_83FF
1 Kbyte
01
0x3_8000–0x3_87FF
2 Kbytes
10
0x3_8000–0x3_8FFF
4 Kbytes
11
0x3_8000–0x3_9FFF
8 Kbytes
All possible P-Flash protection scenarios are shown in Figure 13-14. Although the protection scheme is
loaded from the Flash memory at global address 0x3_FF0C during the reset sequence, it can be changed
by the user. The P-Flash protection scheme can be used by applications requiring reprogramming in single
chip mode while providing as much protection as possible if reprogramming is not required.
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FPHDIS = 1
FPLDIS = 1
FPHDIS = 1
FPLDIS = 0
FPHDIS = 0
FPLDIS = 1
FPHDIS = 0
FPLDIS = 0
7
6
5
4
3
2
1
0
Scenario
0x3_8000
0x3_FFFF
Scenario
FPHS[1:0]
FPLS[1:0]
FLASH START
FPOPEN = 1
128 KByte Flash Module (S12FTMRC128K1V1)
FPHS[1:0]
0x3_8000
FPOPEN = 0
FPLS[1:0]
FLASH START
0x3_FFFF
Unprotected region
Protected region with size
defined by FPLS
Protected region
not defined by FPLS, FPHS
Protected region with size
defined by FPHS
Figure 13-14. P-Flash Protection Scenarios
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128 KByte Flash Module (S12FTMRC128K1V1)
13.3.2.9.1
P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed. Table 13-20 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
Table 13-20. P-Flash Protection Scenario Transitions
To Protection Scenario(1)
From
Protection
Scenario
0
1
2
3
0
X
X
X
X
X
1
X
4
X
X
X
X
X
X
X
X
6
6
7
X
3
5
5
X
X
2
4
X
X
X
X
X
X
X
X
X
X
7
1. Allowed transitions marked with X, see Figure 13-14 for a definition of the scenarios.
13.3.2.10 D-Flash Protection Register (DFPROT)
The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
Offset Module Base + 0x0009
7
R
6
5
4
0
0
0
3
2
DPOPEN
1
0
F
F
DPS[3:0]
W
Reset
F
0
0
0
F
F
= Unimplemented or Reserved
Figure 13-15. D-Flash Protection Register (DFPROT)
The (unreserved) bits of the DFPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, the DFPROT register is loaded with the contents of the D-Flash protection byte
in the Flash configuration field at global address 0x3_FF0D located in P-Flash memory (see Table 13-3)
as indicated by reset condition F in Figure 13-15. To change the D-Flash protection that will be loaded
during the reset sequence, the P-Flash sector containing the D-Flash protection byte must be unprotected,
then the D-Flash protection byte must be programmed. If a double bit fault is detected while reading the
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128 KByte Flash Module (S12FTMRC128K1V1)
P-Flash phrase containing the D-Flash protection byte during the reset sequence, the DPOPEN bit will be
cleared and DPS bits will be set to leave the D-Flash memory fully protected.
Trying to alter data in any protected area in the D-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. Block erase of the D-Flash memory is not possible
if any of the D-Flash sectors are protected.
Table 13-21. DFPROT Field Descriptions
Field
Description
7
DPOPEN
D-Flash Protection Control
0 Enables D-Flash memory protection from program and erase with protected address range defined by DPS
bits
1 Disables D-Flash memory protection from program and erase
3–0
DPS[3:0]
D-Flash Protection Size — The DPS[3:0] bits determine the size of the protected area in the D-Flash memory
as shown in Table 13-22.
Table 13-22. D-Flash Protection Address Range
DPS[3:0]
Global Address Range
Protected Size
0000
0x0_4400 – 0x0_44FF
256 bytes
0001
0x0_4400 – 0x0_45FF
512 bytes
0010
0x0_4400 – 0x0_46FF
768 bytes
0011
0x0_4400 – 0x0_47FF
1024 bytes
0100
0x0_4400 – 0x0_48FF
1280 bytes
0101
0x0_4400 – 0x0_49FF
1536 bytes
0110
0x0_4400 – 0x0_4AFF
1792 bytes
0111
0x0_4400 – 0x0_4BFF
2048 bytes
1000
0x0_4400 – 0x0_4CFF
2304 bytes
1001
0x0_4400 – 0x0_4DFF
2560 bytes
1010
0x0_4400 – 0x0_4EFF
2816 bytes
1011
0x0_4400 – 0x0_4FFF
3072 bytes
1100
0x0_4400 – 0x0_50FF
3328 bytes
1101
0x0_4400 – 0x0_51FF
3584 bytes
1110
0x0_4400 – 0x0_52FF
3840 bytes
1111
0x0_4400 – 0x0_53FF
4096 bytes
13.3.2.11 Flash Common Command Object Register (FCCOB)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register.
Byte wide reads and writes are allowed to the FCCOB register.
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128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x000A
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[15:8]
W
Reset
0
0
0
0
Figure 13-16. Flash Common Command Object High Register (FCCOBHI)
Offset Module Base + 0x000B
7
6
5
4
3
2
1
0
0
0
0
0
R
CCOB[7:0]
W
Reset
0
0
0
0
Figure 13-17. Flash Common Command Object Low Register (FCCOBLO)
13.3.2.11.1 FCCOB - NVM Command Mode
NVM command mode uses the indexed FCCOB register to provide a command code and its relevant
parameters to the Memory Controller. The user first sets up all required FCCOB fields and then initiates
the command’s execution by writing a 1 to the CCIF bit in the FSTAT register (a 1 written by the user
clears the CCIF command completion flag to 0). When the user clears the CCIF bit in the FSTAT register
all FCCOB parameter fields are locked and cannot be changed by the user until the command completes
(as evidenced by the Memory Controller returning CCIF to 1). Some commands return information to the
FCCOB register array.
The generic format for the FCCOB parameter fields in NVM command mode is shown in Table 13-23.
The return values are available for reading after the CCIF flag in the FSTAT register has been returned to
1 by the Memory Controller. Writes to the unimplemented parameter fields (CCOBIX = 110 and CCOBIX
= 111) are ignored with reads from these fields returning 0x0000.
Table 13-23 shows the generic Flash command format. The high byte of the first word in the CCOB array
contains the command code, followed by the parameters for this specific Flash command. For details on
the FCCOB settings required by each command, see the Flash command descriptions in Section 13.4.5.
Table 13-23. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
FCMD[7:0] defining Flash command
LO
6’h0, Global address [17:16]
HI
Global address [15:8]
LO
Global address [7:0]
HI
Data 0 [15:8]
LO
Data 0 [7:0]
000
001
010
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-23. FCCOB - NVM Command Mode (Typical Usage)
CCOBIX[2:0]
Byte
FCCOB Parameter Fields (NVM Command Mode)
HI
Data 1 [15:8]
LO
Data 1 [7:0]
HI
Data 2 [15:8]
LO
Data 2 [7:0]
HI
Data 3 [15:8]
LO
Data 3 [7:0]
011
100
101
13.3.2.12 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000C
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-18. Flash Reserved1 Register (FRSV1)
All bits in the FRSV1 register read 0 and are not writable.
13.3.2.13 Flash Reserved2 Register (FRSV2)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000D
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-19. Flash Reserved2 Register (FRSV2)
All bits in the FRSV2 register read 0 and are not writable.
13.3.2.14 Flash Reserved3 Register (FRSV3)
This Flash register is reserved for factory testing.
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128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x000E
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-20. Flash Reserved3 Register (FRSV3)
All bits in the FRSV3 register read 0 and are not writable.
13.3.2.15 Flash Reserved4 Register (FRSV4)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000F
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-21. Flash Reserved4 Register (FRSV4)
All bits in the FRSV4 register read 0 and are not writable.
13.3.2.16 Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
R
3
2
1
0
F
F
F
F
NV[7:0]
W
Reset
F
F
F
F
= Unimplemented or Reserved
Figure 13-22. Flash Option Register (FOPT)
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 13-3) as indicated
by reset condition F in Figure 13-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-24. FOPT Field Descriptions
Field
Description
7–0
NV[7:0]
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper
use of the NV bits.
13.3.2.17 Flash Reserved5 Register (FRSV5)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0011
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-23. Flash Reserved5 Register (FRSV5)
All bits in the FRSV5 register read 0 and are not writable.
13.3.2.18 Flash Reserved6 Register (FRSV6)
This Flash register is reserved for factory testing.
Offset Module Base + 0x0012
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-24. Flash Reserved6 Register (FRSV6)
All bits in the FRSV6 register read 0 and are not writable.
13.3.2.19 Flash Reserved7 Register (FRSV7)
This Flash register is reserved for factory testing.
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128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x0013
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 13-25. Flash Reserved7 Register (FRSV7)
All bits in the FRSV7 register read 0 and are not writable.
13.4
Functional Description
13.4.1
Modes of Operation
The FTMRC128K1 module provides the modes of operation shown in Table 13-25. The operating mode
is determined by module-level inputs and affects the FCLKDIV, FCNFG, and DFPROT registers, Scratch
RAM writes, and the command set availability (see Table 13-27).
Table 13-25. Modes and Mode Control Inputs
Operating
Mode
13.4.2
FTMRC Input
mmc_mode_ss_t2
Normal:
0
Special:
1
IFR Version ID Word
The version ID word is stored in the IFR at address 0x0_40B6. The contents of the word are defined in
Table 13-26.
Table 13-26. IFR Version ID Fields
•
[15:4]
[3:0]
Reserved
VERNUM
VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111
meaning ‘none’.
13.4.3
Flash Command Operations
Flash command operations are used to modify Flash memory contents.
The next sections describe:
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128 KByte Flash Module (S12FTMRC128K1V1)
•
•
•
How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
BUSCLK for Flash program and erase command operations
The command write sequence used to set Flash command parameters and launch execution
Valid Flash commands available for execution
13.4.3.1
Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 13-7 shows recommended
values for the FDIV field based on BUSCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
13.4.3.2
Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 13.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
CAUTION
Writes to any Flash register must be avoided while a Flash command is
active (CCIF=0) to prevent corruption of Flash register contents and
Memory Controller behavior.
13.4.3.2.1
Define FCCOB Contents
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX
register (see Section 13.3.2.3).
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will
return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic
command write sequence is shown in Figure 13-26.
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128 KByte Flash Module (S12FTMRC128K1V1)
START
Read: FCLKDIV register
Clock Divider
Value Check
FDIV
Correct?
no
no
CCIF
Set?
Read: FSTAT register
yes
FCCOB
Availability Check
yes
Read: FSTAT register
Note: FCLKDIV must be
set after each reset
Write: FCLKDIV register
no
CCIF
Set?
yes
Results from previous Command
ACCERR/
FPVIOL
Set?
no
Access Error and
Protection Violation
Check
yes
Write: FSTAT register
Clear ACCERR/FPVIOL 0x30
Write to FCCOBIX register
to identify specific command
parameter to load.
Write to FCCOB register
to load required command parameter.
More
Parameters?
yes
no
Write: FSTAT register (to launch command)
Clear CCIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF Set?
no
yes
EXIT
Figure 13-26. Generic Flash Command Write Sequence Flowchart
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128 KByte Flash Module (S12FTMRC128K1V1)
13.4.3.3
Valid Flash Module Commands
Table 13-27. Flash Commands by Mode
Unsecured
FCMD
Command
NS
SS(2)
NS
(1)
(3)
SS(4)
0x01
Erase Verify All Blocks
∗
∗
∗
∗
0x02
Erase Verify Block
∗
∗
∗
∗
0x03
Erase Verify P-Flash Section
∗
∗
∗
0x04
Read Once
∗
∗
∗
0x06
Program P-Flash
∗
∗
∗
0x07
Program Once
∗
∗
∗
0x08
Erase All Blocks
0x09
Erase Flash Block
∗
∗
∗
0x0A
Erase P-Flash Sector
∗
∗
∗
0x0B
Unsecure Flash
0x0C
Verify Backdoor Access Key
∗
0x0D
Set User Margin Level
∗
0x0E
Set Field Margin Level
0x10
Erase Verify D-Flash Section
∗
∗
∗
0x11
Program D-Flash
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
0x12
Erase D-Flash Sector
1. Unsecured Normal Single Chip mode.
2. Unsecured Special Single Chip mode.
3. Secured Normal Single Chip mode.
4. Secured Special Single Chip mode.
13.4.3.4
Secured
P-Flash Commands
Table 13-28 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module.
Table 13-28. P-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
0x03
Erase Verify PFlash Section
Function on P-Flash Memory
Verify that all P-Flash (and D-Flash) blocks are erased.
Verify that a P-Flash block is erased.
Verify that a given number of words starting at the address provided are erased.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-28. P-Flash Commands
FCMD
Command
Function on P-Flash Memory
0x04
Read Once
Read a dedicated 64 byte field in the nonvolatile information register in P-Flash block that
was previously programmed using the Program Once command.
0x06
Program P-Flash
0x07
Program Once
Program a dedicated 64 byte field in the nonvolatile information register in P-Flash block
that is allowed to be programmed only once.
0x08
Erase All Blocks
Erase all P-Flash (and D-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to
launching the command.
0x09
Erase Flash Block
Erase a P-Flash (or D-Flash) block.
An erase of the full P-Flash block is only possible when FPLDIS, FPHDIS and FPOPEN
bits in the FPROT register are set prior to launching the command.
0x0A
Erase P-Flash
Sector
0x0B
Unsecure Flash
0x0C
Verify Backdoor
Access Key
Supports a method of releasing MCU security by verifying a set of security keys.
0x0D
Set User Margin
Level
Specifies a user margin read level for all P-Flash blocks.
0x0E
Set Field Margin
Level
Specifies a field margin read level for all P-Flash blocks (special modes only).
13.4.3.5
Program a phrase in a P-Flash block.
Erase all bytes in a P-Flash sector.
Supports a method of releasing MCU security by erasing all P-Flash (and D-Flash) blocks
and verifying that all P-Flash (and D-Flash) blocks are erased.
D-Flash Commands
Table 13-29 summarizes the valid D-Flash commands along with the effects of the commands on the DFlash block.
Table 13-29. D-Flash Commands
FCMD
Command
0x01
Erase Verify All
Blocks
0x02
Erase Verify Block
Function on D-Flash Memory
Verify that all D-Flash (and P-Flash) blocks are erased.
Verify that the D-Flash block is erased.
Erase all D-Flash (and P-Flash) blocks.
An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN
bits in the FPROT register and the DPOPEN bit in the DFPROT register are set prior to
launching the command.
0x08
Erase All Blocks
0x09
Erase Flash Block
0x0B
Unsecure Flash
0x0D
Set User Margin
Level
Specifies a user margin read level for the D-Flash block.
0x0E
Set Field Margin
Level
Specifies a field margin read level for the D-Flash block (special modes only).
Erase a D-Flash (or P-Flash) block.
An erase of the full D-Flash block is only possible when DPOPEN bit in the DFPROT
register is set prior to launching the command.
Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks
and verifying that all D-Flash (and P-Flash) blocks are erased.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-29. D-Flash Commands
FCMD
Command
0x10
Erase Verify DFlash Section
0x11
Program D-Flash
Program up to four words in the D-Flash block.
0x12
Erase D-Flash
Sector
Erase all bytes in a sector of the D-Flash block.
13.4.4
Function on D-Flash Memory
Verify that a given number of words starting at the address provided are erased.
Allowed Simultaneous P-Flash and D-Flash Operations
Only the operations marked ‘OK’ in Table 13-30 are permitted to be run simultaneously on the Program
Flash and Data Flash blocks. Some operations cannot be executed simultaneously because certain
hardware resources are shared by the two memories. The priority has been placed on permitting Program
Flash reads while program and erase operations execute on the Data Flash, providing read (P-Flash) while
write (D-Flash) functionality.
Table 13-30. Allowed P-Flash and D-Flash Simultaneous Operations
Data Flash
Margin
Read1
Program
Sector
Erase
Read
OK
OK
OK
Margin Read(1)
OK(2)
Program Flash
Read
Mass
Erase3
Program
Sector Erase
OK
OK
Mass Erase(3)
1. A ‘Margin Read’ is any read after executing the margin setting commands ‘Set
User Margin Level’ or ‘Set Field Margin Level’ with anything but the ‘normal’
level specified.
2. See the Note on margin settings in Section 13.4.5.12 and Section 13.4.5.13.
3. The ‘Mass Erase’ operations are commands ‘Erase All Blocks’ and ‘Erase
Flash Block’
13.4.5
Flash Command Description
This section provides details of all available Flash commands launched by a command write sequence. The
ACCERR bit in the FSTAT register will be set during the command write sequence if any of the following
illegal steps are performed, causing the command not to be processed by the Memory Controller:
• Starting any command write sequence that programs or erases Flash memory before initializing the
FCLKDIV register
• Writing an invalid command as part of the command write sequence
• For additional possible errors, refer to the error handling table provided for each command
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128 KByte Flash Module (S12FTMRC128K1V1)
If a Flash block is read during execution of an algorithm (CCIF = 0) on that same block, the read operation
will return invalid data. If the SFDIF or DFDIF flags were not previously set when the invalid read
operation occurred, both the SFDIF and DFDIF flags will be set.
If the ACCERR or FPVIOL bits are set in the FSTAT register, the user must clear these bits before starting
any command write sequence (see Section 13.3.2.7).
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
13.4.5.1
Erase Verify All Blocks Command
The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased.
Table 13-31. Erase Verify All Blocks Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x01
Not required
Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify
that the entire Flash memory space is erased. The CCIF flag will set after the Erase Verify All Blocks
operation has completed.
Table 13-32. Erase Verify All Blocks Command Error Handling
Register
Error Bit
ACCERR
FPVIOL
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
None
FSTAT
13.4.5.2
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
Erase Verify Block Command
The Erase Verify Block command allows the user to verify that an entire P-Flash or D-Flash block has been
erased. The FCCOB upper global address bits determine which block must be verified.
Table 13-33. Erase Verify Block Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x02
Global address [17:16] of the
Flash block to be verified.
Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that
the selected P-Flash or D-Flash block is erased. The CCIF flag will set after the Erase Verify Block
operation has completed.
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Table 13-34. Erase Verify Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if an invalid global address [17:16] is supplied
FSTAT
13.4.5.3
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
Erase Verify P-Flash Section Command
The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is
erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and
the number of phrases.
Table 13-35. Erase Verify P-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x03
Global address [17:16] of
a P-Flash block
001
Global address [15:0] of the first phrase to be verified
010
Number of phrases to be verified
Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will
verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash
Section operation has completed.
Table 13-36. Erase Verify P-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:0] is supplied
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
Set if the requested section crosses a 128 Kbyte boundary
FPVIOL
13.4.5.4
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
Read Once Command
The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the
nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once
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128 KByte Flash Module (S12FTMRC128K1V1)
command described in Section 13.4.5.6. The Read Once command must not be executed from the Flash
block containing the Program Once reserved field to avoid code runaway.
Table 13-37. Read Once Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x04
Not Required
001
Read Once phrase index (0x0000 - 0x0007)
010
Read Once word 0 value
011
Read Once word 1 value
100
Read Once word 2 value
101
Read Once word 3 value
Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the
FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid
phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the
Read Once command, any attempt to read addresses within P-Flash block will return invalid data.
8
Table 13-38. Read Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
ACCERR
Set if command not available in current mode (see Table 13-27)
Set if an invalid phrase index is supplied
FSTAT
FPVIOL
13.4.5.5
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
Program P-Flash Command
The Program P-Flash operation will program a previously erased phrase in the P-Flash memory using an
embedded algorithm.
CAUTION
A P-Flash phrase must be in the erased state before being programmed.
Cumulative programming of bits within a Flash phrase is not allowed.
Table 13-39. Program P-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x06
Global address [17:16] to
identify P-Flash block
001
Global address [15:0] of phrase location to be programmed(1)
010
Word 0 program value
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Table 13-39. Program P-Flash Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
011
Word 1 program value
100
Word 2 program value
101
Word 3 program value
1. Global address [2:0] must be 000
Upon clearing CCIF to launch the Program P-Flash command, the Memory Controller will program the
data words to the supplied global address and will then proceed to verify the data words read back as
expected. The CCIF flag will set after the Program P-Flash operation has completed.
Table 13-40. Program P-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:0] is supplied
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
FPVIOL
13.4.5.6
Set if the global address [17:0] points to a protected area
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
Program Once Command
The Program Once command restricts programming to a reserved 64 byte field (8 phrases) in the
nonvolatile information register located in P-Flash. The Program Once reserved field can be read using the
Read Once command as described in Section 13.4.5.4. The Program Once command must only be issued
once since the nonvolatile information register in P-Flash cannot be erased. The Program Once command
must not be executed from the Flash block containing the Program Once reserved field to avoid code
runaway.
Table 13-41. Program Once Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x07
Not Required
001
Program Once phrase index (0x0000 - 0x0007)
010
Program Once word 0 value
011
Program Once word 1 value
100
Program Once word 2 value
101
Program Once word 3 value
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128 KByte Flash Module (S12FTMRC128K1V1)
Upon clearing CCIF to launch the Program Once command, the Memory Controller first verifies that the
selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with
read back. The CCIF flag will remain clear, setting only after the Program Once operation has completed.
The reserved nonvolatile information register accessed by the Program Once command cannot be erased
and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index
values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program
Once command, any attempt to read addresses within P-Flash will return invalid data.
Table 13-42. Program Once Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 101 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid phrase index is supplied
Set if the requested phrase has already been programmed(1)
FSTAT
FPVIOL
MGSTAT1
None
Set if any errors have been encountered during the verify operation
Set if any non-correctable errors have been encountered during the verify
operation
1. If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command will
be allowed to execute again on that same phrase.
MGSTAT0
13.4.5.7
Erase All Blocks Command
The Erase All Blocks operation will erase the entire P-Flash and D-Flash memory space.
Table 13-43. Erase All Blocks Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x08
Not required
Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire
Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash
memory space was properly erased, security will be released. During the execution of this command
(CCIF=0) the user must not write to any Flash module register. The CCIF flag will set after the Erase All
Blocks operation has completed.
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Table 13-44. Erase All Blocks Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 13-27)
FPVIOL
FSTAT
13.4.5.8
Set if any area of the P-Flash or D-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
Erase Flash Block Command
The Erase Flash Block operation will erase all addresses in a P-Flash or D-Flash block.
Table 13-45. Erase Flash Block Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x09
Global address [17:16] to
identify Flash block
Global address [15:0] in Flash block to be erased
Upon clearing CCIF to launch the Erase Flash Block command, the Memory Controller will erase the
selected Flash block and verify that it is erased. The CCIF flag will set after the Erase Flash Block
operation has completed.
Table 13-46. Erase Flash Block Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if the supplied P-Flash address is not phrase-aligned or if the D-Flash
address is not word-aligned
FSTAT
FPVIOL
13.4.5.9
Set if an invalid global address [17:16] is supplied
Set if an area of the selected Flash block is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
Erase P-Flash Sector Command
The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-47. Erase P-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0A
Global address [17:16] to identify
P-Flash block to be erased
Global address [15:0] anywhere within the sector to be erased.
Refer to Section 13.1.2.1 for the P-Flash sector size.
Upon clearing CCIF to launch the Erase P-Flash Sector command, the Memory Controller will erase the
selected Flash sector and then verify that it is erased. The CCIF flag will be set after the Erase P-Flash
Sector operation has completed.
Table 13-48. Erase P-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:16] is supplied
Set if a misaligned phrase address is supplied (global address [2:0] != 000)
FSTAT
FPVIOL
Set if the selected P-Flash sector is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
13.4.5.10 Unsecure Flash Command
The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is
successful, will release security.
Table 13-49. Unsecure Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0B
Not required
Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire
P-Flash and D-Flash memory space and verify that it is erased. If the Memory Controller verifies that the
entire Flash memory space was properly erased, security will be released. If the erase verify is not
successful, the Unsecure Flash operation sets MGSTAT1 and terminates without changing the security
state. During the execution of this command (CCIF=0) the user must not write to any Flash module
register. The CCIF flag is set after the Unsecure Flash operation has completed.
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Table 13-50. Unsecure Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 000 at command launch
ACCERR
Set if command not available in current mode (see Table 13-27)
FPVIOL
FSTAT
Set if any area of the P-Flash or D-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
13.4.5.11 Verify Backdoor Access Key Command
The Verify Backdoor Access Key command will only execute if it is enabled by the KEYEN bits in the
FSEC register (see Table 13-9). The Verify Backdoor Access Key command releases security if usersupplied keys match those stored in the Flash security bytes of the Flash configuration field (see Table 133). The Verify Backdoor Access Key command must not be executed from the Flash block containing the
backdoor comparison key to avoid code runaway.
Table 13-51. Verify Backdoor Access Key Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x0C
Not required
001
Key 0
010
Key 1
011
Key 2
100
Key 3
Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will
check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory
Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the
Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash
configuration field with Key 0 compared to 0x3_FF00, etc. If the backdoor keys match, security will be
released. If the backdoor keys do not match, security is not released and all future attempts to execute the
Verify Backdoor Access Key command are aborted (set ACCERR) until a reset occurs. The CCIF flag is
set after the Verify Backdoor Access Key operation has completed.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-52. Verify Backdoor Access Key Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 100 at command launch
Set if an incorrect backdoor key is supplied
ACCERR
FSTAT
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section 13.3.2.2)
Set if the backdoor key has mismatched since the last reset
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
13.4.5.12 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of the P-Flash or D-Flash block.
Table 13-53. Set User Margin Level Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x0D
001
Global address [17:16] to identify the
Flash block
Margin level setting
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
NOTE
When the D-Flash block is targeted, the D-Flash user margin levels are
applied only to the D-Flash reads. However, when the P-Flash block is
targeted, the P-Flash user margin levels are applied to both P-Flash and DFlash reads. It is not possible to apply user margin levels to the P-Flash
block only.
Valid margin level settings for the Set User Margin Level command are defined in Table 13-54.
Table 13-54. Valid Set User Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
1. Read margin to the erased state
2. Read margin to the programmed state
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Table 13-55. Set User Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:16] is supplied
FSTAT
Set if an invalid margin level setting is supplied
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
NOTE
User margin levels can be used to check that Flash memory contents have
adequate margin for normal level read operations. If unexpected results are
encountered when checking Flash memory contents at user margin levels, a
potential loss of information has been detected.
13.4.5.13 Set Field Margin Level Command
The Set Field Margin Level command, valid in special modes only, causes the Memory Controller to set
the margin level specified for future read operations of the P-Flash or D-Flash block.
Table 13-56. Set Field Margin Level Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x0E
Global address [17:16] to identify the Flash
block
Margin level setting
Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the
field margin level for the targeted block and then set the CCIF flag.
NOTE
When the D-Flash block is targeted, the D-Flash field margin levels are
applied only to the D-Flash reads. However, when the P-Flash block is
targeted, the P-Flash field margin levels are applied to both P-Flash and DFlash reads. It is not possible to apply field margin levels to the P-Flash
block only.
Valid margin level settings for the Set Field Margin Level command are defined in Table 13-57.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-57. Valid Set Field Margin Level Settings
CCOB
(CCOBIX=001)
Level Description
0x0000
Return to Normal Level
0x0001
User Margin-1 Level(1)
0x0002
User Margin-0 Level(2)
0x0003
Field Margin-1 Level1
0x0004
Field Margin-0 Level2
1. Read margin to the erased state
2. Read margin to the programmed state
Table 13-58. Set Field Margin Level Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:16] is supplied
FSTAT
Set if an invalid margin level setting is supplied
FPVIOL
None
MGSTAT1
None
MGSTAT0
None
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at field
margin levels, the Flash memory contents should be erased and
reprogrammed.
13.4.5.14 Erase Verify D-Flash Section Command
The Erase Verify D-Flash Section command will verify that a section of code in the D-Flash is erased. The
Erase Verify D-Flash Section command defines the starting point of the data to be verified and the number
of words.
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-59. Erase Verify D-Flash Section Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
000
0x10
Global address [17:16] to
identify the D-Flash block
001
Global address [15:0] of the first word to be verified
010
Number of words to be verified
Upon clearing CCIF to launch the Erase Verify D-Flash Section command, the Memory Controller will
verify the selected section of D-Flash memory is erased. The CCIF flag will set after the Erase Verify DFlash Section operation has completed.
Table 13-60. Erase Verify D-Flash Section Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 010 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the requested section breaches the end of the D-Flash block
FPVIOL
None
MGSTAT1
Set if any errors have been encountered during the read
MGSTAT0
Set if any non-correctable errors have been encountered during the read
13.4.5.15 Program D-Flash Command
The Program D-Flash operation programs one to four previously erased words in the D-Flash block. The
Program D-Flash operation will confirm that the targeted location(s) were successfully programmed upon
completion.
CAUTION
A Flash word must be in the erased state before being programmed.
Cumulative programming of bits within a Flash word is not allowed.
Table 13-61. Program D-Flash Command FCCOB Requirements
CCOBIX[2:0]
000
FCCOB Parameters
0x11
Global address [17:16] to
identify the D-Flash block
001
Global address [15:0] of word to be programmed
010
Word 0 program value
011
Word 1 program value, if desired
100
Word 2 program value, if desired
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128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-61. Program D-Flash Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
101
Word 3 program value, if desired
Upon clearing CCIF to launch the Program D-Flash command, the user-supplied words will be transferred
to the Memory Controller and be programmed if the area is unprotected. The CCOBIX index value at
Program D-Flash command launch determines how many words will be programmed in the D-Flash block.
The CCIF flag is set when the operation has completed.
Table 13-62. Program D-Flash Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] < 010 at command launch
Set if CCOBIX[2:0] > 101 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
Set if the requested group of words breaches the end of the D-Flash block
FPVIOL
Set if the selected area of the D-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
13.4.5.16 Erase D-Flash Sector Command
The Erase D-Flash Sector operation will erase all addresses in a sector of the D-Flash block.
Table 13-63. Erase D-Flash Sector Command FCCOB Requirements
CCOBIX[2:0]
000
001
FCCOB Parameters
0x12
Global address [17:16] to identify
D-Flash block
Global address [15:0] anywhere within the sector to be erased.
See Section 13.1.2.2 for D-Flash sector size.
Upon clearing CCIF to launch the Erase D-Flash Sector command, the Memory Controller will erase the
selected Flash sector and verify that it is erased. The CCIF flag will set after the Erase D-Flash Sector
operation has completed.
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Table 13-64. Erase D-Flash Sector Command Error Handling
Register
Error Bit
Error Condition
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 13-27)
ACCERR
Set if an invalid global address [17:0] is supplied
Set if a misaligned word address is supplied (global address [0] != 0)
FSTAT
FPVIOL
13.4.6
Set if the selected area of the D-Flash memory is protected
MGSTAT1
Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify
operation
Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
Table 13-65. Flash Interrupt Sources
Interrupt Source
Global (CCR)
Mask
Interrupt Flag
Local Enable
CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
ECC Double Bit Fault on Flash Read
DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read
SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit
Flash Command Complete
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
13.4.6.1
Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to Section 13.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 13.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 13.3.2.7, “Flash
Status Register (FSTAT)”, and Section 13.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 13-27.
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128 KByte Flash Module (S12FTMRC128K1V1)
Flash Command Interrupt Request
CCIE
CCIF
DFDIE
DFDIF
Flash Error Interrupt Request
SFDIE
SFDIF
Figure 13-27. Flash Module Interrupts Implementation
13.4.7
Wait Mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see Section 13.4.6, “Interrupts”).
13.4.8
Stop Mode
If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation
will be completed before the CPU is allowed to enter stop mode.
13.5
Security
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see Table 13-10). During reset, the Flash module initializes the FSEC
register using data read from the security byte of the Flash configuration field at global address 0x3_FF0F.
The security state out of reset can be permanently changed by programming the security byte assuming
that the MCU is starting from a mode where the necessary P-Flash erase and program commands are
available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully
programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using Backdoor Key Access
• Unsecuring the MCU in Special Single Chip Mode using BDM
• Mode and Security Effects on Flash Command Availability
13.5.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the
contents of the backdoor keys (four 16-bit words programmed at addresses 0x3_FF00-0x3_FF07). If the
KEYEN[1:0] bits are in the enabled state (see Section 13.3.2.2), the Verify Backdoor Access Key
command (see Section 13.4.5.11) allows the user to present four prospective keys for comparison to the
keys stored in the Flash memory via the Memory Controller. If the keys presented in the Verify Backdoor
Access Key command match the backdoor keys stored in the Flash memory, the SEC bits in the FSEC
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128 KByte Flash Module (S12FTMRC128K1V1)
register (see Table 13-10) will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are
not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, P-Flash
memory and D-Flash memory will not be available for read access and will return invalid data.
The user code stored in the P-Flash memory must have a method of receiving the backdoor keys from an
external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state (see Section 13.3.2.2), the MCU can be unsecured by the
backdoor key access sequence described below:
1. Follow the command sequence for the Verify Backdoor Access Key command as explained in
Section 13.4.5.11
2. If the Verify Backdoor Access Key command is successful, the MCU is unsecured and the
SEC[1:0] bits in the FSEC register are forced to the unsecure state of 10
The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will
prohibit future use of the Verify Backdoor Access Key command. A reset of the MCU is the only method
to re-enable the Verify Backdoor Access Key command. The security as defined in the Flash security byte
(0x3_FF0F) is not changed by using the Verify Backdoor Access Key command sequence. The backdoor
keys stored in addresses 0x3_FF00-0x3_FF07 are unaffected by the Verify Backdoor Access Key
command sequence. The Verify Backdoor Access Key command sequence has no effect on the program
and erase protections defined in the Flash protection register, FPROT.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is
unsecured, the sector containing the Flash security byte can be erased and the Flash security byte can be
reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the
contents of the backdoor keys by programming addresses 0x3_FF00-0x3_FF07 in the Flash configuration
field.
13.5.2
Unsecuring the MCU in Special Single Chip Mode using BDM
A secured MCU can be unsecured in special single chip mode by using the following method to erase the
P-Flash and D-Flash memory:
1. Reset the MCU into special single chip mode
2. Delay while the BDM executes the Erase Verify All Blocks command write sequence to check if
the P-Flash and D-Flash memories are erased
3. Send BDM commands to disable protection in the P-Flash and D-Flash memory
4. Execute the Erase All Blocks command write sequence to erase the P-Flash and D-Flash memory
5. After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the
MCU into special single chip mode
6. Delay while the BDM executes the Erase Verify All Blocks command write sequence to verify that
the P-Flash and D-Flash memory are erased
If the P-Flash and D-Flash memory are verified as erased, the MCU will be unsecured. All BDM
commands will now be enabled and the Flash security byte may be programmed to the unsecure state by
continuing with the following steps:
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128 KByte Flash Module (S12FTMRC128K1V1)
7. Send BDM commands to execute the Program P-Flash command write sequence to program the
Flash security byte to the unsecured state
8. Reset the MCU
13.5.3
Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in Table 13-27.
13.6
Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to using built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash memory reads and access to most Flash registers are
possible when the hold is removed, writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers are
ignored. Completion of the reset sequence is marked by setting CCIF high which enables writes to the
FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
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Chapter 14
Timer Module (TIM16B8CV2) Block Description
Table 14-1. Revision History
Revision
Number
Revision Date
V02.04
1 Jul 2008
14.3.2.12/14488
14.3.2.13/14489
14.3.2.16/14492
14.4.2/14-497
14.4.3/14-497
- Revised flag clearing procedure, whereby TEN bit must be set when clearing
flags.
V02.05
9 Jul 2009
14.3.2.12/14488
14.3.2.13/14489
14.3.2.15/14491
14.3.2.16/14492
14.3.2.19/14494
14.4.2/14-497
14.4.3/14-497
- Revised flag clearing procedure, whereby TEN or PAEN bit must be set
when clearing flags.
- Add fomula to describe prescaler
V02.06
26 Aug 2009
14.1.2/14-474
14.3.2.15/14491
14.3.2.2/14-480
14.3.2.3/14-481
14.3.2.4/14-482
14.4.3/14-497
14.1
Sections
Affected
Description of Changes
- Correct typo: TSCR ->TSCR1
- Correct reference: Figure 1-25 -> Figure 1-31
- Add description, “a counter overflow when TTOV[7] is set”, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
Introduction
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The
input capture function is used to detect a selected transition edge and record the time. The output compare
function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator
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Timer Module (TIM16B8CV2) Block Description
is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares
timer channel 7 when in event mode.
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
14.1.1
Features
The TIM16B8CV2 includes these distinctive features:
• Eight input capture/output compare channels.
• Clock prescaling.
• 16-bit counter.
• 16-bit pulse accumulator.
14.1.2
Modes of Operation
Stop:
Timer is off because clocks are stopped.
Freeze:
Timer counter keep on running, unless TSFRZ in TSCR1 (0x0006) is set to 1.
Wait:
Counters keep on running, unless TSWAI in TSCR1 (0x0006) is set to 1.
Normal:
Timer counter keep on running, unless TEN in TSCR1 (0x0006) is cleared to 0.
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Timer Module (TIM16B8CV2) Block Description
14.1.3
Block Diagrams
Bus clock
Prescaler
16-bit Counter
Channel 0
Input capture
Output compare
Channel 1
Input capture
Output compare
Channel 2
Input capture
Output compare
Timer overflow
interrupt
Timer channel 0
interrupt
Channel 3
Input capture
Output compare
Registers
Channel 4
Input capture
Output compare
Channel 5
Input capture
Output compare
Timer channel 7
interrupt
PA overflow
interrupt
PA input
interrupt
Channel 6
Input capture
Output compare
16-bit
Pulse accumulator
Channel 7
Input capture
Output compare
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
Figure 14-1. TIM16B8CV2 Block Diagram
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Timer Module (TIM16B8CV2) Block Description
TIMCLK (Timer clock)
CLK1
CLK0
Intermodule Bus
Clock select
(PAMOD)
Edge detector
PT7
PACLK
PACLK / 256
PACLK / 65536
Prescaled clock
(PCLK)
4:1 MUX
Interrupt
PACNT
MUX
Divide by 64
M clock
Figure 14-2. 16-Bit Pulse Accumulator Block Diagram
16-bit Main Timer
PTn
Edge detector
Set CnF Interrupt
TCn Input Capture Reg.
Figure 14-3. Interrupt Flag Setting
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Timer Module (TIM16B8CV2) Block Description
PULSE
ACCUMULATOR
PAD
CHANNEL 7 OUTPUT COMPARE
OCPD
TEN
TIOS7
Figure 14-4. Channel 7 Output Compare/Pulse Accumulator Logic
14.2
External Signal Description
The TIM16B8CV2 module has a total of eight external pins.
14.2.1
IOC7 — Input Capture and Output Compare Channel 7 Pin
This pin serves as input capture or output compare for channel 7. This can also be configured as pulse
accumulator input.
14.2.2
IOC6 — Input Capture and Output Compare Channel 6 Pin
This pin serves as input capture or output compare for channel 6.
14.2.3
IOC5 — Input Capture and Output Compare Channel 5 Pin
This pin serves as input capture or output compare for channel 5.
14.2.4
IOC4 — Input Capture and Output Compare Channel 4 Pin
This pin serves as input capture or output compare for channel 4. Pin
14.2.5
IOC3 — Input Capture and Output Compare Channel 3 Pin
This pin serves as input capture or output compare for channel 3.
14.2.6
IOC2 — Input Capture and Output Compare Channel 2 Pin
This pin serves as input capture or output compare for channel 2.
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Timer Module (TIM16B8CV2) Block Description
14.2.7
IOC1 — Input Capture and Output Compare Channel 1 Pin
This pin serves as input capture or output compare for channel 1.
14.2.8
IOC0 — Input Capture and Output Compare Channel 0 Pin
This pin serves as input capture or output compare for channel 0.
NOTE
For the description of interrupts see Section 14.6, “Interrupts”.
14.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
14.3.1
Module Memory Map
The memory map for the TIM16B8CV2 module is given below in Figure 14-5. The address listed for each
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B8CV2 module and the address offset for each register.
14.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
TIOS
R
W
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0x0001
CFORC
R
W
0
FOC7
0
FOC6
0
FOC5
0
FOC4
0
FOC3
0
FOC2
0
FOC1
0
FOC0
0x0002
OC7M
R
W
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
0x0003
OC7D
R
W
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
0x0004
TCNTH
R
W
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
0x0005
TCNTL
R
W
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
= Unimplemented or Reserved
Figure 14-5. TIM16B8CV2 Register Summary (Sheet 1 of 3)
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Timer Module (TIM16B8CV2) Block Description
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0x0006
TSCR1
R
W
TEN
TSWAI
TSFRZ
TFFCA
PRNT
0x0007
TTOV
R
W
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
0x0008
TCTL1
R
W
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
0x0009
TCTL2
R
W
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
0x000A
TCTL3
R
W
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
0x000B
TCTL4
R
W
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
0x000C
TIE
R
W
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0x000D
TSCR2
R
W
TOI
0
0
0
TCRE
PR2
PR1
PR0
0x000E
TFLG1
R
W
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0x000F
TFLG2
R
W
TOF
0
0
0
0
0
0
0
R
W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
PAOVF
PAIF
0x0010–0x001F
TCxH–TCxL
0x0020
PACTL
R
W
0
0x0021
PAFLG
R
W
0
0x0022
PACNTH
R
PACNT15
W
PACNT14
PACNT13
PACNT12
PACNT11
PACNT10
PACNT9
PACNT8
0x0023
PACNTL
R
W
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
0x0024–0x002B
Reserved
R
W
PACNT7
= Unimplemented or Reserved
Figure 14-5. TIM16B8CV2 Register Summary (Sheet 2 of 3)
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Timer Module (TIM16B8CV2) Block Description
Register
Name
0x002C
OCPD
R
W
0x002D
R
0x002E
PTPSR
R
W
0x002F
Reserved
R
W
Bit 7
6
5
4
3
2
1
Bit 0
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
= Unimplemented or Reserved
Figure 14-5. TIM16B8CV2 Register Summary (Sheet 3 of 3)
14.3.2.1
Timer Input Capture/Output Compare Select (TIOS)
Module Base + 0x0000
7
6
5
4
3
2
1
0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-6. Timer Input Capture/Output Compare Select (TIOS)
Read: Anytime
Write: Anytime
Table 14-2. TIOS Field Descriptions
Field
7:0
IOS[7:0]
14.3.2.2
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
Timer Compare Force Register (CFORC)
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
0
0
0
0
0
0
0
0
Reset
Figure 14-7. Timer Compare Force Register (CFORC)
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Timer Module (TIM16B8CV2) Block Description
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Table 14-3. CFORC Field Descriptions
Field
Description
7:0
FOC[7:0]
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare
on channel 7, overrides any channel 6:0 compares. If forced output compare on any channel occurs at the
same time as the successful output compare then forced output compare action will take precedence and
interrupt flag won’t get set.
14.3.2.3
Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
7
6
5
4
3
2
1
0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-8. Output Compare 7 Mask Register (OC7M)
Read: Anytime
Write: Anytime
Table 14-4. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a channel 7 event, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
channel 7 event.
Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to
be transferred from the output compare 7 data register to the timer port.
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Timer Module (TIM16B8CV2) Block Description
14.3.2.4
Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
7
6
5
4
3
2
1
0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-9. Output Compare 7 Data Register (OC7D)
Read: Anytime
Write: Anytime
Table 14-5. OC7D Field Descriptions
Field
Description
7:0
OC7D[7:0]
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
14.3.2.5
Timer Count Register (TCNT)
Module Base + 0x0004
15
14
13
12
11
10
9
9
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-10. Timer Count Register High (TCNTH)
Module Base + 0x0005
7
6
5
4
3
2
1
0
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-11. Timer Count Register Low (TCNTL)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
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Timer Module (TIM16B8CV2) Block Description
Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
14.3.2.6
Timer System Control Register 1 (TSCR1)
Module Base + 0x0006
7
6
5
4
3
TEN
TSWAI
TSFRZ
TFFCA
PRNT
0
0
0
0
0
R
2
1
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-12. Timer System Control Register 1 (TSCR1)
Read: Anytime
Write: Anytime
Table 14-6. TSCR1 Field Descriptions
Field
7
TEN
Description
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is
generated by the timer prescaler.
6
TSWAI
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU
out of wait.
TSWAI also affects pulse accumulator.
5
TSFRZ
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
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Timer Module (TIM16B8CV2) Block Description
Table 14-6. TSCR1 Field Descriptions (continued)
Field
Description
4
TFFCA
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF flags in the PAFLG register (0x0021). This has the advantage of eliminating software
overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to
unintended accesses.
3
PRNT
Precision Timer
0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection.
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits.
This bit is writable only once out of reset.
14.3.2.7
Timer Toggle On Overflow Register 1 (TTOV)
Module Base + 0x0007
7
6
5
4
3
2
1
0
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-13. Timer Toggle On Overflow Register 1 (TTOV)
Read: Anytime
Write: Anytime
Table 14-7. TTOV Field Descriptions
Field
Description
7:0
TOV[7:0]
Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override
events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
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Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
14.3.2.8
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
7
6
5
4
3
2
1
0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-14. Timer Control Register 1 (TCTL1)
Module Base + 0x0009
7
6
5
4
3
2
1
0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-15. Timer Control Register 2 (TCTL2)
Read: Anytime
Write: Anytime
Table 14-8. TCTL1/TCTL2 Field Descriptions
Field
Description
7:0
OMx
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
an output line to be driven by an OCx the OCPDx must be cleared.
7:0
OLx
Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
an output line to be driven by an OCx the OCPDx must be cleared.
Table 14-9. Compare Result Output Action
OMx
OLx
Action
0
0
No output compare
action on the timer output signal
0
1
Toggle OCx output line
1
0
Clear OCx output line to zero
1
1
Set OCx output line to one
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
485
Timer Module (TIM16B8CV2) Block Description
To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0
respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the
OC7M register must also be cleared.
14.3.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
Module Base + 0x000A
7
6
5
4
3
2
1
0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-16. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
7
6
5
4
3
2
1
0
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-17. Timer Control Register 4 (TCTL4)
Read: Anytime
Write: Anytime.
Table 14-10. TCTL3/TCTL4 Field Descriptions
Field
7:0
EDGnB
EDGnA
Description
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 14-11. Edge Detector Circuit Configuration
EDGnB
EDGnA
Configuration
0
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
1
Capture on any edge (rising or falling)
S12P-Family Reference Manual, Rev. 1.13
486
Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
14.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-18. Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 14-12. TIE Field Descriptions
Field
Description
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
14.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
R
6
5
4
0
0
0
TOI
3
2
1
0
TCRE
PR2
PR1
PR0
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 14-19. Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
487
Timer Module (TIM16B8CV2) Block Description
Table 14-13. TSCR2 Field Descriptions
Field
7
TOI
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
3
TCRE
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000.
2
PR[2:0]
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 14-14.
Table 14-14. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
6
5
4
3
2
1
0
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
Table 14-15. TRLG1 Field Descriptions
Field
Description
7:0
C[7:0]F
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
14.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TOF
W
Reset
0
Unimplemented or Reserved
Figure 14-21. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 14-16. TRLG2 Field Descriptions
Field
Description
7
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one
(See also TCRE control bit explanation.)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
489
Timer Module (TIM16B8CV2) Block Description
14.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7
(TCxH and TCxL)
Module Base + 0x0010 = TC0H
0x0012 = TC1H
0x0014 = TC2H
0x0016 = TC3H
0x0018 = TC4H
0x001A = TC5H
0x001C = TC6H
0x001E = TC7H
15
14
13
12
11
10
9
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-22. Timer Input Capture/Output Compare Register x High (TCxH)
Module Base + 0x0011 = TC0L
0x0013 = TC1L
0x0015 = TC2L
0x0017 = TC3L
0x0019 = TC4L
0x001B = TC5L
0x001D = TC6L
0x001F = TC7L
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-23. Timer Input Capture/Output Compare Register x Low (TCxL)
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
14.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
Module Base + 0x0020
7
R
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
0
0
0
W
Reset
0
Unimplemented or Reserved
Figure 14-24. 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Table 14-17. PACTL Field Descriptions
Field
6
PAEN
Description
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
5
PAMOD
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table 14-18.
0 Event counter mode.
1 Gated time accumulation mode.
4
PEDGE
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See Table 14-18.
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
3:2
CLK[1:0]
Clock Select Bits — Refer to Table 14-19.
1
PAOVI
0
PAI
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
491
Timer Module (TIM16B8CV2) Block Description
Table 14-18. Pin Action
PAMOD
PEDGE
Pin Action
0
0
Falling edge
0
1
Rising edge
1
0
Div. by 64 clock enabled with pin high level
1
1
Div. by 64 clock enabled with pin low level
NOTE
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
Table 14-19. Timer Clock Selection
CLK1
CLK0
Timer Clock
0
0
Use timer prescaler clock as timer counter clock
0
1
Use PACLK as input to timer counter clock
1
0
Use PACLK/256 as timer counter clock frequency
1
1
Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer Figure 14-30.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
14.3.2.16 Pulse Accumulator Flag Register (PAFLG)
Module Base + 0x0021
R
7
6
5
4
3
2
0
0
0
0
0
0
1
0
PAOVF
PAIF
0
0
W
Reset
0
0
0
0
0
0
Unimplemented or Reserved
Figure 14-25. Pulse Accumulator Flag Register (PAFLG)
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while
clearing these bits.
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
Table 14-20. PAFLG Field Descriptions
Field
Description
1
PAOVF
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one.
0
PAIF
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one. Any access to the PACNT register will clear all the flags in this register when TFFCA
bit in register TSCR(0x0006) is set.
14.3.2.17 Pulse Accumulators Count Registers (PACNT)
Module Base + 0x0022
15
14
13
12
11
10
9
0
PACNT15
PACNT14
PACNT13
PACNT12
PACNT11
PACNT10
PACNT9
PACNT8
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-26. Pulse Accumulator Count Register High (PACNTH)
Module Base + 0x0023
7
6
5
4
3
2
1
0
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-27. Pulse Accumulator Count Register Low (PACNTL)
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an active
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
493
Timer Module (TIM16B8CV2) Block Description
14.3.2.18 Output Compare Pin Disconnect Register(OCPD)
Module Base + 0x002C
7
6
5
4
3
2
1
0
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-28. Ouput Compare Pin Disconnect Register (OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-21. OCPD Field Description
Field
OCPD[7:0}
Description
Output Compare Pin Disconnect Bits
0 Enables the timer channel port. Ouptut Compare action will occur on the channel pin. These bits do not affect
the input capture or pulse accumulator functions
1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output
compare flag still become set .
14.3.2.19 Precision Timer Prescaler Select Register (PTPSR)
Module Base + 0x002E
7
6
5
4
3
2
1
0
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 14-29. Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
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Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
Table 14-22. PTPSR Field Descriptions
Field
Description
7:0
PTPS[7:0]
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
These are effective only when the PRNT bit of TSCR1 is set to 1. Table 14-23 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:
PRNT = 1 : Prescaler = PTPS[7:0] + 1
Table 14-23. Precision Timer Prescaler Selection Examples when PRNT = 1
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
Prescale
Factor
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
4
0
0
0
0
0
1
0
0
5
0
0
0
0
0
1
0
1
6
0
0
0
0
0
1
1
0
7
0
0
0
0
0
1
1
1
8
0
0
0
0
1
1
1
1
16
0
0
0
1
1
1
1
1
32
0
0
1
1
1
1
1
1
64
0
1
1
1
1
1
1
1
128
1
1
1
1
1
1
1
1
256
14.4
Functional Description
This section provides a complete functional description of the timer TIM16B8CV2 block. Please refer to
the detailed timer block diagram in Figure 14-30 as necessary.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
495
Timer Module (TIM16B8CV2) Block Description
Bus Clock
CLK[1:0]
PR[2:1:0]
channel 7 output
compare
PACLK
PACLK/256
PACLK/65536
MUX
TCRE
PRESCALER
CxI
TCNT(hi):TCNT(lo)
CxF
CLEAR COUNTER
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOI
TE
TOF
CHANNEL 0
16-BIT COMPARATOR
OM:OL0
TC0
EDG0A
C0F
C0F
EDGE
DETECT
EDG0B
CH. 0 CAPTURE
IOC0 PIN
LOGIC CH. 0COMPARE
TOV0
IOC0 PIN
IOC0
CHANNEL 1
16-BIT COMPARATOR
EDG1A
C1F
C1F
OM:OL1
TC1
EDGE
DETECT
EDG1B
CH. 1 CAPTURE
IOC1 PIN
LOGIC CH. 1 COMPARE
TOV1
IOC1 PIN
IOC1
CHANNEL2
CHANNEL7
16-BIT COMPARATOR
TC7
OM:OL7
EDG7A
EDGE
DETECT
EDG7B
PAOVF
C7F
C7F
PACNT(hi):PACNT(lo)
TOV7
IOC7
PEDGE
PAE
PACLK/65536
CH.7 CAPTURE
IOC7 PIN PA INPUT
LOGIC CH. 7 COMPARE IOC7 PIN
EDGE
DETECT
16-BIT COUNTER
PACLK
PACLK/256
PAMOD
INTERRUPT
REQUEST
INTERRUPT
LOGIC
PAIF
DIVIDE-BY-64
PAOVI
PAI
PAOVF
PAIF
Bus Clock
PAOVF
PAOVI
Figure 14-30. Detailed Timer Block Diagram
14.4.1
Prescaler
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
S12P-Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
Timer Module (TIM16B8CV2) Block Description
The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system
control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,
64 and 128 when the PRNT bit in TSCR1 is disabled.
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this
case, it is possible to set additional prescaler settings for the main timer counter in the present timer by
using PTPSR[7:0] bits of PTPSR register.
14.4.2
Input Capture
Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The
input capture function captures the time at which an external event occurs. When an active edge occurs on
the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel
registers, TCx.
The minimum pulse width for the input capture input is greater than two bus clocks.
An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt
requests. Timer module or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of
PACTL regsiter must be set to one) while clearing CxF (writing one to CxF).
14.4.3
Output Compare
Setting the I/O select bit, IOSx, configures channel x as an output compare channel. The output compare
function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the
timer counter reaches the value in the channel registers of an output compare channel, the timer can set,
clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on
channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. Timer module
or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of PACTL regsiter must be set
to one) while clearing CxF (writing one to CxF).
The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both
OMx and OLx results in no output compare action on the output compare channel pin.
Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output
compare does not set the channel flag.
A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare
on channel 7, overrides output compares on all other output compare channels. The output compare 7 mask
register masks the bits in the output compare 7 data register. The timer counter reset enable bit, TCRE,
enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the
timer counter even if the IOC7 pin is being used as the pulse accumulator input.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is
stored in an internal latch. When the pin becomes available for general-purpose output, the last value
written to the bit appears at the pin.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
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Timer Module (TIM16B8CV2) Block Description
14.4.3.1
OC Channel Initialization
Internal register whose output drives OCx can be programmed before timer drives OCx. The desired state
can be programmed to this Internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN
bits set to one. Setting OCPDx to zero allows Interal register to drive the programmed state to OCx. This
allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set
to zero.
14.4.4
Pulse Accumulator
The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes:
Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI.
Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the
mode of operation.
The minimum pulse width for the PAI input is greater than two bus clocks.
14.4.5
Event Counter Mode
Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7
pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to
increment the count.
NOTE
The PACNT input and timer channel 7 use the same pin IOC7. To use the
IOC7, disconnect it from the output logic by clearing the channel 7 output
mode and output level bits, OM7 and OL7. Also clear the channel 7 output
compare 7 mask bit, OC7M7.
The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin
since the last reset.
The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator
overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests.
NOTE
The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.
14.4.6
Gated Time Accumulation Mode
Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.
The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to
generate interrupt requests.
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Timer Module (TIM16B8CV2) Block Description
The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
14.5
Resets
The reset state of each individual bit is listed within Section 14.3, “Memory Map and Register Definition”
which details the registers and their bit fields.
14.6
Interrupts
This section describes interrupts originated by the TIM16B8CV2 block. Table 14-24 lists the interrupts
generated by the TIM16B8CV2 to communicate with the MCU.
Table 14-24. TIM16B8CV1 Interrupts
Offset
(1)
Vector1
Priority1
Source
Description
C[7:0]F
—
—
—
Timer Channel 7–0
Active high timer channel interrupts 7–0
PAOVI
—
—
—
Pulse Accumulator
Input
Active high pulse accumulator input interrupt
PAOVF
—
—
—
Pulse Accumulator
Overflow
Pulse accumulator overflow interrupt
—
—
—
Timer Overflow
Timer Overflow interrupt
Interrupt
TOF
1. Chip Dependent.
The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
14.6.1
Channel [7:0] Interrupt (C[7:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be
serviced by the system controller.
14.6.2
Pulse Accumulator Input Interrupt (PAOVI)
This active high output will be asserted by the module to request a timer pulse accumulator input interrupt
to be serviced by the system controller.
14.6.3
Pulse Accumulator Overflow Interrupt (PAOVF)
This active high output will be asserted by the module to request a timer pulse accumulator overflow
interrupt to be serviced by the system controller.
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Timer Module (TIM16B8CV2) Block Description
14.6.4
Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt to be serviced
by the system controller.
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Appendix A
Electrical Characteristics
A.1
General
This supplement contains the most accurate electrical information for the MC9S12P-Family
microcontroller available at the time of publication.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE
This classification is shown in the column labeled “C” in the parameter
tables where appropriate.
P:
C:
T:
D:
A.1.2
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
Those parameters are derived mainly from simulations.
Power Supply
The VDDA, VSSA pin pairs supply the A/D converter and parts of the internal voltage regulator.
The VDDX, VSSX pin pairs [2:1] supply the I/O pins.
VDDR supplies the internal voltage regulator.
All VDDX pins are internally connected by metal.
All VSSX pins are internally connected by metal.
VDDA, VDDX and VSSA, VSSX are connected by diodes for ESD protection.
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Electrical Characteristics
NOTE
In the following context VDD35 is used for either VDDA, VDDR, and
VDDX; VSS35 is used for either VSSA and VSSX unless otherwise noted.
IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and
VDDR pins.
A.1.3
Pins
There are four groups of functional pins.
A.1.3.1
I/O Pins
The I/O pins have a level in the range of 3.15V to 5.5V. This class of pins is comprised of all port I/O pins,
the analog inputs, BKGD and the RESET pins. Some functionality may be disabled.
A.1.3.2
Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3
Oscillator
The pins EXTAL, XTAL dedicated to the oscillator have a nominal 1.8V level.
A.1.3.4
TEST
This pin is used for production testing only. The TEST pin must be tied to ground in all applications.
A.1.4
Current Injection
Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD35) is greater than IDD35,
the injection current may flow out of VDD35 and could result in external power supply going out of
regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This
will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if
clock rate is very low which would reduce overall power consumption.
A.1.5
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35).
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Electrical Characteristics
Table A-1. Absolute Maximum Ratings(1)
Num
Rating
Symbol
Min
Max
Unit
1
I/O, regulator and analog supply voltage
VDD35
–0.3
6.0
V
2
Voltage difference VDDX to VDDA
∆VDDX
–6.0
0.3
V
3
Voltage difference VSSX to VSSA
∆VSSX
–0.3
0.3
V
4
Digital I/O input voltage
VIN
–0.3
6.0
V
5
Analog reference
VRH, VRL
–0.3
6.0
V
6
EXTAL, XTAL
VILV
–0.3
2.16
V
7
Instantaneous maximum current
Single pin limit for all digital I/O pins(2)
I
–25
+25
mA
8
Instantaneous maximum current
Single pin limit for EXTAL, XTAL
I
–25
+25
mA
–65
155
°C
D
DL
9
Storage temperature range
Tstg
1. Beyond absolute maximum ratings device might be damaged.
2. All digital I/O pins are internally clamped to VSSX and VDDX, or VSSA and VDDA.
A.1.6
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade
integrated circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
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Electrical Characteristics
Table A-2. ESD and Latch-up Test Conditions
Model
Description
Human Body
Latch-up
Symbol
Value
Unit
Series resistance
R1
1500
Ohm
Storage capacitance
C
100
pF
Number of pulse per pin
Positive
Negative
—
—
3
3
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Table A-3. ESD and Latch-Up Protection Characteristics
Num
C
1
C
2
3
4
A.1.7
Symbol
Min
Max
Unit
Human Body Model (HBM)
VHBM
2000
—
V
C
Charge Device Model (CDM)
VCDM
500
—
V
C
Latch-up current at TA = 125°C
Positive
Negative
ILAT
+100
–100
—
—
Latch-up current at TA = 27°C
Positive
Negative
ILAT
+200
–200
—
—
C
Rating
mA
mA
Operating Conditions
This section describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE
Please refer to the temperature rating of the device (C, V, M) with regards to
the ambient temperature TA and the junction temperature TJ. For power
dissipation calculations refer to Section A.1.8, “Power Dissipation and
Thermal Characteristics”.
Table A-4. Operating Conditions
Rating
Symbol
Min
Typ
Max
Unit
I/O, regulator and analog supply voltage
VDD35
3.13
5
5.5
V
Voltage difference VDDX to VDDA
∆VDDX
Voltage difference VDDR to VDDX
∆VDDR
Voltage difference VSSX to VSSA
∆VSSX
Voltage difference VSS3 , VSSPLL to VSSX
∆VSS
-0.1
0
0.1
V
Digital logic supply voltage
VDD
1.72
1.8
1.98
V
refer to Table A-14
-0.1
0
0.1
V
refer to Table A-14
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Table A-4. Operating Conditions
Oscillator
fosc
4
—
16
MHz
Bus frequency
fbus
0.5
—
32
MHz
Temperature Option C
Operating junction temperature range
Operating ambient temperature range(1)
TJ
TA
–40
–40
—
27
105
85
Temperature Option V
Operating junction temperature range
Operating ambient temperature range1
TJ
TA
–40
–40
—
27
125
105
°C
°C
Temperature Option M
°C
Operating junction temperature range
TJ
–40
—
150
Operating ambient temperature range1
TA
–40
27
125
1. Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between
ambient temperature TA and device junction temperature TJ.
NOTE
Operation is guaranteed when powering down until low voltage reset
assertion.
A.1.8
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
T
T
T
J
= Junction Temperature, [°C ]
A
= Ambient Temperature, [°C ]
P
D
Θ
J
= T + (P • Θ )
A
D
JA
= Total Chip Power Dissipation, [W]
= Package Thermal Resistance, [°C/W]
JA
The total power dissipation can be calculated from:
P
P
D
= P
INT
+P
IO
= Chip Internal Power Dissipation, [W]
2
P
=
R
⋅I
IO
DSON IO i
i
INT
∑
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Electrical Characteristics
PIO is the sum of all output currents on I/O ports associated with VDDX, whereby
R
R
V
OL
= ------------ ;for outputs driven low
DSON
I
OL
V
–V
DD35
OH
= -------------------------------------- ;for outputs driven high
DSON
I
OH
P
INT
= I
DDR
⋅V
DDR
+I
DDA
⋅V
DDA
Table A-5. Thermal Package Characteristics(1)
Num
C
Rating
Symbol
Min
Typ
Max
Unit
QFN 48
1
D
Thermal resistance QFN 48, single sided PCB(2)
θJA
—
—
82
°C/W
2
D
Thermal resistance QFN 48, double sided PCB
with 2 internal planes(3)
θJA
—
—
28
°C/W
3
D
Junction to Board QFN 48
θJB
—
—
11
°C/W
4
D
4
Junction to Case QFN 48
θJC
—
—
1.4
°C/W
5
D
Junction to Case (Bottom) QFN 485
ΨJT
—
—
4
°C/W
2
QFP 80
6
D
Thermal resistance QFP 80, single sided PCB
θJA
—
—
56
°C/W
7
D
Thermal resistance QFP 80, double sided PCB
with 2 internal planes3
θJA
—
—
43
°C/W
8
D
Junction to Board QFP 80
θJB
—
—
28
°C/W
9
D
Junction to Case QFP 80(4)
θJC
—
—
19
°C/W
10
D
Junction to Package Top QFP 80(5)
ΨJT
—
—
5
°C/W
LQFP 64
11
D
Thermal resistance LQFP 64, single sided PCB2
θJA
—
—
70
°C/W
12
D
Thermal resistance LQFP 64, double sided PCB
with 2 internal planes3
θJA
—
—
52
°C/W
13
D
Junction to Board LQFP 64
θJB
—
—
35
°C/W
14
D
Junction to Case LQFP 64(6)
θJC
—
—
17
°C/W
(7)
ΨJT
—
—
3
°C/W
15
D Junction to Package Top LQFP 64
1. The values for thermal resistance are achieved by package simulations
2. Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-2 in a
horizontal configuration in natural convection.
3. Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-7 in a
horizontal configuration in natural convection.
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Electrical Characteristics
4. Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with
the cold plate temperature used as the “case” temperature. This basic cold plate measurement technique is described by MILSTD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is
being used with a heat sink.
5. Thermal characterization parameter ΨJT is the “resistance” from junction to reference point thermocouple on top center of the
case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in a steady state customer
enviroment.
6. Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with
the cold plate temperature used as the “case” temperature. This basic cold plate measurement technique is described by MILSTD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is
being used with a heat sink.
7. Thermal characterization parameter ΨJT is the “resistance” from junction to reference point thermocouple on top center of the
case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in a steady state customer
enviroment.
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Electrical Characteristics
A.1.9
I/O Characteristics
This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins.
Table A-6. 3.3-V I/O Characteristics
ALL 3.3V RANGE I/O PARAMETERS ARE SUBJECT TO CHANGE FOLLOWING CHARACTERIZATION
Conditions are 3.15 V < VDD35 < 3.6 V junction temperature from –40°C to +150°C, unless otherwise noted
I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins.
Num C
Symbol
Min
Typ
Max
Unit
P Input high voltage
VIH
0.65*VDD35
—
—
V
T Input high voltage
VIH
—
—
VDD35 + 0.3
V
P Input low voltage
VIL
—
—
0.35*VDD35
V
T Input low voltage
VIL
VSS35 – 0.3
—
—
V
3
C Input hysteresis
VHYS
4
Input leakage current (pins in high impedance input
mode)(1) Vin = VDD35 or VSS35
P M temperature range –40°C to +150°C
C V temperature range –40°C to +125°C
C C temperature range –40°C to +105°C
1
2
Rating
250
mV
µA
I
in
–1.00
-0.75
-0.50
—
—
—
1.00
0.75
0.50
5
C Output high voltage (pins in output mode)
Partial drive IOH = –0.75 mA
V
OH
VDD35 – 0.4
—
—
V
6
P Output high voltage (pins in output mode)
Full drive IOH = –4 mA
VOH
VDD35 – 0.4
—
—
V
7
C Output low voltage (pins in output mode)
Partial Drive IOL = +0.9 mA
VOL
—
—
0.4
V
8
P Output low voltage (pins in output mode)
Full Drive IOL = +4.75 mA
V
—
—
0.4
V
9
P Internal pull up resistance
VIH min > input voltage > VIL max
RPUL
25
—
50
KΩ
10
P Internal pull down resistance
VIH min > input voltage > VIL max
RPDH
25
—
50
KΩ
11
D Input capacitance
Cin
—
6
—
pF
T Injection current
Single pin limit
Total device limit, sum of all injected currents
IICS
IICP
–2.5
–25
P Port J, P interrupt input pulse filtered (STOP)(3)
tPULSE
—
—
3
µs
12
13
OL
(2)
3
—
mA
2.5
25
14
P Port J, P interrupt input pulse passed (STOP)
tPULSE
10
—
—
µs
15
D Port J, P interrupt input pulse filtered (STOP)
tPULSE
—
—
3
tcyc
16
D Port J, P interrupt input pulse passed (STOP)
tPULSE
4
—
—
tcyc
PWIRQ
1
—
—
tcyc
17 D IRQ pulse width, edge-sensitive mode (STOP)
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each
8°C to 12 C° in the temperature range from 50°C to 125°C.
2. Refer to Section A.1.4, “Current Injection” for more details
3. Parameter only applies in stop or pseudo stop mode.
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Table A-7. 5-V I/O Characteristics
Conditions are 4.5 V < VDD35 < 5.5 V junction temperature from –40°C to +150°C, unless otherwise noted
I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins.
Num C
1
Rating
Symbol
Min
Typ
Max
Unit
0.65*VDD35
—
—
V
P Input high voltage
V
T Input high voltage
VIH
—
—
VDD35 + 0.3
V
P Input low voltage
VIL
—
—
0.35*VDD35
V
T Input low voltage
VIL
VSS35 – 0.3
—
—
V
3
C Input hysteresis
VHYS
250
—
mV
4
Input leakage current (pins in high impedance input
mode)(1) Vin = VDD35 or VSS35
P M temperature range –40°C to +150°C
C V temperature range –40°C to +125°C
C C temperature range –40°C to +105°C
2
IH
I
µA
in
–1.00
-0.75
-0.50
—
—
—
1.00
0.75
0.50
5
C Output high voltage (pins in output mode)
Partial drive IOH = –2 mA
V
OH
VDD35 – 0.8
—
—
V
6
P Output high voltage (pins in output mode)
Full drive IOH = –10 mA
VOH
VDD35 – 0.8
—
—
V
7
C Output low voltage (pins in output mode)
Partial drive IOL = +2 mA
VOL
—
—
0.8
V
8
P Output low voltage (pins in output mode)
Full drive IOL = +10 mA
V
—
—
0.8
V
9
P Internal pull up resistance
VIH min > input voltage > VIL max
RPUL
25
—
50
KΩ
10
P Internal pull down resistance
VIH min > input voltage > VIL max
RPDH
25
—
50
KΩ
11
D Input capacitance
Cin
—
6
—
pF
IICS
IICP
–2.5
–25
tPULSE
—
—
3
µs
12
13
OL
(2)
T Injection current
Single pin limit
Total device Limit, sum of all injected currents
P Port J, P interrupt input pulse filtered (STOP)(3)
3
—
mA
2.5
25
14
P Port J, P interrupt input pulse passed (STOP)
tPULSE
10
—
—
µs
15
D Port J, P interrupt input pulse filtered (STOP)
tPULSE
—
—
3
tcyc
16
D Port J, P interrupt input pulse passed (STOP)
tPULSE
4
—
—
tcyc
PWIRQ
1
—
—
tcyc
17 D IRQ pulse width, edge-sensitive mode (STOP)
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each
8°C to 12 C° in the temperature range from 50°C to 125°C.
2. Refer to Section A.1.4, “Current Injection” for more details
3. Parameter only applies in stop or pseudo stop mode.
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Electrical Characteristics
A.1.10
Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1
Measurement Conditions
Run current is measured on VDDR pin. It does not include the current to drive external loads. Unless
otherwise noted the currents are measured in special single chip mode and the CPU code is executed from
RAM. For Run and Wait current measurements PLL is on and the reference clock is the IRC1M trimmed
to 1MHz. The bus frequency is 32MHz and the CPU frequency is 64MHz. Table A-8., Table A-9. and
Table A-10. show the configuration of the CPMU module and the peripherals for Run, Wait and Stop
current measurement.
Table A-8. CPMU Configuration for Pseudo Stop Current Measurement
CPMU REGISTER
Bit settings/Conditions
CPMUCLKS
PLLSEL=0, PSTP=1,
PRE=PCE=RTIOSCSEL=COPOSCSEL=1
CPMUOSC
OSCE=1, External Square wave on EXTAL fEXTAL=16MHz,
VIH= 1.8V, VIL=0V
CPMURTI
RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111;
CPMUCOP
WCOP=1, CR[2:0]=111
Table A-9. CPUM Configuration for Run/Wait and Full Stop Current Measurement
CPMU REGISTER
CPMUSYNR
CPMUPOSTDIV
Bit settings/Conditions
VCOFRQ[1:0]=01,SYNDIV[5:0] = 32
POSTDIV[4:0]=0,
CPMUCLKS
PLLSEL=1
CPMUOSC
OSCE=0,
Reference clock for PLL is fref=firc1m trimmed to 1MHz
API settings for STOP current measurement
CPMUAPICTL
APIEA=0, APIFE=1, APIE=0
CPMUAPITR
trimmed to 10Khz
CPMUAPIRH/RL
set to $FFFF
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Table A-10. Peripheral Configurations for Run & Wait Current Measurement
Peripheral
MSCAN
Configuration
configured to loop-back mode using a bit rate of 1Mbit/s
SPI
configured to master mode, continously transmit data (0x55
or 0xAA) at 1Mbit/s
SCI
configured into loop mode, continously transmit data (0x55)
at speed of 57600 baud
PWM
configured to toggle its pins at the rate of 40kHz
ATD
the peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on all
input channels in sequence.
DBG
the module is enabled and the comparators are configured
to trigger in outside range.The range covers all the code
executed by the core.
TIM
the peripheral shall be configured to output compare mode,
pulse accumulator and modulus counter enabled.
COP & RTI
enabled
Table A-11. Run and Wait Current Characteristics
Conditions are: VDDR=5.5V, TA=125°C, see Table A-9. and Table A-10.
Num
C
Rating
1
P
IDD Run Current
2
P
IDD Wait Current
Symbol
Min
Typ
Max
Unit
IDDR
18
20
mA
IDDW
11
12
mA
Typ
Max
Unit
Table A-12. Full Stop Current Characteristics
Conditions are: VDDR=5.5V, API see Table A-9.
Num
C
Rating
Symbol
Min
Stop Current API disabled
1
P
150°C
IDDS
250
1100
µA
2
P
-40°C
IDDS
15
35
µA
3
P
25°C,
IDDS
25
50
µA
Stop Current API enabled
4
C
150°C,
IDDS
270
µA
5
C
-40°C
IDDS
20
µA
6
C
25°C
IDDS
40
µA
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Freescale Semiconductor
511
Electrical Characteristics
Table A-13. Pseudo Stop Current Characteristics
Conditions are: VDDR=5.5V, RTI and COP and API enabled, see Table A-8.
Num
C
1
C
150°C
IDDPS
450
µA
2
C
-40°C
IDDPS
175
µA
3
C
25°C
IDDPS
200
µA
A.2
Rating
Symbol
Min
Typ
Max
Unit
ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
A.2.1
ATD Operating Characteristics
The Table A-14 and Table A-15 show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-14. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 3.13 V < VDDA < 5.5 V
Num C
1
Rating
D Reference potential
Low
High
Symbol
Min
Typ
Max
Unit
VRL
VRH
VSSA
VDDA/2
—
—
VDDA/2
VDDA
V
V
2
D Voltage difference VDDX to VDDA
∆VDDX
–2.35
0
0.1
V
3
D Voltage difference VSSX to VSSA
∆VSSX
–0.1
0
0.1
V
VRH-VRL
3.13
5.0
5.5
V
8.0
MHz
(1)
4
C Differential reference voltage
5
C ATD Clock Frequency (derived from bus clock via the
prescaler bus)
6
P ATD Clock Frequency in Stop mode (internal generated
temperature and voltage dependent clock, ICLK)
7
D ADC conversion in stop, recovery time(2)
0.25
fATDCLk
tATDSTPRC
0.6
1
1.7
MHz
—
—
1.5
us
42
41
39
ATD
clock
Cycles
V
8
ATD Conversion Period(3)
12 bit resolution:
D 10 bit resolution:
8 bit resolution:
NCONV12
NCONV10
NCONV8
20
19
17
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
3. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
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Freescale Semiconductor
Electrical Characteristics
A.2.2
Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.2.2.1
Port AD Output Drivers Switching
PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
is recommended to configure PortAD pins as outputs only for low frequency, low load outputs. The impact
on ATD accuracy is load dependent and not specified. The values specified are valid under condition that
no PortAD output drivers switch during conversion.
A.2.2.2
Source Resistance
Due to the input pin leakage current as specified in Table A-6 and Table A-7 in conjunction with the source
resistance there will be a voltage drop from the signal source to the ATD input. The maximum source
resistance RS specifies results in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum
leakage current. If device or operating conditions are less than worst case or leakage-induced error is
acceptable, larger values of source resistance of up to 10Kohm are allowed.
A.2.2.3
Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB (10-bit resilution), then the external filter capacitor, Cf ≥ 1024 * (CINS–CINN).
A.2.2.4
Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF (in 10-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as:
VERR = K * RS * IINJ
with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
513
Electrical Characteristics
Table A-15. ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
RS
—
—
1
KΩ
1
C Max input source resistance(1)
2
D Total input capacitance Non sampling
Total input capacitance Sampling
CINN
CINS
—
—
—
—
10
16
pF
3
D Input internal Resistance
RINA
-
5
15
kΩ
4
C Disruptive analog input current
INA
-2.5
—
2.5
mA
5
C Coupling ratio positive current injection
Kp
—
—
1E-4
A/A
6
C Coupling ratio negative current injection
Kn
1. 1 Refer to A.2.2.2 for further information concerning source resistance
—
—
5E-3
A/A
A.2.3
ATD Accuracy
Table A-16. and Table A-17. specifies the ATD conversion performance excluding any errors due to
current injection, input capacitance and source resistance.
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Freescale Semiconductor
Electrical Characteristics
A.2.3.1
ATD Accuracy Definitions
For the following definitions see also Figure A-1.
Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps.
V –V
i
i–1
DNL ( i ) = --------------------------- – 1
1LSB
The integral non-linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
∑
V –V
n
0
DNL ( i ) = --------------------- – n
1LSB
i=1
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Freescale Semiconductor
515
Electrical Characteristics
DNL
Vi-1
10-Bit Absolute Error Boundary
LSB
Vi
$3FF
8-Bit Absolute Error Boundary
$3FE
$3FD
$FF
$3FC
$3FB
$3FA
$3F9
$FE
$3F8
$3F7
$3F6
$3F5
10-Bit Resolution
$3F3
9
Ideal Transfer Curve
2
8
8-Bit Resolution
$FD
$3F4
7
10-Bit Transfer Curve
6
5
1
4
3
8-Bit Transfer Curve
2
1
0
5
10
15
20
25
30
35
40
45
55
60
65
70
75
80
85
90
95 100 105 110 115 120
5000 +
Vin
mV
Figure A-1. ATD Accuracy Definitions
NOTE
Figure A-1 shows only definitions, for specification values refer to Table A16 and Table A-17.
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Freescale Semiconductor
Electrical Characteristics
Table A-16. ATD Conversion Performance 5V range
Conditions are shown in Table A-4. unless otherwise noted. VREF = VRH - VRL = 5.12V. fATDCLK = 8.0MHz
The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions.
Rating(1)
Num C
Symbol
Min
Typ
Max
1
P Resolution
12-Bit
LSB
2
P Differential Nonlinearity
12-Bit
DNL
-4
±2
4
counts
3
P Integral Nonlinearity
12-Bit
INL
-5
±2.5
5
counts
12-Bit
AE
-7
±4
7
counts
(2)
1.25
Unit
mV
4
P Absolute Error
5
C Resolution
10-Bit
LSB
6
C Differential Nonlinearity
10-Bit
DNL
-1
±0.5
1
counts
7
C Integral Nonlinearity
10-Bit
INL
-2
±1
2
counts
8
C Absolute Error2.
10-Bit
AE
-3
±2
3
counts
9
C Resolution
8-Bit
LSB
10
C Differential Nonlinearity
8-Bit
DNL
-0.5
±0.3
0.5
counts
11
C Integral Nonlinearity
8-Bit
INL
-1
±0.5
1
counts
5
mV
20
mV
8-Bit
AE
-1.5
±1
1.5
counts
12 C Absolute Error2.
1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode.
2. These values include the quantization error which is inherently 1/2 count for any A/D converter.
Table A-17. ATD Conversion Performance 3.3V range
Conditions are shown in Table A-4. unless otherwise noted. VREF = VRH - VRL = 3.3V. fATDCLK = 8.0MHz
The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions.
Rating(1)
Num C
Symbol
Min
Typ
Max
1
P Resolution
12-Bit
LSB
2
P Differential Nonlinearity
12-Bit
DNL
-6
±3
6
counts
3
P Integral Nonlinearity
12-Bit
INL
-7
±3
7
counts
-8
±4
8
counts
(2)
0.80
Unit
mV
4
P Absolute Error
12-Bit
AE
5
C Resolution
10-Bit
LSB
6
C Differential Nonlinearity
10-Bit
DNL
-1.5
±1
1.5
counts
7
C Integral Nonlinearity
10-Bit
INL
-2
±1
2
counts
-3
±2
3
counts
2.
3.22
mV
8
C Absolute Error
10-Bit
AE
9
C Resolution
8-Bit
LSB
10
C Differential Nonlinearity
8-Bit
DNL
-0.5
±0.3
0.5
counts
11
C Integral Nonlinearity
8-Bit
INL
-1
±0.5
1
counts
12.89
mV
2.
8-Bit
AE
-1.5
±1
1.5
counts
12 C Absolute Error
1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode.
2. These values include the quantization error which is inherently 1/2 count for any A/D converter.
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517
Electrical Characteristics
A.3
A.3.1
NVM
Timing Parameters
The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV
register. The frequency of this derived clock must be set within the limits specified as fNVMOP. The NVM
module does not have any means to monitor the frequency and will not prevent program or erase operation
at frequencies above or below the specified minimum. When attempting to program or erase the NVM
module at a lower frequency, a full program or erase transition is not assured.
The following sections provide equations which can be used to determine the time required to execute
specific flash commands. All timing parameters are a function of the bus clock frequency, fNVMBUS. All
program and erase times are also a function of the NVM operating frequency, fNVMOP. A summary of key
timing parameters can be found in Table A-18.
A.3.1.1
Erase Verify All Blocks (Blank Check) (FCMD=0x01)
The time required to perform a blank check on all blocks is dependent on the location of the first non-blank
word starting at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the
command. Assuming that no non-blank location is found, then the time to erase verify all blocks is given
by:
1
t check = 35500 ⋅ --------------------f NVMBUS
A.3.1.2
Erase Verify Block (Blank Check) (FCMD=0x02)
The time required to perform a blank check is dependent on the location of the first non-blank word starting
at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command.
Assuming that no non-blank location is found, then the time to erase verify a P-Flash block is given by:
1
t pcheck = 33500 ⋅ --------------------f NVMBUS
Assuming that no non-blank location is found, then the time to erase verify a D-Flash block is given by:
1
t dcheck = 2800 ⋅ --------------------f NVMBUS
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Freescale Semiconductor
Electrical Characteristics
A.3.1.3
Erase Verify P-Flash Section (FCMD=0x03)
The maximum time to erase verify a section of P-Flash depends on the number of phrases being verified
(NVP) and is given by:
1
t ≈ ( 450 + N VP ) ⋅ --------------------f NVMBUS
A.3.1.4
Read Once (FCMD=0x04)
The maximum read once time is given by:
1
t = 400 ⋅ --------------------f NVMBUS
A.3.1.5
Program P-Flash (FCMD=0x06)
The programming time for a single phrase of four P-Flash words and the two seven-bit ECC fields is
dependent on the bus frequency, fNVMBUS, as well as on the NVM operating frequency, fNVMOP.
The typical phrase programming time is given by:
1
1
t ppgm ≈ 164 ⋅ ------------------- + 2000 ⋅ --------------------f NVMBUS
f NVMOP
The maximum phrase programming time is given by:
1
1
t ppgm ≈ 164 ⋅ ------------------- + 2500 ⋅ --------------------f NVMBUS
f NVMOP
A.3.1.6
Program Once (FCMD=0x07)
The maximum time required to program a P-Flash Program Once field is given by:
1
1
t ≈ 164 ⋅ ------------------- + 2150 ⋅ --------------------f NVMBUS
f NVMOP
A.3.1.7
Erase All Blocks (FCMD=0x08)
The time required to erase all blocks is given by:
1
1
t mass ≈ 100100 ⋅ ------------------- + 70000 ⋅ --------------------f NVMBUS
f NVMOP
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Freescale Semiconductor
519
Electrical Characteristics
A.3.1.8
Erase P-Flash Block (FCMD=0x09)
The time required to erase the P-Flash block is given by:
1
1
t pmass ≈ 100100 ⋅ ------------------- + 67000 ⋅ --------------------f NVMBUS
f NVMOP
A.3.1.9
Erase P-Flash Sector (FCMD=0x0A)
The typical time to erase a 512-byte P-Flash sector is given by:
1
1
t pera ≈ 20020 ⋅ ------------------- + 700 ⋅ --------------------f NVMBUS
f NVMOP
The maximum time to erase a 512-byte P-Flash sector is given by:
1
1
t pera ≈ 20020 ⋅ ------------------- + 1400 ⋅ --------------------f NVMOP
f NVMBUS
A.3.1.10
Unsecure Flash (FCMD=0x0B)
The maximum time required to erase and unsecure the Flash is given by:
for 128 Kbyte P-Flash and 4 Kbyte D-Flash
1
1
t uns ≈ 100100 ⋅ ------------------- + 70000 ⋅ --------------------f NVMBUS
f NVMOP
A.3.1.11
Verify Backdoor Access Key (FCMD=0x0C)
The maximum verify backdoor access key time is given by:
1
t = 400 ⋅ --------------------f NVMBUS
A.3.1.12
Set User Margin Level (FCMD=0x0D)
The maximum set user margin level time is given by:
1
t = 350 ⋅ --------------------f NVMBUS
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Freescale Semiconductor
Electrical Characteristics
A.3.1.13
Set Field Margin Level (FCMD=0x0E)
The maximum set field margin level time is given by:
1
t = 350 ⋅ --------------------f NVMBUS
A.3.1.14
Erase Verify D-Flash Section (FCMD=0x10)
The time required to Erase Verify D-Flash for a given number of words NW is given by:
1
t dcheck ≈ ( 450 + N W ) ⋅ --------------------f NVMBUS
A.3.1.15
Program D-Flash (FCMD=0x11)
D-Flash programming time is dependent on the number of words being programmed and their location
with respect to a row boundary since programming across a row boundary requires extra steps. The DFlash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary.
The typical D-Flash programming time is given by the following equation, where NW denotes the number
of words; BC=0 if no row boundary is crossed and BC=1 if a row boundary is crossed:
1
1
t dpgm ≈ ⎛ ( 14 + ( 54 ⋅ N W ) + ( 14 ⋅ BC ) ) ⋅ ------------------- ⎞ + ⎛ ( 500 + ( 525 ⋅ N W ) + ( 100 ⋅ BC ) ) ⋅ --------------------- ⎞
⎝
f NVMOP ⎠ ⎝
f NVMBUS ⎠
The maximum D-Flash programming time is given by:
1
1
t dpgm ≈ ⎛ ( 14 + ( 54 ⋅ N W ) + ( 14 ⋅ BC ) ) ⋅ ------------------- ⎞ + ⎛ ( 500 + ( 750 ⋅ N W ) + ( 100 ⋅ BC ) ) ⋅ --------------------- ⎞
⎝
f NVMOP ⎠ ⎝
f NVMBUS ⎠
A.3.1.16
Erase D-Flash Sector (FCMD=0x12)
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given
by:
1
1
t dera ≈ 5025 ⋅ ------------------- + 700 ⋅ --------------------f NVMBUS
f NVMOP
Maximum D-Flash sector erase times is given by:
1
1
t dera ≈ 20100 ⋅ ------------------- + 3400 ⋅ --------------------f NVMBUS
f NVMOP
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
521
Electrical Characteristics
The D-Flash sector erase time is ~5ms on a new device and can extend to ~20ms as the flash is cycled.
Table A-18. NVM Timing Characteristics (FTMRC)
Num C
Rating
Symbol
Min
Typ(1)
Max(2)
Unit(3)
1
Bus frequency
fNVMBUS
1
—
32
MHz
2
Operating frequency
fNVMOP
0.8
1.0
1.05
MHz
3
D Erase all blocks (mass erase) time
tmass
—
100
130
ms
4
D Erase verify all blocks (blank check) time
tcheck
—
—
35500
tcyc
5
D Unsecure Flash time
tuns
—
100
130
ms
6
D P-Flash block erase time
tpmass
—
100
130
ms
7
D P-Flash erase verify (blank check) time
tpcheck
—
—
33500
tcyc
8
D P-Flash sector erase time
tpera
—
20
26
ms
9
D P-Flash phrase programming time
tppgm
—
226
285
µs
tdera
—
(4)
5
26
ms
10
D D-Flash sector erase time
11
D D-Flash erase verify (blank check) time
tdcheck
—
—
2800
tcyc
12a
D D-Flash one word programming time
tdpgm1
—
100
107
µs
12b
D D-Flash two word programming time
tdpgm2
—
170
185
µs
12c
D D-Flash three word programming time
tdpgm3
—
241
262
µs
12d
D D-Flash four word programming time
tdpgm4
—
311
339
µs
328
357
µs
—
D D-Flash four word programming time crossing row
tdpgm4c
boundary
1. Typical program and erase times are based on typical fNVMOP and maximum fNVMBUS
2. Maximum program and erase times are based on minimum fNVMOP and maximum fNVMBUS
3. tcyc = 1 / fNVMBUS
4. Typical value for a new device
12e
A.3.2
NVM Reliability Parameters
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The data retention and program/erase cycling failure rates are specified at the operating conditions noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
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522
Freescale Semiconductor
Electrical Characteristics
NOTE
All values shown in Table A-19 are preliminary and subject to further
characterization.
Table A-19. NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
tNVMRET
20
100(2)
—
Years
nFLPE
10K
100K(3)
—
Cycles
Program Flash Arrays
1
C Data retention at an average junction temperature of TJavg =
85°C(1) after up to 10,000 program/erase cycles
2
C Program Flash number of program/erase cycles
(-40°C ≤ tj ≤ 150°C)
Data Flash Array
3
C Data retention at an average junction temperature of TJavg =
85°C1 after up to 50,000 program/erase cycles
tNVMRET
5
1002
—
Years
4
C Data retention at an average junction temperature of TJavg =
85°C1 after up to 10,000 program/erase cycles
tNVMRET
10
1002
—
Years
5
C Data retention at an average junction temperature of TJavg =
85°C1 after less than 100 program/erase cycles
tNVMRET
20
1002
—
Years
6
C Data Flash number of program/erase cycles (-40°C ≤ tj ≤ 150°C)
nFLPE
50K
500K3
—
Cycles
1. TJavg does not exceed 85°C in a typical temperature profile over the lifetime of a consumer, industrial or automotive
application.
2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618
3. Spec table quotes typical endurance evaluated at 25°C for this product family. For additional information on how Freescale
defines Typical Endurance, please refer to Engineering Bulletin EB619.
A.4
A.4.1
Phase Locked Loop
Jitter Definitions
With each transition of the feedback clock, the deviation from the reference clock is measured and input
voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes
in the VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure A-2.
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Freescale Semiconductor
523
Electrical Characteristics
1
0
2
3
N-1
N
tmin1
tnom
tmax1
tminN
tmaxN
Figure A-2. Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N) ⎞
⎛
max
min
J ( N ) = max ⎜ 1 – ----------------------- , 1 – ----------------------- ⎟
N⋅t
N⋅t
⎝
nom
nom ⎠
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J ( N ) = -------N
J(N)
1
5
10
20
N
Figure A-3. Maximum Bus Clock Jitter Approximation
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter
to a large extent.
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Freescale Semiconductor
Electrical Characteristics
A.4.2
Electrical Characteristics for the PLL
Table A-20. PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
fVCORST
Typ
Max
Unit
8
32
MHz
64
MHz
1
D VCO frequency during system reset
2
C VCO locking range
fVCO
32
3
C Reference Clock
fREF
1
4
D Lock Detection
|∆Lock|
0
1.5
%(1)
6
D Un-Lock Detection
|∆unl|
0.5
2.5
%1
7
C Time to lock
tlock
150 +
256/fREF
µs
MHz
j1
8
C Jitter fit parameter 1(2)
1.4
%
1. % deviation from target frequency
2. fREF = 4MHz oscillator, fBUS = 32MHz equivalent fPLL = 64MHz, CPMUREFDIV=$40, CPMUSYNR=$47, CPMUPOSTDIV=$00
A.5
Electrical Characteristics for the IRC1M
Table A-21. IRC1M Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
Rating
P Junction Temperature -40°C to 150°C
Internal Reference Frequency, factory trimmed
Symbol
Min
Typ
Max
Unit
fIRC1M_TRIM
0.985
1
1.015
MHz
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Freescale Semiconductor
525
Electrical Characteristics
A.6
Electrical Characteristics for the Oscillator (OSCLCP)
Table A-22. OSCLCP Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
16
MHz
1
C Crystal oscillator range
fOSC
4.0
2
P Startup Current
iOSC
100
3a
C Oscillator start-up time (LCP, 4MHz)(1)
tUPOSC
—
2
10
ms
3b
C Oscillator start-up time (LCP, 8MHz)1
tUPOSC
—
1.6
8
ms
3c
C Oscillator start-up time (LCP, 16MHz)1
tUPOSC
—
1
5
ms
4
P Clock Monitor Failure Assert Frequency
fCMFA
200
400
1000
KHz
5
D Input Capacitance (EXTAL, XTAL pins)
CIN
6
C EXTAL Pin Input Hysteresis
VHYS,EXTAL
µA
7
—
pF
180
—
mV
EXTAL Pin oscillation amplitude (loop
—
—
VPP,EXTAL
0.9
V
controlled Pierce)
1. These values apply for carefully designed PCB layouts with capacitors that match the crystal/resonator requirements.
7
A.7
C
Reset Characteristics
Table A-23. Reset and Stop & Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
Rating
C Reset input pulse width, minimum input time
Symbol
Min
PWRSTL
2
Typ
Max
Unit
tVCORS
T
2
C Startup from Reset
nRST
768
tVCORS
T
3
C STOP recovery time
tSTP_REC
50
µs
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526
Freescale Semiconductor
Electrical Characteristics
A.8
Electrical Specification for Voltage Regulator
Table A-24. IVREG Characteristics
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
1
P
Input Voltages
VVDDR,A
3.13
—
5.5
V
2
P
VDDA Low Voltage Interrupt Assert Level (1)
VDDA Low Voltage Interrupt Deassert Level
VLVIA
VLVID
4.04
4.19
4.23
4.38
4.40
4.49
V
V
3
P
VDDX Low Voltage Reset Deassert (2) (3)
VLVRXD
—
—
3.13
V
4
T
API ACLK frequency
(APITR[5:0] = %000000)
fACLK
—
10
—
KHz
5
C
Trimmed API internal clock(4) ∆f / fnominal
dfACLK
- 5%
—
+ 5%
—
6
D
The first period after enabling the counter
by APIFE might be reduced by API start up
delay
tsdel
—
—
100
us
7
T
Temperature Sensor Slope
dVTS
4.0
5.5
6.5
mV/
oC
High Temperature Interrupt Assert
THTIA
125
oC
(CPMUHTTR=$88)(5)
105
8
T
THTID
High Temperature Interrupt Deassert
(CPMUHTTR=$88)
1. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply
voltage.
2. Device functionality is guaranteed on power down to the LVR assert level
3. Monitors VDDX, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-4)
4. The API Trimming APITR[5:0] bits must be set so that fACLK=10KHz.
5. A hysteresis is guaranteed by design
NOTE
The LVR monitors the voltages VDD, VDDF and VDDX. As soon as voltage
drops on these supplies which would prohibit the correct function of the
microcontroller, the LVR is triggering a reset.
A.9
Chip Power-up and Voltage Drops
LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or
drops of the supply voltage.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
527
Electrical Characteristics
Figure A-4. MC9S12P-Family - Chip Power-up and Voltage Drops (not scaled)
V
VDDA/VDDX
VLVID
VLVIA
VDD
VLVRD
VLVRA
VPORD
t
LVI
LVI enabled
LVI disabled due to LVR
POR
LVR
S12P-Family Reference Manual, Rev. 1.13
528
Freescale Semiconductor
Electrical Characteristics
A.10
MSCAN
Table A-25. MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P MSCAN wakeup dominant pulse filtered
tWUP
—
—
1.5
µs
2
P MSCAN wakeup dominant pulse pass
tWUP
5
—
—
µs
A.11
SPI Timing
This section provides electrical parametrics and ratings for the SPI. In Table A-26 the measurement
conditions are listed.
Table A-26. Measurement Conditions
Description
Drive mode
Load capacitance
CLOAD(1), on
all outputs
Thresholds for delay measurement points
1. Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
A.11.1
Value
Unit
Full drive mode
—
50
pF
(20% / 80%) VDDX
V
Master Mode
In Figure A-5 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
SS
(Output)
2
1
SCK
(CPOL = 0)
(Output)
12
13
3
4
5
6
Bit MSB-1. . . 1
MSB IN2
10
MOSI
(Output)
13
4
SCK
(CPOL = 1)
(Output)
MISO
(Input)
12
LSB IN
9
MSB OUT2
Bit MSB-1. . . 1
11
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
Figure A-5. SPI Master Timing (CPHA = 0)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
529
Electrical Characteristics
In Figure A-6 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS
(Output)
1
2
12
13
12
13
3
SCK
(CPOL = 0)
(Output)
4
4
SCK
(CPOL = 1)
(Output)
5
MISO
(Input)
6
MSB IN2
Port Data
LSB IN
11
9
MOSI
(Output)
Bit MSB-1. . . 1
Master MSB OUT2
Bit MSB-1. . . 1
Master LSB OUT
Port Data
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure A-6. SPI Master Timing (CPHA = 1)
S12P-Family Reference Manual, Rev. 1.13
530
Freescale Semiconductor
Electrical Characteristics
In Table A-27 the timing characteristics for master mode are listed.
Table A-27. SPI Master Mode Timing Characteristics
Num
C
Characteristic
Symbol
Min
Typ
Max
Unit
1
D
SCK frequency
fsck
1/2048
—
1/2
fbus
1
D
SCK period
tsck
2
D
Enable lead time
tlead
2
—
2048
tbus
—
1/2
—
tsck
3
D
Enable lag time
4
D
Clock (SCK) high or low time
tlag
—
1/2
—
tsck
twsck
—
1/2
—
tsck
5
D
Data setup time (inputs)
tsu
8
—
—
ns
6
D
Data hold time (inputs)
thi
8
—
—
ns
9
D
Data valid after SCK edge
tvsck
—
—
29
ns
10
D
Data valid after SS fall (CPHA = 0)
tvss
—
—
15
ns
11
D
Data hold time (outputs)
tho
20
—
—
ns
12
D
Rise and fall time inputs
trfi
—
—
8
ns
13
D
Rise and fall time outputs
trfo
—
—
8
ns
A.11.2
Slave Mode
In Figure A-7 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
SS
(Input)
1
12
13 3
12
13
SCK
(CPOL = 0)
(Input)
4
2
4
SCK
(CPOL = 1)
(Input) 10
8
7
MISO
(Output)
9
See
Note
Slave MSB
5
MOSI
(Input)
Bit MSB-1 . . . 1
11
11
Slave LSB OUT
See
Note
6
MSB IN
Bit MSB-1. . . 1
LSB IN
NOTE: Not defined
Figure A-7. SPI Slave Timing (CPHA = 0)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
531
Electrical Characteristics
In Figure A-8 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
SS
(Input)
3
1
2
12
13
12
13
SCK
(CPOL = 0)
(Input)
4
4
SCK
(CPOL = 1)
(Input)
See
Note
7
Slave
MSB OUT
5
MOSI
(Input)
8
11
9
MISO
(Output)
Bit MSB-1 . . . 1
Slave LSB OUT
6
MSB IN
Bit MSB-1 . . . 1
LSB IN
NOTE: Not defined
Figure A-8. SPI Slave Timing (CPHA = 1)
In Table A-28 the timing characteristics for slave mode are listed.
Table A-28. SPI Slave Mode Timing Characteristics
Num
C
1
D
1
Symbol
Min
Typ
Max
Unit
SCK frequency
fsck
DC
—
1/4
fbus
D
SCK period
tsck
4
—
∞
tbus
2
D
Enable lead time
tlead
4
—
—
tbus
3
D
Enable lag time
tlag
4
—
—
tbus
4
D
Clock (SCK) high or low time
twsck
4
—
—
tbus
5
D
Data setup time (inputs)
tsu
8
—
—
ns
6
D
Data hold time (inputs)
thi
8
—
—
ns
7
D
Slave access time (time to data active)
ta
—
—
20
ns
8
D
Slave MISO disable time
tdis
—
—
22
9
D
Characteristic
Data valid after SCK edge
tvsck
—
—
29 + 0.5 ⋅
ns
tbus(1)
ns
tbus1
ns
29 + 0.5 ⋅
10
D
Data valid after SS fall
tvss
—
—
11
D
Data hold time (outputs)
tho
20
—
—
ns
12
D
Rise and fall time inputs
trfi
—
—
8
ns
trfo
—
—
8
ns
13
D
Rise and fall time outputs
1. 0.5 tbus added due to internal synchronization delay
S12P-Family Reference Manual, Rev. 1.13
532
Freescale Semiconductor
Ordering Information
Appendix B
Ordering Information
The following figure provides an ordering partnumber example for the devices covered by this data book.
There are two options when ordering a device. Customers must choose between ordering either the maskspecific partnumber or the generic / mask-independent partnumber. Ordering the mask-specific
partnumber enables the customer to specify which particular maskset they will receive whereas ordering
the generic maskset means that FSL will ship the currently preferred maskset (which may change over
time).
In either case, the marking on the device will always show the generic / mask-independent partnumber and
the mask set number.
NOTE
The mask identifier suffix and the Tape & Reel suffix are always both omitted from the
partnumber which is actually marked on the device.
For specific partnumbers to order, please contact your local sales office. The below figure illustrates the
structure of a typical mask-specific ordering number for the MC9S12P-Family devices
S 9 S12 P128
J0 M FT R
Tape & Reel:
R = Tape & Reel
No R = No Tape & Reel
Package Option:
FT = 48 QFN
LH = 64 LQFP
QK = 80 QFP
Temperature Option:
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Maskset identifier Suffix:
First digit usually references wafer fab
Second digit usually differentiates mask rev
(This suffix is omitted in generic partnumbers)
Device Title
Controller Family
Main Memory Type:
9 = Flash
3 = ROM (if available)
Status / Partnumber type:
S or SC = Maskset specific partnumber
MC = Generic / mask-independent partnumber
P or PC = prototype status (pre qualification)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
533
Ordering Information
S12P-Family Reference Manual, Rev. 1.13
534
Freescale Semiconductor
Package Information
Appendix C
Package Information
This section provides the physical dimensions of the MC9S12P-Family packages.
NOTE
The exposed pad of the 48 QFN package should be attached to Vss ground
plane.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
535
Package Information
C.1
80 QFP Package Mechanical Outline
S12P-Family Reference Manual, Rev. 1.13
536
Freescale Semiconductor
Package Information
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
537
Package Information
S12P-Family Reference Manual, Rev. 1.13
538
Freescale Semiconductor
Package Information
C.2
48 QFN Package Mechanical Outline
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
539
Package Information
S12P-Family Reference Manual, Rev. 1.13
540
Freescale Semiconductor
Package Information
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
541
Package Information
C.3
64 LQFP Package Mechanical Outline
S12P-Family Reference Manual, Rev. 1.13
542
Freescale Semiconductor
Package Information
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
543
Package Information
S12P-Family Reference Manual, Rev. 1.13
544
Freescale Semiconductor
Detailed Register Address Map
Appendix D
Detailed Register Address Map
D.1
Detailed Register Map
The following tables show the detailed register map of the MC9S12P-Family.
0x0000-0x0009 Port Integration Module (PIM) Map 1 of 4
Address
Name
0x0000
PORTA
0x0001
PORTB
0x0002
DDRA
0x0003
DDRB
0x0004
Reserved
0x0005
Reserved
0x0006
Reserved
0x0007
Reserved
0x0008
PORTE
0x0009
DDRE
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
0
0
0x000A-0x000B Module Mapping Conrol (MMC) Map 1 of 2
Address
Name
0x000A
Reserved
0x000B
MODE
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODC
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
545
Detailed Register Address Map
0x000C-0x000D Port Integration Module (PIM) Map 2 of 4
Address
Name
0x000C
PUCR
0x000D
RDRIV
Bit 7
R
W
R
W
0
0
Bit 6
BKPUE
Bit 5
0
Bit 4
Bit 3
Bit 2
0
0
0
0
PUPEE
Bit 1
Bit 0
PUPBE
PUPAE
RDPB
RDPA
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDPE
0x000E-0x000F Reserved
Address
Name
0x000E
Reserved
0x000F
Reserved
R
W
R
W
0x0010-0x0017 Module Mapping Control (MMC) Map 2 of 2
Address
Name
0x0010
Reserved
0x0011
DIRECT
0x0012
Reserved
0x0013
Reserved
0x0014
Reserved
0x0015
PPAGE
0x0016
Reserved
0x0017
Reserved
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0018-0x0019 Reserved
Address
Name
0x0018
Reserved
0x0019
Reserved
R
W
R
W
S12P-Family Reference Manual, Rev. 1.13
546
Freescale Semiconductor
Detailed Register Address Map
0x001A-0x001B Part ID Registers
Address
Name
0x001A
PARTIDH
0x001B
PARTIDL
Bit 7
Bit 6
Bit 5
Bit 4
R
W
R
W
Bit 3
Bit 2
Bit 1
Bit 0
PARTIDH
PARTIDL
0x001C-0x001F Port Intergartion Module (PIM) Map 3 of 4
Address
Name
0x001C
ECLKCTL
0x001D
Reserved
0x001E
IRQCR
0x001F
Reserved
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NECLK
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
0
0
0
0
0
0
0
0
IRQE
IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BDM
DBGBRK
0
0
0
0
0
0x0020-0x002F Debug Module (S12SDBG) Map
Address
Name
0x0020
DBGC1
0x0021
DBGSR
0x0022
DBGTCR
0x0023
DBGC2
0x0024
DBGTBH
0x0025
DBGTBL
0x0026
DBGCNT
0x0027
DBGSCRX
0x0027
DBGMFR
0x0028
(1)
0x0028
(2)
DBGACTL
DBGBCTL
Bit 7
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
ARM
TBF
0
Bit 6
Bit 5
0
TRIG
0
0
TSOURCE
0
SSF2
COMRV
SSF1
0
TRCMOD
SSF0
TALIGN
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBF
0
0
0
0
0
SC3
SC2
SC1
SC0
0
0
0
0
0
MC2
MC1
MC0
SZE
SZ
TAG
BRK
RW
RWE
SZE
SZ
TAG
BRK
RW
RWE
ABCM
CNT
0
0
COMPE
COMPE
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
547
Detailed Register Address Map
0x0020-0x002F Debug Module (S12SDBG) Map
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
R
0
0
0x0028
DBGCCTL
TAG
BRK
RW
RWE
(3)
W
R
0
0
0
0
0
0
0x0029
DBGXAH
W
R
0x002A
DBGXAM
Bit 15
14
13
12
11
10
W
R
0x002B
DBGXAL
Bit 7
6
5
4
3
2
W
R
0x002C
DBGADH
Bit 15
14
13
12
11
10
W
R
0x002D
DBGADL
Bit 7
6
5
4
3
2
W
R
0x002E
DBGADHM
Bit 15
14
13
12
11
10
W
R
0x002F
DBGADLM
Bit 7
6
5
4
3
2
W
1. This represents the contents if the Comparator A or C control register is blended into this address
2. This represents the contents if the Comparator B or D control register is blended into this address
3. This represents the contents if the Comparator B or D control register is blended into this address
0
Bit 0
COMPE
17
Bit 16
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
0x0030-0x0033 Reserved
Address
Name
0x0030
Reserved
0x0031
Reserved
0x0032
Reserved
0x0033
Reserved
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 2
Bit 1
Bit 0
0x0034-0x003F Clock Reset and Power Management (CPMU) Map
Address
Name
R
W
R
0x0035 CPMUREFDIV
W
CPMUPOSTDI R
0x0036
V
W
R
0x0037
CPMUFLG
W
0x0034
CPMUSYNR
Bit 7
Bit 6
Bit 5
Bit 4
VCOFRQ[1:0]
REFFRQ[1:0]
Bit 3
SYNDIV[5:0]
0
0
0
0
RTIF
PORF
LVRF
0
REFDIV[3:0]
POSTDIV[4:0]
LOCKIF
LOCK
ILAF
OSCIF
UPOSC
S12P-Family Reference Manual, Rev. 1.13
548
Freescale Semiconductor
Detailed Register Address Map
0x0034-0x003F Clock Reset and Power Management (CPMU) Map
Address
Name
0x0038
CPMUINT
0x0039
CPMUCLKS
0x003A
CPMUPLL
0x003B
CPMURTI
0x003C
CPMUCOP
0x003D
Reserved
0x003E
Reserved
0x003F
CPMU
ARMCOP
Bit 7
R
RTIE
W
R
PLLSEL
W
R
0
W
R
W
R
W
R
W
R
W
R
W
Bit 6
Bit 5
0
0
PSTP
0
Bit 4
LOCKIE
Bit 3
Bit 2
0
0
PRE
PCE
RTIOSCS
EL
COPOSC
SEL
0
0
0
0
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
0
0
0
0
0
0
2
0
1
0
Bit 0
0
0
FM1
FM0
RTR5
RTR4
RTR3
0
0
RTDEC
RTR6
WCOP
RSBCK
0
0
0
WRTMAS
K
0
0
0
0
0
Bit 7
0
6
0
5
0
0
Reserved For Factory Test
0
Reserved For Factory Test
0
0
4
3
Bit 1
OSCIE
Bit 0
0
0x0040-0x006F Timer Module (TIM) Map
Address
Name
0x0040
TIOS
0x0041
CFORC
0x0042
OC7M
0x0043
OC7D
0x0044
TCNTH
0x0045
TCNTL
0x0046
TSCR1
0x0047
TTOV
0x0048
TCTL1
0x0049
TCTL2
0x004A
TCTL3
0x004B
TCTL4
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
FOC7
0
FOC6
0
FOC5
0
FOC4
0
FOC3
0
FOC2
0
FOC1
0
FOC0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
TEN
TSWAI
TSFRZ
TFFCA
PRNT
0
0
0
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
549
Detailed Register Address Map
0x0040-0x006F Timer Module (TIM) Map
Address
Name
0x004C
TIE
0x004D
TSCR2
0x004E
TFLG1
0x004F
TFLG2
0x0050
TC0H
0x0051
TC0L
0x0052
TC1H
0x0053
TC1L
0x0054
TC2H
0x0055
TC2L
0x0056
TC3H
0x0057
TC3L
0x0058
TC4H
0x0059
TC4L
0x005A
TC5H
0x005B
TC5L
0x005C
TC6H
0x005D
TC6L
0x005E
TC7H
0x005F
TC7L
0x0060
PACTL
0x0061
PAFLG
0x0062
PACNTH
Bit 7
R
C7I
W
R
TOI
W
R
C7F
W
R
TOF
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
Bit 15
W
R
Bit 7
W
R
0
W
R
0
W
R
PACNT15
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
TCRE
PR2
PR1
PR0
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
PAOVF
PAIF
PACNT14
PACNT13
PACNT12
PACNT11
PACNT10
PACNT9
PACNT8
S12P-Family Reference Manual, Rev. 1.13
550
Freescale Semiconductor
Detailed Register Address Map
0x0040-0x006F Timer Module (TIM) Map
Address
Name
0x0063
PACNTL
0x0064–
0x006B
Reserved
0x006C
OCPD
0x006D
Reserved
0x006E
PTPSR
0x006F
Reserved
Bit 7
R
PACNT7
W
R
0
W
R
OCPD7
W
R
W
R
PTPS7
W
R
0
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
0
0
0
0
0
0
0
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
0
0
0
0
0
0
0
0x0070-0x009F Analog to Digital Converter 12-Bit 10-Channel (ATD) Map
Address
Name
0x0070
ATDCTL0
0x0071
ATDCTL1
0x0072
ATDCTL2
0x0073
ATDCTL3
0x0074
ATDCTL4
0x0075
ATDCTL5
0x0076
ATDSTAT0
0x0077
Reserved
0x0078
ATDCMPEH
0x0079
ATDCMPEL
0x007A
ATDSTAT2H
0x007B
ATDSTAT2L
0x007C
ATDDIENH
0x007D
ATDDIENL
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
ETRIG
SEL
SRES1
SRES0
AFFC
DJM
SMP2
0
0
SCF
Bit 3
Bit 2
Bit 1
Bit 0
WRAP3
WRAP2
WRAP1
WRAP0
SMP_DIS
ETRIG
CH3
ETRIG
CH2
ETRIG
CH1
ETRIG
CH0
ICLKSTP
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
SC
SCAN
MULT
CD
CC
CB
CA
ETORF
FIFOR
CC3
CC2
CC1
CC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CMPE[9:8]
CMPE[7:0]
CCF[9:8]
CCF[7:0]
0
0
0
0
0
0
IEN[9:8]
IEN[7:0]
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
551
Detailed Register Address Map
0x0070-0x009F Analog to Digital Converter 12-Bit 10-Channel (ATD) Map
Address
0x007E
0x007F
0x0080
0x0081
0x0082
0x0083
0x0084
0x0085
0x0086
0x0087
0x0088
0x0089
0x008A
0x008B
0x008C
0x008D
0x008E
0x008F
0x090
0x091
0x092
0x093
0x094
Name
R
ATDCMPHTH
W
R
ATDCMPHTL
W
R
ATDDR0H
W
R
ATDDR0L
W
R
ATDDR1H
W
R
ATDDR1L
W
R
ATDDR2H
W
R
ATDDR2L
W
R
ATDDR3H
W
R
ATDDR3L
W
R
ATDDR4H
W
R
ATDDR4L
W
R
ATDDR5H
W
R
ATDDR5L
W
R
ATDDR6H
W
R
ATDDR6L
W
R
ATDDR7H
W
R
ATDDR7L
W
R
ATDDR8H
W
R
ATDDR8L
W
R
ATDDR9H
W
R
ATDDR9L
W
R
ATDDR10H
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
0
0
0
0
0
Bit 1
Bit 0
CMPHT[9:8]
CMPHT[7:0]
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
S12P-Family Reference Manual, Rev. 1.13
552
Freescale Semiconductor
Detailed Register Address Map
0x0070-0x009F Analog to Digital Converter 12-Bit 10-Channel (ATD) Map
Address
Name
0x095
ATDDR10L
0x096
ATDDR11H
0x097
ATDDR11L
0x098
ATDDR12H
0x099
ATDDR12L
0x09A
ATDDR13H
0x09B
ATDDR13L
0x09C
ATDDR14H
0x09D
ATDDR14L
0x09E
ATDDR15H
0x009F
ATDDR15L
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Bit7
Bit6
0
0
0
0
0
0
0x00A0-0x00C7 Pulse Width Modulator 6-Channels (PWM) Map
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00A0
PWME
R
W
0
0
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
0x00A1
PWMPOL
R
W
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
0x00A2
PWMCLK
R
W
0
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
0x00A3
PWMPRCLK
0
0x00A4
PWMCAE
R
W
R
W
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
0x00A5
PWMCTL
R
W
0
CON45
CON23
CON01
PSWAI
PFRZ
0
0
0x00A6
PWMTST
Test Only
0x00A7
PWMPRSC
0x00A8
PWMSCLA
R
W
R
W
R
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
PCKB2
0
0
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
553
Detailed Register Address Map
0x00A0-0x00C7 Pulse Width Modulator 6-Channels (PWM) Map
Address
0x00A9
0x00AA
0x00AB
0x00AC
0x00AD
0x00AE
0x00AF
0x00B0
0x00B1
0x00B2
0x00B3
0x00B4
0x00B5
0x00B6
0x00B7
0x00B8
0x00B9
0x00BA
0x00BB
0x00BC
0x00BD
0x00BE
0x00BF0x00C7
Name
R
PWMSCLB
W
R
PWMSCNTA
W
R
PWMSCNTB
W
R
PWMCNT0
W
R
PWMCNT1
W
R
PWMCNT2
W
R
PWMCNT3
W
R
PWMCNT4
W
R
PWMCNT5
W
R
PWMPER0
W
R
PWMPER1
W
R
PWMPER2
W
R
PWMPER3
W
R
PWMPER4
W
R
PWMPER5
W
R
PWMDTY0
W
R
PWMDTY1
W
R
PWMDTY2
W
R
PWMDTY3
W
R
PWMDTY4
W
R
PWMDTY5
W
R
PWMSDN
W
R
Reserved
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
Bit 7
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 0
0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
PWMIF
PWMIE
0
PWM5IN
PWM5INL
PWM5
ENA
0
0
0
0
0
0
0
PWMLVL
PWRSTRT
0
0
S12P-Family Reference Manual, Rev. 1.13
554
Freescale Semiconductor
Detailed Register Address Map
0x00C8-0x00CF Serial Communication Interface (SCI) Map
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R
0x00C8
SCIBDH(1)
IREN
TNP1
TNP0
SBR12
SBR11
W
R
SBR7
SBR6
SBR5
SBR4
SBR3
0x00C9
SCIBDL1
W
R
LOOPS
SCISWAI
RSRC
M
WAKE
0x00CA
SCICR11
W
R
0
0
0
0
RXEDGIF
0x00C8 SCIASR1(2)
W
R
0
0
0
0
RXEDGIE
0x00C9
SCIACR12
W
R
0
0
0
0
0
0x00CA
SCIACR22
W
R
0x00CB
SCICR2
TIE
TCIE
RIE
ILIE
TE
W
R
TDRE
TC
RDRF
IDLE
OR
0x00CC
SCISR1
W
R
0
0
0x00CD
SCISR2
AMAP
TXPOL
RXPOL
W
R
R8
0
0
0
0x00CE
SCIDRH
T8
W
R
R7
R6
R5
R4
R3
0x00CF
SCIDRL
W
T7
T6
T5
T4
T3
1. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one
Bit 2
Bit 1
Bit 0
SBR10
SBR9
SBR8
SBR2
SBR1
SBR0
ILT
PE
PT
BERRV
BERRIF
BKDIF
BERRIE
BKDIE
BERRM1
BERRM0
BKDFE
RE
RWU
SBK
NF
FE
PF
BRK13
TXDIR
0
0
0
R2
T2
R1
T1
R0
T0
0
RAF
0x00D0-0x00D7 Reserved
Address
Name
0x00D00x00D7
Reseved
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0x00D8-0x00DF Serial Peripheral Interface (SPI) Map
Address
Name
0x00D8
SPICR1
0x00D9
SPICR2
0x00DA
SPIBR
0x00DB
SPISR
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
MODFEN
BIDIROE
SPISWAI
SPC0
SPR2
SPR1
SPR0
0
0
0
0
0
SPIF
XFRW
0
SPPR2
SPPR1
SPPR0
0
SPTEF
MODF
0
0
0
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
555
Detailed Register Address Map
0x00D8-0x00DF Serial Peripheral Interface (SPI) Map
Address
Name
0x00DC
SPIDRH
0x00DD
SPI0DRL
0x00DE
Reserved
0x00DF
Reserved
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R15
T15
R7
T7
0
R14
T14
R6
T6
0
R13
T13
R5
T5
0
R12
T12
R4
T4
0
R11
T11
R3
T3
0
R10
T10
R2
T2
0
R9
T9
R1
T1
0
R8
T8
R0
T0
0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0x00E0-0x00FF Reserved
Address
Name
0x00E00x00FF
Reserved
R
W
0x0100-0x0113 NVM Contol Register (FTMRC) Map
Address
Name
0x0100
FCLKDIV
0x0101
FSEC
0x0102
FCCOBIX
0x0103
FRSV0
0x0104
FCNFG
0x0105
FERCNFG
0x0106
FSTAT
0x0107
FERSTAT
0x0108
FPROT
0x0109
DFPROT
0x010A
FCCOBHI
0x010B
FCCOBLO
0x010C
FRSV1
Bit 7
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FDIV6
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
KEYEN1
KEYEN0
RNV5
RNV4
RNV3
RNV2
SEC1
SEC0
0
0
0
0
0
CCOBIX2
CCOBIX1
CCOBIX0
0
0
0
0
0
0
0
0
0
0
0
0
FDFD
FSFD
0
0
0
0
0
DFDIE
SFDIE
ACCERR
FPVIOL
MGBUSY
RSVD
0
0
0
0
FPHDIS
FPHS1
FPHS0
0
0
0
CCOB15
CCOB14
CCOB13
CCOB7
CCOB6
0
0
FDIVLD
CCIE
0
CCIF
0
FPOPEN
DPOPEN
0
0
RNV6
IGNSF
MGSTAT1 MGSTAT0
DFDIF
SFDIF
FPLDIS
FPLS1
FPLS0
DPS3
DPS2
DPS1
DPS0
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
0
0
0
0
0
0
S12P-Family Reference Manual, Rev. 1.13
556
Freescale Semiconductor
Detailed Register Address Map
0x0100-0x0113 NVM Contol Register (FTMRC) Map
Address
Name
0x010D
FRSV2
0x010E
FRSC3
0x010F
FRSV4
0x0110
FOPT
0x0111
FRSV5
0x0112
FRSV6
0x0113
FRSV7
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0114-0x011F Reserved
Address
Name
0x01140x011F
Reserved
R
W
0x0120 Interrupt Vector Base Register
Address
0x0120
Name
IVBR
Bit 7
Bit 6
R
W
IVB_ADDR[7:0]
0x0121-0x013F Reserved
Address
Name
0x01140x011F
Reserved
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIME
WUPE
SLPRQ
INITRQ
SLPAK
INITAK
BRP1
BRP0
0x0140-0x017F MSCAN Map
Address
Name
0x0140
CAN0CTL0
0x0141
CAN0CTL1
0x0142
CAN0BTR0
Bit 7
R
RXFRM
W
R
CANE
W
R
SJW1
W
RXACT
CSWAI
SYNCH
CLKSRC
LOOPB
LISTEN
BORM
WUPM
SJW0
BRP5
BRP4
BRP3
BRP2
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
557
Detailed Register Address Map
0x0140-0x017F MSCAN Map
Address
Name
0x0143
CAN0BTR1
0x0144
CAN0RFLG
0x0145
CAN0RIER
0x0146
CAN0TFLG
0x0147
CAN0TIER
0x0148
CAN0TARQ
0x0149
CAN0TAAK
0x014A
CAN0TBSEL
0x014B
CAN0IDAC
0x014C
Reserved
0x014D
CAN0MISC
0x014E
CAN0RXERR
0x014F
CAN0TXERR
0x01500x0153
CAN0IDAR0CAN0IDAR3
0x0154- CAN0IDMR00x0157 CAN0IDMR3
0x01580x015B
CAN0IDAR4CAN0IDAR7
0x015C- CAN0IDMR40x015F CAN0IDMR7
0x01600x016F
CAN0RXFG
0x01700x017F
CAN0TXFG
Bit 7
R
SAMP
W
R
WUPIF
W
R
WUPIE
W
R
0
W
R
0
W
R
0
W
R
0
W
R
0
W
R
0
W
R
0
W
R
0
W
R RXERR7
W
R TXERR7
W
R
AC7
W
R
AM7
W
R
AC7
W
R
AM7
W
R
W
R
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
RSTAT1
RSTAT0
TSTAT1
TSTAT0
OVRIF
RXF
CSCIE
RSTATE1
RSTATE0
TSTATE1
TSTATE0
OVRIE
RXFIE
0
0
0
0
TXE2
TXE1
TXE0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
0
0
0
0
ABTRQ2
ABTRQ1
ABTRQ0
0
0
0
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
TX2
TX1
TX0
IDAM1
IDAM0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
0
0
0
0
0
0
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CSCIF
0
BOHOLD
FOREGROUND RECEIVE BUFFER
(SeeTable )
FOREGROUND TRANSMIT BUFFER
(SeeTable )
S12P-Family Reference Manual, Rev. 1.13
558
Freescale Semiconductor
Detailed Register Address Map
MSCAN Foreground Receive and Transmit Buffer Layout
Address
0xXXX0
0xXXX1
0xXXX2
0xXXX3
Name
Extended ID
Standard ID
CANxRIDR0
Extended ID
Standard ID
CANxRIDR1
Extended ID
Standard ID
CANxRIDR2
Extended ID
Standard ID
CANxRIDR3
0xXXX4- CANxRDSR00xXXXB CANxRDSR7
0xXXXC
CANRxDLR
0xXXXD
Reserved
0xXXXE CANxRTSRH
0xXXXF
0xXX10
0xXX0x
XX10
0xXX12
0xXX13
CANxRTSRL
Extended ID
CANxTIDR0
Standard ID
Extended ID
CANxTIDR1
Standard ID
Extended ID
CANxTIDR2
Standard ID
Extended ID
CANxTIDR3
Standard ID
0xXX14- CANxTDSR0–
0xXX1B CANxTDSR7
0xXX1C
CANxTDLR
0xXX1D
CANxTTBPR
R
R
W
R
R
W
R
R
W
R
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID28
ID10
ID27
ID9
ID26
ID8
ID25
ID7
ID24
ID6
ID23
ID5
ID22
ID4
ID21
ID3
ID20
ID2
ID19
ID1
ID18
ID0
SRR=1
RTR
IDE=1
IDE=0
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID20
ID19
ID18
SRR=1
IDE=1
ID17
ID16
ID15
ID2
ID1
ID0
RTR
IDE=0
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
PRIO3
PRIO2
PRIO1
PRIO0
PRIO7
PRIO6
PRIO5
PRIO4
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
559
Detailed Register Address Map
MSCAN Foreground Receive and Transmit Buffer Layout
Address
0xXX1E
0xXX1F
Name
R
CANxTTSRH
W
R
CANxTTSRL
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0x0180-023F Reserved
Address
Name
0x01800x023F
Reserved
R
W
0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4
Address
Name
0x0240
PTT
0x0241
PTIT
0x0242
DDRT
0x0243
RDRT
0x0244
PERT
0x0245
PPST
0x0246
Reserved
0x0247
PTTRR
Bit 7
R
PTT7
W
R
PTIT7
W
R
DDRT7
W
R
RDRT7
W
R
PERT7
W
R
PPST7
W
R
0
W
R
PTTRR7
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
PTTRR6
PTTRR5
PTTRR4
PTTRR2
PTTRR1
PTTRR0
0
S12P-Family Reference Manual, Rev. 1.13
560
Freescale Semiconductor
Detailed Register Address Map
0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4
Address
Name
0x0248
PTS
0x0249
PTIS
0x024A
DDRS
0x024B
RDRS
0x024C
PERS
0x024D
PPSS
0x024E
WOMS
0x024F
Reserved
0x0250
PTM
0x0251
PTIM
0x0252
DDRM
0x0253
RDRM
0x0254
PERM
0x0255
PPSM
0x0256
WOMM
0x0257
MODRR
0x0258
PTP
0x0259
PTIP
0x025A
DDRP
0x025B
RDRP
0x025C
PERP
0x025D
PPSP
0x025E
PIEP
0x025F
PIFP
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
DDRM7
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
RDRM7
RDRM6
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
WOMM7
WOMM6
WOMM5
WOMM4
WOMM3
WOMM2
WOMM1
WOMM0
MODRR7
MODRR6
0
0
0
0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSS0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
0
MODRR4
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
561
Detailed Register Address Map
0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4
Address
Name
0x0260
Reserved
0x0261
Reserved
0x0262
Reserved
0x0263
Reserved
0x0264
Reserved
0x0265
Reserved
0x0266
Reserved
0x0267
Reserved
0x0268
PTJ
0x0269
PTIJ
0x026A
DDRJ
0x026B
RDRJ
0x026C
PERJ
0x026D
PPSJ
0x026E
PIEJ
0x026f
PIFJ
0x0270
PT0AD0
0x0271
PT1AD0
0x0272
DDR0AD0
0x0273
DDR1AD0
0x0274
RDR0AD0
0x0275
RDR1AD0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
0
0
0
0
0
0
0
0
R
W
R
W
R
W
R
W
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTJ7
PTJ6
0
0
0
PTJ2
PTJ1
PTJ0
PTIJ7
PTIJ6
0
0
0
PTIJ12
PTIJ1
PTIJ0
DDRJ7
DDRJ6
0
0
0
DDRJ2
DDRJ1
DDRJ0
RDRJ7
RDRJ6
0
0
0
RDRJ2
RDRJ1
RDRJ0
PERJ7
PERJ6
0
0
0
PERJ2
PERJ1
PERJ0
PPSJ7
PPSJ6
0
0
0
PPSJ2
PPSJ1
PPSJ0
PIEJ7
PIEJ6
0
0
0
PIEJ2
PIEJ1
PIEJ0
PIFJ7
PIFJ6
0
0
0
PIFJ2
PIFJ1
PIFJ0
PT0AD0
7
PT1AD0
7
PT0AD0
6
PT1AD0
6
PT0AD0
5
PT1AD0
5
PT0AD0
4
PT1AD0
4
PT0AD0
3
PT1AD0
3
PT0AD0
2
PT1AD0
2
PT0AD0
1
PT1AD0
1
PT0AD0
0
PT1AD0
0
DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0 DDR0AD0
7
6
5
4
3
2
1
0
DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0
7
6
5
4
3
2
1
0
RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0 RDR0AD0
7
6
5
4
3
2
1
0
RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0
7
6
5
4
3
2
1
0
S12P-Family Reference Manual, Rev. 1.13
562
Freescale Semiconductor
Detailed Register Address Map
0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4
Address
Name
0x0276
PER0AD0
0x0277
PER1AD0
0x02780x027F
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0 PER0AD0
7
6
5
4
3
2
1
0
W
R PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0
7
6
5
4
3
2
1
0
W
R
0
0
0
0
0
0
0
0
W
0x0280-0x02EF Reserved
Address
0x02800x02EF
Name
Reserved
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 1
Bit 0
HTIE
HTIF
LVIE
LVIF
APIE
APIF
0
0
0x02F0-0x02FF Clock and Power Management Unit (CPMU) Map 2 of 2
Address
Name
0x02F0
CPMUHTCL
0x02F1
CPMULVCTL
0x02F2 CPMUAPICTL
0x02F3
VREGAPITR
0x02F4
CPMUAPIRH
0x02F5
CPMUAPIRL
0x02F6
Reserved
0x02F7
CPMUHTTR
0x02F8
CPMU
IRCTRIMH
0x02F9
CPMU
IRCTRIML
0x02FA
CPMUOSC
0x02FB
CPMUPROT
0x02FC
Reserved
Bit 7
R
0
W
R
0
W
R
APICLK
W
R
APITR5
W
R
APIR15
W
R
APIR7
W
R
0
W
R
HTOEN
W
R
W
R
W
R
OSCE
W
R
0
W
R
0
W
Bit 6
0
Bit 5
VSEL
0
0
0
0
APITR4
Bit 4
0
Bit 3
HTEN
Bit 2
HTDS
0
0
LVDS
APIFES
APIEA
APIFE
APITR3
APITR2
APITR1
APITR0
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
0
0
0
0
0
0
0
0
0
0
HTTR3
HTTR2
HTTR1
HTTR0
0
0
TCTRIM[3:0]
IRCTRIM[9:8]
IRCTRIM[7:0]
OSCBW
0
OSCFILT[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
PROT
0
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
563
Detailed Register Address Map
0x0300-0x03FF Reserved
Address
0x03000x03FF
Name
Reserved
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
S12P-Family Reference Manual, Rev. 1.13
564
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