MC9S12XDT512CAAR

Freescale Semiconductor Product Brief 9S12XDFAMPP Rev. 2.16, 27-May-2006 MC9S12XD Family 16-bit Microprocessor Family (covers MC9S12XD64 through MC9S12XDP512 and MC3S12XDT256/MC3S12XDG128) Introduction Targeted at automotive multiplexing applications, the MC9S12XD Family will deliver 32-bit performance with all the advantages and efficiencies of a 16-bit MCU. The S12X is designed to retain the low cost, low power consumption, excellent EMC performance and code-size efficiency advantages enjoyed by users of Freescale's previous 16-bit MC9S12 MCU family. Based around an enhanced S12 core, the MC9S12XD Family will deliver two to five times the performance of a 25 MHz S12 whilst retaining a high degree of pin and code compatibility with the original S12D - family. The MC9S12XD Family features the performance boosting XGATE co-processor. The XGATE, which is programmable in "C" language, has an instruction set which is optimized for data movement, logic and bit manipulation instructions. It runs at twice the bus frequency of the S12X and off-loads the CPU by providing high speed data transfer (and data processing) between any peripheral module, RAM and I/O ports. This is particularly useful in applications such as automotive gateways where there are multiple busses carrying heavy data traffic which would otherwise exert a heavy interrupt/processing load on the CPU. © Freescale Semiconductor, Inc., 2005. All rights reserved. Features The MC9S12XD Family will feature an enhanced MSCAN module which, when used in conjunction with XGATE, delivers FullCAN performance with virtually unlimited number of mailboxes and retains backwards compatibility with the MSCAN module featured on previous S12 products. Memory options will range from 64 Kbytes to 512 Kbytes of Freescale's industry-leading, full automotive spec SG-Flash with additional integrated EEPROM. In addition to the rich S12 peripheral set, the MC9S12XD Family will feature more RAM, extra A/D channels, new timer features and additional LIN-compatible SCI ports compared with the original S12 DFamily. The MC9S12XD Family also features a new flexible interrupt handler which allows multilevel nested interrupts. The MC9S12XD Family has full 16-bit data paths throughout. The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to external memories. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. System power consumption is further improved with the new “fast exit from STOP mode” feature and an ultra low power wakeup timer. In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt capability allowing wakeup from STOP or WAIT mode. The MC9S12XD Family will be available in 144-pin LQFP (with optional external bus), 112-pin, and 80-pin options. Features Features of the MC9S12XD Family are listed here. Please see Table 1 for memory options and Table 2 for the peripheral features that are available on the different family members. 16-bit CPU12X Enhanced Interrupt Module • Upward compatible with MC9S12 instruction set • Enhanced indexed addressing • Additional (superset) instructions to improve 32-bit calculations and semaphore handling • Access large data segments independent of PPAGE • Eight levels of nested interrupt • Flexible assignment of interrupt sources to each interrupt level. • One non-maskable high priority interrupt (XIRQ) • Wakeup interrupt inputs – IRQ and non-maskable XIRQ MC9S12XD Family, Rev. 2.16 2 Freescale Semiconductor Features XGATE • Programmable, high performance I/O co-processor module — up to 80 MIPS RISC performance • Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states • Performs logical, shifts, arithmetic, and bit operations on data • Enables FullCAN capability when used in conjunction with MSCAN module • Full LIN master or slave capability when used in conjunction with the six integrated LIN SCI modules • Can interrupt the HCS12X CPU signalling transfer completion • Triggers from any hardware module as well as from the CPU possible • 64K, 128K, 256K, 384K and 512K byte Flash • 128K and 256K ROM • Flash General Features – Automated program and erase algorithm – Fast sector erase and word program operation – 2-stage command pipeline for faster multi-word program times – Sector erase abort feature for critical interrupt response – Protection scheme to prevent accidental program or erase – Automated program and erase algorithm – Fast sector erase and word program operation – 2-stage command pipeline for faster multi-word program times – Sector erase abort feature for critical interrupt response – Protection scheme to prevent accidental program or erase • 4K, 8K, 12K, 14K, 16K, 20K, 32K Byte RAM • Loop control Pierce oscillator using a 0.5 MHz to 16 MHz crystal • Option for full-swing Pierce without internal feedback resistor using a 0.5 MHz to 40 MHz crystal • Current gain control on amplitude output – Signal with low harmonic distortion – Low power – Good noise immunity – Eliminates need for external current limiting resistor • Transconductance sized for optimum start-up margin for typical crystals • Clock monitor Memory Options Oscillator (OSC_LCP) MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 3 Features Clock and Reset Generator (CRG) Non-Multiplexed External Bus (144 Pin package only) Analog-to-Digital Converter (ATD) Enhanced Capture Timer (ECT) • Phase-locked-loop clock frequency multiplier – Reference divider – Automatic bandwidth control mode for low-jitter operation – Automatic frequency lock detector • Fast wakeup from STOP in self clock mode for power saving and immediate program execution • Computer operating properly (COP) watchdog with optional safety window to initialize timeout counter • Real time interrupt for task scheduling purposes or cyclic wakeup from low power modes • System reset generation • 16 bit data • Support for external WAIT input or internal wait cycles to adapt MCU speed to peripheral speed requirements • Up to four chip select outputs to select 16K, 1M, 2M and 4M byte address spaces • Supports glue-less interface to popular asynchronous RAMs and Flash devices • External address space 4M byte for data and program space • Programmable sample time • Left/right, signed/unsigned result data • Continuous conversion mode • Multiple channel scans • Pins can also be used as digital I/O • Eight 16-bit channels for input capture or output compare • One 16-bit free-running counter with 8-bit precision prescaler • One 16-bit modulus down counter with 8-bit precision prescaler • Four 8-bit or two 16-bit pulse accumulators • Four channels have enhanced input capture capabilities: – Delay counter for noise immunity – 16-bit capture buffer – 8-bit pulse accumulator buffer • Four channel x 24-bit modulus down-count timers – Timeout interrupt – Timeout peripheral trigger • Start of timers can be aligned Periodic Interrupt Timer (PIT) MC9S12XD Family, Rev. 2.16 4 Freescale Semiconductor Features Pulse Width Modulator (PWM) Multi-scalable Controller Area Networks (MSCAN) Serial Peripheral Interface (SPI) Serial Communication Interfaces (SCI) • Eight channel x 8-bit or four channel x 16-bit pulse width modulator • Programmable period and duty cycle per channel • Center-aligned or left-aligned outputs • Programmable clock select logic with a wide range of frequencies • Up to five MSCAN modules (see ) • CAN 2.0 A, B software compatible – Standard and extended data frames – 0–8 bytes data length – Programmable bit rate up to 1 Mbps • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization • Flexible identifier acceptance filter programmable as: – 2 x 32-bit – 4 x 16-bit – 8 x 8-bit • Wakeup with integrated low-pass filter option • Loop back for self test • Listen-only mode to monitor CAN bus • Bus-off recovery by software intervention or automatically • 16-bit time stamp of transmitted/received messages • FullCAN capability when used in conjunction with XGATE • Up to three SPI modules (see ) • Full-duplex or single-wire bidirectional • Double-buffered transmit and receive • Master or slave mode • MSB-first or LSB-first shifting • Serial clock phase and polarity options • Up to six SCI modules (see ) • Full-duplex or single wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection • Programmable character length • Programmable polarity for transmitter and receiver • Receive wakeup on active edge • Break detect and transmit collision detect supporting LIN MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 5 Features Inter IC Module (IIC) • Up to two IIC modules (see ) • Compatible with I2C Bus standard • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • supports 400 Kbps • Background Debug (BDM) Debugger (XDBG) – – – Non-intrusive memory access commands Supports in-circuit programming of on-chip non-volatile memory Supports security – – Each can monitor CPU or XGATE busses A and C compares 23-bit address bus and 16-bit data bus with mask register Three modes: simple address/data match, inside address range or outside address range – • System Protection Input/Output Package Options • Power-on reset (POR) • with interrupt or reset • up to 117 general-purpose input/output (I/O) pins depending on the package option and 2 input-only pins • Hysteresis and configurable pullup/pulldown device on all input pins • Configurable drive strength on all output pins • 144-pin low-profile quad flat-pack (LQFP) • 112-pin low-profile quad flat-pack (LQFP) • 80-pin quad flat-pack (QFP) MC9S12XD Family, Rev. 2.16 6 Freescale Semiconductor Features • Ambient temperature range -40°C to 125°C • Temperature options: – -40°C to 85°C – -40°C to 105°C – -40°C to 125°C • Supply voltage 3.15V to 5.5V • Internal voltage regulator providing 2.5 V logic supply – 40 MHz maximum CPU bus frequency in single chip mode – 80 MHz maximum XGATE bus frequency Operating Conditions MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 7 MC9S12XD Family Block Diagram MC9S12XD Family Block Diagram MC9S12XD Family, Rev. 2.16 8 Freescale Semiconductor MC9S12XD Family Block Diagram Digital Supply 2.5V VDD1,2 VSS1,2 CAN0 CAN1 CAN2 CAN3 CAN4 SCI2 PLL Supply 2.5V VDDPLL VSSPLL IIC1 IIC0 Analog Supply 3-5V DDRC PTC VDDA VSSA PWM I/O Supply 3-5V VDDX1,2 VSSX1,2 Voltage Regulator 3-5V DDRD PTD VDDR1,2 VSSR1,2 SCI4 SCI5 SPI1 RXD TXD RXD TXD SPI2 SDA SCL SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS KWJ0 KWJ1 KWJ2 KWJ4 KWJ5 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 DDRAD1 & AD1 PTT PTS SPI0 MISO MOSI SCK SS RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXD TXD PTM SCI1 VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PJ0 CS3 PJ1 PJ2 CS1 PJ4 CS0 PJ5 CS2 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 Signals shown in Bold-Italics are neither available on the 112 Pin nor on the 80 Pin Package Option Signals shown in Bold are not available on the 80 Pin Package DDRB PTB Non-Multiplexed External Bus Interface (EBI) SCI3 RXD TXD SCI0 PTJ DDRA PTA Timer 4 channel 16 bit with Prescaler for internal timebases Enhanced Capture Timer PTP XIRQ IRQ R/W/WE LSTRB/LDS/EROMCTL ECLK MODA/RE/TAGLO MODB/TAGHI ECLKX2/XCLKS IQSTAT0 IQSTAT1 IQSTAT2 IQSTAT3 8 Bit PPAGE ACC0 Allows 4MByte ACC1 Program space ACC2 ROMCTL/EWAIT XGATE Peripheral Co-Processor PTH Periodic Interrupt COP Watchdog Clock Monitor Breakpoints DDRT Enhanced Multilevel Interrupt Module DDRS Clock and Reset Generation Module CPU12X AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD DDRM DDRK PTK ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 EWAIT ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 UDS ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PLL DDRE XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST Single-wire Background Debug Module PTE BKGD Voltage Regulator PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 DDRJ VDDR VSSR VREGEN VDD1,2 VSS1,2 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VRH VRL VDDA VSSA DDRP 4K/2K/1K Byte EEPROM Module to Port Routing 32K/20K/16K/14K/12K/8K/4K Byte RAM ATD1 DDRH VRH VRL VDDA VSSA ATD0 DDRAD0 & AD0 512K/384K/256k/128K/64K Byte Flash MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 9 MC9S12XD Family Block Diagram Table 1. Package and Memory Options of MC9S12XD Family Members Device Package Flash 144 LQFP RAM EEPROM ROM 32K 9S12XDP512 112 LQFP 144 LQFP 9S12XDT512 512K 112 LQFP 20K 80 QFP 144 LQFP 9S12XDT384 112 LQFP 384K 20K 80 QFP 144 LQFP 9S12XDQ256 4K 112 LQFP 80 QFP 16K 144 LQFP 9S12XDT256 112 LQFP 256K 80 QFP 144 LQFP 9S12XD256 112 LQFP 14K 80 QFP 144 LQFP 3S12XDT256 112 LQFP 16K (1) 256K 80 QFP 112 LQFP 9S12XDG128 128K 2K 80 QFP 12K 112 LQFP (1) 3S12XDG128 128K 80 QFP 112 LQFP 9S12XD128 128K 8K 2K 64K 4K 1K 80 QFP 9S12XD64 80 QFP NOTES: 1. No EEPROM is available on ROM versions. MC9S12XD Family, Rev. 2.16 10 Freescale Semiconductor MC9S12XD Family Block Diagram Table 2. Peripheral Options of MC9S12XD Family Members Device Package XGATE CAN SCI SPI IIC ECT PIT A/D I/O 144LQFP 5 6 3 2 8 4 2/24 119 112LQFP 5 6 3 1 8 4 2/16 91 144LQFP 3 6 3 1 8 4 2/24 119 112LQFP 3 6 3 1 8 4 2/16 91 80QFP 3 2 3 1 8 4 1/8 59 144LQFP 3 4 3 1 8 4 2/24 119 112LQFP 3 4 3 1 8 4 2/16 91 80QFP 3 2 3 1 8 4 1/8 59 144LQFP 4 4 3 1 8 4 2/24 119 4 4 3 1 8 4 2/16 91 80QFP 4 2 3 1 8 4 1/8 59 144LQFP 3 4 3 1 8 4 2/24 119 112LQFP 3 4 3 1 8 4 2/16 91 80QFP 3 2 3 1 8 4 1/8 59 144LQFP 1 4 3 1 8 4 2/24 119 112LQFP 1 4 3 1 8 4 2/16 91 80QFP 1 2 3 1 8 4 1/8 59 144LQFP 3 4 3 1 8 4 2/24 119 112LQFP 3 4 3 1 8 4 2/16 91 80QFP 3 2 3 1 8 4 1/8 59 112LQFP 2 2 2 1 8 4 1/16(2) 91 80QFP 2 2 2 1 8 4 1/8 59 112LQFP 2 2 2 1 8 4 1/16(2) 91 2 2 2 1 8 4 1/8 59 112LQFP 1 2 2 1 8 4 1/16(2) 91 80QFP 1 2 2 1 8 4 1/8 59 80QFP 1 2 2 1 8 2 1/8 59 9S12XDP512 9S12XDT512 9S12XDT384 9S12XDQ256 112LQFP yes 9S12XDT256 9S12XD256 3S12XDT256 9S12XDG128 3S12XDG128 80QFP yes(1) 9S12XD128 9S12XD64 NOTES: 1. Can execute code only from RAM 2. ATD1 routed to PAD00-15 instead of PAD08-23. MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 11 MC9S12XD Family Block Diagram Pinout explanations: • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output. – 144 Pin Packages: Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only, H = 8, J = 7, K = 8, M = 8, P = 8, S = 8, T = 8, PAD = 24 25 inputs provide Interrupt capability (H =8, P= 8, J = 7, IRQ, XIRQ) – 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) – 80 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ) • CAN0 can be routed under software control from PM[1:0] to pins PM[3:2] or PM[5:4] or PJ[7:6]. • CAN4 pins are shared between IIC0 pins. • CAN4 can be routed under software control from PJ[7:6] to pins PM[5:4] or PM[7:6]. • Versions with 5 CAN modules will have CAN0, CAN1, CAN2, CAN3 and CAN4 • Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4 • Versions with 3 CAN modules will have CAN0, CAN1 and CAN4. • Versions with 2 CAN modules will have CAN0 and CAN4. • Versions with 1 CAN modules will have CAN0 • Versions with 2 SPI modules will have SPI0 and SPI1. • Versions with 4 SCI modules will have SCI0, SCI1, SCI2 and SCI4. • Versions with 2 SCI modules will have SCI0 and SCI1. • Versions with 1 IIC module will have IIC0. • SPI0 can be routed to either Ports PS[7:4] or PM[5:2]. • SPI1 pins are shared with PWM[3:0]; In 144 and 112-pin versions, SPI1 can be routed under software control to PH[3:0]. • SPI2 pins are shared with PWM[7:4]; In 144 and 112-pin versions, SPI2 can be routed under software control to PH[7:4]. In 80-pin packages, SS-signal of SPI2 is not bonded out! MC9S12XD Family, Rev. 2.16 12 Freescale Semiconductor Pin Assignments Pin Assignments Table 3. Port and Peripheral Availability by Package Option Port 144 LQFP 112 LQFP 80 QFP Port AD/ADC Channels 24/24 16/16 8/8 Port A pins 8 8 8 Port B pins 8 8 8 Port C pins 8 0 0 Port D pins 8 0 0 Port E pins incl. IRQ/XIRQ input only 8 8 8 Port H pins 8 8 0 Port J pins 7 4 2 Port K pins 8 7 0 Port M pins 8 8 6 Port P pins 8 8 7 Port S pins 8 8 4 Port T pins 8 8 8 Sum of Ports 119 91 59 VDDX/VSSX 4/4 3/3 2/2 PJ1:0 IIC1 IIC0 SPI2 SPI1 SPI0 SCI5 SCI4 SCI3 SCI2 SCI1 SCI0 CAN4 CAN3 CAN2 CAN1 CAN0 Table 4. Peripheral–Port Cross Reference(1) X PJ3:2 PJ5:4 X PJ7:6 O PM1:0 X PM3:2 O PM5:4 O PM7:6 PS1:0 PS3:2 X X X O X O X O X X X PS7:4 X PH3:0 O MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 13 Pin Assignments PH5:4 X PH7:6 IIC1 IIC0 SPI2 SPI1 SPI0 SCI5 SCI4 SCI3 SCI2 SCI1 SCI0 CAN4 CAN3 CAN2 CAN1 CAN0 Table 4. Peripheral–Port Cross Reference(1) O X PP3:0 O X PP7:4 X NOTES: 1. X denotes the reset condition and O denotes a possible rerouting under software control Table 5. Pin-Out Summary(1) LQFP 144 LQFP 112 QFP 80 1 1 1 PP3 KWP3 PWM3 SS1 2 2 2 PP2 KWP2 PWM2 SCK1 3 3 3 PP1 KWP1 PWM1 MOSI1 4 4 4 PP0 KWP0 PWM0 MISO1 5 PJ2 KWJ2 CS1 6 PK6 ADDR22 NOACC Pin 2nd Function 3rd Function 7 5 PK3 ADDR19 8 6 PK2 ADDR18 IQSTAT2 9 7 PK1 ADDR17 IQSTAT1 10 8 PK0 ADDR16 IQSTAT0 11 9 5 PT0 IOC0 12 10 6 PT1 IOC1 13 11 7 PT2 IOC2 14 12 8 PT3 IOC3 15 13 9 VDD1 16 14 10 VSS1 17 15 11 PT4 IOC4 18 16 12 PT5 IOC5 19 17 13 PT6 IOC6 20 18 14 PT7 IOC7 21 19 PK5 ADDR21 22 20 PK4 ADDR20 23 21 PJ1 KWJ1 TXD2 24 22 PJ0 KWJ0 RXD2 4th Function 5th Function MC9S12XD Family, Rev. 2.16 14 Freescale Semiconductor Pin Assignments Table 5. Pin-Out Summary(1) LQFP 144 LQFP 112 QFP 80 25 23 15 Pin BKGD 2nd Function 3rd Function 4th Function MODC 26 VDDX2 27 VSSX2 28 PC0 DATA8 29 PC1 DATA9 30 PC2 DATA10 31 PC3 DATA11 32 24 16 PB0 ADDR0 33 25 17 PB1 ADDR1 34 26 18 PB2 ADDR2 35 27 19 PB3 ADDR3 36 28 20 PB4 ADDR4 37 29 21 PB5 ADDR5 38 30 22 PB6 ADDR6 39 31 23 PB7 ADDR7 40 PC4 DATA12 41 PC5 DATA13 42 PC6 DATA14 43 PC7 DATA15 UDS 44 32 PH7 KWH7 SS2 TXD5 45 33 PH6 KWH6 SCK2 RXD5 46 34 PH5 KWH5 MOSI2 TXD4 47 35 PH4 KWH4 MISO2 RXD4 48 36 24 PE7 XCLKS ECLKX2 49 37 25 PE6 MODB TAGHI 50 38 26 PE5 MODA TAGLO RE 51 39 27 PE4 ECLK 52 40 28 VSSR 53 41 29 VDDR 54 42 30 RESET 55 43 31 VDDPLL 56 44 32 XFC 57 45 33 VSSPLL 58 46 34 EXTAL 59 47 35 XTAL 60 48 36 TEST 61 49 SS1 TXD7 PH3 5th Function KWH3 MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 15 Pin Assignments Table 5. Pin-Out Summary(1) LQFP 144 LQFP 112 QFP 80 62 50 PH2 KWH2 SCK1 RXD7 63 51 PH1 KWH1 MOSI1 TXD6 64 52 PH0 KWH0 MISO1 RXD6 65 PD0 DATA0 66 PD1 DATA1 67 PD2 DATA2 68 PD3 DATA3 EROMCTL Pin 2nd Function 3rd Function 69 53 37 PE3 LSTRB LDS 70 54 38 PE2 RW WE 71 55 39 PE1 IRQ 72 56 40 PE0 XIRQ 73 57 41 PA0 ADDR8 74 58 42 PA1 ADDR9 75 59 43 PA2 ADDR10 76 60 44 PA3 ADDR11 77 61 45 PA4 ADDR12 78 62 46 PA5 ADDR13 79 63 47 PA6 ADDR14 80 64 48 PA7 ADDR15 81 VDDX3 82 VDDX3 83 PD4 DATA4 84 PD5 DATA5 85 PD6 DATA6 86 PD7 DATA7 87 65 49 VDD2 88 66 50 VSS2 89 67 51 PAD00 AN0 90 68 PAD08 AN8 91 69 PAD01 AN1 92 70 PAD09 AN9 93 71 PAD02 AN2 94 72 PAD10 AN8 95 73 PAD03 AN3 96 74 PAD11 AN11 97 75 PAD04 AN4 98 76 PAD12 AN12 52 53 54 55 4th Function 5th Function MC9S12XD Family, Rev. 2.16 16 Freescale Semiconductor Pin Assignments Table 5. Pin-Out Summary(1) LQFP 144 LQFP 112 QFP 80 99 77 56 100 78 101 79 102 80 103 81 104 82 Pin 2nd Function PAD05 AN5 PAD13 AN13 PAD06 AN6 PAD14 AN14 PAD07 AN7 PAD15 AN15 105 PAD16 AN16 106 PAD17 AN17 57 58 107 83 59 VDDA 108 84 60 VRH 109 85 61 VRL 110 86 62 VSSA 111 PAD18 AN18 112 PAD19 AN19 113 PAD20 AN20 114 PAD21 AN21 115 PAD22 AN22 116 PAD23 AN23 3rd Function 4th Function 117 87 PM7 TXCAN3 TXCAN4 TXD3 118 88 PM6 RXCAN3 RXCAN4 RXD3 119 89 63 PS0 RXD0 120 90 64 PS1 TXD0 121 91 65 PS2 RXD1 122 92 66 PS3 TXD1 123 93 PS4 MISO0 124 94 PS5 MOSI0 125 95 PS6 SCK0 126 96 PS7 SS0 127 97 67 VREGEN 128 98 68 PJ7 KWJ7 TXCAN4 SCL0 129 99 69 PJ6 KWJ6 RXCAN4 SDA0 130 PJ5 KWJ5 SCL1 CS2 131 PJ4 KWJ4 SDA1 CS0 5th Function 132 100 70 PM5 TXCAN2 TXCAN0 TXCAN4 SCK0 133 101 71 PM4 RXCAN2 RXCAN0 RXCAN4 MOSI0 134 102 72 PM3 TXCAN1 TXCAN0 SS0 135 103 73 PM2 RXCAN1 RXCAN0 MISO0 MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 17 Pin Assignments Table 5. Pin-Out Summary(1) LQFP 144 LQFP 112 QFP 80 136 104 74 PM1 TXCAN0 137 105 75 PM0 RXCAN0 138 106 76 VSSX1 139 107 77 VDDX1 140 108 141 109 142 110 143 111 144 112 Pin 2nd Function 3rd Function 4th Function PK7 ROMCTL EWAIT PP7 KWP7 PWM7 SCK2 PP6 KWP6 PWM6 SS2 79 PP5 KWP5 PWM5 MOSI2 80 PP4 KWP4 PWM4 MISO2 78 5th Function NOTES: 1. Table shows a superset of pin functions. Not all functions are available on all derivatives MC9S12XD Family, Rev. 2.16 18 Freescale Semiconductor 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0 PJ7/KWJ7/TXCAN4/SCL0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 PAD23/AN23 PAD22/AN22 PAD21/AN21 PAD20/AN20 PAD19/AN19 PAD18/AN18 VSSA VRL Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MC9S12XD Family 144 LQFP Pins shown in BOLD-ITALICS are bit available on the 112 LQFP nor on the 80 QFP Package Option Pins shown in BOLD are not available on the 80 QFP package 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VRH VDDA PAD17/AN17 PAD16/AN16 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 VDDX3 VSSX3 PA7/ADDR15 PA6/ADDR14 PA5/ADDR13 PA4/ADDR12 PA3/ADDR11 PA2/ADDR10 PA1/ADDR9 PA0/ADDR8 ADDR5/PB5 ADDR6/PB6 ADDR7/PB7 DATA12/PC4 DATA13/PC5 DATA14/PC6 DATA15/PC7 TXD5/SS2/KWH7/PH7 RXD5/SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 XCLKS/ECLK2X/PE7 TAGHI/MODB/PE6 RE/TAGLO/MODA/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PD0/DATA0 PD1/DATA1 PD2/DATA2 PD3/DATA3 EROMCTL/LDS/LSTRB/PE3 WE/RW/PE2 IRQ/PE1 XIRQ/PE0 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 CS1/KWJ2/PJ2 NOACC/ADDR22/PK6 ADDR19/PK3 IQSTAT2/ADDR18/PK2 IQSTAT1/ADDR17/PK1 IQSTAT0/ADDR16/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 ADDR21/PK5 ADDR20/PK4 TXD2/KWJ1/PJ1 RXD2/KWJ0/PJ0 MODC/BKGD VDDX2 VSSX2 DATA8/PC0 DATA9/PC1 DATA10/PC2 DATA11/PC3 UDS/ADDR0/PB0 ADDR1/PB1 ADDR2/PB2 ADDR3/PB3 ADDR4/PB4 Figure 1. MC9S12XD Family Pin Assignments for 144-pin LQFP Package MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 19 MC9S12XD Family 112LQFP Pins shown in BOLD are not available on the 80 QFP package 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB6 PB7 SS2/KWH7/PH7 SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 ECLK2X/XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PE3 PE2 IRQ/PE1 XIRQ/PE0 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 PK3 PK2 PK1 PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 PK5 PK4 TXD2/KWJ1/PJ1 RXD2/KWJ0/PJ0 MODC/BKGD PB0 PB1 PB2 PB3 PB4 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0 PJ7/KWJ7/TXCAN4/SCL0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4 PM7/TXCAN3/TXCAN4 VSSA VRL Pin Assignments Figure 2. MC9S12XD Family Pin Assignments for 112-pin LQFP Package MC9S12XD Family, Rev. 2.16 20 Freescale Semiconductor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12XD Family 80-Pin QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB6 PB7 XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL Pin Assignments Figure 3. MC9S12XD Family Pin Assignments for 80-pin QFP Package MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 21 Memory Maps Memory Maps $0000 2K Register Space $0800 $0C00 4K Bytes EEPROM 4 * 1K pages accessible through $0800 - $0BFF $1000 $2000 32K Bytes RAM 8 * 4K pages accessible through $1000 - $1FFF $4000 16K Fixed Flash EEPROM External $8000 16K Page Window 32 * 16K Flash EEPROM Pages $C000 16K Fixed Flash EEPROM $FF00 VECTORS VECTORS BDM NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP 2K, 4K, 8K or 16K Protected Boot Sector $FFFF Figure 4. MC9S12XD-Family Memory Map1 1. The memory Map shows the memory sizes of DP512 part. For memory configuration of other parts see Table 1. MC9S12XD Family, Rev. 2.16 22 Freescale Semiconductor Memory Maps Global Address $78_0000 DP512/ DT512 DT384 DQ256/ D256 128K 128K 128K DG128/ D128 D64 (PPAGE $E0) $7A_0000 (PPAGE $E8) 128K $7C_0000 (PPAGE $F0) $7E_0000 128K 128K 128K 128K (PPAGE $F8) 128K 128K 64K Shared XGATE/CPU area Not implemented Figure 5. MC9S12XD-Family Flash Configuration1, 2, 3, 4, 5 1. XGATE read access to Flash not possible on DG128/D128 and D64 2. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF 3. Program Pages available on DQ256/D256 are $E0 - $E7 and $F8 - $FF 4. Shared XGATE/CPU area on DP512/DT512/DT384 at global address $78_0800 to $78_FFFF (30Kbyte) 5. Shared XGATE/CPU area on DQ256/D256 at global address $78_0800 to $79_3FFF (46Kbyte) MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 23 Mechanical Package Dimensions Mechanical Package Dimensions 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 P J1 L M CL B V X G 140X B1 VIEW Y 36 VIEW Y V1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35. 73 37 72 N A1 S1 A S VIEW AB C 0.1 T θ2 144X SEATING PLANE θ2 T PLATING J AA F C2 0.05 R2 θ R1 0.08 M 0.25 BASE METAL D GAGE PLANE T L-M N SECTION J1-J1 (ROTATED 90 ° ) 144 PL (K) C1 E (Y) VIEW AB MILLIMETERS DIM MIN MAX A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 θ 0° θ1 0° 7° θ2 11° 13 ° θ1 (Z) Figure 6. 144-pin LQFP Mechanical Dimensions (case no. 918-03) MC9S12XD Family, Rev. 2.16 24 Freescale Semiconductor Mechanical Package Dimensions 0.20 T L-M N 4X PIN 1 DENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 AA J V1 57 29 F D 56 0.13 N M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 S1 A S C2 C VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. θ3 T θ R R2 R 0.25 R1 GAGE PLANE (K) C1 E θ1 (Y) (Z) VIEW AB DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA θ θ1 θ2 θ3 MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 ° 0° 7 ° 3 ° 13 ° 11 ° 11 ° 13 ° Figure 7. 112-pin LQFP Mechanical Dimensions (case no. 987) MC9S12XD Family, Rev. 2.16 Freescale Semiconductor 25 Mechanical Package Dimensions 41 60 61 B D D S V B P B 0.20 M C A-B L 0.05 D -B- 0.20 M H A-B -A- S S S 40 -A-,-B-,-DDETAIL A DETAIL A 21 80 1 A 0.20 M H A-B S F 20 -DD S 0.05 A-B J S 0.20 M C A-B S D S D M E DETAIL C C -H- -CSEATING PLANE N DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H M G U T DATUM -HPLANE R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5° 10 ° 0.13 0.17 0.325 BSC 0° 7° 0.13 0.30 16.95 17.45 0.13 --0° --16.95 17.45 0.35 0.45 1.6 REF MC9S12XD Family, Rev. 2.16 26 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. 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