MCF51AG128CLF

Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF51AG128 Rev. 5, 6/2010 MCF51AG128 MCF51AG128 ColdFire Microcontroller Covers: MCF51AG128 and MCF51AG96 The MCF51AG128 is a member of the ColdFire® family of 32-bit variable-length reduced instruction set (RISC) microcontroller. This document provides an overview of the MCF51AG128 series MCUs, focusing on its highly integrated and diverse feature set. The MCF51AG128 derivative are low-cost, low-power, and high-performance 32-bit ColdFire V1 microcontroller units (MCUs) designed for industrial and appliance applications. It is an ideal upgrade for designs based on the MC9S08AC128 series of 8-bit microcontrollers. The MCF51AG128 features the following functional units: • 32-bit Version 1 ColdFire® central processor unit (CPU) – Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V – Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM (0.76 DMIPS per MHz when running from flash) – Implements Coldfire Instruction Set Revision C (ISA_C) • On-chip memory – Up to 128 KB flash memory read/program/erase over full operating voltage and temperature – Up to 16 KB random access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Three ultra-low power stop modes and reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents • System Protection – Advanced independent clocked watchdog (WDOG) with features like, robust refresh mechanism, windowed mode, high granulation timeout, fast test of timeout, and always forces a reset – Additional external watchdog monitor (EWM) to help reset external circuits 80 LQFP 14 mm × 14 mm 48 LQFP 7 mm x 7mm – – – – 64 QFP 14 mm × 14 mm Low-voltage detection with reset or interrupt Separate low voltage warning with selectable trip points Illegal opcode and illegal address detection with reset Flash block protection for each array to prevent accidental write/erasure – Hardware CRC module to support fast cyclic redundancy checks • Debug Support – Single-wire back ground debug interface – Real-time debug support, with six hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured into a 1- or 2-level trigger – On-chip trace buffer provides programmable start/stop recording conditions – Support for real-time program (and optional partial data) trace using the debug visibility bus • DMA Controller – Four independently programmable DMA channels provide the means to directly transfer data between system memory and I/O peripherals – DMA enabled peripherals include IIC, SCI, SPI, FTM, HSCMP, ADC, RTC, and eGPIO, and the DMA request from these peripherals can be configured as DMA source or as an iEvent input • CF1_INTC – Support of 44 peripheral I/O interrupt requests and seven software (one per level) interrupt requests – Fixed association between interrupt request source, level and priority, up to two requests can be remapped to the highest maskable level and priority – Unique vector number for each interrupt source – Support for service routine interrupt acknowledge (software IACK) read cycles for improved system performance – Ability to mask any individual or all interrupt sources Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2010. All rights reserved. 64 LQFP 10 mm × 10 mm • System Clock Sources – Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Frequency-locked-loop (FLL) controlled by internal or external reference; trimmable internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 ºC) • Peripherals – ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single or continuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversion complete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation; selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardware triggers during ping-pong mode; on-chip temperature sensor – PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signal initiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORed together; pulsed output could be used for HSCMP windowing signal – iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use as interrupt requests, DMA transfer requests, or hardware triggers – FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for each complementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs or independent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which have write buffer can be synchronized; write protection for critical registers; backwards compatible with TPM – TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, output compare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt – CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value – HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator output; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltage reference from two internal DACs; support DMA transfer – IIC — Compatible with IIC bus standard and SMBus version 2 features; up to 100 kbps with maximum bus loading; multi-master operation; software programmable for one of 64 different serial clock frequencies; programmable slave address and glitch input filter; interrupt driven byte-by-byte data transfer; arbitration lost interrupt with automatic mode switching from master to slave; calling address identification interrupt; bus busy detection; broadcast and 10-bit address extension; address matching causes wake-up when MCU is in Stop3 mode; DMA support – SCI — Two serial communications interface modules with optional 13-bit break; full-duplex, standard non-return-to-zero (NRZ) format; double-buffered transmitter and receiver with separate enables; 13-bit baud rate selection with /32 fractional divide; interrupt-driven or polled operation; hardware parity generation and checking; programmable 8-bit or 9-bit character length; receiver wakeup by idle-line or address-mark; address match feature in receiver to reduce address-mark wakeup ISR overhead; 1/16 bit-time noise detection; DMA transmission for both transmit and receive – SPI — Two serial peripheral interfaces with full-duplex or single-wire bidirectional option; double-buffered transmitter and receiver; master or slave mode operation; selectable MSB-first or LSB-first shifting; 8-bit or 16-bit data modes; programmable transmit bit rate; receive data buffer hardware match feature; DMA transmission for transmit and receive • Input/Output – Up to 69 GPIOs and one Input-only pin – Interrupt or DMA request with selectable polarity on all input pins – Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins – Configurable slew rate and drive strength on all output pins – Independent pin value register to read logic level on digital pin – Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processor’s local 32-bit platform bus with set, clear, and faster toggle functionality MCF51AG128 ColdFire Microcontroller, Rev. 5 2 Freescale Semiconductor Table of Contents 1 2 3 4 5 6 MCF51AG128 Family Configurations . . . . . . . . . . . . . . . . . . . .4 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14 2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 2.4 Electrostatic Discharge (ESD) Protection Characteristics 16 2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21 2.7 High Speed Comparator (HSCMP) Electricals . . . . . . .23 2.8 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .23 2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.10 External Oscillator (XOSC) Characteristics . . . . . . . . .27 2.11 ICS Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.12.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .31 2.12.3 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . .32 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37 5.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .37 5.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .40 5.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.4 48-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 9. MCF51AG128 Series Device Comparison. . . . . . . . . . .4 MCF51AG128 Series Functional Units . . . . . . . . . . . . . .7 Pin Availability by Package Pin-Count. . . . . . . . . . . . . .12 Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .14 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .16 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 17 Table 10. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 21 Table 11.HSCMP Electrical Specifications. . . . . . . . . . . . . . . . . 23 Table 12.5V 12-bit ADC Operating Conditions. . . . . . . . . . . . . . 23 Table 13.5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14.Oscillator Electrical Specifications (Temperature Range = –40 to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15.ICS Frequency Specifications (Temperature Range = –40 to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18.SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . 32 Table 19.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 20.Orderable Part Number Summary. . . . . . . . . . . . . . . . 36 Table 21.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 List of Figures Figure 1. MCF51AG128 Series MCUs Block Diagram . . . . . . . . . 6 Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. 64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Typical IOH vs. VDD – VOH (Low Drive,PTxDSn = 0) . . 19 Figure 6. Typical IOH vs. VDD – VOH (High Drive, PTxDSn = 1) . 19 Figure 7. Typical IOL vs. VOL (Low Drive, PTxDSn = 0) . . . . . . . 20 Figure 8. Typical IOL vs. VOL (High Drive, PTxDSn = 1) . . . . . . . 20 Figure 9. Run Current at Different Conditions. . . . . . . . . . . . . . . 22 Figure 10.ADC Input Impedance Equivalency Diagram. . . . . . . 25 Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 31 Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 33 Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 33 Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 34 Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 34 MCF51AG128 ColdFire Microcontroller, Rev. 5 3 Freescale Semiconductor MCF51AG128 Family Configurations 1 MCF51AG128 Family Configurations 1.1 Device Comparison The following table compares the various device derivatives available within the MCF51AG128 series MCUs. Table 1. MCF51AG128 Series Device Comparison MCF51AG128 MCF51AG96 Feature 80-pin Flash memory size (KB) 64-pin 48-pin 80-pin 128 64-pin 48-pin 96 RAM size (KB) 16 ColdFire V1 core with BDM (background debug module) Yes HSCMP (analog comparator) 2 2 1 2 2 1 ADC (analog-to-digital converter) channels (12-bit) 24 19 12 24 19 12 2 2 1 1 1 No CRC (cyclic redundancy check) Yes DAC 2 2 1 DMA controller 4-ch iEvent (intelligent Event module) Yes EWM (External Watchdog Monitor) Yes WDOG (Watchdog timer) Yes RTC Yes DBG (debug module) Yes IIC (inter-integrated circuit) 1 1 No IRQ (interrupt request input) Yes INTC (interrupt controller) Yes LVD (low-voltage detector) Yes ICS (internal clock source) Yes OSC (crystal oscillator) Yes Port I/O1 69 53 39 69 53 39 RGPIO (rapid general-purpose I/O) 16 16 15 16 16 15 Yes No No SCI (serial communications interface) 2 SPI1 (serial peripheral interface) Yes SPI2 (serial peripheral interface) Yes No No FTM1 (flexible timer module) channels 62 FTM2 channels 62 MCF51AG128 ColdFire Microcontroller, Rev. 5 4 Freescale Semiconductor MCF51AG128 Family Configurations Table 1. MCF51AG128 Series Device Comparison (continued) MCF51AG128 MCF51AG96 Feature 80-pin 64-pin 48-pin TPM3 (timer pulse-width modulator) channels Debug Visibility Bus 1 2 80-pin 64-pin 48-pin Yes No No 2 Yes No No Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module. Some pins of FTMx might not be bonded on small package, therefore these channels could be used as soft timer only. 1.2 Block Diagram Figure 1 shows the connections between the MCF51AG128 series pins and modules. MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 5 RESET FTM1CLK FTM1* SIM IRQ/ TPMCLK FTM2CLK WDOG LVD * Port J: FTM2CH5 FTM2CH4 FTM2CH3 FTM2CH2 Port F: FTM2CH1 FTM2CH0 TPM3 Port B: or Port G: IRQ FTM2 FLASH 128 or 96 KB TPMCLK RAM 16 KB SCI2 Port C: RXD2 TXD2 SPI1 Port E: SS1 SPSCK1 MOSI1 MISO1 Port H: SS2 SPI2 SPSCK2 MOSI2 MISO2 Port F CRC ICS OSC Port G: EXTAL XTAL PTA7/ADP23 PTA6/MCLK PTA5/C2IN3 PTA4/C2IN2 PTA3/CMP2OUT PTA2/CIN1 PTA1/EWM_out PTA0/EWM_in PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTC6/FTM2FLT PTC5/RxD2 PTC4/SS2 PTC3/TxD2 PTC2/ADP8 PTC1/SDA PTC0/SCL PTD7/ADP7 PTD6/FTM1CLK/ADP0 PTD5/ADP1 PTD4/FTM2CLK/ADP2 PTD3/ADP5 PTD2/ADP6/CMP1OUT PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTE7/RGPIO7/SPSCK1 PTE6/RGPIO6/MOSI1 PTE5/RGPIO5/MISO1 PTE4/RGPIO4/SS1 PTE3/RGPIO3/FTM1CH1 PTE2/RGPIO2/FTM1CH0 PTE1/RGPIO1/RxD1 PTE0/RGPIO0/TxD1 PTF7/RGPIO15 PTF6/RGPIO14/FTM1FLT PTF5/RGPIO13/FTM2CH1 PTF4/RGPIO12/FTM2CH0 PTF3/RGPIO11/FTM1CH5 PTF2/RGPIO10/FTM1CH4 PTF1/RGPIO9/FTM1CH3 PTF0/RGPIO8/FTM1CH2 PTG6/XTAL PTG5/EXTAL PTG4/ADP3 PTG3/ADP4 PTG2/BKPT PTG1/PSTCLK1/TPM3CH1 PTG0/PSTCLK0/TPM3CH0 RTC DAC1 VREG IIC Port C: SDA SCL DAC2 EWM_in EWM_out Port E: RXD1 TXD1 Port J VDD VSS VSS Port E: RGPIO7 RGPIO6 RGPIO5 RGPIO4 RGPIO3 RGPIO2 RGPIO1 RGPIO0 SCI1 TPM3CH1 TPM3CH0 Port F: RGPIO15 RGPIO14 RGPIO13 RGPIO12 RGPIO11 RGPIO10 RGPIO9 RGPIO8 RGPIO Port F: FTM1CH5 FTM1CH4 FTM1CH3 FTM1CH2 Port E: FTM1CH1 FTM1CH0 Port B ADP22ADP19 Port A: ADP23 BKPT ColdFire V1 core + DMA + iEvent Port A: CMP2OUT CIN1 HSCMP2 C2IN2 C2IN3 Port C BDM Port B: ADP18ADP11 Port H: ADC Port D BKGD/MS Port J: DDATA3DDATA0 PST3VBUS PST0 Port G: PSTCLK Port G DBG Port D: CMP1OUT CIN1 C1IN2 HSCMP1 C1IN3 Port C,D,G: ADP10ADP0 Port E VREFH VREFL VDDA VSSA Port H VREFH VREFL VDDA VSSA Port A MCF51AG128 Family Configurations EWM PTH6/MISO2 PTH5/MOSI2 PTH4/SPSCK2 PTH3/ADP19/FTM2CH5 PTH2/ADP20/FTM2CH4 PTH1/ADP21/FTM2CH3 PTH0/ADP22/FTM2CH2 PTJ7/DDATA3/FTM2CH2 PTJ6/DDATA2/FTM2CH3 PTJ5/DDATA1/FTM2CH4 PTJ4/DDATA0//FTM2CH5 PTJ3/PST3 PTJ2/PST2 PTJ1/PST1 PTJ0/PST0 Figure 1. MCF51AG128 Series MCUs Block Diagram MCF51AG128 ColdFire Microcontroller, Rev. 5 6 Freescale Semiconductor MCF51AG128 Family Configurations 1.3 Features Table 2 describes the functional units of the MCF51AG128 series. Table 2. MCF51AG128 Series Functional Units Functional Unit Function CF1Core (V1 ColdFire core) Executes programs and interrupt handlers BDM (background debug module) Provides single pin debugging interface (part of the V1 ColdFire core) DBG (debug) Provides debugging and emulation capabilities (part of the V1 ColdFire core) VBUS (debug visibility bus) Allows for real-time program traces (part of the V1 ColdFire core) SIM (system integration module) Controls resets and chip level interfaces between modules Flash (flash memory) Provides storage for program code, constants, and variables RAM (random-access memory) Provides storage for program variables RGPIO (rapid general-purpose input/output) Allows for I/O port access at CPU clock speeds VREG (voltage regulator) Controls power management across the device LVD (low-voltage detect) Monitors internal and external supply voltage levels, and generates a reset or interrupt when the voltages are too low CF1_INTC (interrupt controller) Controls and prioritizes all device interrupts ADC (analog-to-digital converter) Measures analog voltages at up to 12 bits of resolution FTM1, FTM2 (flexible timer/pulse-width modulators) Provide a variety of timing-based features TPM3 (timer/pulse-width modulator) Provides a variety of timing-based features CRC (cyclic redundancy check) Accelerates computation of CRC values for ranges of memory HSCMP1, HSCMP2 (analog comparators) Compare two analog inputs DAC1, DAC2 (digital-to-analog converter) Provide programmable voltage reference for HSCMPx IIC (inter-integrated circuit) Supports standard IIC communications protocol ICS (internal clock source) Provides clocking options for the device, including a frequency-locked loop (FLL) for multiplying slower reference clock sources OSC (crystal oscillator) Allows a crystal or ceramic resonator to be used as the system clock source or reference clock for the FLL SCI1, SCI2 (serial communications interfaces) Serial communications UARTs capable of supporting RS-232 and LIN protocols SPI1, SPI2 (8/16-bit serial peripheral interfaces) Provide 8/16-bit 4-pin synchronous serial interface DMA Provides the means to directly transfer data between system memory and I/O peripherals iEvent Highly programmable module for creating combinational boolean outputs for use as interrupt requests, DMA transfer requests, or hardware triggers EWM (External Watchdog Monitor) Additional watchdog system to help reset external circuits MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 7 MCF51AG128 Family Configurations Table 2. MCF51AG128 Series Functional Units (continued) Functional Unit Function WDOG (Watchdog timer) keeps a watch on the system functioning and resets it in case of its failure RTC (Real Time Counter) Provides a constant time-base with optional interrupt MCF51AG128 ColdFire Microcontroller, Rev. 5 8 Freescale Semiconductor MCF51AG128 Family Configurations 1.4 Pin Assignments This section describes the pin assignments for the available packages. 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTG3/ADP4 PTD3/ADP5 PTD2/ADP6/CMP1OUT PTD7/ADP7 PTC2/ADP8 PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2/ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTH3/ADP19/FTM2CH5 PTH2/ADP20/FTM2CH4 PTH1/ADP21/FTM2CH3 PTH0/ADP22/FTM2CH2 PTA7/ADP23 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PTE4/RGPIO4/SS1 PTE5/RGPIO5/MISO1 PTE6/RGPIO6/MOSI1 PTE7/RGPIO7/SPSCK1 PTJ4/DDATA0/FTM2CH5 PTJ5/DDATA1/FTM2CH4 PTJ6/DDATA2/FTM2CH3 PTJ7/DDATA3/FTM2CH2 PTG0/PSTCLK0/TPM3CH0 VSS VDD PTG1/PSTCLK1/TPM3CH1 PTG2/BKPT PTA0/EWM_in PTA1/EWM_out PTA2/CIN1 PTA3/CMP2OUT PTA4/C2IN2 PTA5/C2IN3 PTA6/MCLK PTC0/SCL PTC1/SDA IRQ/TPMCLK PTF0/RGPIO8/FTM1CH2 PTF1/RGPIO9/FTM1CH3 PTF2/RGPIO10/FTM1CH4 PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTC6/FTM2FLT PTF7/RGPIO15 PTF5/RGPIO13/FTM2CH1 PTF6/RGPIO14/FTM1FLT PTJ0/PST0 PTJ1/PST1 PTJ2/PST2 PTJ3/PST3 PTE0/RGPIO0/TxD1 PTE1/RGPIO1/RxD1 PTE2/RGPIO2/FTM1CH0 PTE3/RGPIO3/FTM1CH1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTC5/RxD2 PTC3/TxD2 PTH6/MISO2 PTH5/MOSI2 PTH4/SPCK2 RESET BKGD/MS PTG6/XTAL PTG5/EXTAL VSS VDD VDDA VREFH VREFL VSSA PTC4/SS2 PTD6/FTM1CLK/ADP0 PTD5/ADP1 PTD4/FTM2CLK/ADP2 PTG4/ADP3 Figure 2 shows the pinout of the 80-pin LQFP. Note: Pin names in bold are not available in lower pin count packages. Figure 2. 80-Pin LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 9 MCF51AG128 Family Configurations 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTC5/RxD2 PTC3/TxD2 PTH5 RESET BKGD/MS PTG6/XTAL PTG5/EXTAL VSS VDD VDDA VREFH VREFL VSSA PTD6/FTM1CLK/ADP0 PTD5/ADP1 PTD4/FTM2CLK/ADP2 Figure 3 shows the pinout of the 64-pin LQFP and QFP. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin QFP 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTG3/ADP4 PTD3/ADP5 PTD2/ADP6/CMP1OUT PTD7/ADP7 PTC2/ADP8 PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2/ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTA7/ADP23 PTE4/RGPIO4/SS1 PTE5/RGPIO5/MISO1 PTE6/RGPIO6/MOSI1 PTE7/RGPIO7/SPSCK1 PTJ6/FTM2CH3 PTJ7/FTM2CH2 PTG0/TPM3CH0 VSS VDD PTA0/EWM_in PTA1/EWM_out PTA2/CIN1 PTA3/CMP2OUT PTA4/C2IN2 PTA5/C2IN3 PTA6/MCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTC0/SCL PTC1/SDA IRQ/TPMCLK PTF0/RGPIO8/FTM1CH2 PTF1/RGPIO9/FTM1CH3 PTF2/RGPIO10/FTM1CH4 PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTC6/FTM2FLT PTF7/RGPIO15 PTF5/RGPIO13/FTM2CH1 PTF6/RGPIO14/FTM1FLT PTE0/RGPIO0/TxD1 PTE1/RGPIO1/RxD1 PTE2/RGPIO2/FTM1CH0 PTE3/RGPIO3/FTM1CH1 Figure 3. 64-Pin QFP and LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 10 Freescale Semiconductor MCF51AG128 Family Configurations IRQ/TPMCLK PTF0/RGPIO8/FTM1CH2 PTF1/RGPIO9/FTM1CH3 PTF2/RGPIO10/FTM1CH4 PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTC6/FTM2FLT PTF7/RGPIO15 PTF5/RGPIO13/FTM2CH1 PTF6/RGPIO14/FTM1FLT 1 2 3 4 5 6 7 8 9 10 11 48 LQFP 12 36 35 34 33 32 31 30 29 28 27 26 25 PTD2/ADP6/CMP1OUT PTD1/ADP9/CMP1IN3 PTD0/ADP10/CMP1IN2 PTB7/ADP11 PTB6/ADP12 PTB5/ADP13 PTB4/ADP14 PTB3/ADP15 PTB2/ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTA3 PTE7 /RGPIO7/ SPSCK1 PTJ6/FTM2CH3 PTJ7/FTM2CH2 PTG0/TPM3CH0 VSS VDD PTA0/EWM_in PTA1/EWM_out PTE2 /RGPIO2/FTM1CH0 PTE4/RGPIO4 / SS1 PTE5 /RGPIO5/MISO1 PTE6 /RGPIO6/ MOSI1 13 14 15 16 17 18 19 20 21 22 23 24 PTE0/RGPIO0/TXD1 PTE1/RGPIO1/RXD1 48 47 46 45 44 43 42 41 40 39 38 37 PTC5/RXD2 PTC3/TXD2 PTH5 RESET BKGD/MS PTG6/XTAL PTG5/EXTAL VSS VDD VDDAD / VREFH VSSAD / VREFL PTD6/FTM1CLK/ADP0 Figure 4 shows the pinout of the 48-pin LQFP. Figure 4. 48-Pin LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 11 MCF51AG128 Family Configurations Table 3 shows the package pin assignments. Table 3. Pin Availability by Package Pin-Count Pin Number Lowest Highest 80 64 48 Alt 1 1 1 — PTC0 SCL 2 2 — PTC1 SDA 3 3 1 IRQ TPMCLK1 4 4 2 PTF0 RGPIO8 FTM1CH2 5 5 3 PTF1 RGPIO9 FTM1CH3 6 6 4 PTF2 RGPIO10 FTM1CH4 7 7 5 PTF3 RGPIO11 FTM1CH5 8 8 6 PTF4 RGPIO12 FTM2CH0 9 9 7 PTC6 FTM2FLT 10 10 8 PTF7 RGPIO15 Alt 2 11 11 9 PTF5 RGPIO13 FTM2CH1 12 12 10 PTF6 RGPIO14 FTM1FLT 13 — — PTJ0 PST0 14 — — PTJ1 PST1 15 — — PTJ2 PST2 16 — — PTJ3 PST3 17 13 11 PTE0 RGPIO0 TxD1 18 14 12 PTE1 RGPIO1 RxD1 19 15 13 PTE2 RGPIO2 FTM1CH0 20 16 — PTE3 RGPIO3 FTM1CH1 21 17 14 PTE4 RGPIO4 SS1 22 18 15 PTE5 RGPIO5 MISO1 23 19 16 PTE6 RGPIO6 MOSI1 24 20 17 PTE7 RGPIO7 SPSCK1 25 — — PTJ4 DDATA0 FTM2CH5 26 — — PTJ5 DDATA1 FTM2CH4 27 21 18 PTJ6 DDATA2 FTM2CH3 28 22 19 PTJ7 DDATA3 FTM2CH2 29 23 20 PTG0 PSTCLK0 TPM3CH0 30 24 21 VSS 31 25 22 VDD 32 — — PTG1 PSTCLK1 TPM3CH1 33 — — PTG2 BKPT 34 26 23 PTA0 EWM_in 35 27 24 PTA1 EWM_out 36 28 — PTA2 CIN1 37 29 25 PTA3 CMP2OUT 38 30 — PTA4 C2IN2 39 31 — PTA5 C2IN3 40 32 — PTA6 MCLK MCF51AG128 ColdFire Microcontroller, Rev. 5 12 Freescale Semiconductor MCF51AG128 Family Configurations Table 3. Pin Availability by Package Pin-Count (continued) Pin Number Lowest Highest 80 64 48 Alt 1 Alt 2 41 33 — PTA7 ADP23 42 — — PTH0 ADP22 FTM2CH2 43 — — PTH1 ADP21 FTM2CH3 44 — — PTH2 ADP20 FTM2CH4 45 — — PTH3 ADP19 FTM2CH5 46 34 26 PTB0 ADP18 TPM3CH0 47 35 27 PTB1 ADP17 TPM3CH1 48 36 28 PTB2 ADP16 49 37 29 PTB3 ADP15 50 38 30 PTB4 ADP14 51 39 31 PTB5 ADP13 52 40 32 PTB6 ADP12 53 41 33 PTB7 ADP11 54 42 34 PTD0 ADP10 C1IN2 55 43 35 PTD1 ADP9 C1IN3 56 44 — PTC2 ADP8 57 45 — PTD7 ADP7 58 46 36 PTD2 ADP6 59 47 — PTD3 ADP5 60 48 — PTG3 ADP4 61 — — PTG4 ADP3 62 49 — PTD4 FTM2CLK 63 50 — PTD5 ADP1 64 51 37 PTD6 FTM1CLK 65 — — PTC4 SS2 66 52 38 VSSA 67 53 38 VREFL 68 54 39 VREFH 69 55 39 VDDA 70 56 40 VDD 71 57 41 VSS 72 58 42 PTG5 EXTAL 73 59 43 PTG6 XTAL MS 74 60 44 BKGD 75 61 45 RESET 76 — — PTH4 SPSCK2 77 62 46 PTH5 MOSI2 78 — — PTH6 MISO2 79 63 47 PTC3 TxD2 80 64 48 PTC5 RxD2 CMP1OUT ADP2 ADP0 MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 13 Preliminary Electrical Characteristics 1 2 TPMCLK, FTM1CLK, and FTM2CLK options are configured via software; out of reset, FTM1CLK, FTM2CLK, and TPMCLK are available to FTM1, FTM2, and TPM3 respectively. Preliminary Electrical Characteristics This section contains electrical specification tables and reference timing diagrams for the MCF51AG128 series MCUs, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 2.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 4. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 2.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 5 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). MCF51AG128 ColdFire Microcontroller, Rev. 5 14 Freescale Semiconductor Preliminary Electrical Characteristics Table 5. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to 5.8 V Input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ±25 mA IDD 120 mA Tstg –55 to 150 °C Maximum current into VDD Storage temperature 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. 2.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD is very small. Table 6. Thermal Characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA –40 to 105 °C Maximum junction temperature TJ 150 °C Thermal resistance 1,2,3,4 80-pin LQFP 1s 2s2p 56 45 64-pin QFP 1s 2s2p θJA 54 41 °C/W 64-pin LQFP 1s 2s2p 67 49 1s 2s2p 69 51 48-pin LQFP MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 15 Preliminary Electrical Characteristics 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s — Single layer board, one signal layer 4 2s2p — Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O VDD VIN VDD VIN VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD. Typical VDD - VOH vs. IOH AT VDD=3V Typical VDD - VOH vs. IOH AT VDD = 5V 0.8 1.4 1.2 Room (25°C) Room (25°C) Cold (-40°C) 1.0 Cold (-40°C) 0.6 VDD - VOH (v) VDD - VOH (v) Hot (105°C) Hot (105°C) 0.8 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0 -1 -2 -3 -4 -5 0 -1 -2 IOH (mA) IOH (mA) Figure 5. Typical IOH vs. VDD – VOH (Low Drive,PTxDSn = 0) Typical VDD - VOH vs. IOH AT VDD = 5V Typical VDD - VOH vs. IOH AT VDD=3V Hot (105°C) 0.8 1.2 Room (25°C) 1.0 Cold (-40°C) Hot (105°C) Room (25°C) VDD - VOH (v) VDD - VOH (v) 1.4 0.8 0.6 0.4 0.2 0.0 0.6 Cold (-40°C) 0.4 0.2 0 -1 -2 -3 -4 -5 -6 -7 -8 -1 9 -10 1 -1 -12 3 -1 -14 5 -1 -16 -17 8 -1 -29 0 0.0 IOH (mA) 0 -1 -2 -3 -4 -5 -6 -7 -8 IOH (mA) Figure 6. Typical IOH vs. VDD – VOH (High Drive, PTxDSn = 1) MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 19 Preliminary Electrical Characteristics Typical VOL vs. IOL AT VDD = 5V 1.40 Hot (105°C) 1.20 0.80 Hot (105°C) Room (25°C) Cold (-40°C) Room (25°C) 0.60 VOL (v) 1.00 VOL (v) Typical VOL vs. IOL AT VDD = 3V 0.80 0.60 0.40 Cold (-40°C) 0.40 0.20 0.20 0.00 0.00 0 0 1 2 3 4 1 2 5 IOL (mA) IOL (mA) Figure 7. Typical IOL vs. VOL (Low Drive, PTxDSn = 0) Typical VOL vs. IOL AT VDD = 3V Typical VOL vs. IOL AT VDD = 5V 1.40 Hot (105°C) 1.20 Hot (105°C) Cold (-40°C) 1.00 Room (25°C) 0.60 0.80 VOL (v) VOL (v) 0.80 Room (25°C) 0.60 0.40 Cold (-40°C) 0.40 0.20 0.20 0.00 0.00 1 2 3 4 5 6 7 8 20 18 16 14 12 8 10 6 4 2 0 0 IOL (mA) IOL (mA) Figure 8. Typical IOL vs. VOL (High Drive, PTxDSn = 1) MCF51AG128 ColdFire Microcontroller, Rev. 5 20 Freescale Semiconductor Preliminary Electrical Characteristics 2.6 Supply Current Characteristics Table 10. Supply Current Characteristics Num C Parameter Symbol VDD (V) Typical1 Max2 1 C Run supply current3 measured at 4 MHz CPU clock (All Peripheral Clocks are ON) RIDD 5 5.8 7 3 5.7 7 5 21 25 3 20.9 25 5 39.2 50 3 39.1 50 5 57.9 70 3 57.8 70 5 4.7 6 3 4.6 6 Run supply current3 measured at 16 MHz CPU clock (All Peripheral Clocks are OFF4) 5 16.1 20 3 15.9 20 Run supply current3 measured at 32 MHz CPU clock (All Peripheral Clocks are OFF4) 5 29 35 3 28.9 35 5 44.1 50 3 44.0 50 5 3.2 5 3 3.2 5 Wait supply current3 measured at 16 MHz CPU clock 5 10.1 13 3 10 13 Wait supply current3 measured at 32 MHz CPU clock 5 19 25 3 18.8 25 Wait supply current3 measured at 50 MHz CPU clock 5 29.2 40 3 29 40 5 1.17 1.35 28.6 3 3 40 μA 1.0 1.34 26.8 3 3 40 μA 2 3 4 5 6 7 8 9 10 11 12 C C P C C C C C C C C 13 Run supply current3 measured at 16 MHz CPU clock (All Peripheral Clocks are ON) Run supply current3 measured at 32 MHz CPU clock (All Peripheral Clocks are ON) 3 Run supply current measured at 50MHz CPU clock (All Peripheral Clocks are ON) Run supply current3 measured at 4 MHz CPU clock (All Peripheral Clocks are OFF4) RIDD 3 measured at 50 MHz CPU Run supply current clock (All Peripheral Clocks are OFF4) Wait supply current3 measured at 4 MHz CPU clock C P C Stop2 mode supply current –40 °C 25 °C 105 °C C P C –40 °C 25 °C 105 °C WIDD S2IDD 3 Unit mA mA mA mA mA mA mA mA mA mA mA mA MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 21 Preliminary Electrical Characteristics Table 10. Supply Current Characteristics Num C 14 17 1 2 3 4 5 6 Symbol C P C Stop3 mode supply current –40 °C 25 °C 105 °C C P C –40 °C 25 °C 105 °C C P C Stop4 mode supply current –40 °C 25 °C 105 °C C P C –40 °C 25 °C 105 °C C RTC adder to stop2 or stop35, 25 °C 15 16 Parameter C S3IDD VDD (V) Typical1 Max2 Unit 5 1.2 1.7 43.3 3 3 60 μA 1.04 1.6 45.5 3 3 60 μA 106 109 155 130 130 170 μA 3 95 98 142 130 130 170 μA 5 300 — nA 3 300 — nA 5, 3 5 — μA 3 S4IDD 6 Adder to stop3 for oscillator enabled (ERCLKEN = 1 and EREFSTEN = 1) S23IDDRTC S3IDDOSC 5 Typicals are measured at 25 °C. Values given here are preliminary estimates prior to completing characterization. Code run from flash, FEI mode, and does not include any dc loads on port pins. Bus CLK= (CPU CLK/2) GPIO filters are working on LPO clock. Most customers are expected to use auto-wakeup from stop2 or stop3 instead of the higher current wait mode. Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0). Figure 9. Run Current at Different Conditions MCF51AG128 ColdFire Microcontroller, Rev. 5 22 Freescale Semiconductor Preliminary Electrical Characteristics 2.7 High Speed Comparator (HSCMP) Electricals Table 11. HSCMP Electrical Specifications Num C Rating Symbol Min Typical Max Unit 1 — Supply voltage VDD 2.7 — 5.5 V 2 T Supply current, high speed mode (EN = 1, PMODE = 1) IDDAHS — 200 — μA 3 T Supply current, low speed mode (EN = 1, PMODE = 0) IDDALS — 20 — μA 4 — Analog input voltage VAIN VSS – 0.3 — VDD V 5 D Analog input offset voltage VAIO — 5 40 mV 6 D Analog Comparator hysteresis VH 3.0 9.0 20.0 mV 7 D Propagation delay, high speed mode (EN = 1, PMODE = 1) tDHS — 70 120 ns 8 D Propagation delay, low speed mode (EN = 1, PMODE = 0) tDLS — 400 600 ns 9 D Analog Comparator initialization delay tAINIT — 400 — ns Symbol Min Typical Max Unit Digital to Analog (DAC) Characteristics 2.8 Num C 1 D Supply voltage VDDA 2.7 — 5.5 V 2 D Supply current (enabled) IDDAC — — 20 μA 3 D Supply current (stand-by) IDDACS — — 150 nA 4 D DAC reference input voltage Vin1,Vin2 VSSA — VDDA V 5 D DAC setup delay tPRGST — 1000 — nS 6 D DAC step size Vstep 3Vin/128 Vin/32 5Vin/128 V 7 D DAC output voltage range Vdacout Vin/32 — Vin V 8 P Bandgap voltage reference factory trimmed at VDD = 5 V, Temp = 25 °C VBG 1.18 1.20 1.21 V 2.9 Rating ADC Characteristics Table 12. 5V 12-bit ADC Operating Conditions Num C 1 D 2 D Characterist ic Conditions Symb Min Typic al1 Max Unit Comment Supply voltage Absolute VDDA 2.7 — 5.5 V — Delta to VDD (VDD–VDDA)2 ΔVDDA –100 0 100 mV — Ground voltage Delta to VSS (VSS–VSSA)2 ΔVSSA –100 0 100 mV — MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 23 Preliminary Electrical Characteristics Table 12. 5V 12-bit ADC Operating Conditions (continued) Conditions Symb Min Typic al1 Max Unit Comment Ref Voltage High — VREFH 2.7 VDDA VDDA V — D Ref Voltage Low — VREFL VSSAD VSSA VSSA V — 5 D Input Voltage — VADIN VREFL — VREFH V — 6 C Input Capacitance — CADIN — 4.5 5.5 pF — 7 C Input Resistance — RADIN — 3 5 kΩ — 8 C Analog Source Resistance kΩ — — — — 2 5 External to MCU 10 bit mode fADCK > 4 MHz fADCK < 4 MHz — — — — 5 10 8 bit mode (all valid fADCK) — — 10 0.4 — 8.0 MHz — 0.4 — 4.0 Num C 3 D 4 Characterist ic C C 9 D D ADC Conversion Clock Freq. 12 bit mode fADCK > 4 MHz fADCK < 4 MHz High Speed (ADLPC = 0) Low Power (ADLPC = 1) RAS fADCK — Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 MCF51AG128 ColdFire Microcontroller, Rev. 5 24 Freescale Semiconductor Preliminary Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS RADIN ADC SAR ENGINE + VADIN VAS – CAS + – RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 10. ADC Input Impedance Equivalency Diagram Table 13. 5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Num C Characteristic Conditions Symb Min Typical1 Max Unit Comment 1 T Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 — IDDAD — 181 — μA — 2 T Supply Current ADLPC = 1 ADLSMP = 0 ADCO = 1 — IDDAD — 334 — μA — 3 T Supply Current ADLPC = 0 ADLSMP = 1 ADCO = 1 — IDDAD — 385 — μA — 4 D Supply Current ADLPC = 0 ADLSMP = 0 ADCO = 1 — IDDAD — 0.717 1 mA — 5 T Supply Current Stop, Reset, Module Off IDDAD — 0.065 1 μA — MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 25 Preliminary Electrical Characteristics Table 13. 5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symb Min Typical1 Max Unit Comment fADACK 2 3.3 5 MHz tADACK = 1/fADACK 1.25 2 3.3 — 20 — ADCK cycles — 40 — See Table 10 for conversion time variances — 3.5 — — 23.5 — — ±3.0 — 10 bit mode — ±1 ±2.5 8 bit mode — ±0.5 ±1.0 — ±1.75 — 10 bit mode3 — ±0.5 ±1.0 8 bit mode5 — ±0.3 ±0.5 — ±1.5 — 10 bit mode — ±0.5 ±1.0 8 bit mode — ±0.3 ±0.5 — ±1.5 — 10 bit mode — ±0.5 ±1.5 8 bit mode — ±0.5 ±0.5 — ±1 — Num C Characteristic 6 P ADC Asynchronous Clock Source High Speed (ADLPC = 0) Conversion Time (Including sample time) Short Sample (ADLSMP = 0) Sample Time Short Sample (ADLSMP = 0) 7 8 P T Conditions Low Power (ADLPC = 1) tADC Long Sample (ADLSMP = 1) tADS Long Sample (ADLSMP = 1) 9 T P Total Unadjusted Error T 10 T P Differential Non-Linearity T 11 T P Integral Non-Linearity T 12 T P Zero-Scale Error T 13 14 15 T Full-Scale Error 12 bit mode 12 bit mode 12 bit mode 12 bit mode 12 bit mode ETUE DNL INL EZS EFS P 10 bit mode — ±0.5 ±1 T 8 bit mode — ±0.5 ±0.5 — –1 to 0 — 10 bit mode — — ±0.5 8 bit mode — — ±0.5 — ±1 — 10 bit mode — ±0.2 ±2.5 8 bit mode — ±0.1 ±1 D D Quantization Error Input Leakage Error 12 bit mode 12 bit mode EQ EIL ADCK cycles LSB2 Includes quantization LSB2 — LSB2 — LSB2 VADIN = VSSAD LSB2 VADIN = VDDAD LSB2 — LSB2 Pad leakage4 * RAS MCF51AG128 ColdFire Microcontroller, Rev. 5 26 Freescale Semiconductor Preliminary Electrical Characteristics Table 13. 5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Num C Characteristic Conditions 16 D Temp Sensor Voltage 25 °C 17 D Temp Sensor Slope –40 °C — 25 °C 25 °C — 85 °C Symb Min Typical1 Max Unit Comment VTEMP25 — 1.396 — mV — m — 3.266 — mV/°C — — 3.638 — Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. 1 2.10 External Oscillator (XOSC) Characteristics Table 14. Oscillator Electrical Specifications (Temperature Range = –40 to 105 °C Ambient) Num 1 C Rating C Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode 2 High range (RANGE = 1, HGO = 1) FBELP mode High range (RANGE = 1, HGO = 0) FBELP mode 2 — Load capacitors 3 — Symbol Min Typical1 Max Unit flo fhi 32 1 1 1 — — — — 38.4 16 16 8 kHz MHz MHz MHz fhi-hgo fhi-lp C1 C2 See crystal or resonator manufacturer’s recommendation. Feedback resistor Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) RF 10 1 — — — — 0 100 0 — — — — — — 0 0 0 0 10 20 — — — — 1500 2000 3 7 — — — — MΩ Series resistor 4 5 6 1 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz — T T Crystal start-up time 3 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)4 High range, high gain (RANGE = 1, HGO = 1)3 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode 2 FBE mode2 FBELP mode RS t t t CSTL-LP CSTL-HGO t CSTH-LP CSTH-HGO fextal 0.03125 0 0 — — — 50.33 50.33 50.33 kΩ ms MHz Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 27 Preliminary Electrical Characteristics 2 When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 4 4 MHz crystal MCU EXTAL XTAL RS RF C1 2.11 Crystal or Resonator C2 ICS Specifications Table 15. ICS Frequency Specifications (Temperature Range = –40 to 105 °C Ambient) Num C Rating Symbol Min Typical1 Max Unit 32.768 — kHz 1 C Internal reference frequency - factory trimmed at VDD = 5 V and temperature = 25 °C fint_ft — 2 C Average internal reference frequency – untrimmed fint_ut 31.25 — 39.06 kHz 3 T Internal reference startup time tirefst — 60 100 μs 4 C DCO output frequency 2 C range - untrimmed Low range (DRS = 00) fdco_ut 16 — 20 MHz 32 — 40 C High range (DRS = 10) 48 — 60 P DCO output frequency2 P Reference =32768Hz and DMX32 = 1 P Low range (DRS = 00) — 16.82 — 5 Mid range (DRS = 01) fdco_DMX32 Mid range (DRS = 01) — 33.69 — High range (DRS = 10) — 50.48 — MHz 6 D Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Δfdco_res_t — ±0.1 ±0.2 %fdco 7 D Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Δfdco_res_t — ±0.2 ±0.4 %fdco 8 D Total deviation of trimmed DCO output frequency over full voltage and temperature range Δfdco_t — 0.5 –1.0 ±2 %fdco 9 D Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 –70 °C Δfdco_t — ±0.5 ±1 %fdco MCF51AG128 ColdFire Microcontroller, Rev. 5 28 Freescale Semiconductor Preliminary Electrical Characteristics Table 15. ICS Frequency Specifications (continued)(Temperature Range = –40 to 105 °C Ambient) Num C Rating 3 Symbol Min Typical1 Max Unit 10 D FLL acquisition time tfll_acquire — — 1 ms 11 D Long term Jitter of DCO output clock (averaged over 2ms interval) 4 CJitter — 0.02 0.2 %fdco 12 D Loss of external clock minimum freq. (RANGE = 0) • ext. clock freq: above (3/5)fint, never reset • ext. clock freq: between (2/5)fint and (3/5)fint, maybe reset (phase dependency) • ext. clock freq: below (2/5)fint, always reset floc_low (3/5) x fint — — kHz 13 D Loss of external clock minimum freq. (RANGE = 1) • ext. clock freq: above (16/5)fint, never reset • ext. clock freq: between (15/5)fint and (16/5)fint, maybe reset (phase dependency) • ext. clock freq: below (15/5)fint, always reset floc_high (16/5) x fint — — kHz Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f BUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry by VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 1 2 MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 29 Preliminary Electrical Characteristics 2.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. 2.12.1 Control Timing Table 16. Control Timing Num C 1 D 2 D Symbol Min Typ1 Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 24 MHz Internal low-power oscillator period tLPO 800 — 1500 μs textrst 100 — — ns Parameter 2 3 D External reset pulse width (tcyc = 1/fSelf_reset) 4 D Reset low drive trstdrv 66 x tcyc — — ns 5 D Active background debug mode latch setup time tMSSU 500 — — ns 6 D Active background debug mode latch hold time tMSH 100 — — ns 7 D IRQ pulse width tILIH, tIHIL 100 1.5 x tcyc — — ns tRise, tFall — — Asynchronous path2 Synchronous path3 8 Port rise and fall time (load = 30 pF for SPI, rest 50 pF)4 Slew rate control disabled (PTxSE = 0) High drive Slew rate control enabled (PTxSE = 1) High drive Slew rate control disabled (PTxSE = 0) Low drive Slew rate control enabled (PTxSE = 1) Low drive 11 35 40 75 ns Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 105°C. 1 2 textrst RESET PIN Figure 11. Reset Timing MCF51AG128 ColdFire Microcontroller, Rev. 5 30 Freescale Semiconductor Preliminary Electrical Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 12. IRQ/KBIPx Timing 2.12.2 Timer (TPM/FTM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 17. TPM/FTM Input Timing NUM C Function Symbol Min Max Unit 1 — External clock frequency fTPMext DC fBus/4 MHz 2 — External clock period tTPMext 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTPMext tclkh TPMxCLK tclkl Figure 13. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 14. Timer Input Capture Pulse MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 31 Preliminary Electrical Characteristics 2.12.3 SPI Characteristics Table 18 and Figure 15 through Figure 18 describe the timing requirements for the SPI system. Table 18. SPI Timing Characteristics No. C Symbol Min Max Unit — D Operating frequency Master Slave fop fBus/2048 0 fBus/2 fBus/4 Hz 1 D SPSCK period Master Slave tSPSCK 2 4 2048 — tcyc tcyc 2 D Enable lead time Master Slave tLead 1/2 1 — — tSPSCK tcyc 3 D Enable lag time Master Slave tLag 1/2 1 — — tSPSCK tcyc 4 D Clock (SPSCK) high or low time Master Slave tWSPSCK tcyc – 30 tcyc – 30 1024 tcyc — ns ns 5 D Data setup time (inputs) Master Slave tSU 30 30 — — ns ns 6 D Data hold time (inputs) Master Slave tHI 10 10 — — ns ns 7 D — — tcyc 8 D — — tcyc — — 25 70 ns ns 10 10 — — ns ns 9 10 1 Function Slave access time Slave MISO disable time ta tdis D Data valid time ( maximum delay after SPCLK edge to Data output) Master Slave tV1 D Data hold time ( minimum delay after SPCLK edge to Data output) Master Slave tHO1 SPI Output Load = 30 pf MCF51AG128 ColdFire Microcontroller, Rev. 5 32 Freescale Semiconductor Preliminary Electrical Characteristics SS1 (OUTPUT) 3 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 9 MOSI (OUTPUT) LSB IN 10 9 MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 15. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 3 2 SPSCK (CPOL = 0) (OUTPUT) 4 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN(2) LSB IN 10 9 MOSI (OUTPUT) PORT DATA BIT 6 . . . 1 MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 16. SPI Master Timing (CPHA = 1) MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 33 Preliminary Electrical Characteristics SS (INPUT) 3 1 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) SLAVE LSB OUT SEE NOTE 6 5 MOSI (INPUT) BIT 6 . . . 1 MSB OUT SLAVE 10 10 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure 17. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 4 10 9 MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) SLAVE MSB OUT 5 8 BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 18. SPI Slave Timing (CPHA = 1) 2.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see MCF51AG128 Reference Manual. MCF51AG128 ColdFire Microcontroller, Rev. 5 34 Freescale Semiconductor Preliminary Electrical Characteristics Table 19. Flash Characteristics Num C 1 — 2 Characteristic Symbol Min Supply voltage for program/erase Vprog/erase — Supply voltage for read operation 3 — 4 5 Typical1 Max Unit 2.7 5.5 V VRead 2.7 5.5 V Internal FCLK frequency2 fFCLK 150 200 kHz — Internal FCLK period (1/FCLK) tFcyc 5 6.67 μs — Byte program time (random location)2 2 tprog 9 tFcyc tBurst 4 tFcyc 6 — Byte program time (burst mode) 7 — Page erase time3 tPage 4000 tFcyc 8 — Mass erase time2 tMass 20,000 tFcyc 9 C Program/erase endurance4 TL to TH = –40 °C to 105 °C T = 25 °C 10 C Data retention5 cycles tD_ret 10,000 — — 100,000 — — 15 100 — years Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. 1 2 2.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 2.14.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 35 Ordering Information 3 Ordering Information This section contains ordering information for MCF51AG128 devices. MCF 51 AG 128 V XX Status (MCF = Fully Qualified ColdFire) (PCF = Product Engineering) Package designator Temperature range (V = –40 °C to 105 °C, C = –40°C to 85 °C ) Core Family Memory size designator Table 20. Orderable Part Number Summary Freescale Part Number Description Flash / SRAM (KB) Package Temperature MCF51AG128VLK MCF51AG128 ColdFire Microcontroller 128 / 16 80 LQFP –40°C to 105°C MCF51AG128VLH MCF51AG128 ColdFire Microcontroller 128 / 16 64 LQFP –40°C to 105°C MCF51AG128VQH MCF51AG128 ColdFire Microcontroller 128 / 16 64 QFP –40°C to 105°C MCF51AG128VLF MCF51AG128 ColdFire Microcontroller 128 / 16 48 LQFP –40°C to 105°C MCF51AG96VLK MCF51AG96 ColdFire Microcontroller 96 / 16 80 LQFP –40°C to 105°C MCF51AG96VLH MCF51AG96 ColdFire Microcontroller 96 / 16 64 LQFP –40°C to 105°C MCF51AG96VQH MCF51AG96 ColdFire Microcontroller 96 / 16 64 QFP –40°C to 105°C MCF51AG96VLF MCF51AG96 ColdFire Microcontroller 96 / 16 48 LQFP –40°C to 105°C 4 Package Information Table 21. Package Descriptions Pin Count Package Type Abbreviation Designator Case No. Document No. LK 917A 98ASS23237W 80 Low Quad Flat Package LQFP 64 Low Quad Flat Package LQFP LH 840F 98ASS23234W 64 Quad Flat Package QFP QH 840B 98ASB42844B 48 Low Quad Flat Package LQFP LF 932 98ASH00962A MCF51AG128 ColdFire Microcontroller, Rev. 5 36 Freescale Semiconductor Mechanical Outline Drawings 5 Mechanical Outline Drawings 5.1 80-pin LQFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 37 Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 38 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 39 Mechanical Outline Drawings 5.2 64-pin LQFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 40 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 41 Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 42 Freescale Semiconductor Mechanical Outline Drawings 5.3 64-pin QFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 43 Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 44 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 45 Mechanical Outline Drawings 5.4 48-pin LQFP Package MCF51AG128 ColdFire Microcontroller, Rev. 5 46 Freescale Semiconductor Mechanical Outline Drawings MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 47 Revision History 6 Revision History Table 22. Revision History Rev. No. Date Description 1 11/2008 Initial Draft Release. 2 4/2009 Internal Release. 3 5/2009 Alpha Customer Release. 4 12/2009 • Added 48-pin LQFP information; • Updated Section 2.5/17 and 2.6/21. • Provided the supply current in Section 2.7/23, and setup delay in Section 2.8/23. 5 6/2010 • • • • • Updated Table 10. Added Figure 9. Corrected pin names of PTG6 and PTG5 in 48-pin LQFP. Standardized Generation 2008 Watchdog to Watchdog. In Table 9, updated Output high/low voltage — Low Drive (PTxDSn = 0) 3 V, ILoad value. MCF51AG128 ColdFire Microcontroller, Rev. 5 48 Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 49 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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