Freescale Semiconductor
Data Sheet: Advanced Information
Document Number: MCF51JE256
Rev. 4, 08/2012
An Energy-Efficient Solution from Freescale
MCF51JE256/128
MCF51JE256/128
The MCF51JE256 series devices are members of the low-cost,
low-power, high-performance ColdFire V1 family of 32-bit
microcontrollers (MCUs).
Not all features are available in all devices or packages; see
Table 1 for a comparison of features by device.
32-Bit ColdFire V1 Central Processor Unit (CPU)
• Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1 V
and 20 MHz CPU above 1.8 V across temperature range of -40°C to
105°C.
• ColdFire Instruction Set Revision C (ISA_C).
• 32-bit multiply and accumulate (MAC) supports signed or unsigned integer
or signed fractional inputs.
On-Chip Memory
• 256 K Flash comprised of two independent 128 K flash arrays;
read/program/erase over full operating voltage and temperature; allows
interrupt processing while programming.
• 32 KB System Random-access memory (RAM).
• Security circuitry to prevent unauthorized access to RAM and Flash
contents.
Power-Saving Modes
• Two ultra-low power stop modes. Peripheral clock enable register can
disable clocks to unused modules to reduce currents.
• Time of Day (TOD) — Ultra low-power 1/4 sec counter with up to 64 sec
timeout.
• Ultra-low power external oscillator that can be used in stop modes to
provide accurate clock source to the TOD. 6 µs typical wake up time from
stop3 mode.
Clock Source Options
• Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or
ceramic resonator dedicated for TOD operation.
• Oscillator (XOSC2) for high frequency crystal input for MCG reference to
be used for system clock and USB operations.
• Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming
of internal reference allows 0.2% resolution and typical +0.5% to -1%
deviation over temperature and voltage; supports CPU frequencies up to
50 MHz.
System Protection
• Watchdog computer operating properly (COP) reset with option to run from
dedicated 1 kHz internal clock source or bus clock.
• Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warning with optional interrupt; selectable trip points.
• Illegal opcode and illegal address detection with reset.
• Flash block protection for each array to prevent accidental write/erasure.
• Hardware CRC to support fast cyclic redundancy checks.
Development Support
• Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
connection supports same electrical interface used by the S08 family
debug modules.
• Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1
data).
• On-chip trace buffer provides programmable start/stop recording
conditions.
80-LQFP
12mm x 12mm
81-BGA
10mm x 10mm
104-BGA
10mm x 10mm
Peripherals
• USB — Dual-role USB On-The-Go (OTG) device, supports USB in either
device, host or OTG configuration. On-chip transceiver and 3.3V regulator
help save system cost, fully compliant with USB Specification 2.0. Allows
control, bulk, interrupt and isochronous transfers.
• SCIx — Two serial communications interfaces with optional 13-bit break;
option to connect Rx input to PRACMP output on SCI1 and SCI2; High
current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge.
• SPI1 — Serial peripheral interface with 32-bit FIFO buffer; 16-bit or 8-bit
data transfers; full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first shifting.
• SPI2 — Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting.
• IIC — Up to 100 kbps with maximum bus loading; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10-bit addressing.
• CMT — Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out (IRO).
Can be used as an output compare timer.
• TPMx — Two 4-channel Timer/PWM Module; Selectable input capture,
output compare, or buffered edge- or center-aligned PWM on each
channel; external clock input/pulse accumulator.
• Mini-FlexBus — Multi-function external bus interface with user
programmable chip selects and the option to multiplex address and data
lines.
• PRACMP — Analog comparator with selectable interrupt; compare option
to programmable internal reference voltage; operation in stop3.
• ADC12 — 12-bit Successive approximation ADC with up to12
single-ended channels; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V.
• PDB — Programmable delay block with 16-bit counter and modulus and
prescale to set reference clock to bus divided by 1 to bus divided by 2048;
8 trigger outputs for ADC module provides periodic coordination of ADC
sampling sequence with sequence completion interrupt; Back-to-Back
mode and Timed mode.
• DAC — 12-bit resolution DAC; configurable settling time.
Input/Output
• Up to 68 GPIOs and 1 output-only pin.
• Voltage Reference output (VREFO).
• Dedicated infrared output pin (IRO)
withhigh current sink capability.
• Up to 16 KBI pins with selectable
polarity.
• Up to 16 pins of rapid general purpose
I/O (RGPIO).
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
100-LQFP
14mm x 14mm
Contents
Table of Contents
1
2
3
4
5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . .15
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16
3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .18
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21
3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.8 12-bit DAC Electricals . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.10 MCG and External Oscillator (XOSC) Characteristics .29
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .32
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .41
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
List of Figures
Figure 1. MCF51JE256/128 Block Diagram. . . . . . . . . . . . . . . . . 3
Figure 2. 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. 80-Pin LQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 23
Figure 7. Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 26
Figure 8. ADC Input Impedance Equivalency Diagram . . . . . . . 28
Figure 9. Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 33
Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 33
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . .
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . .
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . .
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . .
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . .
Figure 19.Typical VREF Output vs Temperature . . . . . . . . . . . .
Figure 20.Typical VREF Output vs VDD . . . . . . . . . . . . . . . . . . .
36
36
38
38
39
39
42
43
List of Tables
Table 1. MCF51JE Features by MCU and Package. . . . . . . . . . 4
Table 2. MCF51JE256/128 Functional Units. . . . . . . . . . . . . . . . 5
Table 2-3.Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16
Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 21
Table 11.Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 24
Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 24
Table 14.DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . . . 25
Table 15.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 26
Table 16.12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 28
Table 17.MCG (Temperature Range = –40 to 105×C Ambient) . 29
Table 18.XOSC (Temperature Range = –40 to 105×C Ambient) 31
Table 19.Mini-FlexBus AC Timing Specifications . . . . . . . . . . . . 32
Table 20.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24.Internal USB 3.3 V Voltage Regulator Characteristics 40
Table 25.VREF Electrical Specifications . . . . . . . . . . . . . . . . . . 41
Table 26.VREF Limited Range Operating Behaviors . . . . . . . . . 42
Table 27.Orderable Part Number Summary. . . . . . . . . . . . . . . . 44
Table 28.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MCF51JE256 Datasheet, Rev. 4
2
Freescale Semiconductor
COCOx
VDDA/VSSA
HWTRS[H:A]
PDB
HWTRS[H:A]
VREFH/VREFL
ADP[11:4]
DADP/M[3:0]
ADC12
Dtrig
VDDA/VSSA
ACMPO
Dtrig
Port A
DADP[3:0]
DADM[3:0]
PRACMP
VREFH/VREFL
DACO
DACO
ACMPO
VREFH/VREFL
RX1
TX1
SCI1
RX2
TX2
IIC
SDA
SCL
KBI1 & KBI2
KBI1P[7:0]
KBI2P[7:0]
Port C
SCI2
Port B
VDDA/VSSA
IRO
4 Ch TPM1
TPM1CH[3:0]
TPMCLK
IRO:
CMT
Hardware CRC
TPM2CH[3:0]
TPMCLK
INTC
RGPIO[15:8]
MCG
V1 ColdFire Core
with MAC
PTD1/CMPP2/RESET
MOSI1 SS1
MISO1 SPSCK1
Clock Check
& Select
SPI2
MOSI2 SS2
MISO2 SPSCK2
XOSC2
CLKO
LVD
FLASH1
128/64 KB
IRQ
USBOTG
Manager
128/64 KB
RAM
32KB
VREG
VSS1,2,3
VDD1,2,3
XOSC1
EXTAL1
XTAL1
Robust
Update
FLASH2
FB_D[7:0]
FB_AD[19:0]
USB_DM
USB_DM
USB_DP
USB_ALTCLK
USB_PULLUP(D+)
USB_DM_DOWN
USB_DP_DOWN
USB_VBUSVLD
USB_ID
USB_SESSVLD
USB_SESSEND
USB_DP
VUSB33
Port H
COP
MINIFLEX
BUS
CLKO
TOD
VBUS
Port J
FB_AD[19:0]
SPI1
SIM
PTE4/CMPP3/
TPMCLK/VPP/IRQ
IRCLK
Port F
REF CLK
RGPIO[7:0]
Port G
RGPIO
control
BKGD/MS
control
PTD0/BKGD/MS
4 Ch TPM2
DBG
BDM
Port E
VREF
Port D
VREFO
PTA7
PTA6
PTA5
PTA4
PTA3/KBI1P2/FB_D6/ADP5
PTA2/KBI1P1/RX1/ADP4
PTA1/KBI1P0/TX1/FB_D1
PTA0/FB_D2/SS1
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB5/XTAL2
PTB4/EXTAL2
PTB3/XTAL1
PTB2/EXTAL1
PTB1/BLMS
PTB0
PTC7/KBI2P2CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE_b/FB_CS0
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW_b/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTF7/MISO1
PTF6/MOSI1
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTG7/FB_AD18
PTG6/FB_AD19
PTG5/FB_RW_b
PTG4/USB_SESSVLD
PTG3/USB_DP_DOWN
PTG2/USB_DM_DOWN
PTG1/USB_SESSEND
PTG0/SPSCK1
PTH7/RGPIOP7/FB_D2
PTH6/RGPIOP6/FB_D3
PTH5/RGPIOP5/FB_D4
PTH4/RGPIOP4/FB_D5
PTH3/RGPIOP3/FB_D6
PTH2/RGPIOP2/FB_D7
PTH1/FB_D0
PTH0/FB_OE_b
PTJ7/FB_AD13
PTJ6/FB_AD14
PTJ5/FB_AD15
PTJ4/RGPIOP15/FB_AD16
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
Green pins not available on the 100, 81 or 80 pin package
Blue pins not available on the 81 or 80 pin package
Red pin not available on the 80 pin package
Figure 1. MCF51JE256/128 Block Diagram
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
3
Features
1
Features
The following table provides a cross-comparison of the features of the MCF51JE256/128 according to
package.
Table 1. MCF51JE Features by MCU and Package
Feature
MCF51JE256
MCF51JE128
262144
131072
FLASH size (bytes)
RAM size (bytes)
32K
Pin quantity
104
100
32K
81
Programmable Analog Comparator (PRACMP)
yes
Debug Module (DBG)
yes
Multipurpose Clock Generator (MCG)
yes
Inter-Integrated Communication (IIC)
yes
Interrupt Request Pin (IRQ)
yes
Keyboard Interrupt (KBI)
16
1
69
Digital General purpose I/O
65
Power and Ground Pins
48
81
80
47
48
47
8
Time Of Day (TOD)
yes
Serial Communications (SCI1)
yes
Serial Communications (SCI2)
yes
Serial Peripheral Interface (SPI1(FIFO))
yes
Serial Peripheral Interface(SPI2)
yes
Carrier Modulator Timer pin (IRO)
yes
Programmable Delay Block (PDB)
yes
TPM input clock pin (TPMCLK)
yes
TPM1 channels
4
TPM2 channels
4
XOSC1
yes
XOSC2
yes
USBOTG
yes
MiniFlex Bus
yes
Rapid GPIO
16
DATA
9
ADC single-ended channels
12
DAC ouput pin (DACO)
yes
Voltage reference output pin (VREFO)
yes
1
80
Port I/O count does not include BLMS, BKGD and IRQ. BLMS BKGD are Output only, IRQ is input only.
The following table describes the functional units of the MCF51JE256/128.
MCF51JE256 Datasheet, Rev. 4
4
Freescale Semiconductor
Features
Table 2. MCF51JE256/128 Functional Units
Unit
Function
DAC (digital to analog converter)
Used to output voltage levels.
12-BIT SAR ADC (analog-to-digital
converter)
Measures analog voltages at up to 12 bits of resolution. The ADC has
up to 12 single-ended inputs.
PDB (Programmable Delay Block)
Precisely trigger the DAC FIFO buffer.
Mini-FlexBus
Provides expansion capability for off-chip memory and peripherals.
USB On-the-Go
Supports the USB On-the-Go dual-role controller.
CMT (Carrier Modulator Timer)
Infrared output used for the Remote Controller operation.
MCG (Multipurpose Clock Generator)
Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources.
BDM (Background Debug Module)
Provides single pin debugging interface (part of the V1 ColdFire core).
CF1 CORE (V1 ColdFire Core)
Executes programs and interrupt handlers.
PRACMP
Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
COP (Computer Operating Properly)
Software Watchdog.
IRQ (Interrupt Request)
Single-pin high-priority interrupt (part of the V1 ColdFire core).
CRC (Cyclic Redundancy Check)
High-speed CRC calculation.
DBG (Debug)
Provides debugging and emulation capabilities (part of the V1 ColdFire
core).
FLASH (Flash Memory)
Provides storage for program code, constants, and variables.
IIC (Inter-integrated Circuits)
Supports standard IIC communications protocol and SMBus.
INTC (Interrupt Controller)
Controls and prioritizes all device interrupts.
KBI1 & KBI2
Keyboard Interfaces 1 and 2.
LVD (Low-voltage Detect)
Provides an interrupt to the ColdFire V1 CORE in the event that the
supply voltage drops below a critical value. The LVD can also be
programmed to reset the device upon a low voltage event.
VREF (Voltage Reference)
The Voltage Reference output is available for both on- and off-chip use.
RAM (Random-Access Memory)
Provides stack and variable storage.
RGPIO (Rapid General-purpose
Input/output)
Allows for I/O port access at CPU clock speeds. RGPIO is used to
implement GPIO functionality.
SCI1, SCI2 (Serial Communications
Interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols.
SIM (system integration unit)
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
5
Features
Table 2. MCF51JE256/128 Functional Units (continued)
Unit
Function
SPI1 (FIFO), SPI2 (Serial Peripheral
Interfaces)
SPI1 and SPI2 provide standard master/slave capability. SPI contains a
FIFO buffer in order to increase the throughput for this peripheral.
TPM1, TPM2 (Timer/PWM Module)
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation.
VREG (Voltage Regulator)
Controls power management across the device.
XOSC1 and XOSC2 (Crystal Oscillators)
These devices incorporate redundant crystal oscillators. One is
intended primarily for use by the TOD, and the other by the CPU and
other peripherals.
MCF51JE256 Datasheet, Rev. 4
6
Freescale Semiconductor
Pinouts and Pin Assignments
2
Pinouts and Pin Assignments
2.1
104-Pin MAPBGA
The following figure shows the 104-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
10
11
A
PTF6
PTF7
USB_DP
USB_DM
VUSB33
PTF4
PTF3
FB_AD12
PTJ7
PTJ5
PTJ4
A
B
PTG0
PTA0
PTG3
VBUS
PTF5
PTJ6
PTH0
PTE5
PTF0
PTF1
PTF2
B
C
IRO
PTG4
PTA6
PTG2
PTG6
PTG5
PTG7
PTH1
PTE4
PTE6
PTE7
C
D
PTA5
PTA4
PTB1
VDD1
VDD3
PTA1
PTE3
PTE2
D
E
VSSA
PTA7
PTB0
PTA2
PTJ3
PTE1
E
F
VREFL
PTJ2
PTJ0
PTJ1
F
G
ADP2
PTD5
PTD7
PTE0
G
VSS3
PTD4
PTD3
PTD2
H
PTG1
H
J
ADP0
K
L
VDD2
ADP3
DACO
1
2
PTC7
PTA3
VSS1
PTH7
PTH6
PTH4
PTH3
PTH2
PTD6
PTC2
PTC0
PTC1
J
ADP1
PTH5
PTB6
PTB7
PTC3
PTD1
PTC4
PTC5
PTC6
K
VREFO
VREFH
VDDA
PTB3
PTB2
PTD0
PTB5
PTB4
L
4
5
6
7
8
9
10
11
3
VSS2
Figure 2. 104-Pin MAPBGA
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
7
Pinouts and Pin Assignments
2.2
100-Pin LQFP
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
FB_AD12
PTJ7/FB_AD13
PTJ6/FB_AD14
PTJ5/FB_AD15
PTJ4/RGPIOP15/FB_AD16
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
96
95
94
92
91
90
89
88
87
86
84
83
82
81
80
79
78
77
76
85
PTF6/MOSI1
97
93
PTF7/MISO1
98
PTG0/SPSCK1
100
99
The following figure shows the 100-pin LQFP pinout configuration.
PTA0/FB_D2/SS1
1
75
PTE4/CMPP3/TPMCLK/IRQ
IRO
2
74
PTE3/KBI2P6/FB_AD8
PTG5/FB_RW
3
73
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTG6/FB_AD19
4
72
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTG7/FB_AD18
5
71
PTJ3/RGPIOP12/FB_AD5
PTH0/FB_OE
6
70
PTJ2/FB_AD4
PTH1/FB_D0
7
69
PTJ1/FB_AD3
PTA1/KBI1P0/TX1/FB_D1
8
68
PTA2/KBI1P1/RX1/ADP4
9
67
PTJ0/FB_AD2
PTE0/KBI2P3/FB_ALE/FB_CS1
PTA3/KBI1P2/FB_D6/ADP5
10
66
PTD7/USB_PULLUP(D+)/RX1
PTA4
11
65
PTA5
12
64
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTA6
13
63
PTD4/SDA/RGPIOP10/TPM1CH2
PTA7
14
62
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTB0
15
61
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTB1/BLMS
16
60
VSSA
17
59
PTD1/CMPP2/RESET
PTD0/BKGD/MS
VREFL
18
58
PTC7/KBI2P2/CLKOUT/ADP11
NC
19
57
PTC6/KBI2P1/PRACMPO/ADP10
NC
20
56
PTC5/KBI2P0/CMPP1/ADP9
ADP2
21
55
PTC4/KBI1P7/CMPP0/ADP8
NC
22
54
PTC3/KBI1P6/SS2/ADP7
NC
23
53
PTC2/KBI1P5/SPSCK2/ADP6
NC
24
52
PTC1/MISO2/FB_D0/FB_AD1
NC
25
51
PTC0/MOSI2/FB_OE/FB_CS0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTH2/RGPIOP2/FB_D7
PTH3/RGPIOP3/FB_D6
PTH4/RGPIOP4/FB_D5
PTH5/RGPIOP5/FB_D4
PTH6/RGPIOP6/FB_D3
PTH7/RGPIOP7/FB_D2
33
ADP1
VSS2
32
VREFO
36
31
NC
VDDA
30
ADP0
35
29
NC
34
28
NC
NC
27
ADP3
VREFH
26
DACO
100 LQFP
Figure 3. 100-Pin LQFP
MCF51JE256 Datasheet, Rev. 4
8
Freescale Semiconductor
Pinouts and Pin Assignments
2.3
81-Pin MAPBGA
The following figure shows the 81-pin MAPBGA pinout configuration.
1
2
3
4
5
6
7
8
9
A
IRO
PTG0
PTF6
USB_DP
VBUS
VUSB33
PTF4
PTF3
PTE4
A
B
PTF7
PTA0
PTG1
USB_DM
PTF5
PTE7
PTF1
PTF0
PTE3
B
C
PTA4
PTA5
PTA6
PTA1
PTF2
PTE6
PTE5
PTE2
PTE1
C
PTA7
PTB0
PTB1
PTA2
PTA3
PTD5
PTD7
PTE0
D
VDD2
VDD3
VDD1
PTD2
PTD3
PTD6
E
VSS2
VSS3
VSS1
PTB7
PTC7
PTD4
F
ADP3
VREFO
PTB6
PTC0
PTC1
PTC2
G
ADP1
PTC3
PTC4
PTD0
PTC5
PTC6
H
J
D
E
ADP2
F
G
ADP0
DACO
H
J
VSSA
VREFL
VREFH
VDDA
PTB2
PTB3
PTD1
PTB4
PTB5
1
2
3
4
5
6
7
8
9
Figure 4. 81-Pin MAPBGA
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
9
Pinouts and Pin Assignments
2.4
80-Pin LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80-Pin LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
DACO
ADP3
NC
NC
ADP0
NC
VREFO
ADP1
NC
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTC0/MOSI2/FB_OE/FB_CS0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTA0/FB_D2/SS1
IRO
PTA1/KBI1P0/TX1/FB_D1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/FB_D6/ADP5
PTA4
PTA5
PTA6
PTA7
PTB0
PTB1/BLMS
VSSA
VREFL
NC
NC
ADP2
NC
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
VDD3
VSS3
The following figure shows the 80-pin LQFP pinout configuration.
Figure 5. 80-Pin LQFP Pinout
MCF51JE256 Datasheet, Rev. 4
10
Freescale Semiconductor
Pinouts and Pin Assignments
2.5
Pin Assignments
Table 3. Package Pin Assignments
Package
Default
Function
Alternate 1
Alternate 2
Alternate 3
Composite Pin Name
1
PTA0
FB_D2
SS1
—
PTA0/FB_D2/SS1
A1
2
IRO
—
—
—
IRO
3
—
—
PTG5
FB_RW
—
—
PTG5/FB_RW
4
—
—
PTG6
FB_AD19
—
—
PTG6/FB_AD19
C7
5
—
—
PTG7
FB_AD18
—
—
PTG7/FB_AD18
B7
6
—
—
PTH0
FB_OE
—
—
PTH0/FB_OE
C8
7
—
—
PTH1
FB_D0
—
—
PTH1/FB_D0
D9
8
C4
3
PTA1
KBI1P0
TX1
FB_D1
PTA1/KBI1P0/TX1/FB_D1
E9
9
D5
4
PTA2
KBI1P1
RX1
ADP4
PTA2/KBI1P1/RX1/ADP4
H3
10
D6
5
PTA3
KBI1P2
FB_D6
ADP5
PTA3/KBI1P2/FB_D6/ADP5
D2
11
C1
6
PTA4
—
—
—
PTA4
D1
12
C2
7
PTA5
—
—
—
PTA5
C3
13
C3
8
PTA6
—
—
—
PTA6
E2
14
D2
9
PTA7
—
—
—
PTA7
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
B2
1
B2
C1
2
C6
C5
E3
15
D3
10
PTB0
—
—
—
PTB0
D3
16
D4
11
PTB1
BLMS
—
—
PTB1/BLMS
E1
17
J1
12
VSSA
—
—
—
VSSA
F1
18
J2
13
VREFL
—
—
—
VREFL
F2
19
D1
19
—
—
—
—
NC
G2
20
E2
15
—
—
—
—
NC
G1
21
F2
16
ADP2
—
—
—
ADP2
H1
22
F1
17
—
—
—
—
NC
H2
23
E2
18
NC
—
—
—
NC
F3
24
F3
19
—
—
—
—
NC
G3
25
E3
20
—
—
—
—
NC
L2
26
G2
21
DACO
—
—
—
DACO
L1
27
G3
22
ADP3
—
—
—
ADP3
K1
28
H4
23
—
—
—
—
NC
K2
29
G4
24
NC
—
—
—
NC
J1
30
G1
25
ADP0
—
—
—
ADP0
J2
31
H1
26
—
—
—
—
NC
L4
32
G5
27
VREFO
—
—
—
VREFO
K3
33
H3
28
ADP1
—
—
—
ADP1
L3
34
H2
29
NC
—
—
—
NC
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
11
Pinouts and Pin Assignments
Table 3. Package Pin Assignments (continued)
Package
Default
Function
Alternate 1
Alternate 2
Alternate 3
Composite Pin Name
30
VREFH
—
—
—
VREFH
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
L5
35
J3
L6
36
J4
31
VDDA
—
—
—
VDDA
H6
37
F4
32
VSS2
—
—
—
VSS2
L8
38
J5
33
PTB2
EXTAL1
—
—
PTB2/EXTAL1
L7
39
J6
34
PTB3
XTAL1
—
—
PTB3/XTAL1
D6
40
E4
35
VDD2
—
—
—
VDD2
L11
41
J8
36
PTB4
EXTAL2
—
—
PTB4/EXTAL2
L10
42
J9
37
PTB5
XTAL2
—
—
PTB5/XTAL2
K5
43
G6
38
PTB6
KBI1P3
RGPIOP0
FB_AD17
PTB6/KBI1P3/RGPIOP0/
FB_AD17
K6
44
F7
39
PTB7
KBI1P4
RGPIOP1
FB_AD0
PTB7/KBI1P4/RGPIOP1/
FB_AD0
J7
45
—
—
PTH2
RGPIOP2
FB_D7
—
PTH2/RGPIOP2/FB_D7
J6
46
—
—
PTH3
RGPIOP3
FB_D6
—
PTH3/RGPIOP3/FB_D6
J5
47
—
—
PTH4
RGPIOP4
FB_D5
—
PTH4/RGPIOP4/FB_D5
K4
48
—
—
PTH5
RGPIOP5
FB_D4
—
PTH5/RGPIOP5/FB_D4
J4
49
—
—
PTH6
RGPIOP6
FB_D3
—
PTH6/RGPIOP6/FB_D3
J3
50
—
—
PTH7
RGPIOP7
FB_D2
—
PTH7/RGPIOP7/FB_D2
J10
51
G7
40
PTC0
MOSI2
FB_OE
FB_CS0
PTC0/MOSI2/FB_OE/ FB_CS0
J11
52
G8
41
PTC1
MISO2
FB_D0
FB_AD1
PTC1/MISO2/FB_D0/FB_AD1
J9
53
G9
42
PTC2
KBI1P5
SPSCK2
ADP6
PTC2/KBI1P5/SPSCK2/ADP6
K7
54
H5
43
PTC3
KBI1P6
SS2
ADP7
PTC3/KBI1P6/SS2/ADP7
K9
55
H6
44
PTC4
KBI1P7
CMPP0
ADP8
PTC4/KBI1P7/CMPP0/ADP8
K10
56
H8
45
PTC5
KBI2P0
CMPP1
ADP9
PTC5/KBI2P0/CMPP1/ADP9
K11
57
H9
46
PTC6
KBI2P1
PRACMPO
ADP10
PTC6/KBI2P1/PRACMPO/
ADP10
F8
58
F8
47
PTC7
KBI2P2
CLKOUT
ADP11
PTC7/KBI2P2/CLKOUT/ADP11
L9
59
H7
48
PTD0
BKGD
MS
—
PTD0/BKGD/MS
K8
60
J7
49
PTD1
CMPP2
RESET
—
PTD1/CMPP2/RESET
H11
61
E7
50
PTD2
USB_ALTCL
K
RGPIOP8
TPM1CH0
PTD2/USB_ALTCLK/RGPIOP8/
TPM1CH0
H10
62
E8
51
PTD3
USB_PULL
UP(D+)
RGPIOP9
TPM1CH1
PTD3/USB_PULLUP(D+)/
RGPIOP9/TPM1CH1
H9
63
F9
52
PTD4
SDA
RGPIOP10
TPM1CH2
PTD4/SDA/RGPIOP10/
TPM1CH2
G9
64
D7
53
PTD5
SCL
RGPIOP11
TPM1CH3
PTD5/SCL/RGPIOP11/
TPM1CH3
J8
65
E9
54
PTD6
USB_ALTCL
K
TX1
—
PTD6/USB_ALTCLK/TX1
MCF51JE256 Datasheet, Rev. 4
12
Freescale Semiconductor
Pinouts and Pin Assignments
Table 3. Package Pin Assignments (continued)
Package
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
G10
66
D8
55
G11
67
D9
F10
68
F11
F9
Default
Function
Alternate 1
Alternate 2
Alternate 3
Composite Pin Name
PTD7
USB_PULL
UP(D+)
RX1
—
PTD7/USB_PULLUP(D+) /RX1
56
PTE0
KBI2P3
FB_ALE
FB_CS1
PTE0/KBI2P3/FB_ALE/
FB_CS1
—
—
PTJ0
FB_AD2
—
—
PTJ0/FB_AD2
69
—
—
PTJ1
FB_AD3
—
—
PTJ1/FB_AD3
70
—
—
PTJ2
FB_AD4
—
—
PTJ2/FB_AD4
E10
71
—
—
PTJ3
RGPIOP12
FB_AD5
—
PTJ3/RGPIOP12/FB_AD5
E11
72
C9
57
PTE1
KBI2P4
RGPIOP13
FB_AD6
PTE1/KBI2P4/RGPIOP13/
FB_AD6
D11
73
C8
58
PTE2
KBI2P5
RGPIOP14
FB_AD7
PTE2/KBI2P5/RGPIOP14/
FB_AD7
D10
74
B9
59
PTE3
KBI2P6
FB_AD8
—
PTE3/KBI2P6/FB_AD8
C9
75
A9
60
PTE4
CMPP3
TPMCLK
IRQ
PTE4/CMPP3/TPMCLK/VPP/
IRQ
H8
76
F5
61
VSS3
—
—
—
VSS3
D8
77
E5
62
VDD3
—
—
—
VDD3
B8
78
C7
63
PTE5
FB_D7
USB_
SESSVLD
TX2
PTE5/FB_D7/USB_SESSVLD/
TX2
C10
79
C6
64
PTE6
FB_RW
USB_
SESSEND
RX2
PTE6/FB_RW_b/
USB_SESSEND/RX2
C11
80
B6
65
PTE7
USB_VBUS
VLD
TPM2CH3
—
PTE7/USB_VBUSVLD/
TPM2CH3
B9
81
B8
66
PTF0
USB_ID
TPM2CH2
—
PTF0/USB_ID/TPM2CH2
B10
82
B7
67
PTF1
RX2
USB_DP_
DOWN
TPM2CH1
PTF1/RX2/USB_DP_DOWN/
TPM2CH1
B11
83
C5
68
PTF2
TX2
USB_DM_
DOWN
TPM2CH0
PTF2/TX2/USB_DM_DOWN/
TPM2CH0
A11
84
—
—
PTJ4
RGPIOP15
FB_AD16
—
PTJ4/RGPIOP15/FB_AD16
A10
85
—
—
PTJ5
FB_AD15
—
—
PTJ5/FB_AD15
B6
86
—
—
PTJ6
FB_AD14
—
—
PTJ6/FB_AD14
A9
87
—
—
PTJ7
FB_AD13
—
—
PTJ7/FB_AD13
A8
88
—
—
FB_AD12
—
—
—
FB_AD12
A7
89
A8
69
PTF3
SCL
FB_D5
FB_AD11
PTF3/SCL/FB_D5/FB_AD11
A6
90
A7
70
PTF4
SDA
FB_D4
FB_AD10
PTF4/SDA/FB_D4/FB_AD10
B5
91
B5
71
PTF5
KBI2P7
FB_D3
FB_AD9
PTF5/KBI2P7/FB_D3/FB_AD9
A5
92
A6
72
VUSB33
—
—
—
VUSB33
A4
93
B4
73
USB_DM
—
—
—
USB_DM
A3
94
A4
74
USB_DP
—
—
—
USB_DP
B4
95
A5
75
VBUS
—
—
—
VBUS
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
13
Pinouts and Pin Assignments
Table 3. Package Pin Assignments (continued)
Package
Default
Function
Alternate 1
Alternate 2
Alternate 3
Composite Pin Name
76
VSS1
—
—
—
VSS1
104
MAPB
GA
100
LQFP
81
MAPB
GA
80
LQFP
H4
96
F6
D4
97
E6
77
VDD1
—
—
—
VDD1
A1
98
A3
78
PTF6
MOSI1
—
—
PTF6/MOSI1
A2
99
B1
79
PTF7
MISO1
—
—
PTF7/MISO1
B1
100
A2
80
PTG0
SPSCK1
—
—
PTG0/SPSCK1
F4
—
B3
—
PTG1
USB_SESS
END
—
—
PTG1/USB_SESSEND
C4
—
—
—
PTG2
USB_DM_D
OWN
—
—
PTG2/USB_DM_DOWN
B3
—
—
—
PTG3
USB_DP_D
OWN
—
—
PTG3/USB_DP_DOWN
C2
—
—
—
PTG4
USB_SESS
VLD
—
—
PTG4/USB_SESSVLD
MCF51JE256 Datasheet, Rev. 4
14
Freescale Semiconductor
Preliminary Electrical Characteristics
3
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51JE256/128 microcontroller, including detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however, be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
3.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 4. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
15
Preliminary Electrical Characteristics
Table 5. Absolute Maximum Ratings
#
1
2
3
Rating
Symbol
Value
Unit
1
Supply voltage
VDD
–0.3 to 3.8
V
2
Maximum current into VDD
IDD
120
mA
3
Digital Input voltage
VIn
–0.3 to VDD + 0.3
V
4
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
25
mA
5
Storage temperature range
Tstg
–55 to 150
C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
All functional non-supply pins are internally clamped to VSS and VDD.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or
VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
loads), the difference between pin voltage and VSS or VDD will be very small.
MCF51JE256 Datasheet, Rev. 4
16
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 6. Thermal Characteristics
#
Symbol
Rating
Value
Unit
Operating temperature range (packaged):
1
2
TA
TJMAX
Thermal resistance
1
2
3
4
MCF51JE128
–40 to 105
135
C
C
Single-layer board — 1s
JA
Thermal
4
–40 to 105
Maximum junction temperature
1,2,3,4
3
MCF51JE256
resistance1, 2, 3, 4
104-pin MBGA
67
100-pin LQFP
53
81-pin MBGA
67
80-pin LQFP
53
C/W
Four-layer board — 2s2p
JA
104-pin MBGA
39
100-pin LQFP
41
81-pin MBGA
39
80-pin LQFP
39
C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Junction to Ambient Natural Convection
1s — Single layer board, one signal layer
2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD JA)
Eqn. 1
where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K (TJ + 273C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD (TA + 273C) + JA (PD)2
Eqn. 3
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
17
Preliminary Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4
ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Storage Capacitance
C
100
pF
Number of Pulse per pin
—
3
—
Series Resistance
R1
0
Storage Capacitance
C
200
pF
Number of Pulse per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Latch-up
Table 8. ESD and Latch-Up Protection Characteristics
#
3.5
Rating
Symbol
Minimum
Maximum
Unit
C
1
Human Body Model (HBM)
VHBM
2000
—
V
T
2
Machine Model (MM)
VMM
200
—
V
T
3
Charge Device Model (CDM)
VCDM
500
—
V
T
4
Latch-up Current at TA = 125C
ILAT
00
—
mA
T
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
MCF51JE256 Datasheet, Rev. 4
18
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 9. DC Characteristics
#
Symbol
1
—
2
VOH
Characteristic
Condition
2
C
—
1.8
—
3.6
V
—
VDD 1.8 V,
ILoad = –600 A
VDD – 0.5
—
—
V
C
VDD 2.7 V,
ILoad = –10 mA
VDD – 0.5
—
—
V
P
VDD 2.3 V,
ILoad = –6 mA
VDD – 0.5
—
—
V
T
VDD 1.8V,
ILoad = –3 mA
VDD – 0.5
—
—
V
C
—
—
—
100
mA
D
VDD 1.8 V,
ILoad = 600 A
—
—
0.5
V
C
VDD 2.7 V,
ILoad = 10 mA
—
—
0.5
V
P
VDD 2.3 V,
ILoad = 6 mA
—
—
0.5
V
T
VDD 1.8 V,
ILoad = 3 mA
—
—
0.5
V
C
—
—
—
100
mA
D
VDD 2.7 V
0.70 x VDD
—
—
V
P
VDD 1.8 V
0.85 x VDD
—
—
V
C
VDD 2.7 V
—
—
0.35 x VDD
V
P
VDD 1.8 V
—
—
0.30 x VDD
V
C
—
0.06 x VDD
—
—
mV
C
all input only pins
(Per pin)
VIn = VDD or VSS
—
—
0.5
A
P
all input/output
(per pin)
VIn = VDD or VSS
—
0.003
0.5
A
P
Operating Voltage
Output high
voltage
Minimum Typical1 Maximum Unit
All I/O pins, low-drive strength
All I/O pins, high-drive strength
3
4
IOHT
VOL
Output high
current
Output low
voltage
Max total IOH for all ports
All I/O pins, low-drive strength
All I/O pins, high-drive strength
5
6
7
IOLT
VIH
VIL
Output low
current
Max total IOL for all ports
Input high voltage all digital inputs
Input low voltage all digital inputs
8
Vhys
Input hysteresis
9
|IIn|
Input leakage
current
10
|IOZ|
Hi-Z (off-state)
leakage current3
all digital inputs
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
19
Preliminary Electrical Characteristics
Table 9. DC Characteristics (continued)
#
Symbol
11
Characteristic
RPU
Pull-up resistors
RPD
Internal
pull-down
resistors4
12
all digital inputs, when
enabled
17.5
—
52.5
k
P
—
17.5
—
52.5
k
P
Single pin limit
VSS > VIN > VDD
–0.2
—
0.2
mA
Total MCU limit, includes
sum of all stressed pins
VSS > VIN > VDD
–5
—
5
mA
DC injection
current 5, 6, 7
14
CIn
Input Capacitance, all pins
—
—
—
8
pF
C
15
VRAM
RAM retention voltage
—
—
0.6
1.0
V
C
16
VPOR
POR re-arm voltage8
—
0.9
1.4
1.79
V
C
17
tPOR
POR re-arm time
—
10
—
—
s
D
VDD falling
2.11
2.16
2.22
V
P
VDD rising
2.16
2.21
2.27
V
P
VDD falling
1.80
1.82
1.91
V
P
VDD rising
1.86
1.90
1.99
V
P
VDD falling
2.36
2.46
V
P
VDD rising
2.36
2.46
2.56
V
P
VDD falling
2.11
2.16
2.22
V
P
VDD rising
2.16
2.21
2.27
V
P
19
20
21
3
4
5
6
7
C
IIC
18
2
Minimum Typical1 Maximum Unit
—
13
1
Condition
VLVDH
VLVDL
Low-voltage detection threshold — high
range9
Low-voltage detection threshold — low range9
VLVWH Low-voltage warning threshold — high
VLVWL
D
range9
2.56
Low-voltage warning threshold — low range9
22
Vhys
Low-voltage inhibit reset/recover
hysteresis10
—
—
50
—
mV
C
23
VBG
Bandgap Voltage Reference11
—
1.145
1.17
1.195
V
P
Typical values are measured at 25C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
Does not include analog module pins. Dedicated analog pins should not be pulled to VDD or VSS and should be left floating when not used
to reduce current leakage.
Measured with VIn = VDD.
All functional non-supply pins are internally clamped to VSS and VDD,except PTD1.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values
for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive
injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out
of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU
is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power
consumption).
MCF51JE256 Datasheet, Rev. 4
20
Freescale Semiconductor
Preliminary Electrical Characteristics
8
9
10
11
Maximum is highest voltage that POR is guaranteed.
Run at 1 MHz bus frequency.
Low voltage detection and warning limits measured at 1 MHz bus frequency.
Factory trimmed at VDD = 3.0 V, Temp = 25C.
3.6
Supply Current Characteristics
Table 10. Supply Current Characteristics
#
Symbol
1
RIDD
2
3
4
5
RIDD
RIDD
RIDD
WIDD
Parameter
Bus
Freq
VDD
(V)
Unit
Temperature
(C)
C
25.165 MHz
3
44
48
mA
–40 to 25
P
25.165 MHz
3
44
48
mA
105
P
20 MHz
3
32.3
—
mA
–40 to 105
T
8 MHz
3
16.4
—
mA
–40 to 105
T
1 MHz
3
2.9
—
mA
–40 to 105
T
25.165 MHz
3
29
29.6
mA
–40 to 105
C
20 MHz
3
25.4
—
mA
–40 to 105
T
8 MHz
3
12.7
—
mA
–40 to 105
T
1 MHz
3
2.4
—
mA
–40 to 105
T
16 kHz FBI
3
232
280
A
–40 to 105
T
16 kHz FBE
3
231
296
A
–40 to 105
T
16 kHz
BLPE
3
74
75
A
0 to 70
T
16 kHz
BLPE
3
74
120
A
–40 to 105
T
25.165 MHz
3
16.5
—
mA
–-40 to 105
C
20 MHz
3
10.3
—
mA
–-40 to 105
T
8 MHz
3
6.6
—
mA
–-40 to 105
T
1 MHz
3
1.7
—
mA
–-40 to 105
T
Typical1 Maximum
Run supply current
FEI mode, all modules ON2
Run supply current
FEI mode, all modules OFF3
Run supply current
LPR=0, all modules OFF3
Run supply current
LPR=1, all modules OFF3
Wait mode supply current
FEI mode, all modules OFF3
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
21
Preliminary Electrical Characteristics
Table 10. Supply Current Characteristics (continued)
#
Symbol
6
S2IDD
7
Parameter
Bus
Freq
VDD
(V)
Unit
Temperature
(C)
C
N/A
3
0.410
1
A
-40 to 25
P
N/A
3
3.7
10
A
70
C
N/A
3
10
20
A
85
C
N/A
3
21
31.5
A
105
P
N/A
2
0.410
0.640
A
-40 to 25
C
N/A
2
3.4
9
A
70
C
N/A
2
9.5
18
A
85
C
N/A
2
20
30
A
105
C
N/A
3
0.750
1.3
A
-40 to 25
P
N/A
3
8.5
18
A
70
C
N/A
3
20
28
A
85
C
N/A
3
53
63
A
105
P
N/A
2
0.400
0.900
A
-40 to 25
C
N/A
2
8.2
16
A
70
C
N/A
2
18
26
A
85
C
N/A
2
47
59
A
105
C
Typical1 Maximum
Stop2 mode
supply current4
Stop3 mode
supply current
No clocks active
S3IDD
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
ON = System Clock Gating Control registers turn on system clock to the corresponding modules.
3 OFF = System Clock Gating Control registers turn off system clock to the corresponding modules.
4
All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages may have some pins that
are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in a known state.
Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. NOTE: I/O pins are configured to
output low; input-only pins are configured to pullup-enabled. IRO pin connects to ground. FB_AD12 pin is pullup-enabled. DACO, and VREFO pins
are at reset state and unconnected.
2
Table 11. Stop Mode Adders
Temperature (°C)
#
Parameter
1
LPO
2
EREFSTEN
3
1
IREFSTEN
4
TOD
Condition
—
RANGE = HGO = 0
—
Does not include clock source current
Units
C
250
nA
D
850
1000
nA
D
80
93
125
A
T
100
150
250
nA
D
-40
25
70
85
105
50
75
100
150
600
650
750
—
73
50
75
MCF51JE256 Datasheet, Rev. 4
22
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. Stop Mode Adders (continued)
Temperature (°C)
#
5
1
Parameter
LVD1
Condition
Units
C
172
A
T
-40
25
70
85
105
LVDSE = 1
116
117
126
132
6
PRACMP
Not using the bandgap (BGBE = 0)
17
18
24
35
74
A
T
7
ADC1
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
75
85
100
115
165
A
T
8
DAC1
High power mode; no load on DACO
500
500
500
500
500
A
T
1
Not available in stop2 mode.
Figure 6. Stop IDD versus Temperature
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
23
Preliminary Electrical Characteristics
3.7
PRACMP Electricals
Table 12. PRACMP Electrical Specifications
#
3.8
Characteristic
Symbol
Minimum
Typical
Maximum
Unit
C
VPWR
1.8
—
3.6
V
P
1
Supply voltage
2
Supply current (active) (PRG enabled)
IDDACT1
—
—
80
A
D
3
Supply current (active) (PRG disabled)
IDDACT2
—
—
40
A
D
4
Supply current (ACMP and PRG all
disabled)
IDDDIS
—
—
2
nA
D
5
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
D
6
Analog input offset voltage
VAIO
—
5
40
mV
D
7
Analog comparator hysteresis
VH
3.0
—
20.0
mV
D
8
Analog input leakage current
IALKG
—
—
1
nA
D
9
Analog comparator initialization delay
tAINIT
—
—
1.0
s
D
10
Programmable reference generator inputs
VIn2 (VDD25)
1.8
—
2.75
V
D
11
Programmable reference generator setup
delay
tPRGST
—
1
—
s
D
12
Programmable reference generator step
size
Vstep
0.75
1
1.25
LSB
D
13
Programmable reference generator voltage
range
Vprgout
VIn/32
—
Vin
V
P
Unit
C
12-bit DAC Electricals
Table 13. DAC 12LV Operating Requirements
#
1
Characteristic
Symbol
Minimum Maximum
1
Supply voltage
VDDA
1.8
3.6
V
P
2
Reference voltage
VDACR
1.15
3.6
V
C
3
Temperature
TA
-40
105
°C
C
4
Output load capacitance1
CL
—
100
pF
C
5
Output load current
IL
—
1
mA
C
A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
MCF51JE256 Datasheet, Rev. 4
24
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Symbol
Minimum
Typical Maximum Unit
C
N
12
—
12
bit
T
—
50
100
A
T
—
345
500
A
T
Notes
1
Resolution
2
Supply current low-power mode
IDDA_DAC
3
Supply current high-power mode
IDDA_DAC
4
Full-scale Settling time (1 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode
5
Full-scale Settling time (1 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode
TsFSHP
—
—
30
s
T
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
6
Code-to-code Settling time (1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8) low-power mode
TsC-CLP
—
—
5
s
T
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature = 25°C
7
Code-to-code Settling time (1 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8) high-power mode
TsC-CHP
—
1
—
s
T
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature = 25°C
8
DAC output voltage range low
(high-power mode, no load, DAC set
to 0, 3 V at room temperature)
Vdacoutl
—
—
mV
T
9
DAC output voltage range high
(high-power mode, no load, DAC set
to 0x0FFF)
Vdacouth
VDACR–100
—
mV
T
10
Integral non-linearity error
INL
—
—
8
LSB
T
11
Differential non-linearity error
VDACR is > 2.4 V
DNL
—
—
±1
LSB
T
12
Offset error
13
Gain error (VREF = Vext = VDD)
14
Power supply rejection ratio
VDD 2.4 V
LP
HP
TsFSLP
EO
—
—
—
±0.4
200
100
—
±3
s
%FSR
T
• VDDA = 3 V or 2.2 V
• VREFSEL = 1
• Temperature
= 25°C
T
Calculated by a best fit
curve from VSS +
100mV to VREFH
–100mV
Calculated by a best fit
curve from VSS +
100mV to VREFH
–100mV
EG
—
±0.1
±0.5
%FSR
T
PSRR
60
—
—
dB
T
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
25
Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Symbol
Minimum
Typical Maximum Unit
15
Temperature drift of offset voltage
(DAC set to 0x0800)1
Tco
—
—
16
Offset aging coefficient
AC
—
—
1
2
8
C
Notes
mV
T
See Typical Drift figure
that follows.
V/yr
T
See Typical Drift figure that follows.
Figure 7. Offset at Half Scale vs Temperature
3.9
ADC Characteristics
Table 15. 12-bit ADC Operating Conditions
#
Symb
1
VDDAD
2
VDDAD
3
VSSAD
4
VREFH
Characteristic
Supply voltage
Minimum Typical1 Maximum
Conditions
Absolute
Supply voltage Delta to VDD (VDD-VDDAD)2
Ground voltage
Ref Voltage High
Delta to VSS (VSS-VSSAD
—
)2
Unit
C
1.8
—
3.6
V
D
-100
0
+100
mV
D
-100
0
+100
mV
D
1.13
VDDAD
VDDAD
V
D
MCF51JE256 Datasheet, Rev. 4
26
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 15. 12-bit ADC Operating Conditions (continued)
Symb
Characteristic
Conditions
Unit
C
5
VREFL
Ref Voltage Low
—
VSSAD
VSSAD
VSSAD
V
D
6
VADIN
Input Voltage
—
VREFL
—
VREFH
V
D
7
CADIN
Input
Capacitance
—
—
4
5
pF
C
8
RADIN
Input Resistance
—
—
2
5
k
C
9
RAS
—
—
1
k
C
4 MHz < fADCK > 8 MHz
—
—
2
k
C
fADCK < 4 MHz
—
—
5
k
C
10-bit mode
fADCK > 8MHz
—
—
2
k
C
4 MHz < fADCK < 8 MHz
—
—
5
k
C
fADCK < 4 MHz
—
—
10
k
C
8-bit mode
fADCK > 8 MHz
—
—
5
k
C
fADCK < 8 MHz
—
—
10
k
C
High Speed (ADLPC=0,
ADHSC=1)
1.0
—
8.0
MHz
D
High Speed (ADLPC=0,
ADHSC=0)
1.0
—
5.0
MHz
D
Low Power (ADLPC=1,
ADHSC=1)
1.0
—
2.5
MHz
D
Analog Source Resistance3
12 bit mode
fADCK > 8 MHz
10
1
2
3
Minimum Typical1 Maximum
#
fADCK
ADC Conversion Clock Freq.
Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential difference.
External to MCU. Assumes ADLSMP=0.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
27
Preliminary Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 8. ADC Input Impedance Equivalency Diagram
Table 16. 12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD)
#
1
2
Symbol
IDDAD
Characteristic
Supply Current
(ADLSMP=0,
ADCO=1)
ADC
Asynchronous
fADACK Clock Source
(tADACK
=1/fADACK)
Conditions1
Minimum Typical2 Maximum
—
215
—
A
T
ADLPC=0, ADHSC=0
—
470
—
A
T
ADLPC=0, ADHSC=1
—
610
—
A
T
Stop, Reset, Module Off
—
0.01
—
A
C
ADLPC=1, ADHSC=0
—
2.4
—
MHz
P
ADLPC=0, ADHSC=0
—
5.2
—
MHz
P
ADLPC=0, ADHSC=1
—
6.2
—
MHz
P
3.5
LSB3
T
T
—
Sample Time — See Reference Manual for sample times.
4
—
Conversion Time — See Rreference Manual for conversion times.
TUE
—
1.75
—
0.8
±1.5
LSB3
—
0.5
±1.0
LSB3
T
—
0.7
1
LSB3
T
10-bit single-ended mode
—
0.5
±0.75
LSB3
T
8-bit single-ended mode
—
0.2
±0.5
LSB3
T
Total Unadjusted 12-bit single-ended mode
Error
10-bit single-ended mode
32x Hardware
Averaging (AVGE
= %1 AVGS =
8-bit single-ended mode
%11)
12-bit single-ended mode
6
Differential
Non-Linearity
C
ADLPC=1, ADHSC=0
3
5
Unit
MCF51JE256 Datasheet, Rev. 4
28
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 16. 12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD) (continued)
#
Symbol
Conditions1
Minimum Typical2 Maximum
Unit
C
—
1.0
2.5
LSB3
T
10-bit single-ended mode
—
0.5
±1.0
3
LSB
T
8-bit single-ended mode
—
0.3
±0.5
LSB3
T
12-bit single-ended mode
—
0.7
2.0
LSB3
T
—
0.4
±1.0
LSB3
T
—
0.2
±0.5
3
T
—
1.0
3.5
3
LSB
T
—
0.4
±1.5
LSB3
T
—
0.2
±0.5
3
LSB
T
—
—
±0.5
LSB3
D
mV
D
Characteristic
12-bit single-ended mode
7
8
9
3
EFS
12-bit single-ended mode
Full-Scale Error
10-bit single-ended mode
(VADIN = VDDAD)
8-bit single-ended mode
Quantization
Error
All modes
11
EIL
Input Leakage
Error (IIn =
leakage current
(refer to DC
Characteristics)
All modes
12
m
Temp Sensor
Slope
13
2
EZS
Zero-Scale Error
10-bit single-ended mode
(VADIN = VSSAD)
8-bit single-ended mode
EQ
10
1
INL
Integral
Non-Linearity
VTEMP25
Temp Sensor
Voltage
IIn * RAS
LSB
-40C to 25C
—
1.646
—
mV/xC
C
25C to 125C
—
1.769
—
mV/xC
C
25C
—
701.2
—
mV
C
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD.
Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
3.10
MCG and External Oscillator (XOSC) Characteristics
Table 17. MCG (Temperature Range = –40 to 105C Ambient)
#
Rating
1 Internal reference startup time
Average internal reference
2
frequency
factory trimmed at
VDD=3.0V and
temp=25C
Symbol
Min
Typical
Max
Unit
C
tirefst
—
55
100
s
D
—
31.25
—
kHz
C
31.25
—
39.0625
KHz
C
16
—
20
MHz
C
32
—
40
MHz
C
40
—
60
MHz
C
—
0.1
0.2
%fdco
C
—
0.2
0.4
%fdco
C
fint_ft
user trimmed
Low range (DRS=00)
3
DCO output frequency range trimmed
Resolution of trimmed DCO output
4 frequency at fixed voltage and
temperature
Mid range (DRS=01)
fdco_t
High range1
(DRS=10)
with FTRIM
without FTRIM
fdco_res_t
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
29
Preliminary Electrical Characteristics
Table 17. MCG (Temperature Range = –40 to 105C Ambient) (continued)
#
Rating
Total deviation of trimmed DCO
5 output frequency over voltage and
temperature
6
7
Acquisition time
Symbol
over fixed voltage
and temp range
of 0 - 70 C
Max
Unit
C
—
1.0
2
%fdco
P
—
0.5
1
%fdco
C
fdco_t
FLL2
tfll_acquire
—
—
1
ms
C
PLL3
tpll_acquire
—
—
1
ms
D
CJitter
—
0.02
0.2
%fdco
C
fvco
7.0
—
55.0
MHz
D
fpll_ref
1.0
—
2.0
MHz
D
Long term Jitter of DCO output clock (averaged over 2mS
interval) 4
9 PLL reference frequency range
Jitter of PLL output clock measured
Long term
over 625 ns
11 Lock frequency tolerance
Typical
over voltage and
temperature
8 VCO operating frequency
10
Min
fpll_jitter_625
ns
4
—
0.566
—
%fpll
D
2.98
%
D
Entry5
Dlock
1.49
—
Exit6
Dunl
4.47
—
5.97
%
D
s
D
D
FLL
tfll_lock
—
—
tfll_acquire+
1075(1/fint_t)
PLL
tpll_lock
—
—
tpll_acquire+
1075(1/fpll_ref)
s
13 Loss of external clock minimum frequency - RANGE = 0
floc_low
(3/5) x
fint_t
—
—
kHz
14 Loss of external clock minimum frequency - RANGE = 1
floc_high
(16/5) x
fint_t
—
—
kHz
12 Lock time
1
2
3
4
5
6
D
D
This should not exceed the maximum CPU frequency of 50.33 MHz.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
being used as the reference, this specification assumes it is already running.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI)
to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are
made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via
VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already
in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
MCF51JE256 Datasheet, Rev. 4
30
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 18. XOSC (Temperature Range = –40 to 105C Ambient)
#
1
2
Symbol Minimum Typical1 Maximum Unit
Characteristic
Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
• Low range (RANGE = 0)
flo
32
—
38.4
kHz
• High range (RANGE = 1),
• FEE or FBE mode 2
fhi-fll
1
—
5
MHz
• High range (RANGE = 1),
• PEE or PBE mode 3
fhi-pll
1
—
16
MHz
• High range (RANGE = 1),
• High gain (HGO = 1),
• FBELP mode
fhi-hgo
1
—
16
MHz
• High range (RANGE = 1),
• Low power (HGO = 0),
• FBELP mode
fhi-lp
1
—
8
MHz
C1
C2
Load capacitors
Feedback resistor
Low range
(32 kHz to 38.4 kHz)
RF
See Note 4
—
10
—
3
M
High range
(1 MHz to 16 MHz)
Series resistor — Low range
—
—
1
—
—
0
—
—
100
—
—
0
—
—
0
0
4 MHz
—
0
10
1 MHz
—
0
20
—
200
—
—
400
—
—
5
—
—
15
—
Low Gain (HGO = 0)
4
High Gain (HGO = 1)
RS
• Low Gain (HGO = 0)
k
• High Gain (HGO = 1)
5
Series resistor — High range
8 MHz
RS
Low range, low gain
(RANGE=0,HGO=0)
6
Crystal start-up time 5, 6
Low range, high gain
(RANGE=0,HGO=1)
t
CSTL
ms
High range, low gain
(RANGE=1,HGO=0)
High range, high gain (RANGE=1,
HGO=1)
1
k
tCSTH
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625
kHz.
When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz to 2 MHz.
See crystal or resonator manufacturer’s recommendation.
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
2
3
4
5
6
o
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
31
Preliminary Electrical Characteristics
3.11
Mini-FlexBus Timing Specifications
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to
interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected
to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices, a simple
chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect
to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus
frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the
Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values.
Table 19. Mini-FlexBus AC Timing Specifications
#
1
2
Characteristic
Symbol
Min
Max
Unit
C
—
—
25.1666
MHz
—
1
Frequency of Operation
2
Clock Period
MB1
39.73
—
ns
D
3
Output Valid1
MB2
—
20
ns
T
4
Output Hold1
MB3
1.0
—
ns
D
5
Input Setup2
MB4
22
—
ns
T
6
Input Hold2
MB5
10
—
ns
D
Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE.
Specification is valid for all MB_D[7:0].
MCF51JE256 Datasheet, Rev. 4
32
Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 9. Mini-FlexBus Read Timing
Figure 10. Mini-FlexBus Write Timing
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
33
Preliminary Electrical Characteristics
3.12
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.12.1
Control Timing
Table 20. Control Timing
#
1
Minimum
Typica
l1
Maximum
Unit
C
VDD 1.8 V
fBus
dc
—
10
MHz
D
VDD > 2.1 V
fBus
dc
—
20
MHz
D
VDD > 2.4 V
fBus
dc
—
25.165
MHz
D
tLPO
700
1000
1300
s
P
textrst
100
—
—
ns
D
trstdrv
66 x tcyc
—
—
ns
D
latch setup time
tMSSU
500
—
—
ns
D
latch hold time
tMSH
100
—
—
ns
D
Bus frequency (tcyc = 1/fBus)
2
Internal low-power oscillator period
3
External reset pulse width2
4
Reset low drive
5
Symbol
Parameter
Active background debug mode
(tcyc =
1/fSelf_reset)
6
Active background debug mode
7
IRQ pulse width
• Asynchronous path2
• Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
8
KBIPx pulse width
• Asynchronous path2
• Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
9
Port rise and fall time (load = 50 pF)4, Low Drive
tRise, tFall
—
11
—
ns
D
tRise, tFall
—
35
—
ns
D
tRise, tFall
—
40
—
ns
D
tRise, tFall
—
75
—
ns
D
Slew rate
control disabled
(PTxSE = 0)
Slew rate
control enabled
(PTxSE = 1)
Slew rate
control disabled
(PTxSE = 0)
Slew rate
control enabled
(PTxSE = 1)
1
2
3
4
D
D
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset
requests from internal sources.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be
recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
MCF51JE256 Datasheet, Rev. 4
34
Freescale Semiconductor
Preliminary Electrical Characteristics
textrst
RESET PIN
Figure 11. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 12. IRQ/KBIPx Timing
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
35
Preliminary Electrical Characteristics
3.12.2
TPM Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 21. TPM Input Timing
#
C
Function
Symbol
Minimum
Maximum
Unit
1
—
External clock frequency
fTPMext
dc
fBus/4
MHz
2
—
External clock period
tTPMext
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTPMext
tclkh
TPMxCLK
tclkl
Figure 13. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 14. Timer Input Capture Pulse
MCF51JE256 Datasheet, Rev. 4
36
Freescale Semiconductor
Preliminary Electrical Characteristics
3.13
SPI Characteristics
The following table and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 22. SPI Timing
No.1
Characteristic2
Symbol
Minimum
Maximum
Unit
C
Master
Slave
fop
fop
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
D
Master
Slave
tSPSCK
tSPSCK
2
4
2048
—
tcyc
tcyc
D
Master
Slave
tLead
tLead
12
1
—
—
tSPSCK
tcyc
D
Master
Slave
tLag
tLag
12
1
—
—
tSPSCK
tcyc
D
Master
Slave
tWSPSCK
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
—
ns
ns
D
Master
Slave
tSU
tSU
15
15
—
—
ns
ns
D
Master
Slave
tHI
tHI
0
25
—
—
ns
ns
D
ta
—
1
tcyc
D
tdis
—
1
tcyc
D
Master
Slave
tv
tv
—
—
25
25
ns
ns
D
Master
Slave
tHO
tHO
0
0
—
—
ns
ns
D
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
D
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
D
Operating frequency
1
SPSCK period
2
Enable lead time
3
Enable lag time
4
Clock (SPSCK) high or low time
5
Data setup time (inputs)
6
Data hold time (inputs)
7
8
9
Slave access time3
Slave MISO disable
time4
Data valid (after SPSCK edge)
10
Data hold time (outputs)
11
Rise time
12
Fall time
13
1
2
3
4
Numbers in this column identify elements in Figure 15 through Figure 18.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
37
Preliminary Electrical Characteristics
SS1
(OUTPUT)
2
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
11
MOSI
(OUTPUT)
LSB IN
11
MSB OUT2
12
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
2
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
11
MOSI
(OUTPUT)
BIT 6 . . . 1
LSB IN
12
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 16. SPI Master Timing (CPHA = 1)
MCF51JE256 Datasheet, Rev. 4
38
Freescale Semiconductor
Preliminary Electrical Characteristics
SS
(INPUT)
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
12
11
BIT 6 . . . 1
MSB OUT
SLAVE
SLAVE LSB OUT
SEE
NOTE
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined, but normally MSB of character just received
Figure 17. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
2
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
11
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
12
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined, but normally LSB of character just received
Figure 18. SPI Slave Timing (CPHA = 1)
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
39
Preliminary Electrical Characteristics
3.14
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory chapter in the Reference
Manual for this device (MCF51JE256RM).
Table 23. Flash Characteristics
#
3
4
Minimum
Typical
Maximum
Unit
3.6
V
C
Supply voltage for program/erase
-40C to 105C
Vprog/erase
1.8
2
Supply voltage for read operation
VRead
1.8
—
3.6
V
D
fFCLK
150
—
200
kHz
D
5
—
6.67
s
D
frequency1
—
D
3
Internal FCLK
4
Internal FCLK period (1/FCLK)
tFcyc
5
Byte program time (random location)2
tprog
9
tFcyc
P
7
2
Symbol
1
6
1
Characteristic
Byte program time (burst
Page erase time
mode)2
tBurst
4
tFcyc
P
2
tPage
4000
tFcyc
P
2
tMass
20,000
tFcyc
P
8
Mass erase time
9
Program/erase endurance3
TL to TH = –40C to + 105C
T = 25C
10
Data retention4
tD_ret
10,000
—
—
100,000
—
—
cycles
15
100
—
years
C
C
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating
approximate time to program and erase.
Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines
typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using
the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618,
Typical Data Retention for Nonvolatile Memory.
3.15
USB Electricals
The USB electricals for the USB On-the-Go module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the
standard or require additional information, this space would be used to communicate that information.
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics
#
Characteristic
Symbol
Minimum
Typical
Maximu
m
Unit
C
1
Regulator operating voltage
Vregin
3.9
—
5.5
V
C
2
VREG output
Vregout
3
3.3
3.75
V
P
MCF51JE256 Datasheet, Rev. 4
40
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 24. Internal USB 3.3 V Voltage Regulator Characteristics (continued)
#
Characteristic
3
VUSB33 input with internal VREG
disabled
4
VREG Quiescent Current
3.16
Symbol
Minimum
Typical
Maximu
m
Unit
C
Vusb33in
3
3.3
3.6
V
C
IVRQ
—
0.5
—
mA
C
VREF Electrical Specifications
Table 25. VREF Electrical Specifications
#
Characteristic
Symbol
Minimum
Maximum
Unit
C
VDDA
1.80
3.6
V
C
1
Supply voltage
2
Temperature
TA
–40
105
C
C
3
Output Load Capacitance
CL
—
100
nf
D
4
Maximum Load
—
—
10
mA
—
5
Voltage Reference Output with Factory
Trim. VDD = 3 V.
Vout
1.148
1.152
V
P
6
Temperature Drift (Vmin - Vmax across
the full temperature range)
Tdrift
—
25
mV1
T
7
Aging Coefficient2
Ac
—
60
V/year
C
8
Powered down Current (Off Mode,
VREFEN = 0, VRSTEN = 0)
I
—
0.10
A
C
9
Bandgap only (MODE_LV[1:0] = 00)
I
—
75
A
T
10
Low-Power buffer (MODE_LV[1:0] = 01)
I
—
125
A
T
11
Tight-Regulation buffer (MODE_LV[1:0]
= 10)
I
—
1.1
mA
T
12
Load Regulation (MODE_LV = 10)
—
—
100
V/mA
C
13
Line Regulation MODE = 1:0, Tight
Regulation VDD < 2.3 V, Delta VDDA =
100 mV, VREFH = 1.2 V driven
externally with VREFO disabled.
(Power Supply Rejection
DC
70
dB
C
—
1
See typical chart below.
Linear reliability model (1008 hours stress at 125oC = 10 years operating life) used to calculate Aging V/year. Vrefo data recorded per
month.
2
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
41
Preliminary Electrical Characteristics
Table 26. VREF Limited Range Operating Behaviors
#
1
Characteristic
Symbol
1
Voltage Reference Output with
Factory Trim
Vout
2
Temperature Drift (Vmin – Vmax
Temperature range from 0° C to
50° C
Tdrift
Minimum
1.149
—
Maximum
Unit
C
1.152
mV
T
3
mV1
T
See typical chart that follows (Figure 19).
Figure 19. Typical VREF Output vs Temperature
MCF51JE256 Datasheet, Rev. 4
42
Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 20. Typical VREF Output vs VDD
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
43
Ordering Information
4
Ordering Information
This section contains ordering information for the device numbering system. See Table 1 for feature
summary by package information.
4.1
Part Numbers
Table 27. Orderable Part Number Summary
Freescale Part
Number
Description
Flash / SRAM
(Kbytes)
Package
Temperature
MCF51JE256VML
MCF51JE256 ColdFire Microcontroller
256K/32K
104 MAPBGA
–40 to 105 °C
MCF51JE256VLL
MCF51JE256 ColdFire Microcontroller
256K/32K
100 LQFP
–40 to 105 °C
MCF51JE256VMB
MCF51JE256 ColdFire Microcontroller
256K/32K
81 MAPBGA
–40 to 105 °C
MCF51JE256VLK
MCF51JE256 ColdFire Microcontroller
256K/32K
80 LQFP
–40 to 105 °C
MCF51JE128VMB
MCF51JE128 ColdFire Microcontroller
128K/32K
81 MAPBGA
–40 to 105 °C
MCF51JE256CML
MCF51JE256 ColdFire Microcontroller
256K/32K
104 MAPBGA
–40 to 85 °C
MCF51JE256CLL
MCF51JE256 ColdFire Microcontroller
256K/32K
10O LQFP
–40 to 85 °C
MCF51JE256CMB
MCF51JE256 ColdFire Microcontroller
256K/32K
81 MAPBGA
–40 to 85 °C
MCF51JE256CLK
MCF51JE256 ColdFire Microcontroller
256K/32K
80 LQFP
–40 to 85 °C
MCF51JE128CMB
MCF51JE128 ColdFire Microcontroller
128K/32K
81 MAPBGA
–40 to 85 °C
MCF51JE128CLK
MCF51JE128 ColdFire Microcontroller
128K/32K
80 LQFP
–40 to 85 °C
4.2
Package Information
Table 28. Package Descriptions
Pin Count
100
4.3
Package Type
Low Quad Flat Package
Abbreviation
Designator
Case No.
Document No.
LQFP
LL
983-03
98ASS23308W
80
Low Quad Flat Package
LQFP
LK
1418
98ASS23174W
104
MAP BGA Package
MAPBGA
ML
1285-02
98ARH98267A
81
MAP BGA Package
MAPBGA
MB
1662-01
98ASA10670D
Mechanical Drawings
Table 28 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MCF51JE256/128 Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 28, or
MCF51JE256 Datasheet, Rev. 4
44
Freescale Semiconductor
Revision History
•
Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate
document number (from Table 28) in the “Enter Keyword” search box at the top of the page.
5
Revision History
This section lists major changes between versions of the MCF51JE256 Data Sheet.
Table 29. Revision History
Revision
Date
0
March/April 09
Description
Initial Draft
1
July 2009
•
•
•
•
2
July 2009
• Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference
Frequency typical value from 32.768 to 31.25
April 2010
• Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices.
• Revised the ESD and Latch-Up Protection Characeristic description to read: Latch-up
Current at TA = 125°C.
• Changed Table 9. DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA
conditions to 1.8 V, ILoad = 600A respectively.
• Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value
to be 1.13 instead of 1.15.
• Updated the ADC electricals.
• Inserted the Mini-FlexBus Timing Specifications.
• Added a Temp Drift parameter to the VREF Electrical Specifications.
• Removed the S08 Naming Convention diagram.
• Updated the Orderable Part Number Summary to include the Freescale Part Number
suffixes.
• Completed the Package Description table values.
• Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W.
• Updated electrical characteristic data.
3
Revised to follow standard template.
Removed extraneous headings from the TOC.
Corrected units for Monotoncity to be blank in for the DAC specification.
Updated ADC characteristic tables to include 16-Bit SAR in headings.
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
45
Revision History
Table 29. Revision History
Revision
4
Date
Description
August 2012
• In Table 1.”MCF51JE256/128 Features by MCU and Package, removed the row of
“12-bit SAR ADCDifferential Channels”.
• In Table 3, “Package Pin Assignments”, changed from: ‘A1’ — PTG1 USB_
SESSEND to:’B3’ — PTG1 USB_ SESSEND.
• In Table 10,”Supply Current Characteristics”, for S3IDD changed the max value from
‘1.2’ to ‘1.3’ and typical value from ‘0.650’ to ‘0.750’ for the first row.
• In Table 10,”Supply Current Characteristics”:
— For parameter 3 and parameter 4 changed LPS to LPR.
— For parameter 3,changed “FBILP” to “FBI”.
— For parameter 4, changed “FBELP” to “BLPE”.
• Fixed the TBD parameters and added figure"Typical Output vs VDD", following the
same setup of MM256DS
— Added Figure 7,”Offset at Half Scale vs Temperature”.
— Updated Table 9,”DC Characteristics”.
— Updated Table 10,”Supply Current Characteristics”.
— Updated Table 11,”Stop Mode Adders”.
— Added Figure 20,”Typical Output vs. VDD.
— Updated Table 14,”DAC 12-Bit Operating Behaviors”.
— Updated Table 20,”Control Timing”.
— Removed “SPI Electrical Characteristics” table.
— Updated Table 25”VREF Electrical Specifications”.
— Updated Table 26,”VREF Limited Range Operating Behaviors“.
• Updated Figure 3, Figure 4, and Figure 5.
MCF51JE256 Datasheet, Rev. 4
46
Freescale Semiconductor
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Document Number: MCF51JE256
Rev. 4
08/2012
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