Freescale Semiconductor
Data Sheet: Technical Data
MCF51JF128
Document Number MCF51JF128
Rev. 7, 03/2015
MCF51JF128
Supports the MCF51JF128VLH,
MCF51JF128VHS, MCF51JF64VLF,
MCF51JF64VHS, MCF51JF32VHS,
MCF51JF32VFM
Features
• Operating characteristics
– Voltage range: 1.71 V to 3.6 V
– Flash write voltage range: 1.71 V to 3.6 V
– Temperature range (ambient): -40°C to 105°C
• Core
– Up to 50 MHz V1 ColdFire CPU
– Dhrystone 2.1 performance: 1.10 DMIPS per MHz
when executing from internal RAM, 0.99 DMIPS
per MHz when executing from flash memory
• System
– DMA controller with four programmable channels
– Integrated ColdFire DEBUG_Rev_B+ interface with
single-wire BDM connection
• Power management
– 10 low power modes to provide power optimization
based on application requirements
– Low-leakage wakeup unit (LLWU)
– Voltage regulator (VREG)
• Clocks
– Crystal oscillators (two, each with range options): 1
kHz to 32 kHz (low), 1 MHz to 8 MHz (medium), 8
MHz to 32 MHz (high)
– Multipurpose clock generator (MCG)
• Memories and memory interfaces
– Flash memory, FlexNVM, FlexRAM, and RAM
– Serial programming interface (EzPort)
– Mini-FlexBus external bus interface
• Security and integrity
– Hardware CRC module to support fast cyclic
redundancy checks
– Hardware random number generator (RNGB)
– Hardware cryptographic acceleration unit (CAU)
– 128-bit unique identification (ID) number per chip
© 2010–2015 Freescale Semiconductor, Inc.
• Analog
– 12-bit SAR ADC
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference (VREF)
• Timers
– Programmable delay block (PDB)
– Motor control/general purpose/PWM timers (FTM)
– 16-bit low-power timers (LPTMRs)
– 16-bit modulo timer (MTIM)
– Carrier modulator transmitter (CMT)
• Communication interfaces
– UARTs with Smart Card support and FIFO
– SPI modules, one with FIFO
– Inter-Integrated Circuit (I2C) modules
– USB full/low speed On-the-Go controller with onchip transceiver
– Integrated Interchip Sound (I2S) / Serial Audio
Interface (SAI) to support full-duplex serial
interfaces with frame sync such as AC97 and
CODEC
• Human-machine interface
– Up to 48 EGPIO pins
– Up to 16 rapid general purpose I/O (RGPIO) pins
– Low-power hardware touch sensor interface (TSI)
– Interrupt request pin (IRQ)
Table of Contents
1 Ordering parts.......................................................................................3
5.4.1
Thermal operating requirements.................................... 20
1.1 Determining valid orderable parts............................................... 3
5.4.2
Thermal attributes.......................................................... 20
2 Part identification................................................................................. 3
6 Peripheral operating requirements and behaviors................................ 21
2.1 Description...................................................................................3
6.1 Core modules............................................................................... 21
2.2 Format.......................................................................................... 3
6.1.1
Debug specifications...................................................... 21
2.3 Fields............................................................................................3
6.2 System modules........................................................................... 21
2.4 Example....................................................................................... 4
6.3 Clock modules............................................................................. 21
3 Terminology and guidelines.................................................................4
6.3.1
MCG specifications........................................................21
3.1 Definition: Operating requirement...............................................4
6.3.2
Oscillator electrical specifications................................. 23
3.2 Definition: Operating behavior.................................................... 4
6.4 Memories and memory interfaces................................................26
3.3 Definition: Attribute.................................................................... 5
6.4.1
Flash electrical specifications........................................ 26
3.4 Definition: Rating........................................................................ 5
6.4.2
EzPort Switching Specifications.................................... 29
3.5 Result of exceeding a rating.........................................................6
6.4.3
Mini-Flexbus Switching Specifications......................... 30
3.6 Relationship between ratings and operating requirements.......... 6
6.5 Security and integrity modules.................................................... 32
3.7 Guidelines for ratings and operating requirements......................6
6.6 Analog..........................................................................................33
3.8 Definition: Typical value............................................................. 7
6.6.1
ADC electrical specifications.........................................33
4 Ratings..................................................................................................8
6.6.2
CMP and 6-bit DAC electrical specifications................36
4.1 Thermal handling ratings............................................................. 8
6.6.3
12-bit DAC electrical characteristics............................. 38
4.2 Moisture handling ratings............................................................ 8
6.6.4
Voltage reference electrical specifications.....................41
4.3 ESD handling ratings................................................................... 8
6.7 Timers.......................................................................................... 42
4.4 Voltage and current operating ratings..........................................8
6.8 Communication interfaces........................................................... 42
5 General................................................................................................. 9
6.8.1
USB electrical specifications......................................... 42
5.1 Typical Value Conditions............................................................ 9
6.8.2
USB DCD electrical specifications................................43
5.2 Nonswitching electrical specifications........................................ 9
6.8.3
USB VREG electrical specifications............................. 43
5.2.1
Voltage and Current Operating Requirements...............9
6.8.4
SPI switching specifications.......................................... 44
5.2.2
LVD and POR operating requirements.......................... 10
6.8.5
I2S/SAI Switching Specifications..................................47
5.2.3
Voltage and current operating behaviors....................... 11
5.2.4
Power mode transition operating behaviors...................12
5.2.5
Power consumption operating behaviors....................... 13
7 Dimensions...........................................................................................50
5.2.6
EMC radiated emissions operating behaviors................16
7.1 Obtaining package dimensions.................................................... 50
5.2.7
Designing with radiated emissions in mind................... 17
8 Pinout................................................................................................... 50
5.2.8
Capacitance attributes.................................................... 17
8.1 Signal Multiplexing and Pin Assignments...................................50
5.3 Switching electrical specifications...............................................17
8.2 Pinout diagrams........................................................................... 53
5.3.1
6.9 Human-machine interfaces (HMI)...............................................49
6.9.1
TSI electrical specifications........................................... 49
General Switching Specifications.................................. 18
8.3 Module-by-module signals.......................................................... 57
5.4 Thermal specifications................................................................. 20
9 Revision History...................................................................................67
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Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device:
1. Go to www.freescale.com.
2. Perform a part number search for the following partial device numbers: PCF51JF and
MCF51JF.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q CCCC DD MMM T PP
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market
flow
• P = Prequalification
CCCC
Core code
CF51 = ColdFire V1
DD
Device number
JF, JU, QF, QH, QM, QU
MMM
Memory size (program flash memory)1
• 32 = 32 KB
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Terminology and guidelines
Field
Description
Values
• 64 = 64 KB
• 128 = 128 KB
T
Temperature range, ambient (°C)
PP
Package identifier
V = –40 to 105
• FM = 32 QFN (5 mm x 5 mm)
• HS = 44 Laminate QFN (5 mm x 5
mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
1. All parts also have FlexNVM, FlexRAM, and RAM.
2.4 Example
This is an example part number:
MCF51JF128VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
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Terminology and guidelines
3.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
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Terminology and guidelines
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
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- Correct operation
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- Possible incorrect operation
Expected permanent failure
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Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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Terminology and guidelines
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
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Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
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General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
VAIO
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
ID
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
VREGIN
USB Regulator input
–0.3
6.0
V
5 General
5.1 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
5.2 Nonswitching electrical specifications
5.2.1 Voltage and Current Operating Requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
0.7 × VDD
—
V
0.75 × VDD
—
V
VIH
Input high voltage
Notes
1
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Nonswitching electrical specifications
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
—
0.35 × VDD
V
2
—
0.3 × VDD
V
0
2
mA
0
–0.2
mA
0
25
mA
0
–5
mA
1.2
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
IIC
DC injection current — single pin
• VIN > VDD
3
• VIN < VSS
DC injection current — total MCU limit, includes sum of
all stressed pins
• VIN > VDD
3
• VIN < VSS
VRAM
VDD voltage required to retain RAM
1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to
VIH (max.), regardless of whether input hysteresis is turned on.
2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to
VIL (min.), regardless of whether input hysteresis is turned on.
3. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified.
To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp
voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during
instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external
VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall
power consumption).
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
2.62
2.70
2.78
V
2.72
2.80
2.88
V
2.82
2.90
2.98
V
2.92
3.00
3.08
V
—
±80
—
mV
VLVW1H
VLVW2H
VLVW3H
VLVW4H
VHYSH
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
Notes
1
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
high range
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Nonswitching electrical specifications
Table 2. LVD and POR operating requirements (continued)
Symbol
VLVDL
VLVW1L
VLVW2L
VLVW3L
VLVW4L
VHYSL
Description
Min.
Typ.
Max.
Unit
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
V
1.74
1.80
1.86
V
1.84
1.90
1.96
V
1.94
2.00
2.06
V
2.04
2.10
2.16
V
—
±60
—
mV
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
Notes
1
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period
900
1000
1100
μs
factory trimmed
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
0.5
V
—
100
mA
• @ full temperature range
—
1.0
μA
• @ 25 °C
—
0.1
μA
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
1
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Nonswitching electrical specifications
Table 3. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
IOZ
Total Hi-Z (off-state) leakage current (all input pins)
—
4
μA
RPU
Internal pullup resistors
22
50
kΩ
2
RPD
Internal pulldown resistors
22
50
kΩ
3
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx-RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock (and flash and Mini-FlexBus clocks) = 25 MHz
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
Min.
Max.
Unit
Notes
—
300 1.71
V/(VDD slew
rate)
μs
1
—
132
μs
—
92
μs
—
92
μs
—
7.5
μs
—
5.5
μs
—
5.5
μs
• 1.71 V/(VDD slew rate) ≤ 300 μs
• 1.71 V/(VDD slew rate) > 300 μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
1, 2
1, 2
1, 2
2
2
2
1. Normal boot (FTFL_FOPT[LPBOOT] is 1)
2. The wakeup time includes the execution time for a small amount of firmware used to produce a GPIO clear event. Wakeup
time is measured from the falling edge of the external wakeup event to the falling edge of a GPIO clear performed by
software.
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Nonswitching electrical specifications
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Min.
Typ.
Max.
Unit
Notes
Analog supply current
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from RAM
—
13
—
mA
—
13
16
mA
—
14.3
—
mA
—
14.5
17.9
mA
—
20
23.5
mA
—
20
25
mA
—
5.8
6.8
mA
—
0.34
0.41
mA
—
0.90
1.8
mA
• @ 1.8 V
2
• @ 3.0 V
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash memory with
page buffering disabled
2
• @ 1.8 V
• @ 3.0 V
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from RAM, exercising
flash memory
3
• @ 1.8 V
• @ 3.0 V
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
IDD_STOP
Stop mode current at 3.0 V
• @ –40 to 25 °C
• @ 105 °C
4
IDD_VLPR
Very low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
0.63
1.32
mA
5
IDD_VLPR
Very low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
0.78
1.46
mA
6
IDD_VLPW
Very low-power wait mode current at 3.0 V
—
0.15
0.62
mA
7
IDD_VLPS
Very low-power stop mode current at 3.0 V
• @ –40 to 25 °C
—
19
45
μA
8
—
145
312
—
3.0
4.8
μA
—
53.3
157
μA
—
1.8
3.3
μA
—
39.2
115
μA
—
1.6
2.8
μA
—
22.2
65
μA
• @ 105 °C
IDD_LLS
Low leakage stop mode current at 3.0 V
• @ –40 to 25 °C
8,9,10
• @ 105 °C
IDD_VLLS3
Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25 °C
8,9,10
• @ 105 °C
IDD_VLLS2
Very low-leakage stop mode 2 current at 3.0 V
8,9
Table continues on the next page...
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
13
Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
1.4
2.6
μA
—
17.6
50
μA
—
0.7
—
μA
Notes
• @ –40 to 25 °C
• @ 105 °C
IDD_VLLS1
Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25 °C
8,9
• @ 105 °C
IDD_RTC
Average current adder for real-time clock function
11
• @ –40 to 25 °C
1. The analog supply current is the sum of the active current for each of the analog modules on the device. See each
module's specification for its supply current.
2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.
3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but
peripherals are not in active operation.
4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.
5. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash memory.
6. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks enabled, but
peripherals are not in active operation. Code executing from flash memory.
7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
8. OSC clocks disabled.
9. All pads disabled.
10. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For
devices with 8 KB of RAM, power consumption is reduced by 750 nA.
11. RTC function current includes LPTMR with OSC enabled with 32.768 kHz crystal at 3.0 V
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode, except for 50 MHz core (FEI mode)
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
• For the ALLON curve, all peripheral clocks are enabled, but peripherals are not in
active operation
• USB Voltage Regulator disabled
• No GPIOs toggled
• Code execution from flash memory with cache enabled
MCF51JF128, Rev. 7, 03/2015
14
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Figure 1. Run mode supply current vs. core frequency
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
15
Nonswitching electrical specifications
Figure 2. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
dBμV
1, 2
—
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
20
VRE2
Radiated emissions voltage, band 2
50–150
19
VRE3
Radiated emissions voltage, band 3
150–500
17
VRE4
Radiated emissions voltage, band 4
500–1000
16
IEC level
0.15–1000
L
VRE_IEC
MCF51JF128, Rev. 7, 03/2015
16
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and
Definitions, and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated
Emissions—TEM Cell and Wideband TEM Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 32 kHz (crystal), fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated
Emissions—TEM Cell and Wideband TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.3 Switching electrical specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
50
MHz
System and core clock when USB in operation
20
—
MHz
Bus clock
—
25
MHz
Mini-FlexBus clock
—
25
MHz
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
FB_CLK
fLPTMR
1
VLPR mode
fSYS
System and core clock
—
2
MHz
fBUS
Bus clock
—
1
MHz
Mini-FlexBus clock
—
1
MHz
—
25
MHz
FB_CLK
fLPTMR
LPTMR
clock2
1
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
17
Nonswitching electrical specifications
1. When the Mini-FlexBus is enabled, its clock frequency is always the same as the bus clock frequency.
2. A maximum frequency of 25 MHz for the LPTMR in VLPR mode is possible when the LPTMR is configured for pulse
counting mode and is driven externally via the LPTMR_ALT1, LPTMR_ALT2, or LPTMR_ALT3 pin.
5.3.1 General Switching Specifications
These general purpose specifications apply to all signals configured for EGPIO, MTIM,
CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,
and full temperature range. The GPIO are set for high drive, no slew rate control, and no
input filter, digital or analog, unless otherwise specified.
Table 9. EGPIO General Control Timing
Symbol
Description
Min.
Max.
Unit
G1
Bus clock from CLK_OUT pin high to GPIO output valid
—
32
ns
G2
Bus clock from CLK_OUT pin high to GPIO output invalid
(output hold)
1
—
ns
G3
GPIO input valid to bus clock high
28
—
ns
G4
Bus clock from CLK_OUT pin high to GPIO input invalid
—
4
ns
GPIO pin interrupt pulse width (digital glitch filter disabled)
1.5
—
Bus
clock
cycles
100
—
ns
50
—
ns
External reset pulse width (digital glitch filter disabled)
100
—
ns
Mode select (MS) hold time after reset deassertion
2
—
Bus
clock
cycles
Synchronous path1
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter enabled)
Asynchronous path2
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled)
Asynchronous path2
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
MCF51JF128, Rev. 7, 03/2015
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Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Bus clock
G1
G2
Data outputs
G3
G4
Data inputs
Figure 3. EGPIO timing diagram
The following general purpose specifications apply to all signals configured for RGPIO,
FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full
temperature range. The GPIO are set for high drive, no slew rate control, and no input
filter, digital or analog, unless otherwise specified.
Table 10. RGPIO General Control Timing
Symbol
Description
Min.
Max.
Unit
R1
CPUCLK from CLK_OUT pin high to GPIO output valid
—
16
ns
R2
CPUCLK from CLK_OUT pin high to GPIO output invalid
(output hold)
1
—
ns
R3
GPIO input valid to bus clock high
17
—
ns
R4
CPUCLK from CLK_OUT pin high to GPIO input invalid
—
2
ns
Bus clock
R1
R2
Data outputs
R3
R4
Data inputs
Figure 4. RGPIO timing diagram
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
19
Thermal specifications
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
115
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
64 LQFP 48 LQFP
44
Laminate
QFN
32 QFN
Unit
Notes
Single-layer RθJA
(1s)
Thermal resistance, junction to
ambient (natural convection)
73
79
108
98
°C/W
1
Four-layer
(2s2p)
Thermal resistance, junction to
ambient (natural convection)
54
55
69
33
°C/W
1
Single-layer RθJMA
(1s)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
61
66
91
81
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
48
48
63
28
°C/W
1
—
RθJB
Thermal resistance, junction to
board
37
34
44
13
°C/W
2
—
RθJC
Thermal resistance, junction to case 20
20
31
2.2
°C/W
3
—
ΨJT
Thermal characterization parameter, 5.0
junction to package top outside
center (natural convection)
4.0
6.0
6.0
°C/W
4
RθJA
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
MCF51JF128, Rev. 7, 03/2015
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug specifications
Table 12. Background debug mode (BDM) timing
Number
Symbol
Description
Min.
Max.
Unit
1
tMSSU
BKGD/MS setup time after issuing background
debug force reset to enter user mode or BDM
500
—
ns
2
tMSH
BKGD/MS hold time after issuing background
debug force reset to enter user mode or BDM1
100
—
µs
1. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after
VDD rises above VLVD.
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
38.214
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
—
± 10
—
%fdco
1
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
Notes
Table continues on the next page...
MCF51JF128, Rev. 7, 03/2015
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21
Clock modules
Table 13. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 4.5
—
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3.3
4
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
48.0
—
100
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
6
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
7
7
Table continues on the next page...
MCF51JF128, Rev. 7, 03/2015
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Freescale Semiconductor, Inc.
Clock modules
Table 13. MCG specifications (continued)
Symbol
Description
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
Min.
Typ.
Max.
Unit
8
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
50
—
ps
PLL accumulated jitter over 1µs (RMS)
8
• fvco = 48 MHz
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Notes
Lock detector detection time
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
6.3.2.1
Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 1 MHz
—
200
—
μA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
—
950
—
μA
Table continues on the next page...
MCF51JF128, Rev. 7, 03/2015
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23
Clock modules
Table 14. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
• 16 MHz
—
1.2
—
mA
• 24 MHz
—
1.5
—
mA
Notes
• 32 MHz
IDDOSC
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 1 MHz
—
300
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
6.6
—
kΩ
—
3.3
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0.6
—
V
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
Table continues on the next page...
MCF51JF128, Rev. 7, 03/2015
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Freescale Semiconductor, Inc.
Clock modules
Table 14. Oscillator DC electrical specifications (continued)
Symbol
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — highfrequency mode (low range)
(MCG_C2[RANGE]=01)
1
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
25
Memories and memory interfaces
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 16. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversblk32k Erase Block high-voltage time for 32 KB
—
52
452
ms
1
thversblk128k Erase Block high-voltage time for 128 KB
—
208
1808
ms
1
Unit
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol
Flash timing specifications — commands
Table 17. Flash command timing specifications
Description
Min.
Typ.
Max.
Read 1s Block execution time
1
trd1blk32k
• 32 KB data flash
—
—
0.5
ms
trd1blk128k
• 128 KB program flash
—
—
1.7
ms
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
Erase Flash Block execution time
2
tersblk32k
• 32 KB data flash
—
55
465
ms
tersblk128k
• 128 KB program flash
—
220
1850
ms
—
14
114
ms
tersscr
Erase Flash Sector execution time
Program Section execution time
2
—
tpgmsec512
• 512 bytes flash
—
4.7
—
ms
tpgmsec1k
• 1 KB flash
—
9.3
—
ms
Table continues on the next page...
MCF51JF128, Rev. 7, 03/2015
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Freescale Semiconductor, Inc.
Memories and memory interfaces
Table 17. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
1
trdonce
Read Once execution time
—
—
25
μs
1
Program Once execution time
—
65
—
μs
—
tersall
Erase All Blocks execution time
—
275
2350
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
Program Partition for EEPROM execution time
tpgmpart32k
• 32 KB FlexNVM
—
—
70
—
ms
Set FlexRAM Function execution time:
—
tsetramff
• Control Code 0xFF
—
50
—
μs
tsetram8k
• 8 KB EEPROM backup
—
0.3
0.5
ms
tsetram32k
• 32 KB EEPROM backup
—
0.7
1.0
ms
260
μs
Byte-write to FlexRAM for EEPROM operation
teewr8bers
Byte-write to erased FlexRAM location execution
time
—
175
Byte-write to FlexRAM execution time:
3
—
teewr8b8k
• 8 KB EEPROM backup
—
340
1700
μs
teewr8b16k
• 16 KB EEPROM backup
—
385
1800
μs
teewr8b32k
• 32 KB EEPROM backup
—
475
2000
μs
260
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
Word-write to FlexRAM execution time:
—
—
teewr16b8k
• 8 KB EEPROM backup
—
340
1700
μs
teewr16b16k
• 16 KB EEPROM backup
—
385
1800
μs
teewr16b32k
• 32 KB EEPROM backup
—
475
2000
μs
540
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
Longword-write to FlexRAM execution time:
—
—
teewr32b8k
• 8 KB EEPROM backup
—
545
1950
μs
teewr32b16k
• 16 KB EEPROM backup
—
630
2050
μs
teewr32b32k
• 32 KB EEPROM backup
—
810
2250
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
27
Memories and memory interfaces
6.4.1.3
Flash high voltage current behaviors
Table 18. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 19. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
2
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
2
tnvmretp100 Data retention after up to 100 cycles
15
100
—
years
2
10 K
50 K
—
cycles
3
nnvmcycp
Cycling endurance
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
2
tnvmretd1k
Data retention after up to 1 K cycles
20
100
—
years
2
tnvmretd100 Data retention after up to 100 cycles
15
100
—
years
2
10 K
50 K
—
cycles
3
nnvmcycd
Cycling endurance
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
2
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
2
tnvmretee1
15
100
—
years
2
35 K
175 K
—
writes
315 K
1.6 M
—
writes
1.27 M
6.4 M
—
writes
10 M
50 M
—
writes
20 M
100 M
—
writes
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree8k
Data retention up to 1% of write endurance
Write endurance
4
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 8192
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology.
3. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
4. Write endurance represents the number of writes to each FlexRAM location at –40 °C ≤Tj ≤ 125 °C influenced by the
cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical
values assume all byte-writes to FlexRAM.
MCF51JF128, Rev. 7, 03/2015
28
Freescale Semiconductor, Inc.
Memories and memory interfaces
6.4.2 EzPort Switching Specifications
All timing is shown with respect to a maximum pin load of 50 pF and input signal
transitions of 3 ns.
Table 20. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
15
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
0.0
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
15
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
0.0
—
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
—
25
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0.0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 5. EzPort Timing Diagram
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
29
Memories and memory interfaces
6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships
can be derived from these values.
Table 21. Flexbus switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
1.71
3.6
V
Frequency of operation
—
25
MHz
FB1
Clock period
40
—
ns
FB2
Address, data, and control output valid
—
20
ns
1
FB3
Address, data, and control output hold
1
—
ns
1
FB4
Data and FB_TA input setup
20
—
ns
2
FB5
Data and FB_TA input hold
10
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS.
2. Specification is valid for all FB_AD[31:0].
Note
The following diagrams refer to signal names that may not be
included on your particular device. Ignore these extraneous
signals.
Also, ignore the AA=0 portions of the diagrams because this
setting is not supported in the Mini-FlexBus.
MCF51JF128, Rev. 7, 03/2015
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Freescale Semiconductor, Inc.
Memories and memory interfaces
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB2
FB_D[X]
Address
FB4
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 6. Mini-FlexBus read timing diagram
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
31
Memories and memory interfaces
FB1
FB_CLK
FB2
FB_A[Y]
FB_D[X]
FB3
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 7. Mini-FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
MCF51JF128, Rev. 7, 03/2015
32
Freescale Semiconductor, Inc.
Analog
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1
12-bit ADC operating conditions
Table 22. 12-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
—
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
—
CADIN
Input capacitance
—
4
5
pF
—
RADIN
Input series
resistance
—
2
5
kΩ
—
RAS
• 8-bit / 10-bit / 12-bit
modes
Analog source
resistance
(external)
12-bit modes
3
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 12-bit mode
1.0
—
18.0
MHz
Crate
ADC conversion
rate
≤ 12-bit modes
No ADC hardware averaging
4
—
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
MCF51JF128, Rev. 7, 03/2015
Freescale Semiconductor, Inc.
33
Analog
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 8. ADC input impedance equivalency diagram
6.6.1.2
12-bit ADC electrical characteristics
Table 23. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
3.0
4.0
7.3
MHz
tADACK =
1/fADACK
• ADLPC = 0, ADHSC = 0
2.4
5.2
6.1
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
•
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