MCF5253VM140J

Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF5253DS Rev. 4, 07/2008 MCF5253 MCF5253 ColdFire® Microprocessor Data Sheet 1 Introduction This document provides an overview of the MCF5253 ColdFire processor and general descriptions of the MCF5253 features and modules. Also provided are electrical specifications, pin assignments, and package diagrams for MCF5253 ColdFire® processor. For functional characteristics, refer to the MCF5253 Reference Manual (MCF5253RM). The MCF5253 is a general purpose system controller with over 125 Dhrystone 2.1 MIPS @ 140 MHz performance. The integrated peripherals and EMAC allow the MCF5253 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can also be remapped as general purpose I/O pins. Package Information MAPBGA–225 Ordering Information: See Table 1 on page 2 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Orderable Part Numbers . . . . . . . . . . . . . . 2 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3 2 Functional Description . . . . . . . . . . . . . . . . . . . 4 2.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . 4 2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 4 3 Signal Description . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical Specifications . . . . . . . . . . . . . . . . . 11 4.1 SDRAM Bus Timing . . . . . . . . . . . . . . . . . 16 4.2 SPDIF Timing . . . . . . . . . . . . . . . . . . . . . . 17 4.3 Serial Audio Interface Timing . . . . . . . . . . 17 4.4 DDATA/PST/PSTCLK Debug Interface . . 17 4.5 BDM and JTAG Timing . . . . . . . . . . . . . . 18 5 Power Consumption . . . . . . . . . . . . . . . . . . . . 19 6 Package Information and Pinout . . . . . . . . . . 19 6.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . 20 6.2 Package Drawing . . . . . . . . . . . . . . . . . . . 26 7 Product Documentation . . . . . . . . . . . . . . . . . 33 7.1 Revision History . . . . . . . . . . . . . . . . . . . . 33 Low power features include flexible PLL (with power-down mode) with dynamic clock switching, a hardwired CD ROM decoder, advanced 0.13 µm CMOS process technology, 1.2 V core power supply, and on-chip 128K-byte SRAM. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008. All rights reserved. Introduction For additional information regarding software drivers and applications, refer to http://www.freescale.com/coldfire. 1.1 Orderable Part Numbers Table 1 lists the orderable part numbers for the MCF5253 processor. Table 1. Orderable Part Numbers Orderable Part Number Maximum Clock Frequency Package Type 140 MHz 225 MAPBGA MCF5253VM140 MCF5253CVM140 Operating Temperature Range Part Status -20 to +70°C Lead free -40 to +85°C MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 2 Freescale Semiconductor Introduction 1.2 Block Diagram Figure 1 illustrates the functional block diagram of the MCF5253 processor. Standard ColdFire Peripheral Blocks Debug Module with JTAG Timer Pins Timer I2C Pins I2 C 8K 64K 5x08 DMA Instruction Cache KRAM1 ColdFire CF2 Core 140 MHz UART Pins UART (3) 5x08 Interrupt 5x08 Arbiter MUX SDRAM SRAM IDE E-bus 64K SDRAM Interface KRAM0 BUFENB1 E-bus “Backdoor” Interface BUFENB2 Translator FlexCAN Pins SmartMedia 2x FlexCAN Controller Clock PLL CRIN/CROUT Pins RTC Pins IDE_DIOR Interrupt Controller SPI Pins Real-Time Clock Audio Interface Pins Audio Interfaces AD IN Pins AD Logic Memory Stick/SD Interface USB 2.0 OTG Controller 16 Kbyte SRAM IDE_IORDY SPI Interface XTAL Oscillator IDE_DIOW FlashMedia Pins USB PHY USB XTAL Oscillator USB Analog USB XTAL Pins ATA Pins ARB DMA ATA Controller Figure 1. MCF5253 Block Diagram MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 3 Functional Description 2 Functional Description 2.1 Version 2 ColdFire Core The Version 2 ColdFire (CF2) core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size. The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then executes the required function. 2.2 Module Inventory Table 2 shows an alphabetical listing of the modules in the processor. Table 2. Digital and Analog Modules Block Mnemonic Block Name Functional Grouping Brief Description ATA Advanced Technology Connectivity Attachment Controller Peripheral The ATA block is an AT attachment host interface. Its main use is to interface with IDE hard disc drives and ATAPI optical disc drives. ADC Battery Level/Keypad Analog/Digital Converter Analog Input The six-channel ADC is based on the Sigma-Delta concept with 12-bit resolution. Both the analog comparator and digital sections are integrated in the MCF5253. AB Audio Bus Audio Interface The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received data on the audio bus and each transmitter takes data from the audio bus for transmission. AIM Audio Interface Audio Interface The audio interface module provides the necessary input and output features to receive and transmit digital audio signals over serial audio interfaces (IIS/EIAJ) and over digital audio interfaces (IEC958). BROM Bootloader Boot ROM The MCF5253 incorporates a ROM Bootloader, which enables booting from UART, I2C, SPI, or IDE devices. FlexCAN Twin Controller Area Network 2.0B Communication Unit Connectivity Peripheral The FlexCan module is a full implementation of the Bosch CAN protocol specification 2.0B, which supports both standard and extended message frames. CSM Chip Select Module Connectivity Peripheral Three programmable chip-select outputs (CS0/CS4, CS1, and CS2) provide signals that enable glueless connection to external memory and peripheral circuits. DMAC Direct Memory Access Controller Module Connectivity Peripheral There are four fully programmable DMA channels for quick data transfer. eMAC enhanced Multiply Accumulate Module Core The integrated eMAC unit provides a common set of DSP operations and enhances the integer multiply instructions in the ColdFire architecture. MBUS Memory Bus Interface Bus Operation The bus interface controller transfers data between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. MMC/SD Multimedia Card/Secure Digital Interface Flash Memory The interface is Sony® Memory Stick®, SecureDigital, and Multi-Media Card Interface card compatible. Note: The Sony Memory Interface does not support Sony MagicGate™. MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 4 Freescale Semiconductor Functional Description Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Brief Description GPIO General Purpose I/O Interface System integration GPIO signals are multiplexed with various other signals. GPT General Timer Module Timer peripheral The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer. IDE Integrated Drive Electronics Connectivity peripheral The IDE hardware consists of bus buffers for address and data and are intended to reduce the load on the bus and prevent SDRAM and Flash accesses from propagating to the IDE bus. INC Instruction Cache Core The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock cycle. I2C Inter IC Communication Module Connectivity peripheral The two-wire I2C bus interfaces, compliant with the Philips I2C bus standard, are bidirectional serial buses that exchange data between devices. SRAM Internal 128-KB SRAM Internal memory The 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and SRAM1 (64K). It provides single clock-cycle access for the ColdFire core. LIN Internal Voltage Regulator Linear regulator An internal 1.2 V regulator is used to supply the CPU and PLL sections of the MCF5253, reducing the number of external components required and allowing operation from a single supply rail, typically 3.3 volts. JTAG Joint Test Action Group Test and debug To help with system diagnostics and manufacturing testing, the MCF5253 includes dedicated user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. QSPI Queued Serial Peripheral Interface Connectivity Interface The QSPI module provides a serial peripheral interface with queued transfer capability. RTC Real-Time Clock Timer Peripheral The RTC is a clock that keeps track of the current time even if the clock is turned off. BDM Background Debug Interface Test and debug A background-debug mode (BDM) interface provides system debug. SDRAMC Synchronous DRAM Memory Controller Peripheral Interface The SDRAM controller provides a glueless interface for one bank of SDRAM, and can address up to 32MB. The controller supports a 16-bit data bus. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMs. SIM System Integration Module System Integration The SIM provides overall control of the internal and external buses and serves as the interface between the ColdFire core and the internal peripherals or external devices. The SIM is responsible for the two interrupt controllers (setting priorities and levels). And it also configures the GPIO ports. PLL System Oscillator and System Phase Lock Loop Clocking The oscillator operates from an external crystal connected across CRIN and CROUT. The circuit can also operate from an external clock connected to CRIN. The on-chip programmable PLL, which generates the processor clock, allows the use of almost any low frequency external clock (5–35 MHz). MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 5 Signal Description Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Brief Description UART Universal Asynchronous Receiver /Transmitter Module Connectivity Peripheral Three UARTs handle asynchronous serial communication. USBOTG USB 2.0 High-Speed On-The-Go Connectivity Peripheral The USB module is used for communication to a PC or communication to slave devices; for example, to download data from a hard disc player to a flash player, and to other devices. 3 Signal Description This chapter describes the MCF5253 input and output signals. The signal descriptions as shown in Table 3 are grouped according to relevant functionality. For additional signal information, see “Chapter 2, Signal Description” in the MCF5253 reference manual. Table 3. MCF5253 Signal Index Signal Name Mnemonic Function Input/ Output Reset State Address A[24:1] A[23]/GPO54 24 address lines—address 23 is multiplexed with GPO54 and address 24 is multiplexed with A20 (SDRAM access only). Out X Read-write control RW Bus write enable—indicates if read or write cycle in progress. Out H Output enable OE Output enable for asynchronous memories connected to chip selects Out negated Data D[31:16] Data bus used to transfer word data In/Out Hi-Z Synchronous row address strobe SDRAS/GPIO59 Row address strobe for external SDRAM Out negated Synchronous column address strobe SDCAS/GPIO39 Column address strobe for external SDRAM Out negated SDRAM write enable SDWE/GPIO38 Write enable for external SDRAM Out negated SDRAM upper byte enable SDUDQM/GPO53 Upper byte enable—indicates during write cycle if high byte is written. Out – SDRAM lower byte enable SDLDQM/GPO52 Lower byte enable—indicates during write cycle if low byte is written. Out – SDRAM chip selects SD_CS0/GPIO60 SDRAM chip select In/Out negated SDRAM clock enable BCLKE/GPIO63 SDRAM clock enable Out – System clock BCLK/GPIO40 SDRAM clock output In/Out – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 6 Freescale Semiconductor Signal Description Table 3. MCF5253 Signal Index (continued) Signal Name Mnemonic Input/ Output Reset State 1 ISA bus read strobe and 1 ISA bus write strobe—allow connection of an independent ISA bus peripheral, such as an IDE slave device. In/Out – In/Out – Function ISA bus read strobe IDE_DIOR/GPIO31 (CS2) ISA bus write strobe IDE_DIOW/GPIO32 (CS2) ISA bus wait signal IDE_IORDY/GPIO33 ISA bus wait line available for both busses In/Out – Chip Selects[2:0] CS0/CS4 CS1/QSPICS3/GPIO28 Chip selects bits 2 through 0— enable peripherals at programmed addresses. CS0 provides boot ROM selection. Out In/Out negated Buffer enable 1 BUFENB1/GPIO29 In/Out – Buffer enable 2 BUFENB2/GPIO30 Two programmable buffer enables—allow seamless steering of external buffers to split data and address bus in sections. In/Out – Transfer acknowledge TA/GPIO12 Transfer Acknowledge signal. In/Out – Wake Up WAKEUP/GPIO21 Wake-up signal input In – Serial Clock Line SCL0/SDATA1_BS1/GPIO41 SCL1/TXD1/GPIO10 Clock signal for Dual I2C module operation In/Out – Serial Data Line SDA0/SDATA3/GPIO42 SDA1/RXD1/GPIO44 Serial data port for second I2C module operation In/Out – Receive Data SDA1/RXD1/GPIO44 RXD0/GPIO46 EF/RXD2/GPIO6 Receive serial data input for UART In – Transmit Data SCL1/TXD1/GPIO10 TXD0/GPIO45 XTRIM/TXD2/GPIO0 Transmit serial data output for UART Out – Request-To-Send DDATA3/RTS0/GPIO4 DDATA1/RTS1/SDATA2_BS2/GPIO2 Signals sent from UART0/1 that it is ready to receive data Out – Clear-To-Send Signals sent to UART0/1 that data DDATA2/CTS0/GPIO3 DDATA0/CTS1/SDATA0_SDIO1/GPIO1 can be transmitted to peripheral In – Timer Output SDATAO1/TOUT0/GPIO18 Capability of output waveform or pulse generation Out – IEC958 inputs EBUIN1/GPIO36 EBUIN2/SCLKOUT/GPIO13 EBUIN3/CMD_SDIO2/GPIO14 QSPICS0/EBUIN4/GPIO15 Audio interfaces to IEC958 inputs In – IEC958 outputs EBUOUT1/GPIO37 QSPICS1/EBUOUT2/GPIO16 Audio interfaces to IEC958 outputs Out – Serial data in SDATAI1/GPIO17 SDATAI3/GPIO8 Audio interfaces to serial data inputs In – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 7 Signal Description Table 3. MCF5253 Signal Index (continued) Signal Name Mnemonic Function Input/ Output Reset State Serial data out SDATAO1/TOUT0/GPIO18 SDATAO2/GPIO34 Audio interfaces to serial data outputs In/Out Out – Word clock LRCK1/GPIO19 LRCK2/GPIO23 LRCK3/AUDIOCLOCK/GPIO43 Audio interfaces to serial word clocks In/Out – Bit clock SCLK1/GPIO20 SCLK2/GPIO22 SCLK3/GPIO35 Audio interfaces to serial bit clocks In/Out – Serial input EF/RXD2/GPIO6 Error flag serial in In/Out – Serial input CFLG/GPIO5 C-flag serial in In/Out – Subcode clock RCK/QSPIDIN/QSPIDOUT/ GPIO26 Audio interfaces to subcode clock In/Out – Subcode sync QSPIDOUT/SFSY/GPIO27 Audio interfaces to subcode sync In/Out – Subcode data QSPICLK/SUBR/GPIO25 Audio interfaces to subcode data In/Out – Clock frequency trim XTRIM/TXD2/GPIO0 Clock trim control Out – Audio clocks out MCLK1/GPIO11 QSPICS2/MCLK2/GPIO24 DAC output clocks Out – Audio clock in LRCK3/AUDIOCLOCK/GPIO43 Optional audio clock input MemoryStick/ SecureDigital interface EBUIN3/CMD_SDIO2/GPIO14 Secure Digital command lane— MemoryStick interface 2 data I/O In/Out – EBUIN2/SCLKOUT/GPIO13 Clock out for both MemoryStick interfaces and for Secure Digital In/Out – DDATA0/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0— MemoryStick interface 1 data I/O In/Out – SCL0/SDATA1_BS1/GPIO41 SecureDigital serial data bit 1— MemoryStick interface 1 strobe In/Out – DDATA1/RTS1/SDATA2_BS2/GPIO2 SecureDigital serial data bit 2— MemoryStick interface 2 strobe Reset output signal In/Out – SDA0/SDATA3/GPIO42 SecureDigital serial data bit 3 In/Out – – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 8 Freescale Semiconductor Signal Description Table 3. MCF5253 Signal Index (continued) Signal Name Input/ Output Reset State ATA write strobe signal Out – ATA read strobe signal Out – Mnemonic AT attachment interface ATA_DIOW (IDE interface) ATA_DIOR Function ATA_IORDY ATA I/O ready input In – ATA_DMARQ ATA DMA request In – ATA_DMACK ATA DMA acknowledge Out – ATA_INTRQ ATA interrupt request In – ATA_CS0 ATA chip select 0 Out – ATA_CS1 ATA chip select 1 Out – ATA_A[2:0] 3-bit ATA address bus Out – ATA_D[15:0] 16-bit ATA data bus In/Out – CAN0_TX CAN 0 transmit Out – CAN0_RX CAN 0 receive In – CAN1_TX CAN 1 transmit Out – CAN1_RX CAN 1 receive In – USBVBUS USB Vbus input In – USBID USB ID input In – USBRES USB current programming resistor pin Analog – USBDN USB DM signalling line In/Out – USBDP USB DP signalling line In/Out – USB oscillator USB_CRIN USB_CROUT Connections for USB oscillator crystal (24 MHz) In Out – RTC oscillator RTC_CRIN RTCCROUT Connections for real-time clock crystal (32.768 kHz) In Out – AD IN ADIN0/GPI52 ADIN1/GPI53 ADIN2/GPI54 ADIN3/GPI55 ADIN4/GPI56 ADIN5/GPI57 Analog-to-Digital Converter input signals In – AD OUT ADREF ADOUT/SCLK4/GPIO58 Analog-to-Digital Converter output signal—connects to ADREF via integrator network. In/Out – QSPI clock QSPICLK/SUBR/GPIO25 QSPI clock signal In/Out – QSPI data in RCK/QSPIDIN/QSPIDOUT/GPIO26 QSPI data input In/Out – CAN interface USB PHY interface MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 9 Signal Description Table 3. MCF5253 Signal Index (continued) Signal Name Mnemonic Function Input/ Output Reset State QSPI data out RCK/QSPIDIN/QSPIDOUT/GPIO26 QSPIDOUT/SFSY/GPIO27 QSPI data out In/Out – QSPI chip selects QSPICS0/EBUIN4/GPIO15 QSPICS1/EBUOUT2/GPIO16 QSPICS2/MCLK2/GPIO24 CS1/QSPICS3/GPIO28 QSPI chip selects In/Out – System oscillator in CRIN System input In – System oscillator out CROUT System output Out – Reset In RSTI Processor reset input In – Freescale Test Mode TEST[2:0] TEST pins. In – Linear regulator output LINOUT Output of 1.2 V to supply core Out – Linear regulator input LININ Input, typically I/O supply (3.3V) In – Linear regulator ground LINGND – High Impedance HI_Z Assertion tri-states output signal pins In Debug Data DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Display of captured processor data and break-point statuses DDATA1/RTS1/SDATA2_BS2/GPIO2 DDATA2/CTS0/GPIO3 DDATA3/RTS0/GPIO4 In/Out Hi-Z Processor Status PST0/GPIO50 PST1/GPIO49 PST2/INTMON2/GPIO48 PST3/INTMON1/GPIO47 Indication of internal processor status. In/Out Hi-Z Processor clock PSTCLK/GPIO51 Processor clock output Out – Test Clock TCK Clock signal for IEEE 1149.1A JTAG In – Test Reset/ Development Serial Clock DSCLK/TRST Multiplexed signal that is asynchronous reset for JTAG controller. Also, clock input for debug module. In – Test Mode Select/Break TMS/BKPT Point Multiplexed signal that is test mode select in JTAG mode and a hardware break-point in debug mode In – Test Data Input/ Development Serial Input TDI/DSI Multiplexed serial input for the JTAG or background debug module. In – Test Data Output/Development Serial Output TDO/DSO Multiplexed serial output for the JTAG or background debug module Out – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 10 Freescale Semiconductor Electrical Specifications 4 Electrical Specifications Table 4 through Table 10 provide the electrical characteristics for the MCF5253 processor. The remaining figures and tables in this section provide the timing diagrams and the timing parameters for the MCF5253 processor. Table 4 provides the maximum rating parameters for the MCF5253 processor. Table 4. Maximum Ratings Rating Symbol Value Units Supply Core Voltage Vcc -0.5 to +2.5 V Maximum Core Operating Voltage Vcc +1.32 V Minimum Core Operating Voltage Vcc +1.08 V Supply I/O Voltage Vcc -0.5 to +4.6 V Maximum I/O Operating Voltage Vcc +3.6 V Minimum I/O Operating Voltage Vcc +3.0 V Input Voltage Vin –0.5 to +6.0 V Storage Temperature Range Tstg –65 to +150 oC Table 5 provides the recommended operating temperatures for the MCF5253 processor. Table 5. Operating Temperature Characteristic Symbol Value Units Maximum Operating Ambient Temperature TAmax +701 oC Minimum Operating Ambient Temperature TAmin -20 oC 1 This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature does not exceed 86.5o C. Table 6 provides the recommended operating supply voltages for the MCF5253 processor. Table 6. Recommended Operating Supply Voltages Pin Name Min Typ Max Unit COREVDD 1.08 1.2 1.32 V PADVDD 3.0 3.3 3.6 V ADVDD 3.0 3.3 3.6 V ADGND – GND – V OSCPADVDD 3.0 3.3 3.6 V OSCPADGND – GND – V USBVDD – 3.3 – V USBVDDP – 1.2 – V MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 11 Electrical Specifications Table 6. Recommended Operating Supply Voltages (continued) Pin Name Min Typ Max Unit USBGND – GND – V RTCVDDA 3.0 – 4.2 V RTCVSSA – GND – V PLLCOREVDD 1.08 1.2 1.32 V PLLCOREGND – GND – V LININ 3.0 3.3 3.6 V GND – GND – V Table 7 provides the operating parameters for the linear regulator. Table 7. Linear Regulator Operating Parameters Characteristic Symbol Min Typ Max Units Input Voltage (LININ) Vin 3.0 3.3 3.6 V Output Voltage (LINOUT) Vout 1.08 1.2 1.32 V Output Current Iout – 100 150 mA Power Dissipation Pd – – 500 mW Load Regulation 10% Iout ≥ 90% Iout – – 50 60 mV Power Supply Rejection PSRR – 40 – dB NOTE A pmos regulator is used as a current source in this linear regulator, so a 10 µF capacitor (ESR 0... 5 Ohm) is needed on the output pin (LINOUT) to integrate the current. Typically, this requires the use of a tantalum type capacitor. Table 8 provides the measured parameters related to temperature for the linear regulator. Table 8. Linear Regulator—Measured Parameters Related to Temperature Characteristic Symbol Input Voltage (LININ) Vin Min 2.97 1.16: 25 Max Units 3.3 3.63 V oC: V oC: 1.19 -40 1.22 Output Voltage (LINOUT) 100 mA load Vout Current Consumption Icc -40 oC: 44 25 oC: 56 125 oC: 68 mA Power Dissipation Pd -40 oC: 131 25 oC: 185 125 oC: 247 mW – oC: oC: Load Regulation 10% Iout ≥ 90% Iout 125 oC: Typ -40 46 25 57 125 oC: 70 mV MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 12 Freescale Semiconductor Electrical Specifications Voutput vs Vinput 1.23 1.22 1.21 1.2 1.19 1.18 1.17 1.16 1.15 1.14 1.13 2.97 3.3 3.63 Input Voltage Figure 2. Linear Regulator—Voutput vs Vinput Table 9 provides the operating parameters for the ADC DC electrical characteristics. Table 9. Operating Parameters for ADC DC Electrical Characteristics Characteristic Symbol Min Typ Max Units Operation Voltage Range for ADC ADVDD 3 – 3.6 V Common Mode Rejection CMR 0 – ADVDD–1.1 v Reference Voltage (external) ADREF 0 – ADVDD–1.1 v Input offset voltage Voffset – 10 – mV Input Hysteresis (ADINx = ADVDD/2) Vhyst 0.73 0.78 0.85 mV ADC Input Linear Operating Range ADINx 0 – ADVDD–1.1 V AD Convertor Error 2 LSB Note: Software and hardware sampling time is dependent on the external RC network used and the internal CPU Frequency and AD Converter clock divider.See Section 12.4.1 in the MCF5253 Reference Manual for more information. Table 10 provides the DC electrical specifications for the digital pins. Table 10. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc) Characteristic Symbol Min Max Units Operation Voltage Range for I/O Vcc 3.0 3.6 V Input High Voltage VIH 2 5.5 V Input Low Voltage VIL -0.3 0.8 V Reset Threshold Voltage - High RtH 2.0 – V Reset Threshold Voltage - Low TtL – 0.8 V Reset Input Rise Time nS 10 – – Reset Input Fall Time nS 10 – – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 13 Electrical Specifications Table 10. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc) (continued) Characteristic Symbol Min Max Units Iin – ±1 μA Hi-Impedance (Three-State) Leakage Current @ 0.0 V/3.3 V During Normal Operation ITSI – ±1 μA Output High Voltage IOH = 11.9 mA1, 6.3 mA2,3.1 mA3 VOH 2.4 – V Output Low Voltage IOL = 7.1m A1, 3.5 mA2, 1.8 mA3 VOL – 0.4 V Schmitt Trigger Low to High Threshold Point4 VT+ 1.67 1.79 V 4 VT- 1.01 1.15 V Load Capacitance: D[31:16], SCLK[4:1], SCLKOUT, EBUOUT[2:1], LRCK[3:1], SDATAO[2:1], CFLG, EF, IDE_DIOR, IDE_DIOW, IDE_IORDY, MCLK1, MCLK2 CL – 50 pF Load Capacitance: A[24:9], ATA_CS0, ATA_CS1, ATA_A[2:0], ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_D[15:0], SDATAI[3,1] CL 15 40 pF Load Capacitance: A[8:1], ADOUT, ATA_RST BCLK, BCLKE, SDCAS, SDRAS, SDLDQM, SDCS0, SDUDQM, SDWE, BUFENB[2:1], CAN0_TX, CAN1_TX, EBUIN1, RXD[2:0] CL – 30 pF Load Capacitance: SDA0, SDA1, SCL0, SCL1, CMD_SDIO2, SDATA2_BS2, SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1, OE, RW, TA, TXD[2:0], XTRIM, TDO/DSO, RCK, SFSY, SUBR, SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0], QSPICLK, GPIO[6:5] CL – 20 pF Load Capacitance: DDATA[3:0], PST[3:0], PSTCLK CL – 15 pF Capacitance5, Vin = 0 V, f = 1 MHz CIN – 6 pF Input Leakage Current @ 0.0 V/3.3 V During Normal Operation Schmitt Trigger High to Low Threshold Point 1 8.0 mA: SCL0, SDA0, SCL1, SDA1, PST[3:0], DDATA[3:0], TDSO, RW, ATA_RST, MCLK1, QSPICS2_MCLK2 4.0 mA: BUFENB1, BUFENB2, EBUOUT1, SCLKOUT, CMDSDIO, IDE_DIOR, IDE_DIOW, TOUT0, RTS[1:0], TXD[1:0], SCLK[4:1], LRCK[4:1], SDATAO1, SDATAO2, QSPICLK, QSPICS0, QSPICS1_EBUOUT2, QSPICS3, QSPIDOUT, RCK, XTRIM, A[8:1], ATA_CS0, ATA_CS1, ATA_A[2:0] 3 2.0 mA: TMS/BKPT, DSI/TDI, TRST/DSCLK 4 SCLK[4:1], SCL0, SCL1, SDA0, SDA1, ATA_DMARQ, ATA_INTRQ, ATA_IORDY 5 Capacitance C is periodically sampled rather than 100% tested. IN 2 MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 14 Freescale Semiconductor Electrical Specifications Figure 3 and Table 11 provide the clock timing diagram and timing parameters. CRIN C5 PSTCLK C6 C6 C7 BCLK C8 C8 Figure 3. Clock Timing Definition NOTE Signals shown in Figure 3 are in relation to the SYSCLK clock. No relationship between signals is implied or intended. Table 11 shows the clock timing parameters. Table 11. Clock Timing Parameters 140 MHz CPU ID Characteristic Units Min Max – CRIN Frequency with external oscillator 5.00 33.86 MHz – CRIN Frequency with internal oscillator 5 16.94 MHz C5 PSTCLK cycle time 7 – ns C6 PSTCLK duty cycle 40 60 % C7 BCLK cycle time 14.0 – ns C8 BCLK duty cycle 35 65 % MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 15 Electrical Specifications Table 12 shows the CRIN Crystal suggested parameters. Table 12. CRIN Crystal Suggested Parameters Parameter Min Typ Max Unit Frequency 5 – 16.94 MHz Frequency Tolerance – – ±50 ppm Frequency Stability Over Operating Temperature Range – – ±50 ppm ESR – 40 – Ω Shunt Capacitance – 7 – pF Load Capacitance – 18 – pF 4.1 SDRAM Bus Timing The SDRAM bus is a synchronous bus. Propagation delays, set-up times and hold times with respect to the SDRAM clock BCLK are shown in Figure 4 and the parameters provided in Table 13. When BCLK clock is not active, SDRAM interface is not valid and the external bus cannot be used. BCLK D1 data (write) D2 BCLKE, SDXDQM, SDWE, SDCS0, SDRAS, SDCAS D3 A[24:9] D4 data (read) D5 Figure 4. SDRAM Bus Timing Diagram MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 16 Freescale Semiconductor Electrical Specifications Table 13. SDRAM Bus Timing Parameters Timing to 50% Points Maximum ID 4.2 Characteristic Units 30 pF Load 40 pF Load 50 pF Load D1 Propagation delay BCLK rising to data valid 7.88 8.8 9.6 ns D2 Propagation delay BCLK rising to BCLKE, SDLDQM, SDUDQM, SDWE, SDCS0, SDRAS, SDCAS valid 8.7 – – ns D3 Propagation delay BCLK rising to A[24:9] valid 8.3 9.2 – ns D4 Set-up time data valid to BCLK rising 0 0 0 ns D5 Hold time BCLK rising to data valid 0.7 0.7 0.7 ns SPDIF Timing The Sony/Philips Digital Interface (SPDIF) timing parameters are provided in Table 14. SPDIF timing is totally asynchronous, therefore there is no need for relationship with the clock. Table 14 shows the differences between high-low and low-high propagation delay which is called the skew. Table 14. SPDIF Propagation Skew and Transition Parameters Pin Load Prop Delay Maximum Skew1 Maximum Transition2 Rise Maximum Transition Fall Maximum Units – – 0.7 – – ns EBUOUT1, EBUOUT2 output 40 pF – 1.5 24.2 31.3 ns EBUOUT1, EBUOUT2 output 20 pF – 1.5 13.6 18.0 ns Characteristic EBUIN1, EBUIN2, EBUIN3, EBUIN4: asynchronous inputs, no specs apply 1 2 Skew value does not include the skew introduced by different rise and fall times. Transition times between 10% Vdd and 90% Vdd. 4.3 Serial Audio Interface Timing The Serial Audio Interface fully complies with the Industry standard Philips IIS (InterIC Serial Audio Bus) timings. 4.4 DDATA/PST/PSTCLK Debug Interface Table 15 provides the timing parameters. Table 15. DDATA/PST/PSTCLK Debug Interface Timing Parameters Characteristic Pin Load Min Max Units PSTCLK clock rise edge to DDATA/PSTDATA1 invalid 15 pF –1.0 — ns PSTCLK clock rise edge to DDATA/PSTDATA2 valid 15 pF — 4.0 ns MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 17 Electrical Specifications 1 Note that output data may go invalid before rising edge of the clock. To clock data in reliably, you need to sample data, for example, 2 ns before rising edge of clock. 2 Timing figure given takes 50% margin for noise and uncertainty on pin capacitance. Simulated clock-to-data, not taking noise effects into account is 2.7 ns. 4.5 BDM and JTAG Timing Table 16 provides the BDM timing parameters. Table 16. BDM Interface Timing Parameters Characteristic Min Max Units Clock period for DSCLK clock — 5T1 ns Set-up time DSI, BKPT, to DSCLK rising edge 4.0 — ns Hold time DSI, BKPT to DSCLK rising edge — T+ 4.0 ns Propagation delay DSCLK rising edge to TDO/DSO change 3T 4T + 32 ns 1 T denotes the CPU clock period. E.g. if the CPU is running at 100 MHz, T = 10 ns Figure 5 provides the JTAG timing diagram and Table 17 provides the JTAG timing parameters. J1 J3A TCK J2A J3B J2B J4 J5 J6 J7 TDI, TMS Boundary Scan Data Input J1 TRST J9 J10 J11 J12 TDO Boundary Scan Data Output Figure 5. JTAG Timing Diagram MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 18 Freescale Semiconductor Power Consumption Table 17. JTAG Timing Parameters ID 5 Characteristic Min Max Units 0 10 MHz – TCK Frequency of Operation J1 TCK Cycle Time 100 — ns J2A TCK Clock Pulse High Width 25 — ns J2B TCK Clock Pulse Low Width 25 — ns J3A TCK Fall Time (VIH=2.4 V to VIL=0.5 V) — 5 ns J3B TCK Rise Time (VIL=0.5 v to VIH=2.4 V) — 5 ns J4 TDI, TMS to TCK rising (Input Setup) 8 — ns J5 TCK rising to TDI, TMS Invalid (Hold) 10 — ns J6 Boundary Scan Data Valid to TCK (Setup) 1 — ns J7 TCK to Boundary Scan Data Invalid to rising edge (Hold) 10 — ns J8 TRST Pulse Width (asynchronous to clock edges) 12 — ns J9 TCK falling to TDO Valid (signal from driven or three-state) — 15 ns J10 TCK falling to TDO High Impedance 2 15 ns J11 TCK falling to Boundary Scan Data Valid (signal from driven or three-state) — 15 ns J12 TCK falling to Boundary Scan. Data High Impedance 1 15 ns Power Consumption Table 18 shows maximum power consumption for the MCF5253 device. Typicals will be supplied at a later time. Table 18. Maximum Power Consumption Supply Maximum Current 1.2 V Core 150 mA 3.3 V I/O (with core supplied separately) 150 mA1 3.3 V I/O (with core supplied via internal 1.2 V regulator which is fed from the 3.3 V supply) 400 mA 1 6 This does not include the current required for any externally connected 3.3V device (e.g., flash, SDRAM, and other I/O devices). Package Information and Pinout This section includes the pin assignment information, contact connection diagram, and the mechanical package drawing. MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 19 Package Information and Pinout The MCF5253 device is available in the following package: • 225 MAPBGA 13 x 13 mm 0.8 mm pitch package as shown in Figure 6. 6.1 Pin Assignment Table 19 defines all the settings of each pad. See Figure 7 for the ball map of pin locations and Table 21 for the device pin list, sorted by signal identification. Table 19. 225 MAPBGA Pin Assignment Name Drive Type/ Load 1st Strength (pF) Function 2nd Function Pinconfig Register Bit GP Pin Reset Notes Address Bus 30 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – O / 8 mA 30 A20 A24 31 A21 O / 8 mA 30 A22 O / 8 mA 30 – – A23/GPO54 O / 8 mA 30 A23 – – – – – – D16 IO / 8 mA 40 D17 IO / 8 mA 40 D18 IO / 8 mA 40 D19 IO / 8 mA 40 D20 IO / 8 mA 40 D21 IO / 8 mA 40 D22 IO / 8 mA 40 D23 IO / 8 mA 40 D24 IO / 8 mA 40 D25 IO / 8 mA 40 D26 IO / 8 mA 40 – – – – – – – – – – – – – – – – – – – – – – A1 O / 2 mA 30 A2 O / 2 mA 30 A3 O / 2 mA 30 A4 O / 2 mA 30 A5 O / 2 mA 30 A6 O / 2 mA 30 A7 O / 2 mA 30 A8 O / 2 mA 30 A9 O / 8 mA 30 A10 O / 8 mA 30 A11 O / 8 mA 30 A12 O / 8 mA 30 A13 O / 8 mA 30 A14 O / 8 mA 30 A15 O / 8 mA 30 A16 O / 8 mA 30 A17 O / 8 mA 30 A18 O / 8 mA 30 A19 O / 8 mA A20/A24 – – – – – – – – – – – – – – – – – – – – X H X H X H X H X G X G X G X H X H X F X G X F – – – – – – – – – – – – – – – – – – – 3 2 1 5 1 3 2 4 6 2 5 3 X F X E X G X E 1 1 4 2 X F X E X F X F – – X D X D O54 X D – – – – – – – – – – – HI_Z C HI_Z E HI_Z E HI_Z B HI_Z C HI_Z D HI_Z C HI_Z B HI_Z A HI_Z B HI_Z A 4 3 5 6 Audio Clock Select: 1-LRCK3 pin; 0-CRIN pin – – 3 1 2 Boot Mode Select:1-Memory connected to CS0; 0-Internal boot rom Data Bus – – – – – – – – – – – 1 4 5 1 2 4 3 2 2 3 3 – – – – – – – – – – – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 20 Freescale Semiconductor Package Information and Pinout Table 19. 225 MAPBGA Pin Assignment (continued) Name Drive Type/ Load 1st Strength (pF) Function – – – – – 2nd Function Pinconfig Register Bit GP Pin – – – – – – – – – – – – – – – HI_Z C HI_Z B HI_Z D HI_Z A HI_Z C – – – – – – – – – – Negated R IO12 IO33 – – – – – – – Negated D27 IO / 8 mA 40 D28 IO / 8 mA 40 D29 IO / 8 mA 40 D30 IO / 8 mA 40 D31 IO / 8 mA 40 OE O / 4 mA 30 RW O / 4 mA 30 – – TA/GPIO12 IO / 2 mA 30 TA BUFENB1/GPIO29 IO / 2 mA 30 BUFENB1 BUFENB2/GPIO30 IO / 2 mA 30 BUFENB2 IDE_DIOR/GPIO31 IO / 2 mA 30 IDE_DIOR IDE_DIOW/GPIO32 IO / 2 mA 30 IDE_DIOW IDE_IORDY/GPIO33 IO / 2 mA 30 IDE_IORDY CS0/CS4 O / 4 mA 30 CS0 CS4 – CS1/QSPICS3/ GPIO28 IO / 2 mA 30 CS1 QSPICS3 25 BCLK/GPIO40 IO / 8 mA 15 BCLK BCLKE/GPIO63 IO / 8 mA 20 BCLKE SDLDQM/GPO52 O / 8 mA 20 SDLDQM SDUDQM/GPO53 O / 8 mA 20 SDUDQM SDWE/GPIO38 IO / 8 mA 20 SDWE SDCS0/GPIO60 IO / 8 mA 20 SDCS0 SDRAS/GPIO59 IO / 8 mA 20 SDRAS SDCAS/GPIO39 IO / 8 mA 20 SDCAS ATA_A0 O / 2 mA 40 ATA_A1 O / 2 mA 40 ATA_A2 O / 2 mA 40 ATA_D0 IO / 8 mA 40 ATA_D1 IO / 8 mA 40 ATA_D2 IO / 8 mA 40 ATA_D3 IO / 8 mA 40 ATA_D4 IO / 8 mA 40 ATA_D5 IO / 8 mA 40 ATA_D6 IO / 8 mA 40 ATA_D7 IO / 8 mA 40 ATA_D8 IO / 8 mA 40 ATA_D9 IO / 8 mA 40 ATA_D10 IO / 8 mA 40 ATA_D11 IO / 8 mA 40 ATA_D12 IO / 8 mA 40 ATA_D13 IO / 8 mA 40 ATA_D14 IO / 8 mA 40 – – – – – – – – – – – – – – – – – – Reset Notes – – – – – 4 4 5 4 5 Bus Control – – – – – – – – IO29 IO30 IO31 IO32 H – – – – – 3 J 4 N 5 P 5 K 6 M 5 P 4 Controlled by CS2 registers Controlled by CS2 registers – R 4 Chip Selects IO28 Negated J 3 Boot Mode Select:1-CS0; 0-CS4 M 7 – SDRAM Controller – – – – – – – – – – – – – – – – IO40 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – IO63 O52 O53 – – – – B 5 E 6 C 6 A 5 IO38 Negated C IO60 Negated B 7 6 IO59 Negated A IO39 Negated D 6 6 – – – – – – – – ATA Interface – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – A 8 B 7 B 8 B 9 A 9 F 8 F 9 B 1 0 C 1 0 A 1 0 D 1 0 D 1 1 B 1 1 C 1 1 A 1 1 A 1 2 E 1 1 B 1 2 – – – – – – – – – – – – – – – – – – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 21 Package Information and Pinout Table 19. 225 MAPBGA Pin Assignment (continued) Name Drive Type/ Load 1st Strength (pF) Function 2nd Function Pinconfig Register Bit GP Pin Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Notes ATA_D15 IO / 8 mA 40 ATA_CS0 O / 2 mA 40 ATA_CS1 O / 2 mA 40 ATA_DIOR O / 8 mA 40 ATA_DIOW O / 8 mA 40 ATA_IORDY I ATA_INTRQ I ATA_DMARQ I – – – ATA_DMACK O / 8 mA 40 ATA_RST O / 2 mA 40 – – – – – – – – – – CRIN CROUT – – RTC_CRIN A – – – – – – – – – – – – – – – – – – RTCCROUT A – – – – – – USB_CRIN A USB_CROUT A – – – – – – – – – – XTRIM/TXD2/GPIO0 IO / 2 mA 30 XTRIM TXD2 0 IO0 – – – TDO/DSO O / 4 mA 30 TDI/DSI I TMS/BKPT I TCK I TRST/DSCLK I HI_Z I – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – PSTCLK/GPIO51 IO / 8 mA 30 PSTCLK – IO / 4 mA 30 PST0 IO50 HI_Z G PST1/GPIO49 IO / 4 mA 30 PST1 – – – IO51 PST0/GPIO50 – – – IO49 HI_Z G PST2/INTMON2/ GPIO48 IO / 4 mA 30 PST2 INTMON2 17 IO48 HI_Z H PST3/INTMON1/ GPIO47 IO / 4 mA 30 PST3 INTMON1 18 IO47 HI_Z H DDATA0/CTS1/ SDATA0_SDIO1/GPIO1 IO / 4 mA 30 DDATA0 CTS1/SDATA 0_SDIO1 14,13 IO1 HI_Z K DDATA1/RTS1/ SDATA2_BS2/GPIO2 IO / 4 mA 30 DDATA1 RTS1/SDATA 2_BS2 24,23 IO2 HI_Z R DDATA2/CTS0/GPIO3 IO / 4 mA 30 DDATA2 CTS0 22 IO3 HI_Z 1 DDATA3/RTS0/GPIO4 IO / 4 mA 30 DDATA3 RTS0 21 IO4 HI_Z 1 TEST0 I TEST1 I – – – – – – – – – – – – TEST2 I – – – – – – RSTI I – – – – – – – – – – – – – – – D 1 2 C 9 D 9 B 1 5 A 1 3 D 7 D 8 A 7 C 1 2 C 8 Clock Generation M 3 N 2 J 1 K 2 L 1 4 L 1 5 R 6 Main Processor Clock Input Main Processor Clock Output Real Time Clock (32.768 kHz) Input Real Time Clock (32.768 kHz) Output USB Clock (24 MHz) Input USB Clock (24 MHz) Output Interrupt Capable Input JTAG/BDM/Test G 1 3 F 1 5 F 1 2 See TEST0 Description See TEST0 Description See TEST0 Description – F 1 3 F 1 4 B 1 3 See TEST0 Description For Normal Operation Tie This Pin High – – – – G 1 4 1 5 1 2 1 4 – 1 3 1 0 1 1 J 4 J 2 F 1 1 G 1 0 H 1 0 Interrupt Capable Input Interrupt Capable Input Interrupt Capable Input Interrupt Capable Input BDM/JTAG Select: 1-BDM; 0-JTAG For normal operation, tie this pin low. For normal operation, tie this pin low. Reset/Wake-up – E 1 5 – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 22 Freescale Semiconductor Package Information and Pinout Table 19. 225 MAPBGA Pin Assignment (continued) Name Drive Type/ Load 1st Strength (pF) Function 2nd Function Pinconfig Register Bit GP Pin Reset – IO21 – – – – – – – – – – – – – – – – – – – – – – – – WAKEUP/GPIO21 IO / 2 mA 30 WAKEUP – USBDN A USBDP A USBID I USBVBUS A USBRES A TESTOUT1 O NC – – – – – – – – – – – – – – – – – – – – – – Notes – R 5 USB – – – – – – – N 1 5 M 1 5 M 1 1 N 1 4 M 1 4 P 1 3 R 1 4 Audio Interface SDATAI1/GPIO17 IO / 2 mA 30 SDATAI1 – – IO17 SDATAO1/TOUT0/ GPIO18 IO / 2 mA 30 SDATAO1 TOUT0 8 IO18 SCLK1/GPIO20 IO / 2 mA 30 SCLK1 IO / 2 mA 30 LRCK1 SDATAO2/GPIO34 IO / 2 mA 30 SDATAO2 SCLK2/GPIO22 IO / 2 mA 30 SCLK2 LRCK2/GPIO23 IO / 2 mA 30 LRCK2 SDATAI3/GPIO8 IO / 2 mA 30 SDATAI3 SCLK3/GPIO35 IO / 2 mA 30 SCLK3 LRCK3/AUDIOCLK/ GPIO43 IO / 2 mA 30 LRCK3 AUDIOCLK – – – – – – – – IO20 LRCK1/GPIO19 – – – – – – – EBUIN1/GPIO36 IO / 2 mA 30 EBUIN1 – – IO36 EBUIN2/SCLKOUT/ GPIO13 IO / 2 mA 30 EBUIN2 SCLKOUT 16 IO13 – – EBUIN3/ CMD_SDIO2/GPIO14 IO / 2 mA 30 EBUIN3 CMDSDIO2 15 IO14 – QSPICS0/EBUIN4/ GPIO15 IO / 2 mA 30 QSPICS0 EBUIN4 30 IO15 – EBUOUT1/GPIO37 IO / 2 mA 30 EBUOUT1 – – IO37 QSPICS1/ EBUOUT2/GPIO16 IO / 2 mA 30 QSPICS1 EBUOUT2 29 IO16 – – CFLG/GPIO5 IO / 2 mA 30 CFLG – IO5 EF/RXD2/GPIO6 IO / 2 mA 30 EF RXD2 MCLK1/GPIO11 IO / 4 mA 30 MCLK1 – – – – IO11 QSPICS2/MCLK2/ GPIO24 IO / 4 mA 30 QSPICS2 MCLK2 28 IO24 ADIN0/GPI52 A ADIN0 ADIN1/GPI53 A ADIN2/GPI54 A ADIN3/GPI55 A ADIN4/GPI56 A ADIN5/GPI57 A ADREF A – – – – – – – ADOUT/SCLK4/ GPIO58 IO / 2 mA 30 IO19 IO34 IO22 IO23 IO8 IO35 IO43 IO6 – – – – – – – – – – – – – – N 9 R 8 – – – – – – – K 8 P 8 D 1 5 E 1 3 E 1 4 N 1 0 R 1 0 M 1 0 See A20/A24 Description – – N 6 M 6 – K 7 – R 7 – – P 6 N 8 M 9 R 9 Interrupt Capable Input Interrupt Capable Input D 1 4 P 9 – – Analog-to-Digital Converter – – – – – – – I52 – – – – – – – – ADOUT SCLK4 9 IO58 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 I53 I54 I55 I56 I57 – – – – – – – – – K 3 L 1 L 2 L 3 M 1 J 6 M 2 J 5 – – – – – – – – MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 23 Package Information and Pinout Table 19. 225 MAPBGA Pin Assignment (continued) Name Drive Type/ Load 1st Strength (pF) Function 2nd Function Pinconfig Register Bit GP Pin Reset – – – – – – – – – – – – Notes FlexCAN – – – – – – – – – IO / 2 mA 30 QSPICLK SUBR 27 IO25 – RCK/QSPIDIN/ QSPIDOUT/GPIO26 IO / 2 mA 30 RCK QSPIDIN/ QSPIDOUT 26 IO26 – QSPIDOUT/SFSY/ GPIO27 IO / 2 mA 30 QSPIDOUT SFSY 10 IO27 – CAN0_TX O / 8 mA 30 CAN0_RX I – CAN1_TX O / 8 mA 30 CAN1_RX I QSPICLK/SUBR/ GPIO25 – – – – C 1 5 D 1 3 C 1 4 E 1 2 QSPI – P 7 – N 7 – M 8 I2C SDA0/SDATA3/ GPIO42 IO / 4 mA 30 SDA0 SDATA3 11 IO42 – SCL0/SDATA1_BS1/ GPIO41 IO / 4 mA 30 SCL0 SDATA1_BS1 12 IO41 – SDA1/RXD1/GPIO44 IO / 4 mA 30 SDA1 RXD1 19 IO44 SCL1/TXD1/GPIO10 IO / 4 mA 30 SCL1 TXD1 20 IO10 – – – – IO45 – K 9 – P 1 0 – – J 1 5 J 1 3 UART TXD0/GPIO45 IO / 2 mA 30 TXD0 RXD0/GPIO46 IO / 2 mA 30 RXD0 – – IO46 – – – – H 1 2 H 1 5 Power/Ground Pins LININ LINOUT LINGND PLLCOREVDD (3 Balls) – – – – – – – – – – – – – – – – – – – – – – – – – – – – A 1 4 B 1 4 3.3 Volt Supply Required 1.2 Volt Output (Approx 50% Efficient) – C 1 3 S e e N ot e 1.2 Volt Supply Required (M4, N3, P2) s PLLCOREGND (3 Balls) – USBVDD (2 Balls) – – – – – – – S e e N4,P3,R2 N ot e s – – – – – – S e e N ot e 3.3 Volt Supply Required (L13, M13) s USBVDDP USBGND (3 Balls) – – – – – – – – – – – – – – L 1 2 S e e 1.2 Volt Supply Required K11, L11, M12 N ot e s OSCPADVDD OSCPADGND RTC_VDDA RTCVSSA ADVDD ADGND PADVDD (10 Balls) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – N 1 3.3 Volt Supply Required – P 1 J 2 3.3 Volt Supply Required – K 1 K 4 3.3 Volt Supply Required – L 4 S e e N ot e s 3.3 Volt Supply Required (E7, E9, F10, H8, H11, K5, L6, L8, L10, R13) MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 24 Freescale Semiconductor Package Information and Pinout Table 19. 225 MAPBGA Pin Assignment (continued) Name Drive Type/ Load 1st Strength (pF) Function COREVDD (4 Balls) – – – 2nd Function Pinconfig Register Bit GP Pin Reset – – – – Notes S e e N ot e 1.2 Volt Supply Required (G8, H7, H9, J8) s COREVSS/PADVSS (18 Balls)2 – – – – – – – S e e N ot e s 1 2 A1, A15, E8, E10, F7, G6, G7, G9, G11, J7, J9, J10, J11, L5, L7, L9, R1, R15 For test purposes only. Leave ball as open circuit. These pads are listed as “GND” in the ball map and the rest of the tables. MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 25 Package Information and Pinout 6.2 Package Drawing Figure 6 shows the package outline diagram for the MCF5253 processor. TOP VIEW BOTTOM VIEW SIDE VIEW Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14. 5M–1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crown of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Figure 6. MCF5253 Package Drawing MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 26 Freescale Semiconductor Freescale Semiconductor 6.2.1 MAPBGA Pinout Figure 7 shows the MCF5253 ball map of pad locations. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDRAS/ GPIO59 ATA_DMAR Q ATA_A0 ATA_D1 ATA_D6 ATA_D11 ATA_D12 ATA_DIOW LININ GND GND D24 D26 D30 B D19 D23 D25 D28 BCLK/ GPIO40 SDCS0/ GPIO60 ATA_A1 ATA_A2 ATA_D0 ATA_D4 ATA_D9 ATA_D14 HI_Z LINOUT ATA_DIOR B C D16 D20 D22 D27 D31 SDLDQM/ GPO52 SDWE/ GPIO38 ATA_RST ATA_CS0 ATA_D5 ATA_D10 ATA_DMAC K LINGND CAN1_TX CAN0_TX C D A22 A23/GPO54 A21 D21 D29 SDCAS/ GPIO39 ATA_CS1 ATA_D7 ATA_D8 ATA_D15 CAN0_RX MCLK1/ GPIO11 SDATAO2/ D GPIO34 E A14 A16 A18 D17 D18 BCLKE/ GPIO63 PADVDD GND PADVDD GND ATA_D13 CAN1_RX SCLK2/ GPIO22 LRCK2/ GPIO23 RSTI E F A13 A10 A12 A17 A19 A20/A24 GND ATA_D2 ATA_D3 PADVDD TEST0 TMS/BKPT TCK TRST/ DSCLK TDI/DSI F G A5 A7 A6 A15 A11 GND GND COREVDD GND TEST1 GND PST1/ GPIO49 TDO/DSO PSTCLK/ GPIO51 PST0/ GPIO50 G H A3 A2 A1 A8 A4 A9 COREVDD PADVDD COREVDD TEST2 PADVDD TXD0/ GPIO45 PST3/ INTMON1/ GPIO47 PST2/ INTMON2/ GPIO48 RXD0/ GPIO46 H J RTC_CRIN RTC_VDDA CS0/CS4 RW ADOUT/ SCLK4/ GPIO58 ADIN5/ GPI57 GND COREVDD GND GND GND DDATA3/ RTS0/ GPIO4 SCL1/TXD1/ GPIO10 DDATA2/ CTS0/ GPIO3 K RTCVSSA RTCCROUT ADIN0/ GPI52 ADVDD PADVDD BUFENB2/ GPIO30 EBUIN3/CM D_SDIO2/ GPIO14 SCLK1/ GPIO20 SDA0/ SDATA3/ GPIO42 DDATA0/ CTS1/SDAT A0_SDIO1/ GPIO1 USBGND N/C N/C N/C GND PADVDD GND PADVDD GND PADVDD USBGND USBVDDP USBVDD USB_CRIN CFLG/ GPIO5 LRCK3/ AUDCLK/ GPIO43 USBID USBGND USBVDD USBRES USBDP M SDATAI1/ GPIO17 SDATAI3/ GPIO8 N/C N/C N/C USBVBUS USBDN N N/C N/C TESTOUT N/C N/C P R ATA_IORDY ATA_INTRQ L ADIN1/ GPI53 ADIN2/ GPI54 ADIN3/ GPI55 ADGND M ADIN4/ GPI56 ADREF CRIN PLLCORE VDD EBUIN2/ IDE_DIOR/ SCLKOUT/ GPIO31 GPIO13 N OSCPAD VDD CROUT PLLCORE VDD PLLCORE GND TA/GPIO12 P OSCPAD GND PLLCORE VDD R GND PLLCORE GND OE 1 2 3 RCK/QSPID QSPICS1/ IN/QSPIDO EBUOUT2/ UT/GPIO26 GPIO16 EBUIN1/ GPIO36 4 5 SDA1/RXD1 J /GPIO44 N/C LRCK1/ GPIO19 XTRIM/ TXD2/ GPIO0 QSPICS0/ EBUIN4/ GPIO15 SDATAO1/ TOUT0/ GPIO18 EF/RXD2/ GPIO6 SCLK3/ GPIO35 DDATA1/RT S1/SDATA2 _BS2/ GPIO2 N/C PADVDD NC GND 6 7 8 9 10 11 12 13 14 15 QSPICS2/ SCL0/SDAT MCLK2/ A1_BS1/ GPIO24 GPIO41 Figure 7. MCF5253 Ball Map K USB_CROU L T QSPICLK/ SUBR/ GPIO25 PLLCORE IDE_DIOW/ BUFENB1/ EBUOUT1/ GND GPIO32 GPIO29 GPIO37 IDE_IORDY/ WAKEUP/ GPIO33 GPIO21 QSPIDOUT/ CS1/ QSPICS3/ SFSY/ GPIO28 GPIO27 A 27 Package Information and Pinout MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 A SDUDQM/ GPO53 Package Information and Pinout Table 20 shows the signal color and signal name legend. Table 20. Signal Color/Name Legend Color None Name Signal name as listed GND PADVDD COREVDD USBGND Table 21 shows the device pin list, sorted by signal identification. 3 Table 21. MCF5253 13 x 13 BGA (225 Signal ID by Pad Grid Location) Signal ID Pad Location A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20/A24 A21 A22 A23/GPO54 A3 A4 A5 A6 A7 A8 A9 ADGND ADIN0/GPI52 ADIN1/GPI53 ADIN2/GPI54 ADIN3/GPI55 ADIN4/GPI56 ADIN5/GPI57 ADOUT/SCLK4/GPIO58 ADREF ADVDD H03 F02 G05 F03 F01 E01 G04 E02 F04 E03 F05 H02 F06 D03 D01 D02 H01 H05 G01 G03 G02 H04 H06 L04 K03 L01 L02 L03 M01 J06 J05 M02 K04 MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 28 Freescale Semiconductor Package Information and Pinout Table 21. MCF5253 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID Pad Location ATA_A0 ATA_A1 ATA_A2 ATA_CS0 ATA_CS1 ATA_D0 ATA_D1 ATA_D10 ATA_D11 ATA_D12 ATA_D13 ATA_D14 ATA_D15 ATA_D2 ATA_D3 ATA_D4 ATA_D5 ATA_D6 ATA_D7 ATA_D8 ATA_D9 ATA_DIOR ATA_DIOW ATA_DMACK ATA_DMARQ ATA_INTRQ ATA_IORDY ATA_RST BCLK/GPIO40 BCLKE/GPIO63 BUFENB1/GPIO29 BUFENB2/GPIO30 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CFLG/GPIO5 COREVDD COREVDD COREVDD COREVDD CRIN CROUT CS0/CS4 CS1/QSPICS3/GPIO28 D16 A08 B07 B08 C09 D09 B09 A09 C11 A11 A12 E11 B12 D12 F08 F09 B10 C10 A10 D10 D11 B11 B15 A13 C12 A07 D08 D07 C08 B05 E06 P05 K06 D13 C15 E12 C14 M09 G08 H07 H09 J08 M03 N02 J03 M07 C01 MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 29 Package Information and Pinout Table 21. MCF5253 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID Pad Location D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DDATA0/CTS1/SDATA0_SDIO1/GPIO1 DDATA1/RTS1/SDATA2_BS2/GPIO2 DDATA2/CTS0/GPIO3 DDATA3/RTS0/GPIO4 EBUIN1/GPIO36 EBUIN2/SCLKOUT/GPIO13 EBUIN3/CMD_SDIO2/GPIO14 EBUOUT1/GPIO37 EF/RXD2/GPIO6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HI_Z IDE_DIOR/GPIO31 IDE_DIOW/GPIO32 IDE_IORDY/GPIO33 E04 E05 B01 C02 D04 C03 B02 A02 B03 A03 C04 B04 D05 A04 C05 K10 R11 J14 J12 N06 M06 K07 P06 R09 A01 A15 E08 E10 F07 G06 G07 G09 G11 J07 J09 J10 J11 L05 L07 L09 R01 R15 B13 M05 P04 R04 MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 30 Freescale Semiconductor Package Information and Pinout Table 21. MCF5253 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID Pad Location LINGND LININ LINOUT LRCK1/GPIO19 LRCK2/GPIO23 LRCK3/AUDIOCLK/GPIO43 MCLK1/GPIO11 NC OE OSCPADGND OSCPADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PADVDD PLLAVDD PLLCOREGND PLLCOREGND PLLCOREGND PLLCOREVDD PLLCOREVDD PST0/GPIO50 PST1/GPIO49 PST2/INTMON2/GPIO48 PST3/INTMON1/GPIO47 PSTCLK/GPIO51 QSPICLK/SUBR/GPIO25 QSPICS0/EBUIN4/GPIO15 QSPICS1/EBUOUT2/GPIO16 QSPICS2/MCLK2/GPIO24 QSPIDOUT/SFSY/GPIO27 RCK/QSPIDIN/QSPIDOUT/GPIO26 RSTI RTC_CRIN RTC_VDDA RTCCROUT RTCVSSA RW RXD0/GPIO46 SCL0/SDATA1_BS1/GPIO41 C13 A14 B14 P08 E14 M10 D14 R14 R03 P01 N01 E07 E09 F10 H08 H11 K05 L06 L08 L10 R13 M04 N04 P03 R02 N03 P02 G15 G12 H14 H13 G14 P07 R07 N08 P09 M08 N07 E15 J01 J02 K02 K01 J04 H15 P10 MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 31 Package Information and Pinout Table 21. MCF5253 13 x 13 BGA (225 Signal ID by Pad Grid Location) (continued) Signal ID Pad Location SCL1/TXD1/GPIO10 SCLK1/GPIO20 SCLK2/GPIO22 SCLK3/GPIO35 SDA0/SDATA3/GPIO42 SDA1/RXD1/GPIO44 SDATAI1/GPIO17 SDATAI3/GPIO8 SDATAO1/TOUT0/GPIO18 SDATAO2/GPIO34 SDCAS/GPIO39 SDCS0/GPIO60 SDLDQM/GPO52 SDRAS/GPIO59 SDUDQM/GPO53 SDWE/GPIO38 TA/GPIO12 TCK TDI/DSI TDO/DSO TEST0 TEST1 TEST2 TESTOUT TMS/BKPT TRST/DSCLK TXD0/GPIO45 USB_CRIN USB_CROUT USBDN USBDP USBGND USBGND USBGND USBID USBRES USBVBUS USBVDD USBVDD USBVDDP WAKEUP/GPIO21 XTRIM/TXD2/GPIO0 J13 K08 E13 R10 K09 J15 N09 N10 R08 D15 D06 B06 C06 A06 A05 C07 N05 F13 F15 G13 F11 G10 H10 P13 F12 F14 H12 L14 L15 N15 M15 K11 L11 M12 M11 M14 N14 L13 M13 L12 R05 R06 MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 32 Freescale Semiconductor Product Documentation 7 Product Documentation This section includes the related product documentation and references to information posted on Freescale’s external web page. This document is labeled as the type: Data Sheet: Technical Data. Definitions for all Freescale document types are available at: http://www.freescale.com. You can also obtain information on the mechanical characteristics of the MCF5253 integrated microprocessor at http://www.freescale.com/coldfire. The following documents are required for a complete description of the device and are necessary for proper design: MCF5253 Reference Manual (order number: MCF5253RM) MCF5253 Product Brief (order number: MCF5253PB) 7.1 Revision History Table 22 summarizes revisions to this document. Table 22. MCF5253DS Revision History Rev. No. Substantive Change(s) 2 First public version. 3 Added industrial temperature part number, MCF5253CVM140. 4 Added Section 5, “Power Consumption” MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4 Freescale Semiconductor 33 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. 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