Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5373DS
Rev. 4, 11/2008
MCF5373
MAPBGA–256
17mm x 17mm
MCF537x ColdFire®
Microprocessor Data Sheet
Features
• Version 3 ColdFire variable-length RISC processor core
• System debug support
• JTAG support for system level board testing
• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,
accessible by core and non-core bus masters (e.g., DMA,
FEC, and USB host and OTG)
• Power management
• Embedded Voice-over-IP (VoIP) system solution
• SDR/DDR SDRAM Controller
• Universal Serial Bus (USB) Host Controller
• Universal Serial Bus (USB) On-the-Go (OTG) controller
• Synchronous Serial Interface (SSI)
• Fast Ethernet Controller (FEC)
• Cryptography Hardware Accelerators
• FlexCAN Module
• Three Universal Asynchronous Receiver Transmitters
(UARTs)
• I2C Module
• Queued Serial Peripheral Interface (QSPI)
• Pulse Width Modulation (PWM) module
• Real Time Clock
• Four 32-bit DMA Timers
• Software Watchdog Timer
• Four Periodic Interrupt Timers (PITs)
• Phase Locked Loop (PLL)
• Interrupt Controllers (x2)
• DMA Controller
• FlexBus (External Interface)
• Chip Configuration Module (CCM)
• Reset Controller
• General Purpose I/O interface
© Freescale Semiconductor, Inc., 2008. All rights reserved.
QFP–160
28mm x 28mm
MAPBGA–196
15mm x 15mm
Table of Contents
1
2
3
4
5
MCF537x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Supply Voltage Sequencing and Separation Cautions . .5
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3 Pinout—160 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .16
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .17
5.6 External Interface Timing Characteristics . . . . . . . . . . .18
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6
7
8
5.7.1 SDR SDRAM AC Timing Characteristics . . . . .
5.7.2 DDR SDRAM AC Timing Characteristics . . . . .
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
5.9 Reset and Configuration Override Timing . . . . . . . . . .
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
5.12 I2C Input/Output Timing Specifications . . . . . . . . . . . .
5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . .
5.13.1 MII Receive Signal Timing . . . . . . . . . . . . . . . .
5.13.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . .
5.13.3 MII Async Inputs Signal Timing . . . . . . . . . . . .
5.13.4 MII Serial Management Channel Timing . . . . .
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . .
5.15 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
5.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
5.17 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Package Dimensions—196 MAPBGA . . . . . . . . . . . . .
7.2 Package Dimensions—160 QFP . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
23
26
27
28
28
29
31
31
31
32
32
33
33
34
36
36
39
40
41
43
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
2
Freescale Semiconductor
MCF537x Family Comparison
USB Host
(To/From SRAM backdoor)
S4
M6
M5
FlexBus
Chip
Selects
SDRAMC
S1
External
Interface
XBS
M2
M1 S7
USB OTG
USB Host
M0
S6
SDRAMC
QSPI
I2C
UART
Cryptography
Modules
SKHA
(To/From PADI)
SDRAMC
INTC0
RNGA
PADI — Pin Muxing
USB OTG
INTC1
FEC
MDHA
FlexCAN1
DMA Timers
(To/From PADI)
I2C
FEC
CANRX
CANTX
SSI
DREQn
DACKn
D[31:0]
A[23:0]
R/W
UARTs
DMA
EMAC
XCVR XCVR
V3 ColdFire CPU
USB OTG
PORTS
USB Host
16 KByte
Cache
(1024x32)x4
SDRAMC
PWMs, EPORT,
Watchdog, PITs
RESET
RCON
RSTOUT
SSI
Reset
XTAL32K
EXTAL32K
TRST
TCLK
TMS
TDI
TDO
32 KByte
SRAM
(4096x32)x2
RTC
XTAL
EXTAL
PLL
CLKOUT
CS[5:0]
TA
TS
BE/BWE[3:0]
BDM
DIV
(To/From PADI)
QSPI
PWM
DMA Timer
JTAG
TAP
JTAG_EN
Note:
1 FlexCAN is only on the
MCF53721 device
(To/From XBS)
Figure 1. MCF5373 Block Diagram
1
MCF537x Family Comparison
The following table compares the various device derivatives available within the MCF537x family.
Table 1. MCF537x Family Configurations
Module
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
•
•
•
•
•
Core (System) Clock
up to
180 MHz
up to 240 MHz
up to
180 MHz
up to
240 MHz
Peripheral and External Bus Clock
(Core clock ÷ 3)
up to
60 MHz
up to 80 MHz
up to
60 MHz
up to
80 MHz
Performance (Dhrystone/2.1 MIPS)
up to 158
up to 211
up to 158
up to 211
Instruction/Data Cache
16 Kbytes
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
3
Ordering Information
Table 1. MCF537x Family Configurations (continued)
Module
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
Static RAM (SRAM)
32 Kbytes
SDR/DDR SDRAM Controller
•
•
•
•
•
USB 2.0 Host
—
•
•
—
•
USB 2.0 On-the-Go
—
•
•
—
•
Synchronous Serial Interface (SSI)
•
•
•
•
•
Fast Ethernet Controller (FEC)
•
•
•
•
•
Cryptography Hardware Accelerators
—
—
—
•
•
Embedded Voice-over-IP System Solution
—
—
•
—
—
FlexCAN 2.0B communication module
—
—
•
—
—
UARTs
3
3
3
3
3
I2C
•
•
•
•
•
QSPI
•
•
•
•
•
—
•
•
—
•
Real Time Clock
•
•
•
•
•
32-bit DMA Timers
4
4
4
4
4
Watchdog Timer (WDT)
•
•
•
•
•
Periodic Interrupt Timers (PIT)
4
4
4
4
4
Edge Port Module (EPORT)
•
•
•
•
•
Interrupt Controllers (INTC)
2
2
2
2
2
16-channel Direct Memory Access (DMA)
•
•
•
•
•
FlexBus External Interface
•
•
•
•
•
up to 46
up to 62
up to 62
up to 46
up to 62
•
•
•
•
•
160
QFP
196
MAPBGA
196
MAPBGA
160
QFP
196
MAPBGA
PWM Module
General Purpose I/O (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Number
Description
Package
Speed
Temperature
MCF5372CAB180
MCF5372 RISC Microprocessor
160 QFP
180 MHz
–40° to +85° C
MCF5372LCVM240
MCF5372 RISC Microprocessor
196 MAPBGA
240 MHz
–40° to +85° C
MCF53721CVM240
MCF53721 RISC Microprocessor
196 MAPBGA
240 MHz
–40° to +85° C
MCF5373CAB180
MCF5373 RISC Microprocessor
160 QFP
180 MHz
–40° to +85° C
MCF5373LCVM240
MCF5373 RISC Microprocessor
196 MAPBGA
240 MHz
–40° to +85° C
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
4
Freescale Semiconductor
Hardware Design Considerations
3
Hardware Design Considerations
3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in
Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as
close to the dedicated PLLVDD pin as possible.
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 2. System PLL VDD Power Filter
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as
close to the dedicated USBVDD pin as possible.
0Ω
Board EVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 3. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or
3.3V) and EVDD are specified relative to IVDD.
3.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD
must powered up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
5
Pin Assignments and Reset States
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.
3.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power down. IVDD should
not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there is undesired high current in the
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
2.
Drop IVDD/PLLVDD to 0 V.
Drop EVDD/SDVDD supplies.
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF537x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the
MCF537x signals, consult the MCF5373 Reference Manual (MCF5373RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.
Table 3. MCF5372/3 Signal Information and Muxing
Dir.1
Voltage
Domain
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
MCF5372
MCF5373
160 QFP
RESET2
—
—
—
I
EVDD
95
K13
RSTOUT
—
—
—
O
EVDD
86
L12
Signal Name
GPIO
Alternate 1
Alternate 2
Reset
Clock
EXTAL
—
—
—
I
EVDD
91
L14
2
XTAL
—
—
—
O
EVDD
93
K14
EXTAL32K
—
—
—
I
EVDD
—
P13
XTAL32K
—
—
—
O
EVDD
—
N13
FB_CLK
—
—
—
O
SDVDD
40
N1
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
6
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Dir.1
Voltage
Domain
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
MCF5372
MCF5373
160 QFP
RCON
—
—
—
I
EVDD
72
P8
DRAMSEL
—
—
—
I
EVDD
92
J11
Signal Name
GPIO
Alternate 1
Alternate 2
Mode Selection
2
FlexBus
A[23:22]
—
FB_CS[5:4]
—
O
SDVDD
134, 133
A9, B9
A[21:16]
—
—
—
O
SDVDD
132–127
C9, D9, A10,
B10, C10, D10
A[15:14]
—
SD_BA[1:0]3
—
O
SDVDD
126, 123
A11, B11
A[13:11]
—
SD_A[13:11]3
—
O
SDVDD
120–118
C11, A12, B12
A10
—
—
—
O
SDVDD
11 7
A13
3
A[9:0]
—
SD_A[9:0]
—
O
SDVDD
116–107
A14, B14, B13,
C12, D11, C14,
C13, D14–D12
D[31:16]
—
SD_D[31:16]4
—
I/O
SDVDD
27–34, 46–53
J2, J1, K4–K1,
L4, L3, N2, P1,
P2, N3, L5, P3,
N4, P4
D[15:1]
—
FB_D[31:17]4
—
I/O
SDVDD
16–23, 57–63
F2, F1, G4–G1,
H4, H3, L6, M6,
N6, P6, L7, M7,
N7
D02
—
FB_D[16]4
—
I/O
SDVDD
64
P7
BE/BWE[3:0]
PBE[3:0]
SD_DQM[3:0]3
—
O
SDVDD
26, 54, 24, 56
J3, M5, H2, P5
OE
PBUSCTL3
—
—
O
SDVDD
66
M8
TA2
PBUSCTL2
—
—
I
SDVDD
106
E14
R/W
PBUSCTL1
—
—
O
SDVDD
65
L8
TS
PBUSCTL0
DACK0
—
O
SDVDD
12
E2
Chip Selects
FB_CS[5:4]
PCS[5:4]
—
—
O
SDVDD
—
D8, C8
FB_CS[3:2]
PCS[3:2]
—
—
O
SDVDD
—
B8, A8
FB_CS1
PCS1
—
—
O
SDVDD
135
D7
FB_CS0
—
—
—
O
SDVDD
136
C7
SDRAM Controller
SD_A10
—
—
—
O
SDVDD
43
M2
SD_CKE
—
—
—
O
SDVDD
14
F4
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
7
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
Voltage
Domain
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
MCF5372
MCF5373
160 QFP
SD_CLK
—
—
—
O
SDVDD
37
L1
SD_CLK
—
—
—
O
SDVDD
38
M1
SD_CS0
—
—
—
O
SDVDD
15
F3
SD_DQS3
—
—
—
O
SDVDD
25
H1
SD_DQS2
—
—
—
O
SDVDD
55
N5
SD_SCAS
—
—
—
O
SDVDD
44
M3
SD_SRAS
—
—
—
O
SDVDD
45
M4
SD_SDR_DQS
—
—
—
O
SDVDD
35
L2
SD_WE
—
—
—
O
SDVDD
13
E1
External Interrupts Port5
IRQ72
PIRQ72
—
—
I
EVDD
102
F13
IRQ62
PIRQ62
USBHOST_
VBUS_EN
—
I
EVDD
—
F12
IRQ52
PIRQ52
USBHOST_
VBUS_OC
—
I
EVDD
—
F11
IRQ42
PIRQ42
SSI_MCLK
—
I
EVDD
101
G14
IRQ32
PIRQ32
—
—
I
EVDD
—
G13
IRQ22
PIRQ22
USB_CLKIN
—
I
EVDD
—
G12
IRQ12
PIRQ12
DREQ12
SSI_CLKIN
I
EVDD
100
G11
FEC
FEC_MDC
PFECI2C3
I2C_SCL2
—
O
EVDD
4
B1
FEC_MDIO
PFECI2C2
I2C_SDA2
—
I/O
EVDD
3
A1
FEC_COL
PFECH7
—
—
I
EVDD
144
B6
FEC_CRS
PFECH6
—
—
I
EVDD
145
A6
FEC_RXCLK
PFECH5
—
—
I
EVDD
146
A5
FEC_RXDV
PFECH4
—
—
I
EVDD
147
B5
FEC_RXD[3:0]
PFECH[3:0]
—
—
I
EVDD
148–151
C5, D5, A4, B4
FEC_RXER
PFECL7
—
—
I
EVDD
152
C4
FEC_TXCLK
PFECL6
—
—
I
EVDD
153
A3
FEC_TXEN
PFECL5
—
—
O
EVDD
154
B3
FEC_TXER
PFECL4
—
—
O
EVDD
155
A2
FEC_TXD[3:0]
PFECL[3:0]
—
—
O
EVDD
157, 158, 1, 2
D4, C3, B2, C2
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
8
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
USBOTG_M
—
—
—
I/O
USB
VDD
—
H14
USBOTG_P
—
—
—
I/O
USB
VDD
—
H13
USBHOST_M
—
—
—
I/O
USB
VDD
—
J13
USBHOST_P
—
—
—
I/O
USB
VDD
—
J12
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
Voltage
Domain
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
MCF5372
MCF5373
160 QFP
USB Host & USB On-the-Go
FlexCAN (MCF53721 only)
CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:
I2C_SDA for CANRX and I2C_SCL for CANTX.
PWM
PWM7
PPWM7
—
—
I/O
EVDD
—
E13
PWM5
PPWM5
—
—
I/O
EVDD
—
E12
PWM3
PPWM3
DT3OUT
DT3IN
I/O
EVDD
—
E11
PWM1
PPWM1
DT2OUT
DT2IN
I/O
EVDD
—
F14
SSI
The SSI signals do not have dedicated bond pads. Please refer to the following pins for muxing: IRQ4 for SSI_MCLK,
IRQ1 for SSI_CLKIN, U1CTS for SSI_BCLK, U1RTS for SSI_FS, U1RXD for SSI_RXD, and U1TXD for SSI_TXD
I2C
I2C_SCL2
PFECI2C1
CANTX6
U2TXD
I/O
EVDD
—
E3
I2C_SDA2
PFECI2C0
CANRX6
U2RXD
I/O
EVDD
—
E4
DMA
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
QSPI
QSPI_CS2
PQSPI5
U2RTS
—
O
EVDD
78
N12
QSPI_CS1
PQSPI4
PWM7
USBOTG_
PU_EN
O
EVDD
—
M12
QSPI_CS0
PQSPI3
PWM5
—
O
EVDD
—
M11
QSPI_CLK
PQSPI2
I2C_SCL2
—
O
EVDD
77
P12
QSPI_DIN
PQSPI1
U2CTS
—
I
EVDD
75
P11
QSPI_DOUT
PQSPI0
I2C_SDA2
—
O
EVDD
76
N11
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
9
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Dir.1
Voltage
Domain
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
MCF5372
MCF5373
160 QFP
U1CTS
PUARTL7
SSI_BCLK
—
I
EVDD
143
C6
U1RTS
PUARTL6
SSI_FS
—
O
EVDD
142
D6
2
—
O
EVDD
141
A7
2
Signal Name
GPIO
Alternate 1
Alternate 2
UARTs
U1TXD
PUARTL5
SSI_TXD
U1RXD
PUARTL4
SSI_RXD
—
I
EVDD
140
B7
U0CTS
PUARTL3
—
—
I
EVDD
85
M14
U0RTS
PUARTL2
—
—
O
EVDD
84
M13
U0TXD
PUARTL1
—
—
O
EVDD
83
N14
U0RXD
PUARTL0
—
—
I
EVDD
80
P14
Note: The UART2 signals are multiplexed on the QSPI, DMA Timers, and I2C pins.
DMA Timers
DT3IN
PTIMER3
DT3OUT
U2RXD
I
EVDD
8
D1
DT2IN
PTIMER2
DT2OUT
U2TXD
I
EVDD
7
C1
DT1IN
PTIMER1
DT1OUT
DACK1
I
EVDD
6
D2
DT0IN
PTIMER0
DT0OUT
DREQ02
I
EVDD
5
D3
BDM/JTAG7
JTAG_EN8
—
—
—
I
EVDD
96
G10
DSCLK
—
TRST2
—
I
EVDD
88
K11
PSTCLK
—
TCLK2
—
O
EVDD
70
N8
—
TMS2
—
I
EVDD
87
L13
DSI
—
TDI2
—
I
EVDD
90
K12
DSO
—
TDO
—
O
EVDD
74
L11
DDATA[3:0]
—
—
—
O
EVDD
—
L9, M9, N9, P9
PST[3:0]
—
—
—
O
EVDD
—
L10, M10, N10,
P10
ALLPST
—
—
—
O
EVDD
73
—
BKPT
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Alternate 1
Alternate 2
Voltage
Domain
GPIO
Dir.1
Signal Name
MCF5372L
MCF53721
MCF5373L
196 MAPBGA
MCF5372
MCF5373
160 QFP
I
EVDD
124
E10
Test
8
TEST
—
—
—
Power Supplies
1
2
3
4
5
6
7
8
EVDD
—
—
—
—
—
9, 69, 71, 81, 94,
103, 139, 160
E6, E7, F5–F7,
G5, H10, J8,
K8–K9
IVDD
—
—
—
—
—
36, 79, 97, 125,
156
E5, J9, K5, K10
PLL_VDD
—
—
—
—
—
99
J10
SD_VDD
—
—
—
—
—
11, 39, 41, 67,
105, 121, 137
E8–E9, F8–F10,
J4–J7, H5, K6,
K7
USB_VDD
—
—
—
—
—
—
H12
VSS
—
—
—
—
—
10, 42, 68, 82,
89, 104, 122,
138, 159
G6–G9, H6–H9
PLL_VSS
—
—
—
—
—
98
H11
USB_VSS
—
—
—
—
—
—
J14
Refers to pin’s primary function.
Pull-up enabled internally on this signal for this mode.
The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor
when accessing SDRAM memory space and are included here for completeness.
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the
DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
MCF53721 only.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning
these pins.
Pull-down enabled internally on this signal for this mode.
NOTE
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
11
Pin Assignments and Reset States
4.2
Pinout—196 MAPBGA
The pinout for the MCF5373LCVM240, MCF5372LCVM240, and MCF53721CVM240 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
FEC_
MDIO
FEC_
TXER
FEC_
TXCLK
FEC_
RXD1
FEC_
RXCLK
FEC_
CRS
U1TXD
FB_CS2
A23
A19
A15
A12
A10
A9
B
FEC_
MDC
FEC_
TXD1
FEC_
TXEN
FEC_
RXD0
FEC_
RXDV
FEC_
COL
U1RXD
FB_CS3
A22/
A18
A14
A11
A7
A8
DT2IN
FEC_
TXD0
FEC_
TXD2
FEC_
RXER
FEC_
RXD3
U1CTS
FB_CS0 FB_CS4
A21
A17
A13
A6
A3
A4
DT3IN
DT1IN
DT0IN
FEC_
TXD3
FEC_
RXD2
U1RTS
FB_CS1 FB_CS5
A20
A16
A5
A0
A1
A2
SD_WE
TS
I2C_SCL I2C_SDA
IVDD
EVDD
EVDD
SD_VDD SD_VDD
TEST
PWM3
PWM5
PWM7
TA
D14
D15
SD_CS0
SD_CKE
EVDD
EVDD
EVDD
SD_VDD SD_VDD SD_VDD
IRQ5
IRQ6
IRQ7
PWM1
D10
D11
D12
D13
EVDD
VSS
VSS
VSS
VSS
JTAG_
EN
IRQ1
IRQ2
IRQ3
IRQ4
SD_
DQS3
BE/
BWE1
D8
D9
SD_VDD
VSS
VSS
VSS
VSS
EVDD
PLL_
VSS
USBOTG
_VDD
USB
OTG_P
USB
OTG_M
D30
D31
BE/
BWE3
EVDD
IVDD
PLL_
VDD
DRAM
SEL
USB
USB
USBHOST J
HOST_P HOST_M
_VSS
D26
D27
D28
D29
IVDD
EVDD
EVDD
IVDD
TRST/
DSCLK
TDI/DSI
RESET
XTAL
SD_CLK
SD_DR_
DQS
D24
D25
D19
D7
D3
R/W
DDATA3
PST3
TDO/
DSO
RSTOUT
TMS/
BKPT
EXTAL
SD_CAS
SD_RAS
BE/
BWE2
D6
D2
OE
DDATA2
PST2
QSPI_
CS0
QSPI_
CS1
U0RTS
U0CTS
C
D
E
F
G
H
J
K
L
M
N
P
SD_CLK SD_A10
SD_VDD SD_VDD SD_VDD SD_VDD
SD_VDD SD_VDD
FB_CLK
D23
D20
D17
SD_
DQS2
D5
D1
TCLK/
PSTCLK
DDATA1
PST1
QSPI_
DOUT
QSPI_
CS2
XTAL
32K
U0TXD
D22
D21
D18
D16
BE/
BWE0
D4
D0
RCON
DDATA0
PST0
QSPI_
DIN
QSPI_
CLK
EXTAL
32K
U0RXD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
K
L
M
N
P
Figure 4. MCF5373LCVM240, MCF5372LCVM240, and MCF53721CVM240 Pinout Top View (196 MAPBGA)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
12
Freescale Semiconductor
Pin Assignments and Reset States
4.3
Pinout—160 QFP
A18
A17
A16
A15
IVDD
TEST
A14
VSS
SD_VDD
EVDD
VSS
SD_VDD
FB_CS0
FB_CS1
A23/FB_CS5
A22/FB_CS4
A21
A20
A19
FEC_RXD2
FEC_RXD3
FEC_RXDV
FEC_RXCLK
FEC_CRS
FEC_COL
U1CTS
U1RTS
U1TXD
U1RXD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
TA
SD_VDD
VSS
EVDD
IRQ7
IRQ4
IRQ1
PLL_VDD
PLL_VSS
IVDD
JTAG_EN
RESET
EVDD
XTAL
DRAMSEL
EXTAL
TDI/DSI
VSS
TRST/DSCLK
TMS/BKPT
RSTOUT
U0CTS
U0RTS
U0TXD
VSS
EVDD
D2
D1
D0
R/W
OE
SD_VDD
VSS
EVDD
TCLK/PSTCLK
EVDD
RCON
ALL_PST
TDO/DSO
QSPI_DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS2
IVDD
U0RXD
D17
D16
BE/BWE2
SD_DQS0/2
BE/BWE0
D7
D6
D5
D4
D3
SD_VDD
VSS
SD_A10
SD_CAS
SD_RAS
D23
D22
D21
D20
D19
D18
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SD_WE
SD_CKE
SD_CS0
D15
D14
D13
D12
D11
D10
D9
D8
BE/BWE1
SD_DQS1/3
BE/BWE3
D31
D30
D29
D28
D27
D26
D25
D24
SD_DR_DQS
IVDD
SD_CLK
SD_CLK
SD_VDD
FB_CLK
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
•
FEC_TXD1
FEC_TXD0
FEC_MDIO
FEC_MDC
DT0IN
DT1IN
DT2IN
DT3IN
EVDD
VSS
SD_VDD
TS
160 EVDD
159 VSS
158 FEC_TXD2
157 FEC_TXD3
156 IVDD
155 FEC_TXER
154 FEC_TXEN
153 FEC_TXCLK
152 FEC_RXER
151 FEC_RXD0
150 FEC_RXD1
The pinout for the MCF5372CAB180 and MCF5373CAB180 packages is shown below.
Figure 5. MCF5372CAB180 and MCF5373CAB180 Pinout Top View (160 QFP)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical Characteristics
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5373 microcontroller unit.
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications of MCF5373.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications
will be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
Core Supply Voltage
IVDD
– 0.5 to +2.0
V
CMOS Pad Supply Voltage
EVDD
– 0.3 to +4.0
V
DDR/Memory Pad Supply Voltage
SDVDD
– 0.3 to +4.0
V
PLL Supply Voltage
PLLVDD
– 0.3 to +2.0
V
VIN
– 0.3 to +3.6
V
ID
25
mA
TA
(TL - TH)
– 40 to +85
°C
Tstg
– 55 to +150
°C
Digital Input Voltage
3
Instantaneous Maximum Current
Single pin limit (applies to all pins) 3, 4, 5
Operating Temperature Range (Packaged)
Storage Temperature Range
1
2
3
4
5
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or
EVDD).
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
and then use the larger of the two values.
All functional non-supply pins are internally clamped to VSS and EVDD.
Power supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than
IDD, the injection current may flow out of EVDD and could result in external power supply going
out of regulation. Ensure external EVDD load shunts current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power
supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic
Symbol
256MBGA
196MBGA
160QFP
Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θJMA
371,2
421,2
491,2
°C/ W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
341,2
381,2
441,2
°C/ W
Junction to board
θJB
273
323
403
°C/ W
Junction to case
θJC
4
4
4
°C/ W
Junction to top of package
1,5
°C/ W
Maximum operating junction temperature
1
2
3
4
5
16
19
39
Ψjt
1,5
4
51,5
12
Tj
105
105
105
o
C
θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA )
Eqn. 1
Where:
TA
QJMA
PD
PINT
PI/O
=
=
=
=
=
Ambient Temperature, °C
Package Thermal Resistance, Junction-to-Ambient, °C/W
PINT + PI/O
IDD × IVDD, Watts - Chip Internal Power
Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = --------------------------------( T J + 273°C )
Eqn. 2
Solving equations 1 and 2 for K gives:
2
K = P D × ( T A × 273°C ) + Q JMA × P D
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical Characteristics
5.3
ESD Protection
Table 6. ESD Protection Characteristics1, 2
Characteristics
Symbol
Value
Units
ESD Target for Human Body Model
HBM
2000
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive
Grade Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
1.4
1.6
V
PLL Supply Voltage
PLLVDD
1.4
1.6
V
EVDD
3.0
3.6
V
1.70
2.25
3.0
1.95
2.75
3.6
USBVDD
3.0
3.6
V
CMOS Input High Voltage
EVIH
2
EVDD + 0.3
V
CMOS Input Low Voltage
EVIL
VSS – 0.3
0.8
V
CMOS Output High Voltage
IOH = –5.0 mA
EVOH
EVDD – 0.4
—
V
CMOS Output Low Voltage
IOL = 5.0 mA
EVOL
—
0.4
V
SDRAM and FlexBus Input High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVIH
1.35
1.7
2
SDVDD + 0.3
SDVDD + 0.3
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
SDVIL
VSS – 0.3
VSS – 0.3
VSS – 0.3
0.45
0.8
0.8
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
SDVDD – 0.35
2.1
2.4
—
—
—
CMOS Pad Supply Voltage
SDRAM and FlexBus Supply Voltage
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
USB Supply Voltage
V
SDVDD
V
V
V
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic
Min
Max
—
—
—
0.3
0.3
0.5
Iin
−1.0
1.0
μA
Weak Internal Pull-Up Device Current, tested at VIL Max.1
IAPU
−10
−130
μA
Input Capacitance 2
All input-only pins
All input/output (three-state) pins
Cin
—
—
7
7
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOL = 5.0 mA for all modes
Input Leakage Current
Vin = VDD or VSS, Input-only pins
1
Symbol
Unit
V
SDVOL
pF
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
5.5
Oscillator and PLL Electrical Characteristics
Table 8. PLL Electrical Characteristics
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
fref_crystal
fref_ext
12
12
251
401
MHz
MHz
fsys
fsys/3
488 x 10−6
163 x 10−6
240
80
MHz
MHz
tcst
—
10
ms
1
PLL Reference Frequency Range
Crystal reference
External reference
2
Core frequency
CLKOUT Frequency2
3
Crystal Start-up Time3, 4
4
EXTAL Input High Voltage
Crystal Mode5
All other modes (External, Limp)
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
5
EXTAL Input Low Voltage
Crystal Mode5
All other modes (External, Limp)
VILEXT
VILEXT
—
—
VXTAL – 0.4
EVDD/2 – 0.4
V
V
7
PLL Lock Time 3, 6
tlpll
—
50000
CLKIN
tdc
40
60
%
IXTAL
1
3
mA
reference 3
8
Duty Cycle of
9
XTAL Current
10
Total on-chip stray capacitance on XTAL
CS_XTAL
1.5
pF
11
Total on-chip stray capacitance on EXTAL
CS_EXTAL
1.5
pF
CL
See crystal
spec
CL_XTAL
2*CL –
CS_XTAL –
CPCB_XTAL7
12
Crystal capacitive load
Discrete load capacitance for XTAL
13
pF
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical Characteristics
Table 8. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Discrete load capacitance for EXTAL
CL_EXTAL
Min.
Value
Max.
Value
Unit
2*CL–CS_EXTAL –
CPCB_EXTAL7
pF
—
—
10
TBD
% fsys/3
% fsys/3
14
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
17
18
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
0.8
2.2
%fsys/3
19
VCO Frequency. fvco = (fref * PFD)/4
fvco
350
540
MHz
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2
All internal registers retain data at 0 Hz.
3 This parameter is guaranteed by characterization before qualification rather than 100% tested.
4 Proper PC board layout procedures must be followed to achieve specifications.
5 This parameter is guaranteed by design rather than 100% tested.
6 This specification is the PLL lock time only and does not include oscillator start-up time.
7 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.
11 Modulation range determined by hardware design.
5.6
External Interface Timing Characteristics
Table 9 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 9
are shown in Figure 7 and Figure 8.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
FB_CLK (80MHz)
TSETUP
THOLD
Input Setup And Hold
Invalid
1.5V Valid 1.5V
Invalid
trise
Input Rise Time
Vh = VIH
Vl = VIL
tfall
Input Fall Time
FB_CLK
Vh = VIH
Vl = VIL
B4
B5
Inputs
Figure 6. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Table 9. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
—
Frequency of Operation
fsys/3
—
80
Mhz
FB1
Clock Period (FB_CLK)
tFBCK (tcyc)
12.5
—
ns
FB2
Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1
tFBCHDCV
—
7.0
ns
FB3
Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2
tFBCHDCI
1
—
ns
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
Table 9. FlexBus AC Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
FB4
Data Input Setup
tDVFBCH
3.5
—
ns
FB5
Data Input Hold
tDIFBCH
0
—
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4
—
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0
—
ns
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC
Timing Characteristics” for SD_CS[3:0] timing.
2
The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB_D[31:X]
FB2
FB5
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 7. FlexBus Read Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 8. FlexBus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 10. SDR Timing Specifications
Symbol
•
Characteristic
Frequency of Operation1
2
Symbol
Min
Max
Unit
•
60
80
MHz
tSDCK
12.5
16.67
ns
SD3
Pulse Width
High3
tSDCKH
0.45
0.55
SD_CLK
SD4
Pulse Width Low4
tSDCKH
0.45
0.55
SD_CLK
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
tSDCHACV
—
0.5 × SD_CLK
+ 1.0
ns
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
SD7
SD_SDR_DQS Output Valid5
tDQSOV
—
Self timed
ns
tDQVSDCH
0.25 ×
SD_CLK
0.40 × SD_CLK
ns
SD1
Clock Period
6
SD8
SD_DQS[3:0] input setup relative to SD_CLK
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
Table 10. SDR Timing Specifications (continued)
Symbol
Characteristic
Symbol
Min
Max
Unit
SD9
SD_DQS[3:2] input hold relative to SD_CLK7
tDQISDCH Does not apply. 0.5×SD_CLK fixed width.
SD10
Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)8
tDVSDCH
0.25 ×
SD_CLK
—
ns
SD11
Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
tSDCHDMV
—
0.75 × SD_CLK
+ 0.5
ns
tSDCHDMI
1.5
—
ns
SD12
SD13
1
2
3
4
5
6
7
8
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5373
Reference Manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
SD_WE
A[23:0]
SD_BA[1:0]
CMD
SD4
ROW
COL
SD11
SDDM
SD12
D[31:0]
WD1
WD2
WD3
WD4
Figure 9. SDR Write Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
ROW
COL
tDQS
SDDM
SD6
SD_SDR_DQS
(Measured at Output Pin)
Board Delay
SD_DQS[3:2]
SD8
(Measured at Input Pin)
SD7
Board Delay
Delayed
SD_CLK
SD9
D[31:0]
from
Memories
WD1
NOTE: Data driven from memories relative
to delayed memory clock.
WD2
WD3
WD4
SD10
Figure 10. SDR Read Timing
5.7.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.
Table 11. DDR Timing Specifications
Num
•
Characteristic
Frequency of Operation
1
Symbol
Min
Max
Unit
tDDCK
60
80
Mhz
tDDSK
12.5
16.67
ns
DD2
Pulse Width High
2
tDDCKH
0.45
0.55
SD_CLK
DD3
Pulse Width Low3
tDDCKL
0.45
0.55
SD_CLK
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid3
tSDCHACV
—
0.5 × SD_CLK
+ 1.0
ns
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tCMDVDQ
—
1.25
SD_CLK
DD7
Data and Data Mask Output Setup (DQ-->DQS) Relative
to DQS (DDR Write Mode)4, 5
tDQDMV
1.5
—
ns
DD1
Clock Period
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
Table 11. DDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
DD8
Data and Data Mask Output Hold (DQS-->DQ) Relative to
DQS (DDR Write Mode)6
tDQDMI
1.0
—
ns
DD9
Input Data Skew Relative to DQS (Input Setup)7
tDVDQ
—
1
ns
tDIDQ
0.25 × SD_CLK
+ 0.5ns
—
ns
DD11 DQS falling edge from SDCLK rising (output hold time)
tDQLSDCH
0.5
—
ns
DD12 DQS input read preamble width
tDQRPRE
0.9
1.1
SD_CLK
DD13 DQS input read postamble width
tDQRPST
0.4
0.6
SD_CLK
DD14 DQS output write preamble width
tDQWPRE
0.25
DD15 DQS output write postamble width
tDQWPST
0.4
8
DD10
1
2
3
4
5
6
7
8
Input Data Hold Relative to DQS
SD_CLK
0.6
SD_CLK
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
DD4
A[13:0]
DD6
ROW
COL
DD7
DM3/DM2
DD8
SD_DQS3/SD_DQS2
DD7
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DD8
Figure 11. DDR Write Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
CL=2
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
CL=2.5
DD4
A[13:0]
ROW
COL
DD9
DQS Read
Preamble
CL = 2
SD_DQS3/SD_DQS2
DQS Read
Postamble
DD10
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
CL = 2.5
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.8
General Purpose I/O Timing
Table 12. GPIO Timing1
1
Num
Characteristic
Symbol
Min
Max
Unit
G1
FB_CLK High to GPIO Output Valid
tCHPOV
—
10
ns
G2
FB_CLK High to GPIO Output Invalid
tCHPOI
1.5
—
ns
G3
GPIO Input Valid to FB_CLK High
tPVCH
9
—
ns
G4
FB_CLK High to GPIO Input Invalid
tCHPI
1.5
—
ns
GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
FB_CLK
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 13. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 13. Reset and Configuration Override Timing
Num
1
Characteristic
Symbol
Min
Max
Unit
R1
RESET Input valid to FB_CLK High
tRVCH
9
—
ns
R2
FB_CLK High to RESET Input invalid
tCHRI
1.5
—
ns
tRIVT
5
—
tCYC
1
R3
RESET Input valid Time
R4
FB_CLK High to RSTOUT Valid
tCHROV
—
10
ns
R5
RSTOUT valid to Config. Overrides valid
tROVCV
0
—
ns
R6
Configuration Override Setup Time to RSTOUT invalid
tCOS
20
—
tCYC
R7
Configuration Override Hold Time after RSTOUT invalid
tCOH
0
—
ns
R8
RSTOUT invalid to Configuration Override High Impedance
tROICZ
—
1
tCYC
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins])
Figure 14. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5373 Reference Manual for more information.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical Characteristics
5.10
USB On-The-Go
The MCF5373 device is compliant with industry standard USB 2.0 specification.
5.11
SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Table 14. SSI Timing – Master Modes1
Num
Description
Symbol
Min
Max
Units
tMCLK
8 × tSYS
—
ns
45%
55%
tMCLK
8 × tSYS
—
ns
45%
55%
tBCLK
S1
SSI_MCLK cycle time2
S2
SSI_MCLK pulse width high / low
S3
SSI_BCLK cycle time3
S4
SSI_BCLK pulse width
S5
SSI_BCLK to SSI_FS output valid
—
15
ns
S6
SSI_BCLK to SSI_FS output invalid
-2
—
ns
S7
SSI_BCLK to SSI_TXD valid
—
15
ns
S8
SSI_BCLK to SSI_TXD invalid / high impedence
-4
—
ns
S9
SSI_RXD / SSI_FS input setup before SSI_BCLK
15
—
ns
S10
SSI_RXD / SSI_FS input hold after SSI_BCLK
0
—
ns
tBCLK
1
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).
3 SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x fSYS.
2
Table 15. SSI Timing – Slave Modes1
Num
1
Description
Symbol
Min
Max
Units
tBCLK
8 × tSYS
—
ns
45%
55%
tBCLK
S11
SSI_BCLK cycle time
S12
SSI_BCLK pulse width high/low
S13
SSI_FS input setup before SSI_BCLK
10
—
ns
S14
SSI_FS input hold after SSI_BCLK
3
—
ns
S15
SSI_BCLK to SSI_TXD/SSI_FS output valid
—
15
ns
S16
SSI_BCLK to SSI_TXD/SSI_FS output invalid/high
impedence
-2
—
ns
S17
SSI_RXD setup before SSI_BCLK
10
—
ns
S18
SSI_RXD hold after SSI_BCLK
3
—
ns
All timings specified with a capactive load of 25pF.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S7
S8
S8
SSI_TXD
S9
S10
SSI_RXD
Figure 15. SSI Timing – Master Modes
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
S17
S18
SSI_RXD
Figure 16. SSI Timing – Slave Modes
5.12
I2C Input/Output Timing Specifications
Table 16 lists specifications for the I2C input timing parameters shown in Figure 17.
Table 16. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
—
tcyc
I2
Clock low period
8
—
tcyc
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical Characteristics
Table 16. I2C Input Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Units
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4
—
tcyc
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
—
tcyc
I9
Stop condition setup time
2
—
tcyc
Table 17 lists specifications for the I2C output timing parameters shown in Figure 17.
Table 17. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
Start condition hold time
6
—
tcyc
I2 1
Clock low period
10
—
tcyc
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
—
µs
I4 1
Data hold time
7
—
tcyc
I5 3
I3
2
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I6
1
Clock high time
10
—
tcyc
I7
1
Data setup time
2
—
tcyc
I8
1
Start condition setup time (for repeated start condition only)
20
—
tcyc
Stop condition setup time
10
—
tcyc
I9 1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 17 are minimum values.
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
3
Specified at a nominal 50-pF load.
Figure 17 shows timing for the values in Table 17 and Table 16.
I5
I6
I2
I2C_SCL
I1
I4
I7
I8
I3
I9
I2C_SDA
Figure 17. I2C Input/Output Timings
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
5.13
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.13.1
MII Receive Signal Timing
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_RXCLK frequency.
Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup
5
—
ns
M2
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
5
—
ns
M3
FEC_RXCLK pulse width high
35%
65%
FEC_RXCLK period
M4
FEC_RXCLK pulse width low
35%
65%
FEC_RXCLK period
Figure 18 shows MII receive signal timings listed in Table 18.
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RXDV
FEC_RXER
M1
M2
Figure 18. MII Receive Signal Timing Diagram
5.13.2
MII Transmit Signal Timing
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_TXCLK frequency.
Table 19. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
5
—
ns
M6
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
—
25
ns
M7
FEC_TXCLK pulse width high
35%
65%
FEC_TXCLK period
M8
FEC_TXCLK pulse width low
35%
65%
FEC_TXCLK period
Figure 19 shows MII transmit signal timings listed in Table 19.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical Characteristics
M7
FEC_TXCLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TXEN
FEC_TXER
M6
Figure 19. MII Transmit Signal Timing Diagram
5.13.3
MII Async Inputs Signal Timing
Table 20 lists MII asynchronous inputs signal timing.
Table 20. MII Async Inputs Signal Timing
Num
M9
Characteristic
FEC_CRS, FEC_COL minimum pulse width
Min
Max
Unit
1.5
—
FEC_TXCLK period
FEC_CRS
FEC_COL
M9
Figure 20. MII Async Inputs Timing Diagram
5.13.4
MII Serial Management Channel Timing
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5
MHz.
Table 21. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)
—
25
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
10
—
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
—
ns
M14
FEC_MDC pulse width high
40% 60% FEC_MDC period
M15
FEC_MDC pulse width low
40% 60% FEC_MDC period
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 21. MII Serial Management Channel Timing Diagram
5.14
32-Bit Timer Module Timing Specifications
Table 22 lists timer module AC timings.
Table 22. Timer Module AC Timing Specifications
Name
5.15
Characteristic
Min
Max
Unit
T1
DT0IN / DT1IN / DT2IN / DT3IN cycle time
3
—
tCYC
T2
DT0IN / DT1IN / DT2IN / DT3IN pulse width
1
—
tCYC
QSPI Electrical Specifications
Table 23 lists QSPI timings.
Table 23. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QSPI_CS[3:0] to QSPI_CLK
1
510
tCYC
QS2
QSPI_CLK high to QSPI_DOUT valid.
—
10
ns
QS3
QSPI_CLK high to QSPI_DOUT invalid. (Output hold)
2
—
ns
QS4
QSPI_DIN to QSPI_CLK (Input setup)
9
—
ns
QS5
QSPI_DIN to QSPI_CLK (Input hold)
9
—
ns
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 22. QSPI Timing
5.16
JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Characteristics1
Num
1
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/3
J2
TCLK Cycle Period
tJCYC
4
—
tCYC
J3
TCLK Clock Pulse Width
tJCW
26
—
ns
J4
TCLK Rise and Fall Times
tJCRF
0
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4
—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
—
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0
33
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0
33
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4
—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
—
ns
J11
TCLK Low to TDO Data Valid
tTDODV
0
26
ns
J12
TCLK Low to TDO High Z
tTDODZ
0
8
ns
J13
TRST Assert Time
tTRSTAT
100
—
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
—
ns
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 23. Test Clock Input Timing
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 24. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 25. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 26. TRST Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
35
Current Consumption
5.17
Debug AC Timing Specifications
Table 25 lists specifications for the debug AC timing parameters shown in Figure 27.
Table 25. Debug AC Timing Specification
Num
1
Characteristic
Min
Max
Units
D0
PSTCLK cycle time
2
2
tSYS = 1/fSYS
D1
PSTCLK rising to PSTDDATA valid
—
3.0
ns
D2
PSTCLK rising to PSTDDATA invalid
1.5
—
ns
D3
DSI-to-DSCLK setup
1
—
PSTCLK
D41
DSCLK-to-DSO hold
4
—
PSTCLK
D5
DSCLK cycle time
5
—
PSTCLK
D6
BKPT assertion time
1
—
PSTCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 27. Real-Time Trace AC Timing
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 28. BDM Serial Port AC Timing
6
Current Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 26 shows the typical
power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
36
Freescale Semiconductor
Current Consumption
Table 26. Current Consumption in Low-Power Modes1,2
Mode
Stop Mode 3 (Stop 11)5
Stop Mode 2 (Stop 10)4
Stop Mode 1(Stop 01)4
Voltage
58 MHz
(Typ)3
64 MHz
(Typ)3
72 MHz
(Typ)3
80 MHz
(Typ)3
80 MHz
(Peak)4
3.3 V
3.9
3.92
4.0
4.0
4.0
1.5 V
1.04
1.04
1.04
1.04
1.08
3.3 V
4.69
4.72
4.8
4.8
4.8
1.5 V
2.69
2.69
2.70
2.70
2.75
3.3 V
4.72
4.73
4.81
4.81
4.81
1.5 V
15.28
16.44
17.85
19.91
20.42
3.3 V
21.65
21.68
24.33
26.13
26.16
1.5 V
15.47
16.63
18.06
20.12
20.67
3.3 V
22.49
22.52
25.21
27.03
39.8
1.5 V
26.79
28.85
30.81
34.47
97.4
3.3 V
33.61
33.61
42.3
50.5
62.6
1.5 V
56.3
60.7
65.4
73.4
132.3
Units
mA
Stop Mode 0 (Stop
00)4
Wait/Doze
Run
1
2
3
4
5
All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room
temperature with pins configured for high drive strength.
Refer to the Power Management chapter in the MCF537x Reference Manual for more information on low-power
modes.
All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low
power mode. All code executed from flash.
All peripheral clocks on before entering low power mode. All code is executed from flash.
See the description of the low-power control register (LCPR) in the MCF537x Reference Manual for more
information on stop modes 0–3.
Power Consumption (mW)
450
400
350
Stop 0 - Flash
300
Stop 1 - Flash
250
Stop 2 - Flash
200
Stop 3 - Flash
150
Wait/Doze - Flash
100
Run - Flash
50
0
58
64
72
80
80(peak)
fsys/3 (MHz)
Figure 29. Current Consumption in Low-Power Modes
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
37
Current Consumption
Table 27. Typical Active Current Consumption Specifications1
fsys/3 Frequency
Voltage
Typical2 Active
(Flash)
Peak3
3.3V
7.73
7.74
1.5V
2.87
3.56
3.3V
8.57
8.60
1.5V
4.37
5.52
3.3V
40.10
49.3
1.5V
65.90
91.70
3.3V
44.40
54.0
1.5V
69.50
97.0
3.3V
53.6
63.7
1.5V
74.6
104.7
3.3V
63.0
73.7
1.5V
79.6
112.9
Unit
1.333 MHz
2.666 MHz
58 MHz
mA
64 MHz
72 MHz
80 MHz
1
All values are measured with a 3.30 V EVDD, 3.30 V SDVDD and 1.5 V IVDD power
supplies. Tests performed at room temperature with pins configured for high drive
strength.
2 CPU polling a status register. All peripheral clocks except UART0, FlexBus,
INTC0, reset controller, PLL, and edge port disabled.
3
Peak current measured while running a while(1) loop with all modules active.
Figure 30 shows the estimated maximum power consumption.
Estimated Power Consumption vs. Core Frequency
Power Consumption (mW)
300
250
200
150
100
50
0
0
40
80
120
160
Core Frequency (MHz)
200
240
Figure 30. Estimated Maximum Power Consumption
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
38
Freescale Semiconductor
Package Information
7
Package Information
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF537x devices.
NOTE
The mechanical drawings are the latest revisions at the time of publication of this
document. The most up-to-date mechanical drawings can be found at the product summary
page located at http://www.freescale.com/coldfire.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
39
Package Information
7.1
Package Dimensions—196 MAPBGA
Figure 31 shows the MCF5373LCVM240, MCF5372LCVM240, and MCF53721CVM240 package dimensions.
NOTES:
1. Dimensions are in millimeters.
2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.
3. Dimension B is measured at the
maximum solder ball diameter,
parallel to datum plane Z.
4. Datum Z (seating plane) is defined
by the spherical crowns of the solder
balls.
5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.
D
X
Laser mark for pin 1
identification in
this area
Y
M
K
Millimeters
DIM Min Max
E
A
A1
A2
b
D
E
e
S
1.32 1.75
0.27 0.47
1.18 REF
0.35 0.65
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
M
Top View
0.20
13X
e
S
14 13 12 11 10
9
6
5
4
3
2
Metalized mark for
pin 1 identification
in this area
1
A
B
C
S
13X
e
D
5
E
0.30 Z
F
A
A2
G
H
J
K
L
M
A1
Z
0.15 Z
4
Detail K
Rotated 90 ° Clockwise
N
P
3
196X
b
0.30 Z X Y
Bottom View
View M-M
0.10 Z
Figure 31. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
40
Freescale Semiconductor
Package Information
7.2
Package Dimensions—160 QFP
Figure 32 and Figure 33 show the MCF5372CAB180 and MCF5373CAB180 package dimensions.
Top View
Figure 32. 160QFP Package Dimensions (Sheet 1 of 2)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
41
Package Information
Figure 33. 160QFP Package Dimensions (Sheet 2 of 2)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
42
Freescale Semiconductor
Revision History
8
Revision History
Table 28. MCF5373DS Document Revision History
Rev. No.
0
Substantive Changes
Date of Release
• Initial release
11/2005
0.1
• Swapped pin locations PLL_VSS (J11->H11) and DRAMSEL
(H11->J11) in Table 1. Figure 4 is correct.
12/2005
0.2
• Added not to Section 7, “Package Information.”
• Added “top view” and “bottom view” where appropriate in mechanical
drawings and pinout figures.
• Figure 6: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”
3/2006
0.3
• Changed 160QFP pinouts in Figure 5 and Table 2: Removed IRQ3
pin, shifted pins 89–99 up one pin to 90–100. Pin 89 is now VSS.
• Table 2: Rearranged GPIO signal names for FEC pins.
• Removed ULPI specifications as the device does not support ULPI.
4/2006
1
• Updated thermal characteristic values in Table 7.
• Updated DC electricals values in Table 7.
• Updated Section 3.3, “Supply Voltage Sequencing and Separation
Cautions” and subsections.
• Updated and added Oscillator/PLL characteristics in Table 8.
• Table 9: Swapped min/max for FB1; Removed FB8 & FB9.
• Updated SDRAM write timing diagram, Figure 9.
• Table 11: Added values for frequency of operation and DD1.
• Replaced figure & table Section 5.11, “SSI Timing Specifications,”
with slave & master mode versions.
• Removed second sentence from Section 5.13.2, “MII Transmit Signal
Timing,” regarding no minimum frequency requirement for TXCLK.
• Removed third and fourth paragraphs from Section 5.13.2, “MII
Transmit Signal Timing,” as this feature is not supported on this
device.
• Updated figure & table Section 5.17, “Debug AC Timing
Specifications.”
• Renamed & moved previous version’s Section 5.5 “Power
Consumption” to Section 6, “Current Consumption.” Added additional
real-world data to this section as well.
7/2007
2
• Added MCF53721 device information throughout: features list, family
configuration table, ordering information table, signals description
table, and relevant package diagram titles
• Remove Footnote 1 from Table 11.
• Changed document type from Advance Information to Technical Data.
8/2007
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
43
Revision History
Table 28. MCF5373DS Document Revision History (continued)
Rev. No.
Substantive Changes
Date of Release
3
• Removed cryptography from Table 1 for the MCF53721 device.
• Corrected D0 spec in Table 25 from 1.5 x tsys to 2 x tsys for min and
max balues.
• Updated FlexBus read and write timing diagrams in Figure 7 and
Figure 8.
• Corrected package information in Table 2 for MCF5373LCVM240
device from “256 MAPBGA” to “196 MAPBGA”.
• Removed footnote 2 from the IRQ[7:1] alternate functions USBHOST
VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and
SSI_CLKIN signals in Table 6.
4/2008
4
Changed the following specs in Table 10 and Table 11:
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
Added FlexCAN for the MCF53721 device in features list, block diagram,
Signal Information and Muxing table, and GPIO timing diagram
11/2008
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
44
Freescale Semiconductor
Revision History
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
45
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Document Number: MCF5373DS
Rev. 4
11/2008
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