Freescale Semiconductor
Data Sheet
Document Number: MCF5485EC
Rev. 4, 12/2007
MCF548x
MCF548x ColdFire®
Microprocessor
TEPBGA–388
27 mm x 27 mm
Supports MCF5480, MCF5481,
MCF5482, MCF5483, MCF5484, and
MCF5485
Features list:
• ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 200MHz peak internal core frequency (308 MIPS
[Dhrystone 2.1] @ 200 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Separate, 32-entry, fully-associative instruction and
data translation lookahead buffers
– Floating point unit (FPU)
– Double-precision conforms to IEE-754 standard
– Eight floating point registers
• Internal master bus (XLB) arbiter
– High performance split address and data transactions
– Support for various parking modes
• 32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
– Supports DDR and SDR DRAM
– Built-in initialization and refresh
– Up to four chip selects enabling up to one GB of external
memory
• Version 2.2 peripheral component interconnect (PCI) bus
– 32-bit target and initiator operation
– Support for up to five external PCI masters
– 33–66 MHz operation with PCI bus to XLB divider
ratios of 1:1, 1:2, and 1:4
• Flexible multi-function external bus (FlexBus)
– Provides a glueless interface to boot flash/ROM,
SRAM, and peripheral devices
– Up to six chip selects
– 33 – 66 MHz operation
• Communications I/O subsystem
– Intelligent 16 channel DMA controller
– Up to two 10/100 Mbps fast Ethernet controllers (FECs)
each with separate 2-Kbyte receive and transmit FIFOs
– Universal serial bus (USB) version 2.0 device controller
– Support for one control and six programmable
© Freescale Semiconductor, Inc., 2007. All rights reserved.
•
•
•
•
•
•
•
endpoints, interrupt, bulk, or isochronous
– 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
of endpoint descriptor RAM
– Integrated physical layer interface
– Up to four programmable serial controllers (PSCs) each
with separate 512-byte receive and transmit FIFOs for
UART, USART, modem, codec, and IrDA 1.1 interfaces
– I2C peripheral interface
– Two FlexCAN controller area network 2.0B controllers
each with 16 message buffers
– DMA Serial Peripheral Interface (DSPI)
Optional Cryptography accelerator module
– Execution units for:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
32-Kbyte system SRAM
– Arbitration mechanism shares bandwidth between
internal bus masters
System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two 32-bit slice timers alarm and interrupt generation
– Up to four 32-bit general-purpose timers, compare, and
PWM capability
– GPIO ports multiplexed with peripheral pins
Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
PLL and clock generator
– 30 to 66.67 MHz input frequency range
Operating Voltages
– 1.5V internal logic
– 2.5V DDR SDRAM bus I/O
– 3.3V PCI, FlexBus, and all other I/O
Estimated power consumption
– Less than 1.5W (388 PBGA)
Table of Contents
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6
4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Supply Voltage Sequencing and Separation Cautions . .6
4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8
4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10
PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12
FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13
SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15
9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18
PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .22
11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22
11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23
11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24
11.4 MII Serial Management Channel Timing (MDIO,MDC).24
General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25
I2C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25
JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26
DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29
Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . .29
Case Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
List of Figures
Figure 1. MCF548X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. System PLL VDD Power Filter . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Supply Voltage Sequencing and Separation Cautions . 7
Figure 4. Preferred VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 6. USB VDD Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11
Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15.DDR Clock Timing Diagram . . . . . . . . . . . . . . . . . . . .
Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18.PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . .
Figure 20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . .
Figure 21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . .
Figure 22.MII Serial Management Channel TIming Diagram. . .
Figure 23.I2C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . .
Figure 24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . .
Figure 25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . .
Figure 26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . .
Figure 27.TRST Timing Debug AC Timing Specifications . . . . .
Figure 28.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . .
Figure 29.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . .
Figure 30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . .
18
20
21
22
23
23
24
24
26
27
27
27
27
28
28
29
31
List of Tables
Table 1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5
Table 5. USB Filter Circuit Values . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11
Table 8. MCF548x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11
Table 9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12
Table 10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13
Table 11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16
Table 12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18
Table 13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18
Table 14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21
Table 15.MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . 23
Table 16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23
Table 17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24
Table 18.MII Serial Management Channel Signal Timing . . . . . 24
Table 19.General AC Timing Specifications . . . . . . . . . . . . . . . . 25
Table 20.I2C Input Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. I2C Output Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26
Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28
Table 24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29
Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29
MCF548x ColdFire® Microprocessor, Rev. 4
2
Freescale Semiconductor
ColdFire V4e Core
FPU, MMU
EMAC
32K D-cache
32K I-Cache
PLL
DDR SDRAM
Interface
FlexBus
Interface
XL Bus
Arbiter
Memory
Controller
FlexBus
Controller
XL
Cryptography
Accelerator***
Slice
Timers x 2
PCI 2.2
Controller
XL Bus
Read/Write
Write
DMA
DMA
32K System
SRAM
Read
Bus
Slave
GP
Timers x 4
Multi-Channel DMA
Master Bus Interface & FIFOs
FlexCAN
x2
PCI Interface
& FIFOs
CommBus
DSPI
PCI I/O Interface & Ports
Watchdog
Timer
R/W
Master/Slave
Interface
Crypto
Interrupt
Controller
I2C
PSC x 4
FEC1
FEC2**
Perpheral Communications I/O Interface & Ports
USB 2.0
DEVICE*
Communications
I/O Subsystem
Perpheral I/O Interface & Ports
System
Integration Unit
Bus
USB 2.0
PHY*
Figure 1. MCF548X Block Diagram
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
3
Maximum Ratings
1
Maximum Ratings
Table 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of
these ranges may cause erratic behavior or damage to the processor.
Table 1. Absolute Maximum Ratings
Rating
Symbol
Value
Units
External (I/O pads) supply voltage (3.3-V power pins)
EVDD
–0.3 to +4.0
V
Internal logic supply voltage
IVDD
–0.5 to +2.0
V
Memory (I/O pads) supply voltage (2.5-V power pins)
SD VDD
–0.3 to +4.0 SDR Memory
–0.3 to +2.8 DDR Memory
V
PLL supply voltage
PLL VDD
–0.5 to +2.0
V
Vin
–0.5 to +3.6
V
–55 to +150
oC
Internal logic supply voltage, input voltage level
Storage temperature range
Tstg
2
Thermal Characteristics
2.1
Operating Temperatures
Table 2 lists junction and ambient operating temperatures.
Table 2. Operating Temperatures
Characteristic
Symbol
Value
Units
Maximum operating junction temperature
Tj
105
oC
Maximum operating ambient temperature
TAmax
DQS) Relative to
DQS (DDR Write Mode) (tQS)
1.0
—
ns
DD8
Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS
(DDR Write Mode) (tQH)
1.0
DD9
Input Data Skew Relative to DQS (Input Setup) (tIS)
DD10
Input Data Hold Relative to DQS (tIH)
DD11
DD12
7
8
—
ns
9
1
ns
10
0.25 × SDCLK
+ 0.5ns
—
ns
11
DQS falling edge to SDCLK rising (output setup time) (tDSS)
0.5
—
ns
DQS falling edge from SDCLK rising (output hold time) (tDSH)
0.5
—
ns
MCF548x ColdFire® Microprocessor, Rev. 4
18
Freescale Semiconductor
SDRAM Bus
Table 13. DDR Timing Specifications (continued)
Symbol
Characteristic
Min
Max
Unit
DD13
DQS input read preamble width (tRPRE)
0.9
1.1
SDCLK
DD14
DQS input read postamble width (tRPST)
0.4
0.6
SDCLK
DD15
DQS output write preamble width (tWPRE)
0.25
—
SDCLK
DD16
DQS output write postamble width (tWPST)
0.4
0.6
SDCLK
Notes
1
DDR memories typically have a minimum speed specification of 83 MHz. Check memory component specifications to verify.
The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external
reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at
the same frequency as the internal bus clock. Please see the reset configuration signals description in the “Signal
Descriptions” chapter within the MCF548x Reference Manual.
3
SDCLK is one memory clock in (ns).
4
Pulse width high plus pulse width low cannot exceed max clock period.
5 Pulse width high plus pulse width low cannot exceed max clock period.
6 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process,
temperature, and voltage variations.
7 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
8 The first data beat is valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data
beats is valid for each subsequent SDDQS edge.
9 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3,
SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0.
10 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing
or other factors).
11 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data
line becomes invalid.
2
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
19
SDRAM Bus
DD1
DD2
SDCLK0
DD3
SDCLK1
SDCLK0
SDCLK1
DD5
SDCSn,SDWE,
RAS, CAS
CMD
DD4
SDADDR,
SDBA[1:0]
DD6
ROW
COL
DD7
SDDM
DD8
SDDQS
DD7
SDDATA
WD1 WD2 WD3 WD4
DD8
Figure 16. DDR Write Timing
MCF548x ColdFire® Microprocessor, Rev. 4
20
Freescale Semiconductor
PCI Bus
DD1
DD2
SDCLK0
DD3
SDCLK1
SDCLK0
SDCLK1
DD5
SDCSn,SDWE,
RAS, CAS
CL=2
CMD
DD4
SDADDR,
SDBA[1:0]
CL=2.5
ROW
COL
DD9
DQS Read
Preamble
SDDQS
DQS Read
Postamble
DD10
SDDATA
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
SDDQS
WD1 WD2 WD3 WD4
SDDATA
Figure 17. DDR Read Timing
10
PCI Bus
The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please
refer to the PCI 2.2 spec for a more detailed timing analysis.
Table 14. PCI Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
25
50
MHz
1
P1
Clock Period (tCK)
20
40
ns
2
P2
Address, Data, and Command (33< PCI ≤ 50 Mhz)—Input Setup (tIS)
3.0
—
ns
P3
Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (tIS)
7.0
—
ns
P4
Address, Data, and Command (33–50 Mhz)—Output Valid (tDV)
—
6.0
ns
P5
Address, Data, and Command (0–33 Mhz) - Output Valid (tDV)
—
11.0
ns
P6
PCI signals (0–50 Mhz) - Output Hold (tDH)
0
—
ns
3
4
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
21
Fast Ethernet AC Timing Specifications
Table 14. PCI Timing Specifications (continued)
Num
1
2
3
4
5
6
Characteristic
Min
Max
Unit
Notes
P7
PCI signals (0–50 Mhz) - Input Hold (tIH)
0
—
ns
5
P8
PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Output valid (tDV)
—
6
ns
6
P9
PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (tDV)
—
12
ns
P10
PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Input Setup (tIS)
—
5
ns
P11
PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (tIS)
12
—
ns
P12
PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (tIS)
10
—
ns
Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x
Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain
frequencies.
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.
PCI 2.2 spec requires zero input hold.
These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
P1
CLKIN
P4
Output
Valid/Hold
P6
Output Valid
P2
Input
Setup/Hold
Input Valid
P7
Figure 18. PCI Timing
11
Fast Ethernet AC Timing Specifications
11.1
MII/7-WIRE Interface Timing Specs
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this
interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver.
MCF548x ColdFire® Microprocessor, Rev. 4
22
Freescale Semiconductor
Fast Ethernet AC Timing Specifications
Table 15. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
M2
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
M3
RXCLK pulse width high
35%
65%
RXCLK period
M4
RXCLK pulse width low
35%
65%
RXCLK period
Min
Max
Unit
M3
RXCLK (Input)
M1
M4
RXD[3:0] (Inputs)
RXDV,
RXER
M2
Figure 19. MII Receive Signal Timing Diagram
11.2
MII Transmit Signal Timing
Table 16. MII Transmit Signal Timing
Num
Characteristic
M5
TXCLK to TXD[3:0], TXEN, TXER invalid
0
—
ns
M6
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
M7
TXCLK pulse width high
35%
65%
TXCLK period
M8
TXCLK pulse width low
35%
65%
TXCLK period
M7
TXCLK (Input)
M5
M8
TXD[3:0] (Outputs)
TXEN,
TXER
M6
Figure 20. MII Transmit Signal Timing Diagram
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
23
Fast Ethernet AC Timing Specifications
11.3
MII Async Inputs Signal Timing (CRS, COL)
Table 17. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M9
CRS, COL minimum pulse width
1.5
—
TX_CLK period
CRS, COL
M9
Figure 21. MII Async Inputs Timing Diagram
11.4
MII Serial Management Channel Timing (MDIO,MDC)
Table 18. MII Serial Management Channel Signal Timing
Num
Characteristic
Min
Max
Unit
M10
MDC falling edge to MDIO output invalid
(min prop delay)
0
—
ns
M11
MDC falling edge to MDIO output valid
(max prop delay)
—
25
ns
M12
MDIO (input) to MDC rising edge setup
10
—
ns
M13
MDIO (input) to MDC rising edge hold
0
—
ns
M14
MDC pulse width high
40%
60%
MDC period
M15
MDC pulse width low
40%
60%
MDC period
M14
M15
MDC (Output)
M10
MDIO (Output)
M12
M11
MDIO (Input)
M13
Figure 22. MII Serial Management Channel TIming Diagram
MCF548x ColdFire® Microprocessor, Rev. 4
24
Freescale Semiconductor
General Timing Specifications
12
General Timing Specifications
Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts.
Table 19. General AC Timing Specifications
Name
13
Characteristic
Min
Max
Unit
G1
CLKIN high to signal output valid
—
2
PSTCLK
G2
CLKIN high to signal invalid (output hold)
0
—
ns
G3
Signal input pulse width
2
—
PSTCLK
I2C Input/Output Timing Specifications
Table 20 lists specifications for the I2C input timing parameters shown in Figure 23.
Table 20. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
—
Bus clocks
I2
Clock low period
8
—
Bus clocks
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
mS
I4
Data hold time
0
—
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
mS
I6
Clock high time
4
—
Bus clocks
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
—
Bus clocks
I9
Stop condition setup time
2
—
Bus clocks
Table 21 lists specifications for the I2C output timing parameters shown in Figure 23.
Table 21. I2C Output Timing Specifications between SCL and SDA
Num
Min
Max
Units
Start condition hold time
6
—
Bus clocks
Clock low period
10
—
Bus clocks
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
—
µS
I4 1
Data hold time
7
—
Bus clocks
I5 3
I1
1
I2 1
I3
2
Characteristic
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
1
Clock high time
10
—
Bus clocks
I7 1
Data setup time
2
—
Bus clocks
I8 1
Start condition setup time (for repeated start
condition only)
20
—
Bus clocks
I9 1
Stop condition setup time
10
—
Bus clocks
I6
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
25
JTAG and Boundary Scan Timing
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 21. The
I2C interface is designed to scale the actual data transition time to move it to the middle of the
SCL low period. The actual position is affected by the prescale and division values programmed
into the IFDR; however, the numbers given in Table 21 are minimum values.
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance
and pull-up resistor values.
3
Specified at a nominal 50-pF load.
Figure 23 shows timing for the values in Table 20 and Table 21.
I2
I6
I5
SCL
I1
I3
I7
I4
I8
I9
SDA
Figure 23. I2C Input/Output Timings
14
JTAG and Boundary Scan Timing
Table 22. JTAG and Boundary Scan Timing
Characteristics1
Num
1
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
10
MHz
J2
TCLK Cycle Period
tJCYC
2
—
tCK
J3
TCLK Clock Pulse Width
tJCW
15.15
—
ns
J4
TCLK Rise and Fall Times
tJCRF
0.0
3.0
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
5.0
—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
24.0
—
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0.0
15.0
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0.0
15.0
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
5.0
—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10.0
—
ns
J11
TCLK Low to TDO Data Valid
tTDODV
0.0
20.0
ns
J12
TCLK Low to TDO High Z
tTDODZ
0.0
15.0
ns
J13
TRST Assert Time
tTRSTAT
100.0
—
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10.0
—
ns
MTMOD is expected to be a static signal. Hence, it is not associated with any timing
MCF548x ColdFire® Microprocessor, Rev. 4
26
Freescale Semiconductor
JTAG and Boundary Scan Timing
J2
J3
J3
VIH
TCLK (Input)
VIL
J4
J4
Figure 24. Test Clock Input Timing
TCLK
VIH
VIL
5
Data Inputs
6
Input Data Valid
7
Output Data Valid
Data Outputs
8
Data Outputs
7
Data Outputs
Output Data Valid
Figure 25. Boundary Scan (JTAG) Timing
TCLK
VIH
VIL
9
TDI, TMS, BKPT
10
Input Data Valid
11
TDO
Output Data Valid
12
TDO
11
TDO
Output Data Valid
Figure 26. Test Access Port Timing
TCLK
14
TRST
13
Figure 27. TRST Timing Debug AC Timing Specifications
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
27
JTAG and Boundary Scan Timing
Table 23 lists specifications for the debug AC timing parameters shown in Figure 29.
Table 23. Debug AC Timing Specifications
50 MHz
Num
Units
Min
Max
D1
PSTDDATA to PSTCLK setup
4.5
—
ns
D2
PSTCLK to PSTDDATA hold
4.5
—
ns
D3
DSI-to-DSCLK setup
1
—
PSTCLKs
DSCLK-to-DSO hold
4
—
PSTCLKs
DSCLK cycle time
5
—
PSTCLKs
D4
1
D5
1
Characteristic
DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 28 shows real-time trace timing for the values in Table 23.
PSTCLK
D1
D2
PSTDDATA[7:0]
Figure 28. Real-Time Trace AC Timing
Figure 29 shows BDM serial port AC timing for the values in Table 23.
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 29. BDM Serial Port AC Timing
MCF548x ColdFire® Microprocessor, Rev. 4
28
Freescale Semiconductor
DSPI Electrical Specifications
15
DSPI Electrical Specifications
Table 24 lists DSPI timings.
Table 24. DSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
1 × tck
510 × tck
ns
DS1
DSPI_CS[3:0] to DSPI_CLK
DS2
DSPI_CLK high to DSPI_DOUT valid.
—
12
ns
DS3
DSPI_CLK high to DSPI_DOUT invalid. (Output hold)
2
—
ns
DS4
DSPI_DIN to DSPI_CLK (Input setup)
10
—
ns
DS5
DSPI_DIN to DSPI_CLK (Input hold)
10
—
ns
The values in Table 24 correspond to Figure 30.
DSPI_CS[3:0]
DS1
DSPI_CLK
DS2
DSPI_DOUT
DS3
DS4
DS5
DSPI_DIN
Figure 30. DSPI Timing
16
Timer Module AC Timing Specifications
Table 25 lists timer module AC timings.
Table 25. Timer Module AC Timing Specifications
0–50 MHz
Name
Characteristic
Unit
Min
Max
T1
TIN0 / TIN1 / TIN2 / TIN3 cycle time
3
—
PSTCLK
T2
TIN0 / TIN1 / TIN2 / TIN3 pulse width
1
—
PSTCLK
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
29
Case Drawing
17
Case Drawing
MCF548x ColdFire® Microprocessor, Rev. 4
30
Freescale Semiconductor
Case Drawing
Figure 31. 388-pin BGA Case Outline
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
31
Revision History
18
Revision History
Revision
Number
Date
Substantive Changes
2.2
August 29, 2005
Table 7: Changed C1 minimum spec from 15.15 ns to 20 ns and maximum
spec from 33.3 ns to 40 ns.
2.3
August 30, 2005
Table 22: Changed J11 maximum from 15 ns to 20 ns.
2.4
December 14, 2005
3
February 20, 2007
Table 4: Updated DC electrical specifications, VIL and VIH.
Table 6: Changed FlexBus output load from 20pF to 30pF.
Added Section 4.3, “General USB Layout Guidelines.”
4
December 4, 2007
Figure 2: Changed resistor value from 10W to 10Ω
Figure 3: Changed note 1 in from “IVDD should not exceed EVDD, SD VDD
or PLL VDD by more than 0.4V...” to “IVDD should not exceed EVDD or SD
VDD by more than 0.4V...”
Table 3: Updated thermal information for θJMA, θJB, and θJC
Table 4: Added input leakage current spec.
Table 6: Added footnote regarding pads having balanced source & sink
current.
Table 9: Added RSTI pulse duration spec.
Added features list, pinout drawing, block diagram, and case outline.
Table 9: Changed heading maximum from 66 MHz to 50 MHz.
Table 10: Changed frequency of operation maximum from 66 MHz to 50 MHz
and corresponding FB1 minimum from 15.15 ns to 20 ns.
Table 10: Changed FB1 maximum from 33.33 ns to 40 ns.
Table 14: Changed frequency of operation maximum from 66 MHz to 50 MHz
and corresponding FB1 minimum from 15.15 ns to 20 ns.
Table 14: Changed FB1 maximum from 33.33 ns to 40 ns.
Table 14: Changed various entry descriptions from “(33 < PCI ≤ 66 Mhz)” to
(33< PCI ≤ 50 Mhz)
Table 23: Changed heading maximum from 66 MHz to 50 MHz.
Table 25: Changed heading maximum from 66 MHz to 50 MHz.
MCF548x ColdFire® Microprocessor, Rev. 4
32
Freescale Semiconductor
THIS PAGE INTENTIONALLY BLANK
MCF548x ColdFire® Microprocessor, Rev. 4
Freescale Semiconductor
33
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Number: MCF5485EC
Rev. 4
12/2007
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2007. All rights reserved.
工商网监
湘ICP备2023018690号
