MCIMX507CVM1B

Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX50CEC Rev. 7, 10/2013 MCIMX50 Package Information Plastic Package Case 416 MAPBGA 13 x 13 mm, 0.5 mm pitch Case 416 PoPBGA 13 x 13 mm, 0.5 mm pitch Case 400 MAPBGA 17 x 17 mm, 0.8 mm pitch i.MX50 Applications Processors for Consumer Products Ordering Information See Table 1 on page 7 for ordering information. 1 Introduction The i.MX50 applications processors are multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX50 processors are Freescale Energy Efficiency Solutions products. The i.MX50 is optimized for portable multimedia applications and features Freescale’s advanced implementation of the ARM Cortex-A8® core, which operates at speeds as high as 1 GHz. The i.MX50 provides a powerful display architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). Additionally, the i.MX50 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. 1. 2. 3. 4. 5. The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the 6. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2013 Freescale Semiconductor, Inc. All rights reserved. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 1.4. Part Number Feature Comparison . . . . . . . . . . . . . 8 1.5. Package Feature Comparison . . . . . . . . . . . . . . . . 9 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 21 4.2. Supply Power-Up/Power-Down Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4. Output Buffer Impedance Characteristics . . . . . . 37 4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 48 4.7. External Interface Module (EIM) . . . . . . . . . . . . . . 60 4.8. DRAM Timing Parameters . . . . . . . . . . . . . . . . . . 68 4.9. External Peripheral Interfaces . . . . . . . . . . . . . . . 73 Package Information and Contact Assignments . . . . . 101 5.1. 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.2. 13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3. 17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.4. Signal Assignments . . . . . . . . . . . . . . . . . . . . . . 124 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Introduction application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, and displays. 1.1 Product Overview The i.MX50 is designed to enable high-tier portable applications by satisfying the performance requirements of advanced operating systems and applications. 1.1.1 Dynamic Performance Scaling Freescale’s dynamic voltage and frequency scaling (DVFS) allows the device to run at much lower voltage and frequency with ample processing capacity for tasks, such as audio decode, resulting in significant power reduction. 1.1.2 Multimedia Processing Powerhouse The multimedia performance of the i.MX50 processor ARM Cortex-A8 core is boosted by a multi-level cache system, a NEON™ coprocessor with SIMD media processing architecture and 32-bit single-precision floating point support, and two vector floating point coprocessors. The system is further enhanced by a programmable smart DMA (SDMA) controller. 1.1.3 Powerful Display System The i.MX50 includes support for both standard LCD displays as well as electrophoretic displays (e-paper). The display subsystem consists of the following modules: • Electrophoretic Display Controller (EPDC) (i.MX508 only) The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD controller. It is specifically designed to drive E-INKTM EPD panels, supporting a wide variety of TFT architectures. The goal of the EPDC is to provide an efficient SoC integration of this functionality for e-paper applications, allowing a significant bill of materials cost savings over an external solution while reaching much higher levels of performance and lower power. The EPDC module is defined in the context of an optimized hardware/software partitioning and works in conjunction with the ePXP (see Section 1.1.4, “Graphics Accelerators”). • Enhanced LCD Controller Interface (eLCDIF) The eLCDIF is a high-performance LCD controller interface that supports a rich set of modes and allows interoperability with a wide variety of LCD panels, including DOTCK/RGB and smart panels. The module also supports synchronous operation with the ePXP to allow the processed frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF can support up to 32-bit interfaces. 1.1.4 Graphics Accelerators Integrated graphics accelerators offload processing from the ARM processor, enabling high performance graphic applications at minimum power. i.MX50 Applications Processors for Consumer Products, Rev. 7 2 Freescale Semiconductor Introduction • • 1.1.5 Pixel Processing Pipeline (ePXP) The ePXP is a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma mapping, and rotation. The ePXP is enhanced with features specifically for grayscale applications working in conjunction with the electrophoretic display controller to form a full grayscale display solution. In addition, the ePXP supports traditional pixel/frame processing paths for still-image and video processing applications, allowing it to interface with the integrated LCD controller (eLCDIF). Graphics acceleration The i.MX50 provides a 2D graphics accelerator with performance up to 200 Mpix/s. Multilevel Memory System The multilevel memory system of the i.MX50 is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The i.MX50 supports many types of external memory devices, including DDR2, LPDDR2, LPDDR1, NOR Flash, PSRAM, Cellular RAM, NAND Flash (MLC and SLC) and OneNAND™, and managed NAND including eMMC up to rev. 4.4. 1.1.6 Smart Speed™ Technology The i.MX50 device has power management throughout the SOC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart Speed technology enables the designer to deliver a feature-rich product that requires levels of power that are far less than industry expectations. 1.1.7 Interface Flexibility The i.MX50 supports connection to a variety of interfaces, including an LCD controller for displays, two high-speed USB on-the-go-capable PHYs, multiple expansion card ports (high-speed MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces (for example, UART, I2C, and I2S serial audio). 1.1.8 Advanced Security The i.MX50 delivers hardware-enabled security features, such as High-Assurance Boot 4 (HAB4) for signed/authenticated firmware images, basic DRM support with random private keys and AES encryption/decryption, and storage and programmability of on-chip fuses. 1.2 Features The i.MX50 applications processor is based on the ARM Cortex-A8 platform and has the following features: • MMU, L1 instruction cache, and L1 data cache • Unified L2 cache • 800 MHz or 1 GHz target frequency of the core (including NEON, VFPv3, and L1 cache) i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 3 Introduction • NEON coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite) coprocessor supporting VFPv3 The memory system consists of the following components: • Level 1 cache: — Instruction (32 Kbyte) — Data (32 Kbyte) • Level 2 cache: — Unified instruction and data (256 Kbyte) • Level 2 (internal) memory: — Boot ROM, including HAB (96 Kbyte) — Internal multimedia/shared, fast access RAM (128 Kbyte) • External memory interfaces: — 16/32-bit DDR2-533, LPDDR2-533, or LPDDR1-400 up to a total of 2 GByte — 8-bit NAND SLC/MLC Flash with up to 100 MHz synchronous clock rate and up to 32-bit hardware ECC for 1 Kbyte block size — 16/32-bit NOR Flash with a dedicated 16-bit muxed-mode interface. I/O muxing logic selects EIMv2 port as primary muxing at system boot. — 16-bit PSRAM, Cellular RAM — Managed NAND, including eMMC up to rev 4.4 The i.MX50 introduces a next generation system bus fabric architecture that aggregates various sub-system buses and masters for access to system peripherals and memories. The various bus-systems and components are as follows: • 64-bit AXI Fabric (266 MHz)—This bus-fabric is the SoC’s central bus aggregation point. — Provides access to all slave targets in the SoC: – ROM (ROMCP) – On-chip RAM (OCRAM) – External DRAM (DRAM MC) – External static RAM (EIM) – Interrupt controller (TZIC) – Decode into the AHB MAX crossbar second level AHB fabric. — Provides arbitration to the following masters in the system: – ARM CPU complex – Pixel processing pipeline (ePXP) – Electrophoretic display controller (EPDC) – eLCDIF LCD display controller – DCP Crypto engine – BCH ECC engine – MAX AHB crossbar i.MX50 Applications Processors for Consumer Products, Rev. 7 4 Freescale Semiconductor Introduction • • • – GPU 2D – SDMA – USBOH1 (USB OTG and host controller complex) – FEC Ethernet controller MAX AHB crossbar (133 MHz)—This connects the various AHB bus sub-segments in the system and provides decode into the following slaves: — IP-Bus 1 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and without DMA capability — IP-Bus 2 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and without DMA capability — APBH DMA bridge (133 MHz)—The APBH DMA bridge is a master to the MAX for its memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing peripheral access to many of the high-speed IP blocks on the i.MX50. IP-Bus 3 (66 MHz)—This third peripheral bus segment contains peripherals accessible by the ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be accessed by the ARM CPU through IP-Bus 1 and SPBA. Quality of service controller (QoSC)—This provides both soft and dynamic arbitration/priority control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and EPDC to provide dynamic priority control, based on real-time metrics. The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption, while freeing up the CPU core for other tasks. The i.MX50 incorporates the following hardware accelerators: • GPU2Dv1—2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance • ePXP—enhanced PiXel Processing Pipeline off loading key pixel processing operations required to support both LCD and EPD display applications The i.MX50 includes the following interfaces to external devices: NOTE Not all the interfaces are available simultaneously depending on I/O multiplexer configuration. • • Displays: — EPDC (i.MX508 Only)—Supporting direct-driver TFT backplanes beyond 2048 × 1536 at 106 Hz refresh (or 4096 × 4096 at 20 Hz) — eLCDIF—Supporting beyond SXGA + (1400 × 1050) at 60 Hz resolutions with up to a 32-bit display interface — On the i.MX508, both displays can be active simultaneously. If both displays are active, the eLCDIF only provides a 16-bit interface due to pin muxing. Expansion cards: — Four SD/MMC card i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 5 Introduction • • USB: — One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY — One High Speed (HS) USB 2.0 host port with integrated HS USB PHY Miscellaneous interfaces: — One-wire (OWIRE) port — Two I2S/SSI/AC97 ports, supporting up to 1.4 Mbps each connected to the Audio Multiplexer (AUDMUX) providing four external ports — Five UART RS232 ports, up to 4.0 Mbps each — Two eCSPI (Enhanced CSPI) ports, up to 66 Mbps each plus CSPI port, up to 16.6 Mbps — Three I2C ports, supporting 400 kbps — Fast Ethernet controller IEEE 802.3, 10/100 Mbps — Key pad port (KPP) — Two pulse width modulators (PWM) — GPIO with interrupt capabilities — Secure JTAG controller (SJC) The system supports efficient and smart power control and clocking: • Supporting DVFS techniques for low power modes, including auto slow architecture • Power gating-SRPG (state retention power gating) for ARM core and NEON • Support for various levels of system power modes • Flexible clock gating control scheme • On-chip temperature monitor • On-chip 32 kHz and 24 MHz oscillators • A total of four PLLs with the fourth PLL providing up to eight independently controllable outputs, improving the ease of clocking control, especially for display and connectivity modules Security functions are enabled and accelerated by the following hardware: • Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features • Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches • Advanced high assurance boot (A-HAB)—HAB with the next embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization i.MX50 Applications Processors for Consumer Products, Rev. 7 6 Freescale Semiconductor Introduction 1.3 Ordering Information Table 1 provides the ordering information. Table 1. Ordering Information Part Number Maximum Mask ARM CLK Set Frequency Features Temperature Range (°C) Tambient Tjunction Package1 MCIMX508CVK1B 1 GHz N78A Full Specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX508CVM1B 1 GHz N78A Full Specification 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX508CVK8B 800 MHz N78A Full Specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX508CZK8B 800 MHz N78A Full Specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 PoPBGA MCIMX508CVM8B 800 MHz N78A Full Specification 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX507CVM1B 1 GHz N78A No GPU 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX507CVK1B 1 GHz N78A No GPU 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX507CVM8B 800 MHz N78A No GPU 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX507CVK8B 800 MHz N78A No GPU 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX503CVK8B 800 MHz N78A No EPD controller 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX503CVM8B 800 MHz N78A No EPD controller 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX503EVM8B 800 MHz N78A No EPD controller, Extended Temperature MCIMX502CVK8B 800 MHz N78A No GPU, no EPD controller 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX502CVM8B 800 MHz N78A No GPU, no EPD controller 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX502EVM8B 800 MHz N78A No GPU, no EPD controller, Extended Temperature 1 -20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA -20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA Case MAPBGA is RoHS compliant, lead-free MSL (Moisture Sensitivity Level) 3. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 7 Introduction 1.4 Part Number Feature Comparison Table 2 provides an overview of the feature differences between the i.MX50 part numbers. Table 2. Part Number Feature Comparison Part Number Disabled Features Comments MCIMX508 None MCIMX507 GPU MCIMX503 EPDC The i.MX503 has the same ball map and IOMUX as the i.MX508. The EPDC pins still exist on the i.MX503, but because the EPDC block is disabled, those pins cannot be used for EPDC functionality (ALT0) and must be configured in the IOMUX with another ALT-mode setting. MCIMX502 GPU, EPDC The i.MX502 has the same ball map and IOMUX as the i.MX508. The EPDC pins still exist on the i.MX502, but because the EPDC block is disabled, those pins cannot be used for EPDC functionality (ALT0) and must be configured in the IOMUX with another ALT-mode setting. i.MX50 Applications Processors for Consumer Products, Rev. 7 8 Freescale Semiconductor Introduction 1.5 Package Feature Comparison Table 3 provides an overview of the feature and pin differences between the i.MX50 packages. Table 3. Package Feature Comparison Package Dimensions I/O Pin Differences Versus 416 MAPBGA Notes on Package Differences 416 MAPBGA 13 x 13 mm, 0.5 mm pitch — • USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 MAPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 MAPBGA package substrate. 416 PoPBGA 13 x 13 mm, 0.5 mm pitch Deleted Pins: DRAM_A10 DRAM_A11 DRAM_A12 DRAM_A13 DRAM_A14 DRAM_CAS DRAM_OPEN DRAM_OPENFB DRAM_RAS DRAM_SDBA0 DRAM_SDBA1 DRAM_SDBA2 DRAM_SDCLK_1 DRAM_SDCLK_1_B DRAM_SDODT0 DRAM_SDODT1 DRAM_SDWE DRAM_OPEN DRAM_OPENFB • The i.MX50 PoPBGA package supports 168-FBGA LPDDR2 DRAM memory only. It is not possible to support LPDDR1 or DDR2 on the i.MX50 PoPBGA. • i.MX50 PoPBGA was designed to accommodate a combined LPDDR2 / eMMC PoP memory. The PoP eMMC device uses the SD3_DATA[7:0], SD3_CLK, and SD3_CMD pins. Because the PoP eMMC I/O and memory supplies are tied together on the substrate, 1.8 V eMMC I/O operation is not supported for the PoP eMMC device. POP_NAND_VCC and NVCC_NANDF must use a 3 V supply. • The NVCC_EMI_DRAM power pins supply 1.2 V power to the i.MX50 DRAM controller as well as the PoP LPDDR2 DRAM. • Additional PoP package pin descriptions may be found in the Special Signals Considerations section (Table 5). • On the PoPBGA package, the DRAM Address, Data, and clock pins are routed to the bottom balls for Freescale test purposes only. It is recommended that these bottom DRAM pins are left unconnected on the customer PCB. • USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 PoPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 PoPBGA package substrate. Added Pins: POP_EMMC_RST POP_LPDDR2_ZQ0 POP_LPDDR2_ZQ1 POP_LPDDR2_1.8V POP_NAND_VCC 400 MAPBGA 17 x 17 mm, 0.8 mm pitch Deleted Pins: DRAM_SDCLK_1 DRAM_SDCLK_1_B DRAM_A14 DRAM_SDODT1 UART2_CTS UART2_RTS • USB_OTG_VDDA25 and USB_H1_VDDA25 are independent and NOT shorted together on the 400 MAPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are independent and NOT shorted together on the 400 MAPBGA package substrate. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 9 Architectural Overview 2 Architectural Overview The following sections provide an architectural overview of the i.MX50 processor system. 2.1 Block Diagram Figure 1 shows the functional modules in the i.MX50 processor system. Figure 1. i.MX50 System Block Diagram i.MX50 Applications Processors for Consumer Products, Rev. 7 10 Freescale Semiconductor Modules List NOTE The numbers in brackets indicate the number of module instances. For example, PWM (2) indicates two separate PWM peripherals. 3 Modules List The i.MX50 processor contains a variety of digital and analog modules that are described in Table 4 in alphabetical order. Table 4. i.MX50 Digital and Analog Modules Block Mnemonic ARM Cortex-A8 Block Name Subsystem Brief Description ARM Cortex-A8 ARM Platform The ARM Cortex-A8 Core Platform consists of the ARM Cortex-A8 processor and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache. The platform also contains an event monitor and debug modules. It also has a NEON coprocessor with SIMD media processing architecture, register file with 32 × 64-bit general-purpose registers, an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating point execute pipeline (FADD, FMUL), load/store and permute pipeline, and a non-pipelined vector floating point (VFP Lite) coprocessor supporting VFPv3. EPDC Electrophoretic Display Display Peripherals Controller The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD controller. It is specifically designed to drive E-INKTM EPD panels supporting a wide variety of TFT backplanes. ePXP enhanced PiXel Display Processing Peripherals Pipeline A high-performance pixel processor capable of 1 pixel/clock performance for combined operations such as color-space conversion, alpha blending, gamma-mapping, and rotation. The ePXP is enhanced with features specifically for grayscale applications. In addition, the ePXP supports traditional pixel/frame processing paths for still-image and video processing applications allowing it to interface with the integrated LCD controller (eLCDIF). eLCDIF enhanced LCD Display Interface Peripherals The eLCDIF is a high-performance LCD controller interface supporting a rich set of modes allowing inter operability with a wide variety of LCD panels, including DOTCK/RGB and smart panels. The module also supports a synchronous operation with the ePXP to allow the processed frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF can support up to 32-bit interfaces. AUDMUX Digital Audio Mux Slave Connectivity Peripherals The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1 and SSI2) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has six ports (two internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports. CAMP-1 Clock Amplifier Clocks, Clock Amplifier Resets, and Power Control i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 11 Modules List Table 4. i.MX50 Digital and Analog Modules (continued) Block Mnemonic CCM GPC SRC CSPI eCSPI-1 eCSPI-2 DAP TPIU CTI DRAM MC Block Name Clock Control Module Global Power Controller System Reset Controller Subsystem Brief Description Clocks, These modules are responsible for clock and reset distribution in the system, Resets, and and also for system power management. Power Control The system includes four PLLs. Configurable Slave SPI, Enhanced Connectivity CSPI Peripherals Full-duplex enhanced synchronous serial interface, with data rate up to 66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. Debug System The Debug System provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, three cross-system triggers (CTI), counters, and sequencers. Debug access port (DAP)—The DAP provides real-time access for the debugger without halting the core to System memory and peripheral registers. All debug configuration registers and Debugger access to JTAG scan chains. System Control Peripherals DRAM Memory External Controller Memory Interface The DRAM MC consists of a DRAM memory controller and PHY, supporting LPDDR2, DDR2, and LPDDR1 memories with clock frequencies up to 266 MHz with 32-bit interface. It is tightly linked with the system bus fabric and employs advanced arbitration mechanism to maximize DRAM bandwidth efficiency. Static Memory Controller External Memory Interface The EIM is an external static memory and generic host interface. It supports up to a 32-bit interface (through pin-muxing) or a dedicated 16-bit muxed interface. It can be used to interface to PSRAMs (sync and async), NOR-flash or any external memory mapped peripheral. BCH32/GPMI2 Raw NAND System with ECC RawNAND and SSP Peripherals The i.MX50 contains a fully hardware accelerated raw NAND flash solution supporting SLC and MLC devices. The system consists of the GPMI2 module, which is driven by the APBH DMA engine to perform the NAND flash interface function (supporting up to ONFI2.1). Coupled with the GPMI2 is the BCH32 hardware error-correction engine which is an AXI bus-master and supports up to 32-bits of correction over block sizes up to 1 Kbyte (that is, supports up to 2 Kbyte code-size). System Fabric System Fabric and QoS and QoS System Peripherals In order to aggregate the multitude of masters and memory mapped devices, the i.MX50 contains a next-generation AMBA3 AXI bus fabric. In addition, the i.MX50 contains a Quality of Service Controller IP (QoSC) which allows both soft priority control and dynamic priority elevation. Software priority control works for all masters but dynamic hardware control only works for EPDC and eLCDIF. Timer Peripherals Each EPIT is a 32-bit set and forget timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. EIM EPIT Enhanced Periodic Interrupt Timer i.MX50 Applications Processors for Consumer Products, Rev. 7 12 Freescale Semiconductor Modules List Table 4. i.MX50 Digital and Analog Modules (continued) Block Mnemonic Block Name Subsystem Brief Description eSDHCv3-3 (eMMC 4.4) Ultra-HighMaster Speed Connectivity Multi-Media Peripherals Card/ Secure Digital card host controller, ver. 3 Ultra High-Speed eSDHC, enhanced to support eMMC 4.4 standard specification, for 832 Mbps. IP is backward compatible to eSDHCv2 IP. See complete features listing in eSDHCv2 entry below. Port 3 is specifically enhanced to support eMMC 4.4 specification, for double data rate (832 Mbps, 8-bit port). eSDHCv2-1 eSDHCv2-2 Enhanced Multi-Media Card/ Secure Digital Host Controller, ver. 2 In Enhanced Multi-Media Card/Secure Digital Host Controller the Ports 1, 2, and 4 are compatible with the MMC System Specification version 4.3, full support The generic features of the eSDHCv2 module, when serving as SD/MMC host, include the following: • Can be configured either as SD/MMC controller • Supports eSD and eMMC standard, for SD/MMC embedded type cards • Conforms to SD Host Controller Standard Specification version 2.0, full support • Compatible with the SD Memory Card Specification version 1.1 • Compatible with the SDIO Card Specification version 1.2 • Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC and MMC RS cards • Configurable to work in one of the following modes: —SD/SDIO 1-bit, 4-bit —MMC 1-bit, 4-bit, 8-bit • Full/High speed mode • Host clock frequency variable between 32 kHz to 52 MHz • Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines • Up to 416 Mbps data transfer for MMC cards using eight parallel data lines eSDHCv2-4 FEC GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 GPT Fast Ethernet Controller Master Connectivity Peripherals The Ethernet Media Access Controller (MAC) is designed to support both 10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media. General Purpose I/O Modules Slave Connectivity Peripherals These modules are used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. General Purpose Timer Timer Peripherals Each GPT is a 32-bit free-running or set and forget mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 13 Modules List Table 4. i.MX50 Digital and Analog Modules (continued) Block Mnemonic GPU2Dv1 Block Name Subsystem Brief Description Graphics Processing Unit-2D, ver. 1 Display Peripherals The GPU2Dv1 provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. I2C-1 I2C-2 I2C-3 I2C Interface Connectivity Peripherals I2C provides serial interface for controlling peripheral devices. Data rates of up to 400 kbps are supported. OCOTP Controller On-chip OTP controller Security Peripherals The on-chip one-time -programmable (OCOTP) ROM serves the functions of hardware and software capability bits, Freescale operations and unique-ID, the customer-programmable cryptography key, and storage of various ROM and general purpose configuration bits. IOMUXC IOMUX Control Slave Connectivity Peripherals This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. Keypad Port Slave Connectivity Peripherals The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection OWIRE One-Wire Interface Slave Connectivity Peripherals One-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example, Dallas DS2502. PWM-1 PWM-2 Pulse Width Modulation Slave Connectivity Peripherals The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound. RAM 128 Kbytes Internal RAM Internal Memory The On-Chip Memory controller (OCRAM) module, is an interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is used for controlling the 128 Kbyte multimedia RAM, through a 64-bit AXI bus. ROM 96 Kbytes Boot ROM Internal Memory Supports secure and regular Boot Modes. The ROM Controller supports ROM Patching. KPP i.MX50 Applications Processors for Consumer Products, Rev. 7 14 Freescale Semiconductor Modules List Table 4. i.MX50 Digital and Analog Modules (continued) Block Mnemonic Block Name Subsystem Brief Description SDMA Smart Direct Memory Access Master Connectivity Peripherals The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by offloading various cores in dynamic data routing. The SDMA features list is as follows: • Powered by a 16-bit instruction-set micro-RISC engine • Multi-channel DMA supports up to 32 time-division multiplexed DMA channels • 48 events with total flexibility to trigger any combination of channels • Memory accesses including linear, FIFO, and 2D addressing • Shared peripherals between ARM Cortex-A8 and SDMA • Very fast context-switching with two-level priority-based preemptive multi-tasking • DMA units with auto-flush and prefetch capability • Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) • DMA ports can handle uni-directional and bi-directional flows (copy mode) • Up to 8-word buffer for configurable burst transfers for EMI • Support of byte-swapping and CRC calculations • A library of scripts and API is available SJC Secure JTAG Controller System Control Peripherals The Secure JTAG Controller provides a mechanism for regulating JTAG access, preventing unauthorized JTAG usage while allowing JTAG access for manufacturing tests and software debugging. The i.MX50 JTAG port provides debug access to several hardware blocks including the ARM processor and the system bus, therefore, it must be accessible for initial laboratory bring-up, manufacturing tests and troubleshooting, and for software debugging by authorized entities. However, if the JTAG port is left unsecured it provides a method for executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The Secure JTAG controller provides three different security modes that can be selected through an e-fuse configuration to prevent unauthorized JTAG access. SPBA Shared Peripheral Bus Arbiter System Control Peripherals SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus) arbiter. SRTC Secure Real Time Clock Security Peripherals The SRTC incorporates a special System State Retention Register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC. The NVCC_SRTC can be energized separately even if all other supply rails are shut down. This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR marks the event (security violation indication). i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 15 Modules List Table 4. i.MX50 Digital and Analog Modules (continued) Block Mnemonic SSI-1 SSI-2 Temperature Monitor UART-1 UART-2 UART-3 UART-4 UART-5 Block Name I2S/SSI/AC97 Interface Temp Sensor Subsystem Brief Description Slave Connectivity Peripherals The SSI is a full-duplex synchronous interface used on the i.MX50 processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX for mapping to external ports. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options. Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two time slots are being used simultaneously. Analog The temperature sensor is an internal module to the i.MX50 that monitors the die temperature. UART Interface, Slave ver. 2 Connectivity Peripherals Each of the UARTv2 modules supports the following serial data transmit/receive protocols and configurations: • 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) • Programmable bit-rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F standard. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) USB 2.0 High-Speed OTG-capable and Host ports Master Connectivity Peripherals USB-OH-1 supports USB2.0 HS/FS/LS, and contains: • One high-speed OTG-capable module with integrated HS USB PHY • One high-speed Host module with integrated HS USB PHY WDOG-1 Watch Dog Timer Peripherals The Watchdog (WDOG) timer module protects against system failures by providing a method of escaping from unexpected events or programming errors. The WDOG Timer supports two comparison points during each counting period. Each of the comparison points is configurable to invoke an interrupt to the ARM core, and a second point invokes an external event on the WDOG line. XTALOSC Crystal Oscillator I/F Clocking The XTALOSC module combined with an external 24 MHz crystal with load capacitors implements a crystal oscillator. USB-OH-1 i.MX50 Applications Processors for Consumer Products, Rev. 7 16 Freescale Semiconductor Modules List 3.1 Special Signal Considerations Table 5 lists special signal considerations for the i.MX50. The signal names are listed in alphabetical order. The package contact assignments are found in Section 5, “Package Information and Contact Assignments.” The signal descriptions are defined in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM). Table 5. Special Signal Considerations Signal Name Remarks BOOT_MODE0, BOOT_MODE1 These two input pins are sampled out of reset and set the boot mode. For Internal boot, they should be set to 00. For Internal Fuse Only boot, they should be set to 10. For USB downloader, they should be set to 11. The BOOTMODE pins are in the NVCC_RESET domain and include an internal 100K pull-up resistor at start-up. BOOT_CONFIG1[7:0], BOOT_CONFIG2[7:0], BOOT_CONFIG3[7:0] These 24 pins are the GPIO boot override pins and may be driven at power up to select the boot mode. They are sampled 4 x CKIL clock cycles after POR is de-asserted. Consult the “System Boot” chapter of the Reference Manual for more details. Note that these are not dedicated pins: the BOOT_CONFIG pins appear over 24 pins of the EIM interface. BT_LPB_FREQ[1:0] If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the BT_LPB_FREQ[1:0] pins will be sampled to determine the ARM core frequency. Consult the “System Boot” chapter of the Reference Manual for more details. Note that these are not dedicated pins: BT_LPB_FREQ0 appears on SSI_TXFS and BT_LPB_FREQ1 appears on SSI_TXC. CHGR_DET_B This is the USB Charger Detect pin. It is an open drain output pin that expects a 100 K pull-up. This pin is asserted low when a USB charger is detected on the OTG PHY DP and DM. This detection occurs with the application of VBUS. This pin is a raw sensor output and care must be taken to follow the system timings outlined in the USB charger specification Rev 1.1. The maximum current leakage at this pin is 8.5 μA. This pin can be controlled by software control as well. If not used, this pin should be tied to ground or left floating. CKIH This is an input to the CAMPs (Clock Amplifiers), which include on-chip AC-coupling precluding the need for external coupling capacitors. The CAMPs are enabled by default, but the main clocks feeding the on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a low jitter external oscillators to feed CKIH (while not required) can be an advantage if low jitter or special frequency clock sources are required by modules sourced by CKIH. See CCM chapter in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for details on the respective clock trees. After initialization, the CAMPs may be disabled if not used by programming the CCR CAMPx_EN field. If disabled, the on-chip CAMP output is low and the input is irrelevant. CKIH is on the NVCC_JTAG power domain, so the input clock amplitude should not exceed NVCC_JTAG. If unused, the user should tie CKIH to GND for best practice. CKIL/ECKIL The user must tie a fundamental mode 32.768 K crystal across ECKIL and CKIL. The target ESR should be 50 K or less. The bias resistor for the amplifier is integrated and approximately 14 MΩ. The target load capacitance for the crystal is approximately 10 pF. The load capacitors on the board should be slightly less than double this value after taking parasitics into account. While driving in an external 32 KHz signal into ECKIL, CKIL should be left floating so that it biases. A differential amplifier senses these two pins to propagate the clock inside the i.MX508. Care must be taken to minimize external leakages on ECKIL and CKIL. If they are significant to the 14 MΩ feedback or 1 μA, then loss of oscillation margin or cessation of oscillation may result. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 17 Modules List Table 5. Special Signal Considerations (continued) Signal Name Remarks DRAM_OPEN, DRAM_OPENFB (for 416 MAPBGA and 400 MAPBGA) These pins are the echo gating output and feedback pins used by the DRAM PHY to bound a window around the DQS transition. For an application using a single DRAM device, these pins should be routed so that the trace length (DRAM_OPEN + DRAM_OPENFB) = trace length (DRAM_SDCLK0 + DRAM_SDQS0). For an application using two DRAM devices, they should be routed so that the trace length (DRAM_OPEN + DRAM_OPENFB) = trace length (AVG(DRAM_SDCLK0+DRAM_SDCLK1) + AVG (DRAM_SDQS0_to_Device0 + DRAM_SDQS0_to_Device1)). This connection is required for LPDDR1, LPDDR2, and DDR2. For the i.MX50 PoP package, these signals are connected on the substrate. DRAM_SDODT0 (for 416 MAPBGA and 400 MAPBGA), DRAM_SDODT1 (for 416 MAPBGA only) These pins are the On-die termination outputs from the i.MX50. For DDR2, these pins should be connected to the DDR2 DRAM ODT pins. For LPDDR1 and LPDDR2, these pins should be left floating. Note that both SDODT pins are removed on the 416 PoPBGA package, and only SDODT0 exists on the 400 MAPBGA package. DRAM_CALIBRATION This pin is the ZQ calibration used to calibrate DRAM Ron and ODT. For LPDDR2, this pin should be connected to ground through a 240 Ω 1% resistor. For DDR2 and LPDDR1, this pin should be connected to ground through a 300 Ω 1% resistor. JTAG_MOD This input has an internal 100K pull-up, by default. Note that JTAG_MOD is referenced as SJC_MOD in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) - both names refer to the same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 kΩ) is allowed. If JTAG port is not needed, the internal pull-up can be disabled in order to reduce supply current to the pin. JTAG_TCK This input has an internal 100K pull-down. This pin is in the NVCC_JTAG domain. JTAG_TDI This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain. JTAG_TDO This is a 3-state output with an internal gate keeper enable to prevent a floating condition. An external pull-up or pull-down resistor on JTAG_TDO is detrimental and should be avoided. This pin is in the NVCC_JTAG domain. JTAG_TMS This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain. JTAG_TRSTB This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain. NC These signals are No Connect (NC) and should be floated by the user. LOW_BATT_GPIO If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the i.MX50 will boot up at a lower ARM clock frequency to reduce system power. The actual ARM clock frequency used when LOW_BATT_GPIO is asserted is determined by the BT_LPB_FREQ[1:0] pins (220 MHz to 55.3 MHz). The polarity of the LOW_BATT_GPIO is active high by default, but may be set to active low by setting the LOW_BATT_GPIO_LEVEL OTP bit. See the “System Boot” chapter of the Reference Manual for more details. Note that this is not a dedicated pin: LOW_BATT_GPIO appears on the UART4_TXD pin. PMIC_STBY_REQ This output may be driven high when the i.MX50 enters the STOP mode to notify the PMIC to enter its low power standby state. This output is in the NVCC_SRTC domain. PMIC_ON_REQ This output from the i.MX50 can instruct the PMIC to turn on when the i.MX50 only has NVCC_SRTC power. This may be useful for an alarm application, as it allows the i.MX50 to turn off all blocks except for the RTC and then power on again at a specified time. This output is in the NVCC_SRTC domain. i.MX50 Applications Processors for Consumer Products, Rev. 7 18 Freescale Semiconductor Modules List Table 5. Special Signal Considerations (continued) Signal Name Remarks PMIC_RDY This input may be used by a PMIC to signal to the i.MX50 that the PMIC supply outputs are at operating levels when resuming from STOP mode. The PMIC_RDY input is pin muxed on ALT3 of the I2C3_SCL pin and is in the NVCC_MISC domain. POP_EMMC_RST (416 PoPBGA Only) This pin is the PoP eMMC 4.4 Reset pin. The customer may connect this on their PCB to any free GPIO, or just leave floating for non-4.4 eMMC. This pin does not connect to the i.MX50 die. POP_LPDDR2_ZQ0/ZQ1 (416 PoPBGA Only) These pins connect to the PoP LPDDR2 DRAM ZQ pins and should be connected on the customer PCB to a 240 Ω 1% resistor to ground if used. These pins do not connect to the i.MX50 die. POP_LPDDR2_1.8V (416 PoPBGA Only) These pins are the 1.8 V supply for the PoP LPDDR2 DRAM. These pins do not connect to the i.MX50 die. POP_NAND_VCC (416 PoPBGA Only) This is the 3.3V I/O and memory supply for the PoP eMMC. Note that most eMMC can operate with a 1.8V I/O or a 3.3V I/O voltage. However, because we tied the eMMC memory and I/O domains together, you can't use the 1.8 V I/O option for the PoP eMMC, only 3.3 V I/O. POR_B This POWER-ON RESET input is a cold reset negative logic input that resets all modules and logic in the IC. The POR_B pin should have an external 68 K pull-up to NVCC_RESET and a 1 μF capacitor to ground. Note: The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. RESET_IN_B This warm reset negative logic input resets all modules and logic except for the following: • Test logic (JTAG, IOMUXC, DAP) • SRTC • Cold reset logic of WDOG—Some WDOG logic is only reset by POR_B. See WDOG chapter in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for details. SSI_EXT1_CLK, SSI_EXT2_CLK The SSI_EXT1_CLK and SSI_EXT2_CLK outputs are recommended for generating a clock output from the i.MX50. Use of the CKO1 and CKO2 clock outputs is not recommended, as the large number of combinational logic muxes on those signals will impact jitter and duty-cycle. Note that these two clock outputs do not have dedicated pins: SSI_EXT1_CLK is IOMUX ALT3 on the OWIRE pin, and SSI_EXT2_CLK is IOMUX ALT3 of the EPITO pin. TEST_MODE TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip pull-down device. The user must either float this signal or tie it to GND. USB_H1_GPANAIO, USB_OTG_GPANAIO These signals are reserved for Freescale manufacturing use only. Users should float these outputs. USB_H1_RREFEXT, USB_OTG_RREFEXT These signals determine the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1% resistor to GND is required. This resistor should be connected through a short (low impedance connection) and placed away from other noisy regions. If USB_H1 is not used, the H1 RREFEXT resistor may be eliminated and the pin left floating. If USB_OTG is not used, the OTG RREFEXT resistor may be eliminated and the pin left floating. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 19 Electrical Characteristics Table 5. Special Signal Considerations (continued) Signal Name Remarks USB_H1_VBUS, USB_OTG_VBUS These inputs are used by the i.MX50 to detect the presence and level of USB 5 V. If either VBUS input pin is connected to an external USB connector, there is a possibility that a fast 5 V edge rate during a cable attach could trigger the VBUS input ESD protection, which could result in damage to the i.MX50 silicon. To prevent this, the system should use some circuitry to prevent the 5 V edge rate from exceeding 5.25 V / 1 μs. Freescale recommends the use of a low pass filter consisting of 100 Ω resistor in series and a 1 μF capacitor close to the i.MX50 pin. In the case when the USB interface is connected on an on-board USB device (for example, 3G modem), the corresponding USB_VBUS pin may be left floating. VREF This pin is the DRAM MC reference voltage input. For LPDDR2 and DDR2, this pin should be connected to ½ of NVCC_EMI_DRAM. For LPDDR1, this pin should be left floating. The user may generate VREF using a precision external resistor divider. Use a 1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a closely-mounted 0.1 µF capacitor. WDOG_B This output can be used to reset the system PMIC when the i.MX50 processor is locked up. This output is in the NVCC_MISC domain. WDOG_RST_B_DEB This output may be used to drive out the internal system reset signal to the system reset controller. This is only intended for debug purposes. XTAL/EXTAL These pins are the 24 MHz crystal driver as well as the external 24 MHz clock input. If using these pins to directly drive a 24 MHz crystal: • The user should tie a 24 MHz fundamental-mode crystal across XTAL and EXTAL. • The crystal must be rated for a maximum drive level of 100 μW or higher. • The recommended crystal ESR (equivalent series resistance) is 80 Ω or less. If using these pins as a clock input from an external 24 MHz oscillator: • The crystal may be eliminated and EXTAL driven directly driven by the external oscillator. The clock signal level on EXTAL must swing from NVCC_SRTC to GND. • In this configuration, the XTAL pin must be floated and the COSC_EN bit (bit 12 in the CCR register in the Clock Control Module) must be cleared to put the on-chip oscillator circuit in bypass mode which allows EXTAL to be externally driven. • Note there are strict jitter requirements if using an external oscillator in a USB application: < 50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY. 4 Electrical Characteristics This section provides the device and module-level electrical characteristics of the i.MX50 processor. NOTE These electrical specifications are preliminary. These specifications are not fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications are published after thorough characterization and device qualifications have been completed. i.MX50 Applications Processors for Consumer Products, Rev. 7 20 Freescale Semiconductor Electrical Characteristics 4.1 Chip-Level Conditions This section provides the chip-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections. Table 6. i.MX50 Chip-Level Conditions For these characteristics, see Topic appears … Absolute Maximum Ratings on page 21 13 x 13 mm MAPBGA Package Thermal Resistance Data on page 22 13 x 13 mm PoPBGA Package Thermal Resistance Data on page 23 17 x 17 mm MAPBGA Package Thermal Resistance Data on page 23 Operating Ranges on page 24 Operating Frequencies on page 26 Supply Current on page 26 4.1.1 Absolute Maximum Ratings CAUTION Stresses beyond those listed under Table 7 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Table 11 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 7. Absolute Maximum Ratings Parameter Description Symbol Min Max Unit VCC –0.3 1.5 V ARM core supply voltage VDDGP –0.3 1.35 V Bandgap and 480 MHz PLL supply VDD3P0 –0.5 3.6 V PLL digital supplies VDD1P2 –0.3 1.35 V PLL analog supplies VDD1P8 –0.3 2.25 V Efuse, 24 MHz oscillator, 32 kHz oscillator mux supply VDD2P5 –0.5 2.85 V VDDA/VDDAL1 –0.5 1.35 V Supply voltage (HVIO) Supplies denoted as I/O supply –0.5 3.6 V Supply voltage (GPIO, LVIO) Supplies denoted as I/O supply –0.5 3.3 Peripheral core supply voltage Memory array supply Input/output voltage range Vin/Vout USB VBUS VBUS DC Transient (t= 200 MHz tIS 0.5 tCK - 1.3 — ns DDR7 Address output hold time CK >= 200 MHz tIH 0.5 tCK - 1.3 — ns DDR6 CK < 200 MHz Address output setup time tIS 1 — ns DDR7 CK < 200 MHz Address output hold time tIH 1 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 70 Freescale Semiconductor Electrical Characteristics NOTE DDR6 and DDR7 can be adjusted by the parameter -DLL_WR_DELAY-; The ideal case is that SDCLK is center aligned to the DRAM_A[9:0] data valid window; For this table, HW_DRAM_PHY23[14:8] (DLL_WR_DELAY) = 0x10; 4.8.3 DRAM Data Output Timing The DRAM data output timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2. DRAM_SDCLK_B DRAM_SDCLK DDR10 DDR11 DDR12 DRAM_SDQS_B DRAM_SDQS DDR13 DRAM_D & DRAM_DQM DDR14 d0 d1 d2 d3 DDR15 DDR16 Figure 30. DRAM Data Output Timing Table 47. DDR Output AC Timing ID Description Symbol Min Max Unit tDQSS -0.3 0.3 ns DDR10 Positive DQS latching edge to associated CK edge DDR11 DQS falling edge from CK rising edge—hold time tDSH 0.5 tCK - 0.3 0.5 tCK + 0.3 ns DDR12 DQS falling edge to CK rising edge—setup time tDSS 0.5 tCK - 0.3 0.5 tCK + 0.3 ns DDR13 DQS output high pulse width tDQSH 0.48 tCK 0.52 tCK ns DDR14 DQS output low pulse width tDQSL 0.48 tCK 0.52 tCK ns tDS 0.5 tCK - 1.3 — ns DDR15 CK >= 200 MHz DQ & DQM output setup time relative to DQS i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 71 Electrical Characteristics Table 47. DDR Output AC Timing ID Description Symbol Min Max Unit DDR16 CK >= 200 MHz DQ & DQM output hold time relative to DQS tDH 0.5 tCK - 1.3 — ns DDR15 CK < 200 MHz DQ & DQM output setup time relative to DQS tDS 1 — ns DDR16 CK < 200 MHz DQ & DQM output hold time relative to DQS tDH 1 — ns NOTE The DDR15,16 could be adjusted by the parameter “DLL_WR_DELAY”; The ideal case is that SDQS is center aligned to the DRAM_D data valid window; For this table, HW_DRAM_PHY15[14:8] (DLL_WR_DELAY) = 0x10; 4.8.4 DRAM Data Input Timing DRAM Data input timing is defined for all DDR types: DDR2, LPDDR1, and LPDDR2. DRAM_SDCLK_B DRAM_SDCLK DDR20 DRAM_SDQS_B DRAM_SDQS DDR22 DDR21 DRAM_D d0 d1 d2 d3 Figure 31. DRAM Data Input Timing Table 48. DDR2 Input AC Timing ID DDR20 Description Positive DQS latching edge to associated CK edge Symbol Min Max Unit tDQSCK -0.5 tCK — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 72 Freescale Semiconductor Electrical Characteristics Table 48. DDR2 Input AC Timing ID Description DDR21 DQS to DQ input skew DDR22 DQS to DQ input hold time Symbol Min Max Unit tDQSQ — 0.65 ns tQH 0.45 tCK -0.85 — ns NOTE The timing parameter DDR20(tDQSCK) is not strictly required by this DRAM MC design. 4.9 External Peripheral Interfaces The following sections provide information on external peripheral interfaces. 4.9.1 AUDMUX Timing Parameters The AUDMUX provides programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. 4.9.2 CSPI and eCSPI Timing Parameters This section describes the timing parameters of the CSPI and eCSPI modules. The CSPI and eCSPI have separate timing parameters for master and slave modes. The nomenclature used with the CSPI/eCSPI modules and the respective routing of these signals is shown in Table 49. Table 49. CSPI Nomenclature and Routing Module I/O Access eCSPI1 GPIO, KPP, DISP0_DAT, CSI0_DAT, and EIM_D through IOMUX eCSPI2 DISP0_DAT, CSI0_DAT, and EIM through IOMUX CSPI DISP0_DAT, EIM_A/D, SD1, and SD2 through IOMUX i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 73 Electrical Characteristics 4.9.2.1 CSPI Master Mode Timing Figure 32 depicts the timing of CSPI in master mode and Table 50 lists the CSPI master mode timing characteristics. CSPIx_DRYN1 CS11 CSPIx_CS_x CS1 CS2 CS3 CS5 CS6 CS4 CSPIx_CLK CS7 CS8 CS3 CS2 CSPIx_DO CS9 CS10 CSPIx_DI Figure 32. CSPI Master Mode Timing Diagram Table 50. CSPI Master Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 CSPIx_CLK Cycle Time tclk 60 — ns CS2 CSPIx_CLK High or Low Time tSW 6 — ns CS3 CSPIx_CLK Rise or Fall tRISE/FALL — — ns CS4 CSPIx_CS_x pulse width tCSLH 15 — ns CS5 CSPIx_CS_x Lead Time (CS setup time) tSCS 5 — ns CS6 CSPIx_CS_x Lag Time (CS hold time) tHCS 5 — ns CS7 CSPIx_DO Setup Time tSmosi 5 — ns CS8 CSPIx_DO Hold Time tHmosi 5 — ns CS9 CSPIx_DI Setup Time tSmiso 5 — ns CS10 CSPIx_DI Hold Time tHmiso 5 — ns CS11 CSPIx_DRYN Setup Time tSDRY 5 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 74 Freescale Semiconductor Electrical Characteristics 4.9.2.2 CSPI Slave Mode Timing Figure 33 depicts the timing of CSPI in slave mode. Table 51 lists the CSPI slave mode timing characteristics. CSPIx_CS_x CS1 CS2 CS3 CS5 CS6 CS4 CSPIx_CLK CS9CS10 CS3 CS2 CSPIx_DI CS7 CS8 CSPIx_DO Figure 33. CSPI Slave Mode Timing Diagram Table 51. CSPI Slave Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 CSPIx_CLK Cycle Time tclk 60 — ns CS2 CSPIx_CLK High or Low Time tSW 15 — ns CS3 CSPIx_CLK Rise or Fall tRISE/FALL — — ns CS4 CSPIx_CS_x pulse width tCSLH 30 — ns CS5 CSPIx_CS_x Lead Time (CS setup time) tSCS 5 — ns CS6 CSPIx_CS_x Lag Time (CS hold time) tHCS 5 — ns CS7 CSPIx_DO Setup Time tSmosi 5 — ns CS8 CSPIx_DO Hold Time tHmosi 5 — ns CS9 CSPIx_DI Setup Time tSmiso 5 — ns CS10 CSPIx_DI Hold Time tHmiso 5 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 75 Electrical Characteristics 4.9.2.3 eCSPI Master Mode Timing Figure 34 depicts the timing of eCSPI in master mode and Table 52 lists the eCSPI master mode timing characteristics. eCSPIx_DRYN1 CS11 eCSPIx_CS_x CS1 CS2 CS3 CS5 CS6 CS4 eCSPIx_CLK CS7 CS8 CS3 CS2 eCSPIx_DO CS9 CS10 eCSPIx_DI Figure 34. eCSPI Master Mode Timing Diagram Table 52. eCSPI Master Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 eCSPIx_CLK Cycle Time–Read eCSPIx_CLK Cycle Time–Write tclk 60 15 — ns CS2 eCSPIx_CLK High or Low Time tSW 6 — ns CS3 eCSPIx_CLK Rise or Fall tRISE/FALL — — ns CS4 eCSPIx_CS_x pulse width tCSLH 15 — ns CS5 eCSPIx_CS_x Lead Time (CS setup time) tSCS 5 — ns CS6 eCSPIx_CS_x Lag Time (CS hold time) tHCS 5 — ns CS7 eCSPIx_DO Setup Time tSmosi 5 — ns CS8 eCSPIx_DO Hold Time tHmosi 5 — ns CS9 eCSPIx_DI Setup Time tSmiso 5 — ns CS10 eCSPIx_DI Hold Time tHmiso 5 — ns CS11 eCSPIx_DRYN Setup Time tSDRY 5 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 76 Freescale Semiconductor Electrical Characteristics 4.9.2.4 eCSPI Slave Mode Timing Figure 35 depicts the timing of eCSPI in slave mode and Table 53 lists the eCSPI slave mode timing characteristics. eCSPIx_CS_x CS1 CS2 CS3 CS5 CS6 CS4 eCSPIx_CLK CS9CS10 CS3 CS2 eCSPIx_DI CS7 CS8 eCSPIx_DO Figure 35. eCSPI Slave Mode Timing Diagram Table 53. eCSPI Slave Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 eCSPIx_CLK Cycle Time–Read eCSPIx_CLK Cycle Time–Write tclk 60 15 — ns CS2 eCSPIx_CLK High or Low Time tSW 6 — ns CS3 eCSPIx_CLK Rise or Fall tRISE/FALL — — ns CS4 eCSPIx_CS_x pulse width tCSLH 15 — ns CS5 eCSPIx_CS_x Lead Time (CS setup time) tSCS 5 — ns CS6 eCSPIx_CS_x Lag Time (CS hold time) tHCS 5 — ns CS7 eCSPIx_DO Setup Time tSmosi 5 — ns CS8 eCSPIx_DO Hold Time tHmosi 5 — ns CS9 eCSPIx_DI Setup Time tSmiso 5 — ns CS10 eCSPIx_DI Hold Time tHmiso 5 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 77 Electrical Characteristics 4.9.3 Enhanced Secured Digital Host Controller (eSDHCv2/v3) and uSDHC AC Timing This section describes the electrical information of the eSDHCv2/v3 and the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing. 4.9.3.1 SD/eMMC4.3 (Single Data Rate) eSDHCv3 and uSDHC AC Timing Figure 36 depicts the timing of SD/eMMC4.3, and Table 54 lists the SD/eMMC4.3 timing characteristics. SD4 SD2 SD1 SD5 SCK SD3 CMD DAT0 DAT1 output from eSDHCv2 to card ...... DAT7 SD6 SD7 SD8 CMD DAT0 DAT1 input from card to eSDHCv2 ...... DAT7 Figure 36. SD/eMMC4.3 Timing Table 54. SD/eMMC4.3 Interface Timing Specification ID Parameter Symbols Min Max Unit fPP1 0 400 kHz Clock Frequency (SD/SDIO Full Speed/High Speed) fPP 2 0 25/50 MHz Clock Frequency (MMC Full Speed/High Speed) fPP3 0 20/52 MHz Clock Frequency (Identification Mode) fOD 100 400 kHz SD2 Clock Low Time tWL 7 — ns SD3 Clock High Time tWH 7 — ns SD4 Clock Rise Time tTLH — 3 ns SD5 Clock Fall Time tTHL — 3 ns Card Input Clock SD1 Clock Frequency (Low Speed) i.MX50 Applications Processors for Consumer Products, Rev. 7 78 Freescale Semiconductor Electrical Characteristics Table 54. SD/eMMC4.3 Interface Timing Specification (continued) ID Parameter Symbols Min Max Unit 2 ns eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) SD6 eSDHC Output Delay tOD –2 eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) SD7 eSDHC Input Setup Time tISU 2.5 — ns SD8 eSDHC Input Hold Time4 tIH 2.5 — ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock frequency can be any value between 0–50 MHz. 3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 2 4.9.3.2 eMMC4.4 (Dual Data Rate) eSDHCv3 and uSDHC AC Timing Figure 37 depicts the timing of eMMC4.4, and Table 55 lists the eMMC4.4 timing characteristics. Be aware that only DAT0-7 is sampled on both edges of clock (not applicable to CMD). SD1 SCK SD2 DAT0 DAT1 output from eSDHCv3 to card ...... DAT7 SD2 ...... SD3 SD4 DAT0 DAT1 input from card to eSDHCv3 ...... DAT7 ...... Figure 37. eMMC4.4 Timing Table 55. eMMC4.4 Interface Timing Specification Parameter ID Symbols Min Max Unit 0 52 MHz Card Input Clock SD1 Clock Frequency (MMC Full Speed/High Speed) fPP eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 79 Electrical Characteristics Table 55. eMMC4.4 Interface Timing Specification (continued) Parameter ID SD2 eSDHC Output Delay Symbols Min Max Unit tOD –5 5 ns eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) SD3 eSDHC Input Setup Time tISU 2.5 — ns SD4 eSDHC Input Hold Time tIH 1.5 — ns 4.9.4 FEC AC Timing Parameters This section describes the AC timing specifications of the FEC. The i.MX50 FEC supports 10/100 Mbps RMII with MII serial management interface. The RMII and serial management signals are compatible with transceivers operating at a voltage of 3.3 V. 4.9.4.1 RMII Async Inputs Signal Timing (FEC_COL) Table 56 lists RMII asynchronous inputs signal timing information. Figure 38 shows MII asynchronous input timings listed in Table 56. Table 56. RMII Async Inputs Signal Timing Num Characteristics Min Max Unit M9 FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period . FEC_COL M9 Figure 38. MII Async Inputs Timing Diagram 4.9.4.2 RMII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 57 lists RMII serial management channel timings. Figure 39 shows RMII serial management channel timings listed in Table 57. The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 RMII specification. However, the FEC can function correctly with a maximum MDC frequency of 15 MHz. Table 57. RMII Transmit Signal Timing ID Characteristics Min Max Unit M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) 0 — ns M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) — 5 ns M12 FEC_MDIO (input) to FEC_MDC rising edge setup 18 — ns M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 80 Freescale Semiconductor Electrical Characteristics Table 57. RMII Transmit Signal Timing (continued) ID Characteristics Min Max Unit M14 FEC_MDC pulse width high 40% 60% FEC_MDC period M15 FEC_MDC pulse width low 40% 60% FEC_MDC period M14 M15 FEC_MDC (output) M10 FEC_MDIO (output) M11 FEC_MDIO (input) M12 M13 Figure 39. RMII Serial Management Channel Timing Diagram 4.9.4.3 RMII Mode Timing In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ± 50 ppm continuous reference clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER. The RMII mode timings are shown in Table 58 and Figure 40. Table 58. RMII Signal Timing No. Characteristics Min Max Unit M16 REF_CLK(FEC_TX_CLK) pulse width high 35% 65% REF_CLK period M17 REF_CLK(FEC_TX_CLK) pulse width low 35% 65% REF_CLK period M18 REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid 2 — ns M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid — 16 ns M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup 4 — ns M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold 2 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 81 Electrical Characteristics M16 M17 REF_CLK (input) M18 FEC_TXD[1:0] (output) FEC_TX_EN M19 CRS_DV (input) FEC_RXD[1:0] FEC_RX_ER M20 M21 Figure 40. RMII Mode Signal Timing Diagram 4.9.5 I2C Module Timing Parameters This section describes the timing parameters of the I2C module. Figure 41 depicts the timing of I2C module, and Table 59 lists the I2C module timing characteristics. I2CLK IC11 IC10 I2DAT IC2 START IC7 IC4 IC8 IC10 IC11 IC6 IC9 IC3 STOP START START IC5 IC1 Figure 41. I2C Bus Timing Table 59. I2C Module Timing Parameters ID Parameter Standard Mode Fast Mode Supply Voltage = Supply Voltage = 1.65 V–1.95 V, 2.7 V–3.3 V 2.7 V–3.3 V Unit Min Max Min Max IC1 I2CLK cycle time 10 — 2.5 — µs IC2 Hold time (repeated) START condition 4.0 — 0.6 — µs IC3 Set-up time for STOP condition 4.0 — 0.6 — µs i.MX50 Applications Processors for Consumer Products, Rev. 7 82 Freescale Semiconductor Electrical Characteristics Table 59. I2C Module Timing Parameters (continued) ID Standard Mode Fast Mode Supply Voltage = Supply Voltage = 1.65 V–1.95 V, 2.7 V–3.3 V 2.7 V–3.3 V Unit Parameter Min Max Min Max IC4 Data hold time 01 3.452 01 0.92 µs IC5 HIGH Period of I2CLK Clock 4.0 — 0.6 — µs IC6 LOW Period of the I2CLK Clock 4.7 — 1.3 — µs IC7 Set-up time for a repeated START condition 4.7 — 0.6 — µs IC8 Data set-up time 250 — 1003 — ns IC9 Bus free time between a STOP and START condition 4.7 — 1.3 — µs 0.1Cb4 300 ns IC10 Rise time of both I2DAT and I2CLK signals — 1000 20 + IC11 Fall time of both I2DAT and I2CLK signals — 300 20 + 0.1Cb4 300 ns IC12 Capacitive load for each bus line (Cb) — 400 — 400 pF 1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal. 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 C = total capacitance of one bus line in pF. b 4.9.6 One-Wire (OWIRE) Timing Parameters Figure 42 depicts the RPP timing, and Table 60 lists the RPP timing parameters. One-WIRE Tx “Reset Pulse” One Wire Device Tx “Presence Pulse” OW2 One-Wire bus (BATT_LINE) OW3 OW1 tR OW4 Figure 42. Reset and Presence Pulses (RPP) Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 83 Electrical Characteristics Table 60. RPP Sequence Delay Comparisons Timing Parameters ID Parameters Symbol Min Typ Max Unit OW1 Reset Time Low tRSTL 480 511 —1 µs OW2 Presence Detect High tPDH 15 — 60 µs OW3 Presence Detect Low tPDL 60 — 240 µs OW4 Reset Time High (includes recovery time) tRSTH 480 512 — µs 1 In order not to mask signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs. Figure 43 depicts Write 0 Sequence timing, and Table 61 lists the timing parameters. OW6 tREC One-Wire bus (BATT_LINE) OW5 Figure 43. Write 0 Sequence Timing Diagram Table 61. WR0 Sequence Timing Parameters ID Parameter Symbol Min Typ Max Unit OW5 Write 0 Low Time tLOW0 60 100 120 µs OW6 Transmission Time Slot tSLOT OW5 117 120 µs — Recovery time tREC 1 — — µs Figure 44 depicts Write 1 Sequence timing, Figure 45 depicts the Read Sequence timing, and Table 62 lists the timing parameters. OW8 One-Wire bus (BATT_LINE) OW7 Figure 44. Write 1 Sequence Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev. 7 84 Freescale Semiconductor Electrical Characteristics OW8 One-Wire bus (BATT_LINE) tSU OW11 OW9 OW10 Figure 45. Read Sequence Timing Diagram Table 62. WR1 /RD Timing Parameters ID Parameter Symbol Min Typ Max Unit OW7 Write 1 Low Time tLOW1 1 5 15 µs OW8 Transmission Time Slot tSLOT 60 117 120 µs — Read Data Setup tSU — — 1 µs OW9 Read Low Time tLOWR 1 5 15 µs OW10 Read Data Valid tRDV — 15 — µs OW11 Release Time tRELEASE 0 — 45 µs 4.9.7 Pulse Width Modulator (PWM) Timing Parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Figure 46 depicts the timing of the PWM, and Table 63 lists the PWM timing parameters. 1 2a 3b System Clock 2b 3a 4b 4a PWM Output Figure 46. PWM Timing i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 85 Electrical Characteristics Table 63. PWM Output Timing Parameter Ref. No. Parameter Min Max Unit 0 ipg_clk MHz 1 System CLK frequency1 2a Clock high time 12.29 — ns 2b Clock low time 9.91 — ns 3a Clock fall time — 0.5 ns 3b Clock rise time — 0.5 ns 4a Output delay time — 9.37 ns 4b Output setup time 8.71 — ns 1 CL of PWMO = 30 pF 4.9.8 Secure JTAG Controller (SJC) Timing Parameters Figure 47 depicts the SJC test clock input timing. Figure 48 depicts the SJC boundary scan timing. Figure 49 depicts the SJC test access port. Figure 50 depicts the TRST timing. The signal parameters are listed in Table 64. SJ1 SJ2 TCK (Input) VM VIH SJ2 VM VIL SJ3 SJ3 Figure 47. Test Clock Input Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev. 7 86 Freescale Semiconductor Electrical Characteristics TCK (Input) VIH VIL SJ5 SJ4 Data Inputs Input Data Valid SJ6 Data Outputs Output Data Valid SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Figure 48. Boundary Scan (JTAG) Timing Diagram TCK (Input) VIH VIL SJ8 TDI TMS (Input) SJ9 Input Data Valid SJ10 TDO (Output) Output Data Valid SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Figure 49. Test Access Port Timing Diagram i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 87 Electrical Characteristics TCK (Input) SJ13 TRST (Input) SJ12 Figure 50. TRST Timing Diagram Table 64. JTAG Timing All Frequencies Parameter1,2 ID Unit Min Max 0.001 22 MHz 45 — ns 22.5 — ns SJ0 TCK frequency of operation 1/(3•TDC)1 SJ1 TCK cycle time in crystal mode SJ2 TCK clock pulse width measured at VM2 SJ3 TCK rise and fall times — 3 ns SJ4 Boundary scan input data set-up time 5 — ns SJ5 Boundary scan input data hold time 24 — ns SJ6 TCK low to output data valid — 40 ns SJ7 TCK low to output high impedance — 40 ns SJ8 TMS, TDI data set-up time 5 — ns SJ9 TMS, TDI data hold time 25 — ns SJ10 TCK low to TDO data valid — 44 ns SJ11 TCK low to TDO high impedance — 44 ns SJ12 TRST assert time 100 — ns SJ13 TRST set-up time to TCK low 40 — ns 1 2 TDC = target frequency of SJC VM = mid-point voltage i.MX50 Applications Processors for Consumer Products, Rev. 7 88 Freescale Semiconductor Electrical Characteristics 4.9.9 SSI Timing Parameters This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces are summarized in Table 65. Table 65. AUDMUX Port Allocation Port Signal Nomenclature Type and Access AUDMUX port 1 SSI 1 Internal AUDMUX port 2 SSI 2 Internal AUDMUX port 3 AUD3 External— AUD3 I/O AUDMUX port 4 AUD4 External—EIM or CSPI1 I/O through IOMUX AUDMUX port 5 AUD5 External—EIM or SD1 I/O through IOMUX AUDMUX port 6 AUD6 External—EIM or DISP2 through IOMUX • • NOTE The terms WL and BL used in the timing diagrams and tables refer to Word Length (WL) and Bit Length (BL). The SSI timing diagrams use generic signal names wherein the names used in the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 89 Electrical Characteristics 4.9.9.1 SSI Transmitter Timing with Internal Clock Figure 51 depicts the SSI transmitter internal clock timing and Table 66 lists the timing parameters for the SSI transmitter internal clock. . SS1 SS3 SS5 SS2 SS4 TXC (Output) SS8 SS6 TXFS (bl) (Output) SS10 SS12 SS14 TXFS (wl) (Output) SS15 SS16 SS18 SS17 TXD (Output) SS43 SS42 SS19 RXD (Input) Note: SRXD input in synchronous mode only Figure 51. SSI Transmitter Internal Clock Timing Diagram Table 66. SSI Transmitter Timing with Internal Clock ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6.0 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6.0 ns SS6 (Tx) CK high to FS (bl) high — 15.0 ns SS8 (Tx) CK high to FS (bl) low — 15.0 ns SS10 (Tx) CK high to FS (wl) high — 15.0 ns SS12 (Tx) CK high to FS (wl) low — 15.0 ns SS14 (Tx/Rx) Internal FS rise time — 6.0 ns SS15 (Tx/Rx) Internal FS fall time — 6.0 ns SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns i.MX50 Applications Processors for Consumer Products, Rev. 7 90 Freescale Semiconductor Electrical Characteristics Table 66. SSI Transmitter Timing with Internal Clock (continued) ID Parameter Min Max Unit SS17 (Tx) CK high to STXD high/low — 15.0 ns SS18 (Tx) CK high to STXD high impedance — 15.0 ns SS19 STXD rise/fall time — 6.0 ns Synchronous Internal Clock Operation SS42 SRXD setup before (Tx) CK falling 10.0 — ns SS43 SRXD hold after (Tx) CK falling 0.0 — ns SS52 Loading — 25.0 pF • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in both the tables and figures. All timings are on Audiomux Pads when SSI is being used for data transfer. The terms WL and BL refer to word length (WL) and bit length (BL). Tx and Rx refer to the transmit and receive sections of the SSI. For internal frame sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 91 Electrical Characteristics 4.9.9.2 SSI Receiver Timing with Internal Clock Figure 52 depicts the SSI receiver internal clock timing and Table 67 lists the timing parameters for the receiver timing with internal clock. SS1 SS3 SS5 SS4 SS2 TXC (Output) SS9 SS7 TXFS (bl) (Output) SS11 TXFS (wl) (Output) SS13 SS20 SS21 RXD (Input) SS47 SS48 SS51 SS49 SS50 RXC (Output) Figure 52. SSI Receiver Internal Clock Timing Diagram Table 67. SSI Receiver Timing with Internal Clock ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6.0 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6.0 ns SS7 (Rx) CK high to FS (bl) high — 15.0 ns SS9 (Rx) CK high to FS (bl) low — 15.0 ns SS11 (Rx) CK high to FS (wl) high — 15.0 ns SS13 (Rx) CK high to FS (wl) low — 15.0 ns SS20 SRXD setup time before (Rx) CK low 10.0 — ns SS21 SRXD hold time after (Rx) CK low 0.0 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 92 Freescale Semiconductor Electrical Characteristics Table 67. SSI Receiver Timing with Internal Clock (continued) ID Parameter Min Max Unit 15.04 — ns Oversampling Clock Operation SS47 Oversampling clock period SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.0 ns • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS as shown in both the tables and figures. All timings are on Audiomux Pads when SSI is being used for data transfer. Tx and Rx refer to the transmit and receive sections of the SSI. The terms WL and BL refer to word length (WL) and bit length (BL). For internal frame sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 93 Electrical Characteristics 4.9.9.3 SSI Transmitter Timing with External Clock Figure 53 depicts the SSI transmitter external clock timing and Table 68 lists the timing parameters for the transmitter timing with external clock. SS22 SS23 SS25 SS26 SS24 TXC (Input) SS27 SS29 TXFS (bl) (Input) SS33 SS31 TXFS (wl) (Input) SS37 SS39 SS38 TXD (Output) SS45 SS44 RXD (Input) SS46 Note: SRXD Input in Synchronous mode only Figure 53. SSI Transmitter External Clock Timing Diagram Table 68. SSI Transmitter Timing with External Clock ID Parameter Min Max Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36.0 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36.0 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS27 (Tx) CK high to FS (bl) high –10.0 15.0 ns SS29 (Tx) CK high to FS (bl) low 10.0 — ns SS31 (Tx) CK high to FS (wl) high –10.0 15.0 ns SS33 (Tx) CK high to FS (wl) low 10.0 — ns SS37 (Tx) CK high to STXD valid from high impedance — 15.0 ns SS38 (Tx) CK high to STXD high/low — 15.0 ns i.MX50 Applications Processors for Consumer Products, Rev. 7 94 Freescale Semiconductor Electrical Characteristics Table 68. SSI Transmitter Timing with External Clock (continued) ID SS39 Parameter (Tx) CK high to STXD high impedance Min Max Unit — 15.0 ns Synchronous External Clock Operation SS44 SRXD setup before (Tx) CK falling 10.0 — ns SS45 SRXD hold after (Tx) CK falling 2.0 — ns SS46 SRXD rise/fall time — 6.0 ns • • • • • NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in both the tables and figures. All timings are on Audiomux Pads when SSI is being used for data transfer. Tx and Rx refer to the transmit and receive sections of the SSI. The terms WL and BL refer to word length (WL) and bit length (BL). For internal frame sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 95 Electrical Characteristics 4.9.9.4 SSI Receiver Timing with External Clock Figure 54 depicts the SSI receiver external clock timing and Table 69 lists the timing parameters for the receiver timing with external clock. SS22 SS26 SS24 SS25 SS23 TXC (Input) SS30 SS28 TXFS (bl) (Input) SS32 SS34 SS35 TXFS (wl) (Input) SS41 SS40 SS36 RXD (Input) Figure 54. SSI Receiver External Clock Timing Diagram Table 69. SSI Receiver Timing with External Clock ID Parameter Min Max Unit 81.4 — ns External Clock Operation SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) CK clock high period 36 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS28 (Rx) CK high to FS (bl) high –10 15.0 ns SS30 (Rx) CK high to FS (bl) low 10 — ns SS32 (Rx) CK high to FS (wl) high –10 15.0 ns SS34 (Rx) CK high to FS (wl) low 10 — ns SS35 (Tx/Rx) External FS rise time — 6.0 ns SS36 (Tx/Rx) External FS fall time — 6.0 ns SS40 SRXD setup time before (Rx) CK low 10 — ns SS41 SRXD hold time after (Rx) CK low 2 — ns i.MX50 Applications Processors for Consumer Products, Rev. 7 96 Freescale Semiconductor Electrical Characteristics • • • • • 4.9.10 NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in both the tables and figures. All timings are on Audiomux Pads when SSI is being used for data transfer. Tx and Rx refer to the transmit and receive sections of the SSI. The terms WL and BL refer to word length (WL) and bit length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). UART I/O Configuration and Timing Parameters The following sections describe the UART I/O configuration and timing parameters. 4.9.10.1 UART RS-232 I/O Configuration in Different Modes Table 70 shows the UART I/O configuration based on which mode is enabled. Table 70. UART I/O Configuration vs. Mode DTE Mode DCE Mode Port Direction Description Direction Description RTS Output RTS from DTE to DCE Input RTS from DTE to DCE CTS Input CTS from DCE to DTE Output CTS from DCE to DTE TXD_MUX Input Serial data from DCE to DTE Output Serial data from DCE to DTE RXD_MUX Output Serial data from DTE to DCE Input Serial data from DTE to DCE 4.9.10.2 UART RS-232 Serial Mode Timing The following sections describe the electrical information of the UART module in the RS-232 mode. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 97 Electrical Characteristics 4.9.10.2.1 UART Transmitter Figure 55 depicts the transmit timing of UART in the RS-232 serial mode with 8 data bit/1 stop bit format. Table 71 lists the UART RS-232 serial mode transmit timing characteristics. UA1 TXD (output) Start Bit Possible Parity Bit UA1 Bit 0 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT Next Start Bit UA1 UA1 Figure 55. UART RS-232 Serial Mode Transmit Timing Diagram Table 71. RS-232 Serial Mode Transmit Timing Parameters ID UA1 1 2 Parameter Symbol Min Max Units tTbit 1/Fbaud_rate1 – Tref_clk2 1/Fbaud_rate + Tref_clk — Transmit Bit Time Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 4.9.10.2.2 UART Receiver Figure 56 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 72 lists serial mode receive timing characteristics. UA2 RXD (input) Start Bit Possible Parity Bit UA2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT Next Start Bit UA2 UA2 Figure 56. UART RS-232 Serial Mode Receive Timing Diagram Table 72. RS-232 Serial Mode Receive Timing Parameters ID Parameter Symbol Min Max Units UA2 Receive Bit Time1 tRbit 1/Fbaud_rate2 – 1/(16*Fbaud_rate) 1/Fbaud_rate + 1/(16*Fbaud_rate) — 1 The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16*Fbaud_rate). 2 F baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 4.9.10.3 UART IrDA Mode Timing The following sections give the UART transmit and receive timings in IrDA mode. i.MX50 Applications Processors for Consumer Products, Rev. 7 98 Freescale Semiconductor Electrical Characteristics 4.9.10.3.1 UART IrDA Mode Transmitter Figure 57 depicts the UART IrDA mode transmit timing with 8 data bit/1 stop bit format. Table 73 lists the transmit timing characteristics. UA3 UA4 UA3 UA3 UA3 TXD (output) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT Figure 57. UART IrDA Mode Transmit Timing Diagram Table 73. IrDA Mode Transmit Timing Parameters 1 2 ID Parameter Symbol Min Max Units UA3 Transmit Bit Time in IrDA mode tTIRbit 1/Fbaud_rate1 – Tref_clk2 1/Fbaud_rate + Tref_clk — UA4 Transmit IR Pulse Duration tTIRpulse (3/16)*(1/Fbaud_rate) – Tref_clk (3/16)*(1/Fbaud_rate) + Tref_clk — Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 4.9.10.3.2 UART IrDA Mode Receiver Figure 58 depicts the UART IrDA mode receive timing with 8 data bit/1 stop bit format. Table 74 lists the receive timing characteristics. UA5 UA6 UA5 UA5 UA5 RXD (input) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT Figure 58. UART IrDA Mode Receive Timing Diagram Table 74. IrDA Mode Receive Timing Parameters ID Parameter Symbol Min. Max. Units UA5 Receive Bit Time1 in IrDA mode tRIRbit 1/Fbaud_rate2 – 1/(16*Fbaud_rate) 1/Fbaud_rate + 1/(16*Fbaud_rate) — UA6 Receive IR Pulse Duration tRIRpulse 1.41 μs (5/16)*(1/Fbaud_rate) — 1 The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16*Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 99 Electrical Characteristics 4.9.11 USB PHY Parameters This section describes the USB OTG PHY and the USB host port PHY parameters. 4.9.11.1 USB PHY AC Parameters Table 75 lists the AC timing parameters for USB PHY. Table 75. USB PHY AC Timing Parameters Parameter Conditions Min Typ Max Unit trise 1.5Mbps 12Mbps 480Mbps 75 4 0.5 — 300 20 ns tfall 1.5Mbps 12Mbps 480Mbps 75 4 0.5 — 300 20 ns Jitter 1.5Mbps 12Mbps 480Mbps — — 10 1 0.2 ns 4.9.11.2 USB PHY Additional Electrical Parameters Table 76 lists the parameters for additional electrical characteristics for USB PHY. Table 76. Additional Electrical Characteristics for USB PHY Parameter Conditions Min Typ Max Unit –0.05 0.8 — 0.5 2.5 V Vcm DC (dc level measured at receiver connector) HS Mode LS/FS Mode Crossover Voltage LS Mode FS Mode 1.3 1.3 — 2 2 V Power supply ripple noise (analog 3.3 V) < 160 MHz –50 0 50 mV Power supply ripple noise (analog 2.5 V) < 1.2 MHz > 1.2 MHz –10 –50 0 0 10 50 mV Power supply ripple noise (Digital 1.2 V) All conditions –50 0 50 mV 4.9.11.3 USB PHY System Clocking (SYSCLK) Table 77 lists the USB PHY system clocking parameters Table 77. USB PHY System Clocking Parameters Parameter Clock deviation Rise/fall time Conditions Min Typ Max Unit Reference Clock frequency 24 MHz –150 — 150 ppm — — — 200 ps i.MX50 Applications Processors for Consumer Products, Rev. 7 100 Freescale Semiconductor Package Information and Contact Assignments Table 77. USB PHY System Clocking Parameters (continued) Parameter Conditions Min Typ Max Unit Jitter (peak-peak) 1.2 MHz 0 — 100 ps Reference Clock frequency 24 MHz 40 — 60 % Duty-cycle 4.9.11.4 USB VBUS Parameters Table 78 lists the USB VBUS input parameters. Table 78. VBUS Comparators Thresholds Parameter Conditions Min Typ Max Unit A-Device Session Valid Comparator Threshold — 0.8 1.4 2.0 V B-Device Session Valid Comparator Threshold — 0.8 1.4 4.0 V B-Device Session End Comparator Threshold — 0.2 0.45 0.8 V VBUS Valid Comparator Threshold1 — 4.4 4.6 4.75 V VBUS for CHGR_DET_B Operation — 3.0 — — V VBUS = 5.25 V — — 350 μA VBUS Input Current 1 For VBUS maximum rating, see Table 7. 5 Package Information and Contact Assignments This section includes the contact assignment information and mechanical package drawing. 5.1 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package Information This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin MAPBGA package. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 101 Package Information and Contact Assignments 5.1.1 Case 416 MAPBGA, 13 x 13 mm, 0.5 mm Pitch Package Views Figure 59 shows the top view of the 13 x 13 mm package, Figure 60 shows the bottom view (416 soldier balls) of the 13 x 13 mm package, and Figure 61 shows the side view of the 13 x 13 mm package. Figure 59. 416 MAPBGA 13x13 mm Package Top View Figure 60. 416 MAPBGA 13x13 mm Package Bottom View i.MX50 Applications Processors for Consumer Products, Rev. 7 102 Freescale Semiconductor Package Information and Contact Assignments Figure 61. 416 MAPBGA 13x13 mm Package Side View The following notes apply to Figure 59, Figure 60, and Figure 61: • Unless otherwise specified dimensions are in millimeters. • All dimensions and tolerances conform to ASME Y14.5M-1994. • Parallelism measurement shall exclude any effect of mark on top surface of package. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 103 104 NC NC DRAM_A14 DRAM_SDODT0 NC VSS F NC EPDC_VCOM0 G NC EPDC_PWRSTAT DRAM_D13 NC EPDC_PWRCTRL3 DRAM_D10 NC EPDC_PWRCTRL2 DRAM_D12 NC EPDC_PWRCTRL1 VSS NC EPDC_PWRCTRL0 NC NC EPDC_PWRCOM NC NC VDDGP DRAM_A13 NC VDDGP VSS NC PWM1 WDOG VDDGP PWM2 EPITO NC NC NC OWIRE I2C2_SDA I2C3_SDA NC I2C2_SCL I2C3_SCL E DRAM_D14 DRAM_D15 NC EPDC_BDR1 EPDC_BDR0 EPDC_SDOEZ EPDC_SDOE EPDC_D3 EPDC_D7 EPDC_D11 EPDC_D15 EPDC_SDCE1 EPDC_SDCE3 EPDC_SDCE5 EIM_CS2 EIM_DA3 EIM_DA7 EIM_DA11 EIM_DA15 EIM_LBA KEY_ROW3 NC I2C1_SDA I2C1_SCL E DRAM_SDQS3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC KEY_COL3 KEY_COL2 C D C NVCC_EMI_DRAM DRAM_SDQS3_B NVCC_EMI_DRAM NC NVCC_EMI_DRAM EPDC_VCOM1 EPDC_SDOED EPDC_SDLE EPDC_D2 EPDC_D6 EPDC_D10 EPDC_D14 EPDC_SDCE0 EPDC_SDCE2 EPDC_SDCE4 EIM_CS1 EIM_DA2 EIM_DA6 EIM_DA10 EIM_DA14 EIM_WAIT KEY_ROW2 NC KEY_ROW1 KEY_ROW0 D DRAM_D29 DRAM_D30 VSS EPDC_D0 EPDC_D4 EPDC_D8 EPDC_D12 EPDC_SDCLK EPDC_GDRL EPDC_GDCLK EPDC_SDSHR EIM_DA0 EIM_DA4 EIM_DA8 EIM_DA12 EIM_BCLK EIM_EB0 EIM_CRE EIM_RDY VSS A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B DRAM_DQM3 DRAM_D24 DRAM_D27 A VSS DRAM_D25 DRAM_D26 24 23 22 NVCC_EMI_DRAM NVCC_EMI_DRAM 21 DRAM_D28 DRAM_D31 VSS EPDC_D1 EPDC_D5 EPDC_D9 EPDC_D13 EPDC_SDCLKN EPDC_GDSP EPDC_GDOE EIM_CS0 EIM_DA1 EIM_DA5 EIM_DA9 EIM_DA13 EIM_RW EIM_EB1 EIM_OE KEY_COL1 KEY_COL0 B 5.1.2 NC F G Package Information and Contact Assignments 416 MAPBGA 13 x 13 mm, 0.5 mm Pitch Ball Map Table 79 shows the 416 MAPBGA 13 x 13 mm, 0.5 mm pitch ball map. Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor Freescale Semiconductor NC NVCC_EPDC VSS NC NC VSS VSS NC VSS DRAM_SDBA2 NC DRAM_A7 DRAM_A8 NC VDDO25 NC NVCC_EPDC VSS VSS VSS VSS VDDAL1 NC VDDA DRAM_SDWE NC DRAM_A5 DRAM_A6 NC DRAM_SDQS0 NC VDDGP VDDGP VSS VSS VSS VCC NC VSS DRAM_SDBA1 NC DRAM_CALIBRATION DRAM_A9 NC DRAM_SDQS1 NC NVCC_EPDC VSS NC NC VSS VSS NC VSS VSS NC VSS VSS NC VREF P N M L DRAM_SDQS1_B VDDGP UART4_RXD CSPI_MISO NVCC_EIM UART3_RXD CSPI_SS0 NVCC_EIM NC NC NVCC_EIM UART2_RTS CSPI_MOSI NC UART2_RXD CSPI_SCLK NC L M DRAM_SDQS0_B DRAM_SDCLK_0 DRAM_SDCLK_0_B NVCC_KEYPAD ECSPI2_MISO ECSPI2_MOSI NVCC_MISC ECSPI2_SS0 ECSPI2_SCLK ECSPI1_MISO NC NC ECSPI1_SS0 ECSPI1_MOSI SD1_D1 NC ECSPI1_SCLK SD1_CLK NC N P K VCC VCC VCC VCC VSS VSS VDDGP VDDGP VDDGP VDDGP SSI_RXFS NC SSI_TXD SSI_TXFS NC UART1_CTS UART1_TXD H DRAM_D8 NC DRAM_CAS DRAM_A11 NC J H DRAM_D9 DRAM_D11 NC DRAM_RAS DRAM_A12 NC DRAM_OPEN DRAM_OPENFB VCC NC NC NC NC NC NC NC NC VDDGP SSI_RXC NC SSI_RXD SSI_TXC NC UART1_RTS UART1_RXD J NVCC_EMI_DRAM DRAM_DQM1 NVCC_EMI_DRAM NC NVCC_EMI_DRAM DRAM_A10 NC DRAM_SDBA0 VCC NC VCC VCC VSS VSS VDDGP VDDGP NC VDDGP VDDGP NC UART4_TXD UART3_TXD NC UART2_CTS UART2_TXD K Package Information and Contact Assignments Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 105 106 SD3_D5 SD3_D7 DRAM_A2 SD3_D4 SD3_D6 DRAM_A4 Y DISP_D10 SD3_D3 AA DISP_D9 DISP_D8 DRAM_D0 DISP_D7 DISP_D6 NVCC_EMI_DRAM DISP_D5 DISP_D4 DRAM_D1 DISP_D3 DISP_D2 NVCC_EMI_DRAM DISP_D1 DISP_D0 NC USB_H1_GPANAIO VSS NC USB_H1_VBUS USB_H1_RREFEXT DRAM_A3 USB_OTG_VBUS VSS NVCC_EMI_DRAM USB_OTG_ID VDD_DCDCO JTAG_TRSTB USB_OTG_RREFEXT JTAG_TMS JTAG_TDI USB_OTG_GPANAIO NC NC GND_KEL ECKIL NGND_SRTC VDD_DCDCI CKIL NVCC_SRTC CKIH Y AA W DRAM_D3 DRAM_D2 NC DRAM_A1 DRAM_A0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND_DCDC JTAG_TCK NC PMIC_STBY_REQ PMIC_ON_REQ W V DRAM_D4 VSS NC VSS VSS NC VSS VSS DISP_D15 DISP_D14 DISP_D13 DISP_D12 DISP_D11 CHGR_DET_B NVCC_NANDF NVCC_NANDF NVCC_RESET JTAG_MOD NC SD2_CMD SD2_D4 NC SD2_D3 SD2_D2 V NC VSS VSS NC NC NC NC NC NC NC NC NVCC_UART NVCC_SD1 NC SD2_WP SD2_CD NC SD2_D1 SD2_D0 T NC DRAM_SDODT1 VDDA NC VDDAL1 VSS VSS VSS VSS NVCC_EPDC NC NVCC_SSI NVCC_SPI NC SD1_D3 SD1_D2 NC SD1_D0 SD1_CMD R U DRAM_D7 DRAM_D5 NC DRAM_CS1 T DRAM_DQM0 DRAM_D6 NC DRAM_CS0 R NVCC_EMI_DRAM NVCC_EMI_DRAM NC NVCC_EMI_DRAM DRAM_SDCKE DRAM_SDCLK_1 DRAM_SDCLK_1_B NC VSS VSS VSS VSS VSS VSS VSS NVCC_LCD NVCC_EPDC NVCC_JTAG NVCC_SD2 JTAG_TDO NC SD2_D7 SD2_D6 NC SD2_D5 SD2_CLK U Package Information and Contact Assignments Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor Package Information and Contact Assignments 5.1.3 AB AC AD DRAM_SDQS2_B VSS 24 DRAM_DQM2 DRAM_SDQS2 DRAM_D23 23 DRAM_D22 NC DRAM_D21 22 DRAM_D20 NC NVCC_EMI_DRAM 21 NVCC_EMI_DRAM NC DRAM_D19 20 DRAM_D18 NC DRAM_D17 19 DRAM_D16 NC VSS 18 VSS NC SD3_CMD 17 SD3_D2 NC SD3_CLK 16 SD3_D1 NC SD3_WP 15 SD3_D0 NC DISP_CS 14 DISP_RESET NC DISP_RD 13 DISP_RS NC NC USB_H1_VDDA33 DISP_BUSY DISP_WR 12 USB_H1_DP 11 USB_OTG_VDDA33 NC 10 USB_H1_DN NC 9 USB_H1_VDDA25_1 USB_OTG_VDDA25_1 NC USB_OTG_DP 8 USB_OTG_DN NC VDD1P8 7 GND1P8 NC VDD1P2 6 GND1P2 NC XTAL 5 EXTAL NC VDD2P5 4 GND3P0 VDD3P0 3 GND2P5 NC BOOT_MODE1 POR_B 2 TEST_MODE BOOT_MODE0 RESET_IN_B VSS 1 AD AC AB Table 79. 416 MAPBGA 13x13 mm, 0.5 mm Pitch Ball Map (continued) 416 MAPBGA 13 x 13 Power Rails Table 80. 416 MAPBGA 13x13 Ground, Power, Sense, and Reference Contact Signals Pin Name Ball Number Comments GND_DCDC W5 — NVCC_EIM L7, M7, M8 — NVCC_EMI_DRAM A21, AA21, AA23, AA24, AC21, AD21, B21, D21, — D23, D24, K21, K23, K24, R21, R23, R24 NVCC_EPDC M10, N10, P10, R10, U10 — NVCC_JTAG U9 — NVCC_KEYPAD N8 — NVCC_LCD U11 — NVCC_MISC P8 — NVCC_NANDF V9, V10 — NVCC_RESET V8 — NVCC_SD1 T7 — NVCC_SD2 U8 — NVCC_SPI R7 — i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 107 Package Information and Contact Assignments Table 80. 416 MAPBGA 13x13 Ground, Power, Sense, and Reference Contact Signals (continued) NVCC_SRTC AA1 — NVCC_SSI R8 — NVCC_UART T8 — USB_H1_VDDA25 AD9 Note that on the 416 MAPBGA package, USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the substrate. USB_H1_VDDA33 AC11 Note that on the 416 MAPBGA package, USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the substrate. USB_OTG_VDDA25 AC9 Note that on the 416 MAPBGA package, USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the substrate. USB_OTG_VDDA33 AD11 Note that on the 416 MAPBGA package, USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the substrate. VCC H14, H15, H16, H17, J17, K14, K15, K17, L15 — VDD_DCDCI Y6 — VDD_DCDCO Y5 — VDD1P2 AD6 — VDD1P8 AD7 — VDD2P5 AD4 — VDD3P0 AD3 — VDDA P17, R17 — VDDAL1 P15, R15 — VDDGP G10, G8, G9, H10, H11, H8, H9, J8, K10, K11, K7, — K8, L10, L11, L8 VDDO25 N23 VSS A1, A18, A24, AA11, AA2, AA9, AC18, AC3, AC4, — AC6, AC7, AD1, AD18, AD24, B18, G20, G21, G23, H12, H13, K12, K13, L12, L13, L14, L17, M11, M14, M15, M17, M18, M20, M21, N11, N14, N15, N17, P11, P12, P13, P14, R11, R12, R13, R14, T17, T18, U12, U13, U14, U15, U16, U17, U18, V17, V18, V20, V21, V23 — i.MX50 Applications Processors for Consumer Products, Rev. 7 108 Freescale Semiconductor Package Information and Contact Assignments 5.2 13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball grid location) for the 13 x 13 mm, 0.5 mm pitch, 416 pin PoPBGA package. 5.2.1 416 PoPBGA 13 x 13 mm Package Views Figure shows the top view of the 416 PoPBGA 13 x 13 package, Figure 63 shows the side view of the package, and Figure 64 shows the bottom view of the package. Figure 62. 416 PoPBGA 13 x 13 mm Package Top View i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 109 Package Information and Contact Assignments Figure 63. 416 PoPBGA 13 x 13 Package Side View Figure 64. 416 PoPBGA 13 x 13 mm Package Bottom View The following notes apply to Figure , Figure 63, and Figure 64: • Unless otherwise specified dimensions are in millimeters. i.MX50 Applications Processors for Consumer Products, Rev. 7 110 Freescale Semiconductor 2 3 4 5 VSS UART1_RXD UART1_TXD I2C3_SCL I2C2_SCL UART2_TXD UART2_CTS UART1_RTS UART1_CTS I2C3_SDA UART2_RXD UART2_RTS NC NC NC SD2_D0 SD2_D1 NC UART3_TXD UART4_RXD SD2_CLK SD2_D5 NC UART3_RXD SD2_D2 SD2_D3 NC SD2_D7 Freescale Semiconductor 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 KEY_ROW0 KEY_COL0 KEY_COL1 EIM_WAIT EIM_BCLK EIM_DA14 EIM_DA10 EIM_DA13 EIM_DA12 EIM_DA9 EIM_DA8 POP_EMMC_RST NVCC_EMI_DRAM 21 23 KEY_ROW3 EIM_DA3 EIM_DA4 VSS I2C1_SDA KEY_ROW1 KEY_COL2 KEY_COL3 EIM_RDY EIM_OE EIM_LBA EIM_RW EIM_DA15 EIM_DA11 EIM_DA7 EIM_DA6 POP_LPDDR2_1.8V POP_LPDDR2_1.8V POP_LPDDR2_1.8V 20 22 I2C1_SCL I2C2_SDA NVCC_EMI_DRAM EIM_DA5 EIM_DA0 EIM_CS0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC EIM_DA2 EIM_DA1 UART4_TXD KEY_ROW2 EPITO WDOG PWM2 PWM1 OWIRE EIM_CRE EIM_EB1 EIM_EB0 EIM_CS2 EIM_CS1 EPDC_SDCE5 POP_NAND_VCC POP_NAND_VCC NVCC_EMI_DRAM NC NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM VSS VSS DRAM_D31 DRAM_D30 DRAM_D29 DRAM_D28 DRAM_D26 DRAM_D25 DRAM_SDQS3 VSS VSS DRAM_D15 DRAM_D14 VSS NC EPDC_PWRCOM EPDC_PWRCTRL0 NVCC_EMI_DRAM NC NC NC NC NC NC NC NC NC NC NC NC NC DRAM_D13 VSS NC EPDC_PWRCTRL2 EPDC_PWRSTAT 5.2.2 NC • • NVCC_EMI_DRAM NVCC_EMI_DRAM 1 A B C D E F Package Information and Contact Assignments All dimensions and tolerances conform to ASME Y14.5M-1994. Parallelism measurement shall exclude any effect of mark on top surface of package. 416 PoPBGA 13 x 13 mm, 0.5 Pitch Ball Map Table 81 shows the 416 PoPBGA 13 x 13 mm ball map. Table 81. 416 PoPBGA 13 x 13 mm Ball Map i.MX50 Applications Processors for Consumer Products, Rev. 7 111 112 SD1_CLK SD1_D2 NC ECSPI1_SCLK SD1_CMD SD1_D1 NC ECSPI1_MOSI VDDGP VDDGP NC VDDGP VSS VSS VSS VSS VCC NC VSS DRAM_DQM1 NC NVCC_EIM NVCC_EIM NC NVCC_EPDC VSS NC NC VSS VSS NC VSS DRAM_DQM0 NC NVCC_EIM NVCC_KEYPAD NC NVCC_EPDC VSS NC NC VSS VSS NC VSS DRAM_SDQS0 NC NC DRAM_SDQS1_B VCC NC VCC VCC VSS VSS VSS VDDGP NC VDDGP VDDGP NC DRAM_A7 ECSPI1_MISO NC ECSPI2_MOSI ECSPI2_SS0 K NC DRAM_D8 VCC NC NC NC NC NC NC NC NC VDDGP VDDGP NC DRAM_A8 SD2_CD NC CSPI_SS0 CSPI_MOSI J EPDC_PWRCTRL3 NC EPDC_GDRL EPDC_SDCLKN NVCC_EMI_DRAM EPDC_D13 NC VREF EPDC_SDLE NVCC_EMI_DRAM EPDC_D14 NC VDDO25 EPDC_SDCE0 EPDC_SDCLK EPDC_PWRCTRL1 NC EPDC_SDCE4 DRAM_D9 NC DRAM_D11 VCC VCC VCC VCC VSS VSS VSS VDDGP VDDGP VDDGP VDDGP NC DRAM_A9 SD2_D6 NC CSPI_MISO CSPI_SCLK H EPDC_SDSHR NC EPDC_GDOE EPDC_VCOM0 EPDC_D12 NC EPDC_SDCE3 EPDC_SDCE2 NVCC_EMI_DRAM NVCC_EMI_DRAM DRAM_SDQS1 NC NC DRAM_A6 ECSPI1_SS0 NC ECSPI2_MISO ECSPI2_SCLK L NC POP_LPDDR2_1.8V POP_LPDDR2_1.8V M N EPDC_GDCLK VSS NC VSS DRAM_D10 NC DRAM_D12 DRAM_DQM3 DRAM_SDQS3_B DRAM_D24 DRAM_D27 VSS VSS VSS VDDGP VDDGP VDDGP NVCC_EMI_DRAM NC NVCC_EMI_DRAM SD2_WP NC SD2_D4 SD2_CMD G Package Information and Contact Assignments Table 81. 416 PoPBGA 13 x 13 mm Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor Freescale Semiconductor EPDC_D3 EPDC_D6 EPDC_D2 NC EPDC_D1 NC EPDC_D0 NC NC NVCC_EMI_DRAM DRAM_D5 EPDC_D10 NVCC_EMI_DRAM NC NVCC_EMI_DRAM VSS EPDC_D8 DRAM_D2 NC DRAM_D1 VSS EPDC_BDR1 DRAM_D0 NC DRAM_DQM2 VSS NC DRAM_SDQS2_B NC DRAM_SDQS2 VSS NC DRAM_D22 NC DRAM_D23 VSS NC DRAM_D20 NC DRAM_D21 VSS EPDC_SDOEZ DRAM_D18 NC DRAM_D19 NVCC_LCD EPDC_SDOE DRAM_D16 NC DRAM_D17 NVCC_EPDC EPDC_VCOM1 NVCC_NANDF NC DRAM_A4 NVCC_JTAG EPDC_BDR0 NVCC_NANDF NC DRAM_A3 NVCC_SD2 DRAM_D3 NVCC_RESET NC DRAM_A2 DRAM_CS1 NC DRAM_CS0 SD3_D7 NC SD3_D3 SD3_D5 U NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DRAM_A0 NC JTAG_MOD GND_DCDC VDD_DCDCO DRAM_A1 JTAG_TDO JTAG_TCK JTAG_TMS NC NC NC NC NC SD3_D1 PMIC_STBY_REQ ECKIL VDD_DCDCI SD3_D0 PMIC_ON_REQ CKIL V W Y EPDC_D5 EPDC_D7 NC EPDC_D9 DRAM_D4 NC DRAM_D6 VSS NC NC NC NC NC NC NC NC NVCC_UART NVCC_SD1 NC DRAM_SDCKE SD3_WP NC SD3_CMD SD3_CLK T EPDC_D4 EPDC_SDOED NC EPDC_D11 NVCC_EMI_DRAM NC DRAM_D7 VDDA NC VDDAL1 VSS VSS VSS VSS NVCC_EPDC NC NVCC_SSI NVCC_SPI NC DRAM_SDCLK_0 SD1_D3 NC SD3_D6 SD3_D2 R EPDC_SDCE1 EPDC_GDSP NC EPDC_D15 NVCC_EMI_DRAM NC DRAM_SDQS0_B VDDA NC VDDAL1 VSS VSS VSS VSS NVCC_EPDC NC NVCC_MISC DRAM_A5 NC DRAM_SDCLK_0_B DRAM_CALIBRATION NC SD1_D0 SD3_D4 P Package Information and Contact Assignments Table 81. 416 PoPBGA 13 x 13 mm Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 113 Package Information and Contact Assignments DISP_BUSY NC POP_LPDDR2_ZQ1 POP_LPDDR2_ZQ0 NC DISP_D14 DISP_D5 DISP_D12 DISP_D13 DISP_D4 DISP_D10 DISP_RS VSS DISP_RESET NC DISP_D7 DISP_D11 NC VSS NC VSS VSS DISP_CS USB_H1_GPANAIO NC DISP_D0 DISP_ DISP_D15 USB_H1_VBUS NC DISP_D1 DISP_D6 DISP_RD CHGR_DET_B NC DISP_D3 DISP_D2 NC USB_OTG_GPANAIO NC SSI_RXD SSI_TXD DISP_D9 USB_OTG_VBUS NC SSI_TXC SSI_RXFS DISP_WR USB_OTG_ID NC SSI_TXFS SSI_RXC VSS VSS NC USB_VDDA25 USB_VDDA25 NC USB_OTG_RREFEXT NC USB_OTG_DP USB_OTG_DN USB_VDDA33 USB_VDDA33 GND_KEL NC VSS VDD1P8 USB_H1_RREFEXT CKIH NC VSS VDD1P2 NC JTAG_TRSTB NC EXTAL XTAL USB_H1_DN JTAG_TDI NC VSS VDD2P5 USB_H1_DP NC NC VSS BOOT_MODE1 TEST_MODE POR_B VSS NVCC_SRTC BOOT_MODE0 RESET_IN_B VSS 5.2.3 VDD3P0 AA AB AC AD Table 81. 416 PoPBGA 13 x 13 mm Ball Map (continued) 416 PoPBGA 13 x 13 mm Power Rails Table 82 shows the device connection list for ground, power, sense, and reference contact signals. Table 85 displays an alpha-sorted list of the signal assignments including power rails and associated power supplies. Table 82. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals Pin Name Ball Number Comments GND_DCDC W5 — NVCC_EIM N7 M7 M8 — NVCC_EMI_DRAM A21, B21, D21, D23, D24, E5, E6, E7, F5, G5, G7, K20, These are the 1.2V supply to both the L20, M20, N20, P20, R20, V18, V20, W20, Y18, Y19, Y20 i.MX50 DRAM controller as well as the PoP LPDDR2. NVCC_EPDC M10, N10, P10, R10, U10 — NVCC_JTAG U9 — NVCC_KEYPAD N8 — NVCC_LCD U11 — NVCC_MISC P8 — NVCC_NANDF V9, V10 — i.MX50 Applications Processors for Consumer Products, Rev. 7 114 Freescale Semiconductor Package Information and Contact Assignments Table 82. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals (continued) NVCC_RESET V8 — NVCC_SD1 T7 — NVCC_SD2 U8 — NVCC_SPI R7 — NVCC_SRTC AA1 — NVCC_SSI R8 — NVCC_UART T8 — POP_EMMC_RST A19 This is PoP eMMC 4.4 NAND Reset input pin. This pin does not connect to the i.MX50. If using eMMC 4.4 NAND, this pin can be connected to a GPIO. For non 4.4 eMMC applications, leave floating. POP_LPDDR2_1.8V A20, B19, B20, M5, N5 This is the 1.8V supply for the PoP LPDDR2. These pins do not connect to the i.MX50. POP_LPDDR2_ZQ0 AA24 This is the PoP LPDDR2 ZQ0 pin. This pin does not connect to the i.MX50. This should be connected on the PCB to a 240 Ω 1% resistor to ground POP_LPDDR2_ZQ1 AA23 This is the PoP LPDDR2 ZQ1 pin. This pin does not connect to the i.MX50. If used, this should be connected on the PCB to a 240 Ω 1% resistor to ground POP_NAND_VCC D19, D20 This is the 3.3V I/O and memory supply for the PoP eMMC NAND. Note that because the eMMC memory and I/O domains are shorted together, it is not possible to support 1.8 V I/O for the PoP eMMC NAND. USB_VDDA25 AC9, AD9 Note that on the PoPBGA package, USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together. USB_VDDA33 AC11, AD11 Note that on the PoPBGA package, USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together. VCC H14, H15, H16, H17, J17, K14, K15, K17, L15 — VDD_DCDCI Y6 — VDD_DCDCO Y5 — VDD1P2 AD6 — VDD1P8 AD7 — i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 115 Package Information and Contact Assignments Table 82. 416 PoPBGA 13 x 13 mm Ground, Power, Sense, and Reference Contact Signals (continued) VDD2P5 AD4 — VDD3P0 AD3 — VDDA P17, R17 — VDDAL1 P15, R15 — VDDGP G10, G8, G9, H10, H7, H8, H9, J7, J8, K10, K7, K8, L10, — L7, L8 VDDO25 N23 VSS A1, A24, AA11, AA18, AA2, AA9, AC18, AC3, AC4, AC6, — AC7, AD1, AD18, AD24, E17, E18, E21, E8, E9, F21, G11, G12, G13, G21, G23, H11, H12, H13, K11, K12, K13, L11, L12, L13, L14, L17, M11, M14, M15, M17, N11, N14, N15, N17, P11, P12, P13, P14, R11, R12, R13, R14, T17, U12, U13, U14, U15, U16, U17 5.3 — 17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package Information This section contains the outline drawing, signal assignment map, ground, power, reference ID (by ball grid location) for the 17 x 17 mm, 0.8 mm pitch, 400 pin MAPBGA package. i.MX50 Applications Processors for Consumer Products, Rev. 7 116 Freescale Semiconductor Package Information and Contact Assignments 5.3.1 400 MAPBGA 17 x 17 mm Package Views Figure 65 shows the top view of the 17 x 17 mm package, Figure 66 shows the bottom view of the package, and Figure 67 shows the side view of the package. C 17 B A1 INDEX AREA 17 4x 0.15 Top View Figure 65. 400 MAPBGA 17x17 mm Package Top view i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 117 Package Information and Contact Assignments Figure 66. 400 MAPBGA 17x17 mm Package Bottom View i.MX50 Applications Processors for Consumer Products, Rev. 7 118 Freescale Semiconductor Package Information and Contact Assignments Figure 67. 400 MAPBGA 17x17 mm Package Side View The following notes apply to Figure 65, Figure 66, and Figure 67: • Unless otherwise specified dimensions are in millimeters. • All dimensions and tolerances conform to ASME Y14.5M-1994. • Parallelism measurement shall exclude any effect of mark on top surface of package. 5.3.2 400 MAPBGA 17 x 17 mm Ball Map Table 83 shows the 400 MAPBGA 17 x 17 mm ball map. 20 NC DRAM_D31 19 DRAM_D30 DRAM_D24 18 DRAM_D29 DRAM_D25 17 DRAM_D28 DRAM_D27 16 DRAM_D26 EPDC_D2 15 EPDC_BDR0 EPDC_D0 14 EPDC_D1 EPDC_VCOM0 13 EPDC_D5 EPDC_SDCLK 12 EPDC_SDCE0 EPDC_SDCE1 11 EPDC_GDCLK EIM_CS0 10 EPDC_GDRL EIM_DA0 9 EIM_DA4 EIM_DA1 8 EPDC_SDSHR EIM_DA5 7 EIM_DA8 EIM_DA9 6 EIM_DA12 EIM_DA13 5 EIM_BCLK EIM_EB0 EIM_EB1 EIM_RW EIM_CRE EIM_OE 4 EIM_RDY KEY_COL1 3 NC KEY_COL0 2 A B 1 Table 83. 400 MAPBGA 17 x 17 mm Ball Map i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 119 120 VDDGP VDDGP VDDGP VSS VSS VSS VSS VSS VSS VDDAL1 VDDAL1 VDDA VCC VSS VSS NVCC_EMI_DRAM EPDC_VCOM1 VSS VSS VSS VSS VDDGP VDDGP VDDGP VDDGP VDDGP SSI_RXFS SSI_TXD SSI_TXC I2C3_SDA I2C3_SCL G DRAM_OPENFB DRAM_OPEN DRAM_A11 DRAM_SDBA1 DRAM_SDCLK_0 DRAM_SDCLK_0_B DRAM_A10 DRAM_SDBA0 DRAM_CAS DRAM_A9 DRAM_SDQS1_B DRAM_SDQS1 NVCC_EMI_DRAM NVCC_EMI_DRAM EPDC_SDOED VDDGP VDDGP SSI_RXC CSPI_SS0 VDDGP SSI_TXFS UART4_RXD VDDGP UART4_TXD UART3_TXD NVCC_KEYPAD UART1_TXD UART1_CTS NVCC_MISC H J DRAM_CALIBRATION DRAM_A13 DRAM_D9 DRAM_DQM1 EPDC_SDOEZ EPDC_PWRCTRL3 EPDC_D11 EPDC_D12 NVCC_EPDC NVCC_EPDC NVCC_EPDC NVCC_EPDC NVCC_EIM NVCC_EIM NVCC_EIM EPITO WDOG SSI_RXD I2C2_SDA I2C2_SCL F EIM_CS2 EIM_DA3 EIM_DA7 EIM_DA11 EIM_DA15 EIM_LBA KEY_ROW3 KEY_ROW1 KEY_ROW0 D EPDC_GDSP EPDC_SDCE2 EPDC_GDOE EIM_CS1 EIM_DA2 EIM_DA6 EIM_DA10 EIM_DA14 EIM_WAIT KEY_ROW2 KEY_COL3 KEY_COL2 C DRAM_RAS DRAM_A12 DRAM_D13 DRAM_D10 EPDC_D9 EPDC_D8 EPDC_D13 EPDC_D15 DRAM_SDQS3 DRAM_D14 DRAM_D15 EPDC_D3 EPDC_SDLE EPDC_D6 EPDC_SDOE DRAM_DQM3 DRAM_SDQS3_B DRAM_D11 DRAM_D12 DRAM_D8 EPDC_BDR1 EPDC_D4 EPDC_D7 EPDC_D10 EPDC_PWRCTRL2 EPDC_SDCLKN EPDC_PWRSTAT EPDC_D14 EPDC_PWRCTRL0 EPDC_SDCE4 EPDC_PWRCTRL1 EPDC_SDCE3 EPDC_PWRCOM EPDC_SDCE5 OWIRE PWM1 PWM2 I2C1_SDA I2C1_SCL E Package Information and Contact Assignments Table 83. 400 MAPBGA 17 x 17 mm Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor Freescale Semiconductor JTAG_TMS VSS VSS VSS VSS VSS VSS JTAG_TDO CHGR_DET_B DISP_D1 DISP_CS DISP_D13 DISP_RESET SD3_D7 NVCC_EMI_DRAM VSS VSS VSS VSS VSS VSS VSS VSS NVCC_SD1 ECSPI2_SCLK ECSPI1_SS0 ECSPI1_SCLK ECSPI2_MOSI N NVCC_EMI_DRAM NVCC_EMI_DRAM VSS VSS NVCC_NANDF NVCC_NANDF NVCC_LCD NVCC_JTAG VSS VSS NVCC_RESET NVCC_SD2 SD1_CMD SD1_D2 SD1_D3 SD1_D1 P VSS VSS VSS VSS VCC VCC VSS VSS VSS VSS NVCC_SPI ECSPI1_MOSI ECSPI1_MISO ECSPI2_SS0 CSPI_SCLK M NVCC_EMI_DRAM VSS VCC VCC VCC VDDA VSS VDDGP VDDGP NVCC_SSI CSPI_MISO UART3_RXD UART1_RTS UART1_RXD K NVCC_EMI_DRAM NVCC_EMI_DRAM VSS VSS VCC VCC VCC VSS VSS VSS VDDGP NVCC_UART ECSPI2_MISO CSPI_MOSI UART2_RXD UART2_TXD L DRAM_A4 DRAM_SDCKE DRAM_D1 DRAM_D0 DRAM_A0 DRAM_A1 DRAM_SDQS2 DRAM_SDQS2_B DRAM_D2 DRAM_D3 DRAM_CS1 DRAM_CS0 DRAM_D4 DRAM_D7 DRAM_D5 DRAM_DQM0 DRAM_D6 DRAM_SDBA2 DRAM_SDQS0_B DRAM_SDQS0 DRAM_A8 DRAM_A6 DRAM_SDWE VDDO25 DRAM_A7 DRAM_A5 DRAM_SDODT0 VREF NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM JTAG_TCK JTAG_MOD SD3_D2 VDD_DCDCI GND_KEL SD2_D6 SD2_D3 GND_DCDC SD2_D0 SD2_CLK VDD_DCDCO SD1_D0 SD2_WP NVCC_SRTC SD1_CLK SD2_CD VSS R T Package Information and Contact Assignments Table 83. 400 MAPBGA 17 x 17 mm Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 121 122 ECKIL CKIL VDD1P8 VDD2P5 CKIH BOOT_MODE0 SD2_D4 SD2_CMD V SD3_WP DISP_D10 DRAM_D20 DISP_D8 DISP_D15 NC DISP_D11 SD3_CLK DRAM_D19 DISP_D3 DISP_D4 DRAM_D16 DISP_D2 DISP_RS DRAM_D21 USB_H1_VDDA33 USB_OTG_VDDA33 DRAM_D17 USB_H1_DN USB_H1_DP SD3_D4 USB_OTG_VDDA25 USB_H1_VDDA25 SD3_D0 USB_OTG_DN DRAM_D22 DRAM_D18 DRAM_A3 SD3_D6 SD3_D1 DISP_D9 DISP_D12 DISP_D7 DISP_RD DISP_D0 DISP_WR USB_H1_VBUS USB_OTG_VBUS USB_OTG_RREFEXT USB_OTG_GPANAIO USB_OTG_DP USB_OTG_ID EXTAL RESET_IN_B PMIC_ON_REQ XTAL SD2_D2 PMIC_STBY_REQ VSS SD2_D7 NC POR_B W Y DRAM_DQM2 DRAM_D23 DRAM_A2 SD3_D5 SD3_CMD SD3_D3 DISP_D14 DISP_D5 DISP_D6 DISP_BUSY USB_H1_GPANAIO USB_H1_RREFEXT JTAG_TDI JTAG_TRSTB VDD1P2 VDD3P0 TEST_MODE BOOT_MODE1 SD2_D5 SD2_D1 U Package Information and Contact Assignments Table 83. 400 MAPBGA 17 x 17 mm Ball Map (continued) i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor Package Information and Contact Assignments 5.3.3 400 MAPBGA 17 x 17 Power Rails Table 84. 400 MAPBGA 17x17 Ground, Power, Sense, and Reference Contact Signals Pin Name Ball Number NC A1 Y1 A20 Y20 NVCC_EIM F6 F7 F8 NVCC_EMI_DRAM K14 N14 J15 K15 L15 N15 P15 H16 J16 K16 L16 M16 N16 P16 R16 NVCC_EPDC F9 F10 F11 F12 NVCC_JTAG P9 NVCC_KEYPAD H5 NVCC_LCD P10 NVCC_MISC J5 NVCC_NANDF P11 P12 NVCC_RESET P6 NVCC_SD1 N5 NVCC_SD2 P5 NVCC_SPI M5 NVCC_SRTC R5 NVCC_SSI K5 NVCC_UART L5 USB_H1_VDDA25 Y9 USB_H1_VDDA33 W11 USB_OTG_VDDA25 W9 USB_OTG_VDDA33 Y11 VCC K10 L10 M10 K11 L11 M11 J12 K12 L12 VDD1P2 U6 VDD1P8 V6 VDD2P5 V5 VDD3P0 U5 VDDA K9 J11 VDDAL1 J9 J10 VDDGP G6 H6 J6 K6 L6 G7 H7 J7 K7 G8 H8 G9 H9 G10 H10 VDDO25 L17 VSS T5 W5 M6 N6 L7 M7 N7 P7 J8 K8 L8 M8 N8 P8 L9 M9 N9 N10 R10 G11 H11 N11 R11 G12 H12 M12 N12 R12 G13 H13 J13 K13 L13 M13 N13 P13 R13 G14 H14 J14 L14 M14 P14 R14 H15 M15 R15 i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 123 Package Information and Contact Assignments Table 84. 400 MAPBGA 17x17 Ground, Power, Sense, and Reference Contact Signals (continued) VDD_DCDCI R7 VDD_DCDCO T6 GND_DCDC R6 5.4 Signal Assignments Table 85. Alphabetical List of Signal Assignments Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset BOOT_MODE0 AB1 AB1 V3 NVCC_RESET LVIO ALT0 IN 100K PU BOOT_MODE1 AB2 AB2 U3 NVCC_RESET LVIO ALT0 IN 100K PU CHGR_DET_B V11 AA15 T10 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG25 — OUT-OD — CKIH AA6 AA6 V4 NVCC_JTAG ANALOG — — — CKIL Y1 Y1 Y4 NVCC_SRTC ANALOG — — — CSPI_MISO M5 H2 K4 NVCC_SPI HVIO ALT1 IN Keeper CSPI_MOSI M2 J1 L3 NVCC_SPI HVIO ALT1 IN Keeper CSPI_SCLK M1 H1 M1 NVCC_SPI HVIO ALT1 IN Keeper CSPI_SS0 M4 J2 J4 NVCC_SPI HVIO ALT1 IN Keeper DISP_BUSY AC12 AA21 U11 NVCC_LCD HVIO ALT1 IN Keeper DISP_CS AD14 AC21 T12 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D0 AA12 AC17 V11 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D1 Y12 AC16 T11 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D10 Y17 AD22 Y16 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D11 V12 AD19 W14 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D12 V13 AC22 V14 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D13 V14 AC23 T13 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D14 V15 AB23 U14 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D15 V16 AD21 Y15 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D2 AA13 AD15 W12 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D3 Y13 AC15 W13 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D4 AA14 AC24 Y13 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D5 Y14 AB24 U13 NVCC_LCD HVIO ALT3 OUT-LO 100K PU i.MX50 Applications Processors for Consumer Products, Rev. 7 124 Freescale Semiconductor Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset DISP_D6 AA15 AD16 U12 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D7 Y15 AC19 V13 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_D8 AA16 AD17 W15 NVCC_NANDF HVIO ALT1 IN Keeper DISP_D9 Y16 AC20 V15 NVCC_NANDF HVIO ALT1 IN Keeper DISP_RD AD13 AA20 V12 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_RESET AC14 AA19 T14 NVCC_LCD HVIO ALT1 IN Keeper DISP_RS AC13 AD23 Y12 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DISP_WR AD12 AD20 V10 NVCC_LCD HVIO ALT3 OUT-LO 100K PU DRAM_A0 W20 V7 T17 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A1 W21 Y7 T18 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A10 K20 — J19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A11 J20 — H19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A12 H20 — E19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A13 F21 — F19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A14 F20 — — NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A2 Y20 Y8 U18 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A3 Y21 Y9 V18 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A4 AA20 Y10 R17 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A5 P20 P7 K19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A6 P21 L5 L19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A7 N20 K5 K20 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A8 N21 J5 L20 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_A9 L21 H5 G19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_CALIBRATI ON L20 P4 F20 NVCC_EMI_DRAM DRAMCALI B — — — DRAM_CAS J21 — G20 NVCC_EMI_DRAM DRAM ALT0 OUT-HI Keeper DRAM_CS0 T21 U5 P17 NVCC_EMI_DRAM DRAM ALT0 OUT-HI Keeper DRAM_CS1 U21 U7 P18 NVCC_EMI_DRAM DRAM ALT0 OUT-HI Keeper DRAM_D0 Y24 V16 R20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D1 Y23 Y17 R19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 125 Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset DRAM_D10 G24 G20 E17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D11 H23 H18 D19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D12 F23 G18 D18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D13 F24 F20 E18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D14 E24 E20 C18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D15 E23 E19 C17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D16 AC19 V11 Y19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D17 AD19 Y11 Y18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D18 AC20 V12 V19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D19 AD20 Y12 W19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D2 W23 V17 P20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D20 AC22 V13 W20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D21 AD22 Y13 W18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D22 AC23 V14 V20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D23 AD23 Y14 U19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D24 B23 G15 B19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D25 A23 E15 B18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D26 A22 E14 A16 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D27 B22 G14 B17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D28 B20 E13 A17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D29 A20 E12 A18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D3 W24 U20 P19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D30 A19 E11 A19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D31 B19 E10 B20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D4 V24 T20 N20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D5 U23 U18 N18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D6 T23 T18 M20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D7 U24 R18 N19 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D8 J23 J18 D17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_D9 H24 H20 F18 NVCC_EMI_DRAM DRAM ALT0 IN Keeper i.MX50 Applications Processors for Consumer Products, Rev. 7 126 Freescale Semiconductor Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset DRAM_DQM0 T24 M18 N17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_DQM1 J24 L18 F17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_DQM2 AC24 Y16 U20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_DQM3 B24 G17 D20 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_OPEN J18 — H18 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_OPENFB H18 — H17 NVCC_EMI_DRAM DRAM ALT0 IN Keeper DRAM_RAS H21 — E20 NVCC_EMI_DRAM DRAM ALT0 OUT-HI Keeper DRAM_SDBA0 K18 — J20 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_SDBA1 L18 — H20 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_SDBA2 N18 — M19 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_SDCKE U20 T5 R18 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_SDCLK_0 N24 R5 J17 NVCC_EMI_DRAM DRAMCLK ALT0 OUT-LO Keeper DRAM_SDCLK_0_ B M24 P5 J18 NVCC_EMI_DRAM DRAMCLK ALT0 OUT-HI — DRAM_SDCLK_1 T20 — — NVCC_EMI_DRAM DRAMCLK ALT0 OUT-LO Keeper DRAM_SDCLK_1_ B R20 — — NVCC_EMI_DRAM DRAMCLK ALT0 OUT-HI — DRAM_SDODT0 G18 — K18 NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_SDODT1 R18 — — NVCC_EMI_DRAM DRAM ALT0 OUT-LO Keeper DRAM_SDQS0 P23 N18 M17 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS0_B P24 P18 M18 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS1 L23 J20 G17 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS1_B L24 K18 G18 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS2 AB23 Y15 T19 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS2_B AB24 V15 T20 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS3 C23 E16 C19 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDQS3_B C24 G16 C20 NVCC_EMI_DRAM DRAMCLK ALT0 IN — DRAM_SDWE P18 — L18 NVCC_EMI_DRAM DRAM ALT0 OUT-HI Keeper ECKIL Y2 Y2 W4 NVCC_SRTC ANALOG — — — ECSPI1_MISO N7 K4 M3 NVCC_SPI HVIO ALT1 IN Keeper ECSPI1_MOSI N2 N4 M4 NVCC_SPI HVIO ALT1 IN Keeper i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 127 Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset ECSPI1_SCLK N1 M4 N2 NVCC_SPI HVIO ALT1 IN Keeper ECSPI1_SS0 P7 L4 N3 NVCC_SPI HVIO ALT1 IN Keeper ECSPI2_MISO N5 L2 L4 NVCC_SPI HVIO ALT1 IN Keeper ECSPI2_MOSI P5 K2 N1 NVCC_SPI HVIO ALT1 IN Keeper ECSPI2_SCLK P4 L1 N4 NVCC_SPI HVIO ALT1 IN Keeper ECSPI2_SS0 N4 K1 M2 NVCC_SPI HVIO ALT1 IN Keeper EIM_BCLK A5 A12 A5 NVCC_EIM HVIO ALT0 OUT-LO 100K PU EIM_CRE A3 D13 A3 NVCC_EIM HVIO ALT0 OUT-LO 100K PU EIM_CS0 B10 B24 B11 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_CS1 D10 D17 C9 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_CS2 E10 D16 D9 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_DA0 A9 B23 B10 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA1 B9 C24 B9 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA10 D7 A14 C6 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA11 E7 B16 D6 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA12 A6 A16 A6 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA13 B6 A15 B6 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA14 D6 A13 C5 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA15 E6 B15 D5 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA2 D9 C23 C8 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA3 E9 A22 D8 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA4 A8 A23 A9 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA5 B8 B22 B8 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA6 D8 B18 C7 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA7 E8 B17 D7 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA8 A7 A18 A7 NVCC_EIM HVIO ALT0 IN 100K PU EIM_DA9 B7 A17 B7 NVCC_EIM HVIO ALT0 IN 100K PU EIM_EB0 A4 D15 A4 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_EB1 B4 D14 B4 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_LBA E5 B13 D4 NVCC_EIM HVIO ALT0 OUT-HI 100K PU i.MX50 Applications Processors for Consumer Products, Rev. 7 128 Freescale Semiconductor Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset EIM_OE B3 B12 B3 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_RDY A2 B11 A2 NVCC_EIM HVIO ALT0 IN 100K PU EIM_RW B5 B14 B5 NVCC_EIM HVIO ALT0 OUT-HI 100K PU EIM_WAIT D5 A11 C4 NVCC_EIM HVIO ALT0 IN 100K PU EPDC_BDR0 E20 Y21 A15 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_BDR1 E21 Y23 D16 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D0 A17 Y24 B15 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D1 B17 W24 A14 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D10 D15 V23 D13 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D11 E15 R21 F14 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D12 A14 J23 F13 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D13 B14 M21 E14 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D14 D14 N21 E11 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D15 E14 P21 E13 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D2 D17 U23 B16 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D3 E17 V24 C16 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D4 A16 R24 D15 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D5 B16 T24 A13 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D6 D16 U24 C14 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D7 E16 T23 D14 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D8 A15 W23 E15 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_D9 B15 T21 E16 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_GDCLK A11 G24 A11 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_GDOE B11 J24 C10 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_GDRL A12 L23 A10 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_GDSP B12 P23 D11 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_PWRCOM G11 E23 E7 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_PWRCTRL 0 G12 E24 E10 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_PWRCTRL 1 G13 K23 E9 NVCC_EPDC HVIO ALT1 IN Keeper i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 129 Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset EPDC_PWRCTRL 2 G14 F23 E12 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_PWRCTRL 3 G15 L21 F15 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_PWRSTAT G16 F24 C12 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCE0 D13 N24 B12 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCE1 E13 P24 A12 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCE2 D12 H21 C11 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCE3 E12 J21 E8 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCE4 D11 K21 D10 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCE5 E11 D18 E6 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCLK A13 K24 B13 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDCLKN B13 L24 D12 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDLE D18 M24 C15 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDOE E18 V21 C13 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDOED D19 R23 G16 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDOEZ E19 U21 F16 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_SDSHR A10 H23 A8 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_VCOM0 G17 H24 B14 NVCC_EPDC HVIO ALT1 IN Keeper EPDC_VCOM1 D20 W21 G15 NVCC_EPDC HVIO ALT1 IN Keeper EPITO G4 D8 F5 NVCC_MISC HVIO ALT1 IN Keeper EXTAL AC5 AC5 W6 VDD2P5 ANALOG — — — GND_KEL AA7 AA7 T7 VDD2P5 ANALOG — — — I2C1_SCL E1 A6 E1 NVCC_MISC HVIO ALT1 IN Keeper I2C1_SDA E2 B7 E2 NVCC_MISC HVIO ALT1 IN Keeper I2C2_SCL F1 A5 F1 NVCC_MISC HVIO ALT1 IN Keeper I2C2_SDA F2 B6 F2 NVCC_MISC HVIO ALT1 IN Keeper I2C3_SCL G1 A4 G1 NVCC_MISC HVIO ALT1 IN Keeper I2C3_SDA G2 B5 G2 NVCC_MISC HVIO ALT1 IN Keeper JTAG_MOD V7 V5 T8 NVCC_JTAG GPIO ALT0 IN 100K PU JTAG_TCK W4 W4 R8 NVCC_JTAG GPIO ALT0 IN 100K PD i.MX50 Applications Processors for Consumer Products, Rev. 7 130 Freescale Semiconductor Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset JTAG_TDI AA4 AA4 U8 NVCC_JTAG GPIO ALT0 IN 47K PU JTAG_TDO U7 V4 T9 NVCC_JTAG GPIO ALT0 OUT-LO Keeper JTAG_TMS Y4 Y4 R9 NVCC_JTAG GPIO ALT0 IN 47K PU JTAG_TRSTB AA5 AA5 U7 NVCC_JTAG GPIO ALT0 IN 47K PU KEY_COL0 B1 A9 B1 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_COL1 B2 A10 B2 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_COL2 C1 B9 C1 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_COL3 C2 B10 C2 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_ROW0 D1 A8 D1 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_ROW1 D2 B8 D2 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_ROW2 D4 D7 C3 NVCC_KEYPAD HVIO ALT1 IN Keeper KEY_ROW3 E4 A7 D3 NVCC_KEYPAD HVIO ALT1 IN Keeper OWIRE G7 D12 E5 NVCC_MISC HVIO ALT1 IN Keeper PMIC_ON_REQ W1 W1 Y3 NVCC_SRTC GPIO ALT0 OUT-LO — PMIC_STBY_REQ W2 W2 Y2 NVCC_SRTC GPIO ALT0 OUT-LO — POR_B AD2 AD2 Y5 NVCC_RESET LVIO ALT0 IN 100K PU PWM1 F5 D11 E4 NVCC_MISC HVIO ALT1 IN Keeper PWM2 F4 D10 E3 NVCC_MISC HVIO ALT1 IN Keeper RESET_IN_B AC1 AC1 W3 NVCC_RESET LVIO ALT0 IN 100K PU SD1_CLK P1 M1 R1 NVCC_SD1 HVIO ALT1 IN Keeper SD1_CMD R1 N1 P4 NVCC_SD1 HVIO ALT1 IN Keeper SD1_D0 R2 P2 R2 NVCC_SD1 HVIO ALT1 IN Keeper SD1_D1 P2 N2 P1 NVCC_SD1 HVIO ALT1 IN Keeper SD1_D2 R4 M2 P3 NVCC_SD1 HVIO ALT1 IN Keeper SD1_D3 R5 R4 P2 NVCC_SD1 HVIO ALT1 IN Keeper SD2_CD T4 J4 T1 NVCC_SD2 HVIO ALT1 IN Keeper SD2_CLK U1 E1 T3 NVCC_SD2 HVIO ALT1 IN Keeper SD2_CMD V5 G1 V1 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D0 T1 D1 R3 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D1 T2 D2 U1 NVCC_SD2 HVIO ALT1 IN Keeper i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 131 Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset IOMUX Direction PAD CTL After After Reset Reset SD2_D2 V1 F1 W2 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D3 V2 F2 T4 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D4 V4 G2 V2 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D5 U2 E2 U2 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D6 U4 H4 R4 NVCC_SD2 HVIO ALT1 IN Keeper SD2_D7 U5 F4 W1 NVCC_SD2 HVIO ALT1 IN Keeper SD2_WP T5 G4 T2 NVCC_SD2 HVIO ALT1 IN Keeper SD3_CLK AD16 T1 Y14 NVCC_NANDF HVIO ALT1 IN Keeper SD3_CMD AD17 T2 U16 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D0 AC15 V1 Y17 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D1 AC16 V2 V16 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D2 AC17 R1 T16 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D3 AA17 U2 U15 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D4 AA18 P1 W17 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D5 Y18 U1 U17 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D6 AA19 R2 V17 NVCC_NANDF HVIO ALT1 IN Keeper SD3_D7 Y19 U4 T15 NVCC_NANDF HVIO ALT1 IN Keeper SD3_WP AD15 T4 W16 NVCC_NANDF HVIO ALT1 IN Keeper SSI_RXC J7 AD12 H4 NVCC_SSI HVIO ALT1 IN Keeper SSI_RXD J5 AC14 F3 NVCC_SSI HVIO ALT1 IN Keeper SSI_RXFS H7 AD13 G5 NVCC_SSI HVIO ALT1 IN Keeper SSI_TXC J4 AC13 G3 NVCC_SSI HVIO ALT1 IN Keeper SSI_TXD H5 AD14 G4 NVCC_SSI HVIO ALT1 IN Keeper SSI_TXFS H4 AC12 H3 NVCC_SSI HVIO ALT1 IN Keeper TEST_MODE AC2 AC2 U4 NVCC_RESET LVIO ALT0 IN 100K PD UART1_CTS H2 B4 J1 NVCC_UART HVIO ALT1 IN Keeper UART1_RTS J2 B3 K2 NVCC_UART HVIO ALT1 IN Keeper UART1_RXD J1 A2 K1 NVCC_UART HVIO ALT1 IN Keeper UART1_TXD H1 A3 H1 NVCC_UART HVIO ALT1 IN Keeper UART2_CTS K2 B2 NVCC_UART HVIO ALT1 IN Keeper i.MX50 Applications Processors for Consumer Products, Rev. 7 132 Freescale Semiconductor Package Information and Contact Assignments Table 85. Alphabetical List of Signal Assignments (continued) Pin Name 416 416 400 MAPBGA PoPBGA MAPBGA Ball Ball Ball Number Number Number Pin Power Domain Pad Type IOMUX MUX CTL After Reset NVCC_UART HVIO ALT1 IN Keeper IOMUX Direction PAD CTL After After Reset Reset UART2_RTS L2 C2 UART2_RXD L1 C1 L2 NVCC_UART HVIO ALT1 IN Keeper UART2_TXD K1 B1 L1 NVCC_UART HVIO ALT1 IN Keeper UART3_RXD L4 E4 K3 NVCC_UART HVIO ALT1 IN Keeper UART3_TXD K4 D4 J2 NVCC_UART HVIO ALT1 IN Keeper UART4_RXD L5 D5 J3 NVCC_UART HVIO ALT1 IN Keeper UART4_TXD K5 D6 H2 NVCC_UART HVIO ALT1 IN Keeper USB_H1_DN AC10 AC10 W10 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG50 — — — USB_H1_DP AD10 AD10 Y10 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG50 — — — USB_H1_GPANAI O Y11 AA17 U10 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG25 — — — USB_H1_RREFEX T AA10 AA10 U9 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG25 — — — USB_H1_VBUS Y10 AA16 V9 USB_H1_VDDA25, USB_H1_VDDA33 ANALOG50 — — — USB_OTG_DN AC8 AC8 W8 USB_OTG_VDDA25, ANALOG50 USB_OTG_VDDA33 — — — USB_OTG_DP AD8 AD8 Y8 USB_OTG_VDDA25, ANALOG50 USB_OTG_VDDA33 — — — USB_OTG_GPANA IO Y7 AA14 V7 USB_OTG_VDDA25, ANALOG25 USB_OTG_VDDA33 — — — USB_OTG_ID Y8 AA12 Y7 USB_OTG_VDDA25, ANALOG25 USB_OTG_VDDA33 — — — USB_OTG_RREFE XT AA8 AA8 W7 USB_OTG_VDDA25, ANALOG25 USB_OTG_VDDA33 — — — USB_OTG_VBUS Y9 AA13 V8 USB_OTG_VDDA25, ANALOG50 USB_OTG_VDDA33 — — — VREF M23 M23 K17 VDDO25 ANALOG — — — WDOG G5 D9 F4 NVCC_MISC HVIO ALT1 IN — XTAL AD5 AD5 Y6 VDD2P5 ANALOG — — — i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 133 Revision History 6 Revision History Table 86 provides a revision history for this data sheet. Table 86. i.MX50 Data Sheet Document Revision History Rev. Number Date Substantive Change(s) Rev. 7 10/2013 • Added new part number information for parts with 1 GHz core frequencies: — MCIMX508CVK1B — MCIMX508CVM1B — MCIMX507CVM1B — MCIMX507CVK1B Updated sections: — Section 1, “Introduction” — Table 1, “Ordering Information” — Table 11, “i.MX50 Operating Ranges” — Table 15, “Maximum Supply Current Consumption—ARM CLK = 1 GHz” (added) Rev. 6 07/2013 • In Table 11, “i.MX50 Operating Ranges,” added VCC Stop mode ranges. Rev. 5 05/2013 • In Table 11, “i.MX50 Operating Ranges,” changed VCC peripheral supply (LPM) minimum voltage from 0.9 V to 1 V, and changed nominal voltage from 0.95 V to 1.05 V. Rev. 4 01/2013 • In Table 1, "Ordering Information," on page 7, added new part number information for MCIMX507CVK8B. • In Figure 27, "DTACK Read Access," on page 67, updated timing of EIM_DTACK. Rev. 3 10/2012 • In Table 11, "i.MX50 Operating Ranges," on page 24: —Changed DDR clock rate for reduced performance mode (RPM) of VCC from 100 MHz to 133 MHz —Changed DDR clock rate for high performance mode (HPM) of VCC from 200 MHz to 266 MHz Rev. 2 05/2012 • In Table 1, "Ordering Information," on page 7, added the following new part numbers: MCIMX508CZK8B, MCIMX503CVK8B, MCIMX503EVM8B, MCIMX502CVK8B, and MCIMX502EVM8B. • In Table 1, "Ordering Information," on page 7, added a new column, Tjunction. • In Table 3, "Package Feature Comparison," on page 9, added a new row for 416 PoPBGA package. • Updated Figure 1, "i.MX50 System Block Diagram," on page 10 by removing “LDOx3” and “DC-DC 1.2V.” • In Table 5, "Special Signal Considerations," on page 17, updated details for the following signals: DRAM_OPEN/DRAM_OPENFB and DRAM_SDODT0/DRAM_SDODT1 • In Table 5, "Special Signal Considerations," on page 17, added new rows for the following signals: POP_EMMC_RST, POP_LPDDR2_ZQ0/ZQ1, POP_LPDDR2_1.8V, and POP_NAND_VCC. • Added Section 4.1.2.1, “13 x 13 mm MAPBGA Package Thermal Resistance Data.” • Added Section 4.1.2.2, “13 x 13 mm PoPBGA Package Thermal Resistance Data.” • Added Section 4.1.2.3, “17 x 17 mm MAPBGA Package Thermal Resistance Data.” • In Table 11, "i.MX50 Operating Ranges," on page 24, added footnotes for USB_OTG_VDDA25 and USB_OTG_VDDA33. • In Table 78, "VBUS Comparators Thresholds," on page 101, changed VBUS input max current to 350 μA. • Added Section 5.2, “13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information.” • In Table 85, "Alphabetical List of Signal Assignments," on page 124: —Added a new column “416 PoPBGA Ball Number” —Changed “USB_H1_VDDA” to “USB_H1_VDDA25, USB_H1_VDDA33” —Changed “USB_OTG_VDDA” to “USB_OTG_VDDA25, USB_OTG_VDDA33” • Replace mDDR with LPDDR1 throughout the document. i.MX50 Applications Processors for Consumer Products, Rev. 7 134 Freescale Semiconductor Revision History Table 86. i.MX50 Data Sheet Document Revision History (continued) Rev. Number Date Substantive Change(s) Rev. 1 10/2011 • Table 5, "Special Signal Considerations," on page 17 changed CHRG_DET_B to CHGR_DET_B. • Table 5, "Special Signal Considerations," on page 17 in the CHGR_DET_B signal remarks, added “The maximum current leakage at this pin is 8.5 μA.” • Table 5, "Special Signal Considerations," on page 17 in the JTAG_MOD remarks, changed “pull-down” to “pull-up, by default” and added “If JTAG port is not needed, the internal pull-up can be disabled in order to reduce supply current to the pin.” • Table 14, "Maximum Supply Current Consumption—ARM CLK = 800 MHz," on page 27 in the 11th row under the Supply column, changed VDDO2P5 to VDDO25. • Table 78, "VBUS Comparators Thresholds," on page 101 changed CHRG_DET_B to CHGR_DET_B. • Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_0 pin number was changed to N24 and DRAM_SDCLK_0_B pin number was changed to M24. • Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDCLK_1 pin number was changed to T20 and DRAM_SDCLK_1_B pin number was changed to R20. • Table 5, "Special Signal Considerations," on page 17 for 416 MAPBGA, DRAM_SDQS0 pin number was changed to P23 and DRAM_SDQS0_B pin number was changed to P24. • Table 5, "Special Signal Considerations," on page 17 changed pad type of pin DRAM_CALIBRATION to DRAMCALIB. • Table 5, "Special Signal Considerations," on page 17 changed pad type of pins DRAM_SDCLK_0, DRAM_SDCLK_0_B, DRAM_SDCLK_1, DRAM_SDCLK_1_B, DRAM_SDQS0, DRAM_SDQS0_B, DRAM_SDQS1, DRAM_SDQS1_B, DRAM_SDQS2, DRAM_SDQS2_B, DRAM_SDQS3, and DRAM_SDQS3_B to DRAMCLK. Rev. 0 07/2011 Initial release. i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 135 How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. 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