MCIMX512CJM6C

Freescale Semiconductor Errata Document Number: IMX51CE Rev. 5, 02/2012 Chip Errata for the i.MX51 This document details the silicon errata known at the time of publication for the i.MX51 multimedia applications processors. The contents of this errata apply to the following devices: IMX51xA, IMX51xC, and IMX51xD. Table 1 provides a revision history for this document. Table 1. Document Revision History Rev. Number Date 0 11/2009 • Initial Release 1 03/2010 • • • • • Substantive Changes • • • • • • • • ENGcm09125 - updated status - Case 2 and 3 are fixed in firmware ENGcm10388 - fixed in firmware ENGcm10724 - updated headline and description Changed erratum number ENGcm10149 to ENGcm10150, no change in contents Added ENGcm10676, ENGcm10967, ENGcm11043, ENGcm10974, ENGcm11060, ENGcm11004, ENGcm11036, ENGcm11041, ENGcm11065 Added ENGcm11104, ENGcm10183, ENGcm11138, and ENGcm04750 Updated ENGcm09114 headline Changed ENGcm10198 number to ENGcm10407 Changed ENGcm10259 number to ENGcm10260 Changed ENGcm10267 number to ENGcm10272 Removed ENGcm10353 - duplicate of ENGcm10356 Removed ENGcm10342 - duplicate of ENGcm10344 Added ENGcm11161 and updated ENGcm11065 workaround. © 2012 Freescale Semiconductor, Inc. All rights reserved. Table 1. Document Revision History (continued) Rev. Number Date 2 06/2010 • • • • • • • • • • • • • • Updated description of ENGcm09107 Added eSDHCv2/eSDHCv3 erratum ENGcm09399 Added NFC/Boot ROM erratum ENGcm11189 Added GPU 2D erratum ENGcm11199 Added ARM Cortex-A8 erratum ENGcm11205 Updated workaround for ENGcm07782 Added CCM erratum ENGcm11208 Added HSC bypass clarification ENGcm08316 Added EMI/M4IF erratum ENGcm11226 Added USB OTG ULPI erratum ENGcm11249 Added clarification on WEIM 8-bit memory devices support ENGcm11244 Added erratum ENGcm11408 for removing HS/FS USB TLL support Updated description of ENGcm10716 Added OneNAND boot erratum ENGcm11353 3 08/2010 • • • • • Changed ENGcm11202 number to ENGcm11226 Added eSDCTL erratum ENGcm08971 Added CCM erratum ENGcm08842 Added ARM NEON erratum ENGcm11422 Added eSDHC erratum ENGcm11403 09/2010 Added Linux and WinCE BSP status information 4 07/2011 Added DPLL erratum ENGcm12051 5 02/2012 • • • • • Substantive Changes Added eSDHC erratum ENGcm12364 Added NFC erratum ENGcm12362 Updated ROM erratum ENGcm10656 Added eSDCTL erratum ENGcm12376 Added EIM erratum ENGcm12378 Chip Errata for the i.MX51, Rev. 5 2 Freescale Semiconductor Table 2 provides a cross-reference to match the revision code to the revision level marked on the device. Table 2. Revision Level to Part Marking Cross-Reference 1 Revision Package Device Marking 1 Mask Set MCIMX51 3.0 19 x 19 mm PCIMX511AJM6C M77X MCIMX51 3.0 19 x 19 mm PCIMX512CJM6C M77X MCIMX51 3.0 19 x 19 mm MCIMX512DJM8C M77X MCIMX51 3.0 19 x 19 mm PCIMX513CJM6C M77X MCIMX51 3.0 19 x 19 mm MCIMX513DJM8C M77X MCIMX51 3.0 19 x 19 mm PCIMX514AJM6C M77X MCIMX51 3.0 19 x 19 mm PCIMX515CJM6C M77X MCIMX51 3.0 19 x 19 mm MCIMX515DJM8C M77X MCIMX51 3.0 19 x 19 mm PCIMX516AJM6C M77X MCIMX51 3.0 13 x 13 mm MCIMX511DVK8C M77X MCIMX51 3.0 13 x 13 mm MCIMX512DVK8C M77X MCIMX51 3.0 13 x 13 mm MCIMX513DVK8C M77X MCIMX51 3.0 13 x 13 mm MCIMX515DVK8C M77X Part numbers with a PC prefix indicate non-production engineering parts. Chip Errata for the i.MX51, Rev. 5 Freescale Semiconductor 3 The following table summarizes errata on thei.MX51 catergorized by module. Table 3. Summary of Silicon Errata Errata Name Solution Page No fix scheduled 11 AIPS ENGcm07298 AIPS: Unaligned access causes abort on writes to the internal registers ARM ENGcm09830 ARM: Load and Store operations on the shared device memory regions may not complete in program order No fix scheduled 12 ENGcm07788 ARM: A RAW hazard on certain CP15 registers can result in a stale register read No fix scheduled 14 ENGcm04786 ARM: ARPROT[0] is incorrectly set to indicate a USER transaction for memory accesses generated from user tablewalks No fix scheduled 16 ENGcm04785 ARM: C15 Cache Selection Register (CSSELR) is not banked No fix scheduled 18 ENGcm07784 ARM: Cache clean memory ops generated by the Preload Engine or Clean by MVA to PoC instructions may corrupt the memory No fix scheduled 19 ENGcm07786 ARM: Under a specific set of conditions, a cache maintenance operation performed by MVA can result in memory corruption No fix scheduled 21 ENGcm07782 ARM: Clean and Clean/Invalidate maintenance ops by MVA to PoC may not push data to external memory No fix scheduled 23 ENGcm04758 ARM: Incorrect L2 cache eviction can occur when L2 is configured as an inner cache No fix scheduled 25 ENGcm04761 ARM: Swap instruction, preload instruction, and instruction fetch request can interact and cause deadlock No fix scheduled 26 ENGcm04759 ARM: NEON load data can be incorrectly forwarded to a subsequent request No fix scheduled 28 ENGcm04760 ARM: Under a specific set of conditions, processor deadlock can occur when L2 cache is servicing write allocate memory No fix scheduled 30 ENGcm10230 ARM: Clarification regarding the ALP bits in AMC register No fix scheduled -Clarified in RM 32 ENGcm10700 ARM: If a Perf Counter OVFL occurs simultaneously with an update to a CP14 or CP15 register, the OVFL status can be lost No fix scheduled 33 ENGcm10716 ARM: A Neon store to device memory can result in dropping a previous store No fix scheduled 35 ENGcm10701 ARM: BTB invalidate by MVA operations do not work as intended when the IBE bit is enabled No fix scheduled 37 ENGcm10703 ARM: Taking a watchpoint is incorrectly prioritized over a precise data abort if both occur simultaneously on the same address No fix scheduled 39 ENGcm10724 ARM: VCVT.f32.u32 can return wrong result for the input 0xFFFF_FF01 in one specific configuration of the floating point unit No fix scheduled 41 Chip Errata for the i.MX51, Rev. 5 4 Freescale Semiconductor Table 3. Summary of Silicon Errata (continued) Errata Name Solution Page ENGcm11205 ARM: Cache maintenance operations by MVA for a non-cacheable memory region can result in processor deadlock No fix scheduled 43 ENGcm11422 ARM: A Neon load from device memory type may result in unpredictable behavior including system hang No fix scheduled 45 CCM ENGcm11208 CCM: ARM clock source switch limitation No fix scheduled 46 ENGcm08842 CCM: System hangs when EMI int1 clock is disabled No fix scheduled 47 No fix scheduled 48 CSPI ENGcm08209 CSPI: Incorrectly clears the overrun status bit DAP ENGcm04789 DAP: Clock synchronization bug prevents access to the IP bus for debug No fix scheduled 49 ENGcm09395 DAP: Debug ROM address in DAP design is incorrect No fix scheduled 50 DPLL ENGcm04750 DPLL: TOG_SEL bit not cleared after the TOG_DIS bit is set No fix scheduled 51 ENGcm12051 DPLL: Meta-stability Issue No fix scheduled 155 eCSPI ENGcm09397 eCSPI: Slave select remains asserted after transfer is complete when the SSB POL = 1 No fix scheduled 52 ENGcm10183 eCSPI Burst completion by SSB signal in Slave mode is not functional No fix scheduled 53 No fix scheduled 160 EIM ENGcm12378 EIM: AUS mode is non functional for devices larger than 32MB EMI ENGcm09421 EMI/SRC: Warm reset can not be issued in sleep mode No fix scheduled 54 ENGcm09424 EMI: Exclusive protocol does not function as defined in the AXI protocol No fix scheduled 55 ENGcm11244 EMI: WEIM 8-bit memory devices support clarification No fix scheduled -Clarified in RM 57 No fix scheduled 58 No fix scheduled 59 EPIT ENGcm04773 EPIT: Possibility of additional pulse on src_clk when switching between clock sources eSDCTL ENGcm06969 eSDCTL: Precharge after write may be delayed Chip Errata for the i.MX51, Rev. 5 Freescale Semiconductor 5 Table 3. Summary of Silicon Errata (continued) Errata Name Solution Page ENGcm08971 eSDCTL: ESDGPR register bits 19 to 31 are not readable No fix scheduled 60 ENGcm12376 eSDCTL: ESDCTLv2 fails to wait the minimal 200uS between DDR clk & clk enable No fix scheduled 159 eSDHC ENGcm06545 eSDHC: Buffer overrun prevents CPU polling reads when WML is set as 1 No fix scheduled 61 ENGcm09111 eSDHC: Cannot finish a write operation after a block gap stop No fix scheduled 62 ENGcm06706 eSDHC: CMD12 does not always stop the clock No fix scheduled 63 ENGcm09107 eSDHC: Does not support Infinite Block Transfer Mode No fix scheduled 64 ENGcm09114 eSDHC: Interrupt is not forwarded to TZIC when HS-I2C is used with SDMA No fix scheduled 65 ENGcm09403 eSDHC: Software can not clear DMA interrupt status bit after read operation No fix scheduled 66 ENGcm09149 eSDHC: Wrong data read from buffer port while WML is 1 No fix scheduled 67 ENGcm10407 eSDHC: Glitch is generated on card clock with software reset or clock divider change No fix scheduled 68 ENGcm11065 eSDHC: ADMA fails when data length in the last descriptor is less or equal to 4 bytes No fix scheduled 69 ENGcm11104 eSDHCv2: ADMA transfer error when the block size is not a multiple of four No fix scheduled 70 ENGcm11161 eSDHCv2: Problem when ADMA2 last descriptor is LINK or NOP No fix scheduled 72 ENGcm09399 eSDHCv2: eSDHC misses SDIO interrupt when CINT is disabled No fix scheduled 73 ENGcm12364 eSDHC AutoCMD12 and R1b polling problem No fix scheduled 157 No fix scheduled 75 No fix scheduled 76 FEC ENGcm04798 FEC: Fast Ethernet Controller (FEC) accesses to NAND Flash Controller (NFC) does not work GPT ENGcm07200 GPT: Possibility of additional pulse on src_clk when switching between clock sources HS-I2C ENGcm09194 HS-I2C: Address Issue No fix scheduled 78 ENGcm08218 HS-I2C: After a read operation, the HS-I2C does not operate properly No fix scheduled 79 ENGcm07892 HS-I2C: Auto Restart not working No fix scheduled 80 ENGcm09179 HS-I2C: Clock Stretching Does not Work No fix scheduled 81 ENGcm07894 HS-I2C: HICR[HIIEN] bit does not mask the interrupts No fix scheduled 82 Chip Errata for the i.MX51, Rev. 5 6 Freescale Semiconductor Table 3. Summary of Silicon Errata (continued) Errata Name Solution Page ENGcm09404 HS-I2C: Read after write from an external device fails No fix scheduled 83 ENGcm07886 HS-I2C: TDC_ZERO and RDC_ZERO status bits are not cleared No fix scheduled 84 2 ENGcm09396 HS-I C: The associated divider of the HIFSFDR does not operate as expected No fix scheduled 85 ENGcm09113 HS-I2C: High Speed mode of HS-I2C does not work No fix scheduled 86 IPU ENGcm09277 IPU: Combining error when setting the global alpha value of IC (Image Converter) to 0xFF No fix scheduled 87 ENGcm09131 IPU/CCM: Configuration for DVFS_PER operation (pixel/EOL/EOF) No fix scheduled 88 ENGcm09634 IPU: CSC1 + Combining + CSC2 Output is Incorrect No fix scheduled 89 ENGcm10295 IPU: Error while combining in IC when two simultaneous tasks are involved No fix scheduled 90 ENGcm08316 IPU: Clarification regarding the bypass mode registers setup for display and camera interfaces No fix scheduled - spec clarification 91 M4IF ENGcm07168 M4IF: Step-by-step mechanism violates AXI protocol No fix scheduled 92 ENGcm10678 M4IF power-saving mode should not be enabled before DDR is configured No fix scheduled 93 ENGcm10709 M4IF: Power-saving restriction on FPST due to DDR No fix scheduled 94 ENGcm11226 M4IF: Reading M4IF status registers of an inactive AXI master or slave stalls entire system No fix scheduled, clarified in RM 95 NFC ENGcm09044 NFC: Auto_erase/auto_program does not latch status correctly No fix scheduled 97 ENGcm09619 NFC: 8-Sym ECC mode does not work with 512 byte page x16 bus NAND Flash No fix scheduled 98 ENGcm09575 NFC: Copy back function destination address restriction No fix scheduled 99 ENGcm09135 NFC: Block write-protect does not support lock-tight No fix scheduled 100 ENGcm06982 NFC: Block write-protect does not work in automatic operations No fix scheduled 101 ENGcm09400 NFC: Copy-back does not work properly when addr_op = 01 No fix scheduled 102 ENGcm09186 NFC: Software reset does not work properly under certain conditions No fix scheduled 103 ENGcm08208 NFC: Status read does not occur at the end of the program, with RBB_MODE = 1 No fix scheduled 104 ENGcm09394 NFC: Unlock registers are reset during warm reset No fix scheduled 105 ENGcm09970 NFC: NFC does not work properly when RBB_MODE = 0 (read status) No fix scheduled 106 Chip Errata for the i.MX51, Rev. 5 Freescale Semiconductor 7 Table 3. Summary of Silicon Errata (continued) Errata Name Solution Page ENGcm09980 NFC: Misses read data when working in Symmetric mode with clock ratio 1:2, and using a 16-bit Flash bus width No fix scheduled 107 ENGcm10033 NFC: Does not Issue DMA read request using 1/2 Kbyte Page in SDMA mode No fix scheduled 108 ENGcm10036 NFC: Cannot reach entire address space when addr_op = 1 or 3 No fix scheduled 109 ENGcm10135 NFC: Incorrect ECC Error Detection when NFC_RST bit is set No fix scheduled 110 ENGcm10150 NFC: Overrides read data in Asymmetric mode using a clock ratio of 1:2, and a 16-bit Flash bus width No fix scheduled 111 ENGcm10158 NFC: Reads only from the last device using addr_op = 2 without read confirmation No fix scheduled 112 ENGcm10176 NFC: Does not work when number of iterations are greater than number of devices No fix scheduled 113 ENGcm10205 NFC Doesn't Protect the Last 10 Spare Bytes of the Last Section in 4KB+218 No fix scheduled 114 ENGcm10245 NFC in RBB_MODE = 1 and atomic operation monitors only rb_b0 instead of the rb_b# of the selected device No fix scheduled 115 ENGcm10356 NFC: ECC mechanism may fail to report uncorrectable error situation No fix scheduled 116 ENGcm10344 NFC fails to transfer data in read burst accesses when rready is deasserted No fix scheduled 117 ENGcm10676 NFC fails to perform ECC encoding in interleave mode if FMP is larger than PS No fix scheduled 118 ENGcm10967 NFC does not function properly for 4 Kbyte Page Size in interleave mode No fix scheduled 120 ENGcm11043 NFC issues premature DMA read request in case of TOO configuration in interleave mode No fix scheduled 121 ENGcm11060 NFC does not perform automatic status read operation (AUTO_STAT) according to ACTIVE_CS No fix scheduled 122 ENGcm11004 NFC can miss the sampling of the ready/busy signal (R/B) when RBB_MODE = 1 No fix scheduled 123 ENGcm11036 SDMA multi-page read from the NFC, when the WEIM is operating, can result in data corruption or EMI hanging No fix scheduled 124 ENGcm12362 NFC wrong indication of ECC uncorrectable error occurrence after reading the spare area No fix scheduled 158 Power Supply ENGcm10640 Grounding nonfunctional UHVIO IO pads power rails can cause malfunction in other UHVIO IO cells No fix scheduled 125 ENGcm11041 Dependency between VCC, VREG and NVCC_HSx supplies No fix scheduled 126 ROM (Boot Code) Chip Errata for the i.MX51, Rev. 5 8 Freescale Semiconductor Table 3. Summary of Silicon Errata (continued) Errata Name Solution Page ENGcm10656 Serial boot will fail if HAB_TYPE is PRODUCTION No fix scheduled 127 ENGcm11189 ROM (Boot)/NFC: NAND Flash Boot fails when one of the unused NANDF_RBx signals are held at low No fix scheduled 128 RTIC ENGcm05863 RTIC: Software reset during one time hash mode corrupts RTIC state machine No fix scheduled 130 ENGcm10974 RTICv3 memory region unlock feature can cause the RTICv3 to hang No fix scheduled 131 No fix scheduled 132 No fix scheduled 133 SAHARA ENGcm10334 SAHARA/CCM: Frequency ratio restriction for AHB and IP buses in SAHARA SRTC ENGcm10272 SRTC: Possible status loss when peripheral power resumes if SRTC in fail state SSI ENGcm06571 SSI: Data Tx starts from FIFO1 in case Rx is enabled before Tx in sync mode No fix scheduled 135 ENGcm09220 SSI: If TX_EN bit toggled 5 clk cycles before FS, the data transmission not correct No fix scheduled 136 ENGcm09222 SSI: Normal Async, Tx is disabled 2 clocks before FS, ddr_stxd is indefinitely high No fix scheduled 137 ENGcm06569 SSI: Transmission does not take place in case of bit length early frame sync mode No fix scheduled 138 ENGcm09212 SSI: With TFR bit set, Rx re-enabled, data not accepted according to masking No fix scheduled 139 ENGcm09668 SSI: Receive Overrun Error Generated at Wrong Time for Watermark Level No fix scheduled 140 ENGcm11138 SSI: In AC97, 16-bit mode, received data is shifted by four bit locations No fix scheduled 141 USB ENGcm09134 USB: Core device fails to receive two sequential OUT transactions in short time No fix scheduled 142 ENGcm09110 USB: Device mode ISO error problem No fix scheduled 143 ENGcm07300 USB: Erroneous descriptor handling by USBOH module No fix scheduled 144 ENGcm10636 USB: Issue when USB_CLK_ROOT Clock is enabled while PHCD bit is set No fix scheduled 145 ENGcm11249 USB: USB-OTG port ULPI interface is not supported No fix scheduled, clarified in RM 147 Chip Errata for the i.MX51, Rev. 5 Freescale Semiconductor 9 Table 3. Summary of Silicon Errata (continued) Errata Name Solution Page ENGcm11408 USB: High Speed Transceiverless Logic interface (HS-TLL) and Full Speed Transceiverless Logic interface (FS-TLL) USB interfaces are not supported No fix scheduled, feature removed from the RM 148 Case 1 - no fix scheduled Cases 2 and 3 - fixed in last firmware release for silicon rev. 2.0 and rev 3.0 149 VPU ENGcm09125 VPU: VC-1 AP bug ENGcm10253 VPU H.263-P3 decoding Advanced Intra coding (Annex I) bug No fix scheduled 151 ENGcm10260 VPU DivX V3.11 Variable-length-decoding (VLC) bug No fix scheduled 152 ENGcm10388 VPU: MPEG-1 full-pel Motion Vector Update Failure Fixed in firmware 153 ENGcm10390 VPU: JPEG decoder does not support different AC/DC Huffman tables for Cb and Cr No fix scheduled 154 Chip Errata for the i.MX51, Rev. 5 10 Freescale Semiconductor ENGcm07298 ENGcm07298 AIPS: Unaligned access causes abort on writes to the internal registers Description: Unaligned access to AIPS can be driven high by SAHARA, DAP, and FEC. If they access the AIPS internal registers during an unaligned access, an ABORT occurs. Projected Impact: Unaligned accesses to the AIPS internal registers fail. Workarounds: Make only aligned accesses to the AIPS internal registers. Proposed Solution: No fix scheduled Linux BSP Status: No software workaround required. Linux BSP does not use unaligned access to the AIPS registers. WinCE BSP Status: No software workaround required. WinCE BSP does not use unaligned access to the AIPS registers. Chip Errata for the i.MX51, Rev. 5 Freescale Semiconductor 11 ENGcm09830 ENGcm09830 ARM: Load and Store operations on the shared device memory regions may not complete in program order Description: If a sequence of load and store operations are performed to different address locations in a memory region that is marked as shared device, then a load can incorrectly bypass a store. The issue is reported by ARM, erratum ID 709718, Category 21. Projected Impact: If the load address and store address are mapped to access the memory region of the same device, and the device relies on memory operations to occur in program order, then this device may not operate as intended. Workarounds: The erratum occurs only for the shared device memory regions and not for the non-shared device memory regions. Therefore, this problem can be worked around by using the remap registers to remap all the shared device transactions to the non-shared device. The only difference between the shared device and the non-shared device is the attributes produced for the transaction on the AXI interface. Therefore, the user does not experience any impact in terms of performance from this workaround. Another possible use of the TEX remap is to map the shared device regions to the strongly ordered transactions. This second remapping option is less desirable as it affects the performance, as strongly ordered transactions are not buffered. The following code sequence is required to setup and enable the TEX remap. This should be done before enabling the MMU. ; Setup MRC BIC MCR PRRR so device is always mapped to non-shared p15, 0, r0, c10, c2, 0; Read Primary Region Remap Register r0,#3