Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51AEC
Rev. 6, 10/2012
IMX51A
i.MX51A Automotive and
Infotainment Applications
Processors
Package Information
Plastic Package
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 2 for ordering information.
1
Introduction
The MCIMX51A (i.MX51A) Automotive Infotainment
Processor represents Freescale Semiconductor’s latest
addition to a growing family of multimedia focused
products offering high performance processing with a
high degree of functional integration, aimed at the
growing automotive infotainment market. This device
includes two graphics processors, 720p video
processing, dual display, and many I/Os.
The i.MX51A processor features Freescale’s advanced
implementation of the ARM Cortex A8™ core, targeting
speeds up to 600 MHz with 200 MHz I/O bus clock
DDR2 and mobile DDR. This device is well-suited for
graphics rendering for HMI and navigation, high
performance speech processing with large databases,
video processing and display, audio playback and
ripping, and many other applications.
© 2012 Freescale Semiconductor, Inc. All rights reserved.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 11
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 13
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 14
3.3. I2C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 14
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 15
3.5. Wireless External Interface Module (WEIM) . . . . 15
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 15
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 15
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4. Output Buffer Impedance Characteristics . . . . . . 29
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 72
5. Package Information and Contact Assignments . . . . . 151
5.1. 19 x 19 mm Package Information . . . . . . . . . . . . 151
5.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Introduction
Features of the i.MX51A processor include the following:
• Smart Speed Technology—The i.MX51A device has power management throughout the IC that
enables the rich suite of multimedia feature and peripherals to achieve minimum power
consumption in both active and various low power modes. Smart Speed Technology enables the
designer to deliver a feature-rich product that requires levels of power that are far less than industry
expectations.
• Multimedia—The multimedia performance of the ARM Cortex A8 is enhanced with a multi-level
cache system, a Multi-standard Hardware Video CODECs, autonomous image processing unit,
multi-standard audio CODECs, Neon (an advanced SIMD, 32 bit single-precision floating point
support and vector floating point co-processor), and a programmable smart DMA controller.
• Powerful Graphics Acceleration—The i.MX51A processor has an integrated Graphics Processing
Unit which includes an OpenGl 2.0 GPU that provides 27Mtri/sec, 166Mpix/s, and 664Mpix/s
z-plane performance. Silicon version 2.0 of the i.MX51A device includes an independent OpenVG
GPU operating at166Mpix/s.
• Interface Flexibility—The i.MX51A processor supports connections to all popular types of
external memories: mobile DDR, DDR2, PSRAM, NOR Flash, NAND Flash (MLC and SLC), and
OneNAND (managed NAND). The i.MX51A processor also includes a rich multimedia suite of
interfaces: LCD controller for two displays, CMOS sensor interface, High-Speed USB On-The-Go
plus three High-Speed USB hosts, high-speed MMC/SDIO, Fast Ethernet controller, UART, I2C,
I2S (SSI), and others.
1.1
Ordering Information
Table 1 provides the ordering information.
Table 1. Ordering Information
Part Number
Mask Set
Features
Junction
Temperature
Range (°C)
Package 1
MCIMX514AJM6C
M77X
No hardware video codecs
–40 to 125
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
MCIMX516AJM6C
M77X
Full specification
–40 to 125
19 x 19 mm, 0.8 mm pitch BGA
Case 2017
1
Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.
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Introduction
1.2
Block Diagram
NOR/Nand Battery Ctrl
Device
Flash
DDR
Memory
Digital
Audio
USB
Dev/Host
USB PHY
External
Memory I/F
Camera 1
Camera 2
LCD Display 1
LCD Display 2
TV-Out
Figure 1 shows the functional modules of the processor.
ATA HDD
Application Processor Domain (AP)
TV Encoder
Image Processing
Subsystem
USB OTG +
3 HS Ports
AP Peripherals
eCSPI (2)
CSPI
Ethernet
Smart DMA
(SDMA)
UART (3)
AUDMUX
GPS
Internal
RAM
(128 Kbytes)
SDMA Peripherals
eSDHC (4)
SSI
UART
eCSPI (1 of 2)
SPDIF Tx
SIM
FEC
P-ATA
Boot
ROM
RF/IF ICs
Security
SAHARA
Lite
RTIC
AXI and AHB Switch Fabric
SPBA
SCC
ARM Cortex A8
Platform
I2C(2),HSI 2C
ARM Cortex A8
PWM (2)
1-WIRE
Neon and VFP
IIM
L1 I/D cache
IOMUXC
L2 cache
KPP
ETM, CTI0,1
GPIOx32 (4)
SJC
SSI (3)
Video
Proc. Unit
(VPU)
FIRI
Debug
3D Graphics
Proc Unit
(GPU)
SRTC
CSU
DAP
TPIU
SIM
CTI (2)
TZIC
Fuse Box
Graphics
Memory
(128 Kbytes)
Timers
WDOG (2)
Clock and Reset
PLL (3)
CCM
Audio/Power
Management
GPC
GPT
2D Graphics
Proc Unit
(GPU2D)
EPIT (2)
JTAG
IrDA
XVR
Bluetooth
WLAN
USB-OTG
XVR
MMC/SDIO
SRC
XTALOSC
CAMP (2)
Keypad
Access.
Conn.
Figure 1. Functional Block Diagram
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Features
2
Features
The i.MX51A processor contains a large number of digital and analog modules that are described in
Table 2.
Table 2. i.MX51A Digital and Analog Modules
Block
Mnemonic
1-WIRE
Block Name
Subsystem
Brief Description
1-Wire
Interface
Connectivity
Peripherals
1-Wire support provided for interfacing with an on-board EEPROM, and smart
battery interfaces, for example: Dallas DS2502.
ARM
Cortex™-A8
ARM
Cortex™-A8
Platform
ARM
The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8
processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains
the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data
cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor
and Debug modules. It also has a NEON co-processor with SIMD media
processing architecture, register file with 32 × 64-bit general-purpose registers,
an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating
point execute pipeline (FADD, FMUL), load/store and permute pipeline and a
Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).
Audio
Subsystem
Audio
Subsystem
Multimedia
Peripherals
The elements of the audio subsystem are three Synchronous Serial Interfaces
(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).
See the specific interface listings in this table.
Digital Audio
Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports (three internal and four external) with identical
functionality and programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
AUDMUX
CCM
GPC
SRC
These modules are responsible for clock and reset distribution in the system,
Clock Control Clocks,
and also for system power management. The modules include three PLLs and
Resets, and
Module
Global Power Power Control a Frequency Pre-Multiplier (FPM).
Controller
System Reset
Controller
CSPI-1,
eCSPI-2
eCSPI-3
Configurable
SPI,
Enhanced
CSPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface, with data rate up to
66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave
modes, four chip selects to support multiple peripherals.
CSU
Central
Security Unit
Security
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX51 platform, and for sharing security information
between the various security modules. The Security Control Registers (SCR) of
the CSU are set during boot time by the High Assurance Boot (HAB) code and
are locked to prevent further writing.
Debug
System
System
Control
The Debug System provides real-time trace debug capability of both instructions
and data. It supports a trace protocol that is an integral part of the ARM Real
Time Debug solution (RealView). Real-time tracing is controlled by specifying a
set of triggering and filtering resources, which include address and data
comparators, cross-system triggers, counters, and sequencers.
Debug
System
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
EMI
EPIT-1
EPIT-2
eSDHC-1
eSDHC-2
eSDHC-3
Block Name
Subsystem
Brief Description
External
Memory
Interface
Connectivity
Peripherals
The EMI is an external and internal memory interface. It performs arbitration
between multi-AXI masters to multi-memory controllers, divided into four major
channels: fast memories (Mobile DDR, DDR2) channel, slow memories
(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory
(RAM, ROM) channel and graphical memory (GMEM) Channel.
In order to increase the bandwidth performance, the EMI separates the buffering
and the arbitration between different channels so parallel accesses can occur.
By separating the channels, slow accesses do not interfere with fast accesses.
EMI features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and what
type (Read or Write) was the last access
• Flexible bank interleaving
• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)
• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)
• Supports up to 2 Gbit Mobile DDR memories
• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async
operating modes), at slow frequency, for debugging purposes
• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow
frequencies for debugging purposes
• Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes
• NAND-Flash (including MLC)
• Multiple chip selects
• Enhanced Mobile DDR memory controller, supporting access latency hiding
• Supports watermarking for security (Internal and external memories)
• Supports Samsung OneNAND™ (only in muxed I/O mode)
Enhanced
Periodic
Interrupt
Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is
enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for division
of input clock frequency to get the required time setting for the interrupts to occur,
and counter values can be programmed on the fly.
Connectivity
Enhanced
Peripherals
Multi-Media
Card/
Secure Digital
Host
Controller
The features of the eSDHC module, when serving as host, include the following:
• Conforms to SD Host Controller Standard Specification version 2.0
• Compatible with the MMC System Specification version 4.2
• Compatible with the SD Memory Card Specification version 2.0
• Compatible with the SDIO Card Specification version 1.2
• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
Combo, MMC and MMC RS cards
• Configurable to work in one of the following modes:
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
• Full-/high-speed mode
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
eSDHC-4
(muxed with
P-ATA)
Connectivity
Enhanced
Peripherals
Multi-Media
Card/
Secure Digital
Host
Controller
Can be configured as eSDHC (see above) and is muxed with the P-ATA
interface.
FEC
Fast Ethernet Connectivity
Controller
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support both
10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media.
FIRI
Fast
Infra-Red
Interface
Connectivity
Peripherals
Fast Infra-Red Interface
General
Purpose I/O
Modules
System
Control
Peripherals
These modules are used for general purpose input/output to external ICs. Each
GPIO module supports up to 32 bits of I/O.
GPT
General
Purpose
Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event, and can be configured to trigger
a capture event on either the leading or trailing edges of an input pulse. When
the timer is configured to operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with minimal processor
intervention. The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on an external
clock or on an internal clock.
GPU
Graphics
Processing
Unit
Multimedia
Peripherals
The GPU provides hardware acceleration for 2D and 3D graphics
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720
resolution. It supports color representation up to 32 bits per pixel.
The GPU with its 128 KByte memory enables high performance mobile 3D and
2D vector graphics at rates up to 27 Mtriangles/sec, 166 Mpixels/sec,
664 Mpixels/sec (Z).
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPU2D
Multimedia
Graphics
Peripherals
Processing
Unit-2D Ver. 1
The GPU2D provides hardware acceleration for 2D graphic
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD720 resolution.
I2C-1
I2C-2
HS-I2C
I2C Interface
I2C provides serial interface for controlling peripheral devices. Data rates of up
to 400 Kbps are supported by two of the I2C ports. Data rates of up to 3.4 Mbps
(I2C Specification v2.1) are supported by the HS-I2C.
Note: See the errata for the HS-I2C in the i.MX51 Chip Errata. The two standard
I2C modules have no errata.
Connectivity
Peripherals
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
IIM
IOMUXC
IPU
Block Name
Subsystem
Brief Description
IC
Identification
Module
Security
The IC Identification Module (IIM) provides an interface for reading,
programming, and/or overriding identification and control information stored in
on-chip fuse elements. The module supports electrically programmable poly
fuses (e-Fuses). The IIM also provides a set of volatile software-accessible
signals that can be used for software control of hardware elements not requiring
non-volatility. The IIM provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are unique
chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals requiring permanent
non-volatility. The IIM also provides up to 28 volatile control signals. The IIM
consists of a master controller, a software fuse value shadow cache, and a set
of registers to hold the values of signals visible outside the module.
IOMUX
Control
System
Control
Peripherals
This module enables flexible I/O multiplexing. Each I/O pad has default as well
as several alternate functions. The alternate functions are software configurable.
Image
Processing
Unit
Multimedia
Peripherals
IPU enables connectivity to displays and image sensors, relevant processing
and synchronization. It supports two display ports and two camera ports,
through the following interfaces.
• Legacy Interfaces
• Analog TV interfaces (through a TV encoder bridge)
The processing includes:
• Support for camera control
• Image enhancement: color adjustment and gamut mapping, gamma
correction and contrast enhancement, sharpening and noise reduction
• Video/graphics combining
• Support for display backlight reduction
• Image conversion—resizing, rotation, inversion and color space conversion
• Synchronization and control capabilities, allowing autonomous operation.
• Hardware de-interlacing support
Keypad Port
Connectivity
Peripherals
The KPP supports an 8 × 8 external keypad matrix. The KPP features are as
follows:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
P-ATA (Muxed Parallel ATA
with
eSDHC-4
Connectivity
Peripherals
The P-ATA block is an AT attachment host interface. Its main use is to interface
with hard disc drives and optical disc drives. It interfaces with the ATA-5
(UDMA-4) compliant device over a number of ATA signals. It is possible to
connect a bus buffer between the host side and the device side. This is muxed
with eSDHC-4 interfaces.
KPP
PWM-1
PWM-2
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate tones.
The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.
RAM
128 Kbytes
Internal RAM
Internal
Memory
Unified RAM, can be split between Secure RAM and Non-Secure RAM
ROM
36 Kbytes
Boot ROM
Internal
Memory
Supports secure and regular Boot Modes
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
RTIC
Block Name
SDMA
SIM
Brief Description
Security
Protecting read-only data from modification is one of the basic elements in
trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data
monitoring device responsible for ensuring that memory content is not corrupted
during program execution. The RTICv3 mechanism periodically checks the
integrity of code or data sections during normal OS run-time execution without
interfering with normal operation. The RTICv3’s purpose is to ensure the integrity
of the peripheral memory contents, protect against unauthorized external
memory elements replacement, and assist with boot authentication.
Security
SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a
security co-processor. It implements symmetric encryption algorithms, (AES,
DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1,
SHA-224, and SHA-256), and a hardware random number generator. It has a
slave IP bus interface for the host to write configuration and command
information, and to read status information. It also has a DMA controller, with an
AHB bus interface, to reduce the burden on the host to move the required data
to and from memory.
Security
Controller
Security
The Security Controller is a security assurance hardware module designed to
safely hold sensitive data such as encryption keys, digital right management
(DRM) keys, passwords, and biometrics reference data. The SCC monitors the
system’s alert signal to determine if the data paths to and from it are
secure—that is, cannot be accessed from outside of the defined security
perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also
features a Key Encryption Module (KEM) that allows non-volatile (external
memory) storage of any sensitive data that is temporarily not in use. The KEM
utilizes a device-specific hidden secret key and a symmetric cryptographic
algorithm to transform the sensitive data into encrypted data.
Smart Direct
Memory
Access
System
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system
performance by off loading various cores in dynamic data routing.
The SDMA features list is as follows:
• Powered by a 16-bit instruction-set micro-RISC engine
• Multi-channel DMA supports up to 32 time-division multiplexed DMA channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM Cortex™-A8 and SDMA
• Very fast context-switching with two-level priority-based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement, and
no address changes on source and destination address)
• DMA ports can handle unit-directional and bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers for EMI
• Support of byte-swapping and CRC calculations
• A library of scripts and API are available
Subscriber
Identity
Module
Interface
Connectivity
Peripherals
The SIM is an asynchronous interface with additional features for allowing
communication with Smart Cards conforming to the ISO 7816 specification. The
SIM is designed to facilitate communication to SIM cards or pre-paid phone
cards.
Real Time
Integrity
Checker
SAHARA Lite SAHARA
security
accelerator
Lite
SCC
Subsystem
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
SJC
Block Name
Secure JTAG
Interface
Subsystem
System
Control
Peripherals
Brief Description
JTAG manipulation is a known hacker’s method of executing unauthorized
program code, getting control over secure applications, and running code in
privileged modes. The JTAG port provides a debug access to several hardware
blocks including the ARM processor and the system bus.
The JTAG port must be accessible during platform initial laboratory bring-up,
manufacturing tests and troubleshooting, as well as for software debugging by
authorized entities. However, in order to properly secure the system,
unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access for manufacturing
tests and software debugging, the i.MX51A processor incorporates a
mechanism for regulating JTAG access. The i.MX51A Secure JTAG Controller
provides four different JTAG security modes that can be selected via e-fuse
configuration.
SPBA
Shared
Peripheral
Bus Arbiter
System
Control
Peripherals
SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus)
arbiter.
SPDIF
Sony Philips
Digital
Interface
Multimedia
Peripherals
A standard digital audio transmission protocol developed jointly by the Sony and
Philips corporations. Only the transmitter functionality is supported.
SRTC
Secure Real
Time Clock
Security
The SRTC incorporates a special System State Retention Register (SSRR) that
stores system parameters during system shutdown modes. This register and all
SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The
NVCC_SRTC_POW can be energized even if all other supply rails are shut
down. The power for this block comes from NVCC_SRTC_POW supply. When
this supply is driven by the MC13892 power management controller, this block
can be power backed up via the coin-cell feature of the MC13892.This register
is helpful for storing warm boot parameters. The SSRR also stores the system
security state. In case of a security violation, the SSRR mark the event (security
violation indication).
SSI-1
I2S/SSI/AC97 Connectivity
Interface
Peripherals
The SSI is a full-duplex synchronous interface used on the i.MX51A processor
to provide connectivity with off-chip audio peripherals. The SSI interfaces
connect internally to the AUDMUX which interfaces to the i.MX51 system
memory. The SSI supports a wide variety of protocols (SSI normal, SSI network,
I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync
options.
Each SSI has two pairs of 8x24 FIFOs and hardware support for an external
DMA controller in order to minimize its impact on system performance. The
second pair of FIFOs provides hardware interleaving of a second audio stream,
which reduces CPU overhead in use cases where two timeslots are being used
simultaneously.
TV Encoder
The TVE is implemented in conjunction with the Image Processing Unit (IPU)
allowing handheld devices to display captured still images and
video directly on a TV or LCD projector. It supports the following analog video
outputs: composite, S-video, and component video up to HD720p/1080i.
SSI-2
SSI-3
TVE
Multimedia
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
TZIC
TrustZone
Aware
Interrupt
Controller
ARM/Control
The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all
i.MX51 sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
UART-1
UART-2
UART-3
UART
Interface
Connectivity
Peripherals
Each of the UART modules supports the following serial data transmit/receive
protocols and configurations:
• 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or
none)
• Programmable baud rates up to 4 MHz. This is a higher max baud rate relative
to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and
previous Freescale UART modules.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB
USB 2.0
High-Speed
OTG and 3x
Hosts
Connectivity
Peripherals
USB-OTG contains one high-speed OTG module, which is internally connected
to the on-chip HS USB PHY. There are an additional three high-speed host
modules that require external USB PHYs.
VPU
Video
Processing
Unit
Multimedia
Peripherals
A high-performing video processing unit (VPU), which covers many SD-level
video decoders and SD-level encoders as a multi-standard video codec engine
as well as several important video processing such as rotation and mirroring.
VPU Features:
• MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile
• MPEG-4 encode: D1, 25/30 fps, simple profile
• H.263 decode: 720p, 30 fps, profile 3
• H.263 encode: D1, 25/30 fps, profile 3
• H.264 decode: 720p, 30 fps, baseline, main, and high profile
• H.264 encode: D1, 25/30 fps, baseline profile
• MPEG-2 decode: 720p, 30 fps, MP-ML
• MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration
in hardware)
• VC-1 decode: 720p, 30 fps, simple, main, and advanced profile
• DivX decode: 720p, 30 fps versions 3, 4, and 5
• RV10 decode: 720p, 30 fps
• MJPEG decode: 32 Mpix/s
• MJPEG encode: 64 Mpix/s
WDOG-1
Watch Dog
Timer
Peripherals
The Watch Dog Timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt to the
ARM core, and a second point evokes an external event on the WDOG line.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
10
Freescale Semiconductor
Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
WDOG-2
(TZ)
Watch Dog
(TrustZone)
Timer
Peripherals
The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone
starvation by providing a method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the normal OS prevents
switching to the TZ mode. This situation should be avoided, as it can
compromise the system’s security. Once the TZ WDOG module is activated, it
must be serviced by TZ software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped
interrupt that forces switching to the TZ mode. If it is still not served, the TZ
WDOG asserts a security violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal mode SW.
XTALOSC
Crystal
Oscillator I/F
Clocking
The XTALOSC module allows connectivity to an external crystal.
2.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX51. The signal names are listed in alphabetical order.
The package contact assignments are found in Section 5, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX51 Multimedia Applications Processor
Reference Manual (MCIMX51RM).
Table 3. Special Signal Considerations
Signal Name
Remarks
CKIH1, CKIH2
Inputs feeding CAMPs (Clock Amplifiers) that have on-chip ac coupling precluding the need for
external coupling capacitors. The CAMPs are enabled by default, but the main clocks feeding the
on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a low jitter
external oscillators to feed CKIH1 or CKIH2 (while not required) can be an advantage if low jitter
or special frequency clock sources are required by modules driven by CKIH1 or CKIH2. See CCM
chapter in the i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for
details on the respective clock trees.
After initialization, the CAMPs could be disabled (if not used) by CCM registers (CCR CAMPx_EN
field). If disabled, the on-chip CAMP output is low; the input is irrelevant. If unused, the user should
tie CKIH1/CKIH2 to GND for best practice.
CLK_SS
Clock Source Select is the input that selects the default reference clock source providing input to
the DPLLs. To use a reference in the megahertz range per Table 8, tie CLK_SS to GND to select
EXTAL/XTAL. To use a reference in the kilohertz range per Table 59, tie CLK_SS to NVCC_PER3
to select CKIL. After initialization, the reference clock source can be changed (initial setting is
overwritten).
Note: Because this input has a keeper circuit, Freescale recommends tying this input to directly
to GND or NVCC_PER3. If a series resistor is used its value must be ≤ 4.7 kΩ.
COMP
The user should bypass this reference with an external 0.1 µ F capacitor tied to GND. If TV OUT is
not used, float the COMP contact and ensure the DACs are powered down.
Note: Previous engineering samples required this reference to be bypassed to a positive supply.
FASTR_ANA and
FASTR_DIG
These signals are reserved for Freescale manufacturing use only. User must tie both connections
to GND.
GPANAIO
This signal is reserved for Freescale manufacturing use only. Users should float this output.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
11
Features
Table 3. Special Signal Considerations (continued)
Signal Name
Remarks
GPIO_NAND
This is a general-purpose input/output (GPIO3_12) on the NVCC_NANDF_A power rail.
IOB, IOG, IOR,
IOB_BACK, IOG_BACK,
and IOR_BACK
These signals are analog TV outputs that should be tied to GND when not being used.
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an
external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX51 Multimedia Applications Processor
Reference Manual (MCIMX51RM). Both names refer to the same signal. JTAG_MOD must be
externally connected to GND for normal operation. Termination to GND through an external
pull-down resistor (such as 1 kΩ) is allowed.
NC
These signals are No Connect (NC) and should be floated by the user.
PMIC_INT_REQ
When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input
on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 kΩ to 68 kΩ resistor.
This avoids a continuous current drain on the real-time clock backup battery due to a 100 kΩ
on-chip pull-up resistor.
PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP
requires that the general-purpose INT output from the MC13892 be connected to the i.MX51 GPIO
input GPIO1_8 configured to cause an interrupt that is not high-priority.
The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the
battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 =
power fail).
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
Note: The POR_B input must be immediately asserted at power-up and remain asserted until
after the last power rail is at its working voltage.
RESET_IN_B
This warm reset negative logic input resets all modules and logic except for the following:
• Test logic (JTAG, IOMUXC, DAP)
• SRTC
• Memory repair – Configuration of memory repair per fuse settings
• Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter
in i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for details.
RREFEXT
Determines the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1%
resistor to GND is required.
SGND, SVCC, and
SVDDGP
These sense lines provide the ability to sense actual on-chip voltage levels on their respective
supplies. SGND monitors differentials of the on-chip ground versus an external power source.
SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends connection
of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test
points.
STR
This signal is reserved for Freescale manufacturing use. The user should float this signal.
TEST_MODE
TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip
pull-down device. Users must either float this signal or tie it to GND.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
12
Freescale Semiconductor
IOMUX Configuration for Boot Media
Table 3. Special Signal Considerations (continued)
Signal Name
Remarks
VREF
When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the
NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a
1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor
with a closely-mounted 0.1 µF capacitor.
To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with
recommended tolerances ensures the ± 2% VREF tolerance (per the DDR-2 specification) is
maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider.
Note: When VREF is used with mDDR this signal must be tied to GND.
VREFOUT
This signal determines the Triple Video DAC (TVDAC) reference voltage. The user must tie
VREFOUT to an external 1.05 kΩ 1% resistor to GND.
VREG
This regulator is no longer used and should be floated by the user.
XTAL/EXTAL
The user should tie a fundamental-mode crystal across XTAL and EXTAL. The crystal must be
rated for a maximum drive level of 100 μW or higher. An ESR (equivalent series resistance) of
80 Ω or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz
on EXTAL.
The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must
be directly driven by the external oscillator and XTAL is floated. The EXTAL signal level must swing
from NVCC_OSC to GND. If the clock is used for USB, then there are strict jitter requirements: < 50
ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY. The
COSC_EN bit in the CCM (Clock Control Module) must be cleared to put the on-chip oscillator
circuit in bypass mode which allows EXTAL to be externally driven. COSC_EN is bit 12 in the CCR
register of the CCM.
Table 4. JTAG Controller Interface Summary
JTAG
I/O Type
On-Chip Termination
JTAG_TCK
Input
100 kΩ pull-down
JTAG_TMS
Input
47 kΩ pull-up
JTAG_TDI
Input
47 kΩ pull-up
JTAG_TDO
3-state output
Keeper
Input
47 kΩ pull-up
JTAG_DE_B
Input/open-drain output
47 kΩ pull-up
JTAG_MOD
Input
100 kΩ pull-up
JTAG_TRSTB
3
IOMUX Configuration for Boot Media
The information provided in this section describes the contacts assigned for each type of bootable media.
It also includes data about the clocks used during boot flow and their frequencies. Signals that can be
multiplexed appear in tables throughout this section. See the IOMUXC chapter in the i.MX51 Multimedia
Applications Processor Reference Manual (MCIMX51RM) for details about how to program the IOMUX
controller.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
13
IOMUX Configuration for Boot Media
3.1
NAND
The NAND Flash Controller (NFC) signals are not configured in the IOMUX. The NFC interface uses
dedicated contacts on the IC.
3.2
SD/MMC IOMUX Pin Configuration
Table 5 shows the SD/MMC IOMUX pin configuration.
Table 5. SD/MMC IOMUX Pin Configuration
1
Signal
eSDHC1
eSDHC2
eSDHC3
eSDHC4
CLK
SD1_CLK.alt0
SD2_CLK.alt0
NANDF_RDY_INT.alt5
NANDF_CS2.alt5
CMD
SD1_CMD.alt0
SD2_CMD.alt0
NANDF_CS7.alt5
NANDF_RB1.alt5
DAT0
SD1_DATA0.alt0
SD2_DATA0.alt0
NANDF_WE_B.alt2
NANDF_CS3.alt5
DAT1
N/A1
N/A
N/A
N/A
DAT2
N/A
N/A
N/A
N/A
CD/DAT3
SD1_DATA3.alt0
SD2_DATA3.alt0
NANDF_RB0.alt5
NANDF_CS6.alt5
DAT4
N/A
N/A
N/A
N/A
DAT5
N/A
N/A
N/A
N/A
DAT6
N/A
N/A
N/A
N/A
DAT7
N/A
N/A
N/A
N/A
N/A in the ROM code indicates the pins are not available.
Only DAT0 is available when the SD/MMC is used for boot. The remaining lines (DAT1–DAT7) are not
available.
3.3
I2C IOMUX Pin Configuration
The contacts assigned to the signals used by the three I2C modules is shown in Table 6.
Table 6. I2C IOMUX Pin Configuration
Signal
HSI2C
I2C1
I2C2
SDA
I2C1_DAT.alt0
I2C1_DAT.alt0
GPIO1_3.alt2
SCL
I2C1_CLK.alt0
I2C1_CLK.alt0
GPIO1_2.alt2
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
14
Freescale Semiconductor
IOMUX Configuration for Boot Media
3.4
eCSPI/CSPI IOMUX Pin Configuration
The contacts assigned to the signals used by the three SPI modules is shown in Table 7.
Table 7. SPI IOMUX Pin Configuration
1
Signal
eCSPI1
eCSPI2
CSPI
MISO
CSPI1_MISO.alt0
NANDF_RB3.alt2
USBH1_NXT.alt1
MOSI
CSPI1_MOSI.alt0
NANDF_D15.alt2
USBH1_DIR.alt1
RDY
CSPI1_RDY.alt0
NANDF_RB1.alt2
USBH1_STP.alt1
SCLK
CSPI1_SCLK.alt0
NANDF_RB2.alt2
USBH1_CLK.alt1
SS0
N/A1
N/A
N/A
SS1
N/A
N/A
USBH1_DATA5.alt1
SS2
N/A
N/A
N/A
SS3
N/A
N/A
N/A
N/A in the ROM code indicates the pins are not available.
3.5
Wireless External Interface Module (WEIM)
The WEIM interface signals are not configured in the IOMUX. The WEIM interface uses dedicated
contacts on the IC.
3.6
UART IOMUX Pin Configuration
The contacts assigned to the signals used by the three UART modules are shown in Table 8.
Table 8. UART IOMUX Pin Configuration
3.7
Signal
UART1
UART2
UART3
TXD
UART1_TXD.alt0
UART2_TXD.alt0
UART3_TXD.alt1
RXD
UART1_RXD.alt0
UART2_RXD.alt0
UART3_RXD.alt1
CTS
UART1_CTS.alt0
USBH1_DATA0.alt1
KEY_COL5.alt2
RTS
UART1_RTS.alt0
USBH1_DATA3.alt1
KEY_COL4.alt2
USB-OTG IOMUX Pin Configuration
The interface signals of the UTMI PHY are not configured in the IOMUX. The UTMI PHY interface uses
dedicated contacts on the IC.
Table 9. ULPI PHY IOMUX Pin Configuration
Signal
ULPI PHY
USB_PWR
GPIO1_8.alt1
USB_OC
GPIO1_9.alt1
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
15
Electrical Characteristics
Table 9. ULPI PHY IOMUX Pin Configuration (continued)
Signal
ULPI PHY
USBOTG_CLK
EIM_CS4.alt2
USBOTG_NXT
EIM_CS3.alt2
USBOTG_STP
EIM_CS2.alt2
USBOTG_DAT0
EIM_D24.alt2
USBOTG_DAT1
EIM_D25.alt2
USBOTG_DAT2
EIM_D26.alt2
USBOTG_DAT3
EIM_D27.alt2
USBOTG_DAT4
EIM_D28.alt2
USBOTG_DAT5
EIM_D29.alt2
USBOTG_DAT6
EIM_D30.alt2
USBOTG_DAT7
EIM_D31.alt2
NOTE
USB OTG ULPI port is not supported and it is not functional. On-chip PHY
is always used for the OTG port.
4
Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX51A processor.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 10 for a quick
reference to the individual tables and sections.
Table 10. i.MX51A Chip-Level Conditions
For these characteristics, …
Topic appears …
Table 11, “Absolute Maximum Ratings”
on page 17
Table 12, “Thermal Resistance Data”
on page 17
Table 13, “i.MX51A Operating Ranges”
on page 18
Table 14, “Interface Frequency”
on page 19
CAUTION
Stresses beyond those listed under Table 11 may cause permanent damage
to the device. These are stress ratings only. Functional operation of the
device at these or any other conditions beyond those indicated under
Table 13 is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
16
Freescale Semiconductor
Electrical Characteristics
Table 11. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
VCC
–0.3
1.35
V
VDDGP
–0.3
1.15
V
Supply Voltage (UHVIO, I2C)
Supplies denoted as I/O Supply
–0.5
3.6
V
Supply Voltage (except UHVIO, I2C)
Supplies denoted as I/O Supply
–0.5
3.3
V
VBUS
—
5.25
V
Vin/Vout
–0.5
OVDD + 0.31
V
Peripheral Core Supply Voltage
ARM Core Supply Voltage
USB VBUS
Input/Output Voltage Range
ESD Damage Immunity:
Vesd
V
Human Body Model (HBM)
Charge Device Model (CDM)
Storage Temperature Range
Junction Temperature
—
—
2000
500
TSTORAGE
–40
125
oC
TJ
—
1252
oC
1
The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in
Table 128. The maximum range can be superseded by the DC tables.
2 During the life of the device, T must be limited to a cumulative of 2% of the time over 105oC.
J
Table 12 provides the thermal resistance data.
Table 12. Thermal Resistance Data
Rating
Junction to Case1, 19 x 19 mm package
1
Board
Symbol
Value
Unit
—
RθJC
6
°C/W
Rjc-x per JEDEC 51-12: The junction-to-case thermal resistance. The “x” indicates the case surface where Tcase is measured
and through which 100% of the junction power is forced to flow due to the cold plate heat sink fixture placed either at the top (T)
or bottom (B) of the package, with no board attached to the package.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
17
Electrical Characteristics
Table 13 shows the i.MX51 operating ranges.
Table 13. i.MX51A Operating Ranges
Minimum1
Nominal2
Maximum1
Unit
ARM core supply voltage
0 < fARM ≤ 600 MHz
0.95
1.0
1.1
V
ARM core supply voltage
Stop mode
0.9
0.95
1.05
V
1.175
1.225
1.275
V
Peripheral supply voltage—Stop mode
0.9
0.95
1.275
V
Memory arrays voltage—Run Mode
1.15
1.20
1.275
V
Memory arrays voltage—Stop Mode
0.9
0.95
1.275
V
VDD_DIG_PLL_A
VDD_DIG_PLL_B
PLL Digital supplies
1.15
1.2
1.35
V
VDD_ANA_PLL_A
VDD_ANA_PLL_B
PLL Analog supplies
1.75
1.8
1.95
V
NVCC_EMI
NVCC_PER5
NVCC_PER10
NVCC_PER11
NVCC_PER12
NVCC_PER13
NVCC_PER14
GPIO EMI Supply and additional digital power
supplies.
1.65
1.875 or
2.775
3.1
V
NVCC_IPUx3
NVCC_PER3
NVCC_PER8
NVCC_PER9
GPIO IPU Supply and additional digital power
supplies.
1.65
1.875 or
2.775
3.1
V
DDR and Fuse Read Supply
1.65
1.8
1.95
V
Fusebox Program Supply (Write Only)
3.0
—
3.3
V
Symbol
VDDGP
MCIMX51xA products
VCC
MCIMX51xA products
VDDA
NVCC_EMI_DRAM
VDD_FUSE4
NVCC_NANDF_x5
NVCC_PER15
NVCC_PER17
NVCC_USBPHY
NVCC_OSC
TVDAC_DHVDD,
NVCC_TV_BACK,
AHVDDRGB
Parameter
Peripheral supply voltage High Performance
Mode (HPM) The clock frequencies are derived
from AXI and AHB buses using 133 or 166 MHz
(as needed). The DDR clock rate is 200 MHz.
Note: For detailed information about the use of
133 or 166 MHz clocks, see i.MX51 Multimedia
Applications Processor Reference Manual
(MCIMX51RM).
Ultra High voltage I/O (UHVIO) supplies
—
V
UHVIO_L
1.65
1.875
1.95
UHVIO_H
2.5
2.775
3.1
UHVIO_UH
3.0
3.3
3.6
USB_PHY analog supply, oscillator analog
supply6
2.25
2.5
2.75
V
TVE-to-DAC level shifter supply, cable detector
supply, analog power supply to RGB channel
2.69
2.75
2.91
V
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
18
Freescale Semiconductor
Electrical Characteristics
Table 13. i.MX51A Operating Ranges (continued)
Minimum1
Nominal2
Maximum1
Unit
HS-GPIO additional digital power supplies
1.65
—
3.1
V
I2C and HS-I2C I/O Supply7
1.65
1.875
1.95
V
2.7
3.0
3.3
SRTC Core and I/O Supply (LVIO)
1.1
1.2
1.3
V
USB PHY I/O analog supply
3.0
3.3
3.6
V
See Table 11 and Table 126 for details. This is
not a power supply.
—
—
—
—
Symbol
Parameter
NVCC_HS4_1
NVCC_HS4_2
NVCC_HS6
NVCC_HS10
NVCC_I2C
NVCC_SRTC_
POW
VDDA33
VBUS
1
2
3
4
5
6
7
Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design
must allow for supply tolerances and system voltage drops.
The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a
tighter tolerance allows reduction of the setpoint with commensurate power savings.
The NVCC_IPUx rails are isolated from one another. This allows the connection of different supply voltages for each one. For
example, NVCC_IPU2 can operate at 1.8 V while NVCC_IPU4 operates at 3.0 V.
In Read mode, Freescale recommends VDD_FUSE be floated or grounded. Tying VDD_FUSE to a positive supply
(3.0 V–3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended.
The NAND Flash supplies are composed of three groups: A, B, and C. Each group can be powered with a different supply
voltage. For example, NVCC_NANDF_A = 1.8 V, NVCC_NANDF_B = 3.0 V, NVCC_NANDF_C = 2.7 V.
The analog supplies should be isolated in the application design. Use of series inductors is recommended.
Operation of the HS-I2C and I2C is not guaranteed when operated between the supply voltages of 1.95 to 2.7 V.
Table 14. Interface Frequency
Parameter Description
Symbol
Min
Max
Unit
JTAG: TCK Operating Frequency
ftck
See Table 99, "JTAG Timing," on page 130
MHz
CKIL: Operating Frequency
fckil
See Table 74, "FPM Specifications," on page 80
kHz
CKIH: Operating Frequency
fckih
See Table 47, "CAMP Electrical Parameters (CKIH1,
CKIH2)," on page 46
MHz
XTAL Oscillator
fxtal
4.1.1
22
27
MHz
Supply Current
Table 15 shows the fuse supply current.
Table 15. Fuse Supply Current1
Description
eFuse Program Current.2
Current required to program one eFuse bit: The associated
VDD_FUSE supply per Table 13.
Symbol
Min
Typ
Max
Unit
Iprogram
—
60
120
mA
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
19
Electrical Characteristics
1
2
The read current of approximately 5 mA is derived from the DDR supply (NVCC_EMI_DRAM).
The current Iprogram is only required during program time.
Table 16 shows the current core consumption (not including I/O) of the i.MX51.
Table 16. i.MX51 Stop Mode Current and Power Consumption
Mode
Condition
Stop Mode
• External reference clocks
gated
• Power gating for ARM and
processing units
• Stop mode voltage
Stop Mode
• External reference clocks
gated
• Power gating for ARM and
processing units
• HPM voltage
Stop Mode
• External reference clocks
enabled
• Power gating for ARM and
processing units
• HPM voltage
VDDGP = 0.95 V, VCC = 0.95 V, VDDA = 0.95 V
ARM CORE in SRPG mode
L1 and L2 caches power gated
IPU in S&RPG mode
VPU and GPU in PG mode
All PLLs off, all CCM-generated clocks off
CKIL input on with 32 kHz signal present
All modules disabled
USBPHY PLL off
External (MHz) crystal and on-chip oscillator
powered down (SBYOS bit asserted)
No external resistive loads that cause current flow
Standby voltage allowed (VSTBY bit is asserted)
TA = 25 °C
VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V
ARM CORE in SRPG mode
L1 and L2 caches power gated
IPU in S&RPG mode
VPU and GPU in PG mode
All PLLs off, all CCM-generated clocks off
CKIL input on with 32 kHz signal present
All modules disabled.
USBPHY PLL off
External (MHz) crystal and on-chip oscillator
powered down (SBYOS bit asserted)
No external resistive loads that cause current flow
TA = 25°C
VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.20 V
ARM CORE in SRPG mode
L1 and L2 caches power gated
IPU in S&RPG mode
VPU and GPU in PG mode
All PLLs off, all CCM-generated clocks off
Supply
Nominal
Unit
VDDGP
0.18
mA
VCC
0.35
VDDA
0.15
NVCC_OSC
0.012
Total
0.66
mW
VDDGP
0.24
mA
VCC
0.45
VDDA
0.2
NVCC_OSC
0.012
Total
1.09
mW
VDDGP
0.24
mA
VCC
0.45
VDDA
0.2
NVCC_OSC
1.5
Total
4.8
mW
CKIL input on with 32 kHz signal present
All modules disabled
USBPHY PLL off
External (MHz) crystal and on-chip oscillator powered and generating reference clock
No external resistive loads that cause current flow
TA = 25 °C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
20
Freescale Semiconductor
Electrical Characteristics
Table 16. i.MX51 Stop Mode Current and Power Consumption (continued)
Mode
Condition
Stop Mode
• External reference clocks
enabled
• No power gating for ARM and
processing units
• HPM voltage
4.1.2
VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V
All PLLs off, all CCM-generated clocks off
CKIL input on with 32 kHz signal present
All modules disabled
USBPHY PLL off
External (MHz) crystal and on-chip oscillator
powered and generating reference clock
No external resistive loads that cause current flow
TA = 25 °C
Supply
Nominal
Unit
VDDGP
50
mA
VCC
2
VDDA
1.15
NVCC_OSC
1.5
Total
63
mW
USB PHY Current Consumption
Table 17 shows the USB PHY current consumption.
Table 17. USB PHY Current Consumption
Parameter
Conditions
Full Speed
Analog Supply
VDDA33 (3.3 V)
High Speed
Full Speed
Analog Supply
NVCC_USBPHY (2.5 V)
High Speed
Full Speed
Digital Supply
VCC (1.2 V)
High Speed
VDDA33 + NVCC_USBPHY + VCC
4.2
Suspend
Typical @ 25 °C
Max
RX
5.5
6
TX
7
8
RX
5
6
TX
5
6
RX
6.5
7
TX
6.5
7
RX
12
13
TX
21
22
RX
6
7
TX
6
7
RX
6
7
TX
6
7
50
100
Unit
mA
mA
mA
μA
Supply Power-Up/Power-Down Requirements and Restrictions
The system design must comply with the power-up and power-down sequence guidelines as described in
this section to guarantee reliable operation of the device. Any deviation from these sequences may result
in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the i.MX51A processor (worst-case scenario)
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
21
Electrical Characteristics
4.2.1
Power-Up Sequence
Figure 2 shows the power-up sequence.
NVCC_SRTC_POW
VCC
NVCC_EMI_DRAM
VDDGP4
VDDA
NVCC_HS4_1
NVCC_HS4_2
NVCC_HS6
NVCC_HS10
NVCC_PERx2
NVCC_EMI
NVCC_IPU
NVCC_I2C
NVCC_NANDF_x
NVCC_PER15
NVCC_PER17
AHVDDRGB
NVCC_TV_BACK
TVDAC_DHVDD
VDD_DIG_PLL_A/B
VDD_ANA_PLL_A/B
NVCC_OSC
NVCC_USBPHY
VDDA33
VDD_FUSE1
1. VDD_FUSE should only be powered when writing.
2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14.
3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.
4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.
5. If all of the UHVIO supplies (NVCC_NANDFx, NVCC_PER15 and NVCC_PER17) are less than 2.75 V then there is no
requirement on the power up sequence order between NVCC_EMI_DRAM and the UHVIO supplies. However, if the voltage
is 2.75 V and above, then NVCC_EMI_DRAM needs to power up before the UHVIO supplies as shown here.
Figure 2. Power-Up Sequence
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
For more information on power up, see i.MX51 Power-Up Sequence
(AN4053).
4.3
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
• General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO)
• Double Data Rate 2 (DDR2)
• Low Voltage I/O (LVIO)
• Ultra High Voltage I/O (UHVIO)
• High-Speed I2C and I2C
• Enhanced Secure Digital Host Controller (eSDHC)
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22
Freescale Semiconductor
Electrical Characteristics
NOTE
The term OVDD in this section refers to the associated supply rail of an
input or output. The association is shown in Table 128.
4.3.1
GPIO/HSGPIO DC Parameters
The parameters in Table 18 are guaranteed per the operating ranges in Table 13, unless otherwise noted.
Table 18. GPIO/HSGPIO DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
Iout = -1 mA
OVDD –0.15
—
OVDD + 0.3
V
Low-level output voltage
Vol
Iout = 1mA
—
—
0.15
V
High-level output current
Ioh
—
—
Low-level output current
Iol
Vout = 0.8×OVDD
Low drive
Medium drive
High drive
Max drive
–1.9
–3.7
–5.2
–6.6
Vout = 0.2×OVDD
Low drive
Medium drive
High drive
Max drive
1.9
3.7
5.2
6.6
mA
—
—
mA
High-Level DC input voltage1
VIH
—
0.7 × OVDD
—
OVDD
V
Low-Level DC input voltage1
VIL
—
0
—
0.3×OVDD
V
VHYS
OVDD = 1.875
OVDD = 2.775
0.25
0.34
0.45
—
V
Schmitt trigger VT+ 1, 2
VT+
—
0.5OVDD
—
—
V
Schmitt trigger VT-1, 2
VT-
—
—
—
Input Hysteresis
0.5
× OVDD
See Note
3
V
Input current (no pull-up/down)
Iin
Vin = OVDD or 0
—
—
Input current (22 kΩ Pull-up)
Iin
Vin = 0
—
—
161
μA
Input current (47 kΩ Pull-up)
Iin
Vin = 0
—
—
76
μA
Input current (100 kΩ Pull-up)
Iin
Vin = 0
—
—
36
μA
Input current (100 kΩ Pull-down)
Iin
Vin = OVDD
—
—
36
μA
Keeper Circuit Resistance
—
OVDD = 1.875V
OVDD = 2.775V
—
—
22
17
—
—
kΩ
—
1
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
3 I/O leakage currents are listed in Table 25.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
23
Electrical Characteristics
4.3.2
DDR2 I/O DC Parameters
The parameters in Table 19 are guaranteed per the operating ranges in Table 13, unless otherwise noted.
Table 19. DDR2 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
Voh
—
OVDD – 0.28
—
V
Low-level output voltage
Vol
—
—
0.28
V
Output minimum Source Current
Ioh
OVDD = 1.7 V
Vout = 1.42 V
–13.4
—
mA
Output min Sink Current
Iol
OVDD = 1.7 V
Vout = 0.28 V
13.4
—
mA
DC input Logic High
VIH
—
OVDD/2 + 0.125
OVDD + 0.3
V
DC input Logic Low
VIL
—
–0.3
OVDD/2 – 0.125
V
Input voltage range of each differential input
Vin
—
–0.3
OVDD + 0.3
V
Differential input voltage required for switching Vid
—
0.25
OVDD + 0.6
V
Termination Voltage
Vtt
Vtt tracking OVDD/2
OVDD/2 – 0.04
OVDD/2 + 0.04
V
Input current (no pull-up/down)
Iin
VI = 0
VI = OVDD
—
—
See Note 1
—
1
I/O leakage currents are listed in Table 25.
4.3.3
Low Voltage I/O (LVIO) DC Parameters
The parameters in Table 20 are guaranteed per the operating ranges in Table 13, unless otherwise noted.
Table 20. LVIO DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
Iout = –1 mA
OVDD – 0.15
—
—
V
Low-level output voltage
Vol
Iout = 1 mA
—
—
0.15
V
I
Vout = 0.8 × OVDD
Low Drive
Medium Drive
High Drive
Max Drive
—
—
–2.1
–4.2
–6.3
–8.4
Iol
Vout = 0.2 × OVDD
Low Drive
Medium Drive
High Drive
Max Drive
2.1
4.2
6.3
8.4
VIH
—
0.7 × OVDD
—
OVDD
V
VIL
—
0
—
0.3 × OVDD
V
VHYS
OVDD = 1.875
OVDD = 2.775
0.35
0.62
1.27
—
V
High-level output current
Ioh
Low-level output current
High-Level DC input voltage1
Low-Level DC input
Input Hysteresis
voltage1
I
mA
—
—
mA
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24
Freescale Semiconductor
Electrical Characteristics
Table 20. LVIO DC Electrical Characteristics (continued)
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Schmitt trigger VT+1, 2
VT+
—
0.5 × OVDD
—
—
V
Schmitt trigger VT–1, 2
VT–
—
—
—
0.5 × OVDD
V
Input current (no pull-up/down)
Iin
VI = 0 or OVDD
—
—
See Note 3
—
Input current (22 kΩ Pull-up)
Iin
VI = 0
—
—
161
μA
Input current (47 kΩ Pull-up)
Iin
VI = 0
—
—
76
μA
Input current (100 kΩ Pull-up)
Iin
VI = 0
—
—
36
μA
Input current (100 kΩ Pull-down)
Iin
VI = OVDD
—
—
36
μA
Keeper Circuit Resistance
—
OVDD = 1.875 V
OVDD = 2.775 V
—
—
22
17
—
—
kΩ
1
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
3
I/O leakage currents are listed in Table 25.
4.3.4
Ultra-High Voltage I/O (UHVIO) DC Parameters
The parameters in Table 21 are guaranteed per the operating ranges in Table 13, unless otherwise noted.
Table 21. UHVIO DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
Iout = –1mA
OVDD–0.15
—
—
V
Low-level output voltage
Vol
Iout = 1mA
—
—
0.15
V
Vout = 0.8 × OVDD
Low Drive
Medium Drive
High Drive
—
—
Ioh_lv
–2.2
–4.4
–6.6
Vout = 0.8 × OVDD
Low Drive
Medium Drive
High Drive
–5.1
–10.2
–15.3
Vout = 0.2 × OVDD
Low Drive
Medium Drive
High Drive
2.2
4.4
6.6
Vout = 0.2 × OVDD
Low Drive
Medium Drive
High Drive
5.1
10.2
15.3
High-level output current, low voltage mode
High-level output current, high voltage mode
Ioh_hv
Low-level output current, low voltage mode
Iol_lv
Low-level output current, high voltage mode
Iol_hv
mA
—
—
mA
—
—
mA
—
—
mA
High-Level DC input voltage1,2
VIH
—
0.7 × OVDD
—
OVDD
V
Low-Level DC input voltage2,3
VIL
—
0
—
0.3 × OVDD
V
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
25
Electrical Characteristics
Table 21. UHVIO DC Electrical Characteristics (continued)
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
VHYS
Low voltage mode
High voltage mode
0.38
0.95
—
0.43
1.33
V
Schmitt trigger VT+2,3
VT+
—
0.5OVDD
—
—
V
VT–2,4
VT–
—
—
—
0.5 × OVDD
V
Input current (no pull-up/down)
Iin
Vin = 0
Vin = OVDD
—
—
See Note 4
—
Input current (22 kΩ Pull-up)
Iin
Vin = 0
—
—
202
μA
Input current (75 kΩ Pull-up)
Iin
Vin = 0
—
—
61
μA
Input current (100 kΩ Pull-up)
Iin
Vin = 0
—
—
47
μA
Input current (360 kΩ Pull-down)
Iin
Vin = OVDD
—
—
5.7
μA
Keeper Circuit Resistance
—
NA
—
17
—
kΩ
Input Hysteresis
Schmitt trigger
1
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
2 Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.
Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4 I/O leakage currents are listed in Table 25.
The UHVIO type of I/O cells have to be configured properly according to their supply voltage level, in
order to prevent permanent damage to them and in order to not degrade their timing performance.
The HVE control bit of the I/O cell (in IOMUX control registers) should be set to 1 for Low voltage
operation and to 0 for High voltage operation.
The HVE bit should be set as follows:
• HVE = 0: High output voltage mode (3.0V to 3.6V)
• HVE = 1: Low output voltage mode (1.65V to 3.1V)
This is related to power domains, such as NVCC_NANDF, NVCC_PER15, and NVCC_PER17.
If HVE bit is not set properly when high voltage level is applied for long durations, it may cause permanent
damage over a period of time, causing reduced timing performance of the pad. Similarly, not setting HVE
bit properly for low voltage will degrade pad timing performance.
The below discussion clarifies concerns about boot-up period.
The HVE bit is set, by default, to 1 for low voltage operation. As a result, there might be a short period
conflict between the HVE bit value and the applied voltage. This conflict is acceptable under the following
conditions:
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
26
Freescale Semiconductor
Electrical Characteristics
•
•
The UHVIO pads receive supply voltage up to 3.3V (3.6V max); however, the pads do not toggle
during the boot-up sequence (using another interface as a boot code source), for boot-up period of
about 22 msec.
The UHVIO pads receive up to 3.15V (3.3V max) and are used for accessing the boot code, for
boot-up period of about 11 msec.
In any case, it is recommended to try to minimize the duration of this period and reduce the amount of
toggling on the pads as much as possible. For this, it is recommended to add proper HVE bit programming
to the DCD boot-up tables. DCD is a table located in the start of the image that can hold up to 60
address/values. ROM code reads addresses and writes values to it. This space should be sufficient to
reprogram the NAND Flash pads for HVE bits.
4.3.5
I2C I/O DC Parameters
NOTE
See the errata for HS-I2C in i.MX51 Chip Errata document. The two
standard I2C modules have no errata.
The DC Electrical Characteristics listed in Table 22 are guaranteed using operating ranges per Table 13,
unless otherwise noted.
Table 22. I2C Standard/Fast/High-Speed Mode Electrical Parameters for Low/Medium Drive Strength
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Vol
Iol = 3 mA
—
—
0.4
V
VIH
—
0.7 × OVDD
—
OVDD
V
VIL
—
0
—
0.3 × OVDD
V
VHYS
—
0.25
—
—
V
Schmitt trigger VT+1,2
VT+
—
0.5 × OVDD
—
—
V
1,2
VT–
—
—
—
0.5 × OVDD
V
Iin
VI = OVDD or 0
—
—
See Note 3
—
Low-level output voltage
High-Level DC input voltage
1
Low-Level DC input voltage1
Input Hysteresis
Schmitt trigger VT–
I/O leakage current (no pull-up)
1
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
3 I/O leakage currents are listed in Table 25.
4.3.6
USBOTG Electrical DC Parameters
This section describes the electrical DC parameters of USBOTG.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
27
Electrical Characteristics
4.3.7
USB Port Electrical DC Characteristics
Table 23 and Table 24 list the electrical DC characteristics.
Table 23. USBOTG Interface Electrical Specification
Parameter
Symbol
Signals
Min
Max
Unit
Test Conditions
Input High Voltage
VIH
USB_VPOUT
USB_VMOUT
USB_XRXD,
USB_VPIN,
USB_VMIN
VDD x 0.7
VDD
V
—
Input low Voltage
VIL
USB_VPOUT
USB_VMOUT
USB_XRXD,
USB_VPIN,
USB_VMIN
0
VDD × 0.3
V
—
Output High Voltage
VOH
USB_VPOUT
USB_VMOUT
USB_TXENB
VDD – 0.43
—
V
7 mA Drv
at IOH = 5 mA
Output Low Voltage
VOL
USB_VPOUT
USB_VMOUT
USB_TXENB
—
0.43
V
7 mA Drv
at IOH = 5 mA
Unit
Test Conditions
Table 24. USB Interface Electrical Specification
Parameter
Symbol
Signals
Min
Max
Input High Voltage
VIH
USB_DAT_VP
USB_SE0_VM
USB_RCV,
USB_VP1,
USB_VM1
VDD x 0.7
VDD
V
—
Input Low Voltage
VIL
USB_DAT_VP
USB_SE0_VM
USB_RCV,
USB_VP1,
USB_VM1
0
VDD x 0.3
V
—
Output High Voltage
VOH
USB_DAT_VP
USB_SE0_VM
USB_TXOE_B
VDD –0.43
Output Low Voltage
VOL
USB_DAT_VP
USB_SE0_VM
USB_TXOE_B
—
—
0.43
V
7 mA Drv
at Iout = 5 mA
V
7 mA Drv
at Iout = 5 mA
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
28
Freescale Semiconductor
Electrical Characteristics
Table 25 shows the I/O leakage currents that are based on the operating ranges in Table 13 and the
operating temperatures in Table 1.
.
Table 25. I/O Leakage Current
Contact Group
Supply Rail
Test Condition
Min
Typ
Max
Unit
NANDF
NVCC_NANDF
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±1
μA
EIM
NVCC_EMI
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±1
μA
DRAM
NVCC_DRAM
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±2.5
μA
CSI1, CSI2, DISP1_Data[5:0]
NVCC_HSx
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±1.5
μA
I2C1
NVCC_I2C
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±1
μA
DI1_DAT[23:6],
DISPB_SER_x, DI_GPx
NVCC_IPU
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±2
μA
CKIL, PMIC_x
NVCC_SRTC_POW
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±1
μA
EXTAL, XTAL
NVCC_OSC
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±170
μA
ID, GPANAIO
NVCC_USBPHY
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±170
μA
DISP2_DAT[0:15]
NVCC_IPU,
NVCC_HS
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±2
μA
SD1, SD2
NVCC_PER15,
NVCC_PER17
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±10
μA
Peripherals except SD1, SD2
NVCC_PERx
V[I/O] = GND or Positive
Supply Rail, I/O = High Z
—
—
±2
μA
4.4
Output Buffer Impedance Characteristics
This section defines the I/O Impedance parameters of the i.MX51A processor.
4.4.1
LVIO I/O Output Buffer Impedance
Table 26 shows the LVIO I/O output buffer impedance.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
29
Electrical Characteristics
Table 26. LVIO I/O Output Buffer Impedance
Typical
Parameter
Symbol
Conditions
Min
Max
Unit
OVDD 2.775 V OVDD 1.875 V
Output Driver
Impedance
Rpu
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength, Ztl = 37.5 Ω
80
40
27
20
104
52
35
26
150
75
51
38
250
125
83
62
Ω
Output Driver
Impedance
Rpd
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength, Ztl = 37.5 Ω
64
32
21
16
88
44
30
22
134
66
44
34
243
122
81
61
Ω
4.4.2
DDR2 Output Buffer Impedance
Table 27 shows the DDR2 output buffer impedance.
Table 27. DDR2 I/O Output Buffer Impedance HVE = 0
Parameter
Symbol
Test Conditions
Best Case
Tj = –40 °C
OVDD = 1.95 V
VCC = 1.3 V
Typical
Tj = 25 °C
OVDD = 1.8 V
VCC = 1.2 V
Worst Case
Tj = 105 °C
OVDD = 1.6 V
VCC = 1.1 V
s0–s5
000000
s0–s5
101010
s0–s5
111111
Unit
Output Driver
Impedance
Rpu
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength
185
92.5
61.7
26.5
140
70
47
19.5
111.4
55.7
37.2
15.4
Ω
Output Driver
Impedance
Rpd
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength
190.3
95.1
63.4
27.6
145.4
72.7
48.5
19.9
120.6
60.3
40.2
16.9
Ω
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
30
Freescale Semiconductor
Electrical Characteristics
4.4.3
UHVIO Output Buffer Impedance
Table 28 shows the UHVIO output buffer impedance.
Table 28. UHVIO Output Buffer Impedance
Min
Test Conditions
Typ
Parameter
Symbol
Output Driver
Impedance
Rpu
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
98
49
32
114
57
38
Output Driver
Impedance
Rpd
Low Drive Strength, Ztl =1 50 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
97
49
32
118
59
40
OVDD
1.95 V
OVDD OVDD
3.0 V 1.875 V
Max
Unit
OVDD
3.3 V
OVDD
1.65 V
OVDD
3.6 V
124
62
41
135
67
45
198
99
66
206
103
69
Ω
126
63
42
154
77
51
179
89
60
217
109
72
Ω
NOTE
Output driver impedance is measured with long transmission line of
impedance Ztl attached to I/O pad and incident wave launched into
transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 3).
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
31
Electrical Characteristics
OVDD
PMOS (Rpu)
Ztl Ω, L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
Vin (do)
VDD
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Rpu =
Vovdd – Vref1
Vref1
Rpd =
Vref2
× Ztl
× Ztl
Vovdd – Vref2
Figure 3. Impedance Matching Load for Measurement
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
32
Freescale Semiconductor
Electrical Characteristics
4.5
I/O AC Parameters
The load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. AC electrical
characteristics for slow and fast I/O are presented in the Table 29 and Table 30, respectively.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 4. Load Circuit for Output
NVCC
80%
80%
20%
0V
20%
Output (at I/O)
tf
tr
Figure 5. Output Transition Time Waveform
4.5.1
Slow I/O AC Parameters
Table 29 shows the slow I/O AC parameters.
Table 29. Slow I/O AC Parameters
Parameter
Symbol
Test Condition Min Rise/Fall
Typ
Max Rise/Fall
Unit
Output Pad Transition Times (Max Drive)
tr, tf
15 pF
35 pF
—
—
1.98/1.52
3.08/2.69
ns
Output Pad Transition Times (High Drive)
tr, tf
15 pF
35 pF
—
—
2.31/1.838
3.8/2.4
ns
Output Pad Transition Times (Medium Drive)
tr, tf
15 pF
35 pF
—
—
2.92/2.43
5.37/4.99
ns
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
4.93/4.53
10.55/9.79
ns
Output Pad Slew Rate (Max Drive)
tps
15 pF
35 pF
0.5/0.65
0.32/0.37
—
—
V/ns
Output Pad Slew Rate (High Drive)
tps
15 pF
35 pF
0.43/0.54
0.26/0.41
—
—
V/ns
Output Pad Slew Rate (Medium Drive)
tps
15 pF
35 pF
0.34/0.41
0.18/0.2
—
—
V/ns
Output Pad Slew Rate (Low Drive)
tps
15 pF
35 pF
0.20/0.22
0.09/0.1
—
—
V/ns
Output Pad di/dt (Max Drive)
tdit
—
—
—
30
mA/ns
Output Pad di/dt (High Drive)
tdit
—
—
—
23
mA/ns
Output Pad di/dt (Medium drive)
tdit
—
—
—
15
mA/ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
33
Electrical Characteristics
Table 29. Slow I/O AC Parameters (continued)
Parameter
Symbol
Test Condition Min Rise/Fall
Typ
Max Rise/Fall
Unit
Output Pad di/dt (Low drive)
tdit
—
—
—
7
mA/ns
Input Transition Times1
trm
—
—
—
25
ns
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
4.5.2
Fast I/O AC Parameters
Table 30 shows the fast I/O AC parameters.
Table 30. Fast I/O AC Parameters
Test
Condition
Min Rise/Fall
Typ
Max Rise/Fall
Unit
15 pF
35 pF
—
—
1.429/1.275
2.770/2.526
ns
tr, tf
15 pF
35 pF
—
—
1.793/1.607
3.565/3.29
ns
Output Pad Transition Times (Medium
Drive)
tr, tf
15 pF
35 pF
—
—
2.542/2.257
5.252/4.918
ns
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
4.641/4.456
10.699/10.0
ns
Output Pad Slew Rate (Max Drive)
tps
15 pF
35 pF
0.69/0.78
0.36/0.39
—
—
V/ns
Output Pad Slew Rate (High Drive)
tps
15 pF
35 pF
0.55/0.62
0.28/0.30
—
—
V/ns
Output Pad Slew Rate (Medium Drive)
tps
15 pF
35 pF
0.39/0.44
0.19/0.20
—
—
V/ns
Output Pad Slew Rate (Low Drive)
tps
15 pF
35 pF
0.21/0.22
0.09/0.1
—
—
V/ns
Output Pad di/dt (Max Drive)
tdit
—
—
—
70
mA/ns
Output Pad di/dt (High Drive)
tdit
—
—
—
53
mA/ns
Output Pad di/dt (Medium drive)
tdit
—
—
—
35
mA/ns
Output Pad di/dt (Low drive)
tdit
—
—
—
18
mA/ns
Input Transition Times1
trm
—
—
—
25
ns
Parameter
Symbol
Output Pad Transition Times (Max Drive)
tr, tf
Output Pad Transition Times (High
Drive)
1
Hysteresis mode is recommended for inputs with transition time greater than 25 ns.
4.5.3
I2C AC Parameters
NOTE
in the i.MX51 Chip Errata document. The two
See the errata for
2
standard I C modules have no errata
HS-I2C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
34
Freescale Semiconductor
Electrical Characteristics
Figure 6 depicts the load circuit for output pads for standard- and fast-mode. Figure 7 depicts the output
pad transition time definition. Figure 8 depicts load circuit with external pull-up current source for
HS-mode. Figure 9 depicts HS-mode timing definition.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 6. Load Circuit for Standard and Fast-Mode
OVDD
70%
Output
30%
0V
tf
Figure 7. Definition of Timing for Standard and Fast-Mode
OVDD
3 mA1
From Output
Under Test
Test Point
CL2
Notes:
1Load current when output is between 0.3×OVDD and 0.7×OVDD
2CL includes package, probe, and fixture capacitance.
Figure 8. Load Circuit for HS-Mode with External Pull-Up Current Source
OVDD
70%
30%
Output (at pad)
tTLH
70%
30%
0V
tTHL
PA3Max = max of tTLH and tTHL
PA4Max = max tTHL
Figure 9. Definition of Timing for HS-Mode
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
35
Electrical Characteristics
The electrical characteristics for I2C I/O are listed in Table 31 to Table 34. Characteristics are guaranteed
using operating ranges per Table 13, unless otherwise noted.
Table 31. I2C Standard- and Fast-Mode Electrical Parameters
for Low/Medium Drive Strength and OVDD = 2.7 V–3.3 V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output fall time,
(low driver strength)
tf
from V IHmin to VILmax with CL from 10 pF to 400 pF
—
—
52
ns
Output fall time,
(medium driver strength)
tf
from V IHmin to VILmax with CL from 10 pF to 400 pF
—
—
28
ns
Table 32. I2C Standard- and Fast-Mode Electrical Parameters
for Low/Medium Drive Strength and OVDD = 1.65 V–1.95 V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output fall time,
(low driver strength)
tof
from V IHmin to VILmax with CL from 10 pF to 400 pF
—
—
70
ns
Output fall time,
(medium driver strength)
tof
from V IHmin to VILmax with CL from 10 pF to 400 pF
—
—
35
ns
Table 33. I2C High-Speed Mode Electrical Parameters
for Low/Medium Drive Strength and OVDD = 2.7 V–3.3 V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output rise time (current-source enabled) and
fall time at SCLH
(low driver strength)
trCL, tfCL
with a 3mA external
pull-up current source
and CL = 100 pF
—
—
18/21
ns
Output rise time (current-source enabled) and
fall time at SCLH
(medium driver strength)
trCL, tfCL
with a 3mA external
pull-up current source
and CL = 100 pF
—
—
9/9
ns
Output fall time at SDAH
(low driver strength)
tfDA
with CL from 10 pF to
100 pF
—
—
14
ns
Output fall time at SDAH
(medium driver strength)
tfDA
with CL from 10 pF to
100 pF
—
—
8
ns
Output fall time at SDAH
(low driver strength)
tfDA
CL = 400 pF
—
—
52
ns
Output fall time at SDAH
(medium driver strength)
tfDA
CL = 400 pF
—
—
27
ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
36
Freescale Semiconductor
Electrical Characteristics
Table 34. I2C High-Speed Mode Electrical Parameters
for Low/Medium Drive Strength and OVDD = 1.65 V–1.95 V
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output rise time (current-source
enabled) and fall time at SCLH
(low driver strength)
trCL, tfCL
with a 3 mA external pull-up current
source and CL = 100 pF
—
—
10/74
ns
Output rise time (current-source
enabled) and fall time at SCLH
(medium driver strength)
trCL, tfCL
with a 3 mA external pull-up current
source and CL = 100 pF
—
—
7/14
ns
Output fall time at SDAH
(low driver strength)
tfDA
with CL from 10 pF to 100 pF
0
—
17
ns
Output fall time at SDAH
(medium driver strength)
tfDA
with CL from 10 pF to 100 pF
0
—
9
ns
Output fall time at SDAH
(low driver strength)
tfDA
CL = 400 pF
30
—
67
ns
Output fall time at SDAH
(medium driver strength)
tfDA
CL = 400 pF
15
—
34
ns
Typ
Max Rise/Fall
Unit
Table 35. Low Voltage I2C I/O Parameters
Parameter
Symbol
Test Condition Min Rise/Fall
Output Pad di/dt (Medium drive)
tdit
—
—
—
22
mA/ns
Output Pad di/dt (Low drive)
tdit
—
—
—
11
mA/ns
trm
—
—
—
25
ns
Input Transition
1
Times1
Hysteresis mode is recommended for inputs with transition time greater than 25 ns
Table 36. High Voltage I2C I/O Parameters
Parameter
Symbol
Typ
Max Rise/Fall
Unit
Output Pad Transition Times (Medium Drive)
tr, tf
15 pF
35 pF
—
—
3/3
6/5
ns
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
5/5
9/9
ns
Output Pad Slew Rate (Medium Drive)
tps
15 pF
35 pF
0/0
0/0
—
—
V/ns
Output Pad Slew Rate (Low Drive)
tps
15 pF
35 pF
0/0
0/0
—
—
V/ns
Output Pad di/dt (Medium drive)
tdit
—
—
—
36
mA/ns
Output Pad di/dt (Low drive)
tdit
—
—
—
16
mA/ns
Input Transition Times1
trm
—
—
—
25
ns
1
Test Condition Min Rise/Fall
Hysteresis mode is recommended for inputs with transition time > 25 ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
37
Electrical Characteristics
4.5.4
AC Electrical Characteristics for DDR2
The load circuit for output pads, the output pad transition time waveform and the output pad propagation
and transition time waveform are below.
Figure 10 shows the output pad transition time waveform.
Figure 10. Output Pad Transition Time Waveform
Figure 11 shows the output pad propagation and transition time waveform.
Figure 11. Output Pad Propagation and Transition Time Waveform
AC electrical characteristics in DDR2 mode for fast mode and for ovdd = 1.65 – 1.95 V, ipp_hve = 0 are
placed in Table 37.
Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and
for ovdd=1.65–1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times1
tpr
15pF
35pF
0.57/0.57
1.29/1.29
0.45/0.44
0.97/0.94
0.45/0.45
0.82/0.85
ns
Output Pad Propagation Delay, 50%-50% 1
tpo
15pF
35pF
0.98/0.96
1.47/1.50
1.27/1.19
1.63/1.57
1.89/1.72
2.20/2.07
ns
Output Pad Slew Rate1
tps
15pF
35pF
2.05/2.05
0.91/0.91
2.40/2.45
1.11/1.15
2.20/2.20
1.21/1.16
V/ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
38
Freescale Semiconductor
Electrical Characteristics
Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and
for ovdd=1.65–1.95 V (ipp_hve=0) (continued)
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
di/dt
—
390
201
99
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128
0.212/0.213
ns
Input Pad Propagation Delay without Hysteresis
(CMOS input), 50%-50% 2
tpi
1.2 pF
0.45/0.93
0.6/0.58
0.9/0.88
ns
Input Pad Propagation Delay with Hysteresis
(CMOS input), 50%-50% 2
tpi
1.2 pF
0.55/0.55
0.71/0.7
1.03/0.98
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.38/0.38
0.58/0.61
1.014/1.07
ns
Maximum Input Transition Times3
trm
—
—
—
5
ns
Parameter
Output Pad di/dt1
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, –40 °C and s0-s5=000000.
2 Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO
1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.
3 Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR2 mode for Slow mode and for ovdd=1.65 – 1.95 V, ipp_hve = 0 are
placed in Table 38:
Table 38. AC Electrical Characteristics of DDR2 IO Pads for Slow Mode and
for ovdd=1.65–1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times1
tpr
15pF
35pF
0.75/0.76
1.39/1.40
0.70/0.74
1.18/1.21
1.06/1.00
1.49/1.47
ns
Output Pad Propagation Delay, 50%-50% 1
tpo
15pF
35pF
1.50/1.55
2.05/2.16
1.90/1.95
2.36/2.48
3.23/3.10
3.82/3.75
ns
Output Pad Slew Rate1
tps
15pF
35pF
1.56/1.54
0.84/0.84
1.54/1.46
0.92/0.89
0.93/0.99
0.66/0.67
V/ns
Output Pad di/dt1
di/dt
—
82
40
19
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay without Hysteresis
(CMOS input), 50%-50%2
tpi
1.2 pF
0.45/0.93
0.6/0.58
0.9/0.88
ns
Input Pad Propagation Delay with Hysteresis
(CMOS input), 50%-50%2
tpi
1.2 pF
0.55/0.55
0.71/0.7
1.03/0.98
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.38/0.38
0.58/0.61
1.014/1.07
ns
Maximum Input Transition Times3
trm
—
—
—
5
ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
39
Electrical Characteristics
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, –40 °C and s0-s5 = 000000.
2
Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO
1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR mobile for Fast mode and ovdd=1.65 – 1.95 V, ipp_hve=0 are placed
in Table 39.
Table 39. AC Electrical Characteristics of DDR mobile IO Pads for Fast Mode and
ovdd=1.65–1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times (High Drive)1
tpr
15pF
35pF
1.35/1.31
2.99/2.94
1.02/1.03
2.28/2.29
0.89/0.89
1.85/1.94
ns
Output Pad Transition Times (Medium Drive)1
tpr
15pF
35pF
2.00/1.99
4.55/4.44
1.56/1.53
3.38/3.45
1.28/1.32
2.79/2.85
ns
Output Pad Transition Times (Low Drive)1
tpr
15pF
35pF
4.08/3.92
8.93/8.95
3.11/3.06
6.84/6.81
2.50/2.61
5.56/5.76
ns
Output Pad Propagation Delay (High Drive)1
tpo
15pF
35pF
1.54/1.52
2.69/2.75
1.73/1.62
2.59/2.55
2.36/2.09
3.04/2.86
ns
Output Pad Propagation Delay (Medium Drive)1
tpo
15pF
35pF
2.00/2.02
3.75/3.86
2.08/2.00
3.38/3.39
2.64/2.40
3.65/3.56
ns
Output Pad Propagation Delay (Low Drive)1
tpo
15pF
35pF
3.43/3.52
6.92/7.20
3.13/3.13
5.72/5.94
3.47/3.34
5.49/5.65
ns
Output Pad Slew Rate (High Drive)1
tps
15pF
35pF
0.87/0.89
0.39/0.40
1.06/1.05
0.47/0.47
1.11/1.11
0.54/0.51
V/ns
Output Pad Slew Rate (Medium Drive)1
tps
15pF
35pF
0.58/0.59
0.26/0.26
0.69/0.71
0.32/0.31
0.77/0.75
0.35/0.35
V/ns
Output Pad Slew Rate (Low Drive)1
tps
15pF
35pF
0.29/0.30
0.13/0.13
0.35/0.35
0.16/0.16
0.40/0.38
0.18/0.17
V/ns
Output Pad di/dt (High Drive)1
di/dt
—
185
91
46
mA/ns
Output Pad di/dt (Medium drive)1
di/dt
—
124
61
31
mA/ns
di/dt
—
62
30
16
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay without Hysteresis
(CMOS input), 50%-50%2
tpi
1.2 pF
0.45/0.93
0.6/0.58
0.9/0.88
ns
Input Pad Propagation Delay with Hysteresis
(CMOS input), 50%-50%2
tpi
1.2 pF
0.55/0.55
0.71/0.7
1.03/0.98
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.38/0.38
0.58/0.61
1.014/1.07
—
Maximum Input Transition Times3
trm
—
—
—
5
ns
Output Pad di/dt (Low
drive)1
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
40
Freescale Semiconductor
Electrical Characteristics
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, –40 °C and s0-s5 = 000000.
2
Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO
1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR mobile for Slow mode and ovdd=1.65-1.95V, ipp_hve=0 are placed
in Table 40.
Table 40. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode
ovdd=1.65–1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times (High Drive)1
tpr
15pF
35pF
1.42/1.43
3.03/2.92
1.20/1.27
2.39/2.38
1.43/1.49
2.35/2.46
ns
Output Pad Transition Times (Medium Drive)1
tpr
15pF
35pF
2.04/2.04
4.51/4.49
1.68/1.74
3.47/3.50
1.82/1.91
3.16/3.30
ns
Output Pad Transition Times (Low Drive)1
tpr
15pF
35pF
4.08/3.93
9.06/8.93
3.16/3.19
6.92/6.93
2.90/3.01
5.74/5.96
ns
Output Pad Propagation Delay (High Drive)1
tpo
15pF
35pF
2.00/2.17
3.15/3.42
2.33/2.50
3.24/3.52
3.70/3.70
4.63/4.75
ns
Output Pad Propagation Delay (Medium Drive)1
tpo
15pF
35pF
2.47/2.68
4.2/4.53
2.72/2.92
4.01/4.37
4.10/4.16
5.33/5.55
ns
Output Pad Propagation Delay (Low Drive)1
tpo
15pF
35pF
3.87/4.18
7.32/7.86
3.78/4.10
6.35/6.90
5.13/5.30
7.25/7.73
ns
Output Pad Slew Rate (High Drive)1
tps
15pF
35pF
0.82/0.82
0.39/0.40
0.90/0.85
0.45/0.49
0.69/0.66
0.42/0.40
V/ns
Output Pad Slew Rate (Medium Drive)1
tps
15pF
35pF
0.57/0.57
0.26/0.26
0.70/0.62
0.31/0.31
0.54/0.52
0.31/0.30
V/ns
Output Pad Slew Rate (Low Drive)1
tps
15pF
35pF
0.29/0.30
0.13/0.13
0.34/0.34
0.16/0.16
0.34/0.33
0.17/0.17
V/ns
Output Pad di/dt (High Drive)1
di/dt
47
14
9
mA/ns
Output Pad di/dt (Medium drive)1
di/dt
—
27
9
6
mA/ns
di/dt
—
12
5
3
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay without Hysteresis
(CMOS input), 50%-50%2
tpi
1.2 pF
0.45/0.93
0.6/0.58
0.9/0.88
ns
Input Pad Propagation Delay with Hysteresis
(CMOS input), 50%-50%2
tpi
1.2 pF
0.55/0.55
0.71/0.7
1.03/0.98
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.38/0.38
0.58/0.61
1.014/1.07
—
Maximum Input Transition Times3
trm
—
—
—
5
ns
Output Pad di/dt (Low
drive)1
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
41
Electrical Characteristics
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, –40 °C and s0-s5=000000.
2
Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO
1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR2 mode for Fast mode and for ovdd=1.65–1.95V, ipp_hve=0 are
placed in Table 41.
Table 41. AC Electrical Characteristics of DDR2_clk IO Pads for Fast mode and
for ovdd=1.65–1.95 V
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times1
tpr
15pF
35pF
0.58/0.57
1.29/1.28
0.45/0.44
0.97/0.93
0.45/0.45
0.82/0.85
ns
Output Pad Propagation Delay, 50%-50% 1
tpo
15pF
35pF
1.05/1.03
1.54/1.56
1.40/1.31
1.75/1.69
2.12/1.96
2.43/2.31
ns
Output Pad Slew Rate1
tps
15pF
35pF
2.02/2.05
0.91/0.91
2.40/2.45
1.11/1.16
2.20/2.20
1.21/1.16
V/ns
Output Pad di/dt1
di/dt
—
390
201
99
mA/ns
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.3/0.36
0.5/0.52
0.82/0.94
ns
Maximum Input Transition Times3
trm
—
—
—
5
ns
Input Pad Transition
Times2
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, -40 °C and s0-s5=000000.
2
Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO 1.8
V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and -40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR2 mode for Slow mode and for ovdd=1.65-1.95V, ipp_hve=0 are
placed in Table 42.
Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for
ovdd=1.65 – 1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times1
tpr
15pF
35pF
0.74/0.76
1.40/1.39
0.69/0.72
1.18/1.20
1.04/1.01
1.48/1.47
ns
Output Pad Propagation Delay, 50%-50% 1
tpo
15pF
35pF
1.56/1.61
2.12/2.22
2.02/2.08
2.49/2.61
3.45/3.33
4.05/3.98
ns
Output Pad Slew Rate1
tps
15pF
35pF
1.58/1.54
0.84/0.84
1.57/1.50
0.92/0.90
0.95/0.98
0.67/0.67
V/ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
42
Freescale Semiconductor
Electrical Characteristics
Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for
ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
di/dt
—
82
40
19
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.3/0.36
0.5/0.52
0.82/0.94
ns
Maximum Input Transition Times3
trm
—
—
—
5
ns
Parameter
Output Pad di/dt1
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, -40 °C and s0-s5=000000.
2 Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO 1.8
V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and -40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR mobile for Fast mode and ovdd=1.65-1.95V, ipp_hve=0 are placed in
Table 43.
Table 43. AC Electrical Characteristics of DDR_clk mobile IO Pads for Fast mode
and ovdd=1.65 – 1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times (High Drive)1
tpr
15pF
35pF
1.35/1.32
3.01/2.96
1.03/1.03
2.29/2.30
0.89/0.89
1.84/1.92
ns
Output Pad Transition Times (Medium Drive)1
tpr
15pF
35pF
1.98/1.98
4.52/4.38
1.55/1.54
3.46/3.45
1.29/1.30
2.80/2.88
ns
Output Pad Transition Times (Low Drive)1
tpr
15pF
35pF
3.99/3.94
8.93/8.86
3.10/3.04
6.77/6.85
2.50/2.57
5.40/5.68
ns
Output Pad Propagation Delay (High Drive)1
tpo
15pF
35pF
1.60/1.58
2.74/2.81
1.85/1.74
2.71/2.67
2.58/2.31
3.26/3.08
ns
Output Pad Propagation Delay (Medium Drive)1
tpo
15pF
35pF
2.07/2.08
3.79/3.92
2.19/2.12
3.46/3.51
2.86/2.62
3.87/3.77
ns
Output Pad Propagation Delay (Low Drive)1
tpo
15pF
35pF
3.47/3.57
6.94/7.26
3.23/3.25
5.84/6.06
3.69/3.55
5.73/5.87
ns
Output Pad Slew Rate (High Drive)1
tps
15pF
35pF
0.87/0.89
0.39/0.40
1.05/1.05
0.47/0.47
1.11/1.11
0.54/0.52
V/ns
Output Pad Slew Rate (Medium Drive)1
tps
15pF
35pF
0.59/0.59
0.26/0.27
0.70/0.70
0.31/0.31
0.77/0.76
0.35/0.34
V/ns
Output Pad Slew Rate (Low Drive)1
tps
15pF
35pF
0.29/0.30
0.13/0.13
0.35/0.36
0.16/0.16
0.40/0.39
0.18/0.17
V/ns
Output Pad di/dt (High Drive)1
di/dt
—
185
91
46
mA/ns
di/dt
—
124
61
31
mA/ns
Output Pad di/dt (Medium
drive)1
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
43
Electrical Characteristics
Table 43. AC Electrical Characteristics of DDR_clk mobile IO Pads for Fast mode
and ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
di/dt
—
62
30
16
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.3/0.36
0.5/0.52
0.82/0.94
—
Maximum Input Transition Times3
trm
—
—
—
5
ns
Parameter
Output Pad di/dt (Low drive)1
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, –40 °C and s0-s5=000000.
2 Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO
1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
AC electrical characteristics in DDR mobile for Slow mode and ovdd=1.65-1.95V, ipp_hve=0 are placed
in Table 44.
Table 44. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode and
ovdd=1.65 – 1.95 V (ipp_hve=0)
Parameter
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
Output Pad Transition Times (High Drive)1
tpr
15pF
35pF
1.42/1.42
3.01/2.96
1.20/1.27
2.38/2.40
1.43/1.49
2.37/2.44
ns
Output Pad Transition Times (Medium Drive)1
tpr
15pF
35pF
2.05/2.04
4.50/4.42
1.67/1.71
3.48/3.52
1.82/1.87
3.16/3.28
ns
Output Pad Transition Times (Low Drive)1
tpr
15pF
35pF
4.06/3.98
8.94/8.86
3.15/3.17
6.92/6.93
2.92/ 3.02
5.69/5.96
ns
Output Pad Propagation Delay (High Drive)1
tpo
15pF
35pF
2.07/2.23
3.21/3.48
2.46/2.62
3.35/3.63
3.92/3.93
4.84/4.97
ns
Output Pad Propagation Delay (Medium Drive)1
tpo
15pF
35pF
2.53/2.74
4.26/4.58
2.83/3.04
4.12/4.49
4.32/4.35
5.55/5.76
ns
Output Pad Propagation Delay (Low Drive)1
tpo
15pF
35pF
3.93/4.23
7.38/7.91
3.89/4.21
6.43/7.01
5.37/5.51
7.45/7.94
ns
Output Pad Slew Rate (High Drive)1
tps
15pF
35pF
0.82/0.82
0.39/0.40
0.90/0.85
0.45/0.45
0.69/0.66
0.42/0.41
V/ns
Output Pad Slew Rate (Medium Drive)1
tps
15pF
35pF
0.57/0.57
0.26/0.26
0.65/0.63
0.31/0.31
0.54/0.53
0.31/0.30
V/ns
Output Pad Slew Rate (Low Drive)1
tps
15pF
35pF
0.29/0.29
0.13/0.13
0.34/0.34
0.16/0.16
0.34/0.33
0.17/0.17
V/ns
Output Pad di/dt (High Drive)1
di/dt
—
47
14
9
mA/ns
di/dt
—
27
9
6
mA/ns
Output Pad di/dt (Medium
drive)1
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
44
Freescale Semiconductor
Electrical Characteristics
Table 44. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode and
ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)
Symbol
Test
Condition
Min
rise/fall
Typ
Max
rise/fall
Units
di/dt
—
12
5
3
mA/ns
Input Pad Transition Times2
trfi
1.2 pF
0.09/0.09 0.132/0.128 0.212/0.213
ns
Input Pad Propagation Delay (DDR input),
50%-50%2
tpi
1.2 pF
0.3/0.36
0.5/0.52
0.82/0.94
—
Maximum Input Transition Times3
trm
—
—
—
5
ns
Parameter
Output Pad di/dt (Low drive)1
1
Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,
tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,
IO 1.95 V, –40 °C and s0-s5=000000.
2 Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO
1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.
3
Hysteresis mode is recommended for input with transition time greater than 25 ns.
4.6
Module Timing
This section contains the timing and electrical parameters for the modules in the i.MX51 processor.
4.6.1
Reset Timings Parameters
Figure 12 shows the reset timing and Table 45 lists the timing parameters.
RESET_IN
(Input)
CC1
Figure 12. Reset Timing Diagram
Table 45. Reset Timing Parameters
ID
CC1
Parameter
Duration of RESET_IN to be qualified as valid (input slope = 5 ns)
Min
Max
Unit
50
—
ns
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
45
Electrical Characteristics
4.6.2
WDOG Reset Timing Parameters
Figure 13 shows the WDOG reset timing and Table 46 lists the timing parameters.
WATCHDOG_RST
(Input)
CC5
Figure 13. WATCHDOG_RST Timing Diagram
Table 46. WATCHDOG_RST Timing Parameters
ID
CC5
Parameter
Duration of WATCHDOG_RESET Assertion
Min
Max
Unit
1
—
TCKIL
NOTE
CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.
4.6.3
AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module.
4.6.4
Clock Amplifier Parameters (CKIH1, CKIH2)
The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave
or sinusoidal frequency source. No external series capacitors are required. Table 47 shows the CAMP
electrical parameters.
Table 47. CAMP Electrical Parameters (CKIH1, CKIH2)
Parameter
Min
Typ
Max
Unit
Input frequency
8.0
—
40.0
MHz
VIL (for square wave input)
0
—
0.3
V
VIH (for square wave input)
NVCC_PER3 - 0.25
—
NVCC_PER3
V
Sinusoidal input amplitude
0.4
—
VDD
Vp-p
Output duty cycle
45
50
55
%
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
46
Freescale Semiconductor
Electrical Characteristics
4.6.5
DPLL Electrical Parameters
Table 48 shows the DPLL electrical parameters.
Table 48. DPLL Electrical Parameters
Parameter
Test Conditions/Remarks
Min
Typ
Max
Unit
Reference clock frequency range1
—
10
—
100
MHz
Reference clock frequency range after
pre-divider
—
10
—
40
MHz
Output clock frequency range (dpdck_2)
—
300
—
1025
MHz
Pre-division factor2
—
1
—
16
—
Multiplication factor integer part
—
5
—
15
—
–67108862
—
67108862
—
—
1
—
67108863
—
—
48.5
50
51.5
%
Frequency lock
(FOL mode or non-integer MF)
—
—
—
398
Tdpdref
Phase lock time
—
—
—
100
µs
—
—
0.02
0.04
Tdck
Phase jitter (peak value)
FPL mode, integer and fractional MF
—
2.0
3.5
ns
Power dissipation
fdck = 300 MHz @ avdd = 1.8 V,
dvdd = 1.2 V
fdck = 650 MHz @ avdd = 1.8 V,
dvdd = 1.2 V
—
—
0.65 (avdd)
0.92 (dvdd)
1.98 (avdd)
1.8 (dvdd)
mW
Multiplication factor numerator3
Multiplication factor
denominator2
Output Duty Cycle
time4
Frequency
jitter5
(peak value)
Should be less than denominator
1
Device input range cannot exceed the electrical specifications of the CAMP, see Table 47.
The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user.Therefore,
the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.
3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be
zero.
4 T
dpdref is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
5 Tdck is the time period of the output clock, dpdck_2.
2
4.6.6
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among different signals of NFC at the module level
in the different operational modes.
Timing parameters in Figure 14, Figure 15, Figure 16, Figure 17, Figure 19, and Table 50 show the default
NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing
parameters in Figure 14, Figure 15, Figure 16, Figure 18, Figure 19, and Table 50 show symmetric NFC
mode using one Flash clock cycle per one access of RE_B and WE_B.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
47
Electrical Characteristics
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20
pF (except for NF16 - 40 pF) and there is max drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider. Table 49 demonstrates few examples for clock
frequency settings.
Table 49. NFC Clock Settings Examples
1
emi_slow_clk (MHz)
nfc_podf (Division Factor)
enfc_clk (MHz)
T—Clock Period (ns)1
133 (max value)
5 (reset value)
26.6
38
133
4
33.25
31
133
3
44.33
23
Rounded up to whole nanoseconds.
NOTE
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low the actual data bus capturing
might occur after the specified trhoh (RE_B high to output hold) period.
Setting the clock frequency above 25.6 MHz (T = 39 ns) guarantees proper
operation for devices having trhoh > 15 ns. It is also recommended to set the
NFC_FREQ_SEL Fuse accordingly to initiate the boot with 33.33 MHz
clock.
Lower frequency operation can be supported for most available devices in
the market, relying on data lines Bus-Keeper logic. This depends on device
behavior on the data bus in the time interval between data output valid to
data output high-Z state. In NAND device parameters this period is marked
between trhoh and trhz (RE_B high to output high-Z). In most devices, the
data transition from valid value to high-Z occurs without going through
other states. Setting the data bus pads to Bus-Keeper mode in the IOMUX
registers, keeps the data bus valid internally after the specified hold time,
allowing proper capturing with slower clock.
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Electrical Characteristics
NFCLE
NF2
NF1
NF3
NF4
NFCE_B
NF5
NFWE_B
NF8
NFIO[7:0]
NF9
command
Figure 14. Command Latch Cycle Timing
NF4
NF3
NFCE_B
NF10
NF11
NF5
NFWE_B
NF7
NF6
NFALE
NF8
NFIO[7:0]
NF9
Address
Figure 15. Address Latch Cycle Timing
NF3
NFCE_B
NF10
NF11
NF5
NFWE_B
NF8
NFIO[15:0]
NF9
Data to NF
Figure 16. Write Data Latch Timing
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49
Electrical Characteristics
NFCE_B
NF14
NF15
NF13
NFRE_B
NF17
NF16
NFRB_B
NF12
NFIO[15:0]
Data from NF
Figure 17. Read Data Latch Timing—Asymmetric Mode
NFCE_B
NF14
NF15
NF13
NFRE_B
NF16
NF18
NFRB_B
NF12
NFIO[15:0]
Data from NF
Figure 18. Read Data Latch Timing—Symmetric Mode
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Electrical Characteristics
NF19
NFCLE
NF20
NFCE_B
NFWE_B
NF21
NF22
NFRE_B
NFRB_B
Figure 19. Other Timing Parameters
Table 50. NFC—Timing Characteristics
ID
Parameter
Symbol
Asymmetric
Mode Min
Symmetric
Mode Min
Max
NF1
NFCLE setup Time
tCLS
2T-1
2T-1
—
NF2
NFCLE Hold Time
tCLH
T-4.45
T-4.45
—
NF3
NFCE_B Setup Time
tCS
2T-1
T-1
—
NF4
NFCE_B Hold Time
tCH
2T-5.55
0.5T-5.55
—
NF5
NFWE_B Pulse Width
tWP
T-2.5
0.5T-1.5
—
NF6
NFALE Setup Time
tALS
2T-2.7
2T-2.7
—
NF7
NFALE Hold Time
tALH
T-4.45
T-4.45
—
NF8
Data Setup Time
tDS
T-2.25
0.5T-2.25
—
NF9
Data Hold Time
tDH
T-6.55
0.5T-5.55
—
NF10
Write Cycle Time
tWC
2T
T
—
NF11
NFWE_B Hold Time
tWH
T-1.25
0.5T-1.25
—
NF12
Ready to NFRE_B Low
tRR
9T
9T
—
NF13
NFRE_B Pulse Width
tRP
1.5T-2.7
0.5T
—
NF14
READ Cycle Time
tRC
2T
T
—
NF15
NFRE_B High Hold Time
tREH
0.5T-1.5
0.5T-1.5
—
NF161
Data Setup on READ
tDSR
11.2+0.5T-Tdl2
11.2-Tdl2
—
NF173
Data Hold on READ
tDHR
0
—
2Taclk+T
NF184
Data Hold on READ
tDHR
—
Tdl2
2Taclk+T
NF19
CLE to RE delay
tCLR
13T
13T
—
NF20
CE to RE delay
tCRE
T-3.45
1.5T-3.45
—
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Electrical Characteristics
Table 50. NFC—Timing Characteristics (continued)
ID
Parameter
Symbol
Asymmetric
Mode Min
Symmetric
Mode Min
Max
NF21
WE high to RE low
tWHR
14T-5.45
14T-5.45
—
NF22
WE high to busy
tWB
—
—
6T
1
tDSR is calculated by the following formula:
Asymmetric mode: tDSR = tREpd + tDpd + 1/2T – Tdl2
Symmetric mode: tDSR = tREpd + tDpd – Tdl2
tREpd + tDpd = 11.2 ns (including clock skew)
where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay
from IO pad to EMI including IO pad delay.
tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR.
2
Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk
period (Taclk). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates
a total of 1 aclk period. Taclk is “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).
3 NF17 is defined only in asymmetric operation mode.
NF17 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
4 NF18 is defined only in Symmetric operation mode.
tDHR (MIN) is calculated by the following formula:
Tdl2 – (tREpd + tDpd)
where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay
from IO pad to EMI including IO pad delay.
NF18 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
4.6.7
External Interface Module (WEIM)
The following sections provide information on the WEIM.
4.6.7.1
WEIM Signal Cross Reference
Table 51 is a guide to help the user identify signals in the WEIM Chapter of the i.MX51 Multimedia
Applications Processor Reference Manual (MCIMX51RM) that are the same as those mentioned in this
data sheet.
Table 51. WEIM Signal Cross Reference
Reference Manual
WEIM Chapter Nomenclature
BCLK
Data Sheet Nomenclature,
Reference Manual External Signals and Pin Multiplexing Chapter,
and IOMUX Controller Chapter Nomenclature
EIM_BCLK
CSx
EIM_CSx
WE_B
EIM_RW
OE_B
EIM_OE
BEy_B
EIM_EBx
ADV
EIM_LBA
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Table 51. WEIM Signal Cross Reference (continued)
Data Sheet Nomenclature,
Reference Manual External Signals and Pin Multiplexing Chapter,
and IOMUX Controller Chapter Nomenclature
Reference Manual
WEIM Chapter Nomenclature
ADDR
EIM_A[27:16], EIM_DA[15:0]
ADDR/M_DATA
EIM_DAx (Addr/Data muxed mode)
DATA
EIM_NFC_D (Data bus shared with NAND Flash)
EIM_Dx (dedicated data bus)
WAIT_B
4.6.7.2
EIM_WAIT
WEIM Internal Module Multiplexing
Table 52 provides WEIM internal muxing information.
38 4
Table 52. WEIM Interface Pinout in Various Configurations
Multiplexed
Address/Data Mode
(MUM=1)
Non Multiplexed Address/Data Mode
(MUM=0)
16-Bit
32-Bit
8-Bit
8-Bit
8-Bit1
16-Bit
16-Bit
32-Bit
8-Bit
(DSZ=100) (DSZ=101) (DSZ=110 (DSZ=111 (DSZ=001) (DSZ=010) (DSZ=011 (DSZ=001) (DSZ=011)
)
)
)
1
A[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
A[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
EIM_A
[27:16]
NANDF_D
[11:0]
D[7:0],
EIM_EB0
NANDF_D
[7:0]
—
—
—
NANDF_D
[7:0]
—
NANDF_D
[7:0]
EIM_DA
[7:0]
EIM_DA
[7:0]
D[15:8],
EIM_EB1
—
NANDF_D
[15:8]
—
—
NANDF_D
[15:8]
—
NANDF_D
[15:8]
EIM_DA
[15:8]
EIM_DA
[15:8]
D[23:16],
EIM_EB2
—
—
EIM_D
[23:16]
—
—
EIM_D
[23:16]
EIM_D
[23:16]
—
NANDF_D
[7:0]
D[31:24],
EIM_EB3
—
—
—
EIM_D
[31:24]
—
EIM_D
[31:24]
EIM_D
[31:24]
—
NANDF_D
[15:8]
This mode is not supported due to erratum ENGcm11244.
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53
Electrical Characteristics
4.6.7.3
General WEIM Timing-Synchronous Mode
Figure 20, Figure 21, and Table 53 specify the timings related to the WEIM module. All WEIM output
control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising
edge according to corresponding assertion/negation control fields.
,
WE2
...
BCLK
WE3
WE1
WE4
WE5
Address
WE6
WE7
WE8
WE9
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
CSx_B
WE_B
OE_B
BEy_B
ADV_B
Output Data
Figure 20. WEIM Outputs Timing Diagram
BCLK
WE18
Input Data
WE19
WE20
WAIT_B
WE21
Figure 21. WEIM Inputs Timing Diagram
Table 53. WEIM Bus Timing Parameters 1
BCD = 0
ID
BCD = 1
BCD = 2
BCD = 3
Parameter
Min
WE1
BCLK Cycle time2
WE2
BCLK Low Level
Width
Max
Min
Max
Min
Max
Min
t
2xt
3xt
4xt
0.4 x t
0.8 x t
1.2 x t
1.6 x t
Max
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Electrical Characteristics
Table 53. WEIM Bus Timing Parameters (continued)1
BCD = 0
ID
BCD = 1
BCD = 2
BCD = 3
Parameter
Min
Max
0.4 x t
Min
Max
0.8 x t
Min
Max
1.2 x t
Min
Max
WE3
BCLK High Level
Width
1.6 x t
WE4
Clock rise to address
valid3
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t
+1.75
-2 x t 1.25
-2 x t +
1.75
WE5
Clock rise to address
invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE6
Clock rise to CSx_B
valid
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t +
1.75
-2 x t 1.25
-2 x t +
1.75
WE7
Clock rise to CSx_B
invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE8
Clock rise to WE_B
Valid
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t +
1.75
-2 x t 1.25
-2 x t +
1.75
WE9
Clock rise to WE_B
Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE10 Clock rise to OE_B
Valid
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t +
1.75
-2 x t 1.25
-2 x t +
1.75
WE11 Clock rise to OE_B
Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE12 Clock rise to BEy_B
Valid
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t +
1.75
-2 x t 1.25
-2 x t +
1.75
WE13 Clock rise to BEy_B
Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE14 Clock rise to ADV_B
Valid
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t +
1.75
-2 x t 1.25
-2 x t +
1.75
WE15 Clock rise to ADV_B
Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE16 Clock rise to Output
Data Valid
-0.5 x t 1.25
-0.5 x t +
1.75
-t - 1.25
-t + 1.75
-1.5 x t 1.25
-1.5 x t +
1.75
-2 x t 1.25
-2 x t +
1.75
WE17 Clock rise to Output
Data Invalid
0.5 x t 1.25
0.5 x t + 1.75
t - 1.25
t + 1.75
1.5 x t 1.25
1.5 x t +
1.75
2xt1.25
2 x t + 1.75
WE18 Input Data setup time
to Clock rise
2 ns
—
4 ns
—
—
—
—
—
WE19 Input Data hold time
from Clock rise
2 ns
—
2 ns
—
—
—
—
—
WE20 WAIT_B setup time to
Clock rise
2 ns
—
4 ns
—
—
—
—
—
WE21 WAIT_B hold time
from Clock rise
2 ns
—
2 ns
—
—
—
—
—
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Electrical Characteristics
1
t is the maximal WEIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum
allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be ≤ 104 MHz. If BCD = 1, then 133 MHz is allowed
for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are
impacted which are clocked from this source. See the CCM chapter of the i.MX51 Reference Manual for a detailed clock tree
description.
2
BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
3
For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
4.6.7.4
Examples of WEIM Synchronous Accesses
Figure 22 to Figure 25 provide few examples of basic WEIM accesses to external memory devices with
the timing parameters mentioned previously for specific control parameters settings.
BCLK
WE4
ADDR
WE5
Address v1
Last Valid Address
WE6
WE7
CSx_B
WE_B
WE14
ADV_B
WE15
WE10
WE11
WE12
WE13
OE_B
BEy_B
WE18
DATA
D(v1)
WE19
Figure 22. Synchronous Memory Read Access, WSC=1
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Electrical Characteristics
BCLK
WE5
WE4
ADDR
Last Valid Address
Address V1
WE6
WE7
WE8
WE9
CSx_B
WE_B
WE14
ADV_B
WE15
OE_B
WE13
WE12
BEy_B
WE16
WE17
DATA
D(V1)
Figure 23. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0
BCLK
ADDR/
M_DATA
WE4
Valid
LastAddr
WE6
WE5
WE17
WE16
Write Data
Address V1
WE7
CSx_B
WE8
WE_B
WE14
WE9
WE15
ADV_B
OE_B
WE10
WE11
BEy_B
Figure 24. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
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Electrical Characteristics
BCLK
ADDR/
M_DATA
WE4
Last Valid Addr
WE6
WE19
WE5
Address V1
Data
WE18
CSx_B
WE7
WE_B
WE14
ADV_B
WE15
WE10
WE11
OE_B
WE12
WE13
BEy_B
Figure 25. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0
4.6.7.5
General WEIM Timing-Asynchronous Mode
Figure 26 through Figure 31, and Table 54 help to determine timing parameters relative to the chip select
(CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the
timing parameters mentioned above.
Asynchronous read and write access length in cycles may vary from what is shown in Figure 26 through
Figure 29 as RWSC, OEN, and CSN is configured differently. See i.MX51 reference manual for the
WEIM programming model.
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Electrical Characteristics
end of
access
start of
access
INT_CLK
MAXCSO
CSx_B
ADDR/
M_DATA
WE31
Last Valid Address
WE32
Next Address
Address V1
WE_B
ADV_B
WE39
WE40
WE35
WE36
WE37
WE38
OE_B
BEy_B
WE44
MAXCO
DATA[7:0]
D(V1)
WE43
MAXDI
Figure 26. Asynchronous Memory Read Access (RWSC = 5)
end of
access
start of
access
INT_CLK
MAXCSO
CSx_B
MAXDI
WE31
ADDR/
M_DATA
Addr. V1
D(V1)
WE32A
WE_B
WE44
WE40A
WE39
ADV_B
WE35A
WE36
OE_B
WE37
WE38
BEy_B
MAXCO
Figure 27. Asynchronous A/D Muxed Read Access (RWSC = 5)
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59
Electrical Characteristics
CSx_B
WE31
ADDR
Last Valid Address
WE33
WE32
Next Address
Address V1
WE34
WE_B
WE39
WE40
WE45
WE46
ADV_B
OE_B
BEy_B
WE42
DATA
D(V1)
WE41
Figure 28. Asynchronous Memory Write Access
CSx_B
WE31
ADDR/
M_DATA
WE41A
Addr. V1
D(V1)
WE32A
WE33
WE34
WE42
WE_B
WE40A
ADV_B
WE39
OE_B
WE45
WE46
BEy_B
WE42
Figure 29. Asynchronous A/D Muxed Write Access
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Electrical Characteristics
CSx_B
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
WE_B
WE39
WE40
WE35
WE36
WE37
WE38
ADV_B
OE_B
BEy_B
WE44
DATA[7:0]
D(V1)
WE43
WE48
DTACK
WE47
Figure 30. DTACK Read Access (DAP=0)
CSx_B
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
WE33
WE34
WE39
WE40
WE45
WE46
WE_B
ADV_B
OE_B
BEy_B
WE42
DATA
D(V1)
WE41
WE48
DTACK
WE47
Figure 31. DTACK Write Access (DAP=0)
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Electrical Characteristics
Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select
Ref No.
Parameter
Determination by
Synchronous measured
parameters 12
Min
Max
(If 133 MHz is
supported by SOC)
Unit
WE31
CSx_B valid to Address Valid
WE4 - WE6 - CSA3
—
3 - CSA
ns
WE32
Address Invalid to CSx_B
invalid
WE7 - WE5 - CSN4
—
3 - CSN
ns
t5 + WE4 - WE7 + (ADVN +
ADVA + 1 - CSA3)
-3 + (ADVN +
ADVA + 1 - CSA)
—
ns
WE32A( CSx_B valid to Address Invalid
muxed
A/D
WE33
CSx_B Valid to WE_B Valid
WE8 - WE6 + (WEA - CSA)
—
3 + (WEA - CSA)
ns
WE34
WE_B Invalid to CSx_B Invalid
WE7 - WE9 + (WEN - CSN)
—
3 - (WEN_CSN)
ns
WE35
CSx_B Valid to OE_B Valid
WE10 - WE6 + (OEA - CSA)
—
3 + (OEA - CSA)
ns
WE35A
(muxed
A/D)
CSx_B Valid to OE_B Valid
WE36
OE_B Invalid to CSx_B Invalid
3 + (OEA +
WE10 - WE6 + (OEA + RADVN
-3 + (OEA +
+ RADVA + ADH + 1 - CSA) RADVN+RADVA+ RADVN+RADVA+AD
H+1-CSA)
ADH+1-CSA)
WE7 - WE11 + (OEN - CSN)
—
3 - (OEN - CSN)
(RBEA6
ns
ns
WE37
CSx_B Valid to BEy_B Valid
(Read access)
WE12 - WE6 + (RBEA - CSA)
—
3+
- CSA)
ns
WE38
BEy_B Invalid to CSx_B Invalid
(Read access)
WE7 - WE13 + (RBEN - CSN)
—
3 - (RBEN7- CSN)
ns
WE39
CSx_B Valid to ADV_B Valid
WE14 - WE6 + (ADVA - CSA)
—
3 + (ADVA - CSA)
ns
WE40
ADV_B Invalid to CSx_B
Invalid (ADVL is asserted)
WE7 - WE15 - CSN
—
3 - CSN
ns
-3 + (ADVN +
ADVA + 1 - CSA)
3 + (ADVN + ADVA +
1 - CSA)
ns
WE40A
(muxed
A/D)
CSx_B Valid to ADV_B Invalid WE14 - WE6 + (ADVN + ADVA
+ 1 - CSA)
WE41
CSx_B Valid to Output Data
Valid
WE16 - WE6 - WCSA
—
3 - WCSA
ns
WE41A
(muxed
A/D)
CSx_B Valid to Output Data
Valid
WE16 - WE6 + (WADVN +
WADVA + ADH + 1 - WCSA)
—
3 + (WADVN +
WADVA + ADH + 1 WCSA)
ns
WE42
Output Data Invalid to CSx_B
Invalid
WE17 - WE7 - CSN
—
3 - CSN
ns
MAXCO Output max. delay from internal
driving ADDR/control FFs to
chip outputs.
10
—
—
ns
MAXCS Output max. delay from CSx
O
internal driving FFs to CSx out.
10
—
—
MAXDI
5
—
—
DATA MAXIMUM delay from
chip input data to its internal FF
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Electrical Characteristics
Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select
Determination by
Synchronous measured
parameters 12
Max
(If 133 MHz is
supported by SOC)
Unit
MAXCO MAXCSO +
MAXDI
—
ns
0
0
—
ns
WE12 - WE6 + (WBEA - CSA)
—
3 + (WBEA - CSA)
ns
BEy_B Invalid to CSx_B Invalid WE7 - WE13 + (WBEN - CSN)
(Write access)
—
-3 + (WBEN - CSN)
ns
—
—
—
MAXCO MAXCSO +
MAXDTI
—
ns
0
—
ns
Ref No.
Parameter
WE43
Input Data Valid to CSx_B
Invalid
MAXCO - MAXCSO + MAXDI
WE44
CSx_B Invalid to Input Data
invalid
WE45
CSx_B Valid to BEy_B Valid
(Write access)
WE46
MAXDTI DTACK MAXIMUM delay from
chip dtack input to its internal
FF + 2 cycles for
synchronization
1
2
3
4
5
6
7
WE47
Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI
WE48
CSx_B Invalid to Dtack invalid
0
Min
Parameters WE4... WE21 value see column BCD = 0 in Table 53.
All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.
CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.
CS Negation. This bit field determines when CS signal is negated during read/write cycles.
t is axi_clk cycle time.
BE Assertion. This bit field determines when BE signal is asserted during read cycles.
BE Negation. This bit field determines when BE signal is negated during read cycles.
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63
Electrical Characteristics
4.6.8
SDRAM Controller Timing Parameters
4.6.8.1
Mobile DDR SDRAM Timing Parameters
Figure 32 shows the basic timing parameters for mobile DDR (mDDR) SDRAM. The timing parameters
for this diagram is shown in Table 55.
DD1
SDCLK
SDCLK
DD2
DD4
DD3
CS
DD5
RAS
DD5
DD4
CAS
DD4
DD5
DD5
WE
DD6
ADDR
DD7
ROW/BA
COL/BA
Figure 32. mDDR SDRAM Basic Timing Parameters
Table 55. mDDR SDRAM Timing Parameter Table
200 MHz
ID
1
Parameter
166 MHz
133 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
DD1
SDRAM clock high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DD2
SDRAM clock low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DD3
SDRAM clock cycle time
tCK
5
—
6
—
7.5
—
ns
DD4
CS, RAS, CAS, CKE, WE setup time
tIS1
0.9
—
1.1
—
1.3
—
ns
DD5
CS, RAS, CAS, CKE, WE hold time
tIH1
0.9
—
1.1
—
1.3
—
ns
DD6
Address output setup time
tIS1
0.9
—
1.1
—
1.3
—
ns
DD7
Address output hold time
tIH1
0.9
—
1.1
—
1.3
—
ns
This parameter is affected by pad timing. if the slew rate is < 1 V/ns, 0.2 ns should be added to the value. For cmos65 pads
this is true for medium and low drive strengths.
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Electrical Characteristics
Figure 33 shows the timing diagram for mDDR SDRAM write cycle. The timing parameters for this
diagram is shown in Table 56.
SDCLK
SDCLK_B
DD19
DD22
DD21
DQS (output)
DD18
DD17
DQ (output)
DD20
DD23
DD17
DD18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DQM (output)
DD17
DD18
DD17
DD18
Figure 33. mDDR SDRAM Write cycle Timing Diagram
Table 56. mDDR SDRAM Write Cycle Parameter Table 1
200 MHz2
ID
Parameter
166 MHz
133 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
DD17
DQ and DQM setup time to DQS
tDS3
0.48
—
0.6
—
0.8
—
ns
DD18
DQ and DQM hold time to DQS
tDH1
0.48
—
0.6
—
0.8
—
ns
DD19
Write cycle DQS falling edge to
SDCLK output setup time
tDSS
0.2
—
0.2
—
0.2
—
tCK
DD20
Write cycle DQS falling edge to
SDCLK output hold time
tDSH
0.2
—
0.2
—
0.2
—
tCK
DD21
Write command to first DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DD22
DQS high level width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DD23
DQS low level width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
1
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
2 SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
3 This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.
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65
Electrical Characteristics
Figure 34 shows the timing diagram for mDDR SDRAM DQ versus DQS and SDCLK read cycle. The
timing parameters for this diagram is shown in Table 57.
SDCLK
SDCLK_B
DD26
DQS (input)
DD25
DD24
Data
DQ (input)
Data
Data
Data
Data
Data
Data
Data
Figure 34. mDDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
Table 57. mDDR SDRAM Read Cycle Parameter Table1
200 MHz2
ID
PARAMETER
166 MHz
133 MHz
Symbol
Unit
Min Max Min Max Min Max
DD24 DQS - DQ Skew (defines the Data valid window in read cycles
related to DQS)
DD25 DQS DQ in HOLD time from DQS
DD26 DQS output access time from SDCLK posedge
tDQSQ
—
0.4
—
0.75
—
0.85
ns
tQH
1.75
—
2.05
—
2.6
—
ns
tDQSCK
2
5
2
5.5
2
6.5
ns
1
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls
2
SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock)
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Electrical Characteristics
4.6.9
DDR2 SDRAM Specific Parameters
Figure 35 shows the timing parameters for DDR2. The timing parameters for this diagram appear in
Table 58.
DDR1
SDCLK
SDCLK
DDR2
DDR4
DDR3
CS
DDR5
RAS
DDR5
DDR4
CAS
DDR4
DDR5
DDR5
WE
ODT/CKE
DDR4
DDR6
ADDR
DDR7
ROW/BA
COL/BA
Figure 35. DDR2 SDRAM Basic Timing Parameters
Table 58. DDR2 SDRAM Timing Parameter Table
SDCLK = 200 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
DDR2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
DDR3
SDRAM clock cycle time
tCK
5
—
ns
1
1.5
—
ns
1.7
—
ns
DDR4
CS, RAS, CAS, CKE, WE, ODT setup time
tIS
DDR5
CS, RAS, CAS, CKE, WE, ODT hold time
tIH1
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67
Electrical Characteristics
Table 58. DDR2 SDRAM Timing Parameter Table (continued)
SDCLK = 200 MHz
ID
DDR6
DDR7
1
Parameter
Symbol
Address output setup time
Address output hold time
Unit
Min
Max
tIS1
1.7
—
ns
1
1.5
—
ns
tIH
These values are for command/address slew rates of 1 V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For
different values use the settings shown in Table 59.
NOTE
Measurements are taken from Vref to Vref (cross-point to cross-point), but
JEDEC timings for single-ended signals are defined from Vref to Vil(ac)
max or to Vih(ac) min.
Table 59. Derating Values for DDR2-400 (SDCLK = 200 MHz)
Command /
Address
Slew Rate
(V/ns)
SDCLK Differential Slew Rates1,2
2.0 V/ns
1.5 V/ns
1.0 V/ns
Unit
ΔtlS
ΔtlH
ΔtlS
ΔtlH
ΔtlS
ΔtlH
4.0
+187
+94
+217
+124
+247
+154
ps
3.5
+179
+89
+209
+119
+239
+149
ps
3.0
+167
+83
+197
+113
+227
+143
ps
2.5
+150
+75
+180
+105
+210
+135
ps
2.0
+125
+45
+155
+75
+185
+105
ps
1.5
+83
+21
+113
+51
+143
+81
ps
1.0
+0
+0
+30
+30
+60
+60
ps
0.9
–11
–14
+19
+16
+49
+46
ps
0.8
–25
–31
+5
–1
+35
+29
ps
0.7
–43
–54
–13
–24
+17
+6
ps
0.6
–67
–83
–37
–53
–7
–23
ps
0.5
–110
–125
–80
–95
–50
–65
ps
0.4
–175
–188
–145
–158
–115
–128
ps
0.3
–285
–292
–255
–262
–225
–232
ps
0.25
–350
–375
–320
–345
–290
–315
ps
0.2
–525
–500
–495
–470
–465
–440
ps
0.15
–800
–708
–770
–678
–740
–648
ps
0.1
–1450
–1125
–1420
–1095
–1390
–1065
ps
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Electrical Characteristics
1
Test conditions are: Capacitance 15 pF for DDR contacts. Recommended drive strengths: Medium for SDCLK and High for
address and controls.
2
SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal
value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of
SDCLK and SDCLK_B.
Figure 36 shows the timing diagram for DDR2 SDRM write cycle. The timing parameters for this diagram
appear in Table 60.
SDCLK
DDR20
SDCLK_B
DDR21
DDR22
DQS (output)
DDR18
DDR17
DQ (output)
DQM (output)
DDR19
DDR23
DDR17
DDR18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DDR17
DDR18
DDR17
DDR18
Figure 36. DDR2 SDRAM Write Cycle Timing Diagram
Table 60. DDR2 SDRAM Write Cycle Parameter Table
SDCLK = 200 MHz
ID
DDR17
Parameter
DQ & DQM setup time to DQS
Symbol
Unit
Min
Max
tDS
0.81
—
ns
—
ns
DDR18
DQ & DQM hold time to DQS
tDH
0.82
DDR19
DQS falling edge to SDCLK output setup time
tDSS
1.6
—
ns
DDR20
DQS falling edge SDCLK output hold time
tDSH
2.4
—
ns
DDR21
DQS latching rising transitions to associated clock edges
tDQSS
-0.7
0.3
ns
DDR22
DQS high level width
tDQSH
0.35
—
tCK
DDR23
DQS low level width
tDQSL
0.35
—
tCK
1
- In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ
window. The minimum window width is 1.6ns (DDR17+DDR18).
- From DDR controller perspective, the timing is the same for both differential and single ended mode.
2 - In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ
window. The minimum window width is 1.6ns (DDR17+DDR18).
- From DDR controller perspective, the timing is the same for both differential and single ended mode.
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69
Electrical Characteristics
NOTE
Measurements are taken from Vref to Vref (cross-point to cross-point), but
JEDEC timings for single-ended signals are defined from Vref to Vil(ac)
max or to Vih(ac) min.
Table 61. Derating values for DDR2 Differential DQS1,2
Table 62. Derating values for DDR2 Single Ended DQS3,4
1. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
3. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
address and controls.
4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
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Electrical Characteristics
Figure 37 shows the timing diagram for DDR2 SDRM read cycle. The timing parameters for this diagram
appear in Table 63.
SDCLK
SDCLK_B
DQS (input)
DDR24
DDR25
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 37. DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
Table 63. DDR2 SDRAM Read Cycle Parameter Table
SDCLK = 200 MHz
ID
Parameter
DDR241 DQS—DQ Skew (defines the Data valid window during read cycles
related to DQS).
DDR252 DQ HOLD time from DQS
Symbol
Unit
Min
Max
tDQSQ
—
0.5
ns
tQH
1.8
—
ns
1
The actual timing may vary depending on read calibration settings. What is actually important for the controller is
DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.
2 The actual timing may vary depending on read calibration settings. What is actually important for the controller is
DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.
NOTE
It is recommended to perform read calibration process in order to achieve
the best performance.
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Freescale Semiconductor
71
Electrical Characteristics
4.7
External Peripheral Interfaces
The following sections provide information on external peripheral interfaces.
4.7.1
CSPI Timing Parameters
This section describes the timing parameters of the CSPI. The CSPI has separate timing parameters for
master and slave modes. The nomenclature used with the CSPI modules and the respective routing of
these signals is shown in Table 64.
Table 64. CSPI Nomenclature and Routing
Module
I/O Access
eCSPI1
CSPI11, USBH1, and DI1 via IOMUX
eCSPI2
NANDF and USBH1 via IOMUX
CSPI
NANDF, USBH1, SD1, SD2, and GPIO via IOMUX
1
4.7.1.1
This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel
CSPI Master Mode Timing
Figure 38 depicts the timing of CSPI in Master mode and Table 65 lists the CSPI Master Mode timing
characteristics.
RDY
CS10
SSx
CS1
CS5
CS6
CS2
CS3
CS4
SCLK
CS7
CS2
CS3
MOSI
CS8
CS9
MISO
Figure 38. CSPI Master Mode Timing Diagram
Table 65. CSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time
tclk
60
—
ns
CS2
SCLK High or Low Time
tSW
26
—
ns
tRISE/FALL
—
—
ns
tCSLH
26
—
ns
Fall1
CS3
SCLK Rise or
CS4
SSx pulse width
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Electrical Characteristics
Table 65. CSPI Master Mode Timing Parameters (continued)
ID
Parameter
2
Min
Max
Unit
CS5
SSx Lead Time (Slave Select
setup time)
tSCS
26
—
ns
CS6
SSx Lag Time (SS hold time)
tHCS
26
—
ns
CS7
MOSI Propagation Delay
(CLOAD = 20 pF)
tPDmosi
–1
21
ns
CS8
MISO Setup Time
tSmiso
5
—
ns
CS9
MISO Hold Time
tHmiso
5
—
ns
tSDRY
5
—
ns
CS10
1
Symbol
RDY to SSx
Time2
See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.7.1.2
CSPI Slave Mode Timing
Figure 39 depicts the timing of CSPI in Slave mode. Table 66 lists the CSPI Slave Mode timing
characteristics.
SSx
CS2
CS1
CS5
CS6
CS4
SCLK
CS2
CS9
MISO
CS7
CS8
MOSI
Figure 39. CSPI Slave Mode Timing Diagram
Table 66. CSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time
tclk
60
—
ns
CS2
SCLK High or Low Time
tSW
26
—
ns
CS4
SSx pulse width
tCSLH
26
—
ns
CS5
SSx Lead Time (SS setup time)
tSCS
26
—
ns
CS6
SSx Lag Time (SS hold time)
tHCS
26
—
ns
CS7
MOSI Setup Time
tSmosi
5
—
ns
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73
Electrical Characteristics
Table 66. CSPI Slave Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS8
MOSI Hold Time
tHmosi
5
—
ns
CS9
MISO Propagation Delay (CLOAD = 20 pF)
tPDmiso
0
35
ns
4.7.2
eCSPI Timing Parameters
This section describes the timing parameters of the eCSPI. The eCSPI has separate timing parameters for
master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these
signals is shown in Table 64.
4.7.2.1
eCSPI Master Mode Timing
Figure 40 depicts the timing of eCSPI in Master mode and Table 67 lists the eCSPI Master Mode timing
characteristics.
eCSPIx_DRYN1
CS11
eCSPIx_CS_x
CS1
CS2
CS3
CS6
CS5
CS4
eCSPIx_CLK
CS7 CS8
CS3
CS2
eCSPIx_DO
CS9 CS10
eCSPIx_DI
Figure 40. eCSPI Master Mode Timing Diagram
Table 67. eCSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
eCSPIx_CLK Cycle Time–Read
eCSPIx_CLK Cycle Time–Write
tclk
60
15
—
ns
CS2
eCSPIx_CLK High or Low Time
tSW
6
—
ns
CS3
eCSPIx_CLK Rise or Fall
tRISE/FALL
—
—
ns
CS4
eCSPIx_CS_x pulse width
tCSLH
15
—
ns
CS5
eCSPIx_CS_x Lead Time (CS setup time)
tSCS
5
—
ns
CS6
eCSPIx_CS_x Lag Time (CS hold time)
tHCS
5
—
ns
CS7
eCSPIx_DO Setup Time
tSmosi
5
—
ns
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Freescale Semiconductor
Electrical Characteristics
Table 67. eCSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS8
eCSPIx_DO Hold Time
tHmosi
5
—
ns
CS9
eCSPIx_DI Setup Time
tSmiso
5
—
ns
CS10
eCSPIx_DI Hold Time
tHmiso
5
—
ns
CS11
eCSPIx_DRYN Setup Time
tSDRY
5
—
ns
4.7.2.2
eCSPI Slave Mode Timing
Figure 41 depicts the timing of eCSPI in Slave mode and Table 68 lists the eCSPI Slave Mode timing
characteristics.
eCSPIx_CS_x
CS1
CS2
CS3
CS6
CS5
CS4
eCSPIx_CLK
CS9CS10
CS3
CS2
eCSPIx_DI
CS7 CS8
eCSPIx_DO
Figure 41. eCSPI Slave Mode Timing Diagram
Table 68. eCSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
eCSPIx_CLK Cycle Time–Read
eCSPIx_CLK Cycle Time–Write
tclk
60
15
—
ns
CS2
eCSPIx_CLK High or Low Time
tSW
6
—
ns
CS3
eCSPIx_CLK Rise or Fall
tRISE/FALL
—
—
ns
CS4
eCSPIx_CS_x pulse width
tCSLH
15
—
ns
CS5
eCSPIx_CS_x Lead Time (CS setup time)
tSCS
5
—
ns
CS6
eCSPIx_CS_x Lag Time (CS hold time)
tHCS
5
—
ns
CS7
eCSPIx_DO Setup Time
tSmosi
5
—
ns
CS8
eCSPIx_DO Hold Time
tHmosi
5
—
ns
CS9
eCSPIx_DI Setup Time
tSmiso
5
—
ns
CS10
eCSPIx_DI Hold Time
tHmiso
5
—
ns
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75
Electrical Characteristics
4.7.3
eSDHCv2 Timing Parameters
This section describes the electrical information of the eSDHCv2.
Figure 42 depicts the timing of eSDHCv2, and Table 69 lists the eSDHCv2 timing characteristics.
SD4
SD2
SD1
SD5
MMCx_CLK
SD3
MMCx_CMD
MMCx_DAT_0
MMCx_DAT_1
output from eSDHCv2 to card
......
MMCx_DAT_7
SD6
SD7
SD8
MMCx_CMD
MMCx_DAT_0
MMCx_DAT_1
input from card to eSDHCv2
......
MMCx_DAT_3
Figure 42. eSDHCv2 Timing
Table 69. eSDHCv2 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (Low Speed)
fPP1
0
400
kHz
Clock Frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50
MHz
Clock Frequency (MMC Full Speed/High Speed)
fPP3
0
20/52
MHz
Clock Frequency (Identification Mode)
fOD
100
400
kHz
SD2
Clock Low Time
tWL
7
—
ns
SD3
Clock High Time
tWH
7
—
ns
SD4
Clock Rise Time
tTLH
—
3
ns
SD5
Clock Fall Time
tTHL
—
3
ns
3
ns
Card Input Clock
SD1
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD64
eSDHC Output Delay
tOD
–3
eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)
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Table 69. eSDHCv2 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD7
eSDHC Input Setup Time
tISU
2.5
—
ns
SD8
eSDHC Input Hold Time
tIH5
2.5
—
ns
1
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock
frequency can be any value between 0–50 MHz.
3
In normal speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
4
Measurement taken with CLoad = 20 pF
5
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2
4.7.4
FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII
pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see i.MX51
Multimedia Applications Processor Reference Manual (MCIMX51RM).
This section describes the AC timing specifications of the FEC.
4.7.4.1
MII Receive Signal Timing
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must
exceed twice the FEC_RX_CLK frequency. Table 70 lists the MII receive channel signal timing
parameters and Figure 43 shows MII receive signal timings.
.
1
Table 70. MII Receive Signal Timing
Num
Characteristic1
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
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M3
FEC_RX_CLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M1
M2
Figure 43. MII Receive Signal Timing Diagram
4.7.4.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 71 lists MII transmit channel timing parameters
and Figure 44 shows MII transmit signal timing diagram for the values listed in Table 71.
Table 71. MII Transmit Signal Timing
Characteristic1
Num
1
Min
Max
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
.
M7
FEC_TX_CLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M6
Figure 44. MII Transmit Signal Timing Diagram
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4.7.4.3
MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 72 lists MII asynchronous inputs signal timing information. Figure 45 shows MII asynchronous
input timings listed in Table 72.
Table 72. MII Async Inputs Signal Timing
1
Num
Characteristic
Min
Max
Unit
M91
FEC_CRS to FEC_COL minimum pulse width
1.5
—
FEC_TX_CLK period
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
.
FEC_CRS, FEC_COL
M9
Figure 45. MII Async Inputs Timing Diagram
4.7.4.4
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 73 lists MII serial management channel timings. Figure 46 shows MII serial management channel
timings listed in Table 73. The MDC frequency should be equal to or less than 2.5 MHz to be compliant
with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC
frequency of 15 MHz.
Table 73. MII Transmit Signal Timing
ID
Characteristic
Min Max
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
0
—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
—
5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
—
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
—
ns
M14
FEC_MDC pulse width high
40% 60% FEC_MDC period
M15
FEC_MDC pulse width low
40% 60% FEC_MDC period
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M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 46. MII Serial Management Channel Timing Diagram
4.7.5
Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)
The FPM is a DPLL that converts a signal operating in the kilohertz region into a clock signal operating
in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs.
Parameters of the FPM are listed in Table 74.
Table 74. FPM Specifications
Parameter
Min
Typ
Max
Unit
Reference clock frequency range—CKIL
32
32.768
256
kHz
FPM output clock frequency range
8
—
33
MHz
128
—
1024
—
—
—
312.5
µs
—
8
20
ns
FPM multiplication factor (test condition is changed by a factor of 2)
Lock-in
time1
Cycle-to-cycle frequency jitter (peak to peak)
1
plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9};
y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. In this case reference clock = 32 kHz which makes
ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5 µs.
4.7.6
High-Speed I2C (HS-I2C) Timing Parameters
This section describes the timing parameters of the HS-I2C module. This module can operate in the
following modes: Standard, Fast and High speed.
NOTE
the HS-I2C module in the i.MX51 Chip Errata. There are
See the errata for
two standard I2C modules that have no errata.
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Electrical Characteristics
4.7.6.1
Standard and Fast Mode Timing Parameters
Figure 47 depicts the standard and fast mode timings of HS-I2C module, and Table 75 lists the timing
characteristics.
SCLH
IC11
IC10
SDAH
IC2
IC10
START
IC7
IC4
IC8
IC9
IC11
IC6
IC3
STOP
START
START
IC5
IC1
Figure 47. HS-I2C Standard and Fast Mode Bus Timing
Table 75. HS-I2C Timing Parameters—Standard and Fast Mode
Standard Mode
ID
Fast Mode
Parameter
Unit
Min
Max
Min
Max
IC1
SCLH cycle time
10
—
2.5
—
µs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
µs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
µs
IC4
Data hold time
01
3.452
01
0.92
µs
IC5
HIGH Period of SCLH Clock
4.0
—
0.6
—
µs
IC6
LOW Period of the SCLH Clock
4.7
—
1.3
—
µs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
µs
IC8
Data set-up time
250
—
1003
—
ns
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
µs
IC10
Rise time of both SDAH and SCLH signals
—
1000
20+0.1Cb4
300
ns
4
300
ns
100
pF
IC11
Fall time of both SDAH and SCLH signals
—
300
20+0.1Cb
IC12
Capacitive load for each bus line (C b)
—
100
—
1
A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the
falling edge of SCLH.
2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC6) of the SCLH signal
3 A Fast-mode I2C-bus device can be used in a Standard-mode I 2C-bus system, but the requirement of Set-up time (ID No IC8)
of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal.
If such a device does stretch the LOW period of the SCLH signal, it must output the next data bit to the SDAH line max_rise_time
(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the SCLH line is released.
4 C = total capacitance of one bus line in pF.
b
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4.7.6.2
High-Speed Mode Timing Parameters
Figure 48 depicts the high-speed mode timings of HS-I2C module, and Table 76 lists the timing
characteristics.
SCLH
IC12
IC11
SDAH
IC3
IC9
START
IC2
IC7
IC6
IC13
IC10
IC4
IC5
START
STOP
START
IC8
IC1
Figure 48. High-Speed Mode Timing
Table 76. HS-I2C High-Speed Mode Timing Parameters
High-Speed Mode
ID
1
Parameter
Unit
Min
Max
IC1
SCLH cycle time
10
3.4
MHz
IC2
Setup time (repeated) START condition
160
—
ns
IC3
Hold time (repeated) START condition
160
—
ns
IC4
LOW Period of the SCLH Clock
160
—
ns
IC5
HIGH Period of SCLH Clock
60
—
ns
IC6
Data set-up time
10
—
ns
IC7
Data hold time
01
70
ns
IC8
Rise time of SCLH
10
40
ns
IC9
Rise time of SCLH signal after a repeated START condition and after an acknowledge bit
10
80
ns
IC10
Fall time of SCLH signal
10
40
ns
IC11
Rise time of SDAH signal
10
80
ns
IC12
Fall time of SDAH signal
10
80
ns
IC13
Set-up time for STOP condition
160
—
ns
IC14
Capacitive load for each bus line (C b)
—
100
pF
A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the
falling edge of SCLH.
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Electrical Characteristics
4.7.7
I2C Module Timing Parameters
This section describes the timing parameters of the I2C Module. Figure 49 depicts the timing of I2C
module, and Table 77 lists the I2C Module timing characteristics.
I2CLK
IC11
IC10
I2DAT
IC2
IC10
START
IC7
IC4
IC8
IC11
IC6
IC9
IC3
STOP
START
START
IC5
IC1
Figure 49. I2C Bus Timing
Table 77. I2C Module Timing Parameters
ID
Parameter
Fast Mode
Standard Mode
Supply Voltage =
Supply Voltage =
2.7 V–3.3 V
Unit
1.65 V–1.95 V, 2.7 V–3.3 V
Min
Max
Min
Max
IC1
I2CLK cycle time
10
—
2.5
—
µs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
µs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
µs
IC4
Data hold time
01
3.45
01
0.92
µs
IC5
HIGH Period of I2CLK Clock
4.0
—
0.6
—
µs
IC6
LOW Period of the I2CLK Clock
4.7
—
1.3
—
µs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
µs
—
ns
2
IC8
Data set-up time
250
—
1003
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
µs
0.1Cb4
300
ns
IC10
Rise time of both I2DAT and I2CLK signals
—
1000
20 +
IC11
Fall time of both I2DAT and I2CLK signals
—
300
20 + 0.1Cb4
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
1
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
4
Cb = total capacitance of one bus line in pF.
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4.7.8
Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
• Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.
• Related image processing and manipulation: display processing, image conversions, and other
related functions.
• Synchronization and control capabilities such as avoidance of tearing artifacts.
4.7.8.1
Sensor Interface Timings
There are three camera timing modes supported by the IPU.
4.7.8.1.1
BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing
syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data
stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking
is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one
component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are
received over the SENSB_DATA bus.
4.7.8.1.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 50.
Active Line
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[19:0]
invalid
invalid
1st byte
1st byte
Figure 50. Gated Clock Mode Timing Diagram
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Electrical Characteristics
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid
as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.7.8.1.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.7.8.1.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 51. All incoming pixel clocks are
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[19:0]
invalid
invalid
1st byte
1st byte
Figure 51. Non-Gated Clock Mode Timing Diagram
The timing described in Figure 51 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.8.2
Electrical Characteristics
Figure 52 shows the sensor interface timing diagram. SENSB_PIX_CLK signal described here is not
generated by the IPU. Table 78 shows the timing characteristics for the diagram shown in Figure 52.
SENSB_PIX_CLK
(Sensor Output)
IP3
IP2
1/IP1
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
Figure 52. Sensor Interface Timing Diagram
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Electrical Characteristics
Table 78. Sensor Interface Timing Characteristics
ID
Parameter
Symbol
Min
Max
Unit
IP1
Sensor output (pixel) clock frequency
Fpck
0.01
120
IP2
Data and control setup time
Tsu
3
—
ns
IP3
Data and control holdup time
Thd
2
—
ns
4.7.8.3
MHz
IPU Display Interface Signal Mapping
The IPU supports a number of display output video formats. Table 79 defines the mapping of the Display
Interface Pins used during various supported video interface formats.
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Electrical Characteristics
Table 79. Video Signal Cross-Reference
i.MX51A
Port Name
(x=1,2)
LCD
RGB/TV Signal Allocation (Example)
RGB,
Signal
Name
16-bit 18-bit 24-bit
8-bit
16-bit 20-bit
(General) RGB RGB RGB YCrCb2 YCrCb YCrCb
Comment1
Smart
Signal
Name
DISPx_DAT0
DAT[0]
B[0]
B[0]
B[0]
Y/C[0]
C[0]
C[0]
DAT[0]
DISPx_DAT1
DAT[1]
B[1]
B[1]
B[1]
Y/C[1]
C[1]
C[1]
DAT[1]
DISPx_DAT2
DAT[2]
B[2]
B[2]
B[2]
Y/C[2]
C[2]
C[2]
DAT[2]
The restrictions are as follows:
a) There are maximal three
continuous groups of bits that
could be independently mapped to
the external bus.
DISPx_DAT3
DAT[3]
B[3]
B[3]
B[3]
Y/C[3]
C[3]
C[3]
DAT[3]
Groups should not be overlapped.
DISPx_DAT4
DAT[4]
B[4]
B[4]
B[4]
Y/C[4]
C[4]
C[4]
DAT[4]
DISPx_DAT5
DAT[5]
G[0]
B[5]
B[5]
Y/C[5]
C[5]
C[5]
DAT[5]
b) The bit order is expressed in
each of the bit groups, for example
B[0] = least significant blue pixel
bit
DISPx_DAT6
DAT[6]
G[1]
G[0]
B[6]
Y/C[6]
C[6]
C[6]
DAT[6]
DISPx_DAT7
DAT[7]
G[2]
G[1]
B[7]
Y/C[7]
C[7]
C[7]
DAT[7]
DISPx_DAT8
DAT[8]
G[3]
G[2]
G[0]
—
Y[0]
C[8]
DAT[8]
DISPx_DAT9
DAT[9]
G[4]
G[3]
G[1]
—
Y[1]
C[9]
DAT[9]
DISPx_DAT10
DAT[10]
G[5]
G[4]
G[2]
—
Y[2]
Y[0]
DAT[10]
DISPx_DAT11
DAT[11]
R[0]
G[5]
G[3]
—
Y[3]
Y[1]
DAT[11]
DISPx_DAT12
DAT[12]
R[1]
R[0]
G[4]
—
Y[4]
Y[2]
DAT[12]
DISPx_DAT13
DAT[13]
R[2]
R[1]
G[5]
—
Y[5]
Y[3]
DAT[13]
DISPx_DAT14
DAT[14]
R[3]
R[2]
G[6]
—
Y[6]
Y[4]
DAT[14]
DISPx_DAT15
DAT[15]
R[4]
R[3]
G[7]
—
Y[7]
Y[5]
DAT[15]
DISPx_DAT16
DAT[16]
—
R[4]
R[0]
—
—
Y[6]
—
DISPx_DAT17
DAT[17]
—
R[5]
R[1]
—
—
Y[7]
—
DISPx_DAT18
DAT[18]
—
—
R[2]
—
—
Y[8]
—
DISPx_DAT19
DAT[19]
—
—
R[3]
—
—
Y[9]
—
DISPx_DAT20
DAT[20]
—
—
R[4]
—
—
—
—
DISPx_DAT21
DAT[21]
—
—
R[5]
—
—
—
—
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Table 79. Video Signal Cross-Reference (continued)
i.MX51A
Port Name
(x=1,2)
LCD
RGB/TV Signal Allocation (Example)
RGB,
Signal
Name
16-bit 18-bit 24-bit
8-bit
16-bit 20-bit
(General) RGB RGB RGB YCrCb2 YCrCb YCrCb
Comment1
Smart
Signal
Name
DISPx_DAT22
DAT[22]
—
—
R[6]
—
—
—
—
—
DISPx_DAT23
DAT[23]
—
—
R[7]
—
—
—
—
—
—
—
DIx_DISP_CLK
PixCLK
DIx_PIN1
—
DIx_PIN2
HSYNC
—
—
DIx_PIN3
VSYNC
—
VSYNC out
DIx_PIN4
—
—
DIx_PIN5
—
—
Additional frame/row synchronous
signals with programmable timing
DIx_PIN6
—
—
DIx_PIN7
—
—
DIx_PIN8
—
—
DIx_D0_CS
—
CS0
—
DIx_D1_CS
—
CS1
Alternate mode of PWM output for
contrast or brightness control
DIx_PIN11
—
WR
—
DIx_PIN12
—
RD
—
DIx_PIN13
—
RS1
Register select signal
DIx_PIN14
—
RS2
Optional RS2
DIx_PIN15
DRDY/DV
DRDY
DIx_PIN16
—
—
DIx_PIN17
Q
—
1
2
VSYNC_IN May be required for anti-tearing
Data validation/blank, data enable
Additional data synchronous
signals with programmable
features/timing
Signal mapping (both data and control/synchronization) is flexible. The table provides examples.
This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line
start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data
during blanking intervals is not supported.
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4.7.8.4
IPU Display Interface Timing
The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.
4.7.8.4.1
Synchronous Controls
The synchronous control is a signal that changes its value as a function either of a system or of an external
clock. This control has a permanent period and a permanent wave form.
There are special physical outputs to provide synchronous controls:
• The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
• The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN and so on)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the
i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).
4.7.8.4.2
Asynchronous Controls
The asynchronous control is a data oriented signal that changes its a value with an output data according
to an additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
• The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays
• The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any else data oriented signal to display.
NOTE
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data in the bus, a
new internal start (local start point) is generated. The signals generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
4.7.8.5
4.7.8.5.1
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface:
• IPP_DISP_CLK—Clock to display
• HSYNC—Horizontal synchronization
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•
•
VSYNC—Vertical synchronization
DRDY—Active data
All synchronous display controls are generated on base of an internal generated “local start point”. The
synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The
display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative
to the local start point.
4.7.8.5.2
LCD Interface Functional Description
Figure 53 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
• DI_CLK internal DI clock, used for calculation of other controls.
• IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
• HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC)
• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC)
• DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(For DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
HSYNC
DRDY
1
2
3
m-1
m
IPP_DISP_CLK
IPP_DATA
Figure 53. Interface Timing Diagram for TFT (Active Matrix) Panels
4.7.8.5.3
TFT Panel Sync Pulse Timing Diagrams
Figure 54 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All shown on the figure parameters are programmable. All controls are started by corresponding
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internal events—local start points. The timing diagrams correspond to inverse polarity of the
IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC and DRDY signals.
IP13o
IP7
IP5o
IP8o
IP8
IP5
DI clock
IPP_DISP_CLK
VSYNC
HSYNC
DRDY
IPP_DATA
D0
local start point
local start point
Dn
IP9o
IP9
local start point
D1
IP10
IP6
Figure 54. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 55 depicts the vertical timing (timing of one frame). All parameters shown in the figure are
programmable.
Start of frame
IP13
End of frame
VSYNC
HSYNC
DRDY
IP11
IP15
IP14
IP12
Figure 55. TFT Panels Timing Diagram—Vertical Sync Pulse
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Table 80 shows timing characteristics of signals presented in Figure 54 and Figure 55.
Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level)
ID
Parameter
Symbol
Value
IP5
Display interface clock period
Tdicp
(1)
IP6
Display pixel clock period
Tdpcp
IP7
Screen width time
Tsw
(SCREEN_WIDTH)
× Tdicp
IP8
HSYNC width time
Thsw
(HSYNC_WIDTH)
IP9
Horizontal blank interval 1
Thbi1
BGXP × Tdicp
IP10
Horizontal blank interval 2
Thbi2
IP12
Screen height
IP13
Description
Display interface clock. IPP_DISP_CLK
DISP_CLK_PER_PIXEL Time of translation of one pixel to display,
× Tdicp
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
Unit
ns
ns
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter2.
ns
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
ns
BGXP—Width of a horizontal blanking
before a first active data in a line. (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
ns
(SCREEN_WIDTH BGXP - FW) × Tdicp
Width a horizontal blanking after a last
active data in a line. (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
ns
Tsh
(SCREEN_HEIGHT)
× Tsw
SCREEN_HEIGHT— screen height in lines
with blanking
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
ns
VSYNC width
Tvsw
VSYNC_WIDTH
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP × Tsw
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
ns
IP15
Vertical blank interval 2
Tvbi2
width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
ns
(SCREEN_HEIGHT BGYP - FH) × Tsw
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Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
ID
Symbol
Value
Todicp
DISP_CLK_OFFSET
× Tdiclk
IP13o Offset of VSYNC
Tovs
IP8o
Offset of HSYNC
IP9o
Offset of DRDY
IP5o
1
Parameter
Offset of IPP_DISP_CLK
Description
Unit
DISP_CLK_OFFSET— offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK×2
(0.5 DI_CLK Resolution)
Defined by DISP_CLK counter
ns
VSYNC_OFFSET
× Tdiclk
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
VSYNC_OFFSET should be built by
suitable DI’s counter.
ns
Tohs
HSYNC_OFFSET
× Tdiclk
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
HSYNC_OFFSET should be built by
suitable DI’s counter.
ns
Todrdy
DRDY_OFFSET
× Tdiclk
DRDY_OFFSET— offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK×2
(0.5 DI_CLK Resolution)
The DRDY_OFFSET should be built by
suitable DI’s counter.
ns
Display interface clock period immediate value.
⎧
DISP_CLK_PERIOD
⎪ T diclk × ------------------------------------------------------- ,
DI_CLK_PERIOD
⎪
Tdicp = ⎨
⎪T
⎛ floor DISP_CLK_PERIOD
------------------------------------------------------- + 0.5 ± 0.5⎞ ,
⎪ diclk ⎝
⎠
DI_CLK_PERIOD
⎩
DISP_CLK_PERIOD
for integer ------------------------------------------------------DI_CLK_PERIOD
DISP_CLK_PERIOD
for fractional ------------------------------------------------------DI_CLK_PERIOD
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
DISP_CLK_PERIOD
Tdicp = T diclk × ------------------------------------------------------DI_CLK_PERIOD
2
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
The maximal accuracy of UP/DOWN edge of controls is
Accuracy = ( 0.5 × T diclk ) ± 0.75ns
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The maximal accuracy of UP/DOWN edge of IPP_DATA is
Accuracy = T
diclk
± 0.75ns
The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed via registers.
Figure 56 shows the synchronous display interface timing diagram for access level. The
DISP_CLK_DOWN and DISP_CLK_UP parameters are set by using the register. Table 81 shows the
timing characteristics for the diagram shown in Figure 56.
IP20o IP20
VSYNC
HSYNC
DRDY
other controls
IPP_DISP_CLK
Tdicu
Tdicd
IPP_DATA
IP16
IP17
IP19
IP18
local start point
Figure 56. Synchronous Display Interface Timing Diagram—Access Level
Table 81. Synchronous Display Interface Timing Characteristics (Access Level)
ID
Parameter
Symbol
Typ1
Min
Max
Unit
IP16
Display interface clock
low time
Tckl
Tdicd-Tdicu–1.5
Tdicd2–Tdicu3
Tdicd–Tdicu+1.5
ns
IP17
Display interface clock
high time
Tckh
Tdicp–Tdicd+Tdicu–1.5
Tdicp–Tdicd+Tdicu
Tdicp–Tdicd+Tdicu+1.5
ns
IP18
Data setup time
Tdsu
Tdicd–1.5
Tdicu
—
ns
IP19
Data holdup time
Tdhd
Tdicp–Tdicd–1.5
Tdicp–Tdicu
—
ns
IP20o
Control signals offset
times (defines for each
pin)
Tocsu
Tocsu–1.5
Tocsu
IP20
Tcsu
Control signals setup
time to display interface
clock (defines for each
pin)
Tocsu+1.5
Tdicd–1.5–Tocsu%Tdicp Tdicu
—
—
ns
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
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2
Display interface clock down time
2 × DISP_CLK_DOWN
1
Tdicd = --- ⎛ T diclk × ceil ------------------------------------------------------------- ⎞
⎠
DI_CLK_PERIOD
2⎝
3
Display interface clock up time
2 × DISP_CLK_UP
1
Tdicu = --- ⎛ T diclk × ceil --------------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
4.7.8.6
Interface to a TV Encoder
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in Figure 57.
•
•
•
•
•
NOTE
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles
— At a transition to an odd field (of the next frame), the negative edges
of VSYNC and HSYNC coincide.
At a transition is to an even field (of the same frame), they do not
coincide.
—
•
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
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DISP_CLK
HSYNC
VSYNC
DRDY
Cb
IPP_DATA
Y
Cr
Y
Cb
Y
Cr
Pixel Data Timing
HSYNC
523
524
525
1
2
3
5
4
6
10
DRDY
VSYNC
Even Field
HSYNC
261
262
263
Odd Field
264
265
266
267
268
269
273
DRDY
VSYNC
Even Field
Odd Field
Line and Field Timing - NTSC
HSYNC
621
622
623
624
625
1
3
2
4
23
DRDY
VSYNC
Even Field
HSYNC
308
309
Odd Field
310
311
312
313
314
315
316
336
DRDY
VSYNC
Even Field
Odd Field
Line and Field Timing - PAL
Figure 57. TV Encoder Interface Timing Diagram
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4.7.8.6.1
TV Encoder Performance Specifications
All the parameters in the table are defined under the following conditions:
Rset = 1.05 kΩ ±1%, resistor on VREFOUT pin to Ground
Rload = 37.5 Ω ±1%, output load to Ground
The TV encoder output specifications are shown in Table 82.
Table 82. TV Encoder Video Performance Specifications
Parameter
Conditions
Min
Typ
Max
Unit
DAC STATIC PERFORMANCE
Resolution1
—
—
10
—
Bits
Integral Nonlinearity (INL)2
—
—
1
2
LSBs
Differential Nonlinearity (DNL)2
—
—
0.6
1
LSBs
Channel-to-channel gain matching2
—
—
2
—
%
Full scale output voltage2
Rset = 1.05 kΩ ±1%
Rload = 37.5 Ω±1%
1.24
1.35
1.45
V
DAC DYNAMIC PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Fout = 3.38 MHz
Fsamp = 216 MHz
—
59
—
dBc
Spurious Free Dynamic Range (SFDR)
Fout = 9.28 MHz
Fsamp = 297 MHz
—
54
—
dBc
VIDEO PERFORMANCE IN SD MODE2, 3
Short Term Jitter (Line to Line)
—
—
2.5
—
±ns
Long Term Jitter (Field to Field)
—
—
3.5
—
±ns
0-4.0 MHz
–0.1
—
0.1
dB
5.75 MHz
–0.7
—
0
dB
Luminance Nonlinearity
—
—
0.5
—
±%
Differential Gain
—
—
0.35
—
%
Differential Phase
—
—
0.6
—
Degrees
Flat field full bandwidth
—
75
—
dB
Hue Accuracy
—
—
0.8
—
±Degrees
Color Saturation Accuracy
—
—
1.5
—
±%
Chroma AM Noise
—
—
–70
—
dB
Chroma PM Noise
—
—
–47
—
dB
Chroma Nonlinear Phase
—
—
0.5
—
±Degrees
Chroma Nonlinear Gain
—
—
2.5
—
±%
Chroma/Luma Intermodulation
—
—
0.1
—
±%
Frequency Response
Signal-to-Noise Ratio (SNR)
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Table 82. TV Encoder Video Performance Specifications (continued)
Chroma/Luma Gain Inequality
—
—
1.0
—
±%
Chroma/Luma Delay Inequality
—
—
1.0
—
±ns
—
—
—
—
—
0-30 MHz
–0.2
—
0.2
dB
0-15 MHz,
YCbCr 422 mode
–0.2
—
0.2
dB
Luma Nonlinearity
—
—
3.2
—
%
Chroma Nonlinearity
—
—
3.4
—
%
Luma Signal-to-Noise Ratio
0-30 MHz
—
62
—
dB
Chroma Signal-to-Noise Ratio
0-15 MHz
—
72
—
dB
VIDEO PERFORMANCE IN HD MODE2
Luma Frequency Response
Chroma Frequency Response
1
Guaranteed by design
Guaranteed by characterization
3 R
set = VREFOUT's external resistor to ground = 1.05 kΩ
2
4.7.8.7
4.7.8.7.1
Asynchronous Interfaces
Standard Parallel Interfaces
The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s
internal control levels (0 or 1) by UP and DOWN are defined in Registers. Each asynchronous pin has a
dynamic connection with one of the signal generators. This connection is redefined again with a new
display access (pixel/component) The IPU can generate control signals according to system 80/68
requirements. The burst length is received as a result from predefined behavior of the internal signal
generator machines.
The access to a display is realized by the following:
• CS (IPP_CS) chip select
• WR (IPP_PIN_11) write strobe
• RD (IPP_PIN_12) read strobe
• RS (IPP_PIN_13) Register select (A0)
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 58,
Figure 59, Figure 60, and Figure 61. The timing images correspond to active-low IPP_CS, WR and RD
signals.
Each asynchronous access is defined by an access size parameter. This parameter can be different between
different kinds of accesses. This parameter defines a length of windows, when suitable controls of the
current access are valid. A pause between two different display accesses can be guaranteed by programing
of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control
signal can be switched at any time during access size.
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IPP_CS
RS
WR
RD
IPP_DATA
Burst access mode with sampling by CS signal
IPP_CS
RS
WR
RD
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
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IPP_CS
RS
WR
RD
IPP_DATA
Burst access mode with sampling by WR/RD signals
IPP_CS
RS
WR
RD
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
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IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Burst access mode with sampling by CS signal
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
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IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Burst access mode with sampling by ENABLE signal
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 61. Asynchronous Parallel System 68k Interface (Type 2) TIming Diagram
Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT
signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until
IPP_WAIT release.
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Figure 62 shows timing of the parallel interface with IPP_WAIT control.
DI clock
IPP_CS
IPP_DATA
WR
RD
IPP_WAIT
IPP_DATA_IN
IP39
waiting
waiting
Figure 62. Parallel Interface Timing Diagram—Read Wait States
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4.7.8.7.2
Asynchronous Parallel Interface Timing Parameters
Figure 63 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k
interfaces. Table 84 shows the timing characteristics at display access level. Table 83 shows the timing
characteristics at the logical level—from configuration perspective. All timing diagrams are based on
active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).
IP29
IP32
IP35
IP36
IP33
IP30
IP47
IP34
IP31
DI clock
IPP_CS
RS
WR
RD
IPP_DATA
A0
D0
D1
D2
PP_DATA_IN
IP27
IP37
IP38
local start point
local start point
local start point
IP28d
local start point
local start point
IP28a
D3
Figure 63. Asynchronous Parallel Interface Timing Diagram
Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level)
ID
Parameter
Symbol
Tcycr
Value
Description
Unit
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP27
Read system cycle time
IP28a
Address Write system cycle time Tcycwa
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP28d
Data Write system cycle time
Tcycwd
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP29
RS start
Tdcsrr
UP#
RS strobe switch, predefined value
in DI REGISTER
ns
IP30
CS start
Tdcsc
UP#
CS strobe switch, predefined value
in DI REGISTER
ns
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Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)
ID
Parameter
Symbol
Value
Description
Unit
IP31
CS hold
Tdchc
DOWN#
CS strobe release, predefined
value in DI REGISTER
—
IP32
RS hold
Tdchrr
DOWN#
RS strobe release, predefined
value in DI REGISTER
—
IP33
Read start
Tdcsr
UP#
read strobe switch, predefined
value in DI REGISTER
ns
IP34
Read hold
Tdchr
DOWN#
read strobe release signal,
predefined value in DI REGISTER
ns
IP35
Write start
Tdcsw
UP#
write strobe switch, predefined
value in DI REGISTER
ns
IP36
Controls hold time for write
Tdchw
DOWN#
write strobe release, predefined
value in DI REGISTER
ns
IP37
Slave device data delay1
Tracc
Delay of incoming data
Physical delay of display’s data,
defined from Read access local
start point
ns
IP38
Slave device data hold time3
Troh
IP47
Read time point13
Tdrp
1This
Hold time of data on the buss Time that display read data is valid
in input bus
Data sampling point
Point of input data sampling by DI,
predefined in DC Microcode
ns
—
parameter is a requirement to the display connected to the IPU.
Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level)
ID
Parameter
Symbol
IP27 Read system cycle time
Tcycr
Typ1
Min
Max
Unit
Tdicpr–1.5
Tdicpr2
Tdicpr+1.5
ns
Tdicpw+1.5
ns
IP28 Write system cycle time
Tcycw
Tdicpw–1.5
Tdicpw 3
IP29 RS start
Tdcsrr
Tdicurs–1.5
Tdicurs
Tdicurs+1.5
ns
IP30 CS start
Tdcsc
Tdicucs–1.5
Tdicur
Tdicucs+1.5
ns
IP31 CS hold
Tdchc
TdicdcsTdicucs–1.5
Tdicdcs4–Tdicucs5
Tdicdcs–Tdicucs+1.5
ns
Tdicdrs–Tdicurs+1.5
ns
Tdicur+1.5
ns
Tdicdr–Tdicur+1.5
ns
Tdicuw+1.5
ns
Tdicdw–Tdicuw+1.5
ns
IP32 RS hold
Tdchrr
Tdicdrs–Tdicurs–1.5
Tdicdrs6–Tdicurs7
IP33 Controls setup time for read
Tdcsr
Tdicur–1.5
Tdicur
Tdicdr–Tdicur–1.5
Tdicdr8
Tdicuw–1.5
Tdicuw
Tdicdw–Tdicuw–1.5
Tdicpw 10
IP34 Controls hold time for read
Tdchr
IP35 Controls setup time for write Tdcsw
–Tdicur
9
11
IP36 Controls hold time for write
Tdchw
IP37 Slave device data delay12
Tracc
0
—
Tdrp13–Tlbd14–Tdicur–1.5
ns
Troh
Tdrp–Tlbd–Tdicdr+1.5
—
Tdicpr–Tdicdr–1.5
ns
IP38 Slave device data hold
time8
–Tdicuw
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Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued)
ID
Parameter
Symbol
IP39 Setup time for wait signal
Tswait
IP47 Read time point13
Tdrp
Min
Typ1
Max
Unit
—
—
—
—
Tdrp–1.5
Tdrp
Tdrp+1.5
ns
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
2
Display period value for read
Tdicpr = T
DI_CLK
DI_ACCESS_SIZE_#
× ceil --------------------------------------------------------DI_CLK_PERIOD
ACCESS_SIZE is predefined in REGISTER
3
Display period value for write
DI_ACCESS_SIZE_#
Tdicpw = T DI_CLK × ceil --------------------------------------------------------DI_CLK_PERIOD
ACCESS_SIZE is predefined in REGISTER
4Display control down for CS
2 × DISP_DOWN_#
1
Tdicdcs = --- ⎛ T
× ceil ----------------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2 ⎝ DI_CLK
DISP_DOWN is predefined in REGISTER
5Display control up for CS
2 × DISP_UP_#
1
Tdicucs = --- ⎛ T DI_CLK × ceil ----------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_UP is predefined in REGISTER
6Display control down for RS
2 × DISP_DOWN_#
1
Tdicdrs = --- ⎛ T DI_CLK × ceil ----------------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_DOWN is predefined in REGISTER
7Display control up for RS
2 × DISP_UP_#
1
Tdicurs = --- ⎛ T
× ceil ----------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2 ⎝ DI_CLK
DISP_UP is predefined in REGISTER
8Display control down for read
2 × DISP_DOWN_#
1
Tdicdr = --- ⎛ T DI_CLK × ceil ----------------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_DOWN is predefined in REGISTER
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9
Display control up for read
2 × DISP_UP_#
1
Tdicur = --- ⎛ T DI_CLK × ceil ----------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_UP is predefined in REGISTER
10
Display control down for read
2 × DISP_DOWN_#
1
Tdicdrw = --- ⎛ T
× ceil ----------------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2 ⎝ DI_CLK
DISP_DOWN is predefined in REGISTER
11
Display control up for write
2 × DISP_UP_#
1
Tdicuw = --- ⎛ T DI_CLK × ceil ----------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_UP is predefined in REGISTER
12This parameter is a requirement to the display connected to the IPU
13Data read point
Tdrp = T
DI_CLK
DISP#_READ_EN
× ceil -------------------------------------------------
DI_CLK_PERIOD
Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data
14Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
4.7.8.8
Standard Serial Interfaces
The IPU supports the following types of asynchronous serial interfaces:
1. 3-wire (with bidirectional data line).
2. 4-wire (with separate data input and output lines).
3. 5-wire type 1 (with sampling RS by the serial clock).
4. 5-wire type 2 (with sampling RS by the chip select signal).
The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire
interfaces.
Figure 64 depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to
active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal.
For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide
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joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D
signal provided by the IPU.
DISPB_D#_CS
programed
delay
programed
delay
DISPB_SD_D_CLK
DISPB_SD_D
RW
RS
D7
D6
D5
D4
D3
D2
D1
D0
Input or output data
Preamble
Figure 64. 3-Wire Serial Interface Timing Diagram
Figure 65 depicts timing diagram of the 4-wire serial interface. For this interface, there are separate input
and output data lines both inside and outside the chip.
Write
DISPB_D#_CS
programed
delay
programed
delay
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
D7
D6
D5
Preamble
D4
D3
D2
D1
D0
Output data
DISPB_SD_D
(Input)
Read
DISPB_D#_CS
programed
delay
programed
delay
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
Figure 65. 4-Wire Serial Interface Timing Diagram
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Figure 66 depicts timing of the 5-wire serial interface. For this interface, a separate RS line is added.
Write
DISPB_D#_CS
programed
delay
programed
delay
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
D4
D3
D2
D1
D0
Output data
Preamble
DISPB_SD_D
(Input)
DISPB_SER_RS
programed
delay
Read
DISPB_D#_CS
programed
delay
programed
delay
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
DISPB_SER_RS
D7
programed
delay
D6
D5
D4
D3
D2
D1
D0
Input data
Figure 66. 5-Wire Serial Interface Timing Diagram
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4.7.8.8.1
Asynchronous Serial Interface Timing Parameters
Figure 67 depicts timing of the serial interface. Table 85 shows timing characteristics at display access
level.
IP73
IP72
DI clock
IPP_DISPB_DO_SD_D
IPP_DO_DISPB_SER_CS
IP71
IP70
IPP_DO_DISPB_SER_RS
IP68
IP58
IPP_IND_DISPB_SD_D
IP59
IP60,
IP64, IP66
IP69
IP50, IP52
IP55, IP57,
IP61
IP54, IP56,
IP65, IP67
local start point
IPP_DO_DISPB_SD_D_CLK
IP51,53
IP48, IP49, IP62, IP63
Figure 67. Asynchronous Serial Interface Timing Diagram
Table 85. Asynchronous Serial Interface Timing Characteristics (Access Level)
ID
Parameter
IP48 Read system cycle time
Symbol
Tcycr
Min
Typ1
Max
Unit
Tdicpr–1.5
Tdicpr2
Tdicpr+1.5
ns
Tdicpw+1.5
ns
Tdicdr–Tdicur+1.5
ns
Tdicpr–Tdicdr+Tdicur+
1.5
ns
IP49 Write system cycle time
Tcycw
Tdicpw–1.5
Tdicpw3
IP50 Read clock low pulse width
Trl
Tdicdr–Tdicur–1.5
Tdicdr4–Tdicur5
IP51 Read clock high pulse width
Trh
Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+
Tdicur
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Table 85. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued)
ID
Parameter
Symbol
Typ1
Min
Max
Unit
IP52 Write clock low pulse width
Twl
Tdicdw–Tdicuw–1.5
Tdicdw6–Tdicuw7 Tdicdw–Tdicuw+1.5
ns
IP53 Write clock high pulse width
Twh
Tdicpw–Tdicdw+
Tdicuw–1.5
Tdicpw–Tdicdw+ Tdicpw–Tdicdw+
Tdicuw
Tdicuw+1.5
ns
IP54 Controls setup time for read
Tdcsr
Tdicur–1.5
Tdicur
—
ns
IP55 Controls hold time for read
Tdchr
Tdicpr–Tdicdr–1.5
Tdicpr–Tdicdr
—
ns
IP56 Controls setup time for write Tdcsw
Tdicuw–1.5
Tdicuw
—
ns
IP57 Controls hold time for write
Tdicpw–Tdicdw–1.5
Tdicpw–Tdicdw
—
ns
10
IP58 Slave device data
delay8
Tdchw
0
—
Tdrp –Tlbd -Tdicur-1.5
ns
IP59 Slave device data hold time8 Troh
Tdrp-Tlbd-Tdicdr+1.5
—
Tdicpr-Tdicdr-1.5
ns
IP60 Write data setup time
Tds
Tdicdw-1.5
Tdicdw
—
ns
IP61 Write data hold time
Tdh
Tdicpw-Tdicdw-1.5
Tdicpw-Tdicdw
—
ns
Tdicpr
Tdicpr-1.5
Tdicpr
Tdicpr+1.5
ns
Tdicpw
Tdicpw-1.5
Tdicpw
Tdicpw+1.5
ns
Tdicdr
Tdicdr-1.5
Tdicdr
Tdicdr+1.5
ns
Tdicur
Tdicur-1.5
Tdicur
Tdicur+1.5
ns
Tdicdw
Tdicdw-1.5
Tdicdw
Tdicdw+1.5
ns
Tdicuw
Tdicuw-1.5
Tdicuw
Tdicuw+1.5
ns
Tdrp
Tdrp-1.5
Tdrp
Tdrp+1.5
ns
Toclk
Toclk-1.5
Toclk
Toclk+1.5
ns
Tdicurs
Tdicurs–1.5
Tdicurs
Tdicurs+1.5
ns
Tdicdrs
Tdicdrs -1.5
Tdicdrs
Tdicdrs+1.5
ns
Tdicucs Tdicucs –1.5
Tdicucs
Tdicucs+1.5
ns
Tdicdcs Tdicdcs –1.5
Tdicdcs
Tdicdcs+1.5
ns
IP62 Read
period2
IP63 Write period3
IP64 Read down
time4
IP65 Read up time5
IP66 Write down
time6
IP67 Write up time7
IP68 Read time
point9
IP69 Clock offset11
IP70 RS up
time12
IP71 RS down time13
IP72 CS up
time14
IP73 CS down time15
Tracc
9
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
2Display interface clock period value for read
DISP#_IF_CLK_PER_RD
Tdicpr = TDI_CLK × ceil -------------------------------------------------------------------DI_CLK_PERIOD
3Display
interface clock period value for write
DISP#_IF_CLK_PER_WR
Tdicpw = T DI_CLK × ceil ---------------------------------------------------------------------DI_CLK_PERIOD
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4
Display interface clock down time for read
2 × DISP_DOWN_#
1
Tdicdr = --- ⎛ T DI_CLK × ceil ----------------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
5
Display interface clock up time for read
2 × DISP_UP_#
1
Tdicur = --- ⎛ T DI_CLK × ceil ----------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
6
Display interface clock down time for write
2 × DISP_DOWN_#
1
Tdicdw = --- ⎛ T DI_CLK × ceil ----------------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
7
Display interface clock up time for write
2 × DISP_UP_#
1
Tdicuw = --- ⎛ T DI_CLK × ceil ----------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
8This
9Data
parameter is a requirement to the display connected to the IPU
read point
DISP_READ_EN
Tdrp = T DI_CLK × ceil ----------------------------------------------DI_CLK_PERIOD
DISP_RD_EN is predefined in REGISTER
10Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
11Display interface clock offset value
Toclk = T
DI_CLK
DISP_CLK_OFFSET
× ceil -------------------------------------------------------DI_CLK_PERIOD
CLK_OFFSET is predefined in REGISTER
12Display RS up time
DISP_RS_UP_#
Tdicurs = T DI_CLK × ceil ----------------------------------------------DI_CLK_PERIOD
DISP_RS_UP is predefined in REGISTER
13Display RS down time
DISP_RS_DOWN_#
Tdicdrs = T DI_CLK × ceil -----------------------------------------------------DI_CLK_PERIOD
DISP_RS_DOWN is predefined in REGISTER
14Display RS up time
DISP_CS_UP_#
Tdicucs = T DI_CLK × ceil ----------------------------------------------DI_CLK_PERIOD
DISP_CS_UP is predefined in REGISTER
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15
Display RS down time
DISP_CS_DOWN_#
Tdicdcs = ( T DI_CLK × ceil) -----------------------------------------------------DI_CLK_PERIOD
DISP_CS_DOWN is predefined in REGISTER.
4.7.9
1-Wire Timing Parameters
Figure 68 depicts the RPP timing and Table 86 lists the RPP timing parameters.
1-WIRE Tx
“Reset Pulse”
DS2502 Tx
“Presence Pulse”
OW2
One-Wire bus
(BATT_LINE)
OW3
OW1
OW4
Figure 68. Reset and Presence Pulses (RPP) Timing Diagram
Table 86. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Symbol
Min
Typ
Max
Unit
OW1
Reset Time Low
tRSTL
480
511
—
µs
OW2
Presence Detect High
tPDH
15
—
60
µs
OW3
Presence Detect Low
tPDL
60
—
240
µs
OW4
Reset Time High
tRSTH
480
512
—
µs
Figure 69 depicts Write 0 Sequence timing, and Table 87 lists the timing parameters.
OW6
One-Wire bus
(BATT_LINE)
OW5
Figure 69. Write 0 Sequence Timing Diagram
Table 87. WR0 Sequence Timing Parameters
ID
Parameter
OW5
Write 0 Low Time
OW6
Transmission Time Slot
Symbol
Min
Typ
Max
Unit
tWR0_low
60
100
120
µs
tSLOT
OW5
117
120
µs
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Figure 70 depicts Write 1 Sequence timing, Figure 71 depicts the Read Sequence timing, and Table 88
lists the timing parameters.
OW8
One-Wire bus
(BATT_LINE)
OW7
Figure 70. Write 1 Sequence Timing Diagram
OW8
One-Wire bus
(BATT_LINE)
OW7
OW9
Figure 71. Read Sequence Timing Diagram
Table 88. WR1 /RD Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Unit
OW7
Write /Read Low Time
tLOW1
1
5
15
µs
OW8
Transmission Time Slot
tSLOT
60
117
120
µs
OW9
Release Time
tRELEASE
15
—
45
µs
4.7.10
Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM.The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
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Figure 72 depicts the timing of the PWM, and Table 89 lists the PWM timing parameters.
1
2a
3b
System Clock
2b
3a
4b
4a
PWM Output
Figure 72. PWM Timing
Table 89. PWM Output Timing Parameter
Ref. No.
1
Parameter
Min
Max
Unit
0
ipg_clk
MHz
1
System CLK frequency1
2a
Clock high time
12.29
—
ns
2b
Clock low time
9.91
—
ns
3a
Clock fall time
—
0.5
ns
3b
Clock rise time
—
0.5
ns
4a
Output delay time
—
9.37
ns
4b
Output setup time
8.71
—
ns
CL of PWMO = 30 pF
4.7.11
P-ATA Timing Parameters
This section describes the timing parameters of the Parallel ATA module which are compliant with
ATA/ATAPI-5 specification.
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 66 Mbyte/s. Parallel ATA
module interface consist of a total of 29 pins, Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-5 specification and these requirements are configurable by the ATA module registers.
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Table 90 and Figure 73 define the AC characteristics of all the P-ATA interface signals on all data
transfer modes.
ATA Interface Signals
SI2
SI1
Figure 73. P-ATA Interface Signals Timing Diagram
Table 90. AC Characteristics of All Interface Signals
ID
1
Parameter
Symbol
Min
Max
Unit
SI1
Rising edge slew rate for any signal on ATA interface.1
Srise
—
1.25
V/ns
SI2
Falling edge slew rate for any signal on ATA interface (see note)
Sfall
—
1.25
V/ns
SI3
Host interface signal capacitance at the host connector
Chost
—
20
pF
SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15–40 pF where all signals have the same capacitive load value.
The user needs to use level shifters for 5.0 V compatibility on the ATA interface. The i.MX51 P-ATA
interface is 3.3 V compatible.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-4) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the i.MX51 P-ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
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Table 91 shows ATA timing parameters.
Table 91. P-ATA Timing Parameters
Name
T
ti_ds
ti_dh
Bus clock period (ipg_clk_ata)
Peripheral clock frequency
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
15 ns
10 ns
7 ns
5 ns
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
5.0 ns
tco
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
12.0 ns
tsu
Set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
Set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
Hold time ata_iordy to bus clock H to L
2.5 ns
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
7 ns
tskew2
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
Transceiver
tskew3
Max difference in buffer propagation delay for any of following signals ata_iordy,
ata_data (read)
Transceiver
Max buffer propagation delay
Transceiver
tbuf
1
Value/
Contributing Factor1
Description
tcable1
Cable propagation delay for ata_data
Cable
tcable2
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
ata_dmack
Cable
tskew4
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Cable
tskew5
Max difference in cable propagation delay between (ata_dior, ata_diow,
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Cable
tskew6
Max difference in cable propagation delay without accounting for ground bounce
Cable
Values provided where applicable.
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4.7.11.1
PIO Mode Read Timing
Figure 74 shows timing for PIO read and Table 92 lists the timing parameters for PIO read.
Figure 74. PIO Read Timing Diagram
Table 92. PIO Read Timing Parameters
ATA
Parameter
Parameter from Figure 74
Value
Controlling
Variable
t1
t1
t1 (min) = time_1 × T – (tskew1 + tskew2 + tskew5)
time_1
t2
t2r
t2 min) = time_2r × T – (tskew1 + tskew2 + tskew5)
time_2r
t9
t9
t9 (min) = time_9 × T – (tskew1 + tskew2 + tskew6)
time_3
t5
t5
t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
t6
t6
0
tA
tA
tA (min) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2×tbuf)
trd
trd1
t0
—
trd1 (max) = (–trd) + (tskew3 + tskew4)
trd1 (min) = (time_pio_rdx – 0.5)×T – (tsu + thi)
(time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4
t0 (min) = (time_1 + time_2 + time_9) × T
If not met, increase
time_2
—
time_ax
time_pio_rdx
time_1, time_2r, time_9
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Figure 75 shows timing for PIO write and Table 93 lists the timing parameters for PIO write.
Figure 75. Multi-word DMA (MDMA) Timing
Table 93. PIO Write Timing Parameters
ATA
Parameter
Parameter from Figure 75
Value
× T – (tskew1 + tskew2 + tskew5)
t2 (min) = time_2w × T – (tskew1 + tskew2 + tskew5)
t9 (min) = time_9 × T – (tskew1 + tskew2 + tskew6)
t3 (min) = (time_2w – time_on)× T – (tskew1 + tskew2 +tskew5)
t1 (min) = time_1
Controlling
Variable
t1
t1
t2
t2w
t9
t9
t3
—
t4
t4
tA
tA
t0
—
× T – tskew1
tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2×tbuf)
t0(min) = (time_1 + time_2 + time_9) × T
—
—
Avoid bus contention when switching buffer on by making ton long enough
—
—
—
Avoid bus contention when switching buffer off by making toff long enough
—
t4 (min) = time_4
time_1
time_2w
time_9
If not met, increase
time_2w
time_4
time_ax
time_1, time_2r,
time_9
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Figure 76 shows timing for MDMA read, Figure 77 shows timing for MDMA write, and Table 94 lists
the timing parameters for MDMA read and write.
Figure 76. MDMA Read Timing Diagram
Figure 77. MDMA Write Timing Diagram
Table 94. MDMA Read and Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 76,
Figure 77
tm, ti
tm
td
td, td1
tk
tk
t0
—
tg(read)
tgr
tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr.(min-drive) = td – te(drive)
tf(read)
tfr
tfr (min-drive) = 0
tg(write)
—
tg (min-write) = time_d × T – (tskew1 + tskew2 + tskew5)
tf(write)
—
tf (min-write) = time_k
tL
—
Value
× T – (tskew1 + tskew2 + tskew5)
td1.(min) = td (min) = time_d × T – (tskew1 + tskew2 + tskew6)
tk.(min) = time_k × T – (tskew1 + tskew2 + tskew6)
t0 (min) = (time_d + time_k) × T
tm (min) = ti (min) = time_m
× T – (tskew1 + tskew2 + tskew6)
tL (max) = (time_d + time_k–2)×T – (tsu + tco + 2×tbuf + 2×tcable2)
Controlling
Variable
time_m
time_d
time_k
time_d, time_k
time_d
—
time_d
time_k
time_d, time_k
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Table 94. MDMA Read and Write Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 76,
Figure 77
tn, tj
tkjn
tn= tj= tkjn = (max(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6)
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
4.7.11.2
Value
Controlling
Variable
time_jn
—
Ultra DMA (UDMA) Input Timing
Figure 78 shows timing when the UDMA in transfer starts, Figure 79 shows timing when the UDMA in
host terminates transfer, Figure 80 shows timing when the UDMA in device terminates transfer, and
Table 95 lists the timing parameters for UDMA in burst.
Figure 78. UDMA In Transfer Starts Timing Diagram
Figure 79. UDMA In Host Terminates Transfer Timing Diagram
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Figure 80. UDMA In Device Terminates Transfer Timing Diagram
Table 95. UDMA In Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 78,
Figure 79,
Figure 80
tack
tack
tack (min) = (time_ack × T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min) = (time_env × T) – (tskew1 + tskew2)
tenv (max) = (time_env × T) + (tskew1 + tskew2)
time_env
tds
tds1
tds – (tskew3) – ti_ds > 0
tdh
tdh1
tdh – (tskew3) – ti_dh > 0
tcyc
tc1
trp
trp
—
tx11
tmli
tmli1
tzah
tzah
tdzfs
tdzfs
tcvh
tcvh
—
ton
toff2
Description
(tcyc – tskew) > T
× T – (tskew1 + tskew2 + tskew6)
(time_rp × T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)
tmli1 (min) = (time_mlix + 0.4) × T
tzah (min) = (time_zah + 0.4) × T
tdzfs = (time_dzfs × T) – (tskew1 + tskew2)
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
ton = time_on × T – tskew1
toff = time_off × T – tskew1
trp (min) = time_rp
Controlling Variable
tskew3, ti_ds, ti_dh
should be low enough
T big enough
time_rp
time_rp
time_mlix
time_zah
time_dzfs
time_cvh
—
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2 Make ton and toff big enough to avoid bus contention.
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4.7.11.3
UDMA Output Timing
Figure 81 shows timing when the UDMA out transfer starts, Figure 82 shows timing when the UDMA out
host terminates transfer, Figure 83 shows timing when the UDMA out device terminates transfer, and
Table 96 lists the timing parameters for UDMA out burst.
Figure 81. UDMA Out Transfer Starts Timing Diagram
Figure 82. UDMA Out Host Terminates Transfer Timing Diagram
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Figure 83. UDMA Out Device Terminates Transfer Timing Diagram
Table 96. UDMA Out Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 81,
Figure 82,
Figure 83
tack
tack
tenv
tenv
tdvs
tdvs
tdvh
tdvh
tcyc
tcyc
t2cyc
—
trfs1
trfs
—
tdzfs
tss
tss
tmli
tdzfs_mli
tli
tli1
tli1 > 0
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
tcvh
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
Value
× T) – (tskew1 + tskew2)
tenv (min) = (time_env × T) – (tskew1 + tskew2)
tenv (max) = (time_env × T) + (tskew1 + tskew2)
tdvs = (time_dvs × T) – (tskew1 + tskew2)
tdvs = (time_dvh × T) – (tskew1 + tskew2)
tcyc = time_cyc × T – (tskew1 + tskew2)
t2cyc = time_cyc × 2 × T
trfs = 1.6 × T + tsui + tco + tbuf + tbuf
tdzfs = time_dzfs × T – (tskew1)
tss = time_ss × T – (tskew1 + tskew2)
tdzfs_mli =max (time_dzfs, time_mli) × T – (tskew1 + tskew2)
tack (min) = (time_ack
Controlling
Variable
time_ack
time_env
time_dvs
time_dvh
time_cyc
time_cyc
—
time_dzfs
time_ss
—
time_cvh
—
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4.7.12
SIM (Subscriber Identification Module) Timing
This section describes the electrical parameters of the SIM module. Each SIM module interface consists
of 12 signals (two separate ports each containing six signals). Typically a a port uses five signals.
The interface is designed to be used with synchronous SIM cards meaning the SIM module provides the
clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rxdata rate, however the
SIM module can work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard
UART data exchanges. All six signals (5 for bi-directional Tx/Rx) of the SIM module are asynchronous to
each other.
There are no required timing relationships between signals in normal mode. The SIM card is initiated by
the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no
defined requirements, the ISO-7816 defines reset and power-down sequences. (For detailed information,
see ISO-7816.)
Table 97 defines the general timing requirements for the SIM interface.
Table 97. SIM Timing Parameters, High Drive Strength
ID
Parameter
Symbol
Min
Max
Unit
SI1
SIM Clock Frequency (SIMx_CLKy)1,
Sfreq
0.01
25
MHz
SI2
SIM Clock Rise Time
(SIMx_CLKy)2
Srise
—
0.09×(1/Sfreq)
ns
SI3
SIM Clock Fall Time (SIMx_CLKy)3
Sfall
—
0.09×(1/Sfreq)
ns
SI4
SIM Input Transition Time
(SIMx_DATAy_RX_TX, SIMx_SIMPDy)
Strans
10
25
ns
SI5
SIM I/O Rise Time / Fall
Time(SIMx_DATAy_RX_TX)4
Tr/Tf
—
1
µs
SI6
SIM RST Rise Time / Fall Time(SIMx_RSTy)5
Tr/Tf
—
1
µs
1
50% duty cycle clock
With C = 50 pF
3 With C = 50 pF
4
With Cin = 30 pF, Cout = 30 pF
5
With Cin = 30 pF
2
1/SI1
SIMx_CLKy
SI3
SI2
Figure 84. SIM Clock Timing Diagram
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4.7.12.1
4.7.12.1.1
Reset Sequence
Cards with internal reset
The sequence of reset for this kind of SIM Cards is as follows (see Figure 85):
• After power up, the clock signal is enabled on SIMx_CLKy(time T0)
• After 200 clock cycles, RX must be high.
• The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles
after T0.
SIMx_SVENy
SIMx_CLKy
SIMx_DATAy_RX_TX
response
1
2
T0
400 clock cycles <
1
< 200 clock cycles
2
< 40000 clock cycles
Figure 85. Internal-Reset Card Reset Sequence
4.7.12.1.2
Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see Figure 86):
• After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
• After 200 clock cycles, SIMx_DATAy_RX_TX must be high.
• SIMx_RSTy must remain Low for at least 40000 clock cycles after T0 (no response is to be
received on RX during those 40000 clock cycles)
• SIMx_RSTy is set High (time T1)
• SIMx_RSTy must remain High for at least 40000 clock cycles after T1 and a response must be
received on SIMx_DATAy_RX_TX between 400 and 40000 clock cycles after T1.
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SIMx_SVENy
SIMx_RSTy
SIMx_CLKy
SIMx_DATAy_RX_TX
response
2
1
3
3
T0
T1
1
< 200 clock cycles
400 clock cycles <
2
< 40000 clock cycles
400000 clock cycles <
3
Figure 86. Active-Low-Reset Cards Reset Sequence
4.7.12.2
Power Down Sequence
Power down sequence for SIM interface is as follows:
• SIMx_SIMPDy port detects the removal of the SIM Card
• SIMx_RSTy goes Low
• SIMx_CLKy goes Low
• SIMx_DATAy_RX_TX goes Low
• SIMx_SVENy goes Low
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Each of these steps is done in one CKIL period (usually 32 kHz). Power-down can be started because of
a SIM Card removal detection or launched by the processor. Figure 87 and Table 98 shows the usual
timing requirements for this sequence, with Fckil = CKIL frequency value.
SI10
SIMx_SIMPDy
SIMx_RSTy
SI7
SIMx_CLKy
SI8
SIMx_DATAy_RX_TX
SI9
SIMx_SVENy
Figure 87. SmartCard Interface Power Down AC Timing
Table 98. Timing Requirements for Power Down Sequence
ID
Parameter
Symbol
Min
Max
Unit
SI7
SIM reset to SIM clock stop
Srst2clk
0.9×1/Fckil
1.1×1/Fckil
ns
SI8
SIM reset to SIM TX data low
Srst2dat
1.8×1/Fckil
2.2×1/Fckil
ns
SI9
SIM reset to SIM voltage enable low
Srst2ven
2.7×1/Fckil
3.3×1/Fckil
ns
SI10
SIM presence detect to SIM reset low
Spd2rst
0.9×1/Fckil
1.1×1/Fckil
ns
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4.7.13
SCAN JTAG Controller (SJC) Timing Parameters
Figure 88 depicts the SJC test clock input timing. Figure 89 depicts the SJC boundary scan timing.
Figure 91 depicts the TRST timing with respect to TCK. Figure 90 depicts the SJC test access port. Signal
parameters are listed in Table 99.
SJ1
SJ2
TCK
(Input)
SJ2
VM
VIH
VM
VIL
SJ3
SJ3
Figure 88. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 89. Boundary Scan (JTAG) Timing Diagram
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Electrical Characteristics
TCK
(Input)
VIH
VIL
SJ8
TDI
TMS
(Input)
SJ9
Input Data Valid
SJ10
TDO
(Output)
Output Data Valid
SJ11
TDO
(Output)
SJ10
TDO
(Output)
Output Data Valid
Figure 90. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 91. TRST Timing Diagram
Table 99. JTAG Timing
All Frequencies
Parameter1,2
ID
Unit
Min
Max
0.001
22
MHz
45
—
ns
22.5
—
ns
SJ0
TCK frequency of operation 1/(3•TDC)1
SJ1
TCK cycle time in crystal mode
SJ2
TCK clock pulse width measured at VM2
SJ3
TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
5
—
ns
SJ5
Boundary scan input data hold time
24
—
ns
SJ6
TCK low to output data valid
—
40
ns
SJ7
TCK low to output high impedance
—
40
ns
SJ8
TMS, TDI data set-up time
5
—
ns
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Table 99. JTAG Timing (continued)
All Frequencies
Parameter1,2
ID
Unit
Min
Max
SJ9
TMS, TDI data hold time
25
—
ns
SJ10
TCK low to TDO data valid
—
44
ns
SJ11
TCK low to TDO high impedance
—
44
ns
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
1
2
TDC = target frequency of SJC
VM = mid-point voltage
4.7.14
SPDIF Timing Parameters
Table 100 shows the timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF).
Table 100. SPDIF Timing
All Frequencies
Characteristics
Symbol
SPDIFOUT output (load = 50 pF)
• Skew
• Transition rising
• Transition falling
—
SPDIFOUT output (load = 30 pF)
• Skew
• Transition rising
• Transition falling
4.7.15
—
Unit
Min
Max
—
—
—
1.5
24.2
31.3
ns
—
—
—
1.5
13.6
18.0
ns
SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous
interfaces is summarized in Table 101.
Table 101. AUDMUX Port Allocation
Port
Signal Nomenclature
Type and Access
AUDMUX port 1
SSI 1
Internal
AUDMUX port 2
SSI 2
Internal
AUDMUX port 3
AUD3
External—AUD3 I/O
AUDMUX port 4
AUD4
External—EIM or CSPI1 I/O via IOMUX
AUDMUX port 5
AUD5
External—EIM or SD1 I/O via IOMUX
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Table 101. AUDMUX Port Allocation (continued)
Port
Signal Nomenclature
Type and Access
AUDMUX port 6
AUD6
External—EIM or DISP2 via IOMUX
AUDMUX port 7
SSI 3
Internal
•
•
4.7.15.1
NOTE
The terms WL and BL used in the timing diagrams and tables refer to
Word Length (WL) and Bit Length (BL).
The SSI timing diagrams use generic signal names wherein the names
used in the i.MX51 Multimedia Applications Processor Reference
Manual (MCIMX51RM) are channel specific signal names. For
example, a channel clock referenced in the IOMUXC chapter as
AUD3_TXC appears in the timing diagram as TXC.
SSI Transmitter Timing with Internal Clock
Figure 92 depicts the SSI transmitter internal clock timing and Table 102 lists the timing parameters for
the SSI transmitter internal clock.
.
SS1
SS5
SS2
SS3
SS4
TXC
(Output)
SS6
TXFS (bl)
(Output)
SS8
SS10
SS12
SS14
TXFS (wl)
(Output)
SS15
SS16
SS18
SS17
TXD
(Output)
SS43
SS42
SS19
RXD
(Input)
Note: SRXD input in synchronous mode only
Figure 92. SSI Transmitter Internal Clock Timing Diagram
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Table 102. SSI Transmitter Timing with Internal Clock
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6.0
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6.0
ns
SS6
(Tx) CK high to FS (bl) high
—
15.0
ns
SS8
(Tx) CK high to FS (bl) low
—
15.0
ns
SS10
(Tx) CK high to FS (wl) high
—
15.0
ns
SS12
(Tx) CK high to FS (wl) low
—
15.0
ns
SS14
(Tx/Rx) Internal FS rise time
—
6.0
ns
SS15
(Tx/Rx) Internal FS fall time
—
6.0
ns
SS16
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
SS17
(Tx) CK high to STXD high/low
—
15.0
ns
SS18
(Tx) CK high to STXD high impedance
—
15.0
ns
SS19
STXD rise/fall time
—
6.0
ns
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
30
—
ns
SS43
SRXD hold after (Tx) CK falling
0.0
—
ns
SS52
Loading
—
25.0
pF
•
•
•
•
•
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
”Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
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4.7.15.2
SSI Receiver Timing with Internal Clock
Figure 93 depicts the SSI receiver internal clock timing and Table 103 lists the timing parameters for the
SSI receiver internal clock.
SS1
SS3
SS5
SS4
SS2
TXC
(Output)
SS9
SS7
TXFS (bl)
(Output)
SS11
TXFS (wl)
(Output)
SS13
SS20
SS21
RXD
(Input)
SS47
SS48
SS51
SS49
SS50
RXC
(Output)
Figure 93. SSI Receiver Internal Clock Timing Diagram
Table 103. SSI Receiver Timing with Internal Clock
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6.0
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6.0
ns
SS7
(Rx) CK high to FS (bl) high
—
15.0
ns
SS9
(Rx) CK high to FS (bl) low
—
15.0
ns
SS11
(Rx) CK high to FS (wl) high
—
15.0
ns
SS13
(Rx) CK high to FS (wl) low
—
15.0
ns
SS20
SRXD setup time before (Rx) CK low
30
—
ns
SS21
SRXD hold time after (Rx) CK low
0.0
—
ns
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Table 103. SSI Receiver Timing with Internal Clock (continued)
ID
Parameter
Min
Max
Unit
15.04
—
ns
Oversampling Clock Operation
SS47
Oversampling clock period
SS48
Oversampling clock high period
6.0
—
ns
SS49
Oversampling clock rise time
—
3.0
ns
SS50
Oversampling clock low period
6.0
—
ns
SS51
Oversampling clock fall time
—
3.0
ns
•
•
•
•
•
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
4.7.15.3
SSI Transmitter Timing with External Clock
Figure 94 depicts the SSI transmitter external clock timing and Table 104 lists the timing parameters for
the SSI transmitter external clock.
SS22
SS23
SS25
SS26
SS24
TXC
(Input)
SS27
SS29
TXFS (bl)
(Input)
SS33
SS31
TXFS (wl)
(Input)
SS37
SS39
SS38
TXD
(Output)
SS45
SS44
RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
Figure 94. SSI Transmitter External Clock Timing Diagram
Table 104. SSI Transmitter Timing with External Clock
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
—
ns
SS23
(Tx/Rx) CK clock high period
36.0
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
36.0
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS27
(Tx) CK high to FS (bl) high
–10.0
15.0
ns
SS29
(Tx) CK high to FS (bl) low
10.0
—
ns
SS31
(Tx) CK high to FS (wl) high
–10.0
15.0
ns
SS33
(Tx) CK high to FS (wl) low
10.0
—
ns
SS37
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
SS38
(Tx) CK high to STXD high/low
—
30
ns
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Table 104. SSI Transmitter Timing with External Clock (continued)
ID
SS39
Parameter
(Tx) CK high to STXD high impedance
Min
Max
Unit
—
15.0
ns
Synchronous External Clock Operation
SS44
SRXD setup before (Tx) CK falling
10.0
—
ns
SS45
SRXD hold after (Tx) CK falling
2.0
—
ns
SS46
SRXD rise/fall time
—
6.0
ns
•
•
•
•
•
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
4.7.15.4
SSI Receiver Timing with External Clock
Figure 95 depicts the SSI receiver external clock timing and Table 105 lists the timing parameters for the
SSI receiver external clock.
SS22
SS26
SS24
SS25
SS23
TXC
(Input)
SS30
SS28
TXFS (bl)
(Input)
SS32
SS34
SS35
TXFS (wl)
(Input)
SS41
SS40
SS36
RXD
(Input)
Figure 95. SSI Receiver External Clock Timing Diagram
Table 105. SSI Receiver Timing with External Clock
ID
Parameter
Min
Max
Unit
81.4
—
ns
External Clock Operation
SS22
(Tx/Rx) CK clock period
SS23
(Tx/Rx) CK clock high period
36
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
36
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS28
(Rx) CK high to FS (bl) high
–10
15.0
ns
SS30
(Rx) CK high to FS (bl) low
10
—
ns
SS32
(Rx) CK high to FS (wl) high
–10
15.0
ns
SS34
(Rx) CK high to FS (wl) low
10
—
ns
SS35
(Tx/Rx) External FS rise time
—
6.0
ns
SS36
(Tx/Rx) External FS fall time
—
6.0
ns
SS40
SRXD setup time before (Rx) CK low
10
—
ns
SS41
SRXD hold time after (Rx) CK low
2
—
ns
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Electrical Characteristics
•
•
•
•
•
4.7.16
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
UART
Table 106 shows the UART I/O configuration based on which mode is enabled.
Table 106. UART I/O Configuration vs. Mode
DTE Mode
DCE Mode
Port
Direction
Description
Direction
Description
RTS
Output
RTS from DTE to DCE
Input
RTS from DTE to DCE
CTS
Input
CTS from DCE to DTE
Output
CTS from DCE to DTE
DTR
Output
DTR from DTE to DCE
Input
DTR from DTE to DCE
DSR
Input
DSR from DCE to DTE
Output
DSR from DCE to DTE
DCD
Input
DCD from DCE to DTE
Output
DCD from DCE to DTE
RI
Input
RING from DCE to DTE
Output
RING from DCE to DTE
TXD_MUX
Input
Serial data from DCE to DTE
Output
Serial data from DCE to DTE
RXD_MUX
Output
Serial data from DTE to DCE
Input
Serial data from DTE to DCE
4.7.16.1
UART Electrical
This section describes the electrical information of the UART module.
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Electrical Characteristics
4.7.16.1.1
UART RS-232 Serial Mode Timing
UART Transmitter
Figure 96 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 107 lists the UART RS-232 serial mode transmit timing characteristics.
Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram
Table 107. UART RS-232 Serial Mode Transmit Timing Diagram
1
ID
Parameter
Symbol
Min
Max
Units
UA1
Transmit Bit Time
tTbit
1/Fbaud_rate1-Tref_clk2
1/Fbaud_rate+Tref_clk
—
1/Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
2
UART Receiver
Figure 97 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 108 lists
serial mode receive timing characteristics.
Figure 97. UART RS-232 Serial Mode Receive Timing Diagram
Table 108. UART RS-232 Serial Mode Transmit Timing Diagram
ID
Parameter
Symbol
Min
Max
Units
UA1
Receive Bit Time1
tRbit
1/Fbaud_rate2-1/(16×Fbaud_rate)
1/Fbaud_rate+1/(16×Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16×Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must
not exceed 3/(16×Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.7.16.1.2
UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
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Electrical Characteristics
UART IrDA Mode Transmitter
Figure 98 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 109 lists
the transmit timing characteristics.
Figure 98. UART IrDA Mode Transmit Timing Diagram
Table 109. IrDA Mode Transmit Timing Parameters
1
2
ID
Parameter
Symbol
Min
Max
Units
UA3
Transmit Bit Time in
IrDA mode
tTIRbit
1/Fbaud_rate1-Tref_clk2
1/Fbaud_rate+Tref_clk
—
UA4
Transmit IR Pulse
Duration
tTIRpulse
(3/16)×(1Fbaud_rate)-Tref_clk
(3/16)×(1Fbaud_rate)+Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
UART IrDA Mode Receiver
Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 110 lists
the receive timing characteristics.
Figure 99. UART IrDA Mode Receive Timing Diagram
Table 110. IrDA Mode Receive Timing Parameters
1
ID
Parameter
Symbol
Min
Max
Units
UA5
Receive Bit Time1 in
IrDA mode
tRIRbit
1/Fbaud_rate21/(16×Fbaud_rate)
1/Fbaud_rate +
1/(16×Fbaud_rate)
—
UA6
Receive IR Pulse
Duration
tRIRpulse
1.41 us
(5/16)×(1/Fbaud_rate)
—
The UART receiver can tolerate 1/(16×Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must
not exceed 3/(16×Fbaud_rate).
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Electrical Characteristics
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.7.17
USBOH3 Parameters
This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip
USB PHY parameters see Section 4.7.19, “USB PHY Parameters.”
4.7.17.1
USB Serial Interface
In order to support four serial different interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
• DAT_SE0 bidirectional, 3-wire mode
• DAT_SE0 unidirectional, 6-wire mode
• VP_VM bidirectional, 4-wire mode
• VP_VM unidirectional, 6-wire mode
The USB controller does not support ULPI Serial mode. Only the legacy serial mode is supported.
Table 111 shows the serial mode signal map for 6-pin Full speed/Low speed (FsLs) serial mode.
Table 112 shows the serial mode signal map for 3-pin FsLs serial mode.
Table 111. Serial Mode Signal Map for 6-pin FsLs Serial Mode
Signal
Maps to
Direction
Description
tx_enable
data(0)
In
Active high transmit enable
tx_dat
data(1)
In
Transmit differential data on D+/D–
tx_se0
data(2)
In
Transmit single-ended zero on D+/D–
int
data(3)
Out
Active high interrupt indication
Must be asserted whenever any unmasked interrupt occurs
rx_dp
data(4)
Out
Single-ended receive data from D+
rx_dm
data(5)
Out
Single-ended receive data from D–
rx_rcv
data(6)
Out
Differential receive data from D+/D–
Reserved
data(7)
Out
Reserved The PHY must drive this signal low
Table 112. Serial Mode Signal Map for 3-pin FsLs Serial Mode
Signal
Maps to
Direction
Description
tx_enable
data(0)
In
Active high transmit enable
dat
data(1)
I/O
Transmit differential data on D+/D– when tx_enable is high
Receive differential data on D+/D– when tx_enable is low
se0
data(2)
I/O
Transmit single-ended zero on D+/D– when tx_enable is high
Receive single-ended zero on D+/D– when tx_enable is low
int
data(3)
Out
Active high interrupt indication
Must be asserted whenever any unmasked interrupt occurs
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Electrical Characteristics
4.7.17.1.1
USB DAT_SE0 Bi-Directional Mode
Table 113 shows the signal definitions in DAT_SE0 bi-directional mode and Figure 100 shows the USB
transmit waveform in DAT_SE0 bi-directional mode.
Table 113. Signal Definitions—DAT_SE0 Bi-Directional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
In
TX data when USB_TXOE_B is low
Differential RX data when USB_TXOE_B is high
USB_SE0_VM
Out
In
SE0 drive when USB_TXOE_B is low
SE0 RX indicator when USB_TXOE_B is high
US3
Transmit
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US1
US4
US2
Figure 100. USB Transmit Waveform in DAT_SE0 Bi-Directional Mode
Figure 101 shows the USB receive waveform in DAT_SE0 bi-directional mode and Table 114 shows the
definitions of USB receive waveform in DAT_SE0 bi-directional mode.
Receive
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US7
US8
USB_SE0_VM
Figure 101. USB Receive Waveform in DAT_SE0 Bi-Directional Mode
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Electrical Characteristics
Table 114. Definitions of USB Receive Waveform in DAT_SE0 Bi-Directional Mode
ID
Parameter
Signal Name
Direction
Min
Max
Unit
Conditions/
Reference Signal
US1
TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US2
TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US3
TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US4
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US7
RX Rise/Fall Time
USB_DAT_VP
In
—
3.0
ns
35 pF
US8
RX Rise/Fall Time
USB_SE0_VM
In
—
3.0
ns
35 pF
4.7.17.1.2
USB DAT_SE0 Unidirectional Mode
Table 115 shows the signal definitions in DAT_SE0 unidirectional mode
Table 115. Signal Definitions—DAT_SE0 Unidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
TX data when USB_TXOE_B is low
USB_SE0_VM
Out
SE0 drive when USB_TXOE_B is low
USB_VP1
In
Buffered data on DP when USB_TXOE_B is high
USB_VM1
In
Buffered data on DM when USB_TXOE_B is high
USB_RCV
In
Differential RX data when USB_TXOE_B is high
Figure 102 and Figure 103 shows the USB transmit/receive waveform in DAT_SE0 uni-directional mode
respectively.
US11
Transmit
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US9
US12
US10
Figure 102. USB Transmit Waveform in DAT_SE0 Uni-directional Mode
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Electrical Characteristics
Receive
USB_TXOE_B
USB_DAT_VP
USB_RCV
US16
US15/US17
USB_SE0_VM
Figure 103. USB Receive Waveform in DAT_SE0 Uni-directional Mode
Table 116 shows the USB port timing specification in DAT_SE0 uni-directional mode.
Table 116. USB Port Timing Specification in DAT_SE0 Uni-Directional Mode
Signal Name
Signal
Source
Min
Max
Unit
Condition/
Reference Signal
TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US10 TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US11 TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US12 TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US15 RX Rise/Fall Time
USB_VP1
In
—
3.0
ns
35 pF
US16 RX Rise/Fall Time
USB_VM1
In
—
3.0
ns
35 pF
US17 RX Rise/Fall Time
USB_RCV
In
—
3.0
ns
35 pF
ID
US9
Parameter
4.7.17.1.3
USB VP_VM Bi-Directional Mode
Table 117 shows the signal definitions in VP_VM bi-directional mode. Figure 104 and Figure 105 shows
the USB transmit/receive waveform in VP_VM bi-directional mode respectively.
Table 117. Signal Definitions—VP_VM Bi-Directional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
USB_DAT_VP
Out (Tx)
In (Rx)
TX VP data when USB_TXOE_B is low
RX VP data when USB_TXOE_B is high
USB_SE0_VM
Out (Tx)
In (Rx)
TX VM data when USB_TXOE_B low
RX VM data when USB_TXOE_B high
USB_RCV
In
Transmit enable, active low
Differential RX data
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Electrical Characteristics
Transmit
US20
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US18
US21
US19
US22
US22
Figure 104. USB Transmit Waveform in VP_VM Bi-Directional Mode
Receive
US26
USB_DAT_VP
USB_SE0_VM
US27
US28
USB_RCV
US29
Figure 105. USB Receive Waveform in VP_VM Bi-Directional Mode
Table 118 shows the USB port timing specification in VP_VM bi-directional mode.
Table 118. USB Port Timing Specification in VP_VM Bi-directional Mode
ID
Parameter
Signal Name
Direction
Min
Max
Unit
Condition/Reference Signal
US18 TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US19 TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US20 TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US21 TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US22 TX Overlap
USB_SE0_VM
Out
–3.0
3.0
ns
USB_DAT_VP
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Table 118. USB Port Timing Specification in VP_VM Bi-directional Mode (continued)
ID
Parameter
Signal Name
Direction
Min
Max
Unit
Condition/Reference Signal
US26 RX Rise/Fall Time
USB_DAT_VP
In
—
3.0
ns
35 pF
US27 RX Rise/Fall Time
USB_SE0_VM
In
—
3.0
ns
35 pF
US28 RX Skew
USB_DAT_VP
In
–4.0
4.0
ns
USB_SE0_VM
US29 RX Skew
USB_RCV
In
–6.0
2.0
ns
USB_DAT_VP
4.7.17.1.4
USB VP_VM Uni-Directional Mode
Table 119 shows the signal definitions in VP_VM uni-directional mode. Figure 106 and Figure 107
shows the USB transmit/receive waveform in VP_VM uni-directional mode respectively.
Table 119. USB Signal Definitions—VP_VM Uni-Directional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
TX VP data when USB_TXOE_B is low
USB_SE0_VM
Out
TX VM data when USB_TXOE_B is low
USB_VP1
In
RX VP data when USB_TXOE_B is high
USB_VM1
In
RX VM data when USB_TXOE_B is high
USB_RCV
In
Differential RX data
Transmit
US32
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US30
US33
US31
US34
US34
Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode
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Electrical Characteristics
Receive
USB_TXOE_B
USB_VP1
US38
USB_VM1
US40
USB_RCV
US39
US41
Figure 107. USB Receive Waveform in VP_VM Uni-directional Mode
Table 120 shows the USB port timing specification in VP_VM uni-directional mode.
Table 120. USB Timing Specification in VP_VM Unidirectional Mode
ID
Parameter
Signal
Direction
Min
Max
Unit
Conditions / Reference Signal
US30
TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US31
TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US32
TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US33
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US34
TX Overlap
USB_SE0_VM
Out
–3.0
3.0
ns
USB_DAT_VP
US38
RX Rise/Fall Time
USB_VP1
In
—
3.0
ns
35 pF
US39
RX Rise/Fall Time
USB_VM1
In
—
3.0
ns
35 pF
US40
RX Skew
USB_VP1
In
–4.0
4.0
ns
USB_VM1
US41
RX Skew
USB_RCV
In
–6.0
2.0
ns
USB_VP1
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4.7.18
USB Parallel Interface Timing
Electrical and timing specifications of Parallel Interface are presented in the subsequent sections.
Table 121 shows the signal definitions in parallel mode. Figure 108 shows the USB transmit/receive
waveform in parallel mode. Table 122 shows the USB timing specification for ULPI parallel mode.
Table 121. Signal Definitions—Parallel Interface (Normal ULPI)
Name
Direction
Signal Description
USB_Clk
In
Interface clock. All interface signals are synchronous to Clock.
USB_Data[7:0]
I/O
Bi-directional data bus, driven low by the link during idle. Bus
ownership is determined by Dir.
USB_Dir
In
Direction. Control the direction of the Data bus.
USB_Stp
Out
USB_Nxt
In
Stop. The link asserts this signal for 1 clock cycle to stop the data
stream currently on the bus.
Next. The PHY asserts this signal to throttle the data.
USB_Clk
US16
US15
USB_Dir/Nxt
US15
US16
USB_Data
US17
US17
USB_Stp
Figure 108. USB Transmit/Receive Waveform in Parallel Mode
Table 122. USB Timing Specification for ULPI Parallel Mode
ID
1
Parameter
Min
Max
Unit
Conditions/
Reference Signal
US15
Setup Time (Dir, Nxt in, Data in)
6
—
ns
10 pF
US16
Hold Time (Dir, Nxt in, Data in)
0
—
ns
10 pF
US17
Output delay Time (Stp out, Data out) for H3 routed to DISP2 I/O1
and H1
—
9
ns
10 pF
US17
Output delay Time (Stp out, Data out) for H2
—
11
ns
10 pF
H3 routed to NANDF I/O is recommended for Full and Low-Speed use only.
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Electrical Characteristics
4.7.19
USB PHY Parameters
This section describes the USB PHY parameters.
4.7.19.1
USB PHY AC Parameters
Table 123 lists the AC timing parameters for USB PHY.
Table 123. USB PHY AC Timing Parameters
Parameter
Conditions
Min
Typ
Max
Unit
trise
1.5 Mbps
12 Mbps
480 Mbps
75
4
0.5
—
300
20
ns
tfall
1.5 Mbps
12 Mbps
480 Mbps
75
4
0.5
—
300
20
ns
Jitter
1.5 Mbps
12 Mbps
480 Mbps
—
—
10
1
0.2
ns
4.7.19.2
USB PHY Additional Electrical Parameters
Table 124 lists the parameters for additional electrical characteristics for USB PHY.
Table 124. Additional Electrical Characteristics for USB PHY
Parameter
Conditions
Min
Typ
Max
Unit
–0.05
0.8
—
0.5
2.5
V
Vcm DC
(dc level measured at receiver connector)
HS Mode
LS/FS Mode
Crossover Voltage
LS Mode
FS Mode
1.3
1.3
—
2
2
V
Power supply ripple noise
(analog 3.3 V)
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