NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6SLCEC
Rev. 6, 11/2018
MCIMX6LxDVN10xx
MCIMX6LxEVN10xx
i.MX 6SoloLite
Applications Processors
for Consumer Products
Package Information
Plastic Package
13 x 13 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 3
1
Introduction
The i.MX 6SoloLite processor represents the latest
achievement in integrated multimedia applications
processors, which are part of a growing family of
multimedia-focused products that offer high
performance processing and are optimized for lowest
power consumption.
The processor features NXP’s advanced implementation
of the a single ARM® Cortex®-A9 MPCore™ multicore
processor, which operates at speeds up to 1 GHz. It
includes 2D graphics processor and integrated power
management. The processor provides a 32-bit
DDR3-800 memory interface and a number of other
interfaces for connecting peripherals, such as WLAN,
Bluetooth™, GPS, hard drive, displays, and camera
sensors.
The i.MX 6SoloLite processor is specifically useful for
applications, such as:
• Color and monochrome eReaders
• Entry level tablets
• Barcode scanners
1
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Updated Signal Naming Convention . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 15
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Power Supplies Requirements and Restrictions . . 26
4.3 Integrated LDO Voltage Regulator Parameters . . 27
4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . . 29
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 38
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 40
4.10 External Peripheral Interface Parameters . . . . . . . 52
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . 80
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . . 80
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . . 81
Package Information and Contact Assignments . . . . . . . 82
6.1 Updated Signal Naming Convention . . . . . . . . . . . 82
6.2 13 x 13mm Package Information. . . . . . . . . . . . . . 83
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
NXP Reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
Introduction
The i.MX 6SoloLite processor features:
• Applications processor—The processor enhances the capabilities of high-tier portable applications
by fulfilling the ever increasing MIPS requirements of operating systems and games. The Dynamic
Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device
to run at lower voltage and frequency with sufficient MIPS for tasks, such as audio decode.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, LPDDR2, NOR Flash, PSRAM, cellular
RAM, and managed NAND, including eMMC up to rev 4.4/4.41.
• Smart speed technology—The processor has power management throughout the IC that enables the
rich suite of multimedia features and peripherals to consume minimum power in both active and
various low power modes. Smart speed technology enables the designer to deliver a feature-rich
product, requiring levels of power far lower than industry expectations.
• Dynamic voltage and frequency scaling—The processor improves the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1
accelerator.
• Interface flexibility—The processor supports connections to a variety of interfaces: LCD
controller, CMOS sensor interface (parallel), high-speed USB on-the-go with PHY, high-speed
USB host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other),
10/100 Mbps Ethernet controller, and a variety of other popular interfaces (such as UART, I2C, and
I2S serial audio).
• Electronic Paper Display Controller—The processor integrates EPD controller that supports E Ink
color and monochrome with up to 2048 x 1536 resolution at 106 Hz refresh, 4096 x 4096 resolution
at 20 Hz refresh and 5-bit grayscale (32-levels per color channel).
• Advanced security—The processor delivers hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6SoloLite security
reference manual (IMX6SLSRM). Contact your local NXP representative for more information.
• Integrated power management—The processor integrates linear regulators and generate internally
all the voltage levels for different domains. This significantly simplifies system power management
structure.
• GPIO with interrupt capabilities—The new GPIO pad design supports configurable dual voltage
rails at 1.8 V and 3.3 V supplies. The pad is configurable to interface at either voltage level.
1.1
Ordering Information
Table 1 provides examples of orderable part numbers covered by this data sheet. Table 1 does not include
all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
2
NXP Semiconductors
Introduction
desired part number is not listed in Table 1, or you have questions about available parts, see
nxp.com/imx6series or contact your NXP representative.
Table 1. Example Orderable Part Numbers
Options
Speed
Grade1
Temperature
(Tj)
Package2
MCIMX6L8DVN10AB
GPU, EPDC
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L8DVN10AC
GPU, EPDC
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L7DVN10AB
EPDC, no GPU
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L7DVN10AC
EPDC, no GPU
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L3DVN10AB
GPU, no EPDC
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L3DVN10AC
GPU, no EPDC
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L3EVN10AB
GPU, no EPDC
1GHz
-40°C to +105°C
13x13mm, 0.5mm pitch BGA
MCIMX6L3EVN10AC
GPU, no EPDC
1GHz
-40°C to +105°C
13x13mm, 0.5mm pitch BGA
MCIMX6L2DVN10AB
no GPU, no EPDC
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L2DVN10AC
no GPU, no EPDC
1GHz
0°C to +95°C
13x13mm, 0.5mm pitch BGA
MCIMX6L2EVN10AB
no GPU, no EPDC
1GHz
-40°C to +105°C
13x13mm, 0.5mm pitch BGA
MCIMX6L2EVN10AC
no GPU, no EPDC
1GHz
-40°C to +105°C
13x13mm, 0.5mm pitch BGA
Part Number
1
2
If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Case 2240 is RoHS compliant, lead-free moisture sensitivity level 3 (MSL).
Figure 1 describes the part number nomenclature so that users can identify the characteristics of the
specific part number they have (for example, Cores, Frequency, Temperature Grade, Fuse options, Silicon
revision).
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
3
Introduction
MC
IMX6
X
@
+
VV
$$
%
A
Silicon revision1
A
Rev 1.0
A
MC
Rev 1.2
Rev 1.3
B2
Special
SC
Rev 1.4
C
Part # series
X
Fusing
%
i.MX 6SoloLite
L
Supports E-INK EPDC if EPD
enabled
A
Part differentiator
@
Frequency
$$
GPU, EPD
8
1 GHz
10
Qualification level
MC
Prototype samples
PC
Mass production
No GPU, EPD
7
GPU, no EPD
3
No GPU, no EPD
2
Package type
MAPBGA 13x13 0.5mm
Temperature Tj
+
Commercial: 0 to + 95°C
D
Extended commercial: -40 to + 105°C
E
RoHS
VN
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.
2. Rev 1.2 (USB_ANALOG_DIGPROG register = 0x0062_0002)
Rev 1.3 (USB_ANALOG_DIGPROG register = 0x0062_0003)
Figure 1. Part Number Nomenclature—i.MX 6SoloLite
1.2
Features
The i.MX 6SoloLite processor is based on ARM Cortex-A9 MPCore multicore processor, which has the
following features:
• ARM Cortex-A9 MPCore CPU processor (with TrustZone)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) co-processor
The ARM Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 256 KB unified I/D L2 cache
• Two Master AXI (64-bit) bus interfaces output of L2 cache
• Frequency of the core (including NEON and L1 cache) as per Table 9, "Operating Ranges," on
page 21
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
4
NXP Semiconductors
Introduction
•
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
• External memory interfaces:
— 16-bit, and 32-bit DDR3-800, and LPDDR2-800 channels
— 16/32-bit NOR Flash.
— 16/32-bit PSRAM, Cellular RAM (32 bits or less)
Each i.MX 6SoloLite processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Displays—Total of three interfaces are available.
— LCD, 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz)
— EPDC, color, and monochrome E Ink, up to 1650 x 2332 resolution and 5-bit grayscale
• Camera sensors:
— Parallel Camera port (up to 16-bit and up to 66 MHz peak)
• Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
– 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode
(200 MB/s max)
• USB:
— Two High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
— One USB 2.0 (480 Mbps) hosts:
– One HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy
• Miscellaneous IPs and interfaces:
— SSI block—capable of supporting audio sample frequencies up to 192 kHz stereo inputs and
outputs with I2S mode
— Five UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
5
Introduction
—
—
—
—
—
—
—
—
—
—
– One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is
due to the SoC IOMUX limitation, since all UART IPs are identical.
Four eCSPI (Enhanced CSPI)
Three I2C, supporting 400 kbps
Ethernet Controller, 10/100 Mbps
Four Pulse Width Modulators (PWM)
System JTAG Controller (SJC)
GPIO with interrupt capabilities
8x8 Key Pad Port (KPP)
Sony Philips Digital Interface (SPDIF), Rx and Tx
Two Watchdog timers (WDOG)
Audio MUX (AUDMUX)
The i.MX 6SoloLite processor integrates advanced power management unit and controllers:
• Provide PMU, including LDO supplies, for on-chip resources
• Use Temperature Sensor for monitoring the die temperature
• Support DVFS techniques for low power modes
• Use Software State Retention and Power Gating for ARM and MPE
• Support various levels of system power modes
• Use flexible clock gating control scheme
The i.MX 6SoloLite processor uses dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6SoloLite processor incorporates the following hardware accelerators:
• GPU2Dv2—2D Graphics Processing Unit (BitBlt).
• GPUVG—OpenVG 1.1 Graphics Processing Unit.
• PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to
support the EPD display applications.
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so
on.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock.
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
6
NXP Semiconductors
Introduction
NOTE
The actual feature set depends on the part numbers as described in Table 1,
"Example Orderable Part Numbers," on page 3. Functions, such as 2D
hardware graphics acceleration or E Ink may not be enabled for specific part
numbers.
1.3
Updated Signal Naming Convention
The signal names of the i.MX6 series of products have been standardized to better align the signal names
within the family and across the documentation. Some of the benefits of these changes are as follows:
• The names are unique within the scope of an SoC and within the series of products
• Searches will return all occurrences of the named signal
• The names are consistent between i.MX 6 series products implementing the same modules
• The module instance is incorporated into the signal name
This change applies only to signal names. The original ball names have been preserved to prevent the need
to change schematics, BSDL models, IBIS models, and so on.
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to
map the signal names used in older documentation to the new standardized naming conventions.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
7
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX 6SoloLite processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6SoloLite processor system.
Figure 2. i.MX 6SoloLite System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (4) indicates four separate PWM peripherals.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
8
NXP Semiconductors
Modules List
3
Modules List
The i.MX 6SoloLite processor contains a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6SoloLite Modules List
Block
Mnemonic
Block Name
Subsystem
Brief Description
128x8
Fuse Box
Electrical Fuse
Array
Security
Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security
Keys, and many other system parameters.
The i.MX 6SoloLite processor consists of 2-128x8-bit fuse box accessible
through OCOTP_CTRL interface.
ARM
ARM Platform
ARM
The ARM Cortex-A9 platform consists of a Cortex-A9 core version r2p10 and
associated sub-blocks, including Level 2 Cache Controller, SCU (Snoop
Control Unit), GIC (General Interrupt Controller), private timers, Watchdog,
and CoreSight debug modules.
AUDMUX
Digital
Audio Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs).
The AUDMUX has seven ports with identical functionality and programming
models. A desired connectivity is achieved by configuring two or more
AUDMUX ports.
CCM
GPC
SRC
Clock Control
Module,
General Power
Controller,
System Reset
Controller
CSU
Central
Security Unit
CTI-1
CTI-2
CTI-3
CTI-4
CTI-5
Cross Trigger
Interfaces
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from masters
attached to CTIs. The CTI module is internal to the Cortex-A9 Core Platform.
CTM
Cross Trigger
Matrix
Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs. The
CTM module is internal to the Cortex-A9 Core Platform.
DAP
Debug Access
Port
System Control The DAP provides real-time access for the debugger without halting the core
Peripherals to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains. The DAP
module is internal to the Cortex-A9 Core Platform.
DCP
Data
co-processor
Clocks, Resets, These modules are responsible for clock and reset distribution in the system,
and also for the system power management.
and Power
Control
Security
Security
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX 6SoloLite platform. The Security Control
Registers (SCR) of the CSU are set during boot time by the HAB and are
locked to prevent further writing.
This module provides support for general encryption and hashing functions
typically used for security functions. Because its basic job is moving data
from memory to memory, it also incorporates a memory-copy (memcopy)
function for both debugging and as a more efficient method of copying data
between memory blocks than the DMA-based approach.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
9
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
eCSPI-1
eCSPI-2
eCSPI-3
eCSPI-4
Configurable
SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface. It is configurable to
support Master/Slave modes, four chip selects to support multiple peripherals.
EIM
NOR-Flash
/PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and async
operating modes), at slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow
frequency
• Multiple chip selects
EPDC
Electrophoretic
Display
Controller
Peripherals
The EPDC is a feature-rich, low power, and high-performance direct-drive,
active matrix EPD controller. It is specifically designed to drive E Ink EPD
panels, supporting a wide variety of TFT backplanes.
EPIT-1
EPIT-2
Enhanced
Periodic
Interrupt
Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT
is enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for
division of input clock frequency to get the required time setting for the
interrupts to occur, and counter value can be programmed on the fly.
FEC
Fast Ethernet
Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support 10 and
100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface
and transceiver function are required to complete the interface to the media.
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
General Purpose System Control Used for general purpose input/output to external ICs. Each GPIO module
I/O Modules
Peripherals supports 32 bits of I/O.
GPT
General
Purpose
Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event and can be configured to trigger
a capture event on either the leading or trailing edges of an input pulse. When
the timer is configured to operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with minimal processor
intervention. The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on an
external clock or on an internal clock.
GPU2Dv2
Graphics
Processing
Unit-2D, ver 2
Multimedia
Peripherals
The GPU2Dv2 provides hardware acceleration for 2D graphics algorithms,
such as Bit BLT, stretch BLT, and many other 2D functions.
GPUVGv2
Vector Graphics
Processing
Unit, ver2
Multimedia
Peripherals
OpenVG graphics accelerator provides OpenVG 1.1 support as well as other
accelerations, including Real-time hardware curve tesselation of lines,
quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and various Vector
Drawing functions.
I2C-1
I2C-2
I2C-3
I2C Interface
Connectivity
Peripherals
I2C provide serial interface for external devices. Data rates of up to 400 kbps
are supported.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
10
NXP Semiconductors
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
IOMUXC
IOMUX
Control
System Control This module enables flexible IO multiplexing. Each IO pad has default and
Peripherals several alternate functions. The alternate functions are software configurable.
KPP
Key Pad Port
Connectivity
Peripherals
KPP Supports 8 x 8 external key pad matrix. KPP features are:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LCDIF
LCD Interface
Multimedia
Peripherals
The LCDIF provides display data for external LCD panels from simple text-only
displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF supports all of
these different interfaces by providing fully programmable functionality and
sharing register space, FIFOs, and ALU resources at the same time. The
LCDIF supports RGB (DOTCLK) modes as well as system mode including
both VSYNC and WSYNC modes.
MMDC
DDR
Controller
Connectivity
Peripherals
DDR Controller has the following features:
• Support 16/32-bit DDR3-800 or LPDDR2-800
• Supports up to 2 GByte DDR memory space
OCOTP_
CTRL
OTP
Controller
Security
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control information
stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals, requiring permanent
non-volatility.
OCRAM
On-Chip Memory
Controller
Data Path
The On-Chip Memory controller (OCRAM) module is designed as an interface
between system’s AXI bus and internal (on-chip) SRAM memory module.
In i.MX 6SoloLite processor, the OCRAM is used for controlling the 128 KB
multimedia RAM through a 64-bit AXI bus.
OCRAM_L2 On-Chip Memory
Controller for
L2 Cache
Data Path
The On-Chip Memory controller for L2 cache (OCRAM_L2) module is
designed as an interface between system’s AXI bus and internal (on-chip) L2
cache memory module during boot mode.
OSC 32 kHz
OSC 32 kHz
Clocking
Generates 32.768 kHz clock from external crystal.
PMU
Power
Management
functions
Data Path
Integrated power management unit. Used to provide power to various SoC
domains.
PWM-1
PWM-2
PWM-3
PWM-4
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images and it can also generate
tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
11
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
PXP
PiXel
Processing
Pipeline
Display
Peripherals
A high-performance pixel processor capable of 1 pixel/clock performance for
combined operations, such as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced with features specifically
for gray scale applications. In addition, the PXP supports traditional
pixel/frame processing paths for still-image and video processing applications,
allowing it to interface with either of the integrated EPD controllers.
RAM
128 KB
Internal RAM
Internal
Memory
Internal RAM, which is accessed through OCRAM memory controller.
RNGB
Random Number
Generator
Security
Random number generating module.
ROM
96KB
Boot ROM
Internal
Memory
Supports secure and regular Boot Modes. Includes read protection on 4K
region for content protection.
ROMCP
ROM Controller
with Patch
Data Path
SDMA
Smart Direct
Memory
Access
System Control The SDMA is multi-channel flexible DMA engine. It helps in maximizing
Peripherals system performance by off-loading the various cores in dynamic data routing.
It has the following features:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA
channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM and SDMA
• Very fast Context-Software switching with 2-level priority based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement,
and no address changes on source and destination address)
• DMA ports can handle unit-directional and bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
System JTAG
Controller
System Control The SJC provides JTAG interface, which complies with JTAG TAP standards,
Peripherals to internal logic. The i.MX 6SoloLite processor uses JTAG port for production,
testing, and system debugging. In addition, the SJC provides BSR (Boundary
Scan Register) standard support, which complies with IEEE1149.1 and
IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory bring-up,
for manufacturing tests and troubleshooting, as well as for software debugging
by authorized entities. The i.MX 6SoloLite SJC incorporates three security
modes for protecting against unauthorized accesses. Modes are selected
through eFUSE configuration.
SNVS
Secure
Non-Volatile
Storage
Security
SPDIF
Sony Phillips
Digital Interface
Multimedia
Peripherals
ROM Controller with ROM Patch support.
Secure Non-Volatile Storage, including Secure Real Time Clock, Security
State Machine, Master Key Control, and Violation/Tamper Detection and
reporting.
A standard audio file transfer format, developed jointly by the Sony and Phillips
corporations. Has Transmitter and Receiver functionality.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
12
NXP Semiconductors
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface, which is used on the AP to
provide connectivity with off-chip audio peripherals. The SSI supports a wide
variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up
to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware support for an external
DMA controller in order to minimize its impact on system performance. The
second pair of FIFOs provides hardware interleaving of a second audio stream
that reduces CPU overhead in use cases where two time slots are being used
simultaneously.
TEMPMON
Temperature
Monitor
TZASC
Trust-Zone
Address Space
Controller
Security
The TZASC (TZC-380 by ARM) provides security address region control
functions required for intended application. It is used on the path to the DRAM
controller.
UART-1
UART-2
UART-3
UART-4
UART-5
UART
Interface
Connectivity
Peripherals
Each of the UARTv2 modules support the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or
none)
• Programmable baud rates up to 5.0 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USBOH2A
2x USB 2.0 High
Speed OTG and
1x HS Hosts
Connectivity
Peripherals
USBO2H contains:
• Two high-speed OTG module with integrated HS USB PHY
• One identical high-speed Host modules connected to HSIC USB ports
System Control The temperature monitor/sensor IP, for detecting high temperature conditions.
Peripherals The Temperature sensor IP for detecting die temperature. The temperature
read out does not reflect case or ambient temperature, but the proximity of the
temperature sensor location on the die. Temperature distribution may not be
uniformly distributed, therefore the read out value may not be the reflection of
the temperature value of the entire die.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
13
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
uSDHC-1
uSDHC-2
uSDHC-2
uSDHC-4
SD/MMC and
SDXC
Enhanced
Multi-Media Card
/ Secure Digital
Host Controller
Connectivity
Peripherals
i.MX 6SoloLite specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and are based on the
uSDHC IP. They are:
• Conforms to the SD Host Controller Standard Specification version 3.0.
• Fully compliant with MMC command/response sets and Physical Layer as
defined in the Multimedia Card System Specification, v4.2/4.3/4.4/4.41/4.5
including high-capacity (size > 2 GB) cards HC MMC. Hardware reset as
specified for eMMC cards is supported at ports 3 and 4 only.
• Fully compliant with SD command/response sets and Physical Layer as
defined in the SD Memory Card Specifications, v3.0 including high-capacity
SDHC cards up to 32 GB and SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets and interrupt/read-wait
mode as defined in the SDIO Card Specification, Part E1, v1.10
• Fully compliant with SD Card Specification, Part A2, SD Host Controller
Standard Specification, v2.00
All four ports support:
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
UHS-I SDR104 mode (104 MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to
52 MHz in both SDR and DDR modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in
HS200 mode (200 MB/s max)
However, the SoC level integration and I/O muxing logic restrict the
functionality to the following:
• Instances 1 and 2 are primarily intended to serve as external slots or
interfaces to on-board SDIO devices. These ports are equipped with “Card
detection” and “Write Protection” pads and do not support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There are two completely
independent I/O power domains for Ports 1 and 2 in four bit configuration
(SD interface). Port 3 is placed in an independent power domain and port 4
shares its power domain with other interfaces.
WDOG-1
Watchdog
Timer
Peripherals
The Watchdog Timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt to
the ARM core, and a second point evokes an external event on the WDOG
line.
WDOG-2
(TZ)
Watchdog
(TrustZone)
Timer
Peripherals
The TrustZone Watchdog (TZ WDOG) timer module protects against
TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the normal
OS prevents switching to the TZ mode. Such situation is undesirable as it can
compromise the system’s security. Once the TZ WDOG module is activated, it
must be serviced by TZ software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ
mapped interrupt that forces switching to the TZ mode. If it is still not served,
the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG
module cannot be programmed or deactivated by a normal mode Software.
XTALOSC
Crystal
Oscillator I/F
Clocking
The XTALOSC module enables connectivity to external crystal oscillator
device. In a typical application use-case, it is used for 24 MHz oscillator.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 6, 11/2018
14
NXP Semiconductors
Modules List
3.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX 6SoloLite processor. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are provided in the i.MX 6SoloLite reference manual (IMX6SLRM).
Table 3. Special Signal Considerations
Signal Name
Remarks
XTALOSC_CLK1_P/ One general purpose differential high speed clock Input/output is provided.
XTALOSC_CLK1_N It could be used to:
• To feed external reference clock to the PLLs and further to the modules inside SoC, for example as
alternate reference clock for Audio interfaces, etc.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a functional
clock for peripherals.
See the i.MX 6SoloLite reference manual for details on the respective clock trees.
The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the maximum
clock out frequency range supported is 528 MHz.
Alternatively one may use single ended signal to drive XTALOSC_CLK1_P input. In this case, the
corresponding XTALOSC_CLK1_N input should be tied to the constant voltage level equal 1/2 of the input
signal swing.
Termination should be provided in case of high frequency signals.
See LVDS pad electrical specification for further details.
After initialization, the XTALOSC_CLK1 input/output could be disabled (if not used). If unused, the
XTALOSC_CLK1_N/P pair can remain unconnected.
DRAM_VREF
When using DRAM_VREF with DDR I/O, the nominal reference voltage must be half of the NVCC_DRAM
supply. The user must tie DRAM_VREF to a precision external resistor divider. Use a 1 kΩ 0.5% resistor
to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt each resistor with a closely-mounted 0.1 µF
capacitor.
To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with recommended
tolerances ensures the ± 2% DRAM_VREF tolerance (per the DDR3 specification) is maintained when
four DDR3 ICs plus the i.MX 6SoloLite are drawing current on the resistor divider.
It is recommended to use regulated power supply for “big” memory configurations (more that eight
devices).
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However, if
external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed.
For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an external
pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided.
JTAG_MODE must be externally connected to GND for normal operation. Termination to GND through
an external pull-down resistor (such as 1 kΩ) is allowed. JTAG_MODE set to high configures the JTAG
interface to mode compliant with IEEE1149.1 standard. JTAG_MODE set to low configures the JTAG
interface for common Software debug adding all the system TAPs to the chain.
NC
These signals are No Connect (NC) and must remain unconnected by the user.
SRC_ONOFF
In normal mode may be connected to ONOFF button (de-bouncing provided at this input). Internally this
pad is pulled up. A short duration (100 MΩ). This will
debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO
should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must remain
unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed
VDD_SNVS_CAP level and the frequency should be
工商网监
湘ICP备2023018690号
