NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6DQCEC
Rev. 6, 11/2018
MCIMX6QxExxxxC
MCIMX6QxExxxxD
MCIMX6QxExxxxE
MCIMX6DxExxxxC
MCIMX6DxExxxxD
MCIMX6DxExxxxE
i.MX 6Dual/6Quad
Applications Processors for
Consumer Products
Package Information
FCPBGA Package
21 x 21 mm, 0.8 mm pitch
Ordering Information
See Table 1
1
Introduction
The i.MX 6Dual/6Quad processors represent the latest
achievement in integrated multimedia applications
processors. These processors are part of a growing
family of multimedia-focused products that offer high
performance processing and are optimized for lowest
power consumption.
The i.MX 6Dual/6Quad processors feature advanced
implementation of the quad Arm® Cortex®-A9 core,
which operates at speeds up to 1.2 GHz. They include 2D
and 3D graphics processors, 1080p video processing,
and integrated power management. Each processor
provides a 64-bit DDR3/DDR3L/LPDDR2 memory
interface and a number of other interfaces for connecting
peripherals, such as WLAN, Bluetooth®, GPS, hard
drive, displays, and camera sensors.
The i.MX 6Dual/6Quad processors are specifically
useful for applications such as the following:
• Netbooks (web tablets)
• Nettops (Internet desktop devices)
1
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 8
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 19
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Power Supplies Requirements and Restrictions . . 33
4.3 Integrated LDO Voltage Regulator Parameters . . 34
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 49
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 53
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 64
4.11 General-Purpose Media Interface (GPMI) Timing. 64
4.12 External Peripheral Interface Parameters . . . . . . . 73
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 138
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 138
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 139
Package Information and Contact Assignments . . . . . . 141
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 141
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 142
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Introduction
•
•
•
•
•
High-end mobile Internet devices (MID)
High-end PDAs
High-end portable media players (PMP) with HD video capability
Gaming consoles
Portable navigation devices (PND)
The i.MX 6Dual/6Quad processors offers numerous advanced features, such as:
• Applications processors—The processors enhance the capabilities of high-tier portable
applications by fulfilling the ever increasing MIPS needs of operating systems and games. The
Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing
the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio
decode.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash,
PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND,
including eMMC up to rev 4.4/4.41.
• Smart speed technology—The processors have power management throughout the device that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
• Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, Neon® MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, 2 autonomous and independent image processing units (IPU), and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: an OpenGL® ES 2.0 3D graphics accelerator with four shaders (up to 200 MTri/s
and OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.
• Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces
(such as UART, I2C, and I2S serial audio, SATA-II, and PCIe-II).
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad
security reference manual (IMX6DQ6SDLSRM).
• Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
2
NXP Semiconductors
Introduction
1.1
Ordering Information
Table 1 shows examples of orderable part numbers covered by this data sheet. This table does not include
all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your
desired part number is not listed in the table, or you have questions about available parts, see
nxp.com/imx6series or contact your NXP representative.
Table 1. Example Orderable Part Numbers
Part Number
Quad/Dual CPU
Options
Speed1
Grade
Temperature
Grade
Package
MCIMX6Q5EYM10AC
i.MX 6Quad
Includes VPU, GPU
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6Q5EYM10AD
i.MX 6Quad
Includes VPU, GPU
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6Q5EYM10AE
i.MX 6Quad
Includes VPU, GPU
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6Q5EYM10CC
i.MX 6Quad
Includes VPU, GPU,
HDCP
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6Q5EYM10CD
i.MX 6Quad
Includes VPU, GPU,
HDCP
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6Q5EYM10CE
i.MX 6Quad
Includes VPU, GPU,
HDCP
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6D5EYM10AC
i.MX 6Dual
Includes VPU, GPU
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6D5EYM10AD
i.MX 6Dual
Includes VPU, GPU
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6D5EYM10AE
i.MX 6Dual
Includes VPU, GPU
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6D5EYM10CC
i.MX 6Dual
Includes VPU, GPU,
HDCP
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6D5EYM10CD
i.MX 6Dual
Includes VPU, GPU,
HDCP
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6D5EYM10CE
i.MX 6Dual
Includes VPU, GPU,
HDCP
1 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6Q5EYM12AC
i.MX 6Quad
Includes VPU, GPU
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6Q5EYM12AD
i.MX 6Quad
Includes VPU, GPU
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6Q5EYM12AE
i.MX 6Quad
Includes VPU, GPU
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6Q5EYM12CC
i.MX 6Quad
Includes VPU, GPU,
HCP
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6Q5EYM12CD
i.MX 6Quad
Includes VPU, GPU,
HCP
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
NXP Semiconductors
3
Introduction
Table 1. Example Orderable Part Numbers (continued)
1
Speed1
Grade
Temperature
Grade
Package
Includes VPU, GPU,
HCP
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
i.MX 6Dual
Includes VPU, GPU
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6D5EYM12AD
i.MX 6Dual
Includes VPU, GPU
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6D5EYM12AE
i.MX 6Dual
Includes VPU, GPU
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6D5EYM12CC
i.MX 6Dual
Includes VPU, GPU,
HCP
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6D5EYM12CD
i.MX 6Dual
Includes VPU, GPU,
HCP
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
SCIMX6D5EYM12CE
i.MX 6Dual
Includes VPU, GPU,
HCP
1.2 GHz
Extended
Commercial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
Part Number
Quad/Dual CPU
Options
SCIMX6Q5EYM12CE
i.MX 6Quad
MCIMX6D5EYM12AC
If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Figure 1 describes the part number nomenclature to identify the characteristics of the specific part number
you have (for example, cores, frequency, temperature grade, fuse options, silicon revision). Figure 1
applies to the i.MX 6Dual/6Quad.
The two characteristics that identify which data sheet a specific part applies to are the part number series
field and the temperature grade (junction) field:
• The i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors data sheet
(IMX6DQAEC) covers parts listed with “A (Automotive temp)”
• The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet (IMX6DQCEC)
covers parts listed with “D (Commercial temp)” or “E (Extended Commercial temp)”
• The i.MX 6Dual/6Quad Applications Processors for Industrial Products data sheet (IMX6DQIEC)
covers parts listed with “C (Industrial temp)”
The Ensure that you have the right data sheet for your specific part by checking the temperature grade
(junction) field and matching it to the right data sheet. If you have questions, see nxp.com/imx6series or
contact your NXP representative.
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
4
NXP Semiconductors
Introduction
MC
IMX6
X
@
+
VV
$$
%
A
Qualification level
MC
Silicon revision1
A
Prototype Samples
PC
Rev 1.2
C
Mass Production
MC
Rev 1.3
D
Special
SC
Rev 1.6
E
Part # series
X
Fusing
%
i.MX 6Quad
Q
Default setting
A
D
HDCP enabled
C
$$
i.MX 6Dual
Part differentiator
@
Frequency
Industrial with VPU, GPU, no MLB
7
800 MHz (Industrial grade)
08
Automotive with VPU, GPU
6
852 MHz (Automotive grade)
08
Consumer with VPU, GPU
5
1 GHz 3
10
Automotive with GPU, no VPU
4
1.2 GHz
12
Temperature Tj
+
Package type
RoHS
E
FCPBGA 21x21 0.8mm (lidded)
VT
FCPBGA 21x21 0.8mm (non lidded)
YM
Extended commercial: -20 to
+105°C
Industrial: -40 to +105°C
C
Automotive: -40 to +125°C
A
2
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Figure 1. Part Number Nomenclature—i.MX 6Quad and i.MX 6Dual
1.2
Features
The i.MX 6Dual/6Quad processors are based on Arm Cortex-A9 MPCore platform, which has the
following features:
• Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone®)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
The Arm Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 1 MB unified I/D L2 cache, shared by two/four cores
• Two Master AXI (64-bit) bus interfaces output of L2 cache
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
NXP Semiconductors
5
Introduction
•
•
Frequency of the core (including Neon and L1 cache) as per Table 6.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
• Boot ROM, including HAB (96 KB)
• Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
• Secure/non-secure RAM (16 KB)
• External memory interfaces:
— 16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels,
supporting DDR interleaving mode, for dual x32 LPDDR2
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
— 16/32-bit PSRAM, Cellular RAM
Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Hard Disk Drives—SATA II, 3.0 Gbps
• Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.
— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual
HD1080 and WXGA at 60 Hz)
— LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two
ports up to 85 MP/sec each
— HDMI 1.4 port
— MIPI/DSI, two lanes at 1 Gbps
• Camera sensors:
— Parallel Camera port (up to 20 bit and up to 240 MHz peak)
— MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to
800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to
four data lanes. Each i.MX 6Dual/6Quad processor has four lanes.
• Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
6
NXP Semiconductors
Introduction
•
•
•
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
USB:
— One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
– One HS host with integrated High Speed PHY
– Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY
Expansion PCI Express port (PCIe) v2.0 one lane
— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint
operations. Uses x1 PHY configuration.
Miscellaneous IPs and interfaces:
— SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and
outputs with I2S mode
— ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with
7.1 multi channel outputs
— Five UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This
is due to the SoC IOMUX limitation, because all UART IPs are identical.
— Five eCSPI (Enhanced CSPI)
— Three I2C, supporting 400 kbps
— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps
— Four Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
— Two Controller Area Network (FlexCAN), 1 Mbps each
— Two Watchdog timers (WDOG)
— Audio MUX (AUDMUX)
— MLB (MediaLB) provides interface to MOST Networks (150 Mbps) with the option of DTCP
cipher accelerator
The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:
• Provide PMU, including LDO supplies, for on-chip resources
• Use Temperature Sensor for monitoring the die temperature
1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus
throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the
ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
NXP Semiconductors
7
Introduction
•
•
•
•
Support DVFS techniques for low power modes
Use Software State Retention and Power Gating for Arm and MPE
Support various levels of system power modes
Use flexible clock gating control scheme
The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:
• VPU—Video Processing Unit
• IPUv3H—Image Processing Unit version 3H (2 IPUs)
• GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4
• GPU2Dv2—2D Graphics Processing Unit (BitBlt) version 2
• GPUVG—OpenVG 1.1 Graphics Processing Unit
• ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
• Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
• CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and
True and Pseudo Random Number Generator (NIST certified)
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
1.3
Signal Naming Convention
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be
used to map the signal names used in older documentation to the new standardized naming conventions.
The signal names of the i.MX6 series of products are standardized to align the signal names within the
family and across the documentation. Benefits of this standardization are as follows:
• Signal names are unique within the scope of an SoC and within the series of products
• Searches will return all occurrences of the named signal
• Signal names are consistent between i.MX 6 series products implementing the same modules
• The module instance is incorporated into the signal name
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
8
NXP Semiconductors
Introduction
This standardization applies only to signal names. The ball names are preserved to prevent the need to
change schematics, BSDL models, IBIS models, and so on.
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
NXP Semiconductors
9
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system.
Digital
Audio
DDR3 (532 MHz)
LPDDR2 (400 MHz)
NOR Flash
PSRAM
External
Memory
Interface
GPMI
MMDC
Internal
RAM
(272KB)
Smart DMA
(SDMA)
TPIU
CTIs
SJC
Shared Peripherals
SSI (3)
eCSPI (5)
5xFast-UART
ESAI
SPDIF Rx/Tx
ASRC
LDB
HDMI
ARM Cortex A9
MPCore Platform
4x A9-Core
Debug
DAP
2xCAN
Interface
1/2 LVDS
(WUXGA+)
ImageProcessing
Subsystem
2x IPUv3H
Boot
ROM
(96KB)
SPBA
PCIe
GPS
Bus
4x Camera
Parallel/MIPI
Application Processor CSI2/MIPI
Domain (AP)
EIM
SATA II
3.0Gbps
Battery Ctrl
Device
Security
CAAM
(16KB Ram)
L1 I/D Cache
Timer, Wdog
AXI and AHB Switch Fabric
Raw/ONFI 2.2
Nand-Flash
1MB L2 cache
SCU, Timer
PTM’s CTI’s
GPT
AUDMUX
MMC/SD
SDXC
OCOTP
Modem IC
KPP
GPIO
Keypad
CAN (2)
1-Gbps ENET
MLB 150
Ethernet
10/100/1000
Mbps
DTCP
HSI/MIPI
OTG PHY1
Host PHY2
WLAN
MMC/SD
eMMC/eSD
uSDHC (4)
IOMUXC
EPIT (2)
Bluetooth
SRC
XTALOSC
OSC32K
3D Graphics
Proc. Unit
(GPU3D)
OpenVG 1.1
Proc. Unit
(GPUVG)
WDOG (2)
Temp Monitor
Crystals
& Clock sources
PLL (8)
CCM
GPC
PWM (4)
2D Graphics
Proc. Unit
(GPU2D)
Timers/Control
Audio,
Power
Mgmnt.
Clock and Reset
Video
Proc. Unit
(VPU + Cache)
Fuse Box
JTAG
(IEEE1149.6)
2xHSIC
PHY
USB OTG
(dev/host)
MIPI
Display
DSI/MIPI
I2C (3)
CSU
Consumer
Standard
Block Diagram
HDMI 1.4
Display
AP Peripherals
SNVS
(SRTC)
GPS
1/2 LCD
Displays
USB OTG +
3 HS Ports
MLB/Most
Network
Figure 2. i.MX 6Dual/6Quad Consumer Grade System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (4) indicates four separate PWM peripherals.
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
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Modules List
3
Modules List
The i.MX 6Dual/6Quad processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6Dual/6Quad Modules List
Block
Mnemonic
Block Name
Subsystem
Brief Description
512 x 8 Fuse Electrical Fuse Array Security
Box
Electrical Fuse Array. Enables to setup Boot Modes, Security Levels,
Security Keys, and many other system parameters.
The i.MX 6Dual/6Quad processors consist of 512x8-bit fuse box
accessible through OCOTP_CTRL interface.
APBH-DMA
NAND Flash and
BCH ECC DMA
Controller
System
Control
Peripherals
DMA controller used for GPMI2 operation.
Arm
Arm Platform
Arm
The Arm Cortex-A9 platform consists of 4x (four) Cortex-A9 cores version
r2p10 and associated sub-blocks, including Level 2 Cache Controller,
SCU (Snoop Control Unit), GIC (General Interrupt Controller), private
timers, Watchdog, and CoreSight debug modules.
ASRC
Asynchronous
Sample Rate
Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC) converts the
sampling rate of a signal associated to an input clock into a signal
associated to a different output clock. The ASRC supports concurrent
sample rate conversion of up to 10 channels of about -120dB THD+N. The
sample rate conversion of each channel is associated to a pair of
incoming and outgoing sampling rates. The ASRC supports up to three
sampling rate pairs.
AUDMUX
Digital Audio Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example,
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice
codecs). The AUDMUX has seven ports with identical functionality and
programming models. A desired connectivity is achieved by configuring
two or more AUDMUX ports.
BCH40
Binary-BCH ECC
Processor
System
Control
Peripherals
The BCH40 module provides up to 40-bit ECC error correction for NAND
Flash controller (GPMI).
CAAM
Cryptographic
Accelerator and
Assurance Module
Security
CAAM is a cryptographic accelerator and assurance module. CAAM
implements several encryption and hashing functions, a run-time integrity
checker, and a Pseudo Random Number Generator (PRNG). The pseudo
random number generator is certified by Cryptographic Algorithm
Validation Program (CAVP) of National Institute of Standards and
Technology (NIST). Its DRBG validation number is 94 and its SHS
validation number is 1455.
CAAM also implements a Secure Memory mechanism. In i.MX
6Dual/6Quad processors, the security memory provided is 16 KB.
CCM
GPC
SRC
Clock Control
Module, General
Power Controller,
System Reset
Controller
Clocks,
These modules are responsible for clock and reset distribution in the
Resets, and system, and also for the system power management.
Power Control
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
CSI
MIPI CSI-2 Interface Multimedia
Peripherals
The CSI IP provides MIPI CSI-2 standard camera interface port. The
CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800
Mbps for 4 data lanes.
CSU
Central Security Unit Security
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX 6Dual/6Quad platform. The Security
Control Registers (SCR) of the CSU are set during boot time by the HAB
and are locked to prevent further writing.
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
Cross Trigger
Interfaces
CTM
Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.
The CTM module is internal to the Cortex-A9 Core Platform.
DAP
Debug Access Port
System
Control
Peripherals
DCIC-0
DCIC-1
Display Content
Integrity Checker
Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX
6Dual/6Quad processor has two such modules, one for each IPU.
DSI
MIPI DSI interface
Multimedia
Peripherals
The MIPI DSI IP provides DSI standard display port interface. The DSI
interface support 80 Mbps to 1 Gbps speed per data lane.
DTCP
MM
Provides encryption function according to Digital Transmission Content
Protection standard for traffic over MLB150.
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface. It is configurable to
support Master/Slave modes, four chip selects to support multiple
peripherals.
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media. The i.MX 6Dual/6Quad processors also consist of
hardware assist for IEEE 1588 standard. For details, see the ENET
chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).
DTCP
eCSPI1-5
ENET
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from
masters attached to CTIs. The CTI module is internal to the Cortex-A9
Core Platform.
The DAP provides real-time access for the debugger without halting the
core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains. The DAP
module is internal to the Cortex-A9 Core Platform.
Note: The theoretical maximum performance of 1 Gbps ENET is limited
to 470 Mbps (total for Tx and Rx) due to internal bus throughput
limitations. The actual measured performance in optimized environment
is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX
6Dual/6Quad errata document (IMX6DQCE).
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
EPIT-1
EPIT-2
ESAI
FlexCAN-1
FlexCAN-2
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
Block Name
Subsystem
Brief Description
Enhanced Periodic
Interrupt Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the
EPIT is enabled by software. It is capable of providing precise interrupts
at regular intervals with minimal processor intervention. It has a 12-bit
prescaler for division of input clock frequency to get the required time
setting for the interrupts to occur, and counter value can be programmed
on the fly.
Enhanced Serial
Audio Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial
port for serial communication with a variety of serial devices, including
industry-standard codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each
section with its own clock generator. All serial transfers are synchronized
to a clock. Additional synchronization signals are used to delineate the
word frames. The normal mode of operation is used to transfer data at a
periodic rate, one word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words (time slots) per
period. This mode can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high speed when the data
becomes available.
The ESAI has 12 pins for data and clocking connection to external
devices.
Flexible Controller
Area Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed to be used as a
vehicle serial data bus, meeting the specific requirements of this field:
real-time processing, reliable operation in the Electromagnetic
interference (EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full implementation of the
CAN protocol specification, Version 2.0 B, which supports both standard
and extended message frames.
General Purpose I/O System
Modules
Control
Peripherals
Used for general purpose input/output to external devices. Each GPIO
module supports 32 bits of I/O.
GPMI
General Purpose
Media Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices. 40-bit ECC error
correction for NAND Flash controller (GPMI2). The GPMI supports
separate DMA channels per NAND device.
GPT
General Purpose
Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with
programmable prescaler and compare and capture register. A timer
counter value can be captured using an external event and can be
configured to trigger a capture event on either the leading or trailing edges
of an input pulse. When the timer is configured to operate in “set and
forget” mode, it is capable of providing precise interrupts at regular
intervals with minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at comparison. This
timer can be configured to run either on an external clock or on an internal
clock.
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
NXP Semiconductors
13
Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
GPU2Dv2
Graphics Processing Multimedia
Unit-2D, ver. 2
Peripherals
The GPU2Dv2 provides hardware acceleration for 2D graphics
algorithms, such as Bit BLT, stretch BLT, and many other 2D functions.
GPU3Dv4
Graphics Processing Multimedia
Unit-3D, ver. 4
Peripherals
The GPU2Dv4 provides hardware acceleration for 3D graphics algorithms
with sufficient processor power to run desktop quality interactive graphics
applications on displays up to HD1080 resolution. The GPU3D provides
OpenGL ES 2.0, including extensions, OpenGL ES 1.1, and OpenVG 1.1
GPUVGv2
Vector Graphics
Processing Unit,
ver. 2
Multimedia
Peripherals
OpenVG graphics accelerator provides OpenVG 1.1 support as well as
other accelerations, including Real-time hardware curve tesselation of
lines, quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and
various Vector Drawing functions.
HDMI Tx
HDMI Tx interface
Multimedia
Peripherals
The HDMI module provides HDMI standard interface port to an HDMI 1.4
compliant display.
HSI
MIPI HSI interface
Connectivity
Peripherals
The MIPI HSI provides a standard MIPI interface to the applications
processor.
I2C Interface
Connectivity
Peripherals
I2C provide serial interface for external devices. Data rates of up to 400
kbps are supported.
IOMUXC
IOMUX Control
System
Control
Peripherals
This module enables flexible IO multiplexing. Each IO pad has default and
several alternate functions. The alternate functions are software
configurable.
IPUv3H-1
IPUv3H-2
Image Processing
Unit, ver. 3H
Multimedia
Peripherals
IPUv3H enables connectivity to displays and video sources, relevant
processing and synchronization and control capabilities, allowing
autonomous operation.
The IPUv3H supports concurrent output to two display ports and
concurrent input from two camera ports, through the following interfaces:
• Parallel Interfaces for both display and camera
• Single/dual channel LVDS display interface
• HDMI transmitter
• MIPI/DSI transmitter
• MIPI/CSI-2 receiver
The processing includes:
• Image conversions: resizing, rotation, inversion, and color space
conversion
• A high-quality de-interlacing filter
• Video/graphics combining
• Image enhancement: color adjustment and gamut mapping, gamma
correction, and contrast enhancement
• Support for display backlight reduction
Key Pad Port
Connectivity
Peripherals
KPP Supports 8 x 8 external key pad matrix. KPP features are:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
I2C-1
I2C-2
I2C-3
KPP
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
LDB
Block Name
Subsystem
LVDS Display Bridge Connectivity
Peripherals
Brief Description
LVDS Display Bridge is used to connect the IPU (Image Processing Unit)
to External LVDS Display Interface. LDB supports two channels; each
channel has following signals:
• One clock pair
• Four data pairs
Each signal pair contains LVDS special differential pad (PadP, PadM).
MediaLB
Connectivity / The MLB interface module provides a link to a MOST® data network,
using the standardized MediaLB protocol (up to 150 Mbps).
Multimedia
The module is backward compatible to MLB-50.
Peripherals
Multi-Mode DDR
Controller
Connectivity
Peripherals
DDR Controller has the following features:
• Supports 16/32/64-bit DDR3 / DDR3L or LPDDR2
• Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2
configurations (including 2x32 interleaved mode)
• Supports up to 4 GByte DDR memory space
Security
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys, JTAG
secure mode, boot characteristics, and various control signals, requiring
permanent non-volatility.
On-Chip Memory
Controller
Data Path
The On-Chip Memory controller (OCRAM) module is designed as an
interface between system’s AXI bus and internal (on-chip) SRAM memory
module.
In i.MX 6Dual/6Quad processors, the OCRAM is used for controlling the
256 KB multimedia RAM through a 64-bit AXI bus.
OSC 32 kHz
Clocking
Generates 32.768 kHz clock from an external crystal.
PCIe
PCI Express 2.0
Connectivity
Peripherals
The PCIe IP provides PCI Express Gen 2.0 functionality.
PMU
Power-Management Data Path
Functions
Integrated power management unit. Used to provide power to various
SoC domains.
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized
to generate sound from stored sample audio images and it can also
generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate
sound.
RAM
16 KB
Secure/non-secure
RAM
Secured
Internal
Memory
Secure/non-secure Internal RAM, interfaced through the CAAM.
RAM
256 KB
Internal RAM
Internal
Memory
Internal RAM, which is accessed through OCRAM memory controllers.
MLB150
MMDC
OCOTP_CTRL OTP Controller
OCRAM
OSC 32 kHz
PWM-1
PWM-2
PWM-3
PWM-4
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NXP Semiconductors
15
Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
ROM
96 KB
ROMCP
Block Name
Boot ROM
Subsystem
Internal
Memory
Brief Description
Supports secure and regular Boot Modes. Includes read protection on 4K
region for content protection
ROM Controller with Data Path
Patch
ROM Controller with ROM Patch support
SATA
Serial ATA
The SATA controller and PHY is a complete mixed-signal IP solution
designed to implement SATA II, 3.0 Gbps HDD connectivity.
SDMA
Smart Direct Memory System
Access
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off-loading the various cores in dynamic data
routing. It has the following features:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA
channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between Arm and SDMA
• Very fast context-switching with 2-level priority based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment,
decrement, and no address changes on source and destination
address)
• DMA ports can handle unit-directional and bi-directional flows (copy
mode)
• Up to 8-word buffer for configurable burst transfers
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
System JTAG
Controller
The SJC provides JTAG interface, which complies with JTAG TAP
standards, to internal logic. The i.MX 6Dual/6Quad processors use JTAG
port for production, testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory
bring-up, for manufacturing tests and troubleshooting, as well as for
software debugging by authorized entities. The i.MX 6Dual/6Quad SJC
incorporates three security modes for protecting against unauthorized
accesses. Modes are selected through eFUSE configuration.
SJC
Connectivity
Peripherals
System
Control
Peripherals
SNVS
Secure Non-Volatile Security
Storage
Secure Non-Volatile Storage, including Secure Real Time Clock, Security
State Machine, Master Key Control, and Violation/Tamper Detection and
reporting.
SPDIF
Sony Philips Digital Multimedia
Interconnect Format Peripherals
A standard audio file transfer format, developed jointly by the Sony and
Phillips corporations. It supports Transmitter and Receiver functionality.
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
SSI-1
SSI-2
SSI-3
TEMPMON
Block Name
I2S/SSI/AC97
Interface
Subsystem
Connectivity
Peripherals
Brief Description
The SSI is a full-duplex synchronous interface, which is used on the
processor to provide connectivity with off-chip audio peripherals. The SSI
supports a wide variety of protocols (SSI normal, SSI network, I2S, and
AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware support for an
external DMA controller to minimize its impact on system performance.
The second pair of FIFOs provides hardware interleaving of a second
audio stream that reduces CPU overhead in use cases where two time
slots are being used simultaneously.
Temperature Monitor System
Control
Peripherals
The temperature monitor/sensor IP module for detecting high temperature
conditions. The temperature read out does not reflect case or ambient
temperature. It reflects the temperature in proximity of the sensor location
on the die. Temperature distribution may not be uniformly distributed;
therefore, the read out value may not be the reflection of the temperature
value for the entire die.
TZASC
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by Arm) provides security address region control
functions required for intended application. It is used on the path to the
DRAM controller.
UART-1
UART-2
UART-3
UART-4
UART-5
UART Interface
Connectivity
Peripherals
Each of the UARTv2 modules support the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd
or none)
• Programmable baud rates up to 5 MHz
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB 2.0 High Speed Connectivity
OTG and 3x HS
Peripherals
Hosts
USBOH3 contains:
• One high-speed OTG module with integrated HS USB PHY
• One high-speed Host module with integrated HS USB PHY
• Two identical high-speed Host modules connected to HSIC USB ports.
USBOH3A
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NXP Semiconductors
17
Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
uSDHC-1
uSDHC-2
uSDHC-2
uSDHC-4
VDOA
VPU
WDOG-1
Block Name
Subsystem
Brief Description
SD/MMC and SDXC Connectivity
Enhanced
Peripherals
Multi-Media Card /
Secure Digital Host
Controller
i.MX 6Dual/6Quad specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and are based on the
uSDHC IP. They are:
• Conforms to the SD Host Controller Standard Specification version 3.0
• Fully compliant with MMC command/response sets and Physical Layer
as defined in the Multimedia Card System Specification,
v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.
Hardware reset as specified for eMMC cards is supported at ports #3
and #4 only.
• Fully compliant with SD command/response sets and Physical Layer
as defined in the SD Memory Card Specifications, v3.0 including
high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.
• Fully compliant with SDIO command/response sets and
interrupt/read-wait mode as defined in the SDIO Card Specification,
Part E1, v1.10
• Fully compliant with SD Card Specification, Part A2, SD Host
Controller Standard Specification, v2.00
All four ports support:
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
UHS-I SDR104 mode (104 MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52
MHz in both SDR and DDR modes (104 MB/s max)
However, the SoC-level integration and I/O muxing logic restrict the
functionality to the following:
• Instances #1 and #2 are primarily intended to serve as external slots or
interfaces to on-board SDIO devices. These ports are equipped with
“Card Detection” and “Write Protection” pads and do not support
hardware reset.
• Instances #3 and #4 are primarily intended to serve interfaces to
embedded MMC memory or interfaces to on-board SDIO devices.
These ports do not have “Card detection” and “Write Protection” pads
and do support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There are two completely
independent I/O power domains for Ports #1 and #2 in four bit
configuration (SD interface). Port #3 is placed in his own independent
power domain and port #4 shares power domain with some other
interfaces.
VDOA
Multimedia
Peripherals
The Video Data Order Adapter (VDOA) is used to re-order video data from
the “tiled” order used by the VPU to the conventional raster-scan order
needed by the IPU.
Video Processing
Unit
Multimedia
Peripherals
A high-performing video processing unit (VPU), which covers many
SD-level and HD-level video decoders and SD-level encoders as a
multi-standard video codec engine as well as several important video
processing, such as rotation and mirroring.
See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete
list of VPU’s decoding/encoding capabilities.
Watchdog
Timer
Peripherals
The Watchdog Timer supports two comparison points during each
counting period. Each of the comparison points is configurable to evoke
an interrupt to the Arm core, and a second point evokes an external event
on the WDOG line.
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
WDOG-2
(TZ)
EIM
XTALOSC
3.1
Block Name
Watchdog
(TrustZone)
Subsystem
Timer
Peripherals
Brief Description
The TrustZone Watchdog (TZ WDOG) timer module protects against
TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such a situation is
undesirable as it can compromise the system’s security. Once the TZ
WDOG module is activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer times out. Upon
a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces
switching to the TZ mode. If it is still not served, the TZ WDOG asserts a
security violation signal to the CSU. The TZ WDOG module cannot be
programmed or deactivated by a normal mode Software.
NOR-Flash /PSRAM Connectivity
interface
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and
async operating modes), at slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow
frequency
• Multiple chip selects
Crystal Oscillator
interface
The XTALOSC module enables connectivity to external crystal oscillator
device. In a typical application use-case, it is used for 24 MHz oscillator.
—
Special Signal Considerations
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual (IMX6DQRM).
Special signal consideration information is contained in the Hardware Development Guide for i.MX
6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).
3.2
Recommended Connections for Unused Analog Interfaces
The recommended connections for unused analog interfaces can be found in the section, “Unused analog
interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of
Applications Processors (IMX6DQ6SDLHDG).
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19
Electrical Characteristics
4
Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad
processors.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick
reference to the individual tables and sections.
Table 3. i.MX 6Dual/6Quad Chip-Level Conditions
For these characteristics, …
4.1.1
Topic appears …
Absolute Maximum Ratings
on page 21
FCPBGA Package Thermal Resistance
on page 22
Operating Ranges
on page 23
External Clock Sources
on page 25
Maximum Measured Supply Currents
on page 27
Low Power Mode Supply Currents
on page 28
USB PHY Current Consumption
on page 30
SATA Typical Power Consumption
on page 30
PCIe 2.0 Maximum Power Consumption
on page 31
HDMI Maximum Power Consumption
on page 32
Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 4 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the Operating Ranges or Parameters tables is not implied.
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Electrical Characteristics
Table 4. Absolute Maximum Ratings
Parameter Description
Core supply input voltage (LDO enabled)
Core supply input voltage (LDO bypass)
Core supply output voltage (LDO enabled)
VDD_HIGH_IN supply voltage
DDR I/O supply voltage
GPIO I/O supply voltage
HDMI, PCIe, and SATA PHY high (VPH) supply voltage
HDMI, PCIe, and SATA PHY low (VP) supply voltage
LVDS, MLB, and MIPI I/O supply voltage (2.5V supply)
PCIe PHY supply voltage
RGMII I/O supply voltage
SNVS IN supply voltage
(Secure Non-Volatile Storage and Real Time Clock)
USB I/O supply voltage
USB VBUS supply voltage
Vin/Vout input/output voltage range (non-DDR pins)
Vin/Vout input/output voltage range (DDR pins)
ESD immunity (HBM)
ESD immunity (CDM)
Storage temperature range
Symbol
VDD_ARM_IN
VDD_ARM23_IN
VDD_SOC_IN
VDD_ARM_IN
VDD_ARM23_IN
VDD_SOC_IN
VDD_ARM_CAP
VDD_SOC_CAP
VDD_PU_CAP
NVCC_PLL_OUT
VDD_HIGH_IN
NVCC_DRAM
NVCC_CSI
NVCC_EIM
NVCC_ENET
NVCC_GPIO
NVCC_LCD
NVCC_NAND
NVCC_SD
NVCC_JTAG
HDMI_VPH
PCIE_VPH
SATA_VPH
HDMI_VP
PCIE_VP
SATA_VP
NVCC_LVDS_2P5
NVCC_MIPI
PCIE_VPTX
NVCC_RGMII
VDD_SNVS_IN
USB_H1_DN
USB_H1_DP
USB_OTG_DN
USB_OTG_DP
USB_OTG_CHD_B
USB_H1_VBUS
USB_OTG_VBUS
Vin/Vout
Vin/Vout
Vesd_HBM
Vesd_CDM
Tstorage
Min
Max
Unit
-0.3
1.6
V
-0.3
1.4
V
-0.3
1.4
V
-0.3
-0.4
3.7
1.975 (See note 1)
V
V
-0.5
3.7
V
-0.3
2.85
V
-0.3
1.4
V
-0.3
2.85
V
-0.3
-0.5
-0.3
1.4
2.725
3.4
V
V
V
-0.3
3.73
V
—
5.35
V
-0.5
-0.5
—
—
-40
OVDD+0.3 (See note 2)
V
V
V
V
°C
OVDD+0.4 (See notes1&2)
2000
500
150
1
The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the
allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.
2 OVDD is the I/O supply voltage.
i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018
NXP Semiconductors
21
Electrical Characteristics
4.1.2
Thermal Resistance
NOTE
Per JEDEC JESD51-2, the intent of thermal resistance measurements is
solely for a thermal performance comparison of one package to another in a
standardized environment. This methodology is not meant to and will not
predict the performance of a package in an application-specific
environment.
4.1.2.1
FCPBGA Package Thermal Resistance
Table 5 provides the FCPBGA package thermal resistance data for the non-lidded package type.
Table 5. FCPBGA Package Thermal Resistance Data (Non-Lidded)
Thermal Parameter
Junction to Ambient1
Junction to
Ambient1
Test Conditions
Symbol
Value
Unit
Single-layer board (1s); natural convection2
RθJA
31
°C/W
Four-layer board (2s2p); natural convection2
RθJA
22
°C/W
RθJMA
24
°C/W
RθJMA
18
°C/W
—
RθJB
12
°C/W
—
RθJCtop
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