Freescale Semiconductor Inc.
Data Sheet: Technical Data
Document Number: IMX6DQIEC
Rev. 4, 07/2015
MCIMX6QxCxxxxC
MCIMX6QxCxxxxD
MCIMX6DxCxxxxC
MCIMX6DxCxxxxD
i.MX 6Dual/6Quad
Applications Processors
for Industrial Products
Package Information
Case FCPBGA 21 x 21 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 2
1
Introduction
The i.MX 6Dual/6Quad processors feature the Freescale
advanced implementation of the quad
ARM® Cortex®-A9 core, which operates at speeds up to
1 GHz. They include 2D and 3D graphics processors, 3D
1080p video processing, and integrated power
management. Each processor provides a 64-bit
DDR3/LVDDR3/LPDDR2-1066 memory interface and
a number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth®, GPS, hard drive, displays,
and camera sensors.
1
2
3
4
The i.MX 6Dual/6Quad processors are specifically
useful for applications such as the following:
The i.MX 6Dual/6Quad processors offers numerous
advanced features, such as:
• Multilevel memory system—The multilevel
memory system of each processor is based on the
L1 instruction and data caches, L2 cache, and
internal and external memory. The processors
support many types of external memory devices,
including DDR3, low voltage DDR3, LPDDR2,
© 2012-2015 Freescale Semiconductor, Inc. All rights reserved.
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Updated Signal Naming Convention . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 17
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Power Supplies Requirements and Restrictions . . 31
4.3 Integrated LDO Voltage Regulator Parameters . . . 32
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 34
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 40
4.8 Output Buffer Impedance Parameters . . . . . . . . . . 45
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48
4.10 General-Purpose Media Interface (GPMI) Timing. 64
4.11 External Peripheral Interface Parameters . . . . . . . 73
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 135
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 135
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 136
Package Information and Contact Assignments . . . . . . 138
6.1 Updated Signal Naming Convention . . . . . . . . . . 138
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 138
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Introduction
•
•
•
•
•
•
•
1.1
NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed
NAND, including eMMC up to rev 4.4/4.41.
Smart speed technology—The processors have power management throughout the device that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, Neon® MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, 2 autonomous and independent image processing units (IPU), and a
programmable smart DMA (SDMA) controller.
Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: an OpenGL® ES 2.0 3D graphics accelerator with four shaders (up to 200 MTri/s
and OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.
Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces
(such as UART, I2C, and I2S serial audio, SATA-II, and PCIe-II).
Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad
security reference manual (IMX6DQ6SDLSRM).
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
Ordering Information
Table 1shows examples of orderable part numbers covered by this data sheet. This table does not include
all possible orderable part numbers. The latest part numbers are available on freescale.com/imx6series. If
your desired part number is not listed in the table, or you have questions about available parts, see
freescale.com/imx6series or contact your Freescale representative.
Table 1. Example Orderable Part Numbers
Part Number
Quad/Dual CPU
Options
Speed1
Grade
Temperature
Grade
MCIMX6Q7CVT08AC
i.MX 6Quad
With VPU, GPU
800 MHz
Industrial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
MCIMX6Q7CVT08AD
i.MX 6Quad
With VPU, GPU
800 MHz
Industrial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
Package
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Introduction
Table 1. Example Orderable Part Numbers (continued)
1
MCIMX6D7CVT08AC
i.MX 6Dual
With VPU, GPU
800 MHz
Industrial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
MCIMX6D7CVT08AD
i.MX 6Dual
With VPU, GPU
800 MHz
Industrial
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
Figure 1 describes the part number nomenclature to identify the characteristics of the specific part number
you have (for example, cores, frequency, temperature grade, fuse options, silicon revision). Figure 1
applies to the i.MX 6Dual/6Quad.
The two characteristics that identify which data sheet a specific part applies to are the part number series
field and the temperature grade (junction) field:
• The i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors data sheet
(IMX6DQAEC) covers parts listed with “A (Automotive temp)”
• The i.MX 6Dual/6Quad Applications Processors for Consumer Products data sheet (IMX6DQCEC)
covers parts listed with “D (Commercial temp)” or “E (Extended Commercial temp)”
• The i.MX 6Dual/6Quad Applications Processors for Industrial Products data sheet (IMX6DQIEC)
covers parts listed with “C (Industrial temp)”
Ensure that you have the right data sheet for your specific part by checking the temperature grade
(junction) field and matching it to the right data sheet. If you have questions, see freescale.com/imx6series
or contact your Freescale representative.
i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 4, 07/2015
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3
Introduction
MC
IMX6
Qualification level
MC
Prototype Samples
PC
Mass Production
MC
Special
SC
Part # series
X
@
+
VV
$$
%
A
X
i.MX 6Quad
Q
i.MX 6Dual
D
Part differentiator
@
Industrial – w/ VPU, GPU, no MLB
7
Automotive – w/ VPU, GPU
6
Consumer – w/ VPU, GPU
5
Automotive – w/ GPU, no VPU
4
Temperature Tj
+
Extended Commercial: -20 to + 105°C
E
Industrial: -40 to +105 °C
C
Automotive: -40 to + 125 °C
A
Silicon revision1
A
Rev 1.2
C
Rev 1.3
D
Fusing
%
Default Setting
A
HDCP Enabled
C
Frequency
$$
800 MHz2 (Industrial grade)
08
852 MHz (Automotive grade)
08
1 GHz3
10
1.2 GHz
12
Package type
RoHS
FCPBGA 21x21 0.8mm (lidded)
VT
FCPBGA 21x21 0.8mm (non lidded)
YM
1. See the freescale.com\imx6series Web page for latest information on the available silicon revision.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Figure 1. Part Number Nomenclature—i.MX 6Quad and i.MX 6Dual
1.2
Features
The i.MX 6Dual/6Quad processors are based on ARM Cortex-A9 MPCore platform, which has the
following features:
• ARM Cortex-A9 MPCore 4xCPU processor (with TrustZone®)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
The ARM Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 1 MB unified I/D L2 cache, shared by two/four cores
• Two Master AXI (64-bit) bus interfaces output of L2 cache
• Frequency of the core (including Neon and L1 cache) as per Table 6.
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Introduction
•
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
— Secure/non-secure RAM (16 KB)
• External memory interfaces:
— 16-bit, 32-bit, and 64-bit DDR3-1066, LVDDR3-1066, and 1/2 LPDDR2-1066 channels,
supporting DDR interleaving mode, for 2x32 LPDDR2-1066
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
— 16/32-bit PSRAM, Cellular RAM
Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Hard Disk Drives—SATA II, 3.0 Gbps
• Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.
— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual
HD1080 and WXGA at 60 Hz)
— LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example,
WUXGA at 60 Hz) each
— HDMI 1.4 port
— MIPI/DSI, two lanes at 1 Gbps
• Camera sensors:
— Parallel Camera port (up to 20 bit and up to 240 MHz peak)
— MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to
800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to
four data lanes. Each i.MX 6Dual/6Quad processor has four lanes.
• Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
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5
Introduction
•
•
•
USB:
— One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
– One HS host with integrated High Speed PHY
– Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) PHY
Expansion PCI Express port (PCIe) v2.0 one lane
— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint
operations. Uses x1 PHY configuration.
Miscellaneous IPs and interfaces:
— SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and
outputs with I2S mode
— ESAI is capable of supporting audio sample frequencies up to 260kHz in I2S mode with 7.1
multi channel outputs
— Five UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is
due to the SoC IOMUX limitation, since all UART IPs are identical.
— Five eCSPI (Enhanced CSPI)
— Three I2C, supporting 400 kbps
— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps
— Four Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
— Two Controller Area Network (FlexCAN), 1 Mbps each
— Two Watchdog timers (WDOG)
— Audio MUX (AUDMUX)
The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:
• Provide PMU, including LDO supplies, for on-chip resources
• Use Temperature Sensor for monitoring the die temperature
• Support DVFS techniques for low power modes
• Use Software State Retention and Power Gating for ARM and MPE
• Support various levels of system power modes
• Use flexible clock gating control scheme
1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus
throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the
ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).
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Introduction
The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:
• VPU—Video Processing Unit
• IPUv3H—Image Processing Unit version 3H (2 IPUs)
• GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4
• GPU2Dv2—2D Graphics Processing Unit (BitBlt)
• GPUVG—OpenVG 1.1 Graphics Processing Unit
• ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
• CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and
True and Pseudo Random Number Generator (NIST certified)
• SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
• CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
• A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
1.3
Updated Signal Naming Convention
The signal names of the i.MX 6 series of products have been standardized to better align the signal names
within the family and across the documentation. Some of the benefits of these changes are as follows:
• The names are unique within the scope of an SoC and within the series of products
• Searches will return all occurrences of the named signal
• The names are consistent between i.MX 6 series products implementing the same modules
• The module instance is incorporated into the signal name
This change applies only to signal names. The original ball names have been preserved to prevent the need
to change schematics, BSDL models, IBIS models, etc.
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to
map the signal names used in older documentation to the new standardized naming conventions.
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7
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system.
Digital
Audio
LPDDR2/DDR3
NOR Flash
532MHz(DDR1066) PSRAM
External
Memory
Interface
GPMI
MMDC
Battery Ctrl 4x Camera
Device
Parallel/MIPI
Internal
RAM
(272KB)
ARM Cortex A9
MPCore Platform
4x A9-Core
TPIU
CTIs
SJC
Shared Peripherals
PCIe Bus
SSI (3)
eCSPI (5)
5xFast-UART
ESAI
SPDIF Rx/Tx
ASRC
HDMI
HDMI 1.4
Display
MIPI
Display
DSI/MIPI
Clock and Reset
Debug
DAP
SPBA
LDB
Image Processing
Subsystem
2x IPUv3H
Boot
ROM
(96KB)
Smart DMA
(SDMA)
2xCAN
Interface
1 / 2 LCD
Displays
Application Processor
CSI2/MIPI
Domain (AP)
EIM
SATA II
3.0Gbps
1 / 2 LVDS
(WUXGA+)
AXI and AHB Switch Fabric
Raw / ONFI 2.2
Nand-Flash
Security
CAAM
(16KB Ram)
SNVS
(SRTC)
CSU
Timers/Control
GPT
SRC
XTALOSC
OSC32K
AP Peripherals
1MB L2 cache
SCU, Timer
uSDHC (3)
PTM’s CTI’s
uSDHC
MMC/SD
eMMC/eSD
MMC/SD
SDXC
AUDMUX
Video
Proc. Unit
(VPU + Cache)
I2C(3)
Modem IC
PWM (4)
OCOTP
3D Graphics
Proc. Unit
(GPU3D)
IOMUXC
2D Graphics
Proc. Unit
(GPU2D)
GPIO
OpenVG 1.1
Proc. Unit
(GPUVG)
WDOG (2)
Crystals
& Clock sources
L1 I/D Cache
Timer, Wdog
Fuse Box
GPS
PLL (8)
CCM
GPC
KPP
Keypad
CAN(2)
1-Gbps ENET
HSI/MIPI
Ethernet
10/100/1000
Mbps
EPIT (2)
Audio,
Power
Mngmnt.
Temp Monitor
OTG PHY1
Host PHY2
Bluetooth
WLAN
JTAG
(IEEE1149.6)
2xHSIC
PHY
USB OTG +
3 HS Ports
USB OTG
(dev/host)
Figure 2. i.MX 6Dual/6Quad Industrial Grade System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (4) indicates four separate PWM peripherals.
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Modules List
3
Modules List
The i.MX 6Dual/6Quad processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6Dual/6Quad Modules List
Block
Mnemonic
Block Name
Subsystem
Brief Description
512x8 Fuse
Box
Electrical Fuse Array Security
Electrical Fuse Array. Enables to setup Boot Modes, Security Levels,
Security Keys, and many other system parameters.
The i.MX 6Dual/6Quad processors consist of 512x8-bit fuse box
accessible through OCOTP_CTRL interface.
APBH-DMA
NAND Flash and
BCH ECC DMA
Controller
System
Control
Peripherals
DMA controller used for GPMI2 operation
ARM
ARM Platform
ARM
The ARM Cortex-A9 platform consists of 4x (four) Cortex-A9 cores
version r2p10 and associated sub-blocks, including Level 2 Cache
Controller, SCU (Snoop Control Unit), GIC (General Interrupt Controller),
private timers, Watchdog, and CoreSight debug modules.
ASRC
Asynchronous
Sample Rate
Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC) converts the
sampling rate of a signal associated to an input clock into a signal
associated to a different output clock. The ASRC supports concurrent
sample rate conversion of up to 10 channels of about -120dB THD+N. The
sample rate conversion of each channel is associated to a pair of
incoming and outgoing sampling rates. The ASRC supports up to three
sampling rate pairs.
AUDMUX
Digital Audio Mux
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example,
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice
codecs). The AUDMUX has seven ports with identical functionality and
programming models. A desired connectivity is achieved by configuring
two or more AUDMUX ports.
BCH40
Binary-BCH ECC
Processor
System
Control
Peripherals
The BCH40 module provides up to 40-bit ECC encryption/decryption for
NAND Flash controller (GPMI)
CAAM
Cryptographic
Accelerator and
Assurance Module
Security
CAAM is a cryptographic accelerator and assurance module. CAAM
implements several encryption and hashing functions, a run-time integrity
checker, and a Pseudo Random Number Generator (PRNG). The pseudo
random number generator is certified by Cryptographic Algorithm
Validation Program (CAVP) of National Institute of Standards and
Technology (NIST). Its DRBG validation number is 94 and its SHS
validation number is 1455.
CAAM also implements a Secure Memory mechanism. In i.MX
6Dual/6Quad processors, the security memory provided is 16 KB.
Clock Control
Module, General
Power Controller,
System Reset
Controller
Clocks,
These modules are responsible for clock and reset distribution in the
Resets, and system, and also for the system power management.
Power Control
CCM
GPC
SRC
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
CSI
MIPI CSI-2 Interface Multimedia
Peripherals
The CSI IP provides MIPI CSI-2 standard camera interface port. The
CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800
Mbps for 4 data lanes.
CSU
Central Security Unit Security
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX 6Dual/6Quad platform. The Security
Control Registers (SCR) of the CSU are set during boot time by the HAB
and are locked to prevent further writing.
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
Cross Trigger
Interfaces
CTM
Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.
The CTM module is internal to the Cortex-A9 Core Platform.
DAP
Debug Access Port
System
Control
Peripherals
DCIC-0
DCIC-1
Display Content
Integrity Checker
Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX
6Dual/6Quad processor has two such modules, one for each IPU.
DSI
MIPI DSI interface
Multimedia
Peripherals
The MIPI DSI IP provides DSI standard display port interface. The DSI
interface support 80 Mbps to 1 Gbps speed per data lane.
eCSPI1-5
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface. It is configurable to
support Master/Slave modes, four chip selects to support multiple
peripherals.
Ethernet Controller
Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media. The i.MX 6Dual/6Quad processors also consist of
hardware assist for IEEE 1588 standard. For details, see the ENET
chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).
ENET
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from
masters attached to CTIs. The CTI module is internal to the Cortex-A9
Core Platform.
The DAP provides real-time access for the debugger without halting the
core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains. The DAP
module is internal to the Cortex-A9 Core Platform.
Note: The theoretical maximum performance of 1 Gbps ENET is limited
to 470 Mbps (total for Tx and Rx) due to internal bus throughput
limitations. The actual measured performance in optimized environment
is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX
6Dual/6Quad errata document (IMX6DQCE).
EPIT-1
EPIT-2
Enhanced Periodic
Interrupt Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the
EPIT is enabled by software. It is capable of providing precise interrupts
at regular intervals with minimal processor intervention. It has a 12-bit
prescaler for division of input clock frequency to get the required time
setting for the interrupts to occur, and counter value can be programmed
on the fly.
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
ESAI
FlexCAN-1
FlexCAN-2
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
Block Name
Subsystem
Brief Description
Enhanced Serial
Audio Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial
port for serial communication with a variety of serial devices, including
industry-standard codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each
section with its own clock generator. All serial transfers are synchronized
to a clock. Additional synchronization signals are used to delineate the
word frames. The normal mode of operation is used to transfer data at a
periodic rate, one word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words (time slots) per
period. This mode can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high speed when the data
becomes available.
The ESAI has 12 pins for data and clocking connection to external
devices.
Flexible Controller
Area Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed to be used as a
vehicle serial data bus, meeting the specific requirements of this field:
real-time processing, reliable operation in the Electromagnetic
interference (EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full implementation of the
CAN protocol specification, Version 2.0 B, which supports both standard
and extended message frames.
General Purpose I/O System
Modules
Control
Peripherals
Used for general purpose input/output to external devices. Each GPIO
module supports 32 bits of I/O.
GPMI
General Purpose
Media Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices. 40-bit ECC
encryption/decryption for NAND Flash controller (GPMI2). The GPMI
supports separate DMA channels per NAND device.
GPT
General Purpose
Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with
programmable prescaler and compare and capture register. A timer
counter value can be captured using an external event and can be
configured to trigger a capture event on either the leading or trailing edges
of an input pulse. When the timer is configured to operate in “set and
forget” mode, it is capable of providing precise interrupts at regular
intervals with minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at comparison. This
timer can be configured to run either on an external clock or on an internal
clock.
GPU2Dv2
Graphics Processing Multimedia
Unit-2D, ver. 2
Peripherals
The GPU2Dv2 provides hardware acceleration for 2D graphics
algorithms, such as Bit BLT, stretch BLT, and many other 2D functions.
GPU2Dv4
Graphics Processing Multimedia
Unit, ver. 4
Peripherals
The GPU2Dv4 provides hardware acceleration for 3D graphics algorithms
with sufficient processor power to run desktop quality interactive graphics
applications on displays up to HD1080 resolution. The GPU3D provides
OpenGL ES 2.0, including extensions, OpenGL ES 1.1, and OpenVG 1.1
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
GPUVGv2
Block Name
Subsystem
Brief Description
Vector Graphics
Processing Unit,
ver. 2
Multimedia
Peripherals
OpenVG graphics accelerator provides OpenVG 1.1 support as well as
other accelerations, including Real-time hardware curve tesselation of
lines, quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and
various Vector Drawing functions.
HDMI Tx
HDMI Tx interface
Multimedia
Peripherals
The HDMI module provides HDMI standard interface port to an HDMI 1.4
compliant display.
HSI
MIPI HSI interface
Connectivity
Peripherals
The MIPI HSI provides a standard MIPI interface to the applications
processor.
I2C Interface
Connectivity
Peripherals
I2C provide serial interface for external devices. Data rates of up to 400
kbps are supported.
IOMUXC
IOMUX Control
System
Control
Peripherals
This module enables flexible IO multiplexing. Each IO pad has default and
several alternate functions. The alternate functions are software
configurable.
IPUv3H-1
IPUv3H-2
Image Processing
Unit, ver. 3H
Multimedia
Peripherals
IPUv3H enables connectivity to displays and video sources, relevant
processing and synchronization and control capabilities, allowing
autonomous operation.
The IPUv3H supports concurrent output to two display ports and
concurrent input from two camera ports, through the following interfaces:
• Parallel Interfaces for both display and camera
• Single/dual channel LVDS display interface
• HDMI transmitter
• MIPI/DSI transmitter
• MIPI/CSI-2 receiver
The processing includes:
• Image conversions: resizing, rotation, inversion, and color space
conversion
• A high-quality de-interlacing filter
• Video/graphics combining
• Image enhancement: color adjustment and gamut mapping, gamma
correction, and contrast enhancement
• Support for display backlight reduction
KPP
Key Pad Port
Connectivity
Peripherals
KPP Supports 8 x 8 external key pad matrix. KPP features are:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LDB
LVDS Display Bridge Connectivity
Peripherals
I2C-1
I2C-2
I2C-3
LVDS Display Bridge is used to connect the IPU (Image Processing Unit)
to External LVDS Display Interface. LDB supports two channels; each
channel has following signals:
• One clock pair
• Four data pairs
Each signal pair contains LVDS special differential pad (PadP, PadM).
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
MMDC
Block Name
Multi-Mode DDR
Controller
Subsystem
Brief Description
Connectivity
Peripherals
DDR Controller has the following features:
• Support 16/32/64-bit DDR3-1066 (LV) or LPDDR2-1066
• Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2
configurations (including 2x32 interleaved mode)
• Support up to 4 GByte DDR memory space
Security
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys, JTAG
secure mode, boot characteristics, and various control signals, requiring
permanent non-volatility.
On-Chip Memory
Controller
Data Path
The On-Chip Memory controller (OCRAM) module is designed as an
interface between system’s AXI bus and internal (on-chip) SRAM memory
module.
In i.MX 6Dual/6Quad processors, the OCRAM is used for controlling the
256 KB multimedia RAM through a 64-bit AXI bus.
OSC 32 kHz
Clocking
Generates 32.768 kHz clock from an external crystal.
PCIe
PCI Express 2.0
Connectivity
Peripherals
The PCIe IP provides PCI Express Gen 2.0 functionality.
PMU
Power-Management Data Path
Functions
Integrated power management unit. Used to provide power to various
SoC domains.
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized
to generate sound from stored sample audio images and it can also
generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate
sound.
RAM
16 KB
Secure/non-secure
RAM
Secured
Internal
Memory
Secure/non-secure Internal RAM, interfaced through the CAAM.
RAM
256 KB
Internal RAM
Internal
Memory
Internal RAM, which is accessed through OCRAM memory controllers.
Boot ROM
Internal
Memory
Supports secure and regular Boot Modes. Includes read protection on 4K
region for content protection
OCOTP_CTRL OTP Controller
OCRAM
OSC 32 kHz
PWM-1
PWM-2
PWM-3
PWM-4
ROM
96KB
ROMCP
SATA
ROM Controller with Data Path
Patch
ROM Controller with ROM Patch support
Serial ATA
The SATA controller and PHY is a complete mixed-signal IP solution
designed to implement SATA II, 3.0 Gbps HDD connectivity.
Connectivity
Peripherals
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
SDMA
Block Name
Subsystem
Brief Description
Smart Direct Memory System
Access
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off-loading the various cores in dynamic data
routing. It has the following features:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA
channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM and SDMA
• Very fast context-switching with 2-level priority based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment,
decrement, and no address changes on source and destination
address)
• DMA ports can handle unit-directional and bi-directional flows (copy
mode)
• Up to 8-word buffer for configurable burst transfers
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
System JTAG
Controller
System
Control
Peripherals
The SJC provides JTAG interface, which complies with JTAG TAP
standards, to internal logic. The i.MX 6Dual/6Quad processors use JTAG
port for production, testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory
bring-up, for manufacturing tests and troubleshooting, as well as for
software debugging by authorized entities. The i.MX 6Dual/6Quad SJC
incorporates three security modes for protecting against unauthorized
accesses. Modes are selected through eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real Time Clock, Security
State Machine, Master Key Control, and Violation/Tamper Detection and
reporting.
SPDIF
Sony Philips Digital Multimedia
Interconnect Format Peripherals
A standard audio file transfer format, developed jointly by the Sony and
Phillips corporations. It supports Transmitter and Receiver functionality.
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
The SSI is a full-duplex synchronous interface, which is used on the
processor to provide connectivity with off-chip audio peripherals. The SSI
supports a wide variety of protocols (SSI normal, SSI network, I2S, and
AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware support for an
external DMA controller to minimize its impact on system performance.
The second pair of FIFOs provides hardware interleaving of a second
audio stream that reduces CPU overhead in use cases where two time
slots are being used simultaneously.
SJC
Connectivity
Peripherals
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
TEMPMON
Block Name
Subsystem
Brief Description
Temperature Monitor System
Control
Peripherals
The temperature monitor/sensor IP module for detecting high temperature
conditions. The temperature read out does not reflect case or ambient
temperature. It reflects the temperature in proximity of the sensor location
on the die. Temperature distribution may not be uniformly distributed;
therefore, the read out value may not be the reflection of the temperature
value for the entire die.
TZASC
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by ARM) provides security address region control
functions required for intended application. It is used on the path to the
DRAM controller.
UART-1
UART-2
UART-3
UART-4
UART-5
UART Interface
Connectivity
Peripherals
Each of the UARTv2 modules support the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd
or none)
• Programmable baud rates up to 5 MHz
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB 2.0 High Speed Connectivity
OTG and 3x HS
Peripherals
Hosts
USBOH3 contains:
• One high-speed OTG module with integrated HS USB PHY
• One high-speed Host module with integrated HS USB PHY
• Two identical high-speed Host modules connected to HSIC USB ports.
USBOH3A
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
uSDHC-1
uSDHC-2
uSDHC-2
uSDHC-4
VDOA
VPU
WDOG-1
Block Name
Subsystem
Brief Description
SD/MMC and SDXC Connectivity
Enhanced
Peripherals
Multi-Media Card /
Secure Digital Host
Controller
i.MX 6Dual/6Quad specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and are based on the
uSDHC IP. They are:
• Conforms to the SD Host Controller Standard Specification version 3.0
• Fully compliant with MMC command/response sets and Physical Layer
as defined in the Multimedia Card System Specification,
v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.
Hardware reset as specified for eMMC cards is supported at ports #3
and #4 only.
• Fully compliant with SD command/response sets and Physical Layer
as defined in the SD Memory Card Specifications, v3.0 including
high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.
• Fully compliant with SDIO command/response sets and
interrupt/read-wait mode as defined in the SDIO Card Specification,
Part E1, v1.10
• Fully compliant with SD Card Specification, Part A2, SD Host
Controller Standard Specification, v2.00
All four ports support:
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
UHS-I SDR104 mode (104 MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52
MHz in both SDR and DDR modes (104 MB/s max)
However, the SoC-level integration and I/O muxing logic restrict the
functionality to the following:
• Instances #1 and #2 are primarily intended to serve as external slots or
interfaces to on-board SDIO devices. These ports are equipped with
“Card Detection” and “Write Protection” pads and do not support
hardware reset.
• Instances #3 and #4 are primarily intended to serve interfaces to
embedded MMC memory or interfaces to on-board SDIO devices.
These ports do not have “Card detection” and “Write Protection” pads
and do support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There are two completely
independent I/O power domains for Ports #1 and #2 in four bit
configuration (SD interface). Port #3 is placed in his own independent
power domain and port #4 shares power domain with some other
interfaces.
VDOA
Multimedia
Peripherals
The Video Data Order Adapter (VDOA) is used to re-order video data from
the “tiled” order used by the VPU to the conventional raster-scan order
needed by the IPU.
Video Processing
Unit
Multimedia
Peripherals
A high-performing video processing unit (VPU), which covers many
SD-level and HD-level video decoders and SD-level encoders as a
multi-standard video codec engine as well as several important video
processing, such as rotation and mirroring.
See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for complete
list of VPU’s decoding/encoding capabilities.
Watchdog
Timer
Peripherals
The Watchdog Timer supports two comparison points during each
counting period. Each of the comparison points is configurable to evoke
an interrupt to the ARM core, and a second point evokes an external event
on the WDOG line.
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Modules List
Table 2. i.MX 6Dual/6Quad Modules List (continued)
Block
Mnemonic
WDOG-2
(TZ)
EIM
XTALOSC
3.1
Block Name
Watchdog
(TrustZone)
Subsystem
Timer
Peripherals
Brief Description
The TrustZone Watchdog (TZ WDOG) timer module protects against
TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such a situation is
undesirable as it can compromise the system’s security. Once the TZ
WDOG module is activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer times out. Upon
a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces
switching to the TZ mode. If it is still not served, the TZ WDOG asserts a
security violation signal to the CSU. The TZ WDOG module cannot be
programmed or deactivated by a normal mode Software.
NOR-Flash /PSRAM Connectivity
interface
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support 16-bit (in muxed IO mode only) PSRAM memories (sync and
async operating modes), at slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow
frequency
• Multiple chip selects
Crystal Oscillator
interface
The XTALOSC module enables connectivity to external crystal oscillator
device. In a typical application use-case, it is used for 24 MHz oscillator.
—
Special Signal Considerations
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual
(IMX6DQRM). Special signal consideration information is contained in the Hardware Development
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
(IMX6DQ6SDLHDG).
3.2
Recommended Connections for Unused Analog Interfaces
The recommended connections for unused analog interfaces can be found in the section, “Unused analog
interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of
Applications Processors (IMX6DQ6SDLHDG).
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Electrical Characteristics
4
Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad
processors.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick
reference to the individual tables and sections.
Table 3. i.MX 6Dual/6Quad Chip-Level Conditions
For these characteristics, …
4.1.1
Topic appears …
Absolute Maximum Ratings
on page 18
FCPBGA Package Thermal Resistance
on page 19
Operating Ranges
on page 20
External Clock Sources
on page 22
Maximum Supply Currents
on page 24
Low Power Mode Supply Currents
on page 25
USB PHY Current Consumption
on page 27
SATA Typical Power Consumption
on page 27
PCIe 2.0 Maximum Power Consumption
on page 29
HDMI Maximum Power Consumption
on page 30
Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 4 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the Operating Ranges or Parameters tables is not implied.
Table 4. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
VDD_ARM_IN
VDD_ARM23_IN
VDD_SOC_IN
-0.3
1.5
V
VDD_ARM_CAP
VDD_ARM23_CAP
VDD_SOC_CAP
VDD_PU_CAP
-0.3
1.3
V
GPIO supply voltage
Supplies denoted as I/O supply
-0.5
3.6
V
DDR I/O supply voltage
Supplies denoted as I/O supply
-0.4
1.975
V
Core supply voltages
Internal supply voltages
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Electrical Characteristics
Table 4. Absolute Maximum Ratings (continued)
Parameter Description
LVDS I/O supply voltage
Symbol
Min
Max
Unit
Supplies denoted as I/O supply
-0.3
2.8
V
VDD_HIGH_IN
-0.3
3.6
V
USB_H1_VBUS/USB_OTG_VBUS
—
5.25
V
USB_DP/USB_DN
-0.3
3.63
V
Vin/Vout
-0.5
OVDD1+0.3
V
Vesd
—
—
2000
500
V
TSTORAGE
-40
150
oC
VDD_HIGH_IN supply voltage
USB VBUS
Input voltage on USB_OTG_DP, USB_OTG_DN,
USB_H1_DP, USB_H1_DN pins
Input/output voltage range
ESD damage immunity:
• Human Body Model (HBM)
• Charge Device Model (CDM)
Storage temperature range
1
OVDD is the I/O supply voltage.
4.1.2
4.1.2.1
Thermal Resistance
FCPBGA Package Thermal Resistance
Table 5 provides the FCPBGA package thermal resistance data.
Table 5. FCPBGA Package Thermal Resistance Data
Value
Thermal Parameter
Junction to Ambient1
Junction to
Ambient1
Test Conditions
Symbol
Junction to
Junction to Case (top)1,5
1
2
3
4
5
Lid
Single-layer board (1s); natural convection2
RθJA
31
24
°C/W
Four-layer board (2s2p); natural convection2
RθJA
22
15
°C/W
RθJMA
24
17
°C/W
RθJMA
18
12
°C/W
—
RθJB
12
5
°C/W
—
RθJCtop
165 MHz
avddtmds
– 200 mV
—
avddtmds
+ 10 mV
mV
Single-ended output low voltage
For definition, see the second
figure above.
If attached sink supports TMDSCLK <
or = 165 MHz
avddtmds
– 600 mV
—
avddtmds
– 400mV
mV
If attached sink supports TMDSCLK >
165 MHz
avddtmds
– 700 mV
—
avddtmds
– 400 mV
mV
—
50
—
200
Ω
Differential source termination load
(inside HDMI 3D Tx PHY)
Although the HDMI 3D Tx PHY
includes differential source
termination, the user-defined value
is set for each single line (for
illustration, see the third figure
above).
Note: RTERM can also be
configured to be open and not
present on TMDS channels.
avddtmds ± 10 mV
mV
mV
Hot plug detect specifications
HPDVH
Hot plug detect high range
—
2.0
—
5.3
V
VHPD
VL
Hot plug detect low range
—
0
—
0.8
V
Z
Hot plug detect input impedance
—
10
—
—
kΩ
Hot plug detect time delay
—
—
—
100
µs
HPD
HPD
t
4.11.8
Switching Characteristics
Table 60 describes switching characteristics for the HDMI 3D Tx PHY. Figure 57 to Figure 61 illustrate
various parameters specified in table.
NOTE
All dynamic parameters related to the TMDS line drivers’ performance
imply the use of assembly guidelines.
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Electrical Characteristics
PTMDSCLK
50%
tCPL
tCPH
Figure 57. TMDS Clock Signal Definitions
Figure 58. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1
Figure 59. Intra-Pair Skew Definition
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Electrical Characteristics
Figure 60. Inter-Pair Skew Definition
Figure 61. TMDS Output Signals Rise and Fall Time Definition
Table 60. Switching Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
—
3.4
Gbps
25
—
340
MHz
2.94
—
40
ns
40
50
60
%
TMDS Drivers Specifications
—
F
TMDSCLK
P
TMDSCLK
t
CDC
t
—
TMDSCLK frequency
On TMDSCLKP/N outputs
TMDSCLK period
RL = 50 Ω
See Figure 57.
TMDSCLK duty cycle
t
CDC
=t
CPH
/P
TMDSCLK
RL = 50 Ω
See Figure 57.
TMDSCLK high time
RL = 50 Ω
See Figure 57.
4
5
6
UI
CPL
TMDSCLK low time
RL = 50 Ω
See Figure 57.
4
5
6
UI
—
TMDSCLK jitter1
RL = 50 Ω
—
—
0.25
UI
SK(p)
Intra-pair (pulse) skew
RL = 50 Ω
See Figure 59.
—
—
0.15
UI
SK(pp)
Inter-pair skew
RL = 50 Ω
See Figure 60.
—
—
1
UI
Differential output signal rise
time
20–80%
RL = 50 Ω
See Figure 61.
75
—
0.4 UI
ps
CPH
t
t
t
Maximum serial data rate
tR
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Electrical Characteristics
Table 60. Switching Characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
75
—
0.4 UI
ps
tF
Differential output signal fall time 20–80%
RL = 50 Ω
See Figure 61.
—
Differential signal overshoot
Referred to 2x VSWING
—
—
15
%
—
Differential signal undershoot
Referred to 2x VSWING
—
—
25
%
—
—
3.35
ms
Data and Control Interface Specifications
tPower-up2
1
2
HDMI 3D Tx PHY power-up time From power-down to
HSI_TX_READY assertion
Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3.
For information about latencies and associated timings, see Section 4.11.7.1, “Latencies and Timing Information.”
4.11.9
I2C Module Timing Parameters
This section describes the timing parameters of the I2C module. Figure 62 depicts the timing of I2C
module, and Table 61 lists the I2C module timing characteristics.
I2Cx_SDA
IC11
IC10
IC2
IC7
IC4
IC8
IC9
IC3
I2Cx_SCL
START
IC10
IC11
IC6
STOP
START
START
IC5
IC1
Figure 62. I2C Bus Timing
Table 61. I2C Module Timing Parameters
Standard Mode
ID
Fast Mode
Parameter
Unit
Min
Max
Min
Max
IC1
I2Cx_SCL cycle time
10
—
2.5
—
µs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
µs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
µs
IC4
Data hold time
01
3.452
01
0.92
µs
IC5
HIGH Period of I2Cx_SCL Clock
4.0
—
0.6
—
µs
IC6
LOW Period of the I2Cx_SCL Clock
4.7
—
1.3
—
µs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
µs
—
1003
—
ns
IC8
Data set-up time
250
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Table 61. I2C Module Timing Parameters (continued)
Standard Mode
ID
IC9
Fast Mode
Parameter
Bus free time between a STOP and START condition
Unit
Min
Max
Min
4.7
—
1.3
Max
—
µs
4
300
ns
IC10
Rise time of both I2Cx_SDA and I2Cx_SCL signals
—
1000
20 + 0.1Cb
IC11
Fall time of both I2Cx_SDA and I2Cx_SCL signals
—
300
20 + 0.1Cb4
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
1
A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling
edge of I2Cx_SCL.
2
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.
3
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.
If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2Cx_SCL line is released.
4 C = total capacitance of one bus line in pF.
b
4.11.10 Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
• Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.
• Related image processing and manipulation: sensor image signal processing, display processing,
image conversions, and other related functions.
• Synchronization and control capabilities, such as avoidance of tearing artifacts.
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Electrical Characteristics
4.11.10.1 IPU Sensor Interface Signal Mapping
The IPU supports a number of sensor input formats. Table 62 defines the mapping of the Sensor Interface
Pins used for various supported interface formats.
Table 62. Camera Input Signal Cross Reference, Format, and Bits Per Cycle
RGB565
8 bits
2 cycles
RGB5652
8 bits
3 cycles
RGB6663
8 bits
3 cycles
RGB888
8 bits
3 cycles
YCbCr4
8 bits
2 cycles
RGB5655
16 bits
2 cycles
YCbCr6
16 bits
1 cycle
YCbCr7
16 bits
1 cycle
YCbCr8
20 bits
1 cycle
IPUx_CSIx_
DATA00
—
—
—
—
—
—
—
0
C[0]
IPUx_CSIx_
DATA01
—
—
—
—
—
—
—
0
C[1]
IPUx_CSIx_
DATA02
—
—
—
—
—
—
—
C[0]
C[2]
IPUx_CSIx_
DATA03
—
—
—
—
—
—
—
C[1]
C[3]
IPUx_CSIx_
DATA04
—
—
—
—
—
B[0]
C[0]
C[2]
C[4]
IPU2_CSIx_
DATA_05
—
—
—
—
—
B[1]
C[1]
C[3]
C[5]
IPUx_CSIx_
DATA06
—
—
—
—
—
B[2]
C[2]
C[4]
C[6]
IPUx_CSIx_
DATA07
—
—
—
—
—
B[3]
C[3]
C[5]
C[7]
IPUx_CSIx_
DATA08
—
—
—
—
—
B[4]
C[4]
C[6]
C[8]
IPUx_CSIx_
DATA09
—
—
—
—
—
G[0]
C[5]
C[7]
C[9]
IPUx_CSIx_
DATA10
—
—
—
—
—
G[1]
C[6]
0
Y[0]
IPUx_CSIx_
DATA11
—
—
—
—
—
G[2]
C[7]
0
Y[1]
IPUx_CSIx_
DATA12
B[0], G[3]
R[2],G[4],B[2]
R/G/B[4]
R/G/B[0]
Y/C[0]
G[3]
Y[0]
Y[0]
Y[2]
IPUx_CSIx_
DATA13
B[1], G[4]
R[3],G[5],B[3]
R/G/B[5]
R/G/B[1]
Y/C[1]
G[4]
Y[1]
Y[1]
Y[3]
IPUx_CSIx_
DATA14
B[2], G[5]
R[4],G[0],B[4]
R/G/B[0]
R/G/B[2]
Y/C[2]
G[5]
Y[2]
Y[2]
Y[4]
IPUx_CSIx_
DATA15
B[3], R[0]
R[0],G[1],B[0]
R/G/B[1]
R/G/B[3]
Y/C[3]
R[0]
Y[3]
Y[3]
Y[5]
IPUx_CSIx_
DATA16
B[4], R[1]
R[1],G[2],B[1]
R/G/B[2]
R/G/B[4]
Y/C[4]
R[1]
Y[4]
Y[4]
Y[6]
IPUx_CSIx_
DATA17
G[0], R[2]
R[2],G[3],B[2]
R/G/B[3]
R/G/B[5]
Y/C[5]
R[2]
Y[5]
Y[5]
Y[7]
IPUx_CSIx_
DATA18
G[1], R[3]
R[3],G[4],B[3]
R/G/B[4]
R/G/B[6]
Y/C[6]
R[3]
Y[6]
Y[6]
Y[8]
IPUx_CSIx_
DATA19
G[2], R[4]
R[4],G[5],B[4]
R/G/B[5]
R/G/B[7]
Y/C[7]
R[4]
Y[7]
Y[7]
Y[9]
Signal
Name1
1
IPU2_CSIx stands for IPU2_CSI1 or IPU2_CSI2.
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Electrical Characteristics
2
3
4
5
6
7
8
The MSB bits are duplicated on LSB bits implementing color extension.
The two MSB bits are duplicated on LSB bits implementing color extension.
YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).
RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly
processing, but only under some restrictions on the control protocol.
YCbCr, 16 bits—Supported as a “generic-data” input—with no on-the-fly processing.
YCbCr, 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).
YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).
4.11.10.2 Sensor Interface Timings
There are three camera timing modes supported by the IPU.
4.11.10.2.1 BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals. The
timing syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is IPU2_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the
data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital
blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding
from the data stream, thus recovering IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals for internal
use. On BT.656 one component per cycle is received over the IPU2_CSIx_DATA_EN bus. On BT.1120
two components per cycle are received over the IPU2_CSIx_DATA_EN bus.
4.11.10.2.2 Gated Clock Mode
The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this
mode. See Figure 63.
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